Merge branch 'master' of https://github.com/mbedmicro/mbed

.travis.yml

@@ -1,8 +1,9 @@
---- 
-python: 
+---
+python:
   - "2.7"
 script: "python workspace_tools/build_travis.py"
 install:
   - "sudo $TRAVIS_BUILD_DIR/travis/install_dependencies.sh > /dev/null"
   - sudo pip install colorama
-  - sudo pip install prettytable
+  - sudo pip install prettytable
+  - sudo pip install jinja2

CONTRIBUTING.md

@@ -10,6 +10,8 @@ You can for example read more in our ```docs``` section in [mbedmicro/mbed/doc](
 # How to contribute
 We really appreciate your contributions! We are Open Source project and we need your help. We want to keep it as easy as possible to contribute changes that get things working in your environment. There are a few guidelines that we need contributors to follow so that we can have a chance of keeping on top of things.
 
+Before a pull request will be merged, the [mbed Contributor Agreement](http://developer.mbed.org/contributor_agreement/) must be signed.
+
 You can pick up existing [mbed GitHub Issue](https://github.com/mbedmicro/mbed/issues) and solve it or implement new feature you find important, attractive or just necessary. We will review your proposal via pull request mechanism, give you comments and merge your changes if we decide your contribution satisfy criteria such as quality.
 
 # Enhancements vs Bugs

libraries/USBDevice/USBDevice/USBEndpoints.h

@@ -47,6 +47,8 @@ typedef enum {
 #include "USBEndpoints_STM32F4.h"
 #elif defined (TARGET_RZ_A1H)
 #include "USBEndpoints_RZ_A1H.h"
+#elif defined(TARGET_Maxim)
+#include "USBEndpoints_Maxim.h"
 #else
 #error "Unknown target type"
 #endif

libraries/USBDevice/USBDevice/USBEndpoints_Maxim.h

@@ -0,0 +1,90 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#define NUMBER_OF_LOGICAL_ENDPOINTS   (8)
+#define NUMBER_OF_PHYSICAL_ENDPOINTS  (NUMBER_OF_LOGICAL_ENDPOINTS * 2)
+
+#define DIR_OUT       0x00
+#define DIR_IN        0x01
+#define EP_NUM(ep)    (ep >> 1)
+#define IN_EP(ep)     (ep & DIR_IN)
+#define OUT_EP(ep)    (!(ep & DIR_IN))
+
+/* Define physical endpoint numbers */
+
+/*      Endpoint    No.   */
+/*      ----------------  */
+#define EP0OUT      ((0 << 1) | DIR_OUT)
+#define EP0IN       ((0 << 1) | DIR_IN)
+#define EP1OUT      ((1 << 1) | DIR_OUT)
+#define EP1IN       ((1 << 1) | DIR_IN)
+#define EP2OUT      ((2 << 1) | DIR_OUT)
+#define EP2IN       ((2 << 1) | DIR_IN)
+#define EP3OUT      ((3 << 1) | DIR_OUT)
+#define EP3IN       ((3 << 1) | DIR_IN)
+#define EP4OUT      ((4 << 1) | DIR_OUT)
+#define EP4IN       ((4 << 1) | DIR_IN)
+#define EP5OUT      ((5 << 1) | DIR_OUT)
+#define EP5IN       ((5 << 1) | DIR_IN)
+#define EP6OUT      ((6 << 1) | DIR_OUT)
+#define EP6IN       ((6 << 1) | DIR_IN)
+#define EP7OUT      ((7 << 1) | DIR_OUT)
+#define EP7IN       ((7 << 1) | DIR_IN)
+
+/* Maximum Packet sizes */
+
+#define MAX_PACKET_SIZE_EP0  (64)
+#define MAX_PACKET_SIZE_EP1  (64)
+#define MAX_PACKET_SIZE_EP2  (64)
+#define MAX_PACKET_SIZE_EP3  (64)
+#define MAX_PACKET_SIZE_EP4  (64)
+#define MAX_PACKET_SIZE_EP5  (64)
+#define MAX_PACKET_SIZE_EP6  (64)
+#define MAX_PACKET_SIZE_EP7  (64)
+
+/* Generic endpoints - intended to be portable accross devices */
+/* and be suitable for simple USB devices. */
+
+/* Bulk endpoints */
+#define EPBULK_OUT  (EP1OUT)
+#define EPBULK_IN   (EP2IN)
+#define EPBULK_OUT_callback   EP1_OUT_callback
+#define EPBULK_IN_callback    EP2_IN_callback
+/* Interrupt endpoints */
+#define EPINT_OUT   (EP3OUT)
+#define EPINT_IN    (EP4IN)
+#define EPINT_OUT_callback    EP3_OUT_callback
+#define EPINT_IN_callback     EP4_IN_callback
+
+#define MAX_PACKET_SIZE_EPBULK  (64)
+#define MAX_PACKET_SIZE_EPINT   (64)

libraries/USBDevice/USBDevice/USBHAL_Maxim.cpp

@@ -0,0 +1,473 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#if defined(TARGET_Maxim)
+
+#include "USBHAL.h"
+#include "usb_regs.h"
+#include "clkman_regs.h"
+
+#define CONNECT_INTS    (MXC_F_USB_DEV_INTEN_BRST | MXC_F_USB_DEV_INTEN_SETUP | MXC_F_USB_DEV_INTEN_EP_IN | MXC_F_USB_DEV_INTEN_EP_OUT | MXC_F_USB_DEV_INTEN_DMA_ERR)
+
+USBHAL *USBHAL::instance;
+
+typedef struct {
+    volatile uint32_t buf0_desc;
+    volatile uint32_t buf0_address;
+    volatile uint32_t buf1_desc;
+    volatile uint32_t buf1_address;
+} ep_buffer_t;
+
+typedef struct {
+    ep_buffer_t out_buffer;
+    ep_buffer_t in_buffer;
+} ep0_buffer_t;
+
+typedef struct {
+    ep0_buffer_t ep0;
+    ep_buffer_t ep[MXC_USB_NUM_EP - 1];
+} ep_buffer_descriptor_t;
+
+// Static storage for endpoint buffer descriptor table. Must be 512 byte alligned for DMA.
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma data_alignment = 512
+#else
+__attribute__ ((aligned (512))) 
+#endif
+ep_buffer_descriptor_t ep_buffer_descriptor;
+
+// static storage for temporary data buffers. Must be 32 byte alligned.
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma data_alignment = 4
+#else
+__attribute__ ((aligned (4))) 
+#endif
+static uint8_t aligned_buffer[NUMBER_OF_LOGICAL_ENDPOINTS][MXC_USB_MAX_PACKET];
+
+// contorl packet state
+static enum {
+    CTRL_NONE = 0,
+    CTRL_SETUP,
+    CTRL_OUT,
+    CTRL_IN,
+} control_state;
+
+USBHAL::USBHAL(void)
+{
+    NVIC_DisableIRQ(USB_IRQn);
+
+    // The PLL must be enabled for USB
+    MBED_ASSERT(MXC_CLKMAN->clk_config & MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE);
+
+    // Enable the USB clock
+    MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N;
+
+    // reset the device
+    MXC_USB->cn = 0;
+    MXC_USB->cn = 1;
+    MXC_USB->dev_inten = 0;
+    MXC_USB->dev_cn = 0;
+    MXC_USB->dev_cn = MXC_F_USB_DEV_CN_URST;
+    MXC_USB->dev_cn = 0;
+
+    // fill in callback arrays
+    epCallback[EP0OUT] = NULL;
+    epCallback[EP0IN]  = NULL;
+    epCallback[EP1OUT] = &USBHAL::EP1_OUT_callback;
+    epCallback[EP1IN ] = &USBHAL::EP1_IN_callback;
+    epCallback[EP2OUT] = &USBHAL::EP2_OUT_callback;
+    epCallback[EP2IN ] = &USBHAL::EP2_IN_callback;
+    epCallback[EP3OUT] = &USBHAL::EP3_OUT_callback;
+    epCallback[EP3IN ] = &USBHAL::EP3_IN_callback;
+    epCallback[EP4OUT] = &USBHAL::EP4_OUT_callback;
+    epCallback[EP4IN ] = &USBHAL::EP4_IN_callback;
+    epCallback[EP5OUT] = &USBHAL::EP5_OUT_callback;
+    epCallback[EP5IN ] = &USBHAL::EP5_IN_callback;
+    epCallback[EP6OUT] = &USBHAL::EP6_OUT_callback;
+    epCallback[EP6IN ] = &USBHAL::EP6_IN_callback;
+    epCallback[EP7OUT] = &USBHAL::EP7_OUT_callback;
+    epCallback[EP7IN ] = &USBHAL::EP7_IN_callback;
+
+    // clear driver state
+    control_state = CTRL_NONE;
+
+    // set the descriptor location
+    MXC_USB->ep_base = (uint32_t)&ep_buffer_descriptor;
+
+    // attach IRQ handler and enable interrupts
+    instance = this;
+    NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr);
+    NVIC_EnableIRQ(USB_IRQn);
+}
+
+USBHAL::~USBHAL(void)
+{
+    MXC_USB->dev_cn = MXC_F_USB_DEV_CN_URST;
+    MXC_USB->dev_cn = 0;
+    MXC_USB->cn = 0;
+}
+
+void USBHAL::connect(void)
+{
+    // enable interrupts
+    MXC_USB->dev_inten |= CONNECT_INTS;
+
+    // allow interrupts on ep0
+    MXC_USB->ep[0] |= MXC_F_USB_EP_INT_EN;
+
+    // pullup enable
+    MXC_USB->dev_cn |= (MXC_F_USB_DEV_CN_CONNECT | MXC_F_USB_DEV_CN_FIFO_MODE);
+}
+
+void USBHAL::disconnect(void)
+{
+    // disable interrupts
+    MXC_USB->dev_inten &= ~CONNECT_INTS;
+
+    // disable pullup
+    MXC_USB->dev_cn &= ~MXC_F_USB_DEV_CN_CONNECT;
+}
+
+void USBHAL::configureDevice(void)
+{
+    // do nothing
+}
+
+void USBHAL::unconfigureDevice(void)
+{
+    // reset endpoints
+    for (int i = 0; i < MXC_USB_NUM_EP; i++) {
+        // Disable endpoint and clear the data toggle
+        MXC_USB->ep[i] &= ~MXC_F_USB_EP_DIR;
+        MXC_USB->ep[i] |= MXC_F_USB_EP_DT;
+    }
+}
+
+void USBHAL::setAddress(uint8_t address)
+{
+    // do nothing
+}
+
+void USBHAL::remoteWakeup(void)
+{
+    // do nothing
+}
+
+static ep_buffer_t *get_desc(uint8_t endpoint)
+{
+    uint8_t epnum = EP_NUM(endpoint);
+    ep_buffer_t *desc;
+
+    if (epnum == 0) {
+        if (IN_EP(endpoint)) {
+            desc = &ep_buffer_descriptor.ep0.in_buffer;
+        } else {
+            desc = &ep_buffer_descriptor.ep0.out_buffer;
+        }
+    } else {
+        desc = &ep_buffer_descriptor.ep[epnum - 1];
+    }
+
+    return desc;
+}
+
+void USBHAL::EP0setup(uint8_t *buffer)
+{
+    memcpy(buffer, (void*)&MXC_USB->setup0, 8); // setup packet is fixed at 8 bytes
+}
+
+void USBHAL::EP0read(void)
+{
+    if (control_state == CTRL_IN) {
+        // This is the status stage. ACK.
+        MXC_USB->ep[0] |= MXC_F_USB_EP_ST_ACK;
+        control_state = CTRL_NONE;
+        return;
+    }
+
+    control_state = CTRL_OUT;
+
+    endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
+}
+
+void USBHAL::EP0readStage(void)
+{
+    // do nothing
+}
+
+uint32_t USBHAL::EP0getReadResult(uint8_t *buffer)
+{
+    uint32_t size;
+
+    if (MXC_USB->out_owner & 1) {
+        return 0;
+    }
+
+    // get the packet length and contents
+    ep_buffer_t *desc = get_desc(EP0OUT);
+    size = desc->buf0_desc;
+    memcpy(buffer, aligned_buffer[0], size);
+
+    return size;
+}
+
+void USBHAL::EP0write(uint8_t *buffer, uint32_t size)
+{
+    if ((size == 0) && (control_state != CTRL_IN)) {
+        // This is a status stage ACK. Handle in hardware.
+        MXC_USB->ep[0] |= MXC_F_USB_EP_ST_ACK;
+        control_state = CTRL_NONE;
+        return;
+    }
+
+    control_state = CTRL_IN;
+
+    endpointWrite(EP0IN, buffer, size);
+}
+
+void USBHAL::EP0stall(void)
+{
+    stallEndpoint(0);
+}
+
+EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize)
+{
+    uint8_t epnum = EP_NUM(endpoint);
+
+    if ((endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS) || IN_EP(endpoint)) {
+        return EP_INVALID;
+    }
+
+    if (maximumSize > MXC_USB_MAX_PACKET) {
+        return EP_INVALID;
+    }
+    
+    uint32_t mask = (1 << epnum);
+    if (MXC_USB->out_owner & mask) {
+        return EP_INVALID;
+    }
+
+    ep_buffer_t *desc = get_desc(endpoint);
+    desc->buf0_desc = maximumSize;
+    desc->buf0_address = (uint32_t)aligned_buffer[epnum];
+
+    MXC_USB->out_owner = mask;
+
+    return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *data, uint32_t *bytesRead)
+{
+    if ((endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS) || IN_EP(endpoint)) {
+        return EP_INVALID;
+    }
+
+    uint32_t mask = (1 << EP_NUM(endpoint));
+    if (MXC_USB->out_owner & mask) {
+        return EP_PENDING;
+    }
+
+    // get the packet length and contents
+    ep_buffer_t *desc = get_desc(endpoint);
+    *bytesRead = desc->buf0_desc;
+    memcpy(data, aligned_buffer[EP_NUM(endpoint)], *bytesRead);
+
+    return EP_COMPLETED;
+}
+
+EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
+{
+    uint8_t epnum = EP_NUM(endpoint);
+
+    if ((endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS) || OUT_EP(endpoint)) {
+        return EP_INVALID;
+    }
+
+    if (size > MXC_USB_MAX_PACKET) {
+        return EP_INVALID;
+    }
+
+    uint32_t mask = (1 << epnum);
+    if (MXC_USB->in_owner & mask) {
+        return EP_INVALID;
+    }
+
+    memcpy(aligned_buffer[epnum], data, size);
+
+    ep_buffer_t *desc = get_desc(endpoint);
+    desc->buf0_desc = size;
+    desc->buf0_address = (uint32_t)aligned_buffer[epnum];
+
+    // start the DMA
+    MXC_USB->in_owner = mask;
+
+    return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint)
+{
+    uint32_t mask = (1 << EP_NUM(endpoint));
+    if (MXC_USB->in_owner & mask) {
+        return EP_PENDING;
+    }
+
+    return EP_COMPLETED;
+}
+
+void USBHAL::stallEndpoint(uint8_t endpoint)
+{
+    uint8_t epnum = EP_NUM(endpoint);
+
+    if (epnum == 0) {
+        MXC_USB->ep[epnum] |= MXC_F_USB_EP_ST_STALL;
+    }
+
+    MXC_USB->ep[epnum] |= MXC_F_USB_EP_STALL;
+}
+
+void USBHAL::unstallEndpoint(uint8_t endpoint)
+{
+    MXC_USB->ep[EP_NUM(endpoint)] &= ~MXC_F_USB_EP_STALL;
+}
+
+bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t options)
+{
+    uint8_t epnum = EP_NUM(endpoint);
+    uint32_t ep_ctrl;
+
+    if (epnum >= NUMBER_OF_PHYSICAL_ENDPOINTS) {
+        return false;
+    }
+
+    if (IN_EP(endpoint)) {
+        ep_ctrl = (MXC_V_USB_EP_DIR_IN << MXC_F_USB_EP_DIR_POS);
+    } else {
+        ep_ctrl = (MXC_S_USB_EP_DIR_OUT << MXC_F_USB_EP_DIR_POS);
+    }
+
+    ep_ctrl |= (MXC_F_USB_EP_DT | MXC_F_USB_EP_INT_EN);
+
+    MXC_USB->ep[epnum] = ep_ctrl;
+
+    return true;
+}
+
+bool USBHAL::getEndpointStallState(unsigned char endpoint)
+{
+    return !!(MXC_USB->ep[endpoint] & MXC_F_USB_EP_STALL);
+}
+
+void USBHAL::_usbisr(void)
+{
+    instance->usbisr();
+}
+
+void USBHAL::usbisr(void)
+{
+    // get and clear irqs
+    uint32_t irq_flags = MXC_USB->dev_intfl;
+    MXC_USB->dev_intfl = irq_flags;
+
+    // process only enabled interrupts
+    irq_flags &= MXC_USB->dev_inten;
+
+    // suspend 
+    if (irq_flags & MXC_F_USB_DEV_INTFL_SUSP) {
+        suspendStateChanged(1);
+    }
+
+    // bus reset
+    if (irq_flags & MXC_F_USB_DEV_INTFL_BRST) {
+
+        // reset endpoints
+        for (int i = 0; i < MXC_USB_NUM_EP; i++) {
+            // Disable endpoint and clear the data toggle
+            MXC_USB->ep[i] &= ~MXC_F_USB_EP_DIR;
+            MXC_USB->ep[i] |= MXC_F_USB_EP_DT;
+        }
+
+        // clear driver state
+        control_state = CTRL_NONE;
+
+        busReset();
+
+        // no need to process events after reset
+        return;
+    }
+
+    // Setup packet
+    if (irq_flags & MXC_F_USB_DEV_INTFL_SETUP) {
+        control_state = CTRL_SETUP;
+        EP0setupCallback();
+    }
+
+    // IN packets
+    if (irq_flags & MXC_F_USB_DEV_INTFL_EP_IN) {
+        // get and clear IN irqs
+        uint32_t in_irqs = MXC_USB->in_int;
+        MXC_USB->in_int = in_irqs;
+
+        if (in_irqs & 1) {
+            EP0in();
+        }
+
+        for (uint8_t epnum = 1; epnum < NUMBER_OF_LOGICAL_ENDPOINTS; epnum++) {
+            uint32_t irq_mask = (1 << epnum);
+            if (in_irqs & irq_mask) {
+                uint8_t endpoint = (epnum << 1) | DIR_IN;
+                (instance->*(epCallback[endpoint]))();
+            }
+        }
+    }
+
+    // OUT packets
+    if (irq_flags & MXC_F_USB_DEV_INTFL_EP_OUT) {
+        // get and clear OUT irqs
+        uint32_t out_irqs = MXC_USB->out_int;
+        MXC_USB->out_int = out_irqs;
+
+        if (out_irqs & 1) {
+            EP0out();
+        }
+
+        for (uint8_t epnum = 1; epnum < NUMBER_OF_LOGICAL_ENDPOINTS; epnum++) {
+            uint32_t irq_mask = (1 << epnum);
+            if (out_irqs & irq_mask) {
+                uint8_t endpoint = (epnum << 1) | DIR_OUT;
+                (instance->*(epCallback[endpoint]))();
+            }
+        }
+    }
+}
+
+#endif

libraries/USBDevice/USBMIDI/MIDIMessage.h

@@ -21,6 +21,8 @@
 
 #include "mbed.h"
 
+#define MAX_MIDI_MESSAGE_SIZE 256 // Max message size. SysEx can be up to 65536 but 256 should be fine for most usage
+
 // MIDI Message Format
 //
 // [ msg(4) | channel(4) ] [ 0 | n(7) ] [ 0 | m(7) ]
@@ -42,13 +44,23 @@
 /** A MIDI message container */
 class MIDIMessage {
 public:
-    MIDIMessage() {}
+    MIDIMessage() : length(4) {}
 
-    MIDIMessage(uint8_t *buf) {
+    MIDIMessage(uint8_t *buf) : length(4) {
         for (int i = 0; i < 4; i++)
             data[i] = buf[i];
     }
 
+    // New constructor, buf is a true MIDI message (not USBMidi message) and buf_len true message length.
+    MIDIMessage(uint8_t *buf, int buf_len) {
+        length=buf_len+1;
+        // first byte keeped for retro-compatibility
+        data[0]=0;
+
+        for (int i = 0; i < buf_len; i++)
+            data[i+1] = buf[i];
+    }
+
     // create messages
 
     /** Create a NoteOff message
@@ -162,6 +174,16 @@ public:
         return ControlChange(123, 0, channel);
     }
 
+     /** Create a SysEx message
+     * @param data SysEx data (including 0xF0 .. 0xF7)
+     * @param len SysEx data length
+     * @returns A MIDIMessage
+     */
+    static MIDIMessage SysEx(uint8_t *data, int len) {
+        MIDIMessage msg=MIDIMessage(data,len);
+        return msg;
+    }
+
     // decode messages
 
     /** MIDI Message Types */
@@ -174,7 +196,8 @@ public:
         ProgramChangeType,
         ChannelAftertouchType,
         PitchWheelType,
-        AllNotesOffType
+        AllNotesOffType,
+        SysExType
     };
 
     /** Read the message type
@@ -196,6 +219,7 @@ public:
             case 0xC: return ProgramChangeType;
             case 0xD: return ChannelAftertouchType;
             case 0xE: return PitchWheelType;
+            case 0xF: return SysExType;
             default: return ErrorType;
         }
     }
@@ -245,7 +269,8 @@ public:
         return p - 8192; // 0 - 16383, 8192 is center
     }
 
-    uint8_t data[4];
+    uint8_t data[MAX_MIDI_MESSAGE_SIZE+1];
+    uint8_t length;
 };
 
 #endif

libraries/USBDevice/USBMIDI/USBMIDI.cpp

@@ -20,13 +20,56 @@
 #include "USBMIDI.h"
 
 
-USBMIDI::USBMIDI(uint16_t vendor_id, uint16_t product_id, uint16_t product_release): USBDevice(vendor_id, product_id, product_release) {
+USBMIDI::USBMIDI(uint16_t vendor_id, uint16_t product_id, uint16_t product_release)
+ : USBDevice(vendor_id, product_id, product_release), cur_data(0), data_end(true)
+{
     midi_evt = NULL;
     USBDevice::connect();
 }
 
+// write plain MIDIMessage that will be converted to USBMidi event packet
 void USBMIDI::write(MIDIMessage m) {
-    USBDevice::write(EPBULK_IN, m.data, 4, MAX_PACKET_SIZE_EPBULK);
+    // first byte keeped for retro-compatibility
+    for(int p=1; p < m.length; p+=3) {
+        uint8_t buf[4];
+        // Midi message to USBMidi event packet
+        buf[0]=m.data[1] >> 4;
+        // SysEx
+        if(buf[0] == 0xF) {
+            if((m.length - p) > 3) {
+                // SysEx start or continue
+                buf[0]=0x4;
+            } else {
+                switch(m.length - p) {
+                    case 1:
+                        // SysEx end with one byte
+                        buf[0]=0x5;
+                        break;
+                    case 2:
+                        // SysEx end with two bytes
+                        buf[0]=0x6;
+                        break;
+                    case 3:
+                        // SysEx end with three bytes
+                        buf[0]=0x7;
+                        break;
+                }
+            }
+        }
+        buf[1]=m.data[p];
+
+        if(p+1 < m.length)
+            buf[2]=m.data[p+1];
+        else
+            buf[2]=0;
+
+        if(p+2 < m.length)
+            buf[3]=m.data[p+2];
+        else
+            buf[3]=0;
+
+        USBDevice::write(EPBULK_IN, buf, 4, MAX_PACKET_SIZE_EPBULK);
+    }
 }
 
 
@@ -34,16 +77,61 @@ void USBMIDI::attach(void (*fptr)(MIDIMessage)) {
     midi_evt = fptr;
 }
 
-
 bool USBMIDI::EPBULK_OUT_callback() {
     uint8_t buf[64];
     uint32_t len;
     readEP(EPBULK_OUT, buf, &len, 64);
 
     if (midi_evt != NULL) {
-        for (uint32_t i=0; i<len; i+=4) {
-            midi_evt(MIDIMessage(buf+i));
-        }
+        for (uint32_t i=0; i<len; i+=4) {   
+            uint8_t data_read;
+            data_end=true;
+            switch(buf[i]) {
+            case 0x2:
+                // Two-bytes System Common Message - undefined in USBMidi 1.0
+                data_read=2;
+                break;
+            case 0x4:
+                // SysEx start or continue
+                data_end=false;
+                data_read=3;
+                break;
+            case 0x5:
+                 // Single-byte System Common Message or SysEx end with one byte
+                data_read=1;
+                break;
+            case 0x6:
+                // SysEx end with two bytes
+                data_read=2;
+                break;
+            case 0xC:
+                // Program change
+                data_read=2;
+                break;
+            case 0xD:
+                // Channel pressure
+                data_read=2;
+                break;      
+            case 0xF:
+                // Single byte
+                data_read=1;
+                break;    
+            default:
+                // Others three-bytes messages
+                data_read=3;
+                break;      
+            } 
+        
+            for(uint8_t j=1;j<data_read+1;j++) {
+                data[cur_data]=buf[i+j];
+                cur_data++;
+            }
+        
+            if(data_end) {
+                 midi_evt(MIDIMessage(data,cur_data));
+                 cur_data=0;            
+            }
+       }
     }
 
     // We reactivate the endpoint to receive next characters
@@ -51,8 +139,6 @@ bool USBMIDI::EPBULK_OUT_callback() {
     return true;
 }
 
-
-
 // Called in ISR context
 // Set configuration. Return false if the
 // configuration is not supported.

libraries/USBDevice/USBMIDI/USBMIDI.h

@@ -102,8 +102,11 @@ protected:
     virtual uint8_t * configurationDesc();
 
 private:
+    uint8_t data[MAX_MIDI_MESSAGE_SIZE+1];
+    uint8_t cur_data;
+    bool data_end;
+    
     void (*midi_evt)(MIDIMessage);
-
 };
 
 #endif

libraries/USBDevice/USBMSD/USBMSD.cpp

@@ -135,10 +135,10 @@ bool USBMSD::connect(bool blocking) {
 }
 
 void USBMSD::disconnect() {
+    USBDevice::disconnect();
     //De-allocate MSD page size:
     free(page);
     page = NULL;
-    USBDevice::disconnect();
 }
 
 void USBMSD::reset() {

libraries/USBDevice/USBSerial/CircBuffer.h

@@ -19,20 +19,10 @@
 #ifndef CIRCBUFFER_H
 #define CIRCBUFFER_H
 
-template <class T>
+template <class T, int Size>
 class CircBuffer {
 public:
-    CircBuffer(int length) {
-        write = 0;
-        read = 0;
-        size = length + 1;
-        buf = (T *)malloc(size * sizeof(T));
-    };
-
-    ~CircBuffer() {
-        free(buf);
-     }
-
+    CircBuffer():write(0), read(0){}
     bool isFull() {
         return ((write + 1) % size == read);
     };
@@ -66,8 +56,8 @@ public:
 private:
     volatile uint16_t write;
     volatile uint16_t read;
-    uint16_t size;
-    T * buf;
+    static const int size = Size+1;  //a modern optimizer should be able to remove this so it uses no ram.
+    T buf[Size];
 };
 
 #endif

libraries/USBDevice/USBSerial/USBSerial.h

@@ -56,7 +56,7 @@ public:
     * @param connect_blocking define if the connection must be blocked if USB not plugged in
     *
     */
-    USBSerial(uint16_t vendor_id = 0x1f00, uint16_t product_id = 0x2012, uint16_t product_release = 0x0001, bool connect_blocking = true): USBCDC(vendor_id, product_id, product_release, connect_blocking), buf(128){
+    USBSerial(uint16_t vendor_id = 0x1f00, uint16_t product_id = 0x2012, uint16_t product_release = 0x0001, bool connect_blocking = true): USBCDC(vendor_id, product_id, product_release, connect_blocking){
         settingsChangedCallback = 0;
     };
 
@@ -154,7 +154,7 @@ protected:
 
 private:
     FunctionPointer rx;
-    CircBuffer<uint8_t> buf;
+    CircBuffer<uint8_t,128> buf;
     void (*settingsChangedCallback)(int baud, int bits, int parity, int stop);
 };
 

libraries/mbed/api/mbed.h

@@ -16,7 +16,7 @@
 #ifndef MBED_H
 #define MBED_H
 
-#define MBED_LIBRARY_VERSION 96
+#define MBED_LIBRARY_VERSION 97
 
 #include "platform.h"
 

libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld

@@ -42,10 +42,11 @@ SECTIONS
 {
     .isr_vector :
     {
-        __vector_table = .;
-        KEEP(*(.vector_table))
+        . = 0;
+        __isr_vector = .;
+        KEEP(*(.isr_vector))
         *(.text.Reset_Handler)
-        *(.text.System_Init)
+        *(.text.SystemInit)
          . = ALIGN(4);
     } > VECTORS
 

libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s

@@ -192,6 +192,13 @@ __isr_vector:
     .globl    Reset_Handler
     .type    Reset_Handler, %function
 Reset_Handler:
+/*
+ *    Call SystemInit before loading the .data section to prevent the watchdog
+ *    from resetting the board.
+ */
+    ldr    r0, =SystemInit
+    blx    r0
+
 /*     Loop to copy data from read only memory to RAM. The ranges
  *      of copy from/to are specified by following symbols evaluated in
  *      linker script.
@@ -212,8 +219,6 @@ Reset_Handler:
 
 .Lflash_to_ram_loop_end:
 
-    ldr    r0, =SystemInit
-    blx    r0
     ldr    r0, =_start
     bx    r0
     .pool

libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c

@@ -100,6 +100,8 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
    -- SystemInit()
    ---------------------------------------------------------------------------- */
 void SystemInit (void) {
+  /* SystemInit MUST NOT use any variables from the .data section, as this section is not loaded yet! */
+
 #if (DISABLE_WDOG)
   /* Disable the WDOG module */
   /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/MAX32600.sct

@@ -0,0 +1,21 @@
+
+; MAX32600
+; 256KB FLASH (0x40000) @ 0x000000000
+; 2KB RAM (0x8000) @ 0x20000000
+
+
+; MAX32600: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
+
+LR_IROM1 0x00000000 0x40000  {    ; load region size_region
+    ER_IROM1 0x00000000 0x40000  {  ; load address = execution address 
+        *.o (RESET, +First)
+        *(InRoot$$Sections)
+        .ANY (+RO)
+    }
+
+    ; [RAM] Vector table dynamic copy: 79 vectors * 4 bytes = (0x140) - alignment
+    RW_IRAM1 (0x20000000+0x140) (0x8000-0x140)  {  ; RW data
+        .ANY (+RW +ZI)
+    }
+
+}

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/startup_MAX32600.s

@@ -0,0 +1,255 @@
+;*******************************************************************************
+; Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+;
+; Permission is hereby granted, free of charge, to any person obtaining a
+; copy of this software and associated documentation files (the "Software"),
+; to deal in the Software without restriction, including without limitation
+; the rights to use, copy, modify, merge, publish, distribute, sublicense,
+; and/or sell copies of the Software, and to permit persons to whom the
+; Software is furnished to do so, subject to the following conditions:
+;
+; The above copyright notice and this permission notice shall be included
+; in all copies or substantial portions of the Software.
+;
+; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+; OTHER DEALINGS IN THE SOFTWARE.
+;
+; Except as contained in this notice, the name of Maxim Integrated
+; Products, Inc. shall not be used except as stated in the Maxim Integrated
+; Products, Inc. Branding Policy.
+;
+; The mere transfer of this software does not imply any licenses
+; of trade secrets, proprietary technology, copyrights, patents,
+; trademarks, maskwork rights, or any other form of intellectual
+; property whatsoever. Maxim Integrated Products, Inc. retains all
+; ownership rights.
+;*******************************************************************************
+
+__initial_sp        EQU     0x20008000  ; Top of RAM
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     DefaultIRQ_Handler        ; MPU Fault Handler
+                DCD     DefaultIRQ_Handler        ; Bus Fault Handler
+                DCD     DefaultIRQ_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     DefaultIRQ_Handler        ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     DefaultIRQ_Handler        ; PendSV Handler
+                DCD     SysTick_IRQHandler        ; SysTick Handler
+
+                ; Maxim 32600 Externals interrupts
+                DCD     UART0_IRQHandler          ; 16: 1 UART0
+                DCD     UART1_IRQHandler          ; 17: 2 UART1
+                DCD     I2CM0_IRQHandler          ; 18: 3 I2C Master 0
+                DCD     I2CS_IRQHandler           ; 19: 4 I2C Slave
+                DCD     USB_IRQHandler            ; 20: 5 USB
+                DCD     PMU_IRQHandler            ; 21: 6 DMA
+                DCD     AFE_IRQHandler            ; 22: 7 AFE
+                DCD     MAA_IRQHandler            ; 23: 8 MAA
+                DCD     AES_IRQHandler            ; 24: 9 AES
+                DCD     SPI0_IRQHandler           ; 25:10 SPI0
+                DCD     SPI1_IRQHandler           ; 26:11 SPI1
+                DCD     SPI2_IRQHandler           ; 27:12 SPI2
+                DCD     TMR0_IRQHandler           ; 28:13 Timer32-0
+                DCD     TMR1_IRQHandler           ; 29:14 Timer32-1
+                DCD     TMR2_IRQHandler           ; 30:15 Timer32-1
+                DCD     TMR3_IRQHandler           ; 31:16 Timer32-2
+                DCD     RSVD0_IRQHandler          ; 32:17 RSVD
+                DCD     RSVD1_IRQHandler          ; 33:18 RSVD
+                DCD     DAC0_IRQHandler           ; 34:19 DAC0  (12-bit DAC)  
+                DCD     DAC1_IRQHandler           ; 35:20 DAC1  (12-bit DAC)  
+                DCD     DAC2_IRQHandler           ; 36:21 DAC2  (8-bit DAC)
+                DCD     DAC3_IRQHandler           ; 37:22 DAC3  (8-bit DAC)
+                DCD     ADC_IRQHandler            ; 38:23 ADC
+                DCD     FLC_IRQHandler            ; 39:24 Flash Controller
+                DCD     PWRMAN_IRQHandler         ; 40:25 PWRMAN
+                DCD     CLKMAN_IRQHandler         ; 41:26 CLKMAN
+                DCD     RTC0_IRQHandler           ; 42:27 RTC INT0
+                DCD     RTC1_IRQHandler           ; 43:28 RTC INT1
+                DCD     RTC2_IRQHandler           ; 44:29 RTC INT2
+                DCD     RTC3_IRQHandler           ; 45:30 RTC INT3
+                DCD     WDT0_IRQHandler           ; 46:31 WATCHDOG0
+                DCD     WDT0_P_IRQHandler         ; 47:32 WATCHDOG0 PRE-WINDOW
+                DCD     WDT1_IRQHandler           ; 48:33 WATCHDOG1
+                DCD     WDT1_P_IRQHandler         ; 49:34 WATCHDOG1 PRE-WINDOW
+                DCD     GPIO_P0_IRQHandler        ; 50:35 GPIO Port 0 
+                DCD     GPIO_P1_IRQHandler        ; 51:36 GPIO Port 1 
+                DCD     GPIO_P2_IRQHandler        ; 52:37 GPIO Port 2 
+                DCD     GPIO_P3_IRQHandler        ; 53:38 GPIO Port 3 
+                DCD     GPIO_P4_IRQHandler        ; 54:39 GPIO Port 4 
+                DCD     GPIO_P5_IRQHandler        ; 55:40 GPIO Port 5 
+                DCD     GPIO_P6_IRQHandler        ; 56:41 GPIO Port 6 
+                DCD     GPIO_P7_IRQHandler        ; 57:42 GPIO Port 7 
+                DCD     TMR16_0_IRQHandler        ; 58:43 Timer16-s0
+                DCD     TMR16_1_IRQHandler        ; 59:44 Timer16-s1
+                DCD     TMR16_2_IRQHandler        ; 60:45 Timer16-s2
+                DCD     TMR16_3_IRQHandler        ; 61:46 Timer16-s3
+                DCD     I2CM1_IRQHandler          ; 62:47 I2C Master 1
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+Reset_Handler   PROC
+                EXPORT Reset_Handler                    [WEAK]
+                IMPORT SystemInit
+                IMPORT __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler             PROC
+                        EXPORT NMI_Handler                      [WEAK]     
+                        B       NMI_Handler
+                        ENDP
+
+HardFault_Handler       PROC
+                        EXPORT HardFault_Handler                [WEAK]             
+                        B       HardFault_Handler
+                        ENDP
+
+DefaultIRQ_Handler      PROC
+                        EXPORT DefaultIRQ_Handler               [WEAK]             
+                        B       DefaultIRQ_Handler
+                        ENDP
+
+DebugMon_Handler        PROC
+                        EXPORT DebugMon_Handler                 [WEAK]             
+                        B       DebugMon_Handler
+                        ENDP
+
+SysTick_IRQHandler      PROC
+                        EXPORT SysTick_IRQHandler               [WEAK]             
+                        B       SysTick_IRQHandler
+                        ENDP
+
+Default_Handler PROC
+
+        EXPORT UART0_IRQHandler                         [WEAK]                              
+        EXPORT UART1_IRQHandler                         [WEAK]                              
+        EXPORT I2CM0_IRQHandler                         [WEAK]                              
+        EXPORT I2CS_IRQHandler                          [WEAK]                             
+        EXPORT USB_IRQHandler                           [WEAK]             
+        EXPORT PMU_IRQHandler                           [WEAK]             
+        EXPORT AFE_IRQHandler                           [WEAK]                            
+        EXPORT MAA_IRQHandler                           [WEAK]                            
+        EXPORT AES_IRQHandler                           [WEAK]                            
+        EXPORT SPI0_IRQHandler                          [WEAK]                             
+        EXPORT SPI1_IRQHandler                          [WEAK]                             
+        EXPORT SPI2_IRQHandler                          [WEAK]                             
+        EXPORT TMR0_IRQHandler                          [WEAK]                             
+        EXPORT TMR1_IRQHandler                          [WEAK]                             
+        EXPORT TMR2_IRQHandler                          [WEAK]                             
+        EXPORT TMR3_IRQHandler                          [WEAK]                             
+        EXPORT RSVD0_IRQHandler                         [WEAK]                              
+        EXPORT RSVD1_IRQHandler                         [WEAK]                              
+        EXPORT DAC0_IRQHandler                          [WEAK]                             
+        EXPORT DAC1_IRQHandler                          [WEAK]                             
+        EXPORT DAC2_IRQHandler                          [WEAK]                             
+        EXPORT DAC3_IRQHandler                          [WEAK]                             
+        EXPORT ADC_IRQHandler                           [WEAK]             
+        EXPORT FLC_IRQHandler                           [WEAK]             
+        EXPORT PWRMAN_IRQHandler                        [WEAK]                               
+        EXPORT CLKMAN_IRQHandler                        [WEAK]                               
+        EXPORT RTC0_IRQHandler                          [WEAK]                             
+        EXPORT RTC1_IRQHandler                          [WEAK]                             
+        EXPORT RTC2_IRQHandler                          [WEAK]                             
+        EXPORT RTC3_IRQHandler                          [WEAK]                             
+        EXPORT WDT0_IRQHandler                          [WEAK]                             
+        EXPORT WDT0_P_IRQHandler                        [WEAK]                               
+        EXPORT WDT1_IRQHandler                          [WEAK]                             
+        EXPORT WDT1_P_IRQHandler                        [WEAK]                               
+        EXPORT GPIO_P0_IRQHandler                       [WEAK]                                
+        EXPORT GPIO_P1_IRQHandler                       [WEAK]                                
+        EXPORT GPIO_P2_IRQHandler                       [WEAK]                                
+        EXPORT GPIO_P3_IRQHandler                       [WEAK]                                
+        EXPORT GPIO_P4_IRQHandler                       [WEAK]                                
+        EXPORT GPIO_P5_IRQHandler                       [WEAK]                                
+        EXPORT GPIO_P6_IRQHandler                       [WEAK]                                
+        EXPORT GPIO_P7_IRQHandler                       [WEAK]                                
+        EXPORT TMR16_0_IRQHandler                       [WEAK]                                
+        EXPORT TMR16_1_IRQHandler                       [WEAK]                                
+        EXPORT TMR16_2_IRQHandler                       [WEAK]                                
+        EXPORT TMR16_3_IRQHandler                       [WEAK]                                
+        EXPORT I2CM1_IRQHandler                         [WEAK]               
+
+UART0_IRQHandler
+UART1_IRQHandler               
+I2CM0_IRQHandler
+I2CS_IRQHandler
+USB_IRQHandler
+PMU_IRQHandler
+AFE_IRQHandler
+MAA_IRQHandler
+AES_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+TMR0_IRQHandler
+TMR1_IRQHandler
+TMR2_IRQHandler
+TMR3_IRQHandler
+RSVD0_IRQHandler
+RSVD1_IRQHandler
+DAC0_IRQHandler
+DAC1_IRQHandler
+DAC2_IRQHandler
+DAC3_IRQHandler
+ADC_IRQHandler
+FLC_IRQHandler
+PWRMAN_IRQHandler
+CLKMAN_IRQHandler
+RTC0_IRQHandler
+RTC1_IRQHandler
+RTC2_IRQHandler
+RTC3_IRQHandler
+WDT0_IRQHandler
+WDT0_P_IRQHandler
+WDT1_IRQHandler
+WDT1_P_IRQHandler
+GPIO_P0_IRQHandler
+GPIO_P1_IRQHandler
+GPIO_P2_IRQHandler
+GPIO_P3_IRQHandler
+GPIO_P4_IRQHandler
+GPIO_P5_IRQHandler
+GPIO_P6_IRQHandler
+GPIO_P7_IRQHandler
+TMR16_0_IRQHandler
+TMR16_1_IRQHandler
+TMR16_2_IRQHandler
+TMR16_3_IRQHandler
+I2CM1_IRQHandler
+
+        B .
+        ENDP
+        ALIGN
+        END

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/sys.cpp

@@ -0,0 +1,57 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/max32600.ld

@@ -0,0 +1,182 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+/******************************************************************************
+ *
+ * Linker configuration file, default ARM Cortex M3 produced by Maxim Integrated Inc.
+ *
+ *****************************************************************************/
+
+MEMORY
+{
+    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 /* start from 0x0, fullsize flash, 256k */
+    RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* full-size SRAM, 32k */
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss :
+    {
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+    } > RAM
+
+    .heap :
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy :
+    {
+        *(.stack)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/startup_max32600.S

@@ -0,0 +1,262 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+    .syntax unified
+    .arch armv7-m
+
+/* Memory Model
+   The HEAP starts at the end of the DATA section and grows upward.
+   
+   The STACK starts at the end of the RAM and grows downward.
+   
+   The HEAP and stack STACK are only checked at compile time:
+   (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+   
+   This is just a check for the bare minimum for the Heap+Stack area before
+   aborting compilation, it is not the run time limit:
+   Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+    .section .stack
+    .align 3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0x00001000
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    Stack_Size
+    .size __StackLimit, . - __StackLimit
+__StackTop:
+    .size __StackTop, . - __StackTop
+
+    .section .heap
+    .align 3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x00000C00
+#endif
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .space    Heap_Size
+    .size __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size __HeapLimit, . - __HeapLimit
+
+    .section .isr_vector
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long    __StackTop            /* Top of Stack */
+    .long    Reset_Handler         /* Reset Handler */
+    .long    NMI_Handler           /* NMI Handler */
+    .long    HardFault_Handler     /* Hard Fault Handler */
+    .long    MemManage_Handler     /* MPU Fault Handler */
+    .long    BusFault_Handler      /* Bus Fault Handler */
+    .long    UsageFault_Handler    /* Usage Fault Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    SVC_Handler           /* SVCall Handler */
+    .long    DebugMon_Handler      /* Debug Monitor Handler */
+    .long    0                     /* Reserved */
+    .long    PendSV_Handler        /* PendSV Handler */
+    .long    SysTick_Handler       /* SysTick Handler */
+
+    /* Externals interrupts */
+    .long UART0_IRQHandler          /* 16: 1 UART0 */
+    .long UART1_IRQHandler          /* 17: 2 UART1 */
+    .long I2CM0_IRQHandler          /* 18: 3 I2C Master 0 */
+    .long I2CS_IRQHandler           /* 19: 4 I2C Slave */
+    .long USB_IRQHandler            /* 20: 5 USB */
+    .long PMU_IRQHandler            /* 21: 6 DMA */
+    .long AFE_IRQHandler            /* 22: 7 AFE */
+    .long MAA_IRQHandler            /* 23: 8 MAA */
+    .long AES_IRQHandler            /* 24: 9 AES */
+    .long SPI0_IRQHandler           /* 25:10 SPI0 */
+    .long SPI1_IRQHandler           /* 26:11 SPI1 */
+    .long SPI2_IRQHandler           /* 27:12 SPI2 */
+    .long TMR0_IRQHandler           /* 28:13 Timer32-0 */
+    .long TMR1_IRQHandler           /* 29:14 Timer32-1 */
+    .long TMR2_IRQHandler           /* 30:15 Timer32-1 */
+    .long TMR3_IRQHandler           /* 31:16 Timer32-2 */
+    .long RSVD0_IRQHandler          /* 32:17 RSVD */
+    .long RSVD1_IRQHandler          /* 33:18 RSVD */
+    .long DAC0_IRQHandler           /* 34:19 DAC0  (12-bit DAC) */  
+    .long DAC1_IRQHandler           /* 35:20 DAC1  (12-bit DAC) */  
+    .long DAC2_IRQHandler           /* 36:21 DAC2  (8-bit DAC) */
+    .long DAC3_IRQHandler           /* 37:22 DAC3  (8-bit DAC) */
+    .long ADC_IRQHandler            /* 38:23 ADC */
+    .long FLC_IRQHandler            /* 39:24 Flash Controller */
+    .long PWRMAN_IRQHandler         /* 40:25 PWRMAN */
+    .long CLKMAN_IRQHandler         /* 41:26 CLKMAN */
+    .long RTC0_IRQHandler           /* 42:27 RTC INT0 */
+    .long RTC1_IRQHandler           /* 43:28 RTC INT1 */
+    .long RTC2_IRQHandler           /* 44:29 RTC INT2 */
+    .long RTC3_IRQHandler           /* 45:30 RTC INT3 */
+    .long WDT0_IRQHandler           /* 46:31 WATCHDOG0 */
+    .long WDT0_P_IRQHandler         /* 47:32 WATCHDOG0 PRE-WINDOW */
+    .long WDT1_IRQHandler           /* 48:33 WATCHDOG1 */
+    .long WDT1_P_IRQHandler         /* 49:34 WATCHDOG1 PRE-WINDOW */
+    .long GPIO_P0_IRQHandler        /* 50:35 GPIO Port 0  */
+    .long GPIO_P1_IRQHandler        /* 51:36 GPIO Port 1  */
+    .long GPIO_P2_IRQHandler        /* 52:37 GPIO Port 2  */
+    .long GPIO_P3_IRQHandler        /* 53:38 GPIO Port 3  */
+    .long GPIO_P4_IRQHandler        /* 54:39 GPIO Port 4  */
+    .long GPIO_P5_IRQHandler        /* 55:40 GPIO Port 5  */
+    .long GPIO_P6_IRQHandler        /* 56:41 GPIO Port 6  */
+    .long GPIO_P7_IRQHandler        /* 57:42 GPIO Port 7  */
+    .long TMR16_0_IRQHandler        /* 58:43 Timer16-s0 */
+    .long TMR16_1_IRQHandler        /* 59:44 Timer16-s1 */
+    .long TMR16_2_IRQHandler        /* 60:45 Timer16-s2 */
+    .long TMR16_3_IRQHandler        /* 61:46 Timer16-s3 */
+    .long I2CM1_IRQHandler          /* 62:47 I2C Master 1 */
+
+	
+    .text 	
+    .thumb
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+.Lflash_to_ram_loop:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt    .Lflash_to_ram_loop
+
+.Lflash_to_ram_loop_end:
+
+    ldr    r0, =SystemInit
+    blx    r0
+    ldr    r0, =_start
+    bx     r0
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+    
+    .text
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_default_handler    handler_name
+    .align 1
+    .thumb_func
+    .weak    \handler_name
+    .type    \handler_name, %function
+\handler_name :
+    b    .
+    .size    \handler_name, . - \handler_name
+    .endm
+
+    def_default_handler    NMI_Handler
+    def_default_handler    HardFault_Handler
+    def_default_handler    MemManage_Handler
+    def_default_handler    BusFault_Handler
+    def_default_handler    UsageFault_Handler
+    def_default_handler    SVC_Handler
+    def_default_handler    DebugMon_Handler
+    def_default_handler    PendSV_Handler
+    def_default_handler    SysTick_Handler
+    def_default_handler    Default_Handler
+
+    .macro    def_irq_default_handler    handler_name
+    .weak     \handler_name
+    .set      \handler_name, Default_Handler
+    .endm
+ 
+    def_irq_default_handler UART0_IRQHandler          /* 16: 1 UART0 */
+    def_irq_default_handler UART1_IRQHandler          /* 17: 2 UART1 */
+    def_irq_default_handler I2CM0_IRQHandler          /* 18: 3 I2C Master 0 */
+    def_irq_default_handler I2CS_IRQHandler           /* 19: 4 I2C Slave */
+    def_irq_default_handler USB_IRQHandler            /* 20: 5 USB */
+    def_irq_default_handler PMU_IRQHandler            /* 21: 6 DMA */
+    def_irq_default_handler AFE_IRQHandler            /* 22: 7 AFE */
+    def_irq_default_handler MAA_IRQHandler            /* 23: 8 MAA */
+    def_irq_default_handler AES_IRQHandler            /* 24: 9 AES */
+    def_irq_default_handler SPI0_IRQHandler           /* 25:10 SPI0 */
+    def_irq_default_handler SPI1_IRQHandler           /* 26:11 SPI1 */
+    def_irq_default_handler SPI2_IRQHandler           /* 27:12 SPI2 */
+    def_irq_default_handler TMR0_IRQHandler           /* 28:13 Timer32-0 */
+    def_irq_default_handler TMR1_IRQHandler           /* 29:14 Timer32-1 */
+    def_irq_default_handler TMR2_IRQHandler           /* 30:15 Timer32-1 */
+    def_irq_default_handler TMR3_IRQHandler           /* 31:16 Timer32-2 */
+    def_irq_default_handler RSVD0_IRQHandler          /* 32:17 RSVD */
+    def_irq_default_handler RSVD1_IRQHandler          /* 33:18 RSVD */
+    def_irq_default_handler DAC0_IRQHandler           /* 34:19 DAC0  (12-bit DAC) */  
+    def_irq_default_handler DAC1_IRQHandler           /* 35:20 DAC1  (12-bit DAC) */  
+    def_irq_default_handler DAC2_IRQHandler           /* 36:21 DAC2  (8-bit DAC) */
+    def_irq_default_handler DAC3_IRQHandler           /* 37:22 DAC3  (8-bit DAC) */
+    def_irq_default_handler ADC_IRQHandler            /* 38:23 ADC */
+    def_irq_default_handler FLC_IRQHandler            /* 39:24 Flash Controller */
+    def_irq_default_handler PWRMAN_IRQHandler         /* 40:25 PWRMAN */
+    def_irq_default_handler CLKMAN_IRQHandler         /* 41:26 CLKMAN */
+    def_irq_default_handler RTC0_IRQHandler           /* 42:27 RTC INT0 */
+    def_irq_default_handler RTC1_IRQHandler           /* 43:28 RTC INT1 */
+    def_irq_default_handler RTC2_IRQHandler           /* 44:29 RTC INT2 */
+    def_irq_default_handler RTC3_IRQHandler           /* 45:30 RTC INT3 */
+    def_irq_default_handler WDT0_IRQHandler           /* 46:31 WATCHDOG0 */
+    def_irq_default_handler WDT0_P_IRQHandler         /* 47:32 WATCHDOG0 PRE-WINDOW */
+    def_irq_default_handler WDT1_IRQHandler           /* 48:33 WATCHDOG1 */
+    def_irq_default_handler WDT1_P_IRQHandler         /* 49:34 WATCHDOG1 PRE-WINDOW */
+    def_irq_default_handler GPIO_P0_IRQHandler        /* 50:35 GPIO Port 0  */
+    def_irq_default_handler GPIO_P1_IRQHandler        /* 51:36 GPIO Port 1  */
+    def_irq_default_handler GPIO_P2_IRQHandler        /* 52:37 GPIO Port 2  */
+    def_irq_default_handler GPIO_P3_IRQHandler        /* 53:38 GPIO Port 3  */
+    def_irq_default_handler GPIO_P4_IRQHandler        /* 54:39 GPIO Port 4  */
+    def_irq_default_handler GPIO_P5_IRQHandler        /* 55:40 GPIO Port 5  */
+    def_irq_default_handler GPIO_P6_IRQHandler        /* 56:41 GPIO Port 6  */
+    def_irq_default_handler GPIO_P7_IRQHandler        /* 57:42 GPIO Port 7  */
+    def_irq_default_handler TMR16_0_IRQHandler        /* 58:43 Timer16-s0 */
+    def_irq_default_handler TMR16_1_IRQHandler        /* 59:44 Timer16-s1 */
+    def_irq_default_handler TMR16_2_IRQHandler        /* 60:45 Timer16-s2 */
+    def_irq_default_handler TMR16_3_IRQHandler        /* 61:46 Timer16-s3 */
+    def_irq_default_handler I2CM1_IRQHandler          /* 62:47 I2C Master 1 */
+
+    .end

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/MAX32600.icf

@@ -0,0 +1,29 @@
+/* [ROM] */
+define symbol __intvec_start__        = 0x0;
+define symbol __region_ROM_start__    = 0x0;
+define symbol __region_ROM_end__      = 0x0003FFFF;
+
+/* [RAM] Vector table dynamic copy: 79 vectors * 4 bytes = 316 bytes (0x13C) */
+define symbol __NVIC_start__          = 0x00000000;
+define symbol __NVIC_end__            = 0x00000140; /* to be aligned on 8 bytes */
+define symbol __region_RAM_start__    = 0x20000000;
+define symbol __region_RAM_end__      = 0x20007FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __region_ROM_start__   to __region_ROM_end__];
+define region RAM_region      = mem:[from __region_RAM_start__   to __region_RAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x800;
+define symbol __size_heap__   = 0x800;
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/startup_MAX32600.s

@@ -0,0 +1,383 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+                MODULE  ?cstartup
+
+                ;; Forward declaration of sections.
+                SECTION CSTACK:DATA:NOROOT(3)
+
+                SECTION .intvec:CODE:NOROOT(2)
+
+                EXTERN  __iar_program_start
+                EXTERN  SystemInit
+                PUBLIC  __vector_table
+
+                DATA
+__vector_table  DCD     sfe(CSTACK)               /* Top of Stack */
+                DCD     Reset_Handler             /* Reset Handler */
+                DCD     NMI_Handler               /* NMI Handler */
+                DCD     HardFault_Handler         /* Hard Fault Handler */
+                DCD     DefaultIRQ_Handler        /* MPU Fault Handler */
+                DCD     DefaultIRQ_Handler        /* Bus Fault Handler */
+                DCD     DefaultIRQ_Handler        /* Usage Fault Handler */
+                DCD     0                         /* Reserved */
+                DCD     0                         /* Reserved */
+                DCD     0                         /* Reserved */
+                DCD     0                         /* Reserved */
+                DCD     DefaultIRQ_Handler        /* SVCall Handler */
+                DCD     DebugMon_Handler          /* Debug Monitor Handler */
+                DCD     0                         /* Reserved */
+                DCD     DefaultIRQ_Handler        /* PendSV Handler */
+                DCD     SysTick_IRQHandler        /* SysTick Handler */
+
+                /* Maxim 32600 Externals interrupts */
+                DCD     UART0_IRQHandler          /* 16: 1 UART0 */
+                DCD     UART1_IRQHandler          /* 17: 2 UART1 */
+                DCD     I2CM0_IRQHandler          /* 18: 3 I2C Master 0 */
+                DCD     I2CS_IRQHandler           /* 19: 4 I2C Slave */
+                DCD     USB_IRQHandler            /* 20: 5 USB */
+                DCD     PMU_IRQHandler            /* 21: 6 DMA */
+                DCD     AFE_IRQHandler            /* 22: 7 AFE */
+                DCD     MAA_IRQHandler            /* 23: 8 MAA */
+                DCD     AES_IRQHandler            /* 24: 9 AES */
+                DCD     SPI0_IRQHandler           /* 25:10 SPI0 */
+                DCD     SPI1_IRQHandler           /* 26:11 SPI1 */
+                DCD     SPI2_IRQHandler           /* 27:12 SPI2 */
+                DCD     TMR0_IRQHandler           /* 28:13 Timer32-0 */
+                DCD     TMR1_IRQHandler           /* 29:14 Timer32-1 */
+                DCD     TMR2_IRQHandler           /* 30:15 Timer32-1 */
+                DCD     TMR3_IRQHandler           /* 31:16 Timer32-2 */
+                DCD     RSVD0_IRQHandler          /* 32:17 RSVD */
+                DCD     RSVD1_IRQHandler          /* 33:18 RSVD */
+                DCD     DAC0_IRQHandler           /* 34:19 DAC0  (12-bit DAC) */  
+                DCD     DAC1_IRQHandler           /* 35:20 DAC1  (12-bit DAC) */  
+                DCD     DAC2_IRQHandler           /* 36:21 DAC2  (8-bit DAC) */
+                DCD     DAC3_IRQHandler           /* 37:22 DAC3  (8-bit DAC) */
+                DCD     ADC_IRQHandler            /* 38:23 ADC */
+                DCD     FLC_IRQHandler            /* 39:24 Flash Controller */
+                DCD     PWRMAN_IRQHandler         /* 40:25 PWRMAN */
+                DCD     CLKMAN_IRQHandler         /* 41:26 CLKMAN */
+                DCD     RTC0_IRQHandler           /* 42:27 RTC INT0 */
+                DCD     RTC1_IRQHandler           /* 43:28 RTC INT1 */
+                DCD     RTC2_IRQHandler           /* 44:29 RTC INT2 */
+                DCD     RTC3_IRQHandler           /* 45:30 RTC INT3 */
+                DCD     WDT0_IRQHandler           /* 46:31 WATCHDOG0 */
+                DCD     WDT0_P_IRQHandler         /* 47:32 WATCHDOG0 PRE-WINDOW */
+                DCD     WDT1_IRQHandler           /* 48:33 WATCHDOG1 */
+                DCD     WDT1_P_IRQHandler         /* 49:34 WATCHDOG1 PRE-WINDOW */
+                DCD     GPIO_P0_IRQHandler        /* 50:35 GPIO Port 0  */
+                DCD     GPIO_P1_IRQHandler        /* 51:36 GPIO Port 1  */
+                DCD     GPIO_P2_IRQHandler        /* 52:37 GPIO Port 2  */
+                DCD     GPIO_P3_IRQHandler        /* 53:38 GPIO Port 3  */
+                DCD     GPIO_P4_IRQHandler        /* 54:39 GPIO Port 4  */
+                DCD     GPIO_P5_IRQHandler        /* 55:40 GPIO Port 5  */
+                DCD     GPIO_P6_IRQHandler        /* 56:41 GPIO Port 6  */
+                DCD     GPIO_P7_IRQHandler        /* 57:42 GPIO Port 7  */
+                DCD     TMR16_0_IRQHandler        /* 58:43 Timer16-s0 */
+                DCD     TMR16_1_IRQHandler        /* 59:44 Timer16-s1 */
+                DCD     TMR16_2_IRQHandler        /* 60:45 Timer16-s2 */
+                DCD     TMR16_3_IRQHandler        /* 61:46 Timer16-s3 */
+                DCD     I2CM1_IRQHandler          /* 62:47 I2C Master 1 */
+
+                THUMB
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+                PUBWEAK Reset_Handler
+                SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__iar_program_start
+                BX      R0
+	
+                PUBWEAK NMI_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+                B       NMI_Handler
+
+                PUBWEAK HardFault_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+                B       HardFault_Handler
+
+                PUBWEAK DefaultIRQ_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+DefaultIRQ_Handler
+                B       DefaultIRQ_Handler
+                   
+                PUBWEAK DebugMon_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+                B       DebugMon_Handler
+
+                PUBWEAK SysTick_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_IRQHandler
+                B       SysTick_IRQHandler
+      
+                PUBWEAK UART0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+UART0_IRQHandler
+                B       UART0_IRQHandler
+    
+                PUBWEAK UART1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+UART1_IRQHandler
+                B       UART1_IRQHandler
+    
+                PUBWEAK I2CM0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+I2CM0_IRQHandler
+                B       I2CM0_IRQHandler
+    
+                PUBWEAK I2CS_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+I2CS_IRQHandler
+                B       I2CS_IRQHandler
+     
+                PUBWEAK USB_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+USB_IRQHandler
+                B       USB_IRQHandler
+      
+                PUBWEAK PMU_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+PMU_IRQHandler
+                B       PMU_IRQHandler
+      
+                PUBWEAK AFE_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+AFE_IRQHandler
+                B       AFE_IRQHandler
+      
+                PUBWEAK MAA_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+MAA_IRQHandler
+                B       MAA_IRQHandler
+      
+                PUBWEAK AES_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+AES_IRQHandler
+                B       AES_IRQHandler
+      
+                PUBWEAK SPI0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+SPI0_IRQHandler
+                B       SPI0_IRQHandler
+     
+                PUBWEAK SPI1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+                B       SPI1_IRQHandler
+     
+                PUBWEAK SPI2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler
+                B       SPI2_IRQHandler
+     
+                PUBWEAK TMR0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+TMR0_IRQHandler
+                B       TMR0_IRQHandler
+     
+                PUBWEAK TMR1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_IRQHandler
+                B       TMR1_IRQHandler
+     
+                PUBWEAK TMR2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+TMR2_IRQHandler
+                B       TMR2_IRQHandler
+     
+                PUBWEAK TMR3_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+TMR3_IRQHandler
+                B       TMR3_IRQHandler
+     
+                PUBWEAK RSVD0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+RSVD0_IRQHandler
+                B       RSVD0_IRQHandler
+    
+                PUBWEAK RSVD1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+RSVD1_IRQHandler
+                B       RSVD1_IRQHandler
+    
+                PUBWEAK DAC0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+DAC0_IRQHandler
+                B       DAC0_IRQHandler
+     
+                PUBWEAK DAC1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+DAC1_IRQHandler
+                B       DAC1_IRQHandler
+     
+                PUBWEAK DAC2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+DAC2_IRQHandler
+                B       DAC2_IRQHandler
+     
+                PUBWEAK DAC3_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+DAC3_IRQHandler
+                B       DAC3_IRQHandler
+     
+                PUBWEAK ADC_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+ADC_IRQHandler
+                B       ADC_IRQHandler
+      
+                PUBWEAK FLC_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+FLC_IRQHandler
+                B       FLC_IRQHandler
+    
+                PUBWEAK PWRMAN_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+PWRMAN_IRQHandler
+                B       PWRMAN_IRQHandler
+ 
+                PUBWEAK CLKMAN_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+CLKMAN_IRQHandler
+                B       CLKMAN_IRQHandler
+ 
+                PUBWEAK RTC0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+RTC0_IRQHandler
+                B       RTC0_IRQHandler
+   
+                PUBWEAK RTC1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+RTC1_IRQHandler
+                B       RTC1_IRQHandler
+   
+                PUBWEAK RTC2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+RTC2_IRQHandler
+                B       RTC2_IRQHandler
+   
+                PUBWEAK RTC3_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+RTC3_IRQHandler
+                B       RTC3_IRQHandler
+   
+                PUBWEAK WDT0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+WDT0_IRQHandler
+                B       WDT0_IRQHandler
+   
+                PUBWEAK WDT0_P_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+WDT0_P_IRQHandler
+                B       WDT0_P_IRQHandler
+ 
+                PUBWEAK WDT1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+WDT1_IRQHandler
+                B       WDT1_IRQHandler
+   
+                PUBWEAK WDT1_P_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+WDT1_P_IRQHandler
+                B       WDT1_P_IRQHandler
+ 
+                PUBWEAK GPIO_P0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P0_IRQHandler
+                B       GPIO_P0_IRQHandler
+
+                PUBWEAK GPIO_P1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P1_IRQHandler
+                B       GPIO_P1_IRQHandler
+
+                PUBWEAK GPIO_P2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P2_IRQHandler
+                B       GPIO_P2_IRQHandler
+
+                PUBWEAK GPIO_P3_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P3_IRQHandler
+                B       GPIO_P3_IRQHandler
+
+                PUBWEAK GPIO_P4_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P4_IRQHandler
+                B       GPIO_P4_IRQHandler
+
+                PUBWEAK GPIO_P5_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P5_IRQHandler
+                B       GPIO_P5_IRQHandler
+
+                PUBWEAK GPIO_P6_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P6_IRQHandler
+                B       GPIO_P6_IRQHandler
+
+                PUBWEAK GPIO_P7_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P7_IRQHandler
+                B       GPIO_P7_IRQHandler
+
+                PUBWEAK TMR16_0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+TMR16_0_IRQHandler
+                B       TMR16_0_IRQHandler
+
+                PUBWEAK TMR16_1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+TMR16_1_IRQHandler
+                B       TMR16_1_IRQHandler
+
+                PUBWEAK TMR16_2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+TMR16_2_IRQHandler
+                B       TMR16_2_IRQHandler
+
+                PUBWEAK TMR16_3_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+TMR16_3_IRQHandler
+                B       TMR16_3_IRQHandler
+
+                PUBWEAK I2CM1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+I2CM1_IRQHandler
+                B       I2CM1_IRQHandler  
+	
+                END

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/adc_regs.h

@@ -0,0 +1,466 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_ADC_REGS_H
+#define _MXC_ADC_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  adc_regs.h
+ * @addtogroup adc ADC
+ * @{
+ */
+
+/**
+ * @brief Defines ADC Modes.
+ */
+typedef enum {
+    /** Single Mode Full Rate */
+    MXC_E_ADC_MODE_SMPLCNT_FULL_RATE = 0,
+    /** Single Mode Low Power */
+    MXC_E_ADC_MODE_SMPLCNT_LOW_POWER = 1,
+    /** Continuous Mode Full Rate */
+    MXC_E_ADC_MODE_CONTINUOUS_FULL_RATE = 2,
+    /** Continuous Mode Low Power */
+    MXC_E_ADC_MODE_CONTINUOUS_LOW_POWER = 3,
+    /** Single Mode Full Rate with Scan Enabled */
+    MXC_E_ADC_MODE_SMPLCNT_SCAN_FULL_RATE = 8,
+    /** Single Mode Low Power with Scan Enabled */
+    MXC_E_ADC_MODE_SMPLCNT_SCAN_LOW_POWER = 9,
+    /** Continuous Mode Full Rate with Scan Enabled */
+    MXC_E_ADC_MODE_CONTINUOUS_SCAN_FULL_RATE = 10,
+    /** Continuous Mode Low Power with Scan Enabled */
+    MXC_E_ADC_MODE_CONTINUOUS_SCAN_LOW_POWER = 11
+} mxc_adc_mode_t;
+
+/**
+ * @brief Defines ADC Range Control.
+ */
+typedef enum {
+    /** Bi-polar Operation (-Vref/2 -> Vref/2) */
+    MXC_E_ADC_RANGE_HALF = 0,
+    /** Bi-polar Operation (-Vref -> Vref) */
+    MXC_E_ADC_RANGE_FULL
+} mxc_adc_range_t;
+
+/**
+ * @brief Defines ADC Bipolar operation.
+ */
+typedef enum {
+    /** Uni-polar operation (0 -> Vref) */
+    MXC_E_ADC_BI_POL_UNIPOLAR = 0,
+    /** Bi-polar operation see ADC Range Control */
+    MXC_E_ADC_BI_POL_BIPOLAR
+} mxc_adc_bi_pol_t;
+
+/**
+ * @brief Defines Decimation Filter Modes.
+ */
+typedef enum {
+    /** Decimation Filter ByPassed */
+    MXC_E_ADC_AVG_MODE_FILTER_BYPASS = 0,
+    /** Output Average Only*/
+    MXC_E_ADC_AVG_MODE_FILTER_OUTPUT,
+    /** Output Average and Raw Data (Test Mode Only) */
+    MXC_E_ADC_AVG_MODE_FILTER_OUTPUT_RAW
+} mxc_adc_avg_mode_t;
+
+/**
+ * @brief Defines ADC StartMode Modes.
+ */
+typedef enum {
+    /** StarMode via Software */
+    MXC_E_ADC_STRT_MODE_SOFTWARE = 0,
+    /** StarMode via PulseTrain */
+    MXC_E_ADC_STRT_MODE_PULSETRAIN
+} mxc_adc_strt_mode_t;
+
+/**
+ * @brief Defines Mux Channel Select for the Positive Input to the ADC.
+ */
+typedef enum {
+    /** Single Mode Input AIN0+; Diff Mode AIN0+/AIN8-  */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN0 = 0,
+    /** Single Mode Input AIN1+; Diff Mode AIN1+/AIN9-  */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN1 = 1,
+    /** Single Mode Input AIN2+; Diff Mode AIN2+/AIN10- */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN2 = 2,
+    /** Single Mode Input AIN3+; Diff Mode AIN3+/AIN11- */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN3 = 3,
+    /** Single Mode Input AIN4+; Diff Mode AIN4+/AIN12- */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN4 = 4,
+    /** Single Mode Input AIN5+; Diff Mode AIN5+/AIN13-  */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN5 = 5,
+    /** Single Mode Input AIN6+; Diff Mode AIN6+/AIN14-  */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN6 = 6,
+    /** Single Mode Input AIN7+; Diff Mode AIN7+/AIN15-  */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN7 = 7,
+    /** Single Mode Input AIN8+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN8 = 8,
+    /** Single Mode Input AIN9+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN9 = 9,
+    /** Single Mode Input AIN10+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN10 = 10,
+    /** Single Mode Input AIN11+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN11 = 11,
+    /** Single Mode Input AIN12+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN12 = 12,
+    /** Single Mode Input AIN13+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN13 = 13,
+    /** Single Mode Input AIN14+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN14 = 14,
+    /** Single Mode Input AIN15+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN15 = 15,
+    /** Positive Input VSSADC */
+    MXC_E_ADC_PGA_MUX_CH_SEL_VSSADC = 16,
+    /** Positive Input TMON_R */
+    MXC_E_ADC_PGA_MUX_CH_SEL_TMON_R = 17,
+    /** Positive Input VDDA/4 */
+    MXC_E_ADC_PGA_MUX_CH_SEL_VDDA4 = 18,
+    /** Positive Input PWRMAN_TST */
+    MXC_E_ADC_PGA_MUX_CH_SEL_PWRMON_TST = 19,
+    /** Positive Input Ain0Div */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN0DIV = 20,
+    /** Positive Input OpAmp OUTA */
+    MXC_E_ADC_PGA_MUX_CH_SEL_OUTA = 32,
+    /** Positive Input OpAmp OUTB */
+    MXC_E_ADC_PGA_MUX_CH_SEL_OUTB = 33,
+    /** Positive Input OpAmp OUTC */
+    MXC_E_ADC_PGA_MUX_CH_SEL_OUTC = 34,
+    /** Positive Input OpAmp OUTD */
+    MXC_E_ADC_PGA_MUX_CH_SEL_OUTD = 35,
+    /** Positive INA+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_INAPLUS = 36,
+    /** Positive SNO_or */
+    MXC_E_ADC_PGA_MUX_CH_SEL_SNO_OR = 37,
+    /** Positive SCM_or */
+    MXC_E_ADC_PGA_MUX_CH_SEL_SCM_OR = 38,
+    /** Positive TPROBE_sense */
+    MXC_E_ADC_PGA_MUX_CH_SEL_TPROBE_SENSE = 48,
+    /** Positive VREFDAC */
+    MXC_E_ADC_PGA_MUX_CH_SEL_VREFDAC = 49,
+    /** Positive VREFADJ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_VREFADJ = 50,
+    /** Positive Vdd3xtal */
+    MXC_E_ADC_PGA_MUX_CH_SEL_VDD3XTAL = 51
+} mxc_adc_pga_mux_ch_sel_t;
+
+/**
+ * @brief Decoded with the MUX Channel Select to enable Differential Mode Input to the ADC.
+ */
+typedef enum {
+    /** Differential Mode Disabled */
+    MXC_E_ADC_PGA_MUX_DIFF_DISABLE = 0,
+    /** Differential Mode Enabled */
+    MXC_E_ADC_PGA_MUX_DIFF_ENABLE
+} mxc_adc_pga_mux_diff_t;
+
+/**
+ * @brief Defines the PGA Gain Options.
+ */
+typedef enum {
+    /** PGA Gain = 1 */
+    MXC_E_ADC_PGA_GAIN_1 = 0,
+    /** PGA Gain = 2 */
+    MXC_E_ADC_PGA_GAIN_2,
+    /** PGA Gain = 4 */
+    MXC_E_ADC_PGA_GAIN_4,
+    /** PGA Gain = 8 */
+    MXC_E_ADC_PGA_GAIN_8,
+} mxc_adc_pga_gain_t;
+
+/**
+ * @brief Defines the Switch Control Mode.
+ */
+typedef enum {
+    /** Switch Control Mode = Software */
+    MXC_E_ADC_SPST_SW_CTRL_SOFTWARE = 0,
+    /** Switch Control Mode = Pulse Train */
+    MXC_E_ADC_SPST_SW_CTRL_PULSETRAIN
+} mxc_adc_spst_sw_ctrl_t;
+
+/**
+ * @brief Defines the number of channels to scan when Scan Mode is enabled.
+ */
+typedef enum {
+    /** Number of Channels to Scan = 1 */
+    MXC_E_ADC_SCAN_CNT_1 = 0,
+    /** Number of Channels to Scan = 2 */
+    MXC_E_ADC_SCAN_CNT_2,
+    /** Number of Channels to Scan = 3 */
+    MXC_E_ADC_SCAN_CNT_3,
+    /** Number of Channels to Scan = 4 */
+    MXC_E_ADC_SCAN_CNT_4,
+    /** Number of Channels to Scan = 5 */
+    MXC_E_ADC_SCAN_CNT_5,
+    /** Number of Channels to Scan = 6 */
+    MXC_E_ADC_SCAN_CNT_6,
+    /** Number of Channels to Scan = 7 */
+    MXC_E_ADC_SCAN_CNT_7,
+    /** Number of Channels to Scan = 8 */
+    MXC_E_ADC_SCAN_CNT_8,
+} mxc_adc_scan_cnt_t;
+
+/*                                              Offset   Register Description
+                                                ======   =================================================== */
+typedef struct {
+    __IO uint32_t ctrl0;                    /*  0x0000   ADC Control Register 0                              */
+    __IO uint32_t pga_ctrl;                 /*  0x0004   PGA Control Register                                */
+    __IO uint32_t tg_ctrl0;                 /*  0x0008   ADC Timing Generator Control 0                      */
+    __IO uint32_t tg_ctrl1;                 /*  0x000C   ADC Timing Generator Control 1                      */
+    __IO uint32_t limit;                    /*  0x0010   ADC Limit Settings                                  */
+    __IO uint32_t intr;                     /*  0x0014   ADC Interrupt Flags and Enable/Disable Controls     */
+    __IO uint32_t out;                      /*  0x0018   ADC Output Register                                 */
+} mxc_adc_regs_t;
+
+/*                                              Offset   Register Description
+                                                ======   =================================================== */
+typedef struct {
+    __IO uint32_t ctrl1;                    /*  0x0000   ADC Control Register 1                              */
+    __IO uint32_t scan1;                    /*  0x0004   ADC Auto-Scan Settings 1                            */
+    __IO uint32_t scan2;                    /*  0x0008   ADC Auto-Scan Settings 2                            */
+    __IO uint32_t ro_cal0;                  /*  0x000C   ADC Ring Osc Calibration 0                          */
+    __IO uint32_t ro_cal1;                  /*  0x0010   ADC Ring Osc Calibration 1                          */
+} mxc_adccfg_regs_t;
+
+typedef struct {
+    __IO uint16_t data;                     /*  0x0000   Read to pull sample data from ADC FIFO              */
+} mxc_adc_fifo_regs_t;
+
+/*
+   Register offsets for module ADC, ADCCFG, ADC_FIFO
+*/
+#define MXC_R_ADC_OFFS_CTRL0                      ((uint32_t)0x00000000UL)
+#define MXC_R_ADC_OFFS_PGA_CTRL                   ((uint32_t)0x00000004UL)
+#define MXC_R_ADC_OFFS_TG_CTRL0                   ((uint32_t)0x00000008UL)
+#define MXC_R_ADC_OFFS_TG_CTRL1                   ((uint32_t)0x0000000CUL)
+#define MXC_R_ADC_OFFS_LIMIT                      ((uint32_t)0x00000010UL)
+#define MXC_R_ADC_OFFS_INTR                       ((uint32_t)0x00000014UL)
+#define MXC_R_ADC_OFFS_OUT                        ((uint32_t)0x00000018UL)
+
+#define MXC_R_ADCCFG_OFFS_CTRL1                   ((uint32_t)0x00000000UL)
+#define MXC_R_ADCCFG_OFFS_SCAN1                   ((uint32_t)0x00000004UL)
+#define MXC_R_ADCCFG_OFFS_SCAN2                   ((uint32_t)0x00000008UL)
+#define MXC_R_ADCCFG_OFFS_RO_CAL0                 ((uint32_t)0x0000000CUL)
+#define MXC_R_ADCCFG_OFFS_RO_CAL1                 ((uint32_t)0x00000010UL)
+#define MXC_R_ADC_FIFO_OFFS_DATA                  ((uint32_t)0x00000000UL)
+
+/*
+   Field positions and masks for module ADC.
+*/
+#define MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS                    0
+#define MXC_F_ADC_CTRL0_ADC_WAKE_CNT                        ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS))
+#define MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS                   5
+#define MXC_F_ADC_CTRL0_ADC_STRT_MODE                       ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS))
+#define MXC_F_ADC_CTRL0_ADC_RANGE_POS                       6
+#define MXC_F_ADC_CTRL0_ADC_RANGE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_RANGE_POS))
+#define MXC_F_ADC_CTRL0_ADC_BI_POL_POS                      7
+#define MXC_F_ADC_CTRL0_ADC_BI_POL                          ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_BI_POL_POS))
+#define MXC_F_ADC_CTRL0_ADC_DV_REG_POS                      8
+#define MXC_F_ADC_CTRL0_ADC_DV_REG                          ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_REG_POS))
+#define MXC_F_ADC_CTRL0_ADC_DV_POS                          9
+#define MXC_F_ADC_CTRL0_ADC_DV                              ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_POS))
+#define MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS                   10
+#define MXC_F_ADC_CTRL0_ADC_LMT_DMODE                       ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS))
+#define MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS                     11
+#define MXC_F_ADC_CTRL0_ADC_SMP_EXT                         ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS))
+#define MXC_F_ADC_CTRL0_ADC_CLK_EN_POS                      12
+#define MXC_F_ADC_CTRL0_ADC_CLK_EN                          ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_CLK_EN_POS))
+#define MXC_F_ADC_CTRL0_CPU_ADC_RST_POS                     13
+#define MXC_F_ADC_CTRL0_CPU_ADC_RST                         ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_RST_POS))
+#define MXC_F_ADC_CTRL0_CPU_ADC_START_POS                   14
+#define MXC_F_ADC_CTRL0_CPU_ADC_START                       ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_START_POS))
+#define MXC_F_ADC_CTRL0_CPU_ADC_EN_POS                      15
+#define MXC_F_ADC_CTRL0_CPU_ADC_EN                          ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_EN_POS))
+#define MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS                   18
+#define MXC_F_ADC_CTRL0_ADC_FIFO_FULL                       ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS))
+#define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS                  19
+#define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY                      ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS))
+#define MXC_F_ADC_CTRL0_AVG_MODE_POS                        20
+#define MXC_F_ADC_CTRL0_AVG_MODE                            ((uint32_t)(0x00000003UL << MXC_F_ADC_CTRL0_AVG_MODE_POS))
+#define MXC_F_ADC_CTRL0_CPU_DAC_START_POS                   22
+#define MXC_F_ADC_CTRL0_CPU_DAC_START                       ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_DAC_START_POS))
+#define MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS                    24
+#define MXC_F_ADC_CTRL0_ADC_CLK_MODE                        ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS))
+#define MXC_F_ADC_CTRL0_ADC_MODE_POS                        28
+#define MXC_F_ADC_CTRL0_ADC_MODE                            ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_MODE_POS))
+
+#define MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS                     0
+#define MXC_F_ADC_PGA_CTRL_PGA_GAIN                         ((uint32_t)(0x00000003UL << MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS           2
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN               ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS                  3
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST                      ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS            4
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY                ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS                  5
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK                      ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS               6
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS                   ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS))
+#define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS                 8
+#define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT                     ((uint32_t)(0x0000001FUL << MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS))
+#define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS                   13
+#define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN                       ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS))
+#define MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS                     14
+#define MXC_F_ADC_PGA_CTRL_MUX_DIFF                         ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS))
+#define MXC_F_ADC_PGA_CTRL_MUX_MODE_POS                     15
+#define MXC_F_ADC_PGA_CTRL_MUX_MODE                         ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_MODE_POS))
+#define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS              20
+#define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT                  ((uint32_t)(0x0000000FUL << MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS))
+#define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS                   24
+#define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL                       ((uint32_t)(0x0000003FUL << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS))
+
+#define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS                  0
+#define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT                      ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS))
+#define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS                 16
+#define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT                     ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS))
+
+#define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS                  0
+#define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT                      ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS))
+#define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS                  4
+#define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT                      ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS))
+#define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS                 8
+#define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT                     ((uint32_t)(0x00000007UL << MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS))
+#define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS                  12
+#define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT                      ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS))
+#define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS                  16
+#define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT                      ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS))
+
+#define MXC_F_ADC_LIMIT_LO_LIMIT_POS                        0
+#define MXC_F_ADC_LIMIT_LO_LIMIT                            ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_LO_LIMIT_POS))
+#define MXC_F_ADC_LIMIT_HI_LIMIT_POS                        16
+#define MXC_F_ADC_LIMIT_HI_LIMIT                            ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_HI_LIMIT_POS))
+
+#define MXC_F_ADC_INTR_FIFO_AF_POS                          6
+#define MXC_F_ADC_INTR_FIFO_AF                              ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_AF_POS))
+#define MXC_F_ADC_INTR_OUT_RNG_IF_POS                       7
+#define MXC_F_ADC_INTR_OUT_RNG_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IF_POS))
+#define MXC_F_ADC_INTR_HI_RNG_IF_POS                        8
+#define MXC_F_ADC_INTR_HI_RNG_IF                            ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IF_POS))
+#define MXC_F_ADC_INTR_LO_RNG_IF_POS                        9
+#define MXC_F_ADC_INTR_LO_RNG_IF                            ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IF_POS))
+#define MXC_F_ADC_INTR_DONE_IF_POS                          10
+#define MXC_F_ADC_INTR_DONE_IF                              ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_UF_IF_POS                       11
+#define MXC_F_ADC_INTR_FIFO_UF_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_OF_IF_POS                       12
+#define MXC_F_ADC_INTR_FIFO_OF_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_3Q_IF_POS                       13
+#define MXC_F_ADC_INTR_FIFO_3Q_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_2Q_IF_POS                       14
+#define MXC_F_ADC_INTR_FIFO_2Q_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_1Q_IF_POS                       15
+#define MXC_F_ADC_INTR_FIFO_1Q_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IF_POS))
+#define MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS                  16
+#define MXC_F_ADC_INTR_SPST0_CTRL_MODE                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS))
+#define MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS                  17
+#define MXC_F_ADC_INTR_SPST1_CTRL_MODE                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS))
+#define MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS                  18
+#define MXC_F_ADC_INTR_SPST2_CTRL_MODE                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS))
+#define MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS                  19
+#define MXC_F_ADC_INTR_SPST3_CTRL_MODE                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS))
+#define MXC_F_ADC_INTR_OUT_RNG_IE_POS                       23
+#define MXC_F_ADC_INTR_OUT_RNG_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IE_POS))
+#define MXC_F_ADC_INTR_HI_RNG_IE_POS                        24
+#define MXC_F_ADC_INTR_HI_RNG_IE                            ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IE_POS))
+#define MXC_F_ADC_INTR_LO_RNG_IE_POS                        25
+#define MXC_F_ADC_INTR_LO_RNG_IE                            ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IE_POS))
+#define MXC_F_ADC_INTR_DONE_IE_POS                          26
+#define MXC_F_ADC_INTR_DONE_IE                              ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_UF_IE_POS                       27
+#define MXC_F_ADC_INTR_FIFO_UF_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_OF_IE_POS                       28
+#define MXC_F_ADC_INTR_FIFO_OF_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_3Q_IE_POS                       29
+#define MXC_F_ADC_INTR_FIFO_3Q_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_2Q_IE_POS                       30
+#define MXC_F_ADC_INTR_FIFO_2Q_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_1Q_IE_POS                       31
+#define MXC_F_ADC_INTR_FIFO_1Q_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IE_POS))
+
+#define MXC_F_ADC_OUT_DATA_REG_POS                          0
+#define MXC_F_ADC_OUT_DATA_REG                              ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_OUT_DATA_REG_POS))
+
+#define MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS                    16
+#define MXC_F_ADC_CTRL1_ADC_SCAN_CNT                        ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS))
+
+#define MXC_F_ADC_SCAN1_ADC_SCAN0_POS                       0
+#define MXC_F_ADC_SCAN1_ADC_SCAN0                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN0_POS))
+#define MXC_F_ADC_SCAN1_ADC_SCAN1_POS                       8
+#define MXC_F_ADC_SCAN1_ADC_SCAN1                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN1_POS))
+#define MXC_F_ADC_SCAN1_ADC_SCAN2_POS                       16
+#define MXC_F_ADC_SCAN1_ADC_SCAN2                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN2_POS))
+#define MXC_F_ADC_SCAN1_ADC_SCAN3_POS                       24
+#define MXC_F_ADC_SCAN1_ADC_SCAN3                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN3_POS))
+
+#define MXC_F_ADC_SCAN2_ADC_SCAN4_POS                       0
+#define MXC_F_ADC_SCAN2_ADC_SCAN4                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN4_POS))
+#define MXC_F_ADC_SCAN2_ADC_SCAN5_POS                       8
+#define MXC_F_ADC_SCAN2_ADC_SCAN5                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN5_POS))
+#define MXC_F_ADC_SCAN2_ADC_SCAN6_POS                       16
+#define MXC_F_ADC_SCAN2_ADC_SCAN6                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN6_POS))
+#define MXC_F_ADC_SCAN2_ADC_SCAN7_POS                       24
+#define MXC_F_ADC_SCAN2_ADC_SCAN7                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN7_POS))
+
+#define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS                     0
+#define MXC_F_ADC_RO_CAL0_RO_CAL_EN                         ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS))
+#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS                    1
+#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN                        ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS))
+#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS                   2
+#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD                       ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS))
+#define MXC_F_ADC_RO_CAL0_TRM_MU_POS                        8
+#define MXC_F_ADC_RO_CAL0_TRM_MU                            ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS))
+#define MXC_F_ADC_RO_CAL0_RO_TRM_POS                        23
+#define MXC_F_ADC_RO_CAL0_RO_TRM                            ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS))
+
+#define MXC_F_ADC_RO_CAL1_TRM_INIT_POS                      0
+#define MXC_F_ADC_RO_CAL1_TRM_INIT                          ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS))
+#define MXC_F_ADC_RO_CAL1_TRM_MIN_POS                       10
+#define MXC_F_ADC_RO_CAL1_TRM_MIN                           ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS))
+#define MXC_F_ADC_RO_CAL1_TRM_MAX_POS                       20
+#define MXC_F_ADC_RO_CAL1_TRM_MAX                           ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* _MXC_ADC_REGS_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/aes_regs.h

@@ -0,0 +1,159 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_AES_REGS_H_
+#define _MXC_AES_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  aes_regs.h
+ * @addtogroup aes AES
+ * @{
+ */
+
+/**
+ * @brief  Settings for AES_CTRL.CRYPT_MODE 
+ */
+typedef enum {
+    MXC_E_AES_CTRL_ENCRYPT_MODE = 0,
+    MXC_E_AES_CTRL_DECRYPT_MODE = 1
+} mxc_aes_ctrl_crypt_mode_t;
+
+/**
+ * @brief Settings for AES_CTRL.EXP_KEY_MODE 
+ */
+typedef enum {
+    MXC_E_AES_CTRL_CALC_NEW_EXP_KEY = 0,
+    MXC_E_AES_CTRL_USE_LAST_EXP_KEY = 1
+} mxc_aes_ctrl_exp_key_mode_t;
+
+/**
+ * @brief Settings for AES_CTRL.KEY_SIZE 
+ */
+typedef enum {
+    MXC_E_AES_CTRL_KEY_SIZE_128 = 0,
+    MXC_E_AES_CTRL_KEY_SIZE_192 = 1,
+    MXC_E_AES_CTRL_KEY_SIZE_256 = 2
+} mxc_aes_ctrl_key_size_t;
+
+/*                                       Offset   Register Description
+                                         ======   =========================================================== */
+typedef struct {
+    __IO uint32_t ctrl;              /*  0x0000   AES Control and Status                                      */
+    __I uint32_t rsv004;             /*  0x0004                                                               */
+    __IO uint32_t erase_all;         /*  0x0008   Write to Trigger AES Memory Erase                           */
+} mxc_aes_regs_t;
+
+/*                                       Offset   Register Description
+                                         ======   =========================================================== */
+typedef struct {
+    __IO uint32_t inp[4];            /*  0x0000   AES Input 0..3                                              */
+    __IO uint32_t key[8];            /*  0x0010   AES Key 0..7                                                */
+    __IO uint32_t out[4];            /*  0x0030   AES Output 0..3                                             */
+    __IO uint32_t expkey[8];         /*  0x0040   AES Expanded Key Data 0..7                                  */
+} mxc_aes_mem_regs_t;
+
+/*
+   Register offsets for module AES.
+*/
+#define MXC_R_AES_OFFS_CTRL                       ((uint32_t)0x00000000UL)
+#define MXC_R_AES_OFFS_ERASE_ALL                  ((uint32_t)0x00000008UL)
+#define MXC_R_AES_MEM_OFFS_INP0                   ((uint32_t)0x00000000UL)
+#define MXC_R_AES_MEM_OFFS_INP1                   ((uint32_t)0x00000004UL)
+#define MXC_R_AES_MEM_OFFS_INP2                   ((uint32_t)0x00000008UL)
+#define MXC_R_AES_MEM_OFFS_INP3                   ((uint32_t)0x0000000CUL)
+#define MXC_R_AES_MEM_OFFS_KEY0                   ((uint32_t)0x00000010UL)
+#define MXC_R_AES_MEM_OFFS_KEY1                   ((uint32_t)0x00000014UL)
+#define MXC_R_AES_MEM_OFFS_KEY2                   ((uint32_t)0x00000018UL)
+#define MXC_R_AES_MEM_OFFS_KEY3                   ((uint32_t)0x0000001CUL)
+#define MXC_R_AES_MEM_OFFS_KEY4                   ((uint32_t)0x00000020UL)
+#define MXC_R_AES_MEM_OFFS_KEY5                   ((uint32_t)0x00000024UL)
+#define MXC_R_AES_MEM_OFFS_KEY6                   ((uint32_t)0x00000028UL)
+#define MXC_R_AES_MEM_OFFS_KEY7                   ((uint32_t)0x0000002CUL)
+#define MXC_R_AES_MEM_OFFS_OUT0                   ((uint32_t)0x00000030UL)
+#define MXC_R_AES_MEM_OFFS_OUT1                   ((uint32_t)0x00000034UL)
+#define MXC_R_AES_MEM_OFFS_OUT2                   ((uint32_t)0x00000038UL)
+#define MXC_R_AES_MEM_OFFS_OUT3                   ((uint32_t)0x0000003CUL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY0                ((uint32_t)0x00000040UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY1                ((uint32_t)0x00000044UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY2                ((uint32_t)0x00000048UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY3                ((uint32_t)0x0000004CUL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY4                ((uint32_t)0x00000050UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY5                ((uint32_t)0x00000054UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY6                ((uint32_t)0x00000058UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY7                ((uint32_t)0x0000005CUL)
+
+#define MXC_F_AES_CTRL_START_POS                  0
+#define MXC_F_AES_CTRL_START                      ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS))
+#define MXC_F_AES_CTRL_CRYPT_MODE_POS             1
+#define MXC_F_AES_CTRL_CRYPT_MODE                 ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS))
+#define MXC_F_AES_CTRL_EXP_KEY_MODE_POS           2
+#define MXC_F_AES_CTRL_EXP_KEY_MODE               ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
+#define MXC_F_AES_CTRL_KEY_SIZE_POS               3
+#define MXC_F_AES_CTRL_KEY_SIZE                   ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS))
+#define MXC_F_AES_CTRL_INTEN_POS                  5
+#define MXC_F_AES_CTRL_INTEN                      ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS))
+#define MXC_F_AES_CTRL_INTFL_POS                  6
+#define MXC_F_AES_CTRL_INTFL                      ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS))
+
+#define MXC_V_AES_CTRL_ENCRYPT_MODE               0
+#define MXC_V_AES_CTRL_DECRYPT_MODE               1
+#define MXC_S_AES_CTRL_ENCRYPT_MODE               ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS))
+#define MXC_S_AES_CTRL_DECRYPT_MODE               ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS))
+
+#define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY           0
+#define MXC_V_AES_CTRL_USE_LAST_EXP_KEY           1
+#define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY           ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
+#define MXC_S_AES_CTRL_USE_LAST_EXP_KEY           ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
+
+#define MXC_V_AES_CTRL_KEY_SIZE_128               0
+#define MXC_V_AES_CTRL_KEY_SIZE_192               1
+#define MXC_V_AES_CTRL_KEY_SIZE_256               2
+#define MXC_S_AES_CTRL_KEY_SIZE_128               ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS))
+#define MXC_S_AES_CTRL_KEY_SIZE_192               ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS))
+#define MXC_S_AES_CTRL_KEY_SIZE_256               ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_AES_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/afe_regs.h

@@ -0,0 +1,626 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_AFE_REGS_H
+#define _MXC_AFE_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  afe_regs.h
+ * @addtogroup afe AFE
+ * @{
+ */
+
+/**
+ * @brief Defines Configure Options for the LED Ports.
+ */
+typedef enum {
+    /** LED Sink Port 0 with OpAmp A, LED Sink Port 1 with OpAmp C */
+    MXC_E_AFE_LED_CFG_PORT_OPAMP_A_C = 0,
+    /** LED Sink Port 0 with OpAmp B, LED Sink Port 1 with OpAmp D */
+    MXC_E_AFE_LED_CFG_PORT_OPAMP_B_D,
+    /** Disable LED Sink Port 0,Disable LED Sink Port 1 */
+    MXC_E_AFE_LED_CFG_PORT_DISABLED,
+} mxc_afe_led_cfg_port_t;
+
+/**
+ * @brief Setup of Wake Up Detector for LPCs.
+ */
+typedef enum {
+    /** IDLE */
+    MXC_E_AFE_EN_WUD_COMP_IDLE = 0,
+    /** Activate WUD for falling edges */
+    MXC_E_AFE_EN_WUD_COMP_FALLING_EDGE = 2,
+    /** Activate WUD for rising edges */
+    MXC_E_AFE_EN_WUD_COMP_RISING_EDGE = 3
+} mxc_afe_en_wud_comp_t;
+
+/**
+ * @brief LPC InMode.
+ */
+typedef enum {
+    /** InMode: both Nch and Pch */
+    MXC_E_AFE_IN_MODE_COMP_NCH_PCH = 0,
+    /** InMode: only Nch  */
+    MXC_E_AFE_IN_MODE_COMP_NCH,
+    /** InMode: only Pch  */
+    MXC_E_AFE_IN_MODE_COMP_PCH,
+} mxc_afe_in_mode_comp_t;
+
+/**
+ * @brief LPC Bias.
+ */
+typedef enum {
+    /** BIAS 0.52uA Delay 4.0us  */
+    MXC_E_AFE_BIAS_MODE_COMP_0 = 0,
+    /** BIAS 1.4uA Delay 1.7us  */
+    MXC_E_AFE_BIAS_MODE_COMP_1,
+    /** BIAS 2.8uA Delay 1.1us  */
+    MXC_E_AFE_BIAS_MODE_COMP_2,
+    /** BIAS 5.1uA Delay 0.7us  */
+    MXC_E_AFE_BIAS_MODE_COMP_3
+} mxc_afe_bias_mode_comp_t;
+
+/**
+ * @brief TMON Current Value.
+ */
+typedef enum {
+    /** TMON Current 4uA  */
+    MXC_E_AFE_TMON_CURRENT_VAL_0 = 0,
+    /** TMON Current 60uA  */
+    MXC_E_AFE_TMON_CURRENT_VAL_1,
+    /** TMON Current 64uA  */
+    MXC_E_AFE_TMON_CURRENT_VAL_2,
+    /** TMON Current 120uA  */
+    MXC_E_AFE_TMON_CURRENT_VAL_3
+} mxc_afe_tmon_current_t;
+
+/**
+ * @brief REFADC and REFDAC Voltage Select.
+ */
+typedef enum {
+    /** Voltage Reference = 1.024 V */
+    MXC_E_AFE_REF_VOLT_SEL_1024 = 0,
+    /** Voltage Reference = 1.5 V */
+    MXC_E_AFE_REF_VOLT_SEL_1500,
+    /** Voltage Reference = 2.048 V */
+    MXC_E_AFE_REF_VOLT_SEL_2048,
+    /** Voltage Reference = 2.5 V */
+    MXC_E_AFE_REF_VOLT_SEL_2500
+} mxc_afe_ref_volt_sel_t;
+
+/**
+ * @brief Selection for DAC VOltage Reference, REFADC or REFDAC.
+ */
+typedef enum {
+    /** DAC Voltage Reference = REFADC */
+    MXC_E_AFE_DAC_REF_REFADC = 0,
+    /** DAC Voltage Reference = REFDAC */
+    MXC_E_AFE_DAC_REF_REFDAC
+} mxc_afe_dac_ref_t;
+
+/**
+ * @brief Selection for LPC Hysteresis.
+ */
+typedef enum {
+    /** LPC Hysteresis = 0 mV */
+    MXC_E_AFE_HYST_COMP_0 = 0,
+    /** LPC Hysteresis = 7.5 mV */
+    MXC_E_AFE_HYST_COMP_1,
+    /** LPC Hysteresis = 15 mV */
+    MXC_E_AFE_HYST_COMP_2,
+    /** LPC Hysteresis = 30 mV */
+    MXC_E_AFE_HYST_COMP_3
+} mxc_afe_hyst_comp_t;
+
+/**
+ * @brief Selection for MUX for  SCM_or_sel.
+ */
+typedef enum {
+    /** SCM_or = HIZ */
+    MXC_E_AFE_SCM_OR_SEL_HIZ = 0,
+    /** SCM_or = SCM0 */
+    MXC_E_AFE_SCM_OR_SEL_SCM0,
+    /** SCM_or = SCM1 */
+    MXC_E_AFE_SCM_OR_SEL_SCM1,
+    /** SCM_or = SCM2 */
+    MXC_E_AFE_SCM_OR_SEL_SCM2,
+    /** SCM_or = SCM3 */
+    MXC_E_AFE_SCM_OR_SEL_SCM3
+} mxc_afe_scm_or_sel_t;
+
+/**
+ * @brief Selection for MUX for  SNO_or_sel.
+ */
+typedef enum {
+    /** SNO_or = HIZ */
+    MXC_E_AFE_SNO_OR_SEL_HIZ = 0,
+    /** SNO_or = SNO0 */
+    MXC_E_AFE_SNO_OR_SEL_SNO0,
+    /** SNO_or = SNO1 */
+    MXC_E_AFE_SNO_OR_SEL_SNO1,
+    /** SNO_or = SNO2 */
+    MXC_E_AFE_SNO_OR_SEL_SNO2,
+    /** SNO_or = SNO3 */
+    MXC_E_AFE_SNO_OR_SEL_SNO3
+} mxc_afe_sno_or_sel_t;
+
+/**
+ * @brief Selection for MUX  DACx_sel.
+ */
+typedef enum {
+    /** dacx  = DACOP */
+    MXC_E_AFE_DACX_SEL_P = 0,
+    /** dacx  = DACON */
+    MXC_E_AFE_DACX_SEL_N
+} mxc_afe_dacx_sel_t;
+
+/**
+ * @brief Selection for state of Switch.
+ */
+typedef enum {
+    /** Switch is OPEN */
+    MXC_E_AFE_CLOSE_SPST_SWITCH_OPEN = 0,
+    /** Switch is CLOSED */
+    MXC_E_AFE_CLOSE_SPST_SWITCH_CLOSE
+} mxc_afe_close_spst_t;
+
+/**
+ * @brief Switch to Connect Positive Pad to GND.
+ */
+typedef enum {
+    /** Positive Pad GND Switch OPEN */
+    MXC_E_AFE_GND_SEL_OPAMP_SWITCH_OPEN = 0,
+    /** Positive Pad GND Switch CLOSED */
+    MXC_E_AFE_GND_SEL_OPAMP_SWITCH_CLOSED
+} mxc_afe_gnd_sel_opamp_t;
+
+/**
+ * @brief MUX Selection for OpPsel.
+ */
+typedef enum {
+    /** OpPsel = INx+ */
+    MXC_E_AFE_P_IN_SEL_OPAMP_INPLUS = 0,
+    /** OpPsel = DAC_or */
+    MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR,
+    /** OpPsel = SNO_or */
+    MXC_E_AFE_P_IN_SEL_OPAMP_SNO_OR,
+    /** OpPsel = DAC_or also output on INx+ */
+    MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR_AND_INPLUS
+} mxc_afe_p_in_sel_opamp_t;
+
+/**
+ * @brief MUX Selection for OpNsel.
+ */
+typedef enum {
+    /** OpNsel = INx- */
+    MXC_E_AFE_N_IN_SEL_OPAMP_INMINUS = 0,
+    /** OpNsel = OUTx */
+    MXC_E_AFE_N_IN_SEL_OPAMP_OUT,
+    /** OpNsel = SCM_or */
+    MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR,
+    /**OpNsel = SCM_or also output on INx- */
+    MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR_AND_INMINUS,
+} mxc_afe_n_in_sel_opamp_t;
+
+/**
+ * @brief MUX Selection for DAC_sel.
+ */
+typedef enum {
+    /** DAC_or = DAC0 */
+    MXC_E_AFE_DAC_SEL_DAC0 = 0,
+    /** DAC_or = DAC1 */
+    MXC_E_AFE_DAC_SEL_DAC1,
+    /** DAC_or = DAC2P */
+    MXC_E_AFE_DAC_SEL_DAC2P,
+    /** DAC_or = DAC3P */
+    MXC_E_AFE_DAC_SEL_DAC3P
+} mxc_afe_dac_sel_t;
+
+/**
+ * @brief MUX Selection for NPAD_sel.
+ */
+typedef enum {
+    /** NPAD_Sel = HIZ */
+    MXC_E_AFE_NPAD_SEL_HIZ = 0,
+    /** NPAD_Sel = LED Observe Port */
+    MXC_E_AFE_NPAD_SEL_LED_OBS_PORT,
+    /** NPAD_Sel = DAC_or */
+    MXC_E_AFE_NPAD_SEL_DAC_OR,
+    /** NPAD_Sel = DAC_or and LED Observe Port */
+    MXC_E_AFE_NPAD_SEL_DAC_OR_AND_LED_OBS_PORT
+} mxc_afe_npad_sel_t;
+
+/**
+ * @brief MUX Selection for CmpPSel.
+ */
+typedef enum {
+    /** CmpPSel = INx+ */
+    MXC_E_AFE_POS_IN_SEL_COMP_INPLUS = 0,
+    /** CmpPSel = SCM */
+    MXC_E_AFE_POS_IN_SEL_COMP_SCM,
+    /** CmpPSel = dac1 */
+    MXC_E_AFE_POS_IN_SEL_COMP_DAC1,
+    /** CmpPSel = DAC3P */
+    MXC_E_AFE_POS_IN_SEL_COMP_DAC3P,
+    /** CmpPSel = LED Observe Port */
+    MXC_E_AFE_POS_IN_SEL_COMP_LED_OBS_PORT,
+    /** CmpPSel = dac1 also output on INx+ */
+    MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_INPLUS,
+    /** CmpPSel = DAC3P also output on INx+ */
+    MXC_E_AFE_POS_IN_SEL_COMP_DAC3P_AND_INPLUS,
+    /** CmpPSel = dac1 also output on SCM */
+    MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_SCM
+} mxc_afe_pos_in_sel_comp_t;
+
+/**
+ * @brief MUX Selection for CmpNSel.
+ */
+typedef enum {
+    /** CmpNSel = INx- */
+    MXC_E_AFE_NEG_IN_SEL_COMP_INMINUS = 0,
+    /** CmpNSel = SNO */
+    MXC_E_AFE_NEG_IN_SEL_COMP_SNO,
+    /** CmpNSel = dac0 */
+    MXC_E_AFE_NEG_IN_SEL_COMP_DAC0,
+    /** CmpNSel = DAC2P */
+    MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P,
+    /** CmpNSel = LED Observation Port */
+    MXC_E_AFE_NEG_IN_SEL_COMP_LED_OBS_PORT,
+    /** CmpNSel = dac0 also output on INx- */
+    MXC_E_AFE_NEG_IN_SEL_COMP_DAC0_AND_INMINUS,
+    /** CmpNSel = DAC2 also output on INx- */
+    MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_INMINUS,
+    /** CmpNSel = DAC2 also output on SNO */
+    MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_SNO
+} mxc_afe_neg_in_sel_comp_t;
+
+/*                                      Offset   Register Description
+                                        ======   ==================================================== */
+typedef struct {
+    __IO uint32_t intr;             /*  0x0000   Analog Front End Interrupt Flags and Enable/Disable  */
+    __IO uint32_t ctrl0;            /*  0x0004   Analog Front End Control 0                           */
+    __IO uint32_t ctrl1;            /*  0x0008   Analog Front End Control 1                           */
+    __IO uint32_t ctrl2;            /*  0x000C   Analog Front End Control 2                           */
+    __IO uint32_t ctrl3;            /*  0x0010   Analog Front End Control 3                           */
+    __IO uint32_t ctrl4;            /*  0x0014   Analog Front End Control 4                           */
+    __IO uint32_t ctrl5;            /*  0x0018   Analog Front End Control 5                           */
+} mxc_afe_regs_t;
+
+/*
+   Register offsets for module AFE.
+*/
+#define MXC_R_AFE_OFFS_INTR                   ((uint32_t)0x00000000UL)
+#define MXC_R_AFE_OFFS_CTRL0                  ((uint32_t)0x00000004UL)
+#define MXC_R_AFE_OFFS_CTRL1                  ((uint32_t)0x00000008UL)
+#define MXC_R_AFE_OFFS_CTRL2                  ((uint32_t)0x0000000CUL)
+#define MXC_R_AFE_OFFS_CTRL3                  ((uint32_t)0x00000010UL)
+#define MXC_R_AFE_OFFS_CTRL4                  ((uint32_t)0x00000014UL)
+#define MXC_R_AFE_OFFS_CTRL5                  ((uint32_t)0x00000018UL)
+
+/*
+   Field positions and masks for module AFE.
+*/
+#define MXC_F_AFE_INTR_OP_COMP0_IF_POS                      0
+#define MXC_F_AFE_INTR_OP_COMP0_IF                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IF_POS))
+#define MXC_F_AFE_INTR_OP_COMP1_IF_POS                      1
+#define MXC_F_AFE_INTR_OP_COMP1_IF                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IF_POS))
+#define MXC_F_AFE_INTR_OP_COMP2_IF_POS                      2
+#define MXC_F_AFE_INTR_OP_COMP2_IF                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IF_POS))
+#define MXC_F_AFE_INTR_OP_COMP3_IF_POS                      3
+#define MXC_F_AFE_INTR_OP_COMP3_IF                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IF_POS))
+#define MXC_F_AFE_INTR_LP_COMP0_IF_POS                      4
+#define MXC_F_AFE_INTR_LP_COMP0_IF                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IF_POS))
+#define MXC_F_AFE_INTR_LP_COMP1_IF_POS                      5
+#define MXC_F_AFE_INTR_LP_COMP1_IF                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IF_POS))
+#define MXC_F_AFE_INTR_LP_COMP2_IF_POS                      6
+#define MXC_F_AFE_INTR_LP_COMP2_IF                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IF_POS))
+#define MXC_F_AFE_INTR_LP_COMP3_IF_POS                      7
+#define MXC_F_AFE_INTR_LP_COMP3_IF                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IF_POS))
+#define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS                 8
+#define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU                     ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS                 9
+#define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU                     ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS                 10
+#define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU                     ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS                 11
+#define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU                     ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS                 12
+#define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU                     ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS                 13
+#define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU                     ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS                 14
+#define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU                     ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS                 15
+#define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU                     ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_OP_COMP0_POL_POS                     16
+#define MXC_F_AFE_INTR_OP_COMP0_POL                         ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_POL_POS))
+#define MXC_F_AFE_INTR_OP_COMP1_POL_POS                     17
+#define MXC_F_AFE_INTR_OP_COMP1_POL                         ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_POL_POS))
+#define MXC_F_AFE_INTR_OP_COMP2_POL_POS                     18
+#define MXC_F_AFE_INTR_OP_COMP2_POL                         ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_POL_POS))
+#define MXC_F_AFE_INTR_OP_COMP3_POL_POS                     19
+#define MXC_F_AFE_INTR_OP_COMP3_POL                         ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_POL_POS))
+#define MXC_F_AFE_INTR_LP_COMP0_POL_POS                     20
+#define MXC_F_AFE_INTR_LP_COMP0_POL                         ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_POL_POS))
+#define MXC_F_AFE_INTR_LP_COMP1_POL_POS                     21
+#define MXC_F_AFE_INTR_LP_COMP1_POL                         ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_POL_POS))
+#define MXC_F_AFE_INTR_LP_COMP2_POL_POS                     22
+#define MXC_F_AFE_INTR_LP_COMP2_POL                         ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_POL_POS))
+#define MXC_F_AFE_INTR_LP_COMP3_POL_POS                     23
+#define MXC_F_AFE_INTR_LP_COMP3_POL                         ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_POL_POS))
+#define MXC_F_AFE_INTR_OP_COMP0_IE_POS                      24
+#define MXC_F_AFE_INTR_OP_COMP0_IE                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IE_POS))
+#define MXC_F_AFE_INTR_OP_COMP1_IE_POS                      25
+#define MXC_F_AFE_INTR_OP_COMP1_IE                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IE_POS))
+#define MXC_F_AFE_INTR_OP_COMP2_IE_POS                      26
+#define MXC_F_AFE_INTR_OP_COMP2_IE                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IE_POS))
+#define MXC_F_AFE_INTR_OP_COMP3_IE_POS                      27
+#define MXC_F_AFE_INTR_OP_COMP3_IE                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IE_POS))
+#define MXC_F_AFE_INTR_LP_COMP0_IE_POS                      28
+#define MXC_F_AFE_INTR_LP_COMP0_IE                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IE_POS))
+#define MXC_F_AFE_INTR_LP_COMP1_IE_POS                      29
+#define MXC_F_AFE_INTR_LP_COMP1_IE                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IE_POS))
+#define MXC_F_AFE_INTR_LP_COMP2_IE_POS                      30
+#define MXC_F_AFE_INTR_LP_COMP2_IE                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IE_POS))
+#define MXC_F_AFE_INTR_LP_COMP3_IE_POS                      31
+#define MXC_F_AFE_INTR_LP_COMP3_IE                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IE_POS))
+
+#define MXC_F_AFE_CTRL0_LED_CFG_POS                         0
+#define MXC_F_AFE_CTRL0_LED_CFG                             ((uint32_t)(0x0000000FUL << MXC_F_AFE_CTRL0_LED_CFG_POS))
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS                 4
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0                     ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS))
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS                 5
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1                     ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS))
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS                 6
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2                     ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS))
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS                 7
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3                     ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS))
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS                    8
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP0                        ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS))
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS                    10
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP1                        ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS))
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS                    12
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP2                        ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS))
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS                    14
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP3                        ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS))
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS                   16
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP0                       ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS))
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS                   18
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP1                       ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS))
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS                   20
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP2                       ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS))
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS                   22
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP3                       ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS))
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS                 24
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS))
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS                 26
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS))
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS                 28
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS))
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS                 30
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS))
+
+#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS           0
+#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN               ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS))
+#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS          1
+#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL              ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS           3
+#define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN               ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS           4
+#define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN               ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS))
+#define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS                 5
+#define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL                     ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS                6
+#define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL                    ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS                8
+#define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL                    ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_SEL_POS                         10
+#define MXC_F_AFE_CTRL1_REF_SEL                             ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS                 11
+#define MXC_F_AFE_CTRL1_REF_ADC_POWERUP                     ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS                 12
+#define MXC_F_AFE_CTRL1_REF_DAC_POWERUP                     ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS))
+#define MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS                 13
+#define MXC_F_AFE_CTRL1_REF_BLK_POWERUP                     ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_COMP_POS                    14
+#define MXC_F_AFE_CTRL1_REF_ADC_COMP                        ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_COMP_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_COMP_POS                    15
+#define MXC_F_AFE_CTRL1_REF_DAC_COMP                        ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_COMP_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS               16
+#define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN                   ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS               18
+#define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN                   ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS))
+#define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS                   20
+#define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0                       ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS))
+#define MXC_F_AFE_CTRL1_PLL_TST_EN_POS                      23
+#define MXC_F_AFE_CTRL1_PLL_TST_EN                          ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_PLL_TST_EN_POS))
+#define MXC_F_AFE_CTRL1_V1EXTADJ_POS                        25
+#define MXC_F_AFE_CTRL1_V1EXTADJ                            ((uint32_t)(0x0000001FUL << MXC_F_AFE_CTRL1_V1EXTADJ_POS))
+#define MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS                    30
+#define MXC_F_AFE_CTRL1_TMON_CUR_SEL                        ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS))
+
+#define MXC_F_AFE_CTRL2_HYST_COMP0_POS                      0
+#define MXC_F_AFE_CTRL2_HYST_COMP0                          ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP0_POS))
+#define MXC_F_AFE_CTRL2_HYST_COMP1_POS                      2
+#define MXC_F_AFE_CTRL2_HYST_COMP1                          ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP1_POS))
+#define MXC_F_AFE_CTRL2_HYST_COMP2_POS                      4
+#define MXC_F_AFE_CTRL2_HYST_COMP2                          ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP2_POS))
+#define MXC_F_AFE_CTRL2_HYST_COMP3_POS                      6
+#define MXC_F_AFE_CTRL2_HYST_COMP3                          ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP3_POS))
+#define MXC_F_AFE_CTRL2_HY_POL_COMP0_POS                    8
+#define MXC_F_AFE_CTRL2_HY_POL_COMP0                        ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP0_POS))
+#define MXC_F_AFE_CTRL2_HY_POL_COMP1_POS                    9
+#define MXC_F_AFE_CTRL2_HY_POL_COMP1                        ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP1_POS))
+#define MXC_F_AFE_CTRL2_HY_POL_COMP2_POS                    10
+#define MXC_F_AFE_CTRL2_HY_POL_COMP2                        ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP2_POS))
+#define MXC_F_AFE_CTRL2_HY_POL_COMP3_POS                    11
+#define MXC_F_AFE_CTRL2_HY_POL_COMP3                        ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP3_POS))
+#define MXC_F_AFE_CTRL2_POWERUP_COMP0_POS                   12
+#define MXC_F_AFE_CTRL2_POWERUP_COMP0                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP0_POS))
+#define MXC_F_AFE_CTRL2_POWERUP_COMP1_POS                   13
+#define MXC_F_AFE_CTRL2_POWERUP_COMP1                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP1_POS))
+#define MXC_F_AFE_CTRL2_POWERUP_COMP2_POS                   14
+#define MXC_F_AFE_CTRL2_POWERUP_COMP2                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP2_POS))
+#define MXC_F_AFE_CTRL2_POWERUP_COMP3_POS                   15
+#define MXC_F_AFE_CTRL2_POWERUP_COMP3                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP3_POS))
+#define MXC_F_AFE_CTRL2_DACOUT_EN0_POS                      16
+#define MXC_F_AFE_CTRL2_DACOUT_EN0                          ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN0_POS))
+#define MXC_F_AFE_CTRL2_DACOUT_EN1_POS                      17
+#define MXC_F_AFE_CTRL2_DACOUT_EN1                          ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN1_POS))
+#define MXC_F_AFE_CTRL2_DACOUT_EN2_POS                      18
+#define MXC_F_AFE_CTRL2_DACOUT_EN2                          ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN2_POS))
+#define MXC_F_AFE_CTRL2_DACOUT_EN3_POS                      19
+#define MXC_F_AFE_CTRL2_DACOUT_EN3                          ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN3_POS))
+#define MXC_F_AFE_CTRL2_SCM_OR_SEL_POS                      20
+#define MXC_F_AFE_CTRL2_SCM_OR_SEL                          ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SCM_OR_SEL_POS))
+#define MXC_F_AFE_CTRL2_SNO_OR_SEL_POS                      23
+#define MXC_F_AFE_CTRL2_SNO_OR_SEL                          ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SNO_OR_SEL_POS))
+#define MXC_F_AFE_CTRL2_DAC0_SEL_POS                        26
+#define MXC_F_AFE_CTRL2_DAC0_SEL                            ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC0_SEL_POS))
+#define MXC_F_AFE_CTRL2_DAC1_SEL_POS                        27
+#define MXC_F_AFE_CTRL2_DAC1_SEL                            ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC1_SEL_POS))
+
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS                  12
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP0                      ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS))
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS                  13
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP1                      ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS))
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS                  14
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP2                      ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS))
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS                  15
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP3                      ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS))
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS                  16
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0                      ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS))
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS                  17
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1                      ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS))
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS                  18
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2                      ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS))
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS                  19
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3                      ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS))
+#define MXC_F_AFE_CTRL3_CLOSE_SPST0_POS                     20
+#define MXC_F_AFE_CTRL3_CLOSE_SPST0                         ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST0_POS))
+#define MXC_F_AFE_CTRL3_CLOSE_SPST1_POS                     21
+#define MXC_F_AFE_CTRL3_CLOSE_SPST1                         ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST1_POS))
+#define MXC_F_AFE_CTRL3_CLOSE_SPST2_POS                     22
+#define MXC_F_AFE_CTRL3_CLOSE_SPST2                         ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST2_POS))
+#define MXC_F_AFE_CTRL3_CLOSE_SPST3_POS                     23
+#define MXC_F_AFE_CTRL3_CLOSE_SPST3                         ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST3_POS))
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS                   24
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS))
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS                   25
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS))
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS                   26
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS))
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS                   27
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS))
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS                   28
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS))
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS                   29
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS))
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS                   30
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS))
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS                   31
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS))
+
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS                 0
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS))
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS                 2
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS))
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS                 4
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS))
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS                 6
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS))
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS                 8
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS))
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS                 10
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS))
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS                 12
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS))
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS                 14
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS))
+#define MXC_F_AFE_CTRL4_DAC_SEL_A_POS                       16
+#define MXC_F_AFE_CTRL4_DAC_SEL_A                           ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_A_POS))
+#define MXC_F_AFE_CTRL4_DAC_SEL_B_POS                       18
+#define MXC_F_AFE_CTRL4_DAC_SEL_B                           ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_B_POS))
+#define MXC_F_AFE_CTRL4_DAC_SEL_C_POS                       20
+#define MXC_F_AFE_CTRL4_DAC_SEL_C                           ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_C_POS))
+#define MXC_F_AFE_CTRL4_DAC_SEL_D_POS                       22
+#define MXC_F_AFE_CTRL4_DAC_SEL_D                           ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_D_POS))
+#define MXC_F_AFE_CTRL4_NPAD_SEL_A_POS                      24
+#define MXC_F_AFE_CTRL4_NPAD_SEL_A                          ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_A_POS))
+#define MXC_F_AFE_CTRL4_NPAD_SEL_B_POS                      26
+#define MXC_F_AFE_CTRL4_NPAD_SEL_B                          ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_B_POS))
+#define MXC_F_AFE_CTRL4_NPAD_SEL_C_POS                      28
+#define MXC_F_AFE_CTRL4_NPAD_SEL_C                          ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_C_POS))
+#define MXC_F_AFE_CTRL4_NPAD_SEL_D_POS                      30
+#define MXC_F_AFE_CTRL4_NPAD_SEL_D                          ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_D_POS))
+
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS               0
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0                   ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS))
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS               3
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1                   ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS))
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS               6
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2                   ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS))
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS               9
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3                   ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS))
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS               12
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0                   ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS))
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS               15
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1                   ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS))
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS               18
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2                   ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS))
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS               21
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3                   ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS))
+#define MXC_F_AFE_CTRL5_OP_CMP0_POS                         24
+#define MXC_F_AFE_CTRL5_OP_CMP0                             ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP0_POS))
+#define MXC_F_AFE_CTRL5_OP_CMP1_POS                         25
+#define MXC_F_AFE_CTRL5_OP_CMP1                             ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP1_POS))
+#define MXC_F_AFE_CTRL5_OP_CMP2_POS                         26
+#define MXC_F_AFE_CTRL5_OP_CMP2                             ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP2_POS))
+#define MXC_F_AFE_CTRL5_OP_CMP3_POS                         27
+#define MXC_F_AFE_CTRL5_OP_CMP3                             ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP3_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_AFE_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/clkman_regs.h

@@ -0,0 +1,493 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_CLKMAN_REGS_H_
+#define _MXC_CLKMAN_REGS_H_ 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  clkman_regs.h
+ * @addtogroup clkman CLKMAN
+ * @{
+ */
+
+/**
+ * @brief Defines clock input selections for the phase locked loop.
+ */
+typedef enum {
+    /** Input select for high frequency crystal oscillator */
+    MXC_E_CLKMAN_PLL_INPUT_SELECT_HFX = 0,
+    /** Input select for 24MHz ring oscillator */
+    MXC_E_CLKMAN_PLL_INPUT_SELECT_24MHZ_RO,
+} mxc_clkman_pll_input_select_t;
+
+/**
+ * @brief Defines clock input frequency for the phase locked loop.
+ */
+typedef enum {
+    /** Input frequency of 24MHz */
+    MXC_E_CLKMAN_PLL_DIVISOR_SELECT_24MHZ = 0,
+    /** Input frequency of 12MHz */
+    MXC_E_CLKMAN_PLL_DIVISOR_SELECT_12MHZ,
+    /** Input frequency of 8MHz */
+    MXC_E_CLKMAN_PLL_DIVISOR_SELECT_8MHZ,
+} mxc_clkman_pll_divisor_select_t;
+
+/**
+ * @brief Defines terminal count for PLL stable.
+ */
+typedef enum {
+    /** Clock stable after 2^8 = 256 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_8_CLKS = 0,
+    /** Clock stable after 2^9 = 512 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_9_CLKS,
+    /** Clock stable after 2^10 = 1024 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_10_CLKS,
+    /** Clock stable after 2^11 = 2048 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_11_CLKS,
+    /** Clock stable after 2^12 = 4096 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_12_CLKS,
+    /** Clock stable after 2^13 = 8192 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_13_CLKS,
+    /** Clock stable after 2^14 = 16384 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_14_CLKS,
+    /** Clock stable after 2^15 = 32768 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_15_CLKS,
+    /** Clock stable after 2^16 = 65536 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_16_CLKS,
+    /** Clock stable after 2^17 = 131072 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_17_CLKS,
+    /** Clock stable after 2^18 = 262144 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_18_CLKS,
+    /** Clock stable after 2^19 = 524288 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_19_CLKS,
+    /** Clock stable after 2^20 = 1048576 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_20_CLKS,
+    /** Clock stable after 2^21 = 2097152 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_21_CLKS,
+    /** Clock stable after 2^22 = 4194304 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_22_CLKS,
+    /** Clock stable after 2^23 = 8388608 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_23_CLKS
+} mxc_clkman_stability_count_t;
+
+/**
+ * @brief Defines clock source selections for system clock.
+ */
+typedef enum {
+    /** Clock select for 24MHz ring oscillator divided by 8 (3MHz) */
+    MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8 = 0,
+    /** Clock select for 24MHz ring oscillator */
+    MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO,
+    /** Clock select for high frequency crystal oscillator */
+    MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX,
+    /** Clock select for 48MHz phase locked loop output divided by 2 (24MHz) */
+    MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2
+} mxc_clkman_system_source_select_t;
+
+/**
+ * @brief Defines clock source selections for analog to digital converter clock.
+ */
+typedef enum {
+    /** Clock select for system clock frequency */
+    MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM = 0,
+    /** Clock select for 8MHz phase locked loop output */
+    MXC_E_CLKMAN_ADC_SOURCE_SELECT_PLL_8MHZ,
+    /** Clock select for high frequency crystal oscillator */
+    MXC_E_CLKMAN_ADC_SOURCE_SELECT_HFX,
+    /** Clock select for 24MHz ring oscillator */
+    MXC_E_CLKMAN_ADC_SOURCE_SELECT_24MHZ_RO,
+} mxc_clkman_adc_source_select_t;
+
+/**
+ * @brief Defines clock source selections for watchdog timer clock.
+ */
+typedef enum {
+    /** Clock select for system clock frequency */
+    MXC_E_CLKMAN_WDT_SOURCE_SELECT_SYSTEM = 0,
+    /** Clock select for 8MHz phase locked loop output */
+    MXC_E_CLKMAN_WDT_SOURCE_SELECT_RTC,
+    /** Clock select for high frequency crystal oscillator */
+    MXC_E_CLKMAN_WDT_SOURCE_SELECT_24MHZ_RO,
+    /** Clock select for 24MHz ring oscillator */
+    MXC_E_CLKMAN_WDT_SOURCE_SELECT_NANO,
+} mxc_clkman_wdt_source_select_t;
+
+/**
+ * @brief Defines clock scales for various clocks.
+ */
+typedef enum {
+    /** Clock disabled */
+    MXC_E_CLKMAN_CLK_SCALE_DISABLED = 0,
+    /** Clock enabled */
+    MXC_E_CLKMAN_CLK_SCALE_ENABLED,
+    /** Clock scale for dividing by 2 */
+    MXC_E_CLKMAN_CLK_SCALE_DIV_2,
+    /** Clock scale for dividing by 4 */
+    MXC_E_CLKMAN_CLK_SCALE_DIV_4,
+    /** Clock scale for dividing by 8 */
+    MXC_E_CLKMAN_CLK_SCALE_DIV_8,
+    /** Clock scale for dividing by 16 */
+    MXC_E_CLKMAN_CLK_SCALE_DIV_16,
+    /** Clock scale for dividing by 32 */
+    MXC_E_CLKMAN_CLK_SCALE_DIV_32,
+    /** Clock scale for dividing by 64 */
+    MXC_E_CLKMAN_CLK_SCALE_DIV_64,
+    /** Clock scale for dividing by 128 */
+    MXC_E_CLKMAN_CLK_SCALE_DIV_128,
+    /** Clock scale for dividing by 256 */
+    MXC_E_CLKMAN_CLK_SCALE_DIV_256
+} mxc_clkman_clk_scale_t;
+
+/**
+ * @brief Defines Setting of the Clock Gates .
+ */
+typedef enum {
+    /** Clock Gater is Off */
+    MXC_E_CLKMAN_CLK_GATE_OFF  = 0,
+    /** Clock Gater is Dynamic */
+    MXC_E_CLKMAN_CLK_GATE_DYNAMIC,
+    /** Clock Gater is On */
+    MXC_E_CLKMAN_CLK_GATE_ON
+} mxc_clkman_clk_gate_t;
+
+/*                                               Offset   Register Description
+                                                 ======   ===================================================================== */
+typedef struct {
+    __IO uint32_t clk_config;                /*  0x0000   System Clock Configuration                                  */
+    __IO uint32_t clk_ctrl;                  /*  0x0004   System Clock Controls                                                 */
+    __IO uint32_t intfl;                     /*  0x0008   Interrupt Flags                                             */
+    __IO uint32_t inten;                     /*  0x000C   Interrupt Enable/Disable Controls                           */
+    __IO uint32_t trim_calc;                 /*  0x0010   Trim Calculation Controls                                   */
+    __I uint32_t rsv0014[4];                 /*  0x0014                                                               */
+    __IO uint32_t i2c_timer_ctrl;            /*  0x0024   I2C Timer Control                                           */
+    __I uint32_t rsv0028[6];                 /*  0x0028                                                               */
+    __IO uint32_t clk_ctrl_0_system;         /*  0x0040   Control Settings for CLK0 - System Clock                    */
+    __IO uint32_t clk_ctrl_1_gpio;           /*  0x0044   Control Settings for CLK1 - GPIO Module Clock               */
+    __IO uint32_t clk_ctrl_2_pt;             /*  0x0048   Control Settings for CLK2 - Pulse Train Module Clock        */
+    __IO uint32_t clk_ctrl_3_spi0;           /*  0x004C   Control Settings for CLK3 - SPI0 Master Clock               */
+    __IO uint32_t clk_ctrl_4_spi1;           /*  0x0050   Control Settings for CLK4 - SPI1 Master Clock               */
+    __IO uint32_t clk_ctrl_5_spi2;           /*  0x0054   Control Settings for CLK5 - SPI2 Master Clock               */
+    __IO uint32_t clk_ctrl_6_i2cm;           /*  0x0058   Control Settings for CLK6 - Clock for all I2C Masters       */
+    __IO uint32_t clk_ctrl_7_i2cs;           /*  0x005C   Control Settings for CLK7 - I2C Slave Clock                 */
+    __IO uint32_t clk_ctrl_8_lcd_chpump;     /*  0x0060   Control Settings for CLK8 - LCD Charge Pump Clock           */
+    __IO uint32_t clk_ctrl_9_puf;            /*  0x0064   Control Settings for CLK9 - PUF Clock                       */
+    __IO uint32_t clk_ctrl_10_prng;          /*  0x0068   Control Settings for CLK10 - PRNG Clock                     */
+    __IO uint32_t clk_ctrl_11_wdt0;          /*  0x006C   Control Settings for CLK11 - Watchdog Timer 0 ScaledSysClk  */
+    __IO uint32_t clk_ctrl_12_wdt1;          /*  0x0070   Control Settings for CLK12 - Watchdog Timer 1 ScaledSysClk  */
+    __IO uint32_t clk_ctrl_13_rtc_int_sync;  /*  0x0074   Control Settings for CLK13 - RTC Interrupt Sync Clock       */
+    __IO uint32_t clk_ctrl_14_dac0;          /*  0x0078   Control Settings for CLK14 - 12-bit DAC 0 Clock             */
+    __IO uint32_t clk_ctrl_15_dac1;          /*  0x007C   Control Settings for CLK15 - 12-bit DAC 1 Clock             */
+    __IO uint32_t clk_ctrl_16_dac2;          /*  0x0080   Control Settings for CLK16 - 8-bit DAC 0 Clock              */
+    __IO uint32_t clk_ctrl_17_dac3;          /*  0x0084   Control Settings for CLK17 - 8-bit DAC 1 Clock              */
+    __I uint32_t rsv0088[30];                /*  0x0088                                                               */
+    __IO uint32_t crypt_clk_ctrl_0_aes;      /*  0x0100   Control Settings for Crypto Clock 0 - AES                   */
+    __IO uint32_t crypt_clk_ctrl_1_maa;      /*  0x0104   Control Settings for Crypto Clock 1 - MAA                   */
+    __IO uint32_t crypt_clk_ctrl_2_prng;     /*  0x0108   Control Settings for Crypto Clock 2 - PRNG                  */
+    __I uint32_t rsv010C[13];                /*  0x010C                                                               */
+    __IO uint32_t clk_gate_ctrl0;            /*  0x0140   Dynamic Clock Gating Control Register 0                     */
+    __IO uint32_t clk_gate_ctrl1;            /*  0x0144   Dynamic Clock Gating Control Register 1                     */
+    __IO uint32_t clk_gate_ctrl2;            /*  0x0148   Dynamic Clock Gating Control Register 2                     */
+} mxc_clkman_regs_t;
+
+/*
+   Register offsets for module CLKMAN.
+*/
+#define MXC_R_CLKMAN_OFFS_CLK_CONFIG                ((uint32_t)0x00000000UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL                  ((uint32_t)0x00000004UL)
+#define MXC_R_CLKMAN_OFFS_INTFL                     ((uint32_t)0x00000008UL)
+#define MXC_R_CLKMAN_OFFS_INTEN                     ((uint32_t)0x0000000CUL)
+#define MXC_R_CLKMAN_OFFS_TRIM_CALC                 ((uint32_t)0x00000010UL)
+#define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL            ((uint32_t)0x00000024UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_0_SYSTEM         ((uint32_t)0x00000040UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_1_GPIO           ((uint32_t)0x00000044UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_2_PT             ((uint32_t)0x00000048UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_3_SPI0           ((uint32_t)0x0000004CUL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_4_SPI1           ((uint32_t)0x00000050UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_5_SPI2           ((uint32_t)0x00000054UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_6_I2CM           ((uint32_t)0x00000058UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_7_I2CS           ((uint32_t)0x0000005CUL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_8_LCD_CHPUMP     ((uint32_t)0x00000060UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_9_PUF            ((uint32_t)0x00000064UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_10_PRNG          ((uint32_t)0x00000068UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_11_WDT0          ((uint32_t)0x0000006CUL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_12_WDT1          ((uint32_t)0x00000070UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_13_RTC_INT_SYNC  ((uint32_t)0x00000074UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_14_DAC0          ((uint32_t)0x00000078UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_15_DAC1          ((uint32_t)0x0000007CUL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_16_DAC2          ((uint32_t)0x00000080UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_17_DAC3          ((uint32_t)0x00000084UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES      ((uint32_t)0x00000100UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA      ((uint32_t)0x00000104UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG     ((uint32_t)0x00000108UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0            ((uint32_t)0x00000140UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1            ((uint32_t)0x00000144UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2            ((uint32_t)0x00000148UL)
+
+/*
+   Field positions and masks for module CLKMAN.
+*/
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS                  0
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE                      ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS                  1
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS                      ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS             2
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE                 ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS               4
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST                   ((uint32_t)(0x0000001FUL << MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS              9
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL                  ((uint32_t)(0x00000007UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS                  12
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE                      ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS                 13
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N                     ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS            14
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT                ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS          16
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS             18
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE                 ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS                  19
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS                      ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS         20
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS               24
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE                   ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS              25
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N                  ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS      28
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT          ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS          1
+#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS              3
+#define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE                  ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS                    4
+#define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N                        ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS                    8
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N                        ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS             9
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT                 ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS                 12
+#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N                     ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS              16
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N                  ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS       17
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT           ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS              20
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N                  ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS       21
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT           ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS                     24
+#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE                         ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS))
+
+#define MXC_F_CLKMAN_INTFL_RING_STABLE_POS                      0
+#define MXC_F_CLKMAN_INTFL_RING_STABLE                          ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_RING_STABLE_POS))
+#define MXC_F_CLKMAN_INTFL_PLL_STABLE_POS                       1
+#define MXC_F_CLKMAN_INTFL_PLL_STABLE                           ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_PLL_STABLE_POS))
+#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS                    2
+#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE                        ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS))
+
+#define MXC_F_CLKMAN_INTEN_RING_STABLE_POS                      0
+#define MXC_F_CLKMAN_INTEN_RING_STABLE                          ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_RING_STABLE_POS))
+#define MXC_F_CLKMAN_INTEN_PLL_STABLE_POS                       1
+#define MXC_F_CLKMAN_INTEN_PLL_STABLE                           ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_PLL_STABLE_POS))
+#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS                    2
+#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE                        ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS))
+
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS                 0
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL                     ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS              1
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START                  ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS          2
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED              ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS                  3
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE                      ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS            16
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS                ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS))
+
+#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS        0
+#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN            ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS        0
+#define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS         0
+#define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS    0
+#define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE        ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS         0
+#define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS         0
+#define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS         0
+#define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS         0
+#define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS         0
+#define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS    0
+#define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE        ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS           0
+#define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE               ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS        0
+#define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS   0
+#define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE       ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS   0
+#define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE       ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE     ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS        0
+#define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS        0
+#define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS        0
+#define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS        0
+#define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS     0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE         ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS    0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE        ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS   0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE       ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS           0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS        2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS        4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS         6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER             ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS          8
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS    10
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER        ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS        12
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS         14
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER             ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS         16
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER             ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS        18
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS        20
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS        22
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS        24
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS     26
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER         ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS     28
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER         ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS           30
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS       0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER           ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS           2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS       4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER           ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS       6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER           ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS        8
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS        10
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS           12
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS           14
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS          16
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS    18
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER        ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS          20
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS          22
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS          24
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS         26
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER             ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS         28
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER             ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS          30
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS           0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS           2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS        4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS           6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_CLKMAN_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis.h

@@ -0,0 +1,40 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "max32600.h"
+#include "cmsis_nvic.h"
+
+#endif

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.c

@@ -0,0 +1,65 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#include "cmsis_nvic.h"
+
+#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_ARM_STD)
+__attribute__((aligned(256)))
+#endif
+#if defined(TOOLCHAIN_IAR)
+#pragma data_alignment=256
+#endif
+static void (*ramVectorTable[MXC_IRQ_COUNT])(void);
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR != (uint32_t)ramVectorTable) {
+        uint32_t *old_vectors = (uint32_t*)SCB->VTOR;
+        vectors = (uint32_t*)ramVectorTable;
+        for (i = 0; i < NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)ramVectorTable;
+    }
+    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.h

@@ -0,0 +1,53 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS      MXC_IRQ_COUNT
+#define NVIC_USER_IRQ_OFFSET  16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBED_CMSIS_NVIC_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/crc_regs.h

@@ -0,0 +1,89 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_CRC_REGS_H_
+#define _MXC_CRC_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  crc_regs.h
+ * @addtogroup crc CRC
+ * @{
+ */
+
+/*                                             Offset   Register Description
+                                               ======   ======================================================= */
+typedef struct {
+    __IO uint32_t reseed;                  /*  0x0000   CRC-16/CRC-32 Reseed Controls                           */
+    __IO uint32_t seed16;                  /*  0x0004   Reseed Value for CRC-16 Calculations                    */
+    __IO uint32_t seed32;                  /*  0x0008   Reseed Value for CRC-32 Calculations                    */
+} mxc_crc_regs_t;
+
+/*                                             Offset   Register Description
+                                               ======   ======================================================= */
+typedef struct {
+    __IO uint32_t value16[512];            /*  0x0000   Write Next CRC-16 Data Value / Read CRC-16 Result Value */
+    __IO uint32_t value32[512];            /*  0x0800   Write Next CRC-32 Data Value / Read CRC-32 Result Value */
+} mxc_crc_data_regs_t;
+
+/*
+   Register offsets for module CRC.
+*/
+#define MXC_R_CRC_OFFS_RESEED           ((uint32_t)0x00000000UL)
+#define MXC_R_CRC_OFFS_SEED16           ((uint32_t)0x00000004UL)
+#define MXC_R_CRC_OFFS_SEED32           ((uint32_t)0x00000008UL)
+#define MXC_R_CRC_DATA_OFFS_VALUE16     ((uint32_t)0x00000000UL)
+#define MXC_R_CRC_DATA_OFFS_VALUE32     ((uint32_t)0x00000800UL)
+
+/*
+   Field positions and masks for module CRC.
+*/
+#define MXC_F_CRC_RESEED_CRC16_POS      0
+#define MXC_F_CRC_RESEED_CRC16          ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC16_POS))
+#define MXC_F_CRC_RESEED_CRC32_POS      1
+#define MXC_F_CRC_RESEED_CRC32          ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC32_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_CRC_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/dac_regs.h

@@ -0,0 +1,180 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_DAC_REGS_H
+#define _MXC_DAC_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  dac_regs.h
+ * @addtogroup dac DAC
+ * @{
+ */
+
+/**
+ * @brief Defines the DAC Operational Modes.
+ */
+typedef enum {
+    /** DAC OpMode FIFO */
+    MXC_E_DAC_OP_MODE_FIFO = 0,
+    /** DAC OpMode Sample Count */
+    MXC_E_DAC_OP_MODE_DACSMPLCNT,
+    /** DAC OpMode DAC_REG Control */
+    MXC_E_DAC_OP_MODE_DAC_REG,
+    /** DAC OpMode Continuous */
+    MXC_E_DAC_OP_MODE_CONTINUOUS
+} mxc_dac_op_mode_t;
+
+/**
+ * @brief Defines the DAC Interpolation Options.
+ */
+typedef enum {
+    /** DAC Interpolation is Disabled */
+    MXC_E_DAC_INTERP_MODE_DISABLED = 0,
+    /** DAC Interpolation 2:1 */
+    MXC_E_DAC_INTERP_MODE_2_TO_1,
+    /** DAC Interpolation 4:1 */
+    MXC_E_DAC_INTERP_MODE_4_TO_1,
+    /** DAC Interpolation 8:1 */
+    MXC_E_DAC_INTERP_MODE_8_TO_1
+} mxc_dac_interp_mode_t;
+
+/**
+ * @brief Defines the DAC Start Modes.
+ */
+typedef enum {
+    /** Start on FIFO Not Empty */
+    MXC_E_DAC_START_MODE_FIFO_NOT_EMPTY = 0,
+    /** Start on ADC generated Start Strobe */
+    MXC_E_DAC_START_MODE_ADC_STROBE,
+    /** Start on DAC generated Start Strobe */
+    MXC_E_DAC_START_MODE_DAC_STROBE
+} mxc_dac_start_mode_t;
+
+/*                                                  Offset   Register Description
+                                                    ======   ================================================== */
+typedef struct {
+    __IO uint32_t ctrl0;                        /*  0x0000   DAC Control Register 0                             */
+    __IO uint32_t rate;                         /*  0x0004   DAC Output Rate Control                            */
+    __IO uint32_t ctrl1_int;                    /*  0x0008   DAC Control Register 1, Interrupt Flags and Enable */
+    __IO uint32_t reg;                          /*  0x000C   DAC Data Register                                  */
+    __IO uint32_t trm;                          /*  0x0010   DAC Trim Register */
+} mxc_dac_regs_t;
+
+/*                                                  Offset   Register Description
+                                                    ======   ================================================== */
+typedef struct {
+    union {
+        __IO uint8_t output_8;                  /*  0x0000   Write to push values to DAC output FIFO            */
+        __IO uint16_t output_16;                /*  0x0000   Write to push values to DAC output FIFO            */
+    };
+} mxc_dac_fifo_t;
+
+/*
+   Register offsets for module DAC12.
+*/
+#define MXC_R_DAC_OFFS_CTRL0                    ((uint32_t)0x00000000UL)
+#define MXC_R_DAC_OFFS_RATE                     ((uint32_t)0x00000004UL)
+#define MXC_R_DAC_OFFS_CTRL1_INT                ((uint32_t)0x00000008UL)
+#define MXC_R_DAC_FIFO_OFFS_OUTPUT              ((uint32_t)0x00000000UL)
+
+/*
+   Field positions and masks for module DAC.
+*/
+#define MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS         0
+#define MXC_F_DAC_CTRL0_FIFO_AE_CNT             ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS))
+#define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS    5
+#define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL        ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS))
+#define MXC_F_DAC_CTRL0_FIFO_EMPTY_POS          6
+#define MXC_F_DAC_CTRL0_FIFO_EMPTY              ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_EMPTY_POS))
+#define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS   7
+#define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY       ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS))
+#define MXC_F_DAC_CTRL0_INTERP_MODE_POS         8
+#define MXC_F_DAC_CTRL0_INTERP_MODE             ((uint32_t)(0x00000007UL << MXC_F_DAC_CTRL0_INTERP_MODE_POS))
+#define MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS         12
+#define MXC_F_DAC_CTRL0_FIFO_AF_CNT             ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS))
+#define MXC_F_DAC_CTRL0_START_MODE_POS          16
+#define MXC_F_DAC_CTRL0_START_MODE              ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_START_MODE_POS))
+#define MXC_F_DAC_CTRL0_CPU_START_POS           20
+#define MXC_F_DAC_CTRL0_CPU_START               ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CPU_START_POS))
+#define MXC_F_DAC_CTRL0_OP_MODE_POS             24
+#define MXC_F_DAC_CTRL0_OP_MODE                 ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_OP_MODE_POS))
+#define MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS      26
+#define MXC_F_DAC_CTRL0_POWER_MODE_1_0          ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS))
+#define MXC_F_DAC_CTRL0_POWER_ON_POS            28
+#define MXC_F_DAC_CTRL0_POWER_ON                ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_ON_POS))
+#define MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS       29
+#define MXC_F_DAC_CTRL0_CLOCK_GATE_EN           ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS))
+#define MXC_F_DAC_CTRL0_POWER_MODE_2_POS        30
+#define MXC_F_DAC_CTRL0_POWER_MODE_2            ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_MODE_2_POS))
+#define MXC_F_DAC_CTRL0_RESET_POS               31
+#define MXC_F_DAC_CTRL0_RESET                   ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_RESET_POS))
+
+#define MXC_F_DAC_RATE_RATE_CNT_POS             0
+#define MXC_F_DAC_RATE_RATE_CNT                 ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_RATE_CNT_POS))
+#define MXC_F_DAC_RATE_SAMPLE_CNT_POS           16
+#define MXC_F_DAC_RATE_SAMPLE_CNT               ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_SAMPLE_CNT_POS))
+
+#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS     0
+#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF         ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS))
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS    1
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF        ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS))
+#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS 2
+#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF     ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS))
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS       3
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW           ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS))
+#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS     16
+#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE         ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS))
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS    17
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE        ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS))
+#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS 18
+#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE     ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS))
+#define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS  28
+#define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE      ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS))
+#define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS  29
+#define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE      ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _DAC12_REGS_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/flc_regs.h

@@ -0,0 +1,210 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_FLC_REGS_H
+#define _MXC_FLC_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  flc_regs.h
+ * @addtogroup flc FLC
+ * @{
+ */
+/*                                          Offset   Register Description
+                                            ======   ======================================================= */
+typedef struct {
+    __IO uint32_t faddr;                /*  0x0000   Flash Operation Address                                 */
+    __IO uint32_t fckdiv;               /*  0x0004   Flash Clock Rate Divisor                                */
+    __IO uint32_t ctrl;                 /*  0x0008   Flash Control Register                                  */
+    __I uint32_t rsv000C[6];            /*  0x000C                                                           */
+    __IO uint32_t intr;                 /*  0x0024   Flash Controller Interrupt Flags and Enable/Disable 0   */
+    __I uint32_t rsv0028[2];            /*  0x0028                                                           */
+    __IO uint32_t fdata;                /*  0x0030   Flash Operation Data Register                           */
+    __I uint32_t rsv0034[7];            /*  0x0034                                                           */
+    __IO uint32_t perform;              /*  0x0050   Flash Performance Settings                              */
+    __I uint32_t rsv0054[11];           /*  0x0054                                                           */
+    __IO uint32_t status;               /*  0x0080   Security Status Flags                                   */
+    __I uint32_t rsv0084;               /*  0x0084                                                           */
+    __IO uint32_t security;             /*  0x0088   Flash Controller Security Settings                      */
+    __I uint32_t rsv008C[4];            /*  0x008C                                                           */
+    __IO uint32_t bypass;               /*  0x009C   Status Flags for DSB Operations                         */
+    __IO uint32_t user_option;          /*  0x0100   Used to set DSB Access code and Auto-Lock in info block */
+    __I uint32_t rsv0104[15];           /*  0x0104                                                           */
+    __IO uint32_t ctrl2;                /*  0x0140   Flash Control Register 2                                */
+    __IO uint32_t intfl1;               /*  0x0144   Interrupt Flags Register 1                              */
+    __IO uint32_t inten1;               /*  0x0148   Interrupt Enable/Disable Register 1                     */
+    __I uint32_t rsv014C;               /*  0x014C                                                           */
+    __IO uint32_t disable_xr0;          /*  0x0150   Disable Flash Page Exec/Read Register 0                 */
+    __IO uint32_t disable_xr1;          /*  0x0154   Disable Flash Page Exec/Read Register 1                 */
+    __IO uint32_t disable_xr2;          /*  0x0158   Disable Flash Page Exec/Read Register 2                 */
+    __IO uint32_t disable_xr3;          /*  0x015C   Disable Flash Page Exec/Read Register 3                 */
+    __IO uint32_t disable_we0;          /*  0x0160   Disable Flash Page Write/Erase Register 0               */
+    __IO uint32_t disable_we1;          /*  0x0164   Disable Flash Page Write/Erase Register 1               */
+    __IO uint32_t disable_we2;          /*  0x0168   Disable Flash Page Write/Erase Register 2               */
+    __IO uint32_t disable_we3;          /*  0x016C   Disable Flash Page Write/Erase Register 3               */
+} mxc_flc_regs_t;
+
+/*
+   Register offsets for module FLC.
+*/
+#define MXC_R_FLC_OFFS_FADDR                          ((uint32_t)0x00000000UL)
+#define MXC_R_FLC_OFFS_FCKDIV                         ((uint32_t)0x00000004UL)
+#define MXC_R_FLC_OFFS_CTRL                           ((uint32_t)0x00000008UL)
+#define MXC_R_FLC_OFFS_INTR                           ((uint32_t)0x00000024UL)
+#define MXC_R_FLC_OFFS_FDATA                          ((uint32_t)0x00000030UL)
+#define MXC_R_FLC_OFFS_PERFORM                        ((uint32_t)0x00000050UL)
+#define MXC_R_FLC_OFFS_STATUS                         ((uint32_t)0x00000080UL)
+#define MXC_R_FLC_OFFS_SECURITY                       ((uint32_t)0x00000088UL)
+#define MXC_R_FLC_OFFS_BYPASS                         ((uint32_t)0x0000009CUL)
+#define MXC_R_FLC_OFFS_USER_OPTION                    ((uint32_t)0x00000100UL)
+#define MXC_R_FLC_OFFS_CTRL2                          ((uint32_t)0x00000140UL)
+#define MXC_R_FLC_OFFS_INTFL1                         ((uint32_t)0x00000144UL)
+#define MXC_R_FLC_OFFS_INTEN1                         ((uint32_t)0x00000148UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR0                    ((uint32_t)0x00000150UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR1                    ((uint32_t)0x00000154UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR2                    ((uint32_t)0x00000158UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR3                    ((uint32_t)0x0000015CUL)
+#define MXC_R_FLC_OFFS_DISABLE_WE0                    ((uint32_t)0x00000160UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE1                    ((uint32_t)0x00000164UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE2                    ((uint32_t)0x00000168UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE3                    ((uint32_t)0x0000016CUL)
+
+#define MXC_V_FLC_ERASE_CODE_PAGE_ERASE               ((uint8_t)0x55)
+#define MXC_V_FLC_ERASE_CODE_MASS_ERASE               ((uint8_t)0xAA)
+
+#define MXC_V_FLC_FLSH_UNLOCK_KEY                     ((uint8_t)0x2)
+
+/*
+   Field positions and masks for module FLC.
+*/
+#define MXC_F_FLC_FADDR_FADDR_POS                     0
+#define MXC_F_FLC_FADDR_FADDR                         ((uint32_t)(0x0003FFFFUL << MXC_F_FLC_FADDR_FADDR_POS))
+
+#define MXC_F_FLC_FCKDIV_FCKDIV_POS                   0
+#define MXC_F_FLC_FCKDIV_FCKDIV                       ((uint32_t)(0x0000001FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS))
+
+#define MXC_F_FLC_CTRL_WRITE_POS                      0
+#define MXC_F_FLC_CTRL_WRITE                          ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS))
+#define MXC_F_FLC_CTRL_MASS_ERASE_POS                 1
+#define MXC_F_FLC_CTRL_MASS_ERASE                     ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS))
+#define MXC_F_FLC_CTRL_PAGE_ERASE_POS                 2
+#define MXC_F_FLC_CTRL_PAGE_ERASE                     ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS))
+#define MXC_F_FLC_CTRL_ERASE_CODE_POS                 8
+#define MXC_F_FLC_CTRL_ERASE_CODE                     ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS))
+#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS          16
+#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK              ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS))
+#define MXC_F_FLC_CTRL_WRITE_ENABLE_POS               17
+#define MXC_F_FLC_CTRL_WRITE_ENABLE                   ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS))
+#define MXC_F_FLC_CTRL_PENDING_POS                    24
+#define MXC_F_FLC_CTRL_PENDING                        ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS))
+#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS           25
+#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID               ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS))
+#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS            27
+#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE                ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS))
+#define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS                28
+#define MXC_F_FLC_CTRL_FLSH_UNLOCK                    ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS))
+
+#define MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS           0
+#define MXC_F_FLC_INTR_FLASH_OP_DONE_IF               ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS))
+#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS         1
+#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF             ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS))
+#define MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS           9
+#define MXC_F_FLC_INTR_FLASH_OP_DONE_IE               ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS))
+#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS         10
+#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE             ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS))
+
+#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS       8
+#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN           ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS))
+#define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS             0
+#define MXC_F_FLC_PERFORM_DELAY_SE_EN                 ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS))
+
+#define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS        0
+#define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW            ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS))
+#define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS        1
+#define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC            ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS))
+#define MXC_F_FLC_STATUS_AUTO_LOCK_POS                3
+#define MXC_F_FLC_STATUS_AUTO_LOCK                    ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS))
+
+#define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS          0
+#define MXC_F_FLC_SECURITY_DEBUG_DISABLE              ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS))
+#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS        8
+#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK            ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS))
+#define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS          31
+#define MXC_F_FLC_SECURITY_SECURITY_LOCK              ((uint32_t)(0x00000001UL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS))
+
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS    0
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE        ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS))
+#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS          1
+#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE              ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS))
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE     ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS))
+#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS       3
+#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE           ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS))
+
+#define MXC_F_FLC_CTRL2_FLASH_LVE_POS                 0
+#define MXC_F_FLC_CTRL2_FLASH_LVE                     ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_FLASH_LVE_POS))
+#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS           8
+#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL               ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS))
+
+#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS        0
+#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED            ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS))
+#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS       1
+#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR           ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS))
+#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS        2
+#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED            ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS))
+#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS         3
+#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE             ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS))
+
+#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS        0
+#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED            ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS))
+#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS       1
+#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR           ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS))
+#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS        2
+#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED            ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS))
+#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS         3
+#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE             ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_FLC_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/gpio_regs.h

@@ -0,0 +1,477 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_GPIO_REGS_H_
+#define _MXC_GPIO_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  gpio_regs.h
+ * @addtogroup gpio GPIO
+ * @{
+ */
+
+/*                                             Offset          Register Description
+                                            =============   ========================================== */
+typedef struct {
+    __I uint32_t rsv000[16];            /*  0x0000-0x003C                                              */
+
+    __IO uint32_t free[8];              /*  0x0040-0x005C   Port P[0..7] Free for GPIO Operation Flags */
+    __I uint32_t rsv060[8];             /*  0x0060-0x007C                                              */
+
+    __IO uint32_t out_mode[8];          /*  0x0080-0x009C   Port P[0..7] GPIO Output Drive Mode        */
+    __I uint32_t rsv0A0[8];             /*  0x00A0-0x00BC                                              */
+
+    __IO uint32_t out_val[8];           /*  0x00C0-0x00DC   Port P[0..7] GPIO Output Value             */
+    __I uint32_t rsv0E0[8];             /*  0x00E0-0x00FC                                              */
+
+    __IO uint32_t func_sel[8];          /*  0x0100-0x011C   Port P[0..7] GPIO Function Select          */
+    __I uint32_t rsv120[8];             /*  0x0120-0x013C                                              */
+
+    __IO uint32_t in_mode[8];           /*  0x0140-0x015C   Port P[0..7] GPIO Input Monitoring Mode    */
+    __I uint32_t rsv160[8];             /*  0x0160-0x017C                                              */
+
+    __IO uint32_t in_val[8];            /*  0x0180-0x019C   Port P[0..7] GPIO Input Value              */
+    __I uint32_t rsv1A0[8];             /*  0x01A0-0x01BC                                              */
+
+    __IO uint32_t int_mode[8];          /*  0x01C0-0x01DC   Port P[0..7] Interrupt Detection Mode      */
+    __I uint32_t rsv1E0[8];             /*  0x01E0-0x01FC                                              */
+
+    __IO uint32_t intfl[8];             /*  0x0200-0x021C   Port P[0..7] Interrupt Flags               */
+    __I uint32_t rsv220[8];             /*  0x0220-0x023C                                              */
+
+    __IO uint32_t inten[8];             /*  0x0240-0x025C   Port P[0..7] Interrupt Enables             */
+} mxc_gpio_regs_t;
+
+/*
+   Register offsets for module GPIO.
+*/
+#define MXC_R_GPIO_OFFS_FREE_P0                   ((uint32_t)0x00000040UL)
+#define MXC_R_GPIO_OFFS_FREE_P1                   ((uint32_t)0x00000044UL)
+#define MXC_R_GPIO_OFFS_FREE_P2                   ((uint32_t)0x00000048UL)
+#define MXC_R_GPIO_OFFS_FREE_P3                   ((uint32_t)0x0000004CUL)
+#define MXC_R_GPIO_OFFS_FREE_P4                   ((uint32_t)0x00000050UL)
+#define MXC_R_GPIO_OFFS_FREE_P5                   ((uint32_t)0x00000054UL)
+#define MXC_R_GPIO_OFFS_FREE_P6                   ((uint32_t)0x00000058UL)
+#define MXC_R_GPIO_OFFS_FREE_P7                   ((uint32_t)0x0000005CUL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P0               ((uint32_t)0x00000080UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P1               ((uint32_t)0x00000084UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P2               ((uint32_t)0x00000088UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P3               ((uint32_t)0x0000008CUL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P4               ((uint32_t)0x00000090UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P5               ((uint32_t)0x00000094UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P6               ((uint32_t)0x00000098UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P7               ((uint32_t)0x0000009CUL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P0                ((uint32_t)0x000000C0UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P1                ((uint32_t)0x000000C4UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P2                ((uint32_t)0x000000C8UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P3                ((uint32_t)0x000000CCUL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P4                ((uint32_t)0x000000D0UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P5                ((uint32_t)0x000000D4UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P6                ((uint32_t)0x000000D8UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P7                ((uint32_t)0x000000DCUL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P0               ((uint32_t)0x00000100UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P1               ((uint32_t)0x00000104UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P2               ((uint32_t)0x00000108UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P6               ((uint32_t)0x00000118UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P7               ((uint32_t)0x0000011CUL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P0                ((uint32_t)0x00000140UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P1                ((uint32_t)0x00000144UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P2                ((uint32_t)0x00000148UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P3                ((uint32_t)0x0000014CUL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P4                ((uint32_t)0x00000150UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P5                ((uint32_t)0x00000154UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P6                ((uint32_t)0x00000158UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P7                ((uint32_t)0x0000015CUL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P0                 ((uint32_t)0x00000180UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P1                 ((uint32_t)0x00000184UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P2                 ((uint32_t)0x00000188UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P3                 ((uint32_t)0x0000018CUL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P4                 ((uint32_t)0x00000190UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P5                 ((uint32_t)0x00000194UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P6                 ((uint32_t)0x00000198UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P7                 ((uint32_t)0x0000019CUL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P0               ((uint32_t)0x000001C0UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P1               ((uint32_t)0x000001C4UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P2               ((uint32_t)0x000001C8UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P3               ((uint32_t)0x000001CCUL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P4               ((uint32_t)0x000001D0UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P5               ((uint32_t)0x000001D4UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P6               ((uint32_t)0x000001D8UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P7               ((uint32_t)0x000001DCUL)
+#define MXC_R_GPIO_OFFS_INTFL_P0                  ((uint32_t)0x00000200UL)
+#define MXC_R_GPIO_OFFS_INTFL_P1                  ((uint32_t)0x00000204UL)
+#define MXC_R_GPIO_OFFS_INTFL_P2                  ((uint32_t)0x00000208UL)
+#define MXC_R_GPIO_OFFS_INTFL_P3                  ((uint32_t)0x0000020CUL)
+#define MXC_R_GPIO_OFFS_INTFL_P4                  ((uint32_t)0x00000210UL)
+#define MXC_R_GPIO_OFFS_INTFL_P5                  ((uint32_t)0x00000214UL)
+#define MXC_R_GPIO_OFFS_INTFL_P6                  ((uint32_t)0x00000218UL)
+#define MXC_R_GPIO_OFFS_INTFL_P7                  ((uint32_t)0x0000021CUL)
+#define MXC_R_GPIO_OFFS_INTEN_P0                  ((uint32_t)0x00000240UL)
+#define MXC_R_GPIO_OFFS_INTEN_P1                  ((uint32_t)0x00000244UL)
+#define MXC_R_GPIO_OFFS_INTEN_P2                  ((uint32_t)0x00000248UL)
+#define MXC_R_GPIO_OFFS_INTEN_P3                  ((uint32_t)0x0000024CUL)
+#define MXC_R_GPIO_OFFS_INTEN_P4                  ((uint32_t)0x00000250UL)
+#define MXC_R_GPIO_OFFS_INTEN_P5                  ((uint32_t)0x00000254UL)
+#define MXC_R_GPIO_OFFS_INTEN_P6                  ((uint32_t)0x00000258UL)
+#define MXC_R_GPIO_OFFS_INTEN_P7                  ((uint32_t)0x0000025CUL)
+
+
+/*
+   Field positions and masks for module GPIO.
+*/
+#define MXC_F_GPIO_FREE_PIN0_POS                             0
+#define MXC_F_GPIO_FREE_PIN0                                ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS))
+#define MXC_F_GPIO_FREE_PIN1_POS                             1
+#define MXC_F_GPIO_FREE_PIN1                                ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS))
+#define MXC_F_GPIO_FREE_PIN2_POS                             2
+#define MXC_F_GPIO_FREE_PIN2                                ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS))
+#define MXC_F_GPIO_FREE_PIN3_POS                             3
+#define MXC_F_GPIO_FREE_PIN3                                ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS))
+#define MXC_F_GPIO_FREE_PIN4_POS                             4
+#define MXC_F_GPIO_FREE_PIN4                                ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS))
+#define MXC_F_GPIO_FREE_PIN5_POS                             5
+#define MXC_F_GPIO_FREE_PIN5                                ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS))
+#define MXC_F_GPIO_FREE_PIN6_POS                             6
+#define MXC_F_GPIO_FREE_PIN6                                ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS))
+#define MXC_F_GPIO_FREE_PIN7_POS                             7
+#define MXC_F_GPIO_FREE_PIN7                                ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS))
+
+#define MXC_F_GPIO_OUT_MODE_PIN0_POS                         0
+#define MXC_F_GPIO_OUT_MODE_PIN0                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN1_POS                         4
+#define MXC_F_GPIO_OUT_MODE_PIN1                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN2_POS                         8
+#define MXC_F_GPIO_OUT_MODE_PIN2                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN3_POS                        12
+#define MXC_F_GPIO_OUT_MODE_PIN3                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN4_POS                        16
+#define MXC_F_GPIO_OUT_MODE_PIN4                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN5_POS                        20
+#define MXC_F_GPIO_OUT_MODE_PIN5                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN6_POS                        24
+#define MXC_F_GPIO_OUT_MODE_PIN6                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN7_POS                        28
+#define MXC_F_GPIO_OUT_MODE_PIN7                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+
+#define MXC_F_GPIO_OUT_VAL_PIN0_POS                          0
+#define MXC_F_GPIO_OUT_VAL_PIN0                             ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN1_POS                          1
+#define MXC_F_GPIO_OUT_VAL_PIN1                             ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN2_POS                          2
+#define MXC_F_GPIO_OUT_VAL_PIN2                             ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN3_POS                          3
+#define MXC_F_GPIO_OUT_VAL_PIN3                             ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN4_POS                          4
+#define MXC_F_GPIO_OUT_VAL_PIN4                             ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN5_POS                          5
+#define MXC_F_GPIO_OUT_VAL_PIN5                             ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN6_POS                          6
+#define MXC_F_GPIO_OUT_VAL_PIN6                             ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN7_POS                          7
+#define MXC_F_GPIO_OUT_VAL_PIN7                             ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS))
+
+#define MXC_F_GPIO_FUNC_SEL_PIN0_POS                         0
+#define MXC_F_GPIO_FUNC_SEL_PIN0                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN1_POS                         4
+#define MXC_F_GPIO_FUNC_SEL_PIN1                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN2_POS                         8
+#define MXC_F_GPIO_FUNC_SEL_PIN2                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN3_POS                        12
+#define MXC_F_GPIO_FUNC_SEL_PIN3                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN4_POS                        16
+#define MXC_F_GPIO_FUNC_SEL_PIN4                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN5_POS                        20
+#define MXC_F_GPIO_FUNC_SEL_PIN5                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN6_POS                        24
+#define MXC_F_GPIO_FUNC_SEL_PIN6                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN7_POS                        28
+#define MXC_F_GPIO_FUNC_SEL_PIN7                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS))
+
+#define MXC_F_GPIO_IN_MODE_PIN0_POS                          0
+#define MXC_F_GPIO_IN_MODE_PIN0                             ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS))
+#define MXC_F_GPIO_IN_MODE_PIN1_POS                          4
+#define MXC_F_GPIO_IN_MODE_PIN1                             ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS))
+#define MXC_F_GPIO_IN_MODE_PIN2_POS                          8
+#define MXC_F_GPIO_IN_MODE_PIN2                             ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS))
+#define MXC_F_GPIO_IN_MODE_PIN3_POS                         12
+#define MXC_F_GPIO_IN_MODE_PIN3                             ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS))
+#define MXC_F_GPIO_IN_MODE_PIN4_POS                         16
+#define MXC_F_GPIO_IN_MODE_PIN4                             ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS))
+#define MXC_F_GPIO_IN_MODE_PIN5_POS                         20
+#define MXC_F_GPIO_IN_MODE_PIN5                             ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS))
+#define MXC_F_GPIO_IN_MODE_PIN6_POS                         24
+#define MXC_F_GPIO_IN_MODE_PIN6                             ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS))
+#define MXC_F_GPIO_IN_MODE_PIN7_POS                         28
+#define MXC_F_GPIO_IN_MODE_PIN7                             ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS))
+
+#define MXC_F_GPIO_IN_VAL_PIN0_POS                           0
+#define MXC_F_GPIO_IN_VAL_PIN0                              ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS))
+#define MXC_F_GPIO_IN_VAL_PIN1_POS                           1
+#define MXC_F_GPIO_IN_VAL_PIN1                              ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS))
+#define MXC_F_GPIO_IN_VAL_PIN2_POS                           2
+#define MXC_F_GPIO_IN_VAL_PIN2                              ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS))
+#define MXC_F_GPIO_IN_VAL_PIN3_POS                           3
+#define MXC_F_GPIO_IN_VAL_PIN3                              ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS))
+#define MXC_F_GPIO_IN_VAL_PIN4_POS                           4
+#define MXC_F_GPIO_IN_VAL_PIN4                              ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS))
+#define MXC_F_GPIO_IN_VAL_PIN5_POS                           5
+#define MXC_F_GPIO_IN_VAL_PIN5                              ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS))
+#define MXC_F_GPIO_IN_VAL_PIN6_POS                           6
+#define MXC_F_GPIO_IN_VAL_PIN6                              ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS))
+#define MXC_F_GPIO_IN_VAL_PIN7_POS                           7
+#define MXC_F_GPIO_IN_VAL_PIN7                              ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS))
+
+#define MXC_F_GPIO_INT_MODE_PIN0_POS                         0
+#define MXC_F_GPIO_INT_MODE_PIN0                            ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS))
+#define MXC_F_GPIO_INT_MODE_PIN1_POS                         4
+#define MXC_F_GPIO_INT_MODE_PIN1                            ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS))
+#define MXC_F_GPIO_INT_MODE_PIN2_POS                         8
+#define MXC_F_GPIO_INT_MODE_PIN2                            ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS))
+#define MXC_F_GPIO_INT_MODE_PIN3_POS                        12
+#define MXC_F_GPIO_INT_MODE_PIN3                            ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS))
+#define MXC_F_GPIO_INT_MODE_PIN4_POS                        16
+#define MXC_F_GPIO_INT_MODE_PIN4                            ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS))
+#define MXC_F_GPIO_INT_MODE_PIN5_POS                        20
+#define MXC_F_GPIO_INT_MODE_PIN5                            ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS))
+#define MXC_F_GPIO_INT_MODE_PIN6_POS                        24
+#define MXC_F_GPIO_INT_MODE_PIN6                            ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS))
+#define MXC_F_GPIO_INT_MODE_PIN7_POS                        28
+#define MXC_F_GPIO_INT_MODE_PIN7                            ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS))
+
+#define MXC_F_GPIO_INTFL_PIN0_POS                            0
+#define MXC_F_GPIO_INTFL_PIN0                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS))
+#define MXC_F_GPIO_INTFL_PIN1_POS                            1
+#define MXC_F_GPIO_INTFL_PIN1                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS))
+#define MXC_F_GPIO_INTFL_PIN2_POS                            2
+#define MXC_F_GPIO_INTFL_PIN2                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS))
+#define MXC_F_GPIO_INTFL_PIN3_POS                            3
+#define MXC_F_GPIO_INTFL_PIN3                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS))
+#define MXC_F_GPIO_INTFL_PIN4_POS                            4
+#define MXC_F_GPIO_INTFL_PIN4                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS))
+#define MXC_F_GPIO_INTFL_PIN5_POS                            5
+#define MXC_F_GPIO_INTFL_PIN5                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS))
+#define MXC_F_GPIO_INTFL_PIN6_POS                            6
+#define MXC_F_GPIO_INTFL_PIN6                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS))
+#define MXC_F_GPIO_INTFL_PIN7_POS                            7
+#define MXC_F_GPIO_INTFL_PIN7                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS))
+
+#define MXC_F_GPIO_INTEN_PIN0_POS                            0
+#define MXC_F_GPIO_INTEN_PIN0                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS))
+#define MXC_F_GPIO_INTEN_PIN1_POS                            1
+#define MXC_F_GPIO_INTEN_PIN1                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS))
+#define MXC_F_GPIO_INTEN_PIN2_POS                            2
+#define MXC_F_GPIO_INTEN_PIN2                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS))
+#define MXC_F_GPIO_INTEN_PIN3_POS                            3
+#define MXC_F_GPIO_INTEN_PIN3                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS))
+#define MXC_F_GPIO_INTEN_PIN4_POS                            4
+#define MXC_F_GPIO_INTEN_PIN4                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS))
+#define MXC_F_GPIO_INTEN_PIN5_POS                            5
+#define MXC_F_GPIO_INTEN_PIN5                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS))
+#define MXC_F_GPIO_INTEN_PIN6_POS                            6
+#define MXC_F_GPIO_INTEN_PIN6                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS))
+#define MXC_F_GPIO_INTEN_PIN7_POS                            7
+#define MXC_F_GPIO_INTEN_PIN7                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS))
+
+
+/*
+   Field values and shifted values for module GPIO.
+*/
+#define MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE                                      ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN0_AVAILABLE                                          ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN0_NOT_AVAILABLE                                      ((uint32_t)(MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE  << MXC_F_GPIO_FREE_PIN0_POS))
+#define MXC_S_GPIO_FREE_PIN0_AVAILABLE                                          ((uint32_t)(MXC_V_GPIO_FREE_PIN0_AVAILABLE      << MXC_F_GPIO_FREE_PIN0_POS))
+
+#define MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE                                      ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN1_AVAILABLE                                          ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN1_NOT_AVAILABLE                                      ((uint32_t)(MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE  << MXC_F_GPIO_FREE_PIN1_POS))
+#define MXC_S_GPIO_FREE_PIN1_AVAILABLE                                          ((uint32_t)(MXC_V_GPIO_FREE_PIN1_AVAILABLE      << MXC_F_GPIO_FREE_PIN1_POS))
+
+#define MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE                                      ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN2_AVAILABLE                                          ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN2_NOT_AVAILABLE                                      ((uint32_t)(MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE  << MXC_F_GPIO_FREE_PIN2_POS))
+#define MXC_S_GPIO_FREE_PIN2_AVAILABLE                                          ((uint32_t)(MXC_V_GPIO_FREE_PIN2_AVAILABLE      << MXC_F_GPIO_FREE_PIN2_POS))
+
+#define MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE                                      ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN3_AVAILABLE                                          ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN3_NOT_AVAILABLE                                      ((uint32_t)(MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE  << MXC_F_GPIO_FREE_PIN3_POS))
+#define MXC_S_GPIO_FREE_PIN3_AVAILABLE                                          ((uint32_t)(MXC_V_GPIO_FREE_PIN3_AVAILABLE      << MXC_F_GPIO_FREE_PIN3_POS))
+
+#define MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE                                      ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN4_AVAILABLE                                          ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN4_NOT_AVAILABLE                                      ((uint32_t)(MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE  << MXC_F_GPIO_FREE_PIN4_POS))
+#define MXC_S_GPIO_FREE_PIN4_AVAILABLE                                          ((uint32_t)(MXC_V_GPIO_FREE_PIN4_AVAILABLE      << MXC_F_GPIO_FREE_PIN4_POS))
+
+#define MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE                                      ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN5_AVAILABLE                                          ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN5_NOT_AVAILABLE                                      ((uint32_t)(MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE  << MXC_F_GPIO_FREE_PIN5_POS))
+#define MXC_S_GPIO_FREE_PIN5_AVAILABLE                                          ((uint32_t)(MXC_V_GPIO_FREE_PIN5_AVAILABLE      << MXC_F_GPIO_FREE_PIN5_POS))
+
+#define MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE                                      ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN6_AVAILABLE                                          ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN6_NOT_AVAILABLE                                      ((uint32_t)(MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE  << MXC_F_GPIO_FREE_PIN6_POS))
+#define MXC_S_GPIO_FREE_PIN6_AVAILABLE                                          ((uint32_t)(MXC_V_GPIO_FREE_PIN6_AVAILABLE      << MXC_F_GPIO_FREE_PIN6_POS))
+
+#define MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE                                      ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN7_AVAILABLE                                          ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN7_NOT_AVAILABLE                                      ((uint32_t)(MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE  << MXC_F_GPIO_FREE_PIN7_POS))
+#define MXC_S_GPIO_FREE_PIN7_AVAILABLE                                          ((uint32_t)(MXC_V_GPIO_FREE_PIN7_AVAILABLE      << MXC_F_GPIO_FREE_PIN7_POS))
+
+#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP                                  ((uint32_t)(0x00000000UL))
+#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN                                          ((uint32_t)(0x00000001UL))
+#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP                              ((uint32_t)(0x00000002UL))
+#define MXC_V_GPIO_OUT_MODE_HIGH_Z                                              ((uint32_t)(0x00000003UL))
+#define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z                                       ((uint32_t)(0x00000004UL))
+#define MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE                                        ((uint32_t)(0x00000005UL))
+#define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z                                         ((uint32_t)(0x00000006UL))
+#define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE                                          ((uint32_t)(0x00000007UL))
+#define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z                                         ((uint32_t)(0x00000008UL))
+#define MXC_V_GPIO_OUT_MODE_FAST_DRIVE                                          ((uint32_t)(0x00000009UL))
+
+#define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z_WEAK_PULLUP                             ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP      << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN              << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN_WEAK_PULLUP                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP  << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z                                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z                  << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_HIGH_Z                                  ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z           << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_DRIVE                                   ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE            << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_FAST_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_FAST_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z_WEAK_PULLUP                             ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP      << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN              << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN_WEAK_PULLUP                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP  << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z                                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z                  << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_HIGH_Z                                  ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z           << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_DRIVE                                   ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE            << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_FAST_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_FAST_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z_WEAK_PULLUP                             ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP      << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN              << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN_WEAK_PULLUP                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP  << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z                                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z                  << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_HIGH_Z                                  ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z           << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_DRIVE                                   ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE            << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_FAST_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_FAST_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z_WEAK_PULLUP                             ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP      << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN              << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN_WEAK_PULLUP                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP  << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z                                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z                  << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_HIGH_Z                                  ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z           << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_DRIVE                                   ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE            << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_FAST_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_FAST_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z_WEAK_PULLUP                             ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP      << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN              << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN_WEAK_PULLUP                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP  << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z                                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z                  << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_HIGH_Z                                  ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z           << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_DRIVE                                   ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE            << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_FAST_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_FAST_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z_WEAK_PULLUP                             ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP      << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN              << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN_WEAK_PULLUP                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP  << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z                                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z                  << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_HIGH_Z                                  ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z           << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_DRIVE                                   ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE            << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_FAST_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_FAST_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z_WEAK_PULLUP                             ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP      << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN              << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN_WEAK_PULLUP                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP  << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z                                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z                  << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_HIGH_Z                                  ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z           << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_DRIVE                                   ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE            << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_FAST_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_FAST_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z_WEAK_PULLUP                             ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP      << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN              << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN_WEAK_PULLUP                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP  << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z                                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z                  << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_HIGH_Z                                  ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z           << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_DRIVE                                   ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE            << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_FAST_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_FAST_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+
+#define MXC_V_GPIO_INT_MODE_DISABLED                                            ((uint32_t)(0x00000000UL))
+#define MXC_V_GPIO_INT_MODE_FALLING_EDGE                                        ((uint32_t)(0x00000001UL))
+#define MXC_V_GPIO_INT_MODE_RISING_EDGE                                         ((uint32_t)(0x00000002UL))
+#define MXC_V_GPIO_INT_MODE_BOTH_EDGES                                          ((uint32_t)(0x00000003UL))
+#define MXC_V_GPIO_INT_MODE_LOW_LEVEL                                           ((uint32_t)(0x00000004UL))
+#define MXC_V_GPIO_INT_MODE_HIGH_LEVEL                                          ((uint32_t)(0x00000005UL))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_GPIO_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/i2cm_regs.h

@@ -0,0 +1,192 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_I2CM_REGS_H_
+#define _MXC_I2CM_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  i2cm_regs.h
+ * @addtogroup i2cm I2CM
+ * @{
+ */
+
+/*                                      Offset   Register Description
+                                        ======   ================================================ */
+typedef struct {
+    __IO uint32_t fs_clk_div;       /*  0x0000   Full Speed SCL Clock Settings                    */
+    __IO uint32_t hs_clk_div;       /*  0x0004   High Speed SCL Clock Settings                    */
+    __I uint32_t rsv0008;           /*  0x0008                                                    */
+    __IO uint32_t timeout;          /*  0x000C   [TO_CNTL] Timeout and Auto-Stop Settings         */
+    __IO uint32_t ctrl;             /*  0x0010   [EN_CNTL] I2C Master Control Register            */
+    __IO uint32_t trans;            /*  0x0014   [MSTR_CNTL] I2C Master Tx Start and Status Flags */
+    __IO uint32_t intfl;            /*  0x0018   Interrupt Flags                                  */
+    __IO uint32_t inten;            /*  0x001C   Interrupt Enable/Disable Controls                */
+    __I uint32_t rsv0020[2];        /*  0x0020                                                    */
+    __IO uint32_t bb;               /*  0x0028   Bit-Bang Control Register                        */
+} mxc_i2cm_regs_t;
+
+/*                                      Offset   Register Description
+                                        ======   ================================================ */
+typedef struct {
+    __IO uint32_t trans[512];       /*  0x0000   I2C Master Transaction FIFO                      */
+    __IO uint32_t rslts[512];       /*  0x0800   I2C Master Results FIFO                          */
+} mxc_i2cm_fifo_regs_t;
+
+/*
+   Register offsets for module I2CM.
+*/
+#define MXC_R_I2CM_OFFS_FS_CLK_DIV                ((uint32_t)0x00000000UL)
+#define MXC_R_I2CM_OFFS_HS_CLK_DIV                ((uint32_t)0x00000004UL)
+#define MXC_R_I2CM_OFFS_TIMEOUT                   ((uint32_t)0x0000000CUL)
+#define MXC_R_I2CM_OFFS_CTRL                      ((uint32_t)0x00000010UL)
+#define MXC_R_I2CM_OFFS_TRANS                     ((uint32_t)0x00000014UL)
+#define MXC_R_I2CM_OFFS_INTFL                     ((uint32_t)0x00000018UL)
+#define MXC_R_I2CM_OFFS_INTEN                     ((uint32_t)0x0000001CUL)
+#define MXC_R_I2CM_OFFS_BB                        ((uint32_t)0x00000028UL)
+#define MXC_R_I2CM_OFFS_AHB_RETRY                 ((uint32_t)0x00000030UL)
+
+#define MXC_R_I2CM_FIFO_OFFS_TRANS                ((uint32_t)0x00000000UL)
+#define MXC_R_I2CM_FIFO_OFFS_RSLTS                ((uint32_t)0x00000800UL)
+
+/*
+   Field positions and masks for module I2CM.
+*/
+#define MXC_S_I2CM_TRANS_TAG_START                0x000
+#define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK           0x100
+#define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK          0x200
+#define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT         0x400
+#define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK          0x500
+#define MXC_S_I2CM_TRANS_TAG_STOP                 0x700
+#define MXC_S_I2CM_RSTLS_TAG_DATA                 0x100
+#define MXC_S_I2CM_RSTLS_TAG_EMPTY                0x200
+
+#define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS               0
+#define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV                   ((uint32_t)(0x000000FFUL << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS))
+#define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS                   8
+#define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT                       ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS))
+#define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS                   20
+#define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT                       ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS))
+
+#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS                   16
+#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT                       ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS))
+#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS                 24
+#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN                     ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS))
+
+#define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS                      2
+#define MXC_F_I2CM_CTRL_TX_FIFO_EN                          ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS))
+#define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS                      3
+#define MXC_F_I2CM_CTRL_RX_FIFO_EN                          ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS))
+#define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS                   7
+#define MXC_F_I2CM_CTRL_MSTR_RESET_EN                       ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS))
+
+#define MXC_F_I2CM_TRANS_TX_START_POS                       0
+#define MXC_F_I2CM_TRANS_TX_START                           ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS))
+#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS                 1
+#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS                     ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS))
+#define MXC_F_I2CM_TRANS_TX_DONE_POS                        2
+#define MXC_F_I2CM_TRANS_TX_DONE                            ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS))
+#define MXC_F_I2CM_TRANS_TX_NACKED_POS                      3
+#define MXC_F_I2CM_TRANS_TX_NACKED                          ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS))
+#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS                 4
+#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR                     ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS))
+#define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS                     5
+#define MXC_F_I2CM_TRANS_TX_TIMEOUT                         ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS))
+
+#define MXC_F_I2CM_INTFL_TX_DONE_POS                        0
+#define MXC_F_I2CM_INTFL_TX_DONE                            ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS))
+#define MXC_F_I2CM_INTFL_TX_NACKED_POS                      1
+#define MXC_F_I2CM_INTFL_TX_NACKED                          ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS))
+#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS                 2
+#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR                     ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS))
+#define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS                     3
+#define MXC_F_I2CM_INTFL_TX_TIMEOUT                         ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS))
+#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS                  4
+#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY                      ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS))
+#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS               5
+#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY                   ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS))
+#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS              6
+#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY                  ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS))
+#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS                7
+#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL                    ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS))
+#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS                8
+#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL                    ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS))
+#define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS                   9
+#define MXC_F_I2CM_INTFL_RX_FIFO_FULL                       ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS))
+
+#define MXC_F_I2CM_INTEN_TX_DONE_POS                        0
+#define MXC_F_I2CM_INTEN_TX_DONE                            ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS))
+#define MXC_F_I2CM_INTEN_TX_NACKED_POS                      1
+#define MXC_F_I2CM_INTEN_TX_NACKED                          ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS))
+#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS                 2
+#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR                     ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS))
+#define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS                     3
+#define MXC_F_I2CM_INTEN_TX_TIMEOUT                         ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS))
+#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS                  4
+#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY                      ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS))
+#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS               5
+#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY                   ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS))
+#define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS                  6
+#define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY                      ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS))
+#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS                7
+#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL                    ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS))
+#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS                8
+#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL                    ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS))
+#define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS                   9
+#define MXC_F_I2CM_INTEN_RX_FIFO_FULL                       ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS))
+
+#define MXC_F_I2CM_BB_BB_SCL_OUT_POS                        0
+#define MXC_F_I2CM_BB_BB_SCL_OUT                            ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS))
+#define MXC_F_I2CM_BB_BB_SDA_OUT_POS                        1
+#define MXC_F_I2CM_BB_BB_SDA_OUT                            ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS))
+#define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS                     2
+#define MXC_F_I2CM_BB_BB_SCL_IN_VAL                         ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS))
+#define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS                     3
+#define MXC_F_I2CM_BB_BB_SDA_IN_VAL                         ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS))
+#define MXC_F_I2CM_BB_RX_FIFO_CNT_POS                       16
+#define MXC_F_I2CM_BB_RX_FIFO_CNT                           ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/icc_regs.h

@@ -0,0 +1,96 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_ICC_REGS_H_
+#define _MXC_ICC_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  icc_regs.h
+ * @addtogroup icc ICC
+ * @{
+ */
+
+/*                                              Offset   Register Description
+                                                ======   =================================================== */
+typedef struct {
+    __IO uint32_t id;                       /*  0x0000   Device ID Register                                  */
+    __IO uint32_t mem_cfg;                  /*  0x0004   Memory Configuration                                */
+    __I uint32_t rsv0008[62];               /*  0x0008                                                       */
+    __IO uint32_t ctrl_stat;                /*  0x0100   Control and Status                                  */
+    __I uint32_t rsv0104[383];              /*  0x0104                                                       */
+    __IO uint32_t invdt_all;                /*  0x0700   Invalidate (Clear) Cache Control                    */
+} mxc_icc_regs_t;
+
+/*
+   Register offsets for module ICC.
+*/
+#define MXC_R_ICC_OFFS_ID                       ((uint32_t)0x00000000UL)
+#define MXC_R_ICC_OFFS_MEM_CFG                  ((uint32_t)0x00000004UL)
+#define MXC_R_ICC_OFFS_CTRL_STAT                ((uint32_t)0x00000100UL)
+#define MXC_R_ICC_OFFS_INVDT_ALL                ((uint32_t)0x00000700UL)
+
+/*
+   Field positions and masks for module ICC.
+*/
+#define MXC_F_ICC_ID_RTL_VERSION_POS            0
+#define MXC_F_ICC_ID_RTL_VERSION                ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_RTL_VERSION_POS))
+#define MXC_F_ICC_ID_PART_NUM_POS               6
+#define MXC_F_ICC_ID_PART_NUM                   ((uint32_t)(0x0000000FUL << MXC_F_ICC_ID_PART_NUM_POS))
+#define MXC_F_ICC_ID_CACHE_ID_POS               10
+#define MXC_F_ICC_ID_CACHE_ID                   ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_CACHE_ID_POS))
+
+#define MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS        0
+#define MXC_F_ICC_MEM_CFG_CACHE_SIZE            ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS))
+#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS  16
+#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE      ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS))
+
+#define MXC_F_ICC_CTRL_STAT_ENABLE_POS          0
+#define MXC_F_ICC_CTRL_STAT_ENABLE              ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_ENABLE_POS))
+#define MXC_F_ICC_CTRL_STAT_READY_POS           16
+#define MXC_F_ICC_CTRL_STAT_READY               ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_READY_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_ICC_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/ioman_regs.h

@@ -0,0 +1,508 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_IOMAN_REGS_H_
+#define _MXC_IOMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  ioman_regs.h
+ * @addtogroup ioman IO MUX Manager
+ * @{
+ */
+
+typedef enum {
+    /** Pin Mapping 'A' */
+    MXC_E_IOMAN_MAPPING_A = 0,
+    /** Pin Mapping 'B' */
+    MXC_E_IOMAN_MAPPING_B,
+    /** Pin Mapping 'C' */
+    MXC_E_IOMAN_MAPPING_C,
+    /** Pin Mapping 'D' */
+    MXC_E_IOMAN_MAPPING_D,
+    /** Pin Mapping 'E' */
+    MXC_E_IOMAN_MAPPING_E,
+    /** Pin Mapping 'F' */
+    MXC_E_IOMAN_MAPPING_F,
+    /** Pin Mapping 'G' */
+    MXC_E_IOMAN_MAPPING_G,
+    /** Pin Mapping 'H' */
+    MXC_E_IOMAN_MAPPING_H,
+} ioman_mapping_t;
+
+/*                                      Offset   Register Description
+                                        ======   ========================================== */
+typedef struct {
+    __IO uint32_t wud_req0;         /*  0x0000   Wakeup Detect Mode Request Register 0      */
+    __IO uint32_t wud_req1;         /*  0x0004   Wakeup Detect Mode Request Register 1      */
+    __IO uint32_t wud_ack0;         /*  0x0008   Wakeup Detect Mode Acknowledge Register 0  */
+    __IO uint32_t wud_ack1;         /*  0x000C   Wakeup Detect Mode Acknowledge Register 1  */
+    __IO uint32_t ali_req0;         /*  0x0010   Analog Input Request Register 0            */
+    __IO uint32_t ali_req1;         /*  0x0014   Analog Input Request Register 1            */
+    __IO uint32_t ali_ack0;         /*  0x0018   Analog Input Acknowledge Register 0        */
+    __IO uint32_t ali_ack1;         /*  0x001C   Analog Input Acknowledge Register 1        */
+    __IO uint32_t spi0_req;         /*  0x0020   SPI0 I/O Mode Request                      */
+    __IO uint32_t spi0_ack;         /*  0x0024   SPI0 I/O Mode Acknowledge                  */
+    __IO uint32_t spi1_req;         /*  0x0028   SPI1 I/O Mode Request                      */
+    __IO uint32_t spi1_ack;         /*  0x002C   SPI1 I/O Mode Acknowledge                  */
+    __IO uint32_t spi2_req;         /*  0x0030   SPI2 I/O Mode Request                      */
+    __IO uint32_t spi2_ack;         /*  0x0034   SPI2 I/O Mode Acknowledge                  */
+    __IO uint32_t uart0_req;        /*  0x0038   UART0 I/O Mode Request                     */
+    __IO uint32_t uart0_ack;        /*  0x003C   UART0 I/O Mode Acknowledge                 */
+    __IO uint32_t uart1_req;        /*  0x0040   UART1 I/O Mode Request                     */
+    __IO uint32_t uart1_ack;        /*  0x0044   UART1 I/O Mode Acknowledge                 */
+    __IO uint32_t i2cm0_req;        /*  0x0048   I2C Master 0 I/O Request                   */
+    __IO uint32_t i2cm0_ack;        /*  0x004C   I2C Master 0 I/O Acknowledge               */
+    __IO uint32_t i2cs0_req;        /*  0x0050   I2C Slave 0 I/O Request                    */
+    __IO uint32_t i2s0_ack;         /*  0x0054   I2C Slave 0 I/O Acknowledge                */
+    __IO uint32_t lcd_com_req;      /*  0x0058   LCD COM Driver I/O Request                 */
+    __IO uint32_t lcd_com_ack;      /*  0x005C   LCD COM Driver I/O Acknowledge             */
+    __IO uint32_t lcd_seg_req0;     /*  0x0060   LCD SEG Driver I/O Request Register 0      */
+    __IO uint32_t lcd_seg_req1;     /*  0x0064   LCD SEG Driver I/O Request Register 1      */
+    __IO uint32_t lcd_seg_ack0;     /*  0x0068   LCD SEG Driver I/O Acknowledge Register 0  */
+    __IO uint32_t lcd_seg_ack1;     /*  0x006C   LCD SEG Driver I/O Acknowledge Register 1  */
+    __IO uint32_t crnt_req;         /*  0x0070   Current Drive I/O Request Register         */
+    __IO uint32_t io_crnt_ack;      /*  0x0074   Current Drive I/O Acknowledge Register     */
+    __IO uint32_t crnt_mode;        /*  0x0078   Current Drive I/O Mode Control             */
+    __IO uint32_t ali_connect0;     /*  0x007C   Analog I/O Connection Control Register 0   */
+    __IO uint32_t ali_connect1;     /*  0x0080   Analog I/O Connection Control Register 1   */
+    __IO uint32_t i2cm1_req;        /*  0x0084   I2C Master 1 I/O Request                   */
+    __IO uint32_t i2cm1_ack;        /*  0x0088   I2C Master 1 I/O Acknowledge               */
+    __IO uint32_t padx_control;     /*  0x008C   PADX Control                               */
+} mxc_ioman_regs_t;
+
+
+/*
+   Register offsets for module IOMAN.
+*/
+#define MXC_R_IOMAN_OFFS_WUD_REQ0                 ((uint32_t)0x00000000UL)
+#define MXC_R_IOMAN_OFFS_WUD_REQ1                 ((uint32_t)0x00000004UL)
+#define MXC_R_IOMAN_OFFS_WUD_ACK0                 ((uint32_t)0x00000008UL)
+#define MXC_R_IOMAN_OFFS_WUD_ACK1                 ((uint32_t)0x0000000CUL)
+#define MXC_R_IOMAN_OFFS_ALI_REQ0                 ((uint32_t)0x00000010UL)
+#define MXC_R_IOMAN_OFFS_ALI_REQ1                 ((uint32_t)0x00000014UL)
+#define MXC_R_IOMAN_OFFS_ALI_ACK0                 ((uint32_t)0x00000018UL)
+#define MXC_R_IOMAN_OFFS_ALI_ACK1                 ((uint32_t)0x0000001CUL)
+#define MXC_R_IOMAN_OFFS_SPI0_REQ                 ((uint32_t)0x00000020UL)
+#define MXC_R_IOMAN_OFFS_SPI0_ACK                 ((uint32_t)0x00000024UL)
+#define MXC_R_IOMAN_OFFS_SPI1_REQ                 ((uint32_t)0x00000028UL)
+#define MXC_R_IOMAN_OFFS_SPI1_ACK                 ((uint32_t)0x0000002CUL)
+#define MXC_R_IOMAN_OFFS_SPI2_REQ                 ((uint32_t)0x00000030UL)
+#define MXC_R_IOMAN_OFFS_SPI2_ACK                 ((uint32_t)0x00000034UL)
+#define MXC_R_IOMAN_OFFS_UART0_REQ                ((uint32_t)0x00000038UL)
+#define MXC_R_IOMAN_OFFS_UART0_ACK                ((uint32_t)0x0000003CUL)
+#define MXC_R_IOMAN_OFFS_UART1_REQ                ((uint32_t)0x00000040UL)
+#define MXC_R_IOMAN_OFFS_UART1_ACK                ((uint32_t)0x00000044UL)
+#define MXC_R_IOMAN_OFFS_I2CM0_REQ                ((uint32_t)0x00000048UL)
+#define MXC_R_IOMAN_OFFS_I2CM0_ACK                ((uint32_t)0x0000004CUL)
+#define MXC_R_IOMAN_OFFS_I2CS0_REQ                ((uint32_t)0x00000050UL)
+#define MXC_R_IOMAN_OFFS_I2SC0_ACK                ((uint32_t)0x00000054UL)
+#define MXC_R_IOMAN_OFFS_LCD_COM_REQ              ((uint32_t)0x00000058UL)
+#define MXC_R_IOMAN_OFFS_LCD_COM_ACK              ((uint32_t)0x0000005CUL)
+#define MXC_R_IOMAN_OFFS_LCD_SEG_REQ0             ((uint32_t)0x00000060UL)
+#define MXC_R_IOMAN_OFFS_LCD_SEG_REQ1             ((uint32_t)0x00000064UL)
+#define MXC_R_IOMAN_OFFS_LCD_SEG_ACK0             ((uint32_t)0x00000068UL)
+#define MXC_R_IOMAN_OFFS_LCD_SEG_ACK1             ((uint32_t)0x0000006CUL)
+#define MXC_R_IOMAN_OFFS_IO_CRNT_REQ              ((uint32_t)0x00000070UL)
+#define MXC_R_IOMAN_OFFS_IO_CRNT_ACK              ((uint32_t)0x00000074UL)
+#define MXC_R_IOMAN_OFFS_IO_CRNT_MODE             ((uint32_t)0x00000078UL)
+#define MXC_R_IOMAN_OFFS_ALI_CONNECT0             ((uint32_t)0x0000007CUL)
+#define MXC_R_IOMAN_OFFS_ALI_CONNECT1             ((uint32_t)0x00000080UL)
+#define MXC_R_IOMAN_OFFS_I2CM1_REQ                ((uint32_t)0x00000084UL)
+#define MXC_R_IOMAN_OFFS_I2CM1_ACK                ((uint32_t)0x00000088UL)
+#define MXC_R_IOMAN_OFFS_PADX_CONTROL             ((uint32_t)0x0000008CUL)
+
+
+/*
+   Field positions and masks for module IOMAN.
+*/
+#define MXC_F_IOMAN_WUD_REQ0_PORT0_POS                      0
+#define MXC_F_IOMAN_WUD_REQ0_PORT0                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT0_POS))
+#define MXC_F_IOMAN_WUD_REQ0_PORT1_POS                      8
+#define MXC_F_IOMAN_WUD_REQ0_PORT1                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT1_POS))
+#define MXC_F_IOMAN_WUD_REQ0_PORT2_POS                      16
+#define MXC_F_IOMAN_WUD_REQ0_PORT2                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT2_POS))
+#define MXC_F_IOMAN_WUD_REQ0_PORT3_POS                      24
+#define MXC_F_IOMAN_WUD_REQ0_PORT3                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT3_POS))
+
+#define MXC_F_IOMAN_WUD_REQ1_PORT4_POS                      0
+#define MXC_F_IOMAN_WUD_REQ1_PORT4                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT4_POS))
+#define MXC_F_IOMAN_WUD_REQ1_PORT5_POS                      8
+#define MXC_F_IOMAN_WUD_REQ1_PORT5                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT5_POS))
+#define MXC_F_IOMAN_WUD_REQ1_PORT6_POS                      16
+#define MXC_F_IOMAN_WUD_REQ1_PORT6                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT6_POS))
+#define MXC_F_IOMAN_WUD_REQ1_PORT7_POS                      24
+#define MXC_F_IOMAN_WUD_REQ1_PORT7                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT7_POS))
+
+#define MXC_F_IOMAN_WUD_ACK0_PORT0_POS                      0
+#define MXC_F_IOMAN_WUD_ACK0_PORT0                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT0_POS))
+#define MXC_F_IOMAN_WUD_ACK0_PORT1_POS                      8
+#define MXC_F_IOMAN_WUD_ACK0_PORT1                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT1_POS))
+#define MXC_F_IOMAN_WUD_ACK0_PORT2_POS                      16
+#define MXC_F_IOMAN_WUD_ACK0_PORT2                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT2_POS))
+#define MXC_F_IOMAN_WUD_ACK0_PORT3_POS                      24
+#define MXC_F_IOMAN_WUD_ACK0_PORT3                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT3_POS))
+
+#define MXC_F_IOMAN_WUD_ACK1_PORT4_POS                      0
+#define MXC_F_IOMAN_WUD_ACK1_PORT4                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT4_POS))
+#define MXC_F_IOMAN_WUD_ACK1_PORT5_POS                      8
+#define MXC_F_IOMAN_WUD_ACK1_PORT5                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT5_POS))
+#define MXC_F_IOMAN_WUD_ACK1_PORT6_POS                      16
+#define MXC_F_IOMAN_WUD_ACK1_PORT6                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT6_POS))
+#define MXC_F_IOMAN_WUD_ACK1_PORT7_POS                      24
+#define MXC_F_IOMAN_WUD_ACK1_PORT7                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT7_POS))
+
+#define MXC_F_IOMAN_ALI_REQ0_PORT0_POS                      0
+#define MXC_F_IOMAN_ALI_REQ0_PORT0                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT0_POS))
+#define MXC_F_IOMAN_ALI_REQ0_PORT1_POS                      8
+#define MXC_F_IOMAN_ALI_REQ0_PORT1                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT1_POS))
+#define MXC_F_IOMAN_ALI_REQ0_PORT2_POS                      16
+#define MXC_F_IOMAN_ALI_REQ0_PORT2                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT2_POS))
+#define MXC_F_IOMAN_ALI_REQ0_PORT3_POS                      24
+#define MXC_F_IOMAN_ALI_REQ0_PORT3                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT3_POS))
+
+#define MXC_F_IOMAN_ALI_REQ1_PORT4_POS                      0
+#define MXC_F_IOMAN_ALI_REQ1_PORT4                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT4_POS))
+#define MXC_F_IOMAN_ALI_REQ1_PORT5_POS                      8
+#define MXC_F_IOMAN_ALI_REQ1_PORT5                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT5_POS))
+#define MXC_F_IOMAN_ALI_REQ1_PORT6_POS                      16
+#define MXC_F_IOMAN_ALI_REQ1_PORT6                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT6_POS))
+#define MXC_F_IOMAN_ALI_REQ1_PORT7_POS                      24
+#define MXC_F_IOMAN_ALI_REQ1_PORT7                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT7_POS))
+
+#define MXC_F_IOMAN_ALI_ACK0_PORT0_POS                      0
+#define MXC_F_IOMAN_ALI_ACK0_PORT0                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT0_POS))
+#define MXC_F_IOMAN_ALI_ACK0_PORT1_POS                      8
+#define MXC_F_IOMAN_ALI_ACK0_PORT1                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT1_POS))
+#define MXC_F_IOMAN_ALI_ACK0_PORT2_POS                      16
+#define MXC_F_IOMAN_ALI_ACK0_PORT2                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT2_POS))
+#define MXC_F_IOMAN_ALI_ACK0_PORT3_POS                      24
+#define MXC_F_IOMAN_ALI_ACK0_PORT3                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT3_POS))
+
+#define MXC_F_IOMAN_ALI_ACK1_PORT4_POS                      0
+#define MXC_F_IOMAN_ALI_ACK1_PORT4                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT4_POS))
+#define MXC_F_IOMAN_ALI_ACK1_PORT5_POS                      8
+#define MXC_F_IOMAN_ALI_ACK1_PORT5                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT5_POS))
+#define MXC_F_IOMAN_ALI_ACK1_PORT6_POS                      16
+#define MXC_F_IOMAN_ALI_ACK1_PORT6                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT6_POS))
+#define MXC_F_IOMAN_ALI_ACK1_PORT7_POS                      24
+#define MXC_F_IOMAN_ALI_ACK1_PORT7                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT7_POS))
+
+#define MXC_F_IOMAN_SPI_MAPPING_POS                         0
+#define MXC_F_IOMAN_SPI_MAPPING                             ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPI_MAPPING_POS))
+#define MXC_F_IOMAN_SPI_CORE_IO_POS                         4
+#define MXC_F_IOMAN_SPI_CORE_IO                             ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_CORE_IO_POS))
+#define MXC_F_IOMAN_SPI_SS0_IO_POS                          8
+#define MXC_F_IOMAN_SPI_SS0_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS0_IO_POS))
+#define MXC_F_IOMAN_SPI_SS1_IO_POS                          9
+#define MXC_F_IOMAN_SPI_SS1_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS1_IO_POS))
+#define MXC_F_IOMAN_SPI_SS2_IO_POS                          10
+#define MXC_F_IOMAN_SPI_SS2_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS2_IO_POS))
+#define MXC_F_IOMAN_SPI_SS3_IO_POS                          11
+#define MXC_F_IOMAN_SPI_SS3_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS3_IO_POS))
+#define MXC_F_IOMAN_SPI_SS4_IO_POS                          12
+#define MXC_F_IOMAN_SPI_SS4_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS4_IO_POS))
+#define MXC_F_IOMAN_SPI_SR0_IO_POS                          16
+#define MXC_F_IOMAN_SPI_SR0_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR0_IO_POS))
+#define MXC_F_IOMAN_SPI_SR1_IO_POS                          17
+#define MXC_F_IOMAN_SPI_SR1_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR1_IO_POS))
+#define MXC_F_IOMAN_SPI_QUAD_IO_POS                         20
+#define MXC_F_IOMAN_SPI_QUAD_IO                             ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_QUAD_IO_POS))
+#define MXC_F_IOMAN_SPI_FAST_MODE_POS                       24
+#define MXC_F_IOMAN_SPI_FAST_MODE                           ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_UART_MAPPING_POS                        0
+#define MXC_F_IOMAN_UART_MAPPING                            ((uint32_t)(0x00000003UL << MXC_F_IOMAN_UART_MAPPING_POS))
+#define MXC_F_IOMAN_UART_CORE_IO_POS                        4
+#define MXC_F_IOMAN_UART_CORE_IO                            ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CORE_IO_POS))
+#define MXC_F_IOMAN_UART_CTS_IO_POS                         5
+#define MXC_F_IOMAN_UART_CTS_IO                             ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CTS_IO_POS))
+#define MXC_F_IOMAN_UART_RTS_IO_POS                         6
+#define MXC_F_IOMAN_UART_RTS_IO                             ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_RTS_IO_POS))
+
+#define MXC_F_IOMAN_I2CM_MAPPING_POS                        0
+#define MXC_F_IOMAN_I2CM_MAPPING                            ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM_MAPPING_POS))
+#define MXC_F_IOMAN_I2CM_CORE_IO_POS                        4
+#define MXC_F_IOMAN_I2CM_CORE_IO                            ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM_CORE_IO_POS))
+
+#define MXC_F_IOMAN_I2CS_MAPPING_POS                        0
+#define MXC_F_IOMAN_I2CS_MAPPING                            ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_MAPPING_POS))
+#define MXC_F_IOMAN_I2CS_CORE_IO_POS                        4
+#define MXC_F_IOMAN_I2CS_CORE_IO                            ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_CORE_IO_POS))
+
+#define MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS                  0
+#define MXC_F_IOMAN_LCD_COM_REQ_COM_IO                      ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS))
+
+#define MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS                  0
+#define MXC_F_IOMAN_LCD_COM_ACK_COM_IO                      ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS))
+
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS              0
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS              1
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS              2
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS              3
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS              4
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS              5
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS              6
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS              7
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS              8
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS              9
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS              10
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS              11
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS              12
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS              13
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS              14
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS              15
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS              16
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS              17
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS              18
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS              19
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS              20
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS              21
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS              22
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS              23
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS              24
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS              25
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS              26
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS              27
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS              28
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS              29
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS              30
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS              31
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS))
+
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS              0
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS              1
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS              2
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS              3
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS              4
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS              5
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS              6
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS              7
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS))
+
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS              0
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS              1
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS              2
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS              3
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS              4
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS              5
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS              6
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS              7
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS              8
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS              9
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS              10
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS              11
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS              12
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS              13
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS              14
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS              15
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS              16
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS              17
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS              18
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS              19
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS              20
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS              21
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS              22
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS              23
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS              24
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS              25
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS              26
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS              27
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS              28
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS              29
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS              30
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS              31
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS))
+
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS              0
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS              1
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS              2
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS              3
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS              4
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS              5
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS              6
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS              7
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS))
+
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS               0
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS               1
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS               2
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS               3
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS               4
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS               5
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS               6
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS               7
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS))
+
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS               0
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS               1
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS               2
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS               3
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS               4
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS               5
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS               6
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS               7
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS))
+
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS                  0
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS                  4
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS                  8
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS                  12
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS                  16
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS                  20
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS                  24
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS                  28
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS))
+
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS     0
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL         ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS))
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS    4
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE        ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS))
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS 6
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE     ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS))
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS    8
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE        ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS))
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS 10
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE     ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_IOMAN_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/lcd_regs.h

@@ -0,0 +1,70 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_LCD_REGS_H
+#define _MXC_LCD_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  lcd_regs.h
+ * @addtogroup lcd LCD
+ * @{
+ */
+
+#define MXC_LCD_ADDRESS_SEGS 21
+
+/*                                 Offset   Register Description
+                                   ======   ======================================================= */
+typedef struct {    
+    __IO uint32_t lcfg;         /* 0x0000                                                           */
+    __IO uint32_t lcra;         /* 0x0004                                                           */
+    __IO uint32_t lpcf;         /* 0x0008  LCD Port Configuration Register                          */
+    __IO uint32_t lcaddr;       /* 0x000C                                                           */
+    __IO uint32_t lcdata;       /* 0x0010  LCD Memory Data Read / Write                             */
+    __IO uint32_t lpwrctrl;     /* 0x0014  LCD Power Control                                        */
+} mxc_lcd_regs_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* _MXC_LCD_REGS_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/maa_regs.h

@@ -0,0 +1,124 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_MAA_REGS_H_
+#define _MXC_MAA_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  maa_regs.h
+ * @addtogroup maa MAA
+ * @{
+ */
+
+/*                                    Offset   Register Description
+                                      ======   ========================================================== */
+typedef struct {
+    __IO uint32_t ctrl;           /*  0x0000   MAA Control, Configuration and Status                      */
+    __IO uint32_t maws;           /*  0x0004   MAA Word (Operand) Size, Big/Little Endian Mode Select     */
+} mxc_maa_regs_t;
+
+/*                                    Offset   Register Description
+                                      ======   ========================================================== */
+typedef struct {
+    __IO uint32_t seg0[16];        /*  0x0000   [64 bytes] MAA Memory Segment 0                            */
+    __IO uint32_t seg1[16];        /*  0x0040   [64 bytes] MAA Memory Segment 1                            */
+    __IO uint32_t seg2[16];        /*  0x0080   [64 bytes] MAA Memory Segment 2                            */
+    __IO uint32_t seg3[16];        /*  0x00C0   [64 bytes] MAA Memory Segment 3                            */
+    __IO uint32_t seg4[16];        /*  0x0100   [64 bytes] MAA Memory Segment 4                            */
+    __IO uint32_t seg5[16];        /*  0x0140   [64 bytes] MAA Memory Segment 5                            */
+} mxc_maa_mem_regs_t;
+
+/*
+   Register offsets for module MAA.
+*/
+#define MXC_R_MAA_OFFS_CTRL         ((uint32_t)0x00000000UL)
+#define MXC_R_MAA_OFFS_MAWS         ((uint32_t)0x00000004UL)
+#define MXC_R_MAA_MEM_OFFS_SEG0     ((uint32_t)0x00000000UL)
+#define MXC_R_MAA_MEM_OFFS_SEG1     ((uint32_t)0x00000040UL)
+#define MXC_R_MAA_MEM_OFFS_SEG2     ((uint32_t)0x00000080UL)
+#define MXC_R_MAA_MEM_OFFS_SEG3     ((uint32_t)0x000000C0UL)
+#define MXC_R_MAA_MEM_OFFS_SEG4     ((uint32_t)0x00000100UL)
+#define MXC_R_MAA_MEM_OFFS_SEG5     ((uint32_t)0x00000140UL)
+
+/*
+   Field positions and masks for module MAA.
+*/
+#define MXC_F_MAA_CTRL_START_POS    0
+#define MXC_F_MAA_CTRL_START        ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_START_POS))
+#define MXC_F_MAA_CTRL_OPSEL_POS    1
+#define MXC_F_MAA_CTRL_OPSEL        ((uint32_t)(0x00000007UL << MXC_F_MAA_CTRL_OPSEL_POS))
+#define MXC_F_MAA_CTRL_OCALC_POS    4
+#define MXC_F_MAA_CTRL_OCALC        ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_OCALC_POS))
+#define MXC_F_MAA_CTRL_INTEN_POS    5
+#define MXC_F_MAA_CTRL_INTEN        ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_INTEN_POS))
+#define MXC_F_MAA_CTRL_IF_DONE_POS  6
+#define MXC_F_MAA_CTRL_IF_DONE      ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_DONE_POS))
+#define MXC_F_MAA_CTRL_IF_ERROR_POS 7
+#define MXC_F_MAA_CTRL_IF_ERROR     ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_ERROR_POS))
+#define MXC_F_MAA_CTRL_OFS_A_POS    8
+#define MXC_F_MAA_CTRL_OFS_A        ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_A_POS))
+#define MXC_F_MAA_CTRL_OFS_B_POS    10
+#define MXC_F_MAA_CTRL_OFS_B        ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_B_POS))
+#define MXC_F_MAA_CTRL_OFS_EXP_POS  12
+#define MXC_F_MAA_CTRL_OFS_EXP      ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_EXP_POS))
+#define MXC_F_MAA_CTRL_OFS_MOD_POS  14
+#define MXC_F_MAA_CTRL_OFS_MOD      ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_MOD_POS))
+#define MXC_F_MAA_CTRL_SEG_A_POS    16
+#define MXC_F_MAA_CTRL_SEG_A        ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_A_POS))
+#define MXC_F_MAA_CTRL_SEG_B_POS    20
+#define MXC_F_MAA_CTRL_SEG_B        ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_B_POS))
+#define MXC_F_MAA_CTRL_SEG_RES_POS  24
+#define MXC_F_MAA_CTRL_SEG_RES      ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_RES_POS))
+#define MXC_F_MAA_CTRL_SEG_TMP_POS  28
+#define MXC_F_MAA_CTRL_SEG_TMP      ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_TMP_POS))
+
+#define MXC_F_MAA_MAWS_MODLEN_POS   0
+#define MXC_F_MAA_MAWS_MODLEN       ((uint32_t)(0x000003FFUL << MXC_F_MAA_MAWS_MODLEN_POS))
+#define MXC_F_MAA_MAWS_BYTESWAP_POS 16
+#define MXC_F_MAA_MAWS_BYTESWAP     ((uint32_t)(0x00000001UL << MXC_F_MAA_MAWS_BYTESWAP_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_MAA_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/max32600.h

@@ -0,0 +1,666 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MAX32600_H_
+#define _MAX32600_H_
+
+#include <stdint.h>
+
+typedef enum IRQn_Type {
+    NonMaskableInt_IRQn = -14,
+    HardFault_IRQn = -13,
+    MemoryManagement_IRQn = -12,
+    BusFault_IRQn = -11,
+    UsageFault_IRQn = -10,
+    SVCall_IRQn = -5,
+    DebugMonitor_IRQn = -4,
+    PendSV_IRQn = -2,
+    SysTick_IRQn = -1,
+
+    /* Externals interrupts */
+    UART0_IRQn = 0,      /* 16:01 UART0 */
+    UART1_IRQn,          /* 17: 2 UART1 */
+    I2CM0_IRQn,          /* 18: 3 I2C Master 0 */
+    I2CS_IRQn,           /* 19: 4 I2C Slave */
+    USB_IRQn,            /* 20: 5 USB */
+    PMU_IRQn,            /* 21: 6 DMA */
+    AFE_IRQn,            /* 22: 7 AFE */
+    MAA_IRQn,            /* 23: 8 MAA */
+    AES_IRQn,            /* 24: 9 AES */
+    SPI0_IRQn,           /* 25:10 SPI0 */
+    SPI1_IRQn,           /* 26:11 SPI1 */
+    SPI2_IRQn,           /* 27:12 SPI2 */
+    TMR0_IRQn,           /* 28:13 Timer32-0 */
+    TMR1_IRQn,           /* 29:14 Timer32-1 */
+    TMR2_IRQn,           /* 30:15 Timer32-1 */
+    TMR3_IRQn,           /* 31:16 Timer32-2 */
+    RSVD0_IRQn,          /* 32:17 RSVD */
+    RSVD1_IRQn,          /* 33:18 RSVD */
+    DAC0_IRQn,           /* 34:19 DAC0  (12-bit DAC) */
+    DAC1_IRQn,           /* 35:20 DAC1  (12-bit DAC) */
+    DAC2_IRQn,           /* 36:21 DAC2  (8-bit DAC) */
+    DAC3_IRQn,           /* 37:22 DAC3  (8-bit DAC) */
+    ADC_IRQn,            /* 38:23 ADC */
+    FLC_IRQn,            /* 39:24 Flash Controller */
+    PWRMAN_IRQn,         /* 40:25 PWRMAN */
+    CLKMAN_IRQn,         /* 41:26 CLKMAN */
+    RTC0_IRQn,           /* 42:27 RTC INT0 */
+    RTC1_IRQn,           /* 43:28 RTC INT1 */
+    RTC2_IRQn,           /* 44:29 RTC INT2 */
+    RTC3_IRQn,           /* 45:30 RTC INT3 */
+    WDT0_IRQn,           /* 46:31 WATCHDOG0 */
+    WDT0_P_IRQn,         /* 47:32 WATCHDOG0 PRE-WINDOW */
+    WDT1_IRQn,           /* 48:33 WATCHDOG1 */
+    WDT1_P_IRQn,         /* 49:34 WATCHDOG1 PRE-WINDOW */
+    GPIO_P0_IRQn,        /* 50:35 GPIO Port 0  */
+    GPIO_P1_IRQn,        /* 51:36 GPIO Port 1  */
+    GPIO_P2_IRQn,        /* 52:37 GPIO Port 2  */
+    GPIO_P3_IRQn,        /* 53:38 GPIO Port 3  */
+    GPIO_P4_IRQn,        /* 54:39 GPIO Port 4  */
+    GPIO_P5_IRQn,        /* 55:40 GPIO Port 5  */
+    GPIO_P6_IRQn,        /* 56:41 GPIO Port 6  */
+    GPIO_P7_IRQn,        /* 57:42 GPIO Port 7  */
+    TMR16_0_IRQn,        /* 58:43 Timer16-s0 */
+    TMR16_1_IRQn,        /* 59:44 Timer16-s1 */
+    TMR16_2_IRQn,        /* 60:45 Timer16-s2 */
+    TMR16_3_IRQn,        /* 61:46 Timer16-s3 */
+    I2CM1_IRQn,          /* 62:47 I2C Master 1 */
+    MXC_IRQ_EXT_COUNT,
+} IRQn_Type;
+
+#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+#define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels         */
+
+#include <core_cm3.h>                       /* Processor and core peripherals */
+#include "system_max32600.h"                /* System Header */
+
+/* ================================================================================ */
+/* ==================       Device Specific Memory Section       ================== */
+/* ================================================================================ */
+
+#define MXC_FLASH_MEM_BASE    0x00000000UL
+#define MXC_FLASH_PAGE_SIZE   0x1000        // 256 x 128b = 4KB
+#define MXC_FLASH_MEM_SIZE    0x00040000UL
+#define MXC_SYS_MEM_BASE      0x20000000UL
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+
+/*******************************************************************************/
+/*                                            General Purpose I/O Ports (GPIO) */
+
+#define MXC_BASE_GPIO                   ((uint32_t)0x40000000UL)
+#define MXC_GPIO                        ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
+#define MXC_BASE_GPIO_BITBAND           ((uint32_t)0x42000000UL)
+
+#define MXC_GPIO_GET_IRQ(i)             (((unsigned int)i) + GPIO_P0_IRQn)
+
+
+/*******************************************************************************/
+/*                                                      Pulse Train Generation */
+
+#define MXC_CFG_PT_INSTANCES             (13)
+
+#define MXC_BASE_PTG                     ((uint32_t)0x40001000UL)
+#define MXC_PTG                          ((mxc_ptg_regs_t *)MXC_BASE_PTG)
+#define MXC_BASE_PT                      ((uint32_t)0x40001008UL)
+#define MXC_PT                           ((mxc_pt_regs_t *)MXC_BASE_PT)
+#define MXC_BASE_PT0                     ((uint32_t)0x40001008UL)
+#define MXC_PT0                          ((mxc_pt_regs_t *)MXC_BASE_PT0)
+#define MXC_BASE_PT1                     ((uint32_t)0x40001010UL)
+#define MXC_PT1                          ((mxc_pt_regs_t *)MXC_BASE_PT1)
+#define MXC_BASE_PT2                     ((uint32_t)0x40001018UL)
+#define MXC_PT2                          ((mxc_pt_regs_t *)MXC_BASE_PT2)
+#define MXC_BASE_PT3                     ((uint32_t)0x40001020UL)
+#define MXC_PT3                          ((mxc_pt_regs_t *)MXC_BASE_PT3)
+#define MXC_BASE_PT4                     ((uint32_t)0x40001028UL)
+#define MXC_PT4                          ((mxc_pt_regs_t *)MXC_BASE_PT4)
+#define MXC_BASE_PT5                     ((uint32_t)0x40001030UL)
+#define MXC_PT5                          ((mxc_pt_regs_t *)MXC_BASE_PT5)
+#define MXC_BASE_PT6                     ((uint32_t)0x40001038UL)
+#define MXC_PT6                          ((mxc_pt_regs_t *)MXC_BASE_PT6)
+#define MXC_BASE_PT7                     ((uint32_t)0x40001040UL)
+#define MXC_PT7                          ((mxc_pt_regs_t *)MXC_BASE_PT7)
+#define MXC_BASE_PT8                     ((uint32_t)0x40001048UL)
+#define MXC_PT8                          ((mxc_pt_regs_t *)MXC_BASE_PT8)
+#define MXC_BASE_PT9                     ((uint32_t)0x40001050UL)
+#define MXC_PT9                          ((mxc_pt_regs_t *)MXC_BASE_PT9)
+#define MXC_BASE_PT10                    ((uint32_t)0x40001058UL)
+#define MXC_PT10                         ((mxc_pt_regs_t *)MXC_BASE_PT10)
+#define MXC_BASE_PT11                    ((uint32_t)0x40001060UL)
+#define MXC_PT11                         ((mxc_pt_regs_t *)MXC_BASE_PT11)
+
+/*                                       PT12, PT13, PT14 are not used         */
+
+/*******************************************************************************/
+/*                                                        CRC-16/CRC-32 Engine */
+
+#define MXC_BASE_CRC                    ((uint32_t)0x40010000UL)
+#define MXC_CRC_REGS                    ((mxc_crc_regs_t *)MXC_BASE_CRC)
+
+#define MXC_BASE_CRC_DATA               ((uint32_t)0x4010B000UL)
+#define MXC_CRC_DATA                    ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
+
+/*******************************************************************************/
+/*                                                 Trust Protection Unit (TPU) */
+
+#define MXC_BASE_TPU                     ((uint32_t)0x40011000UL)
+#define MXC_TPU                          ((mxc_tpu_regs_t *)MXC_BASE_TPU)
+
+#define MXC_BASE_TPU_TSR                 ((uint32_t)0x40011C00UL)
+#define MXC_TPU_TSR                      ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
+
+/*******************************************************************************/
+/*                                                    AES Cryptographic Engine */
+
+#define MXC_BASE_AES                     ((uint32_t)0x40011400UL)
+#define MXC_AES                          ((mxc_aes_regs_t *)MXC_BASE_AES)
+
+#define MXC_BASE_AES_MEM                 ((uint32_t)0x4010A000UL)
+#define MXC_AES_MEM                      ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
+
+
+/*******************************************************************************/
+/*                                                    MAA Cryptographic Engine */
+
+#define MXC_BASE_MAA                     ((uint32_t)0x40011800UL)
+#define MXC_MAA                          ((mxc_maa_regs_t *)MXC_BASE_MAA)
+
+#define MXC_BASE_MAA_MEM                 ((uint32_t)0x4010A800UL)
+#define MXC_MAA_MEM                      ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
+
+/*******************************************************************************/
+/*                                                    32-Bit PWM Timer/Counter */
+
+#define MXC_CFG_TMR_INSTANCES            (4)
+
+#define MXC_BASE_TMR0                    ((uint32_t)0x40012000UL)
+#define MXC_BASE_TMR0_BITBAND            ((uint32_t)0x42240000UL)
+#define MXC_TMR0                         ((mxc_tmr_regs_t *) MXC_BASE_TMR0)
+
+#define MXC_BASE_TMR1                    ((uint32_t)0x40013000UL)
+#define MXC_BASE_TMR1_BITBAND            ((uint32_t)0x42260000UL)
+#define MXC_TMR1                         ((mxc_tmr_regs_t *) MXC_BASE_TMR1)
+
+#define MXC_BASE_TMR2                    ((uint32_t)0x40014000UL)
+#define MXC_BASE_TMR2_BITBAND            ((uint32_t)0x42280000UL)
+#define MXC_TMR2                         ((mxc_tmr_regs_t *) MXC_BASE_TMR2)
+
+#define MXC_BASE_TMR3                    ((uint32_t)0x40015000UL)
+#define MXC_BASE_TMR3_BITBAND            ((uint32_t)0x422A0000UL)
+#define MXC_TMR3                         ((mxc_tmr_regs_t *) MXC_BASE_TMR3)
+
+
+#define MXC_TMR_GET_IRQ_32(i)            ((i) == 0 ? TMR0_IRQn :    \
+                                          (i) == 1 ? TMR1_IRQn :    \
+                                          (i) == 2 ? TMR2_IRQn :    \
+                                          (i) == 3 ? TMR3_IRQn : 0)
+
+#define MXC_TMR_GET_IRQ_16(i)            ((i) == 0 ? TMR0_IRQn :    \
+                                          (i) == 1 ? TMR1_IRQn :    \
+                                          (i) == 2 ? TMR2_IRQn :    \
+                                          (i) == 3 ? TMR3_IRQn :    \
+                                          (i) == 4 ? TMR16_0_IRQn :    \
+                                          (i) == 5 ? TMR16_1_IRQn :    \
+                                          (i) == 6 ? TMR16_2_IRQn :    \
+                                          (i) == 7 ? TMR16_3_IRQn : 0)
+
+#define MXC_TMR_GET_BASE(i)              ((i) == 0 ? MXC_BASE_TMR0 : \
+                                          (i) == 1 ? MXC_BASE_TMR1 : \
+                                          (i) == 2 ? MXC_BASE_TMR2 : \
+                                          (i) == 3 ? MXC_BASE_TMR3 : 0)
+
+#define MXC_TMR_GET_TMR(i)               ((i) == 0 ? MXC_TMR0 : \
+                                          (i) == 1 ? MXC_TMR1 : \
+                                          (i) == 2 ? MXC_TMR2 : \
+                                          (i) == 3 ? MXC_TMR3 : 0)
+/*******************************************************************************/
+/*                                                              Watchdog Timer */
+
+#define MXC_CFG_WDT_INSTANCES            (2)
+
+#define MXC_BASE_WDT0                    ((uint32_t)0x40021000UL)
+#define MXC_BASE_WDT0_BITBAND            ((uint32_t)0x42420000UL)
+#define MXC_WDT0                         ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
+
+#define MXC_BASE_WDT1                    ((uint32_t)0x40022000UL)
+#define MXC_BASE_WDT1_BITBAND            ((uint32_t)0x42440000UL)
+#define MXC_WDT1                         ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
+
+#define MXC_WDT_GET_IRQ(i)               ((i) == 0 ? WDT0_IRQn : \
+                                          (i) == 1 ? WDT1_IRQn : 0)
+
+#define MXC_WDT_GET_IRQ_P(i)             ((i) == 0 ? WDT0_P_IRQn : \
+                                          (i) == 1 ? WDT1_P_IRQn : 0)
+
+#define MXC_WDT_GET_BASE(i)              ((i) == 0 ? MXC_BASE_WDT0 : \
+                                          (i) == 1 ? MXC_BASE_WDT1 : 0)
+
+#define MXC_WDT_GET_WDT(i)               ((i) == 0 ? MXC_WDT0 : \
+                                          (i) == 1 ? MXC_WDT1 : 0)
+
+/*******************************************************************************/
+/*                                                               SPI Interface */
+
+#define MXC_CFG_SPI_INSTANCES            (3)
+#define MXC_CFG_SPI_FIFO_DEPTH           (16)
+
+#define MXC_BASE_SPI0                    ((uint32_t)0x40030000UL)
+#define MXC_SPI0                         ((mxc_spi_regs_t *)MXC_BASE_SPI0)
+
+#define MXC_BASE_SPI0_TXFIFO             ((uint32_t)0x40100000UL)
+#define MXC_SPI0_TXFIFO                  ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI0_TXFIFO)
+#define MXC_BASE_SPI0_RXFIFO             ((uint32_t)0x40100800UL)
+#define MXC_SPI0_RXFIFO                  ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI0_RXFIFO)
+
+#define MXC_BASE_SPI1                    ((uint32_t)0x40031000UL)
+#define MXC_SPI1                         ((mxc_spi_regs_t *)MXC_BASE_SPI1)
+
+#define MXC_BASE_SPI1_TXFIFO             ((uint32_t)0x40101000UL)
+#define MXC_SPI1_TXFIFO                  ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI1_TXFIFO)
+#define MXC_BASE_SPI1_RXFIFO             ((uint32_t)0x40101800UL)
+#define MXC_SPI1_RXFIFO                  ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI1_RXFIFO)
+
+#define MXC_BASE_SPI2                    ((uint32_t)0x40032000UL)
+#define MXC_SPI2                         ((mxc_spi_regs_t *)MXC_BASE_SPI2)
+
+#define MXC_BASE_SPI2_TXFIFO             ((uint32_t)0x40102000UL)
+#define MXC_SPI2_TXFIFO                  ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI2_TXFIFO)
+#define MXC_BASE_SPI2_RXFIFO             ((uint32_t)0x40102800UL)
+#define MXC_SPI2_RXFIFO                  ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI2_RXFIFO)
+
+
+#define MXC_SPI_GET_IRQ(i)               ((i) == 0 ? SPI0_IRQn :       \
+                                          (i) == 1 ? SPI1_IRQn :       \
+                                          (i) == 2 ? SPI2_IRQn : 0)
+
+#define MXC_SPI_GET_BASE(i)              ((i) == 0 ? MXC_BASE_SPI0 :      \
+                                          (i) == 1 ? MXC_BASE_SPI1 :      \
+                                          (i) == 2 ? MXC_BASE_SPI2 : 0)
+
+#define MXC_SPI_GET_SPI(i)               ((i) == 0 ? MXC_SPI0 :      \
+                                          (i) == 1 ? MXC_SPI1 :      \
+                                          (i) == 2 ? MXC_SPI2 : 0)
+
+#define MXC_SPI_GET_RXFIFO(i)            ((i) == 0 ? MXC_SPI0_RXFIFO :      \
+                                          (i) == 1 ? MXC_SPI1_RXFIFO :      \
+                                          (i) == 2 ? MXC_SPI2_RXFIFO : 0)
+
+#define MXC_SPI_GET_TXFIFO(i)            ((i) == 0 ? MXC_SPI0_TXFIFO :      \
+                                          (i) == 1 ? MXC_SPI1_TXFIFO :      \
+                                          (i) == 2 ? MXC_SPI2_TXFIFO : 0)
+
+#define MXC_SPI_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_SPI0)
+#define MXC_SPI_BASE_TO_INSTANCE(base)     (((uint32_t)(base) & 0x00003000) >> 12)
+
+
+/*******************************************************************************/
+/*                                                              UART Interface */
+
+#define MXC_CFG_UART_INSTANCES           (2)
+
+#define MXC_BASE_UART0                   ((uint32_t)0x40038000UL)
+#define MXC_BASE_UART0_BITBAND           ((uint32_t)0x42700000UL)
+#define MXC_UART0                        ((mxc_uart_regs_t *)MXC_BASE_UART0)
+
+#define MXC_BASE_UART1                   ((uint32_t)0x40039000UL)
+#define MXC_BASE_UART1_BITBAND           ((uint32_t)0x42720000UL)
+#define MXC_UART1                        ((mxc_uart_regs_t *)MXC_BASE_UART1)
+
+
+#define MXC_UART_GET_IRQ(i)              ((i) == 0 ? UART0_IRQn :      \
+                                          (i) == 1 ? UART1_IRQn : 0)
+
+#define MXC_UART_GET_BASE(i)             ((i) == 0 ? MXC_BASE_UART0 :     \
+                                          (i) == 1 ? MXC_BASE_UART1 : 0)
+
+#define MXC_UART_GET_UART(i)             ((i) == 0 ? MXC_UART0 :     \
+                                          (i) == 1 ? MXC_UART1 : 0)
+
+#define MXC_UART_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_UART0)
+#define MXC_UART_BASE_TO_INSTANCE(base)     (((uint32_t)(base) & 0x00001000) >> 12)
+
+
+/*******************************************************************************/
+/*                                                        I2C Master Interface */
+
+#define MXC_CFG_I2CM_INSTANCES           (2)
+
+#define MXC_BASE_I2CM0                   ((uint32_t)0x40040000UL)
+#define MXC_BASE_I2CM0_BITBAND           ((uint32_t)0x42800000UL)
+#define MXC_I2CM0                        ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
+#define MXC_BASE_I2CM0_TX_FIFO           ((uint32_t)0x40103000UL)
+#define MXC_BASE_I2CM0_RX_FIFO           ((uint32_t)0x40103800UL)
+
+#define MXC_BASE_I2CM1                   ((uint32_t)0x40042000UL)
+#define MXC_BASE_I2CM1_BITBAND           ((uint32_t)0x42840000UL)
+#define MXC_I2CM1                        ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
+#define MXC_BASE_I2CM1_TX_FIFO           ((uint32_t)0x4010D000UL)
+#define MXC_BASE_I2CM1_RX_FIFO           ((uint32_t)0x4010D800UL)
+
+#define MXC_I2CM_GET_IRQ(i)              ((i) == 0 ? I2CM0_IRQn :      \
+                                          (i) == 1 ? I2CM1_IRQn : 0)
+
+#define MXC_I2CM_GET_BASE(i)             ((i) == 0 ? MXC_BASE_I2CM0 :     \
+                                          (i) == 1 ? MXC_BASE_I2CM1 : 0)
+
+#define MXC_I2CM_GET_I2CM(i)             ((i) == 0 ? MXC_I2CM0 :     \
+                                          (i) == 1 ? MXC_I2CM1 : 0)
+
+#define MXC_I2CM_GET_BASE_TX_FIFO(i)     ((i) == 0 ? MXC_BASE_I2CM0_TX_FIFO :  \
+                                          (i) == 1 ? MXC_BASE_I2CM1_TX_FIFO : 0)
+
+#define MXC_I2CM_GET_BASE_RX_FIFO(i)     ((i) == 0 ? MXC_BASE_I2CM0_RX_FIFO :  \
+                                          (i) == 1 ? MXC_BASE_I2CM1_RX_FIFO : 0)
+
+#define MXC_I2CM_INSTANCE_TO_BASE(instance)   (((uint32_t)(instance) << 13) + MXC_BASE_I2CM0)
+#define MXC_I2CM_BASE_TO_INSTANCE(base)       (((uint32_t)(base) & 0x00002000) >> 13)
+
+
+/*******************************************************************************/
+/*                                                         I2C Slave Interface */
+
+#define MXC_CFG_I2CS_INSTANCES           (1)
+
+#define MXC_BASE_I2CS0                   ((uint32_t)0x40041000UL)
+#define MXC_BASE_I2CS0_BITBAND           ((uint32_t)0x42820000UL)
+#define MXC_I2CS0                        ((mxc_i2cs_regs_t *)MXC_BASE_I2CS0)
+
+#define MXC_BASE_I2CS0_FIFO              ((uint32_t)0x40104000UL)
+#define MXC_I2CS0_FIFO                   ((mxc_i2cs_fifo_regs_t *)MXC_BASE_I2CS0)
+
+
+
+/*******************************************************************************/
+/*                                                                        DACs */
+
+#define MXC_CFG_DAC_INSTANCES            (4)
+#define MXC_CFG_DAC_FIFO_DEPTH           (32)
+
+#define MXC_BASE_DAC0                    ((uint32_t)0x40050000UL)
+#define MXC_DAC0                         ((mxc_dac_regs_t *)MXC_BASE_DAC0)
+#define MXC_BASE_DAC0_FIFO               ((uint32_t)0x40105000UL)
+#define MXC_DAC0_FIFO                    ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC0_FIFO)
+#define MXC_DAC0_WIDTH                   ((uint8_t)(2))
+
+#define MXC_BASE_DAC1                    ((uint32_t)0x40051000UL)
+#define MXC_DAC1                         ((mxc_dac_regs_t *)MXC_BASE_DAC1)
+#define MXC_BASE_DAC1_FIFO               ((uint32_t)0x40106000UL)
+#define MXC_DAC1_FIFO                    ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC1_FIFO)
+#define MXC_DAC1_WIDTH                   ((uint8_t)(2))
+
+#define MXC_BASE_DAC2                    ((uint32_t)0x40052000UL)
+#define MXC_DAC2                         ((mxc_dac_regs_t *)MXC_BASE_DAC2)
+#define MXC_BASE_DAC2_FIFO               ((uint32_t)0x40107000UL)
+#define MXC_DAC2_FIFO                    ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC2_FIFO)
+#define MXC_DAC2_WIDTH                   ((uint8_t)(1))
+
+#define MXC_BASE_DAC3                    ((uint32_t)0x40053000UL)
+#define MXC_DAC3                         ((mxc_dac_regs_t *)MXC_BASE_DAC3)
+#define MXC_BASE_DAC3_FIFO               ((uint32_t)0x40108000UL)
+#define MXC_DAC3_FIFO                    ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC3_FIFO)
+#define MXC_DAC3_WIDTH                   ((uint8_t)(1))
+
+
+#define MXC_DAC_GET_IRQ(i)               ((i) == 0 ? DAC0_IRQn :     \
+                                          (i) == 1 ? DAC1_IRQn :     \
+                                          (i) == 2 ? DAC2_IRQn :     \
+                                          (i) == 3 ? DAC3_IRQn : 0)
+
+
+#define MXC_DAC_GET_BASE(i) (i == 0 ? MXC_BASE_DAC0 : \
+                             i == 1 ? MXC_BASE_DAC1 : \
+                             i == 2 ? MXC_BASE_DAC2 : \
+                             i == 3 ? MXC_BASE_DAC3 : 0)
+
+#define MXC_DAC_GET_FIFO(i) (i == 0 ? MXC_BASE_DAC0_FIFO : \
+                             i == 1 ? MXC_BASE_DAC1_FIFO : \
+                             i == 2 ? MXC_BASE_DAC2_FIFO  : \
+                             i == 3 ? MXC_BASE_DAC3_FIFO  : 0)
+
+#define MXC_DAC_GET_PMU_FIFO_IRQ(i) (i == 0 ? PMU_IRQ_DAC0_FIFO_AE : \
+                                     i == 1 ? PMU_IRQ_DAC1_FIFO_AE : \
+                                     i == 2 ? PMU_IRQ_DAC2_FIFO_AE  : \
+                                     i == 3 ? PMU_IRQ_DAC3_FIFO_AE  : 0)
+
+#define MXC_DAC_GET_DAC(i)  (i == 0 ? MXC_DAC0 : \
+                             i == 1 ? MXC_DAC1 : \
+                             i == 2 ? MXC_DAC2 : \
+                             i == 3 ? MXC_DAC3 : 0)
+
+#define MXC_DAC_GET_WIDTH(i)  (i == 0 ? MXC_DAC0_WIDTH : \
+                               i == 1 ? MXC_DAC1_WIDTH : \
+                               i == 2 ? MXC_DAC2_WIDTH : \
+                               i == 3 ? MXC_DAC3_WIDTH : 0)
+
+
+/*******************************************************************************/
+/*                                                            Analog Front End */
+
+#define MXC_BASE_AFE                     ((uint32_t)0x4005401CUL)
+#define MXC_AFE                          ((mxc_afe_regs_t *)MXC_BASE_AFE)
+
+
+
+/*******************************************************************************/
+/*                                                                         ADC */
+
+#define MXC_CFG_ADC_FIFO_DEPTH           ((uint32_t)(32))
+
+#define MXC_BASE_ADC                     ((uint32_t)0x40054000UL)
+#define MXC_ADC                          ((mxc_adc_regs_t *)MXC_BASE_ADC)
+
+#define MXC_BASE_ADCCFG                  ((uint32_t)0x40054038UL)
+#define MXC_ADCCFG                       ((mxc_adccfg_regs_t *)MXC_BASE_ADCCFG)
+
+#define MXC_BASE_ADC_FIFO                ((uint32_t)0x40109000UL)
+#define MXC_ADC_FIFO                     ((mxc_adc_fifo_regs_t *)MXC_BASE_ADC_FIFO)
+
+
+
+/*******************************************************************************/
+/*                                                                         LCD */
+#define MXC_BASE_LCD                     ((uint32_t)0x40060000)
+#define MXC_LCD                          ((mxc_lcd_regs_t *)MXC_BASE_LCD)
+
+/*******************************************************************************/
+/*                  Peripheral Management Unit (PMU) - formerly DMA Controller */
+
+#define MXC_CFG_PMU_CHANNELS             (6)
+
+#define MXC_BASE_PMU0                    ((uint32_t)0x40070000UL)
+#define MXC_PMU0                         ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
+#define MXC_BASE_PMU1                    ((uint32_t)0x40070020UL)
+#define MXC_PMU1                         ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
+#define MXC_BASE_PMU2                    ((uint32_t)0x40070040UL)
+#define MXC_PMU2                         ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
+#define MXC_BASE_PMU3                    ((uint32_t)0x40070060UL)
+#define MXC_PMU3                         ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
+#define MXC_BASE_PMU4                    ((uint32_t)0x40070080UL)
+#define MXC_PMU4                         ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
+#define MXC_BASE_PMU5                    ((uint32_t)0x400700A0UL)
+#define MXC_PMU5                         ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
+
+#define MXC_BASE_PMU_BITBAND            ((uint32_t)0x42E00000UL)
+#define MXC_BASE_PMU_BITBAND_CHOFFSET   ((uint32_t)0x00000400UL)
+/*******************************************************************************/
+
+typedef enum {
+    PMU_IRQ_DAC0_FIFO_AE,
+    PMU_IRQ_DAC1_FIFO_AE,
+    PMU_IRQ_DAC2_FIFO_AE,
+    PMU_IRQ_DAC3_FIFO_AE,
+    PMU_IRQ_DAC0_DONE,
+    PMU_IRQ_DAC1_DONE,
+    PMU_IRQ_DAC2_DONE,
+    PMU_IRQ_DAC3_DONE,
+    PMU_IRQ_ADC_FIFO_AF,
+    PMU_IRQ_ADC_DONE,
+    PMU_IRQ_I2C_MST0_DONE,
+    PMU_IRQ_I2C_MST1_DONE,
+    PMU_IRQ_SPI0_RSLTS_DONE,
+    PMU_IRQ_SPI1_RSLTS_DONE,
+    PMU_IRQ_SPI2_RSLTS_DONE,
+    PMU_IRQ_MAA_DONE,
+    PMU_IRQ_SPI0_TX_FIFO_AE,
+    PMU_IRQ_SPI0_RSLTS_FIFO_AF,
+    PMU_IRQ_SPI1_TX_FIFO_AE,
+    PMU_IRQ_SPI1_RSLTS_FIFO_AF,
+    PMU_IRQ_SPI2_TX_FIFO_AE,
+    PMU_IRQ_SPI3_RSLTS_FIFO_AF,
+    PMU_IRQ_I2C_MST0_TRANS_FIFO,
+    PMU_IRQ_I2C_MST0_RSLT_FIFO,
+    PMU_IRQ_I2C_MST1_TRANS_FIFO,
+    PMU_IRQ_I2C_MST2_RSLT_FIFO,
+    PMU_IRQ_I2C_SLV_TRANS_FIFO,
+    PMU_IRQ_I2C_SLV_RSLT_FIFO,
+    PMU_IRQ_UART0_TX_FIFO,
+    PMU_IRQ_UART0_RX_FIFO,
+    PMU_IRQ_UART1_TX_FIFO,
+    PMU_IRQ_UART1_RX_FIFO,
+    PMU_IRQ_SPI0_EXCP,
+    PMU_IRQ_SPI1_EXCP,
+    PMU_IRQ_SPI2_EXCP,
+    PMU_IRQ_RSVD0,
+    PMU_IRQ_I2C_MST0_EXCP,
+    PMU_IRQ_I2C_MST1_EXCP,
+    PMU_IRQ_I2C_SLV_EXCP,
+    PMU_IRQ_RSVD1,
+    PMU_IRQ_GPIO0,
+    PMU_IRQ_GPIO1,
+    PMU_IRQ_GPIO2,
+    PMU_IRQ_GPIO3,
+    PMU_IRQ_GPIO4,
+    PMU_IRQ_GPIO5,
+    PMU_IRQ_GPIO6,
+    PMU_IRQ_GPIO7,
+    PMU_IRQ_GPIO8,
+    PMU_IRQ_AFE_COMP_NMI,
+    PMU_IRQ_AES_ENGINE,
+} pmu_int_mask_t;
+
+/*******************************************************************************/
+/*                                                                         USB */
+
+#define MXC_BASE_USB                     ((uint32_t)0x4010C000UL)
+#define MXC_USB                          ((mxc_usb_regs_t *)MXC_BASE_USB)
+
+#define MXC_USB_MAX_PACKET               (64)
+#define MXC_USB_NUM_EP                   (8)
+
+
+/*******************************************************************************/
+/*                                                Instruction Cache Controller */
+
+#define MXC_BASE_ICC                     ((uint32_t)0x40080000UL)
+#define MXC_ICC                          ((mxc_icc_regs_t *)MXC_BASE_ICC)
+
+/*                                                              System Manager */
+
+#define MXC_BASE_SYSMAN                 ((uint32_t)0x40090000UL)
+
+/*******************************************************************************/
+/*                                                               Clock Manager */
+
+#define MXC_BASE_CLKMAN                  ((uint32_t)0x40090400UL)
+#define MXC_CLKMAN                       ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
+
+
+/*******************************************************************************/
+/*                                                               Power Manager */
+
+#define MXC_BASE_PWRMAN                  ((uint32_t)0x40090800UL)
+#define MXC_PWRMAN                       ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
+
+/*******************************************************************************/
+/*                                                                 I/O Manager */
+
+#define MXC_BASE_IOMAN                   ((uint32_t)0x40090C00UL)
+#define MXC_IOMAN                        ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
+
+
+/*******************************************************************************/
+/*                                                           RTC: Timer/Alarms */
+
+#define MXC_BASE_RTCTMR                 ((uint32_t)0x40090A00UL)
+#define MXC_RTCTMR                       ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
+
+#define MXC_RTCTMR_GET_IRQ(i) (i == 0 ? RTC0_IRQn :    \
+                               i == 1 ? RTC1_IRQn :    \
+                               i == 2 ? RTC2_IRQn :    \
+                               i == 3 ? RTC3_IRQn : 0)
+
+#define MXC_BASE_RTCCFG                  ((uint32_t)0x40090A70UL)
+#define MXC_RTCCFG                       ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
+/*******************************************************************************/
+/*                                                        RTC: Power Sequencer */
+
+#define MXC_BASE_PWRSEQ                  ((uint32_t)0x40090A30UL)
+#define MXC_PWRSEQ                       ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
+
+/*******************************************************************************/
+/*                                                       Trim Shadow Registers */
+
+#define MXC_BASE_TRIM                    ((uint32_t)0x400E0000UL)
+#define MXC_TRIM                         ((mxc_ftr_regs_t *)MXC_BASE_TRIM)
+
+/*******************************************************************************/
+/*                                          Flash Memory Controller / Security */
+
+#define MXC_BASE_FLC                     ((uint32_t)0x400F0000UL)
+#define MXC_FLC                          ((mxc_flc_regs_t *)MXC_BASE_FLC)
+#define MXC_BASE_FLC_BITBAND             ((uint32_t)0x43E00000UL)
+#define MXC_FLC_PAGE_SIZE_SHIFT          11
+#define MXC_FLC_PAGE_SIZE                (1 << MXC_FLC_PAGE_SIZE_SHIFT)
+#define MXC_FLC_PAGE_ERASE_MSK           ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
+
+/*******************************************************************************/
+
+#define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set))
+
+/*******************************************************************************/
+
+#define BITBAND(reg, bit)        ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
+#define BITBAND_ClrBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 0
+#define BITBAND_SetBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 1
+#define BITBAND_GetBit(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
+
+/*******************************************************************************/
+
+#endif  /* _MAX32600_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pmu_regs.h

@@ -0,0 +1,111 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_PMU_REGS_H_
+#define _MXC_PMU_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  pmu_regs.h
+ * @addtogroup pmu PMU
+ * @{
+ */
+
+/*                                     Offset   Register Description
+                                       ======   ======================================================== */
+typedef struct {
+    __IO uint32_t dscadr;          /*  0x0000   Starting Descriptor Address                              */
+    __IO uint32_t cfg;             /*  0x0004   Channel Configuration                                    */
+    __IO uint32_t loop;            /*  0x0008   Channel Loop Counters                                    */
+    __IO uint32_t op;              /*  0x000C   Current Descriptor DWORD 0 (OP)                          */
+    __IO uint32_t dsc1;            /*  0x0010   Current Descriptor DWORD 1                               */
+    __IO uint32_t dsc2;            /*  0x0014   Current Descriptor DWORD 2                               */
+    __IO uint32_t dsc3;            /*  0x0018   Current Descriptor DWORD 3                               */
+    __IO uint32_t dsc4;            /*  0x001C   Current Descriptor DWORD 4                               */
+} mxc_pmu_regs_t;
+
+/*
+   Register offsets for module PMU.
+*/
+#define MXC_R_PMU_OFFS_DSCADR                     ((uint32_t)0x00000000UL)
+#define MXC_R_PMU_OFFS_CFG                        ((uint32_t)0x00000004UL)
+#define MXC_R_PMU_OFFS_LOOP                       ((uint32_t)0x00000008UL)
+#define MXC_R_PMU_OFFS_OP                         ((uint32_t)0x0000000CUL)
+#define MXC_R_PMU_OFFS_DSC1                       ((uint32_t)0x00000010UL)
+#define MXC_R_PMU_OFFS_DSC2                       ((uint32_t)0x00000014UL)
+#define MXC_R_PMU_OFFS_DSC3                       ((uint32_t)0x00000018UL)
+#define MXC_R_PMU_OFFS_DSC4                       ((uint32_t)0x0000001CUL)
+
+/*
+   Field positions and masks for module PMU.
+*/
+#define MXC_F_PMU_CFG_ENABLE_POS                            0
+#define MXC_F_PMU_CFG_ENABLE                                ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS))
+#define MXC_F_PMU_CFG_LL_STOPPED_POS                        2
+#define MXC_F_PMU_CFG_LL_STOPPED                            ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS))
+#define MXC_F_PMU_CFG_MANUAL_POS                            3
+#define MXC_F_PMU_CFG_MANUAL                                ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS))
+#define MXC_F_PMU_CFG_BUS_ERROR_POS                         4
+#define MXC_F_PMU_CFG_BUS_ERROR                             ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS))
+#define MXC_F_PMU_CFG_TO_STAT_POS                           6
+#define MXC_F_PMU_CFG_TO_STAT                               ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS))
+#define MXC_F_PMU_CFG_TO_SEL_POS                            11
+#define MXC_F_PMU_CFG_TO_SEL                                ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS))
+#define MXC_F_PMU_CFG_PS_SEL_POS                            14
+#define MXC_F_PMU_CFG_PS_SEL                                ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS))
+#define MXC_F_PMU_CFG_INTERRUPT_POS                         16
+#define MXC_F_PMU_CFG_INTERRUPT                             ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS))
+#define MXC_F_PMU_CFG_INT_EN_POS                            17
+#define MXC_F_PMU_CFG_INT_EN                                ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS))
+#define MXC_F_PMU_CFG_BURST_SIZE_POS                        24
+#define MXC_F_PMU_CFG_BURST_SIZE                            ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS))
+
+#define MXC_F_PMU_LOOP_COUNTER_0_POS                        0
+#define MXC_F_PMU_LOOP_COUNTER_0                            ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS))
+#define MXC_F_PMU_LOOP_COUNTER_1_POS                        16
+#define MXC_F_PMU_LOOP_COUNTER_1                            ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_PMU_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pt_regs.h

@@ -0,0 +1,175 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_PT_REGS_H_
+#define _MXC_PT_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  pt_regs.h
+ * @addtogroup pt PT
+ * @{
+ */
+
+typedef struct {
+    __IO uint32_t ctrl;
+    __IO uint32_t resync;
+} mxc_ptg_regs_t;
+
+/*                                      Offset   Register Description
+                                        ======   ================================================== */
+typedef struct {
+    __IO uint32_t rate_length;      /*  0x0000   Pulse train Output length and rate                 */
+    __IO uint32_t train;            /*  0x0004   Pulse Train Output Pattern                         */
+} mxc_pt_regs_t;
+
+/*
+   Register offsets for module PT.
+*/
+#define MXC_R_PTG_OFFS_CTRL                         ((uint32_t)0x00000000UL)
+#define MXC_R_PTG_OFFS_RESYNC                       ((uint32_t)0x00000004UL)
+#define MXC_R_PT_OFFS_RATE_LENGTH                   ((uint32_t)0x00000000UL)
+#define MXC_R_PT_OFFS_TRAIN                         ((uint32_t)0x00000004UL)
+
+
+/*
+   Field positions and masks for module PT.
+*/
+#define MXC_F_PT_CTRL_ENABLE_ALL_POS                1
+#define MXC_F_PT_CTRL_ENABLE_ALL                    ((uint32_t)(0x00000001UL << MXC_F_PT_CTRL_ENABLE_ALL_POS))
+
+#define MXC_F_PT_RESYNC_PT0_POS                     0
+#define MXC_F_PT_RESYNC_PT0                         ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT0_POS))
+#define MXC_F_PT_RESYNC_PT1_POS                     1
+#define MXC_F_PT_RESYNC_PT1                         ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT1_POS))
+#define MXC_F_PT_RESYNC_PT2_POS                     2
+#define MXC_F_PT_RESYNC_PT2                         ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT2_POS))
+#define MXC_F_PT_RESYNC_PT3_POS                     3
+#define MXC_F_PT_RESYNC_PT3                         ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT3_POS))
+#define MXC_F_PT_RESYNC_PT4_POS                     4
+#define MXC_F_PT_RESYNC_PT4                         ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT4_POS))
+#define MXC_F_PT_RESYNC_PT5_POS                     5
+#define MXC_F_PT_RESYNC_PT5                         ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT5_POS))
+#define MXC_F_PT_RESYNC_PT6_POS                     6
+#define MXC_F_PT_RESYNC_PT6                         ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT6_POS))
+#define MXC_F_PT_RESYNC_PT7_POS                     7
+#define MXC_F_PT_RESYNC_PT7                         ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT7_POS))
+
+#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS       0
+#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL           ((uint32_t)(0x07FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS))
+#define MXC_F_PT_RATE_LENGTH_MODE_POS               27
+#define MXC_F_PT_RATE_LENGTH_MODE                   ((uint32_t)(0x0000001FUL << MXC_F_PT_RATE_LENGTH_MODE_POS))
+
+/*
+   Field values and shifted values for module PT.
+*/
+#define MXC_V_PT_RATE_LENGTH_MODE_32_BIT_PATTERN    ((uint32_t)(0x0x00000000UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE       ((uint32_t)(0x0x00000001UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_2_BIT_PATTERN     ((uint32_t)(0x0x00000002UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_3_BIT_PATTERN     ((uint32_t)(0x0x00000003UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_4_BIT_PATTERN     ((uint32_t)(0x0x00000004UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_5_BIT_PATTERN     ((uint32_t)(0x0x00000005UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_6_BIT_PATTERN     ((uint32_t)(0x0x00000006UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_7_BIT_PATTERN     ((uint32_t)(0x0x00000007UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_8_BIT_PATTERN     ((uint32_t)(0x0x00000008UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_9_BIT_PATTERN     ((uint32_t)(0x0x00000009UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_10_BIT_PATTERN    ((uint32_t)(0x0x00000010UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_11_BIT_PATTERN    ((uint32_t)(0x0x00000011UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_12_BIT_PATTERN    ((uint32_t)(0x0x00000012UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_13_BIT_PATTERN    ((uint32_t)(0x0x00000013UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_14_BIT_PATTERN    ((uint32_t)(0x0x00000014UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_15_BIT_PATTERN    ((uint32_t)(0x0x00000015UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_16_BIT_PATTERN    ((uint32_t)(0x0x00000016UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_17_BIT_PATTERN    ((uint32_t)(0x0x00000017UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_18_BIT_PATTERN    ((uint32_t)(0x0x00000018UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_19_BIT_PATTERN    ((uint32_t)(0x0x00000019UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_20_BIT_PATTERN    ((uint32_t)(0x0x00000020UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_21_BIT_PATTERN    ((uint32_t)(0x0x00000021UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_22_BIT_PATTERN    ((uint32_t)(0x0x00000022UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_23_BIT_PATTERN    ((uint32_t)(0x0x00000023UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_24_BIT_PATTERN    ((uint32_t)(0x0x00000024UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_25_BIT_PATTERN    ((uint32_t)(0x0x00000025UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_26_BIT_PATTERN    ((uint32_t)(0x0x00000026UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_27_BIT_PATTERN    ((uint32_t)(0x0x00000027UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_28_BIT_PATTERN    ((uint32_t)(0x0x00000028UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_29_BIT_PATTERN    ((uint32_t)(0x0x00000029UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_30_BIT_PATTERN    ((uint32_t)(0x0x00000030UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_31_BIT_PATTERN    ((uint32_t)(0x0x00000031UL))
+
+#define MXC_S_PT_RATE_LENGTH_MODE_32_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_32_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE       ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE      << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_2_BIT_PATTERN     ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_2_BIT_PATTERN    << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_3_BIT_PATTERN     ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_3_BIT_PATTERN    << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_4_BIT_PATTERN     ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_4_BIT_PATTERN    << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_5_BIT_PATTERN     ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_5_BIT_PATTERN    << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_6_BIT_PATTERN     ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_6_BIT_PATTERN    << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_7_BIT_PATTERN     ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_7_BIT_PATTERN    << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_8_BIT_PATTERN     ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_8_BIT_PATTERN    << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_9_BIT_PATTERN     ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_9_BIT_PATTERN    << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_10_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_10_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_11_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_11_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_12_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_12_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_13_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_13_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_14_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_14_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_15_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_15_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_16_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_16_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_17_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_17_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_18_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_18_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_19_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_19_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_20_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_20_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_21_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_21_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_22_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_22_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_23_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_23_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_24_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_24_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_25_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_25_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_26_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_26_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_27_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_27_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_28_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_28_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_29_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_29_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_30_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_30_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_31_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_31_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_PT_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrman_regs.h

@@ -0,0 +1,386 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_PWRMAN_REGS_H_
+#define _MXC_PWRMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  pwrman_regs.h
+ * @addtogroup pwrman PWRMAN
+ * @{
+ */
+
+/**
+ * @brief Defines PAD Modes for Wake Up Detection.
+ */
+typedef enum {
+    /** WUD Mode for Selected PAD = Clear/Activate */
+    MXC_E_PWRMAN_PAD_MODE_CLEAR_SET,
+    /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */
+    MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO,
+    /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */
+    MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO,
+    /** WUD Mode for Selected PAD = No pad state change */
+    MXC_E_PWRMAN_PAD_MODE_NONE
+} mxc_pwrman_pad_mode_t;
+
+/*                                          Offset   Register Description
+                                            ======   =========================================== */
+typedef struct {
+    __IO uint32_t pwr_rst_ctrl;         /*  0x0000   Power Reset Control and Status              */
+    __IO uint32_t intfl;                /*  0x0004   Interrupt Flags                             */
+    __IO uint32_t inten;                /*  0x0008   Interrupt Enable/Disable Controls           */
+    __IO uint32_t svm_events;           /*  0x000C   SVM Event Status Flags (read-only)          */
+    __IO uint32_t wud_ctrl;             /*  0x0010   Wake-Up Detect Control                      */
+    __IO uint32_t wud_pulse0;           /*  0x0014   WUD Pulse To Mode Bit 0                     */
+    __IO uint32_t wud_pulse1;           /*  0x0018   WUD Pulse To Mode Bit 1                     */
+    __I uint32_t rsv001C[5];            /*  0x001C                                               */
+
+    __IO uint32_t wud_seen0;            /*  0x0030   Wake-up Detect Status for P0/P1/P2/P3       */
+    __IO uint32_t wud_seen1;            /*  0x0034   Wake-up Detect Status for P4/P5/P6/P7       */
+    __IO uint32_t die_type;             /*  0x0038   Die ID Register (Device Type)               */
+    __IO uint32_t base_part_num;        /*  0x003C   Base Part Number                            */
+    __IO uint32_t mask_id0;             /*  0x0040   Mask ID Register 0                          */
+    __IO uint32_t mask_id1;             /*  0x0044   Mask ID Register 1                          */
+    __IO uint32_t peripheral_reset;     /*  0x0048   Peripheral Reset Control Register           */
+} mxc_pwrman_regs_t;
+
+/*
+   Register offsets for module PWRMAN.
+*/
+#define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL          ((uint32_t)0x00000000UL)
+#define MXC_R_PWRMAN_OFFS_INTFL                 ((uint32_t)0x00000004UL)
+#define MXC_R_PWRMAN_OFFS_INTEN                 ((uint32_t)0x00000008UL)
+#define MXC_R_PWRMAN_OFFS_SVM_EVENTS            ((uint32_t)0x0000000CUL)
+#define MXC_R_PWRMAN_OFFS_WUD_CTRL              ((uint32_t)0x00000010UL)
+#define MXC_R_PWRMAN_OFFS_WUD_PULSE0            ((uint32_t)0x00000014UL)
+#define MXC_R_PWRMAN_OFFS_WUD_PULSE1            ((uint32_t)0x00000018UL)
+#define MXC_R_PWRMAN_OFFS_WUD_SEEN0             ((uint32_t)0x00000030UL)
+#define MXC_R_PWRMAN_OFFS_WUD_SEEN1             ((uint32_t)0x00000034UL)
+#define MXC_R_PWRMAN_OFFS_DIE_TYPE              ((uint32_t)0x00000038UL)
+#define MXC_R_PWRMAN_OFFS_BASE_PART_NUM         ((uint32_t)0x0000003CUL)
+#define MXC_R_PWRMAN_OFFS_MASK_ID0              ((uint32_t)0x00000040UL)
+#define MXC_R_PWRMAN_OFFS_MASK_ID1              ((uint32_t)0x00000044UL)
+#define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET      ((uint32_t)0x00000048UL)
+
+/*
+   Field positions and masks for module PWRMAN.
+*/
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS          0
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE              ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS           1
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE               ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS           2
+#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED               ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS             3
+#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS           4
+#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED               ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS       5
+#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED           ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS        8
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET            ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS      9
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET          ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS             12
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS         16
+#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT             ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS     17
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN         ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS      18
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT          ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS        19
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM            ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS            20
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS       21
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION           ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS                   22
+#define MXC_F_PWRMAN_PWR_RST_CTRL_POR                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS        31
+#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE            ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS))
+
+#define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS                 0
+#define MXC_F_PWRMAN_INTFL_V1_8_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS                 1
+#define MXC_F_PWRMAN_INTFL_V3_3_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS                  2
+#define MXC_F_PWRMAN_INTFL_RTC_WARNING                      ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_V3_3_RESET_POS                   3
+#define MXC_F_PWRMAN_INTFL_V3_3_RESET                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_RESET_POS))
+#define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS                 4
+#define MXC_F_PWRMAN_INTFL_VDDA_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS))
+
+#define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS                 0
+#define MXC_F_PWRMAN_INTEN_V1_8_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS                 1
+#define MXC_F_PWRMAN_INTEN_V3_3_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS                  2
+#define MXC_F_PWRMAN_INTEN_RTC_WARNING                      ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_V3_3_RESET_POS                   3
+#define MXC_F_PWRMAN_INTEN_V3_3_RESET                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_RESET_POS))
+#define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS                 4
+#define MXC_F_PWRMAN_INTEN_VDDA_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS))
+
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS            0
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS            1
+#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS             2
+#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS              3
+#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS            4
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS))
+
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS                0
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT                    ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS))
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS                  8
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE                      ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS))
+#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS                 12
+#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS))
+
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS                    0
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS                    1
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS                    2
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS                    3
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS                    4
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS                    5
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS                    6
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS                    7
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS                    8
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS                    9
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS                   10
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS                   11
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS                   12
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS                   13
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS                   14
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS                   15
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS                   16
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS                   17
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS                   18
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS                   19
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS                   20
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS                   21
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS                   22
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS                   23
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS                   24
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS                   25
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS                   26
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS                   27
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS                   28
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS                   29
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS                   30
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS                   31
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS))
+
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS                   0
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS                   1
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS                   2
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS                   3
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS                   4
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS                   5
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS                   6
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS                   7
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS                   8
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS                   9
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS                   10
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS                   11
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS                   12
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS                   13
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS                   14
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS                   15
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS                   16
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS                   17
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS                   18
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS                   19
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS                   20
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS                   21
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS                   22
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS                   23
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS                   24
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS                   25
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS                   26
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS                   27
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS                   28
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS                   29
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS                   30
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS                   31
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS))
+
+#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS     0
+#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER         ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS))
+#define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS       28
+#define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT           ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS))
+
+#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS               0
+#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID                   ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS))
+#define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS                   4
+#define MXC_F_PWRMAN_MASK_ID0_MASK_ID                       ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS))
+
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS                   0
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID                       ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS))
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS            31
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS))
+
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS             0
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS             1
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS            2
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS            3
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS            4
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS            5
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS         6
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0             ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS               7
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS               8
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS              9
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS              10
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS              11
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS              12
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS               13
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS               14
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS              15
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS       16
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN           ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS              17
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS              18
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS              19
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS             20
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS             21
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS              22
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS               23
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS               24
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS               25
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_PWRMAN_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrseq_regs.h

@@ -0,0 +1,299 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_PWRSEQ_REGS_H
+#define _MXC_PWRSEQ_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  pwrseq_regs.h
+ * @addtogroup pwrseq PWRSEQ
+ * @{
+ */
+
+/*                                      Offset   Register Description
+                                        ======   ================================================= */
+typedef struct {
+    __IO uint32_t reg0;             /*  0x0000   Power Sequencer Control Register 0                */
+    __IO uint32_t reg1;             /*  0x0004   Power Sequencer Control Register 1                */
+    __IO uint32_t reg2;             /*  0x0008   Power Sequencer Control Register 2                */
+    __IO uint32_t reg3;             /*  0x000C   Power Sequencer Control Register 3                */
+    __IO uint32_t reg4;             /*  0x0010   Power Sequencer Control Register 4                */
+    __IO uint32_t reg5;             /*  0x0014   Power Sequencer Control Register 5 (Trim 0)       */
+    __IO uint32_t reg6;             /*  0x0018   Power Sequencer Control Register 6 (Trim 1)       */
+    __I uint32_t rsv001C;           /*  0x001C                                                     */
+    __IO uint32_t flags;            /*  0x0020   Power Sequencer Flags                             */
+    __IO uint32_t msk_flags;        /*  0x0024   Power Sequencer Flags Mask Register               */
+} mxc_pwrseq_regs_t;
+
+
+/*
+   Register offsets for module PWRSEQ.
+*/
+#define MXC_R_PWRSEQ_OFFS_REG0                    ((uint32_t)0x00000000UL)
+#define MXC_R_PWRSEQ_OFFS_REG1                    ((uint32_t)0x00000004UL)
+#define MXC_R_PWRSEQ_OFFS_REG2                    ((uint32_t)0x00000008UL)
+#define MXC_R_PWRSEQ_OFFS_REG3                    ((uint32_t)0x0000000CUL)
+#define MXC_R_PWRSEQ_OFFS_REG4                    ((uint32_t)0x00000010UL)
+#define MXC_R_PWRSEQ_OFFS_REG5                    ((uint32_t)0x00000014UL)
+#define MXC_R_PWRSEQ_OFFS_REG6                    ((uint32_t)0x00000018UL)
+#define MXC_R_PWRSEQ_OFFS_FLAGS                   ((uint32_t)0x00000020UL)
+#define MXC_R_PWRSEQ_OFFS_MSK_FLAGS               ((uint32_t)0x00000024UL)
+
+
+/*
+   Field positions and masks for module PWRSEQ.
+*/
+#define MXC_F_PWRSEQ_REG0_PWR_LP1_POS                       0
+#define MXC_F_PWRSEQ_REG0_PWR_LP1                           ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS                1
+#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS                2
+#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS                 3
+#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS                 4
+#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS                5
+#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS                6
+#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS                  7
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS                  8
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS                  9
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS                  10
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS                 11
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS                 12
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS                13
+#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS                14
+#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS                15
+#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS                16
+#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS              17
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS              18
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS                19
+#define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS))
+
+#define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS                0
+#define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG                    ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS                  8
+#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS            9
+#define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS                  10
+#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS              11
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS             12
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS             13
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS               14
+#define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS))
+
+#define MXC_F_PWRSEQ_REG2_PWR_RST3_POS                      0
+#define MXC_F_PWRSEQ_REG2_PWR_RST3                          ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_RST3_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_W3_POS                        5
+#define MXC_F_PWRSEQ_REG2_PWR_W3                            ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W3_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_W1_POS                        10
+#define MXC_F_PWRSEQ_REG2_PWR_W1                            ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS                    15
+#define MXC_F_PWRSEQ_REG2_PWR_W1_LOW                        ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_WRTC_POS                      20
+#define MXC_F_PWRSEQ_REG2_PWR_WRTC                          ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_WRTC_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS                    25
+#define MXC_F_PWRSEQ_REG2_PWR_WVDDA3                        ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS))
+
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS                     0
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL                         ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS               3
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK                   ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS                    5
+#define MXC_F_PWRSEQ_REG3_PWR_SVMSEL                        ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS            8
+#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO                ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS              10
+#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL                  ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS               13
+#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX                   ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS                15
+#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS                 16
+#define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS                     17
+#define MXC_F_PWRSEQ_REG3_PWR_BO_TC                         ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS))
+
+#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS              0
+#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS            1
+#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS             2
+#define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS              3
+#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS           4
+#define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS               5
+#define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS               6
+#define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS))
+
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS               0
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG                   ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS               6
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8                   ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS               10
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3                   ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS             15
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF                 ((uint32_t)(0x0000007FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS))
+
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS             0
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS                 ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS           3
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES               ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS           7
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES               ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
+
+#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS               0
+#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS               1
+#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS             2
+#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS            3
+#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS              4
+#define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS                5
+#define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS                 6
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS                7
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS                 8
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS             9
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS                10
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS                11
+#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS               12
+#define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS                    13
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0                        ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS                    14
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1                        ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS             15
+#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS                 16
+#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS             17
+#define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS          18
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP              ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS        19
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS                20
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS               21
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS))
+
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS           1
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS         2
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS        3
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS          4
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP              ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS            5
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS             6
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS            7
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS             8
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS         9
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS            10
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS            11
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS           12
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS                13
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS                14
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS         15
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS             16
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS         17
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS      18
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP          ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS    19
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP        ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS            20
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS           21
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_PWRSEQ_REGS_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/rtc_regs.h

@@ -0,0 +1,246 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_RTC_REGS_H
+#define _MXC_RTC_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  rtc_regs.h
+ * @addtogroup rtc RTCTMR
+ * @{
+ */
+
+/**
+ * @brief Defines clock divider for 4096Hz input clock.
+ */
+typedef enum {
+    /** (4kHz) divide input clock by 2^0 = 1 */
+    MXC_E_RTC_PRESCALE_DIV_2_0 = 0,
+    /** (2kHz) divide input clock by 2^1 = 2 */
+    MXC_E_RTC_PRESCALE_DIV_2_1,
+    /** (1kHz) divide input clock by 2^2 = 4 */
+    MXC_E_RTC_PRESCALE_DIV_2_2,
+    /** (512Hz) divide input clock by 2^3 = 8 */
+    MXC_E_RTC_PRESCALE_DIV_2_3,
+    /** (256Hz) divide input clock by 2^4 = 16 */
+    MXC_E_RTC_PRESCALE_DIV_2_4,
+    /** (128Hz) divide input clock by 2^5 = 32 */
+    MXC_E_RTC_PRESCALE_DIV_2_5,
+    /** (64Hz) divide input clock by 2^6 = 64 */
+    MXC_E_RTC_PRESCALE_DIV_2_6,
+    /** (32Hz) divide input clock by 2^7 = 128 */
+    MXC_E_RTC_PRESCALE_DIV_2_7,
+    /** (16Hz) divide input clock by 2^8 = 256 */
+    MXC_E_RTC_PRESCALE_DIV_2_8,
+    /** (8Hz) divide input clock by 2^9 = 512 */
+    MXC_E_RTC_PRESCALE_DIV_2_9,
+    /** (4Hz) divide input clock by 2^10 = 1024 */
+    MXC_E_RTC_PRESCALE_DIV_2_10,
+    /** (2Hz) divide input clock by 2^11 = 2048 */
+    MXC_E_RTC_PRESCALE_DIV_2_11,
+    /** (1Hz) divide input clock by 2^12 = 4096 */
+    MXC_E_RTC_PRESCALE_DIV_2_12,
+} mxc_rtc_prescale_t;
+
+/*                                          Offset   Register Description
+                                            ======   ========================================= */
+typedef struct {
+    __IO uint32_t ctrl;                 /*  0x0000   RTC Timer Control                         */
+    __IO uint32_t timer;                /*  0x0004   RTC Timer Count Value                     */
+    __IO uint32_t comp[2];              /*  0x0008   RTC Alarm (0..1) Compare Registers        */
+    __IO uint32_t flags;                /*  0x0010   CPU Interrupt and RTC Domain Flags        */
+    __I uint32_t rsv0014;               /*  0x0014                                             */
+    __IO uint32_t inten;                /*  0x0018   Interrupt Enable Controls                 */
+    __IO uint32_t prescale;             /*  0x001C   RTC Timer Prescale Setting                */
+    __I uint32_t rsv0020;               /*  0x0020                                             */
+    __IO uint32_t prescale_mask;        /*  0x0024   RTC Timer Prescale Compare Mask           */
+    __IO uint32_t trim_ctrl;            /*  0x0028   RTC Timer Trim Controls                   */
+    __IO uint32_t trim_value;           /*  0x002C   RTC Timer Trim Adjustment Interval        */
+} mxc_rtctmr_regs_t;
+
+/*
+   Register offsets for module RTCTMR.
+*/
+#define MXC_R_RTCTMR_OFFS_CTRL                    ((uint32_t)0x00000000UL)
+#define MXC_R_RTCTMR_OFFS_TIMER                   ((uint32_t)0x00000004UL)
+#define MXC_R_RTCTMR_OFFS_COMP_0                  ((uint32_t)0x00000008UL)
+#define MXC_R_RTCTMR_OFFS_COMP_1                  ((uint32_t)0x0000000CUL)
+#define MXC_R_RTCTMR_OFFS_FLAGS                   ((uint32_t)0x00000010UL)
+#define MXC_R_RTCTMR_OFFS_INTEN                   ((uint32_t)0x00000018UL)
+#define MXC_R_RTCTMR_OFFS_PRESCALE                ((uint32_t)0x0000001CUL)
+#define MXC_R_RTCTMR_OFFS_PRESCALE_MASK           ((uint32_t)0x00000024UL)
+#define MXC_R_RTCTMR_OFFS_TRIM_CTRL               ((uint32_t)0x00000028UL)
+#define MXC_R_RTCTMR_OFFS_TRIM_VALUE              ((uint32_t)0x0000002CUL)
+
+/*
+   Field positions and masks for module RTCTMR.
+*/
+#define MXC_F_RTC_CTRL_ENABLE_POS                           0
+#define MXC_F_RTC_CTRL_ENABLE                               ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS))
+#define MXC_F_RTC_CTRL_CLEAR_POS                            1
+#define MXC_F_RTC_CTRL_CLEAR                                ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS))
+#define MXC_F_RTC_CTRL_PENDING_POS                          2
+#define MXC_F_RTC_CTRL_PENDING                              ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS))
+#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS                  3
+#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS                      ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS))
+#define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS                   4
+#define MXC_F_RTC_CTRL_AGGRESSIVE_RST                       ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS))
+#define MXC_F_RTC_CTRL_EN_ACTIVE_POS                        16
+#define MXC_F_RTC_CTRL_EN_ACTIVE                            ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_EN_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS              17
+#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE                  ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS            18
+#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE                ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS               19
+#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE                   ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_SET_ACTIVE_POS                       20
+#define MXC_F_RTC_CTRL_SET_ACTIVE                           ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_SET_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_CLR_ACTIVE_POS                       21
+#define MXC_F_RTC_CTRL_CLR_ACTIVE                           ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLR_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS              22
+#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE                  ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS            23
+#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE                ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS           24
+#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE               ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS                 25
+#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE                     ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS                 26
+#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE                     ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS))
+
+#define MXC_F_RTC_FLAGS_COMP0_POS                           0
+#define MXC_F_RTC_FLAGS_COMP0                               ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS))
+#define MXC_F_RTC_FLAGS_COMP1_POS                           1
+#define MXC_F_RTC_FLAGS_COMP1                               ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS))
+#define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS                   2
+#define MXC_F_RTC_FLAGS_PRESCALE_COMP                       ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS))
+#define MXC_F_RTC_FLAGS_OVERFLOW_POS                        3
+#define MXC_F_RTC_FLAGS_OVERFLOW                            ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS))
+#define MXC_F_RTC_FLAGS_TRIM_POS                            4
+#define MXC_F_RTC_FLAGS_TRIM                                ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS))
+#define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS                    8
+#define MXC_F_RTC_FLAGS_COMP0_FLAG_A                        ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS                    9
+#define MXC_F_RTC_FLAGS_COMP1_FLAG_A                        ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS                   10
+#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A                       ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS                 11
+#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A                     ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS                     12
+#define MXC_F_RTC_FLAGS_TRIM_FLAG_A                         ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS                 31
+#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS                     ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS))
+
+#define MXC_F_RTC_INTEN_COMP0_POS                           0
+#define MXC_F_RTC_INTEN_COMP0                               ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS))
+#define MXC_F_RTC_INTEN_COMP1_POS                           1
+#define MXC_F_RTC_INTEN_COMP1                               ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS))
+#define MXC_F_RTC_INTEN_PRESCALE_COMP_POS                   2
+#define MXC_F_RTC_INTEN_PRESCALE_COMP                       ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS))
+#define MXC_F_RTC_INTEN_OVERFLOW_POS                        3
+#define MXC_F_RTC_INTEN_OVERFLOW                            ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS))
+#define MXC_F_RTC_INTEN_TRIM_POS                            4
+#define MXC_F_RTC_INTEN_TRIM                                ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS))
+
+#define MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS              0
+#define MXC_F_RTC_PRESCALE_WIDTH_SELECTION                  ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS))
+
+#define MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS               0
+#define MXC_F_RTC_PRESCALE_MASK_COMP_MASK                   ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS))
+
+#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS               0
+#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R                   ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS))
+#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS           1
+#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R               ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS))
+#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS               2
+#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R                   ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS))
+
+#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS                 0
+#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE                     ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS))
+#define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS               18
+#define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL                   ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS))
+
+#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS            0
+#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER                ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS))
+
+#define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS                      0
+#define MXC_F_RTC_CLK_CTRL_OSC1_EN                          ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS))
+#define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS                      1
+#define MXC_F_RTC_CLK_CTRL_OSC2_EN                          ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS))
+#define MXC_F_RTC_CLK_CTRL_NANO_EN_POS                      2
+#define MXC_F_RTC_CLK_CTRL_NANO_EN                          ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS))
+
+#define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS                0
+#define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE                    ((uint32_t)(0x00000001UL << MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS))
+
+#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS                   0
+#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS                       ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS))
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS                1
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R                    ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS))
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS              2
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL                  ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS))
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS                3
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O                    ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS))
+
+/*                                      Offset   Register Description
+                                        ======   ===================================================================== */
+typedef struct {
+    __IO uint32_t nano_counter;     /*  0x0000   Nanoring Counter Read Register                                        */
+    __IO uint32_t clk_ctrl;         /*  0x0004   RTC Clock Control Settings                                            */
+    __IO uint32_t dsen_ctrl;        /*  0x0008   Dynamic Tamper Sensor Control                                         */
+    __IO uint32_t osc_ctrl;         /*  0x000C   RTC Oscillator Control                                                */
+} mxc_rtccfg_regs_t;
+
+/*
+   Register offsets for module RTCCFG.
+*/
+#define MXC_R_RTCCFG_OFFS_NANO_COUNTER            ((uint32_t)0x00000000UL)
+#define MXC_R_RTCCFG_OFFS_CLK_CTRL                ((uint32_t)0x00000004UL)
+#define MXC_R_RTCCFG_OFFS_DSEN_CTRL               ((uint32_t)0x00000008UL)
+#define MXC_R_RTCCFG_OFFS_OSC_CTRL                ((uint32_t)0x0000000CUL)
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_RTC_REGS_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/spi_regs.h

@@ -0,0 +1,215 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_SPI_REGS_H
+#define _MXC_SPI_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  spi_regs.h
+ * @addtogroup spi SPI
+ * @{
+ */
+
+/*                                       Offset   Register Description
+                                         ======   ============================================ */
+typedef struct {
+    __IO uint32_t mstr_cfg;          /*  0x0000   SPI Master Configuration Register            */
+    __IO uint32_t ss_sr_polarity;    /*  0x0004   Polarity Control for SS and SR Signals       */
+    __IO uint32_t gen_ctrl;          /*  0x0008   SPI Master General Control Register          */
+    __IO uint32_t fifo_ctrl;         /*  0x000C   SPI Master FIFO Control Register             */
+    __IO uint32_t spcl_ctrl;         /*  0x0010   SPI Master Special Mode Controls             */
+    __IO uint32_t intfl;             /*  0x0014   SPI Master Interrupt Flags                   */
+    __IO uint32_t inten;             /*  0x0018   SPI Master Interrupt Enable/Disable Settings */
+    __I uint32_t rsv001C;            /*  0x001C   Deprecated - was SPI_AHB_RETRY               */
+} mxc_spi_regs_t;
+
+/**
+ * @brief TX FIFO register. Can do 8, 16, or 32 bit access.
+ */
+typedef struct {
+    union {
+        __O uint8_t txfifo_8;
+        __O uint16_t txfifo_16;
+        __O uint32_t txfifo_32;
+    };
+} mxc_spi_txfifo_regs_t;
+
+/**
+ * @brief RX FIFO register. Can do 8, 16, or 32 bit access.
+ */
+typedef struct {
+    union {
+        __I uint8_t rxfifo_8;
+        __I uint16_t rxfifo_16;
+        __I uint32_t rxfifo_32;
+    };
+} mxc_spi_rxfifo_regs_t;
+
+/*
+   Register offsets for module SPI.
+*/
+#define MXC_R_SPI_OFFS_MSTR_CFG                   ((uint32_t)0x00000000UL)
+#define MXC_R_SPI_OFFS_SS_SR_POLARITY             ((uint32_t)0x00000004UL)
+#define MXC_R_SPI_OFFS_GEN_CTRL                   ((uint32_t)0x00000008UL)
+#define MXC_R_SPI_OFFS_FIFO_CTRL                  ((uint32_t)0x0000000CUL)
+#define MXC_R_SPI_OFFS_SPCL_CTRL                  ((uint32_t)0x00000010UL)
+#define MXC_R_SPI_OFFS_INTFL                      ((uint32_t)0x00000014UL)
+#define MXC_R_SPI_OFFS_INTEN                      ((uint32_t)0x00000018UL)
+
+#define MXC_R_SPI_FIFO_OFFS_TRANS                 ((uint32_t)0x00000000UL)
+#define MXC_R_SPI_FIFO_OFFS_RSLTS                 ((uint32_t)0x00000800UL)
+
+/*
+   Field positions and masks for module SPI.
+*/
+#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS                    0
+#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL                        ((uint32_t)(0x00000007UL << MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS))
+#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS              3
+#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE                  ((uint32_t)(0x00000001UL << MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS))
+#define MXC_F_SPI_MSTR_CFG_SPI_MODE_POS                     4
+#define MXC_F_SPI_MSTR_CFG_SPI_MODE                         ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS))
+#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS                    6
+#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE                        ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS))
+#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS                   8
+#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK                       ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS))
+#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS                   12
+#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK                       ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS))
+#define MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS                    16
+#define MXC_F_SPI_MSTR_CFG_ACT_DELAY                        ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS))
+#define MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS                  18
+#define MXC_F_SPI_MSTR_CFG_INACT_DELAY                      ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS))
+#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS               20
+#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK                   ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS))
+#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS               24
+#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK                   ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS))
+
+#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS            0
+#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY                ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS))
+#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS            8
+#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY                ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS))
+
+#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS                  0
+#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN                      ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS))
+#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS                   1
+#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN                       ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS))
+#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS                   2
+#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN                       ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS))
+#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS                3
+#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE                    ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS                 4
+#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT                     ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS                     5
+#define MXC_F_SPI_GEN_CTRL_BB_SR_IN                         ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS                6
+#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT                    ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS                   8
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN                       ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS                  12
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT                      ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS                16
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN                    ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS))
+
+#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS              0
+#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL                  ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS))
+#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS                8
+#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED                    ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS))
+#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS              16
+#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL                  ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS))
+#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS                24
+#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED                    ((uint32_t)(0x0000003FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS))
+
+#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS              0
+#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE                  ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS))
+#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS                  1
+#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN                      ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS))
+#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS              4
+#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT                  ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS))
+#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS            8
+#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN                ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS))
+
+#define MXC_F_SPI_INTFL_TX_STALLED_POS                      0
+#define MXC_F_SPI_INTFL_TX_STALLED                          ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_STALLED_POS))
+#define MXC_F_SPI_INTFL_RX_STALLED_POS                      1
+#define MXC_F_SPI_INTFL_RX_STALLED                          ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_STALLED_POS))
+#define MXC_F_SPI_INTFL_TX_READY_POS                        2
+#define MXC_F_SPI_INTFL_TX_READY                            ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_READY_POS))
+#define MXC_F_SPI_INTFL_RX_DONE_POS                         3
+#define MXC_F_SPI_INTFL_RX_DONE                             ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_DONE_POS))
+#define MXC_F_SPI_INTFL_TX_FIFO_AE_POS                      4
+#define MXC_F_SPI_INTFL_TX_FIFO_AE                          ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_FIFO_AE_POS))
+#define MXC_F_SPI_INTFL_RX_FIFO_AF_POS                      5
+#define MXC_F_SPI_INTFL_RX_FIFO_AF                          ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_FIFO_AF_POS))
+
+#define MXC_F_SPI_INTEN_TX_STALLED_POS                      0
+#define MXC_F_SPI_INTEN_TX_STALLED                          ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_STALLED_POS))
+#define MXC_F_SPI_INTEN_RX_STALLED_POS                      1
+#define MXC_F_SPI_INTEN_RX_STALLED                          ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_STALLED_POS))
+#define MXC_F_SPI_INTEN_TX_READY_POS                        2
+#define MXC_F_SPI_INTEN_TX_READY                            ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_READY_POS))
+#define MXC_F_SPI_INTEN_RX_DONE_POS                         3
+#define MXC_F_SPI_INTEN_RX_DONE                             ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_DONE_POS))
+#define MXC_F_SPI_INTEN_TX_FIFO_AE_POS                      4
+#define MXC_F_SPI_INTEN_TX_FIFO_AE                          ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_FIFO_AE_POS))
+#define MXC_F_SPI_INTEN_RX_FIFO_AF_POS                      5
+#define MXC_F_SPI_INTEN_RX_FIFO_AF                          ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_FIFO_AF_POS))
+
+#define MXC_F_SPI_FIFO_DIR_POS                              0
+#define MXC_F_SPI_FIFO_DIR                                  ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_DIR_POS))
+#define MXC_F_SPI_FIFO_UNIT_POS                             2
+#define MXC_F_SPI_FIFO_UNIT                                 ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_UNIT_POS))
+#define MXC_F_SPI_FIFO_SIZE_POS                             4
+#define MXC_F_SPI_FIFO_SIZE                                 ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_SIZE_POS))
+#define MXC_F_SPI_FIFO_WIDTH_POS                            9
+#define MXC_F_SPI_FIFO_WIDTH                                ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_WIDTH_POS))
+#define MXC_F_SPI_FIFO_ALT_POS                              11
+#define MXC_F_SPI_FIFO_ALT                                  ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_ALT_POS))
+#define MXC_F_SPI_FIFO_FLOW_POS                             12
+#define MXC_F_SPI_FIFO_FLOW                                 ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_FLOW_POS))
+#define MXC_F_SPI_FIFO_DASS_POS                             13
+#define MXC_F_SPI_FIFO_DASS                                 ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_DASS_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_SPI_REGS_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c

@@ -0,0 +1,144 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "max32600.h"
+#include "clkman_regs.h"
+#include "pwrman_regs.h"
+#include "ioman_regs.h"
+#include "trim_regs.h"
+#include "flc_regs.h"
+#include "pwrseq_regs.h"
+#include "dac_regs.h"
+#include "icc_regs.h"
+
+/* Application developer should override where necessary with different external HFX source */
+#ifndef __SYSTEM_HFX
+#define __SYSTEM_HFX 8000000
+#endif
+
+uint32_t SystemCoreClock = 24000000;
+
+void SystemCoreClockUpdate(void)
+{
+    switch ((MXC_CLKMAN->clk_ctrl & MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) >> MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS) {
+        case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8:
+            SystemCoreClock = 3000000;
+            break;
+        case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO:
+        case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2:
+            SystemCoreClock = 24000000;
+            break;
+        case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX:
+            SystemCoreClock = __SYSTEM_HFX;
+            break;
+    }
+
+    uint32_t shift = MXC_CLKMAN->clk_ctrl_0_system;
+    if (shift) {
+        SystemCoreClock = SystemCoreClock >> (shift - 1);
+    }
+}
+
+/* power seq registers */
+static void set_pwr_regs(void)
+{
+    uint32_t dac2trim =  MXC_DAC2->reg & 0xff00ffff;
+    uint32_t dac3trim =  MXC_DAC3->reg & 0xff00ffff;
+    dac2trim = dac2trim + MXC_TRIM->trim_reg_36;
+    dac3trim = dac3trim + MXC_TRIM->trim_reg_37;
+    MXC_PWRSEQ->reg5 = MXC_TRIM->trim_reg_13;
+    MXC_PWRSEQ->reg6 = MXC_TRIM->trim_reg_14;
+    MXC_DAC0->trm = MXC_TRIM->trim_reg_34;
+    MXC_DAC1->trm = MXC_TRIM->trim_reg_35;
+    MXC_DAC2->reg = dac2trim;
+    MXC_DAC3->reg = dac3trim;
+}
+
+void ICC_Enable(void)
+{
+    /* clock gater must be 'on' not 'dynamic' for cache control */
+    uint32_t temp = MXC_CLKMAN->clk_gate_ctrl0;
+    temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER;
+    temp |= (MXC_E_CLKMAN_CLK_GATE_ON << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS);
+    MXC_CLKMAN->clk_gate_ctrl0 = temp;
+
+
+    /* invalidate, wait, enable */
+    MXC_ICC->invdt_all = 0xFFFF;
+    while(!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY));
+    MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE;
+
+    /* must invalidate a second time for proper use */
+    MXC_ICC->invdt_all = 1;
+
+    /* clock gater 'dynamic' safe again */
+    temp = MXC_CLKMAN->clk_gate_ctrl0;
+    temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER;
+    temp |= (MXC_E_CLKMAN_CLK_GATE_DYNAMIC << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS);
+    MXC_CLKMAN->clk_gate_ctrl0 = temp;
+}
+
+// This function to be implemented by the hal
+extern void low_level_init(void);
+
+void SystemInit(void)
+{
+    set_pwr_regs();
+
+    // enable instruction cache
+    ICC_Enable();
+
+    low_level_init();
+
+    // Clear IO Active
+    MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
+                                MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE);
+
+    // Set WUD Clear
+    MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
+                                MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE |
+                                MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR);
+
+    // Set IO Active
+    MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
+                                MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE |
+                                MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE |
+                                MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED);
+
+    MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN;
+
+    // set systick to the RTC input 32.768kHz clock, not system clock; this is needed to keep JTAG alive during sleep
+    MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;
+
+    SystemCoreClockUpdate();
+}

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.h

@@ -0,0 +1,53 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef SYSTEM_MAX32600_H_
+#define SYSTEM_MAX32600_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+extern void SystemInit (void);
+
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_MAX32600_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tmr_regs.h

@@ -0,0 +1,146 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_TMR_REGS_H
+#define _MXC_TMR_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  tmr_regs.h
+ * @addtogroup tmr TMR
+ * @{
+ */
+
+/**
+ * @brief Defines timer modes for 16 and 32-bit timers
+ */
+typedef enum {
+    /** 32-bit or 16-bit timer one-shot mode */
+    MXC_E_TMR_MODE_ONE_SHOT = 0,
+    /** 32-bit or 16-bit timer one-shot mode */
+    MXC_E_TMR_MODE_CONTINUOUS,
+    /** 32-bit timer counter mode */
+    MXC_E_TMR_MODE_COUNTER,
+    /** 32-bit timer pulse width modulation mode */
+    MXC_E_TMR_MODE_PWM,
+    /** 32-bit timer capture mode */
+    MXC_E_TMR_MODE_CAPTURE,
+    /** 32-bit timer compare mode */
+    MXC_E_TMR_MODE_COMPARE,
+    /** 32-bit timer gated mode */
+    MXC_E_TMR_MODE_GATED,
+    /** 32-bit timer measure mode */
+    MXC_E_TMR_MODE_MEASURE
+} mxc_tmr_mode_t;
+
+/*                                          Offset   Register Description
+                                            ======   ============================================== */
+typedef struct {
+    __IO uint32_t ctrl;                 /*  0x0000   Timer Control Register                         */
+    __IO uint32_t count32;              /*  0x0004   [32 bit] Current Count Value                   */
+    __IO uint32_t term_cnt32;           /*  0x0008   [32 bit] Terminal Count Setting                */
+    __IO uint32_t pwm_cap32;            /*  0x000C   [32 bit] PWM Compare Setting or Capture/Measure Value */
+    __IO uint32_t count16_0;            /*  0x0010   [16 bit] Current Count Value, 16-bit Timer0    */
+    __IO uint32_t term_cnt16_0;         /*  0x0014   [16 bit] Terminal Count Setting, 16-bit Timer0 */
+    __IO uint32_t count16_1;            /*  0x0018   [16 bit] Current Count Value, 16-bit Timer1    */
+    __IO uint32_t term_cnt16_1;         /*  0x001C   [16 bit] Terminal Count Setting, 16-bit Timer1 */
+    __IO uint32_t intfl;                /*  0x0020   Timer Module Interrupt Flags                   */
+    __IO uint32_t inten;                /*  0x0024   Timer Module Interrupt Enable/Disable Settings */
+} mxc_tmr_regs_t;
+
+/*
+   Register offsets for module TMR.
+*/
+#define MXC_R_TMR_OFFS_CTRL                       ((uint32_t)0x00000000UL)
+#define MXC_R_TMR_OFFS_COUNT32                    ((uint32_t)0x00000004UL)
+#define MXC_R_TMR_OFFS_TERM_CNT32                 ((uint32_t)0x00000008UL)
+#define MXC_R_TMR_OFFS_PWM_CAP32                  ((uint32_t)0x0000000CUL)
+#define MXC_R_TMR_OFFS_COUNT16_0                  ((uint32_t)0x00000010UL)
+#define MXC_R_TMR_OFFS_TERM_CNT16_0               ((uint32_t)0x00000014UL)
+#define MXC_R_TMR_OFFS_COUNT16_1                  ((uint32_t)0x00000018UL)
+#define MXC_R_TMR_OFFS_TERM_CNT16_1               ((uint32_t)0x0000001CUL)
+#define MXC_R_TMR_OFFS_INTFL                      ((uint32_t)0x00000020UL)
+#define MXC_R_TMR_OFFS_INTEN                      ((uint32_t)0x00000024UL)
+
+/*
+   Field positions and masks for module TMR.
+*/
+#define MXC_F_TMR_CTRL_MODE_POS                             0
+#define MXC_F_TMR_CTRL_MODE                                 ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS))
+#define MXC_F_TMR_CTRL_TMR2X16_POS                          3
+#define MXC_F_TMR_CTRL_TMR2X16                              ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS))
+#define MXC_F_TMR_CTRL_PRESCALE_POS                         4
+#define MXC_F_TMR_CTRL_PRESCALE                             ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS))
+#define MXC_F_TMR_CTRL_POLARITY_POS                         8
+#define MXC_F_TMR_CTRL_POLARITY                             ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS))
+#define MXC_F_TMR_CTRL_ENABLE0_POS                          12
+#define MXC_F_TMR_CTRL_ENABLE0                              ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS))
+#define MXC_F_TMR_CTRL_ENABLE1_POS                          13
+#define MXC_F_TMR_CTRL_ENABLE1                              ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS))
+
+#define MXC_F_TMR_COUNT16_0_VALUE_POS                       0
+#define MXC_F_TMR_COUNT16_0_VALUE                           ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS))
+
+#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS               0
+#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT                   ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS))
+
+#define MXC_F_TMR_COUNT16_1_VALUE_POS                       0
+#define MXC_F_TMR_COUNT16_1_VALUE                           ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS))
+
+#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS               0
+#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT                   ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS))
+
+#define MXC_F_TMR_INTFL_TIMER0_POS                          0
+#define MXC_F_TMR_INTFL_TIMER0                              ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS))
+#define MXC_F_TMR_INTFL_TIMER1_POS                          1
+#define MXC_F_TMR_INTFL_TIMER1                              ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS))
+
+#define MXC_F_TMR_INTEN_TIMER0_POS                          0
+#define MXC_F_TMR_INTEN_TIMER0                              ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS))
+#define MXC_F_TMR_INTEN_TIMER1_POS                          1
+#define MXC_F_TMR_INTEN_TIMER1                              ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_TMR_REGS_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tpu_regs.h

@@ -0,0 +1,108 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_TPU_REGS_H_
+#define _MXC_TPU_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  tpu_regs.h
+ * @addtogroup tpu TPU
+ * @{
+ */
+
+/*                                               Offset   Register Description
+                                                 ======   ================================================== */
+typedef struct {
+    __I uint32_t rsv0000;                    /*  0x0000   Reserved                                          */
+    __I uint32_t rsv0004;                    /*  0x0004   Reserved - PUF Control (Deprecated)               */
+    __I uint32_t rsv0008;                    /*  0x0008   Reserved - PUF Output (Deprecated)                */
+    __I uint32_t rsv000C[125];               /*  0x000C                                                     */
+    __IO uint32_t prng_user_entropy;         /*  0x0200   PRNG User Entropy Value                           */
+    __IO uint32_t prng_rnd_num;              /*  0x0204   PRNG Random Number Output                         */
+} mxc_tpu_regs_t;
+
+/*                                               Offset   Register Description
+                                                 ======   ================================================= */
+typedef struct {
+    __IO uint32_t status;                    /*  0x0000   Dynamic Tamper Sensor Status                      */
+    __IO uint32_t ctrl0;                     /*  0x0004   Dynamic Tamper Sensor Control 0                   */
+    __IO uint32_t ctrl1;                     /*  0x0008   Dynamic Tamper Sensor Control 1                   */
+    __IO uint32_t sks0;                      /*  0x0010   TPU Secure Key Storage Register 0                 */
+    __IO uint32_t sks1;                      /*  0x0014   TPU Secure Key Storage Register 0                 */
+    __IO uint32_t sks2;                      /*  0x0018   TPU Secure Key Storage Register 0                 */
+    __IO uint32_t sks3;                      /*  0x001C   TPU Secure Key Storage Register 0                 */
+} mxc_tpu_tsr_regs_t;
+
+/*
+   Register offsets for module TPU.
+*/
+#define MXC_R_TPU_OFFS_PRNG_USER_ENTROPY    ((uint32_t)0x00000200UL)
+#define MXC_R_TPU_OFFS_PRNG_RND_NUM         ((uint32_t)0x00000204UL)
+#define MXC_R_TPU_TSR_OFFS_STATUS           ((uint32_t)0x00000000UL)
+#define MXC_R_TPU_TSR_OFFS_CTRL0            ((uint32_t)0x00000004UL)
+#define MXC_R_TPU_TSR_OFFS_CTRL1            ((uint32_t)0x00000008UL)
+#define MXC_R_TPU_TSR_OFFS_SKS0             ((uint32_t)0x00000010UL)
+#define MXC_R_TPU_TSR_OFFS_SKS1             ((uint32_t)0x00000014UL)
+#define MXC_R_TPU_TSR_OFFS_SKS2             ((uint32_t)0x00000018UL)
+#define MXC_R_TPU_TSR_OFFS_SKS3             ((uint32_t)0x0000001CUL)
+
+
+/*
+   Field positions and masks for module TPU.
+*/
+#define MXC_F_TPU_CTRL0_ERR_THR_POS         0
+#define MXC_F_TPU_CTRL0_ERR_THR             ((uint32_t)(0x0000001FUL << MXC_F_TPU_CTRL0_ERR_THR_POS))
+#define MXC_F_TPU_CTRL0_OUT_FREQ_POS        5
+#define MXC_F_TPU_CTRL0_OUT_FREQ            ((uint32_t)(0x00000007UL << MXC_F_TPU_CTRL0_OUT_FREQ_POS))
+#define MXC_F_TPU_CTRL0_CLOCK_DIV_POS       8
+#define MXC_F_TPU_CTRL0_CLOCK_DIV           ((uint32_t)(0x00000007UL << MXC_F_TPU_CTRL0_CLOCK_DIV_POS))
+#define MXC_F_TPU_CTRL0_RTC_TX_BUSY_POS     14
+#define MXC_F_TPU_CTRL0_RTC_TX_BUSY         ((uint32_t)(0x00000001UL << MXC_F_TPU_CTRL0_RTC_TX_BUSY_POS))
+#define MXC_F_TPU_CTRL0_LOCK_POS            15
+#define MXC_F_TPU_CTRL0_LOCK                ((uint32_t)(0x00000001UL << MXC_F_TPU_CTRL0_LOCK_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_TPU_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/trim_regs.h

@@ -0,0 +1,92 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_TRIM_REGS_H
+#define _MXC_TRIM_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+typedef struct {
+    __IO uint32_t trim_reg_00;
+    __IO uint32_t trim_reg_01;
+    __IO uint32_t trim_reg_02;
+    __IO uint32_t trim_reg_03;
+    __IO uint32_t trim_reg_04;
+    __IO uint32_t trim_reg_05;
+    __IO uint32_t trim_reg_06;
+    __IO uint32_t trim_reg_07;
+    __IO uint32_t trim_reg_08;
+    __IO uint32_t trim_reg_09;
+    __IO uint32_t trim_reg_10;
+    __IO uint32_t trim_reg_11;
+    __IO uint32_t trim_reg_12;
+    __IO uint32_t trim_reg_13;
+    __IO uint32_t trim_reg_14;
+    __IO uint32_t trim_reg_15;
+    __IO uint32_t trim_reg_16;
+    __IO uint32_t trim_reg_17;
+    __IO uint32_t trim_reg_18;
+    __IO uint32_t trim_reg_19;
+    __IO uint32_t trim_reg_20;
+    __IO uint32_t trim_reg_21;
+    __IO uint32_t trim_reg_22;
+    __IO uint32_t trim_reg_23;
+    __IO uint32_t trim_reg_24;
+    __IO uint32_t trim_reg_25;
+    __IO uint32_t trim_reg_26;
+    __IO uint32_t trim_reg_27;
+    __IO uint32_t trim_reg_28;
+    __IO uint32_t trim_reg_29;
+    __IO uint32_t trim_reg_30;
+    __IO uint32_t trim_reg_31;
+    __IO uint32_t trim_reg_32;
+    __IO uint32_t trim_reg_33;
+    __IO uint32_t trim_reg_34;
+    __IO uint32_t trim_reg_35;
+    __IO uint32_t trim_reg_36;
+    __IO uint32_t trim_reg_37;
+    __IO uint32_t trim_reg_38;
+    __IO uint32_t trim_reg_39;
+    __IO uint32_t trim_reg_40;
+    __IO uint32_t trim_reg_41;
+} mxc_ftr_regs_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_TRIM_REGS_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/uart_regs.h

@@ -0,0 +1,175 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_UART_REGS_H_
+#define _MXC_UART_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  uart_regs.h
+ * @addtogroup uart UART
+ * @{
+ */
+
+/*                                      Offset   Register Description
+                                        ======   ============================================== */
+typedef struct {
+    __IO uint32_t ctrl;             /*  0x0000   UART Control Register                          */
+    __IO uint32_t status;           /*  0x0004   UART Status Register                           */
+    __IO uint32_t inten;            /*  0x0008   Interrupt Enable/Disable Controls              */
+    __IO uint32_t intfl;            /*  0x000C   Interrupt Flags                                */
+    __IO uint32_t baud_int;         /*  0x0010   Baud Rate Setting (Integer Portion)            */
+    __IO uint32_t baud_div_128;     /*  0x0014   Baud Rate Setting                              */
+    __IO uint32_t tx_fifo_out;      /*  0x0018   TX FIFO Output End (read-only)                 */
+    __IO uint32_t hw_flow_ctrl;     /*  0x001C   Hardware Flow Control Register                 */
+    __IO uint32_t tx_rx_fifo;       /*  0x0020   Write to load TX FIFO, Read to unload RX FIFO  */
+} mxc_uart_regs_t;
+
+
+/*
+    Register offsets for module UART.
+*/
+#define MXC_R_UART_OFFS_CTRL                      ((uint32_t)0x00000000UL)
+#define MXC_R_UART_OFFS_STATUS                    ((uint32_t)0x00000004UL)
+#define MXC_R_UART_OFFS_INTEN                     ((uint32_t)0x00000008UL)
+#define MXC_R_UART_OFFS_INTFL                     ((uint32_t)0x0000000CUL)
+#define MXC_R_UART_OFFS_BAUD_INT                  ((uint32_t)0x00000010UL)
+#define MXC_R_UART_OFFS_BAUD_DIV_128              ((uint32_t)0x00000014UL)
+#define MXC_R_UART_OFFS_TX_FIFO_OUT               ((uint32_t)0x00000018UL)
+#define MXC_R_UART_OFFS_HW_FLOW_CTRL              ((uint32_t)0x0000001CUL)
+#define MXC_R_UART_OFFS_TX_RX_FIFO                ((uint32_t)0x00000020UL)
+
+/*
+   Field positions and masks for module UART.
+*/
+#define MXC_F_UART_CTRL_RX_THRESHOLD_POS                    0
+#define MXC_F_UART_CTRL_RX_THRESHOLD                        ((uint32_t)(0x00000007UL << MXC_F_UART_CTRL_RX_THRESHOLD_POS))
+#define MXC_F_UART_CTRL_PARITY_ENABLE_POS                   4
+#define MXC_F_UART_CTRL_PARITY_ENABLE                       ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_ENABLE_POS))
+#define MXC_F_UART_CTRL_PARITY_MODE_POS                     5
+#define MXC_F_UART_CTRL_PARITY_MODE                         ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_MODE_POS))
+#define MXC_F_UART_CTRL_PARITY_BIAS_POS                     6
+#define MXC_F_UART_CTRL_PARITY_BIAS                         ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_BIAS_POS))
+#define MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS                   8
+#define MXC_F_UART_CTRL_TX_FIFO_FLUSH                       ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS))
+#define MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS                   9
+#define MXC_F_UART_CTRL_RX_FIFO_FLUSH                       ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS))
+#define MXC_F_UART_CTRL_CHAR_LENGTH_POS                     10
+#define MXC_F_UART_CTRL_CHAR_LENGTH                         ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_CHAR_LENGTH_POS))
+#define MXC_F_UART_CTRL_STOP_BIT_MODE_POS                   12
+#define MXC_F_UART_CTRL_STOP_BIT_MODE                       ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_STOP_BIT_MODE_POS))
+#define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS                 13
+#define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN                     ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS))
+#define MXC_F_UART_CTRL_BAUD_CLK_EN_POS                     14
+#define MXC_F_UART_CTRL_BAUD_CLK_EN                         ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_BAUD_CLK_EN_POS))
+
+#define MXC_F_UART_STATUS_TX_BUSY_POS                       0
+#define MXC_F_UART_STATUS_TX_BUSY                           ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_BUSY_POS))
+#define MXC_F_UART_STATUS_RX_BUSY_POS                       1
+#define MXC_F_UART_STATUS_RX_BUSY                           ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_BUSY_POS))
+#define MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS                 4
+#define MXC_F_UART_STATUS_RX_FIFO_EMPTY                     ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS))
+#define MXC_F_UART_STATUS_RX_FIFO_FULL_POS                  5
+#define MXC_F_UART_STATUS_RX_FIFO_FULL                      ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_FULL_POS))
+#define MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS                 6
+#define MXC_F_UART_STATUS_TX_FIFO_EMPTY                     ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS))
+#define MXC_F_UART_STATUS_TX_FIFO_FULL_POS                  7
+#define MXC_F_UART_STATUS_TX_FIFO_FULL                      ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_FULL_POS))
+#define MXC_F_UART_STATUS_RX_FIFO_CHARS_POS                 8
+#define MXC_F_UART_STATUS_RX_FIFO_CHARS                     ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_RX_FIFO_CHARS_POS))
+#define MXC_F_UART_STATUS_TX_FIFO_CHARS_POS                 12
+#define MXC_F_UART_STATUS_TX_FIFO_CHARS                     ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_TX_FIFO_CHARS_POS))
+
+#define MXC_F_UART_INTEN_RX_FRAME_ERROR_POS                 0
+#define MXC_F_UART_INTEN_RX_FRAME_ERROR                     ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAME_ERROR_POS))
+#define MXC_F_UART_INTEN_RX_PARITY_ERROR_POS                1
+#define MXC_F_UART_INTEN_RX_PARITY_ERROR                    ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERROR_POS))
+#define MXC_F_UART_INTEN_CTS_CHANGE_POS                     2
+#define MXC_F_UART_INTEN_CTS_CHANGE                         ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_CTS_CHANGE_POS))
+#define MXC_F_UART_INTEN_RX_OVERRUN_POS                     3
+#define MXC_F_UART_INTEN_RX_OVERRUN                         ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVERRUN_POS))
+#define MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS              4
+#define MXC_F_UART_INTEN_RX_OVER_THRESHOLD                  ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS))
+#define MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS                5
+#define MXC_F_UART_INTEN_TX_ALMOST_EMPTY                    ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS))
+#define MXC_F_UART_INTEN_TX_HALF_EMPTY_POS                  6
+#define MXC_F_UART_INTEN_TX_HALF_EMPTY                      ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_HALF_EMPTY_POS))
+
+#define MXC_F_UART_INTFL_RX_FRAME_ERROR_POS                 0
+#define MXC_F_UART_INTFL_RX_FRAME_ERROR                     ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAME_ERROR_POS))
+#define MXC_F_UART_INTFL_RX_PARITY_ERROR_POS                1
+#define MXC_F_UART_INTFL_RX_PARITY_ERROR                    ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERROR_POS))
+#define MXC_F_UART_INTFL_CTS_CHANGE_POS                     2
+#define MXC_F_UART_INTFL_CTS_CHANGE                         ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_CTS_CHANGE_POS))
+#define MXC_F_UART_INTFL_RX_OVERRUN_POS                     3
+#define MXC_F_UART_INTFL_RX_OVERRUN                         ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVERRUN_POS))
+#define MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS              4
+#define MXC_F_UART_INTFL_RX_OVER_THRESHOLD                  ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS))
+#define MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS                5
+#define MXC_F_UART_INTFL_TX_ALMOST_EMPTY                    ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS))
+#define MXC_F_UART_INTFL_TX_HALF_EMPTY_POS                  6
+#define MXC_F_UART_INTFL_TX_HALF_EMPTY                      ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_HALF_EMPTY_POS))
+
+#define MXC_F_UART_BAUD_INT_FBAUD_POS                       0
+#define MXC_F_UART_BAUD_INT_FBAUD                           ((uint32_t)(0x00000FFFUL << MXC_F_UART_BAUD_INT_FBAUD_POS))
+
+#define MXC_F_UART_BAUD_DIV_128_DIV_POS                     0
+#define MXC_F_UART_BAUD_DIV_128_DIV                         ((uint32_t)(0x0000007FUL << MXC_F_UART_BAUD_DIV_128_DIV_POS))
+
+#define MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS                  0
+#define MXC_F_UART_TX_FIFO_OUT_TX_FIFO                      ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS))
+
+#define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS               0
+#define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT                   ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS))
+#define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS              1
+#define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT                  ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS))
+
+#define MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS                 0
+#define MXC_F_UART_TX_RX_FIFO_FIFO_DATA                     ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS))
+#define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS              8
+#define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR                  ((uint32_t)(0x00000001UL << MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_UART_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/usb_regs.h

@@ -0,0 +1,480 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_USB_REGS_H_
+#define _MXC_USB_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  usb_regs.h
+ * @addtogroup usb USB
+ * @{
+ */
+
+/*                                                Offset   Register Description
+                                                  ======   ================================================ */
+typedef struct {
+    __IO uint32_t cn;                         /*  0x0000   USB Control Register                             */
+    __I uint32_t rsv0004[127];                /*  0x0004                                                    */
+    __IO uint32_t dev_addr;                   /*  0x0200   USB Device Address Register                      */
+    __IO uint32_t dev_cn;                     /*  0x0204   USB Device Control Register                      */
+    __IO uint32_t dev_intfl;                  /*  0x0208   USB Device Interrupt                             */
+    __IO uint32_t dev_inten;                  /*  0x020C   USB Device Interrupt Enable                      */
+    __I uint32_t rsv0210[4];                  /*  0x0210                                                    */
+    __IO uint32_t ep_base;                    /*  0x0220   USB Endpoint Descriptor Table Base Address       */
+    __IO uint32_t cur_buf;                    /*  0x0224   USB Current Endpoint Buffer Register             */
+    __IO uint32_t in_owner;                   /*  0x0228   USB IN Endpoint Buffer Owner Register            */
+    __IO uint32_t out_owner;                  /*  0x022C   USB OUT Endpoint Buffer Owner Register           */
+    __IO uint32_t in_int;                     /*  0x0230   USB IN Endpoint Buffer Available Interrupt       */
+    __IO uint32_t out_int;                    /*  0x0234   USB OUT Endpoint Data Available Interrupt        */
+    __IO uint32_t nak_int;                    /*  0x0238   USB IN Endpoint NAK Interrupt                    */
+    __IO uint32_t dma_err_int;                /*  0x023C   USB DMA Error Interrupt                          */
+    __IO uint32_t buf_ovr_int;                /*  0x0240   USB Buffer Overflow Interrupt                    */
+    __I uint32_t rsv0244[7];                  /*  0x0244                                                    */
+    __IO uint32_t setup0;                     /*  0x0260   USB SETUP Packet Bytes 0 to 3                    */
+    __IO uint32_t setup1;                     /*  0x0264   USB SETUP Packet Bytes 4 to 7                    */
+    __I uint32_t rsv0268[6];                  /*  0x0268                                                    */
+    __IO uint32_t ep[MXC_USB_NUM_EP];         /*  0x0280   USB Endpoint Control Registers                   */
+} mxc_usb_regs_t;
+
+
+/*
+   Register offsets for module USB.
+*/
+#define MXC_R_USB_OFFS_CN                       ((uint32_t)0x00000000UL)
+#define MXC_R_USB_OFFS_DEV_ADDR                 ((uint32_t)0x00000200UL)
+#define MXC_R_USB_OFFS_DEV_CN                   ((uint32_t)0x00000204UL)
+#define MXC_R_USB_OFFS_DEV_INTFL                ((uint32_t)0x00000208UL)
+#define MXC_R_USB_OFFS_DEV_INTEN                ((uint32_t)0x0000020CUL)
+#define MXC_R_USB_OFFS_EP_BASE                  ((uint32_t)0x00000220UL)
+#define MXC_R_USB_OFFS_CUR_BUF                  ((uint32_t)0x00000224UL)
+#define MXC_R_USB_OFFS_IN_OWNER                 ((uint32_t)0x00000228UL)
+#define MXC_R_USB_OFFS_OUT_OWNER                ((uint32_t)0x0000022CUL)
+#define MXC_R_USB_OFFS_IN_INT                   ((uint32_t)0x00000230UL)
+#define MXC_R_USB_OFFS_OUT_INT                  ((uint32_t)0x00000234UL)
+#define MXC_R_USB_OFFS_NAK_INT                  ((uint32_t)0x00000238UL)
+#define MXC_R_USB_OFFS_DMA_ERR_INT              ((uint32_t)0x0000023CUL)
+#define MXC_R_USB_OFFS_BUF_OVR_INT              ((uint32_t)0x00000240UL)
+#define MXC_R_USB_OFFS_SETUP0                   ((uint32_t)0x00000260UL)
+#define MXC_R_USB_OFFS_SETUP1                   ((uint32_t)0x00000264UL)
+#define MXC_R_USB_OFFS_EP0                      ((uint32_t)0x00000280UL)
+#define MXC_R_USB_OFFS_EP1                      ((uint32_t)0x00000284UL)
+#define MXC_R_USB_OFFS_EP2                      ((uint32_t)0x00000288UL)
+#define MXC_R_USB_OFFS_EP3                      ((uint32_t)0x0000028CUL)
+#define MXC_R_USB_OFFS_EP4                      ((uint32_t)0x00000290UL)
+#define MXC_R_USB_OFFS_EP5                      ((uint32_t)0x00000294UL)
+#define MXC_R_USB_OFFS_EP6                      ((uint32_t)0x00000298UL)
+#define MXC_R_USB_OFFS_EP7                      ((uint32_t)0x0000029CUL)
+
+
+/*
+   Field positions and masks for module USB.
+*/
+#define MXC_F_USB_CN_USB_EN_POS                 0
+#define MXC_F_USB_CN_USB_EN                     ((uint32_t)(0x00000001UL << MXC_F_USB_CN_USB_EN_POS))
+
+#define MXC_F_USB_DEV_ADDR_DEV_ADDR_POS         0
+#define MXC_F_USB_DEV_ADDR_DEV_ADDR             ((uint32_t)(0x0000007FUL << MXC_F_USB_DEV_ADDR_DEV_ADDR_POS))
+
+#define MXC_F_USB_DEV_CN_SIGRWU_POS             2
+#define MXC_F_USB_DEV_CN_SIGRWU                 ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_SIGRWU_POS))
+#define MXC_F_USB_DEV_CN_CONNECT_POS            3
+#define MXC_F_USB_DEV_CN_CONNECT                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_CONNECT_POS))
+#define MXC_F_USB_DEV_CN_ULPM_POS               4
+#define MXC_F_USB_DEV_CN_ULPM                   ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_ULPM_POS))
+#define MXC_F_USB_DEV_CN_URST_POS               5
+#define MXC_F_USB_DEV_CN_URST                   ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_URST_POS))
+#define MXC_F_USB_DEV_CN_VBGATE_POS             6
+#define MXC_F_USB_DEV_CN_VBGATE                 ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_VBGATE_POS))
+#define MXC_F_USB_DEV_CN_FIFO_MODE_POS          9
+#define MXC_F_USB_DEV_CN_FIFO_MODE              ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_FIFO_MODE_POS))
+
+#define MXC_F_USB_DEV_INTFL_DPACT_POS           0
+#define MXC_F_USB_DEV_INTFL_DPACT               ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DPACT_POS))
+#define MXC_F_USB_DEV_INTFL_RWU_DN_POS          1
+#define MXC_F_USB_DEV_INTFL_RWU_DN              ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_RWU_DN_POS))
+#define MXC_F_USB_DEV_INTFL_BACT_POS            2
+#define MXC_F_USB_DEV_INTFL_BACT                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BACT_POS))
+#define MXC_F_USB_DEV_INTFL_BRST_POS            3
+#define MXC_F_USB_DEV_INTFL_BRST                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_POS))
+#define MXC_F_USB_DEV_INTFL_SUSP_POS            4
+#define MXC_F_USB_DEV_INTFL_SUSP                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SUSP_POS))
+#define MXC_F_USB_DEV_INTFL_NO_VBUS_POS         5
+#define MXC_F_USB_DEV_INTFL_NO_VBUS             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_NO_VBUS_POS))
+#define MXC_F_USB_DEV_INTFL_VBUS_POS            6
+#define MXC_F_USB_DEV_INTFL_VBUS                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_POS))
+#define MXC_F_USB_DEV_INTFL_BRST_DN_POS         7
+#define MXC_F_USB_DEV_INTFL_BRST_DN             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_DN_POS))
+#define MXC_F_USB_DEV_INTFL_SETUP_POS           8
+#define MXC_F_USB_DEV_INTFL_SETUP               ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SETUP_POS))
+#define MXC_F_USB_DEV_INTFL_EP_IN_POS           9
+#define MXC_F_USB_DEV_INTFL_EP_IN               ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_IN_POS))
+#define MXC_F_USB_DEV_INTFL_EP_OUT_POS          10
+#define MXC_F_USB_DEV_INTFL_EP_OUT              ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_OUT_POS))
+#define MXC_F_USB_DEV_INTFL_EP_NAK_POS          11
+#define MXC_F_USB_DEV_INTFL_EP_NAK              ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_NAK_POS))
+#define MXC_F_USB_DEV_INTFL_DMA_ERR_POS         12
+#define MXC_F_USB_DEV_INTFL_DMA_ERR             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DMA_ERR_POS))
+#define MXC_F_USB_DEV_INTFL_BUF_OVR_POS         13
+#define MXC_F_USB_DEV_INTFL_BUF_OVR             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BUF_OVR_POS))
+#define MXC_F_USB_DEV_INTFL_VBUS_ST_POS         16
+#define MXC_F_USB_DEV_INTFL_VBUS_ST             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_ST_POS))
+
+#define MXC_F_USB_DEV_INTEN_DPACT_POS           0
+#define MXC_F_USB_DEV_INTEN_DPACT               ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DPACT_POS))
+#define MXC_F_USB_DEV_INTEN_RWU_DN_POS          1
+#define MXC_F_USB_DEV_INTEN_RWU_DN              ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_RWU_DN_POS))
+#define MXC_F_USB_DEV_INTEN_BACT_POS            2
+#define MXC_F_USB_DEV_INTEN_BACT                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BACT_POS))
+#define MXC_F_USB_DEV_INTEN_BRST_POS            3
+#define MXC_F_USB_DEV_INTEN_BRST                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_POS))
+#define MXC_F_USB_DEV_INTEN_SUSP_POS            4
+#define MXC_F_USB_DEV_INTEN_SUSP                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SUSP_POS))
+#define MXC_F_USB_DEV_INTEN_NO_VBUS_POS         5
+#define MXC_F_USB_DEV_INTEN_NO_VBUS             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_NO_VBUS_POS))
+#define MXC_F_USB_DEV_INTEN_VBUS_POS            6
+#define MXC_F_USB_DEV_INTEN_VBUS                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_VBUS_POS))
+#define MXC_F_USB_DEV_INTEN_BRST_DN_POS         7
+#define MXC_F_USB_DEV_INTEN_BRST_DN             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_DN_POS))
+#define MXC_F_USB_DEV_INTEN_SETUP_POS           8
+#define MXC_F_USB_DEV_INTEN_SETUP               ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SETUP_POS))
+#define MXC_F_USB_DEV_INTEN_EP_IN_POS           9
+#define MXC_F_USB_DEV_INTEN_EP_IN               ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_IN_POS))
+#define MXC_F_USB_DEV_INTEN_EP_OUT_POS          10
+#define MXC_F_USB_DEV_INTEN_EP_OUT              ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_OUT_POS))
+#define MXC_F_USB_DEV_INTEN_EP_NAK_POS          11
+#define MXC_F_USB_DEV_INTEN_EP_NAK              ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_NAK_POS))
+#define MXC_F_USB_DEV_INTEN_DMA_ERR_POS         12
+#define MXC_F_USB_DEV_INTEN_DMA_ERR             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DMA_ERR_POS))
+#define MXC_F_USB_DEV_INTEN_BUF_OVR_POS         13
+#define MXC_F_USB_DEV_INTEN_BUF_OVR             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BUF_OVR_POS))
+
+#define MXC_F_USB_EP_BASE_EP_BASE_POS           9
+#define MXC_F_USB_EP_BASE_EP_BASE               ((uint32_t)(0x007FFFFFUL << MXC_F_USB_EP_BASE_EP_BASE_POS))
+
+#define MXC_F_USB_CUR_BUF_OUT_BUF_POS           0
+#define MXC_F_USB_CUR_BUF_OUT_BUF               ((uint32_t)(0x000000FFUL << MXC_F_USB_CUR_BUF_OUT_BUF_POS))
+#define MXC_F_USB_CUR_BUF_IN_BUF_POS            16
+#define MXC_F_USB_CUR_BUF_IN_BUF                ((uint32_t)(0x000000FFUL << MXC_F_USB_CUR_BUF_IN_BUF_POS))
+
+#define MXC_F_USB_IN_OWNER_BUF0_OWNER_POS       0
+#define MXC_F_USB_IN_OWNER_BUF0_OWNER           ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_OWNER_BUF0_OWNER_POS))
+#define MXC_F_USB_IN_OWNER_BUF1_OWNER_POS       16
+#define MXC_F_USB_IN_OWNER_BUF1_OWNER           ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_OWNER_BUF1_OWNER_POS))
+
+#define MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS      0
+#define MXC_F_USB_OUT_OWNER_BUF0_OWNER          ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS))
+#define MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS      16
+#define MXC_F_USB_OUT_OWNER_BUF1_OWNER          ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS))
+
+#define MXC_F_USB_IN_INT_INBAV0_POS             0
+#define MXC_F_USB_IN_INT_INBAV0                 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV0_POS))
+#define MXC_F_USB_IN_INT_INBAV1_POS             1
+#define MXC_F_USB_IN_INT_INBAV1                 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV1_POS))
+#define MXC_F_USB_IN_INT_INBAV2_POS             2
+#define MXC_F_USB_IN_INT_INBAV2                 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV2_POS))
+#define MXC_F_USB_IN_INT_INBAV3_POS             3
+#define MXC_F_USB_IN_INT_INBAV3                 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV3_POS))
+#define MXC_F_USB_IN_INT_INBAV4_POS             4
+#define MXC_F_USB_IN_INT_INBAV4                 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV4_POS))
+#define MXC_F_USB_IN_INT_INBAV5_POS             5
+#define MXC_F_USB_IN_INT_INBAV5                 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV5_POS))
+#define MXC_F_USB_IN_INT_INBAV6_POS             6
+#define MXC_F_USB_IN_INT_INBAV6                 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV6_POS))
+#define MXC_F_USB_IN_INT_INBAV7_POS             7
+#define MXC_F_USB_IN_INT_INBAV7                 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV7_POS))
+
+#define MXC_F_USB_OUT_INT_OUTDAV0_POS           0
+#define MXC_F_USB_OUT_INT_OUTDAV0               ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV0_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV1_POS           1
+#define MXC_F_USB_OUT_INT_OUTDAV1               ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV1_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV2_POS           2
+#define MXC_F_USB_OUT_INT_OUTDAV2               ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV2_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV3_POS           3
+#define MXC_F_USB_OUT_INT_OUTDAV3               ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV3_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV4_POS           4
+#define MXC_F_USB_OUT_INT_OUTDAV4               ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV4_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV5_POS           5
+#define MXC_F_USB_OUT_INT_OUTDAV5               ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV5_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV6_POS           6
+#define MXC_F_USB_OUT_INT_OUTDAV6               ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV6_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV7_POS           7
+#define MXC_F_USB_OUT_INT_OUTDAV7               ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV7_POS))
+
+#define MXC_F_USB_NAK_INT_NAK0_POS              0
+#define MXC_F_USB_NAK_INT_NAK0                  ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK0_POS))
+#define MXC_F_USB_NAK_INT_NAK1_POS              1
+#define MXC_F_USB_NAK_INT_NAK1                  ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK1_POS))
+#define MXC_F_USB_NAK_INT_NAK2_POS              2
+#define MXC_F_USB_NAK_INT_NAK2                  ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK2_POS))
+#define MXC_F_USB_NAK_INT_NAK3_POS              3
+#define MXC_F_USB_NAK_INT_NAK3                  ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK3_POS))
+#define MXC_F_USB_NAK_INT_NAK4_POS              4
+#define MXC_F_USB_NAK_INT_NAK4                  ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK4_POS))
+#define MXC_F_USB_NAK_INT_NAK5_POS              5
+#define MXC_F_USB_NAK_INT_NAK5                  ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK5_POS))
+#define MXC_F_USB_NAK_INT_NAK6_POS              6
+#define MXC_F_USB_NAK_INT_NAK6                  ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK6_POS))
+#define MXC_F_USB_NAK_INT_NAK7_POS              7
+#define MXC_F_USB_NAK_INT_NAK7                  ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK7_POS))
+
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR0_POS      0
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR0          ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR0_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR1_POS      1
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR1          ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR1_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR2_POS      2
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR2          ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR2_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR3_POS      3
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR3          ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR3_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR4_POS      4
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR4          ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR4_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR5_POS      5
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR5          ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR5_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR6_POS      6
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR6          ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR6_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR7_POS      7
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR7          ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR7_POS))
+
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR0_POS      0
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR0          ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR0_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR1_POS      1
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR1          ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR1_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR2_POS      2
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR2          ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR2_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR3_POS      3
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR3          ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR3_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR4_POS      4
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR4          ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR4_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR5_POS      5
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR5          ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR5_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR6_POS      6
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR6          ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR6_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR7_POS      7
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR7          ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR7_POS))
+
+#define MXC_F_USB_SETUP0_BYTE0_POS              0
+#define MXC_F_USB_SETUP0_BYTE0                  ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE0_POS))
+#define MXC_F_USB_SETUP0_BYTE1_POS              8
+#define MXC_F_USB_SETUP0_BYTE1                  ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE1_POS))
+#define MXC_F_USB_SETUP0_BYTE2_POS              16
+#define MXC_F_USB_SETUP0_BYTE2                  ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE2_POS))
+#define MXC_F_USB_SETUP0_BYTE3_POS              24
+#define MXC_F_USB_SETUP0_BYTE3                  ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE3_POS))
+
+#define MXC_F_USB_SETUP1_BYTE4_POS              0
+#define MXC_F_USB_SETUP1_BYTE4                  ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE4_POS))
+#define MXC_F_USB_SETUP1_BYTE5_POS              8
+#define MXC_F_USB_SETUP1_BYTE5                  ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE5_POS))
+#define MXC_F_USB_SETUP1_BYTE6_POS              16
+#define MXC_F_USB_SETUP1_BYTE6                  ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE6_POS))
+#define MXC_F_USB_SETUP1_BYTE7_POS              24
+#define MXC_F_USB_SETUP1_BYTE7                  ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE7_POS))
+
+#define MXC_F_USB_EP0_EP_DIR_POS                0
+#define MXC_F_USB_EP0_EP_DIR                    ((uint32_t)(0x00000003UL << MXC_F_USB_EP0_EP_DIR_POS))
+#define MXC_F_USB_EP0_EP_BUF2_POS               3
+#define MXC_F_USB_EP0_EP_BUF2                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_BUF2_POS))
+#define MXC_F_USB_EP0_EP_INT_EN_POS             4
+#define MXC_F_USB_EP0_EP_INT_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_INT_EN_POS))
+#define MXC_F_USB_EP0_EP_NAK_EN_POS             5
+#define MXC_F_USB_EP0_EP_NAK_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_NAK_EN_POS))
+#define MXC_F_USB_EP0_EP_DT_POS                 6
+#define MXC_F_USB_EP0_EP_DT                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_DT_POS))
+#define MXC_F_USB_EP0_EP_STALL_POS              8
+#define MXC_F_USB_EP0_EP_STALL                  ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_STALL_POS))
+#define MXC_F_USB_EP0_EP_ST_STALL_POS           9
+#define MXC_F_USB_EP0_EP_ST_STALL               ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_ST_STALL_POS))
+#define MXC_F_USB_EP0_EP_ST_ACK_POS             10
+#define MXC_F_USB_EP0_EP_ST_ACK                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP1_EP_DIR_POS                0
+#define MXC_F_USB_EP1_EP_DIR                    ((uint32_t)(0x00000003UL << MXC_F_USB_EP1_EP_DIR_POS))
+#define MXC_F_USB_EP1_EP_BUF2_POS               3
+#define MXC_F_USB_EP1_EP_BUF2                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_BUF2_POS))
+#define MXC_F_USB_EP1_EP_INT_EN_POS             4
+#define MXC_F_USB_EP1_EP_INT_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_INT_EN_POS))
+#define MXC_F_USB_EP1_EP_NAK_EN_POS             5
+#define MXC_F_USB_EP1_EP_NAK_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_NAK_EN_POS))
+#define MXC_F_USB_EP1_EP_DT_POS                 6
+#define MXC_F_USB_EP1_EP_DT                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_DT_POS))
+#define MXC_F_USB_EP1_EP_STALL_POS              8
+#define MXC_F_USB_EP1_EP_STALL                  ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_STALL_POS))
+#define MXC_F_USB_EP1_EP_ST_STALL_POS           9
+#define MXC_F_USB_EP1_EP_ST_STALL               ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_ST_STALL_POS))
+#define MXC_F_USB_EP1_EP_ST_ACK_POS             10
+#define MXC_F_USB_EP1_EP_ST_ACK                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP2_EP_DIR_POS                0
+#define MXC_F_USB_EP2_EP_DIR                    ((uint32_t)(0x00000003UL << MXC_F_USB_EP2_EP_DIR_POS))
+#define MXC_F_USB_EP2_EP_BUF2_POS               3
+#define MXC_F_USB_EP2_EP_BUF2                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_BUF2_POS))
+#define MXC_F_USB_EP2_EP_INT_EN_POS             4
+#define MXC_F_USB_EP2_EP_INT_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_INT_EN_POS))
+#define MXC_F_USB_EP2_EP_NAK_EN_POS             5
+#define MXC_F_USB_EP2_EP_NAK_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_NAK_EN_POS))
+#define MXC_F_USB_EP2_EP_DT_POS                 6
+#define MXC_F_USB_EP2_EP_DT                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_DT_POS))
+#define MXC_F_USB_EP2_EP_STALL_POS              8
+#define MXC_F_USB_EP2_EP_STALL                  ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_STALL_POS))
+#define MXC_F_USB_EP2_EP_ST_STALL_POS           9
+#define MXC_F_USB_EP2_EP_ST_STALL               ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_ST_STALL_POS))
+#define MXC_F_USB_EP2_EP_ST_ACK_POS             10
+#define MXC_F_USB_EP2_EP_ST_ACK                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP3_EP_DIR_POS                0
+#define MXC_F_USB_EP3_EP_DIR                    ((uint32_t)(0x00000003UL << MXC_F_USB_EP3_EP_DIR_POS))
+#define MXC_F_USB_EP3_EP_BUF2_POS               3
+#define MXC_F_USB_EP3_EP_BUF2                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_BUF2_POS))
+#define MXC_F_USB_EP3_EP_INT_EN_POS             4
+#define MXC_F_USB_EP3_EP_INT_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_INT_EN_POS))
+#define MXC_F_USB_EP3_EP_NAK_EN_POS             5
+#define MXC_F_USB_EP3_EP_NAK_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_NAK_EN_POS))
+#define MXC_F_USB_EP3_EP_DT_POS                 6
+#define MXC_F_USB_EP3_EP_DT                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_DT_POS))
+#define MXC_F_USB_EP3_EP_STALL_POS              8
+#define MXC_F_USB_EP3_EP_STALL                  ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_STALL_POS))
+#define MXC_F_USB_EP3_EP_ST_STALL_POS           9
+#define MXC_F_USB_EP3_EP_ST_STALL               ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_ST_STALL_POS))
+#define MXC_F_USB_EP3_EP_ST_ACK_POS             10
+#define MXC_F_USB_EP3_EP_ST_ACK                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP4_EP_DIR_POS                0
+#define MXC_F_USB_EP4_EP_DIR                    ((uint32_t)(0x00000003UL << MXC_F_USB_EP4_EP_DIR_POS))
+#define MXC_F_USB_EP4_EP_BUF2_POS               3
+#define MXC_F_USB_EP4_EP_BUF2                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_BUF2_POS))
+#define MXC_F_USB_EP4_EP_INT_EN_POS             4
+#define MXC_F_USB_EP4_EP_INT_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_INT_EN_POS))
+#define MXC_F_USB_EP4_EP_NAK_EN_POS             5
+#define MXC_F_USB_EP4_EP_NAK_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_NAK_EN_POS))
+#define MXC_F_USB_EP4_EP_DT_POS                 6
+#define MXC_F_USB_EP4_EP_DT                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_DT_POS))
+#define MXC_F_USB_EP4_EP_STALL_POS              8
+#define MXC_F_USB_EP4_EP_STALL                  ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_STALL_POS))
+#define MXC_F_USB_EP4_EP_ST_STALL_POS           9
+#define MXC_F_USB_EP4_EP_ST_STALL               ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_ST_STALL_POS))
+#define MXC_F_USB_EP4_EP_ST_ACK_POS             10
+#define MXC_F_USB_EP4_EP_ST_ACK                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP5_EP_DIR_POS                0
+#define MXC_F_USB_EP5_EP_DIR                    ((uint32_t)(0x00000003UL << MXC_F_USB_EP5_EP_DIR_POS))
+#define MXC_F_USB_EP5_EP_BUF2_POS               3
+#define MXC_F_USB_EP5_EP_BUF2                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_BUF2_POS))
+#define MXC_F_USB_EP5_EP_INT_EN_POS             4
+#define MXC_F_USB_EP5_EP_INT_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_INT_EN_POS))
+#define MXC_F_USB_EP5_EP_NAK_EN_POS             5
+#define MXC_F_USB_EP5_EP_NAK_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_NAK_EN_POS))
+#define MXC_F_USB_EP5_EP_DT_POS                 6
+#define MXC_F_USB_EP5_EP_DT                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_DT_POS))
+#define MXC_F_USB_EP5_EP_STALL_POS              8
+#define MXC_F_USB_EP5_EP_STALL                  ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_STALL_POS))
+#define MXC_F_USB_EP5_EP_ST_STALL_POS           9
+#define MXC_F_USB_EP5_EP_ST_STALL               ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_ST_STALL_POS))
+#define MXC_F_USB_EP5_EP_ST_ACK_POS             10
+#define MXC_F_USB_EP5_EP_ST_ACK                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP6_EP_DIR_POS                0
+#define MXC_F_USB_EP6_EP_DIR                    ((uint32_t)(0x00000003UL << MXC_F_USB_EP6_EP_DIR_POS))
+#define MXC_F_USB_EP6_EP_BUF2_POS               3
+#define MXC_F_USB_EP6_EP_BUF2                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_BUF2_POS))
+#define MXC_F_USB_EP6_EP_INT_EN_POS             4
+#define MXC_F_USB_EP6_EP_INT_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_INT_EN_POS))
+#define MXC_F_USB_EP6_EP_NAK_EN_POS             5
+#define MXC_F_USB_EP6_EP_NAK_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_NAK_EN_POS))
+#define MXC_F_USB_EP6_EP_DT_POS                 6
+#define MXC_F_USB_EP6_EP_DT                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_DT_POS))
+#define MXC_F_USB_EP6_EP_STALL_POS              8
+#define MXC_F_USB_EP6_EP_STALL                  ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_STALL_POS))
+#define MXC_F_USB_EP6_EP_ST_STALL_POS           9
+#define MXC_F_USB_EP6_EP_ST_STALL               ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_ST_STALL_POS))
+#define MXC_F_USB_EP6_EP_ST_ACK_POS             10
+#define MXC_F_USB_EP6_EP_ST_ACK                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP7_EP_DIR_POS                0
+#define MXC_F_USB_EP7_EP_DIR                    ((uint32_t)(0x00000003UL << MXC_F_USB_EP7_EP_DIR_POS))
+#define MXC_F_USB_EP7_EP_BUF2_POS               3
+#define MXC_F_USB_EP7_EP_BUF2                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_BUF2_POS))
+#define MXC_F_USB_EP7_EP_INT_EN_POS             4
+#define MXC_F_USB_EP7_EP_INT_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_INT_EN_POS))
+#define MXC_F_USB_EP7_EP_NAK_EN_POS             5
+#define MXC_F_USB_EP7_EP_NAK_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_NAK_EN_POS))
+#define MXC_F_USB_EP7_EP_DT_POS                 6
+#define MXC_F_USB_EP7_EP_DT                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_DT_POS))
+#define MXC_F_USB_EP7_EP_STALL_POS              8
+#define MXC_F_USB_EP7_EP_STALL                  ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_STALL_POS))
+#define MXC_F_USB_EP7_EP_ST_STALL_POS           9
+#define MXC_F_USB_EP7_EP_ST_STALL               ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_ST_STALL_POS))
+#define MXC_F_USB_EP7_EP_ST_ACK_POS             10
+#define MXC_F_USB_EP7_EP_ST_ACK                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP_DIR_POS                    (0)
+#define MXC_F_USB_EP_DIR                        ((uint32_t)(0x00000003UL << MXC_F_USB_EP_DIR_POS))
+
+#define MXC_V_USB_EP_DIR_DISABLE                ((uint32_t)0x00000000UL)
+#define MXC_V_USB_EP_DIR_OUT                    ((uint32_t)0x00000001UL)
+#define MXC_V_USB_EP_DIR_IN                     ((uint32_t)0x00000002UL)
+#define MXC_V_USB_EP_DIR_CONTROL                ((uint32_t)0x00000003UL)
+
+#define MXC_S_USB_EP_DIR_DISABLE                (MXC_V_USB_EP_DIR_DISABLE << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_OUT                    (MXC_V_USB_EP_DIR_OUT << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_IN                     (MXC_V_USB_EP_DIR_IN << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_CONTROL                (MXC_V_USB_EP_DIR_CONTROL << MXC_F_USB_EP_DIR_POS)
+
+#define MXC_F_USB_EP_BUF2_POS                   (3)
+#define MXC_F_USB_EP_BUF2                       ((uint32_t)(0x00000001UL << MXC_F_USB_EP_BUF2_POS))
+#define MXC_F_USB_EP_INTEN_POS                  (4)
+#define MXC_F_USB_EP_INT_EN                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP_INTEN_POS))
+#define MXC_F_USB_EP_NAK_EN_POS                 (5)
+#define MXC_F_USB_EP_NAK_EN                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP_NAK_EN_POS))
+#define MXC_F_USB_EP_DT_POS                     (6)
+#define MXC_F_USB_EP_DT                         ((uint32_t)(0x00000001UL << MXC_F_USB_EP_DT_POS))
+#define MXC_F_USB_EP_STALL_POS                  (8)
+#define MXC_F_USB_EP_STALL                      ((uint32_t)(0x00000001UL << MXC_F_USB_EP_STALL_POS))
+#define MXC_F_USB_EP_ST_STALL_POS               (9)
+#define MXC_F_USB_EP_ST_STALL                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_STALL_POS))
+#define MXC_F_USB_EP_ST_ACK_POS                 (10)
+#define MXC_F_USB_EP_ST_ACK                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_ACK_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_USB_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/wdt_regs.h

@@ -0,0 +1,150 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_WDT_REGS_H_
+#define _MXC_WDT_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  wdt_regs.h
+ * @addtogroup wdt WDT
+ * @{
+ */
+
+/**
+ * @brief Defines watchdog timer periods
+ */
+typedef enum {
+    /** 2^31 cycle period */
+    MXC_E_WDT_PERIOD_2_31_CLKS = 0,
+    /** 2^30 cycle period */
+    MXC_E_WDT_PERIOD_2_30_CLKS,
+    /** 2^29 cycle period */
+    MXC_E_WDT_PERIOD_2_29_CLKS,
+    /** 2^28 cycle period */
+    MXC_E_WDT_PERIOD_2_28_CLKS,
+    /** 2^27 cycle period */
+    MXC_E_WDT_PERIOD_2_27_CLKS,
+    /** 2^26 cycle period */
+    MXC_E_WDT_PERIOD_2_26_CLKS,
+    /** 2^25 cycle period */
+    MXC_E_WDT_PERIOD_2_25_CLKS,
+    /** 2^24 cycle period */
+    MXC_E_WDT_PERIOD_2_24_CLKS,
+    /** 2^23 cycle period */
+    MXC_E_WDT_PERIOD_2_23_CLKS,
+    /** 2^22 cycle period */
+    MXC_E_WDT_PERIOD_2_22_CLKS,
+    /** 2^21 cycle period */
+    MXC_E_WDT_PERIOD_2_21_CLKS,
+    /** 2^20 cycle period */
+    MXC_E_WDT_PERIOD_2_20_CLKS,
+    /** 2^19 cycle period */
+    MXC_E_WDT_PERIOD_2_19_CLKS,
+    /** 2^18 cycle period */
+    MXC_E_WDT_PERIOD_2_18_CLKS,
+    /** 2^17 cycle period */
+    MXC_E_WDT_PERIOD_2_17_CLKS,
+    /** 2^16 cycle period */
+    MXC_E_WDT_PERIOD_2_16_CLKS,
+} mxc_wdt_period_t;
+
+/*                                  Offset   Register Description
+                                    ======   ================================================ */
+typedef struct {
+    __IO uint32_t ctrl;         /*  0x0000   Watchdog Timer Control Register                  */
+    __IO uint32_t clear;        /*  0x0004   Watchdog Clear Register (Feed Dog)               */
+    __IO uint32_t int_rst_fl;   /*  0x0008   Watchdog Interrupt/Reset Flags                   */
+    __IO uint32_t int_rst_en;   /*  0x000C   Interrupt/Reset Enable/Disable Controls          */
+    __I uint32_t rsv0010;       /*  0x0010                                                    */
+    __IO uint32_t lock_ctrl;    /*  0x0014   Lock Register Setting for WDT CTRL               */
+} mxc_wdt_regs_t;
+
+/*
+   Register offsets for module WDT.
+*/
+#define MXC_R_WDT_OFFS_CTRL                       ((uint32_t)0x00000000UL)
+#define MXC_R_WDT_OFFS_CLEAR                      ((uint32_t)0x00000004UL)
+#define MXC_R_WDT_OFFS_INT_RST_FL                 ((uint32_t)0x00000008UL)
+#define MXC_R_WDT_OFFS_INT_RST_EN                 ((uint32_t)0x0000000CUL)
+#define MXC_R_WDT_OFFS_LOCK_CTRL                  ((uint32_t)0x00000014UL)
+
+#define MXC_V_WDT_WDLOCK_LOCK_KEY                 ((uint8_t)0x24)
+#define MXC_V_WDT_WDLOCK_UNLOCK_KEY               ((uint8_t)0x42)
+
+
+/*
+   Field positions and masks for module WDT.
+*/
+#define MXC_F_WDT_CTRL_INT_PERIOD_POS       0
+#define MXC_F_WDT_CTRL_INT_PERIOD           ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS))
+#define MXC_F_WDT_CTRL_RST_PERIOD_POS       4
+#define MXC_F_WDT_CTRL_RST_PERIOD           ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS))
+#define MXC_F_WDT_CTRL_EN_TIMER_POS         8
+#define MXC_F_WDT_CTRL_EN_TIMER             ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS))
+#define MXC_F_WDT_CTRL_EN_CLOCK_POS         9
+#define MXC_F_WDT_CTRL_EN_CLOCK             ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS))
+#define MXC_F_WDT_CTRL_WAIT_PERIOD_POS      12
+#define MXC_F_WDT_CTRL_WAIT_PERIOD          ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
+
+#define MXC_F_WDT_FLAGS_TIMEOUT_POS         0
+#define MXC_F_WDT_FLAGS_TIMEOUT             ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS))
+#define MXC_F_WDT_FLAGS_PRE_WIN_POS         1
+#define MXC_F_WDT_FLAGS_PRE_WIN             ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS))
+#define MXC_F_WDT_FLAGS_RESET_OUT_POS       2
+#define MXC_F_WDT_FLAGS_RESET_OUT           ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS))
+
+#define MXC_F_WDT_ENABLE_TIMEOUT_POS        0
+#define MXC_F_WDT_ENABLE_TIMEOUT            ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS))
+#define MXC_F_WDT_ENABLE_PRE_WIN_POS        1
+#define MXC_F_WDT_ENABLE_PRE_WIN            ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS))
+#define MXC_F_WDT_ENABLE_RESET_OUT_POS      2
+#define MXC_F_WDT_ENABLE_RESET_OUT          ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS))
+
+#define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS      0
+#define MXC_F_WDT_LOCK_CTRL_WDLOCK          ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_WDT_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/startup_MAX32610.s

@@ -1,35 +1,34 @@
-/*******************************************************************************
- * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
- * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Except as contained in this notice, the name of Maxim Integrated
- * Products, Inc. shall not be used except as stated in the Maxim Integrated
- * Products, Inc. Branding Policy.
- *
- * The mere transfer of this software does not imply any licenses
- * of trade secrets, proprietary technology, copyrights, patents,
- * trademarks, maskwork rights, or any other form of intellectual
- * property whatsoever. Maxim Integrated Products, Inc. retains all
- * ownership rights.
- *******************************************************************************
- */
+;*******************************************************************************
+; Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+;
+; Permission is hereby granted, free of charge, to any person obtaining a
+; copy of this software and associated documentation files (the "Software"),
+; to deal in the Software without restriction, including without limitation
+; the rights to use, copy, modify, merge, publish, distribute, sublicense,
+; and/or sell copies of the Software, and to permit persons to whom the
+; Software is furnished to do so, subject to the following conditions:
+;
+; The above copyright notice and this permission notice shall be included
+; in all copies or substantial portions of the Software.
+;
+; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+; OTHER DEALINGS IN THE SOFTWARE.
+;
+; Except as contained in this notice, the name of Maxim Integrated
+; Products, Inc. shall not be used except as stated in the Maxim Integrated
+; Products, Inc. Branding Policy.
+;
+; The mere transfer of this software does not imply any licenses
+; of trade secrets, proprietary technology, copyrights, patents,
+; trademarks, maskwork rights, or any other form of intellectual
+; property whatsoever. Maxim Integrated Products, Inc. retains all
+; ownership rights.
+;*******************************************************************************
 
 __initial_sp        EQU     0x20008000  ; Top of RAM
 
@@ -44,71 +43,71 @@ __initial_sp        EQU     0x20008000  ; Top of RAM
                 EXPORT  __Vectors_End
                 EXPORT  __Vectors_Size
 
-__Vectors       DCD     __initial_sp              /* Top of Stack */
-                DCD     Reset_Handler             /* Reset Handler */
-                DCD     NMI_Handler               /* NMI Handler */
-                DCD     HardFault_Handler         /* Hard Fault Handler */
-                DCD     DefaultIRQ_Handler        /* MPU Fault Handler */
-                DCD     DefaultIRQ_Handler        /* Bus Fault Handler */
-                DCD     DefaultIRQ_Handler        /* Usage Fault Handler */
-                DCD     0                         /* Reserved */
-                DCD     0                         /* Reserved */
-                DCD     0                         /* Reserved */
-                DCD     0                         /* Reserved */
-                DCD     DefaultIRQ_Handler        /* SVCall Handler */
-                DCD     DebugMon_Handler          /* Debug Monitor Handler */
-                DCD     0                         /* Reserved */
-                DCD     DefaultIRQ_Handler        /* PendSV Handler */
-                DCD     SysTick_IRQHandler        /* SysTick Handler */
+__Vectors       DCD     __initial_sp              ; Top of Stack 
+                DCD     Reset_Handler             ; Reset Handler 
+                DCD     NMI_Handler               ; NMI Handler 
+                DCD     HardFault_Handler         ; Hard Fault Handler 
+                DCD     DefaultIRQ_Handler        ; MPU Fault Handler 
+                DCD     DefaultIRQ_Handler        ; Bus Fault Handler 
+                DCD     DefaultIRQ_Handler        ; Usage Fault Handler 
+                DCD     0                         ; Reserved 
+                DCD     0                         ; Reserved 
+                DCD     0                         ; Reserved 
+                DCD     0                         ; Reserved 
+                DCD     DefaultIRQ_Handler        ; SVCall Handler 
+                DCD     DebugMon_Handler          ; Debug Monitor Handler 
+                DCD     0                         ; Reserved 
+                DCD     DefaultIRQ_Handler        ; PendSV Handler 
+                DCD     SysTick_IRQHandler        ; SysTick Handler 
 
-                /* Maxim 32610 Externals interrupts */
-                DCD     UART0_IRQHandler          /* 16: 1 UART0 */
-                DCD     UART1_IRQHandler          /* 17: 2 UART1 */
-                DCD     I2CM0_IRQHandler          /* 18: 3 I2C Master 0 */
-                DCD     I2CS_IRQHandler           /* 19: 4 I2C Slave */
-                DCD     USB_IRQHandler            /* 20: 5 USB */
-                DCD     PMU_IRQHandler            /* 21: 6 DMA */
-                DCD     AFE_IRQHandler            /* 22: 7 AFE */
-                DCD     MAA_IRQHandler            /* 23: 8 MAA */
-                DCD     AES_IRQHandler            /* 24: 9 AES */
-                DCD     SPI0_IRQHandler           /* 25:10 SPI0 */
-                DCD     SPI1_IRQHandler           /* 26:11 SPI1 */
-                DCD     SPI2_IRQHandler           /* 27:12 SPI2 */
-                DCD     TMR0_IRQHandler           /* 28:13 Timer32-0 */
-                DCD     TMR1_IRQHandler           /* 29:14 Timer32-1 */
-                DCD     TMR2_IRQHandler           /* 30:15 Timer32-1 */
-                DCD     TMR3_IRQHandler           /* 31:16 Timer32-2 */
-                DCD     RSVD0_IRQHandler          /* 32:17 RSVD */
-                DCD     RSVD1_IRQHandler          /* 33:18 RSVD */
-                DCD     DAC0_IRQHandler           /* 34:19 DAC0  (12-bit DAC) */  
-                DCD     DAC1_IRQHandler           /* 35:20 DAC1  (12-bit DAC) */  
-                DCD     DAC2_IRQHandler           /* 36:21 DAC2  (8-bit DAC) */
-                DCD     DAC3_IRQHandler           /* 37:22 DAC3  (8-bit DAC) */
-                DCD     ADC_IRQHandler            /* 38:23 ADC */
-                DCD     FLC_IRQHandler            /* 39:24 Flash Controller */
-                DCD     PWRMAN_IRQHandler         /* 40:25 PWRMAN */
-                DCD     CLKMAN_IRQHandler         /* 41:26 CLKMAN */
-                DCD     RTC0_IRQHandler           /* 42:27 RTC INT0 */
-                DCD     RTC1_IRQHandler           /* 43:28 RTC INT1 */
-                DCD     RTC2_IRQHandler           /* 44:29 RTC INT2 */
-                DCD     RTC3_IRQHandler           /* 45:30 RTC INT3 */
-                DCD     WDT0_IRQHandler           /* 46:31 WATCHDOG0 */
-                DCD     WDT0_P_IRQHandler         /* 47:32 WATCHDOG0 PRE-WINDOW */
-                DCD     WDT1_IRQHandler           /* 48:33 WATCHDOG1 */
-                DCD     WDT1_P_IRQHandler         /* 49:34 WATCHDOG1 PRE-WINDOW */
-                DCD     GPIO_P0_IRQHandler        /* 50:35 GPIO Port 0  */
-                DCD     GPIO_P1_IRQHandler        /* 51:36 GPIO Port 1  */
-                DCD     GPIO_P2_IRQHandler        /* 52:37 GPIO Port 2  */
-                DCD     GPIO_P3_IRQHandler        /* 53:38 GPIO Port 3  */
-                DCD     GPIO_P4_IRQHandler        /* 54:39 GPIO Port 4  */
-                DCD     GPIO_P5_IRQHandler        /* 55:40 GPIO Port 5  */
-                DCD     GPIO_P6_IRQHandler        /* 56:41 GPIO Port 6  */
-                DCD     GPIO_P7_IRQHandler        /* 57:42 GPIO Port 7  */
-                DCD     TMR16_0_IRQHandler        /* 58:43 Timer16-s0 */
-                DCD     TMR16_1_IRQHandler        /* 59:44 Timer16-s1 */
-                DCD     TMR16_2_IRQHandler        /* 60:45 Timer16-s2 */
-                DCD     TMR16_3_IRQHandler        /* 61:46 Timer16-s3 */
-                DCD     I2CM1_IRQHandler          /* 62:47 I2C Master 1 */
+                ; Maxim 32610 Externals interrupts 
+                DCD     UART0_IRQHandler          ; 16: 1 UART0 
+                DCD     UART1_IRQHandler          ; 17: 2 UART1 
+                DCD     I2CM0_IRQHandler          ; 18: 3 I2C Master 0 
+                DCD     I2CS_IRQHandler           ; 19: 4 I2C Slave 
+                DCD     USB_IRQHandler            ; 20: 5 USB 
+                DCD     PMU_IRQHandler            ; 21: 6 DMA 
+                DCD     AFE_IRQHandler            ; 22: 7 AFE 
+                DCD     MAA_IRQHandler            ; 23: 8 MAA 
+                DCD     AES_IRQHandler            ; 24: 9 AES 
+                DCD     SPI0_IRQHandler           ; 25:10 SPI0 
+                DCD     SPI1_IRQHandler           ; 26:11 SPI1 
+                DCD     SPI2_IRQHandler           ; 27:12 SPI2 
+                DCD     TMR0_IRQHandler           ; 28:13 Timer32-0 
+                DCD     TMR1_IRQHandler           ; 29:14 Timer32-1 
+                DCD     TMR2_IRQHandler           ; 30:15 Timer32-1 
+                DCD     TMR3_IRQHandler           ; 31:16 Timer32-2 
+                DCD     RSVD0_IRQHandler          ; 32:17 RSVD 
+                DCD     RSVD1_IRQHandler          ; 33:18 RSVD 
+                DCD     DAC0_IRQHandler           ; 34:19 DAC0  (12-bit DAC)   
+                DCD     DAC1_IRQHandler           ; 35:20 DAC1  (12-bit DAC)   
+                DCD     DAC2_IRQHandler           ; 36:21 DAC2  (8-bit DAC) 
+                DCD     DAC3_IRQHandler           ; 37:22 DAC3  (8-bit DAC) 
+                DCD     ADC_IRQHandler            ; 38:23 ADC 
+                DCD     FLC_IRQHandler            ; 39:24 Flash Controller 
+                DCD     PWRMAN_IRQHandler         ; 40:25 PWRMAN 
+                DCD     CLKMAN_IRQHandler         ; 41:26 CLKMAN 
+                DCD     RTC0_IRQHandler           ; 42:27 RTC INT0 
+                DCD     RTC1_IRQHandler           ; 43:28 RTC INT1 
+                DCD     RTC2_IRQHandler           ; 44:29 RTC INT2 
+                DCD     RTC3_IRQHandler           ; 45:30 RTC INT3 
+                DCD     WDT0_IRQHandler           ; 46:31 WATCHDOG0 
+                DCD     WDT0_P_IRQHandler         ; 47:32 WATCHDOG0 PRE-WINDOW 
+                DCD     WDT1_IRQHandler           ; 48:33 WATCHDOG1 
+                DCD     WDT1_P_IRQHandler         ; 49:34 WATCHDOG1 PRE-WINDOW 
+                DCD     GPIO_P0_IRQHandler        ; 50:35 GPIO Port 0  
+                DCD     GPIO_P1_IRQHandler        ; 51:36 GPIO Port 1  
+                DCD     GPIO_P2_IRQHandler        ; 52:37 GPIO Port 2  
+                DCD     GPIO_P3_IRQHandler        ; 53:38 GPIO Port 3  
+                DCD     GPIO_P4_IRQHandler        ; 54:39 GPIO Port 4  
+                DCD     GPIO_P5_IRQHandler        ; 55:40 GPIO Port 5  
+                DCD     GPIO_P6_IRQHandler        ; 56:41 GPIO Port 6  
+                DCD     GPIO_P7_IRQHandler        ; 57:42 GPIO Port 7  
+                DCD     TMR16_0_IRQHandler        ; 58:43 Timer16-s0 
+                DCD     TMR16_1_IRQHandler        ; 59:44 Timer16-s1 
+                DCD     TMR16_2_IRQHandler        ; 60:45 Timer16-s2 
+                DCD     TMR16_3_IRQHandler        ; 61:46 Timer16-s3 
+                DCD     I2CM1_IRQHandler          ; 62:47 I2C Master 1 
 __Vectors_End
 
 __Vectors_Size  EQU  __Vectors_End - __Vectors

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c

@@ -109,7 +109,7 @@ void ICC_Enable(void)
 }
 
 // This function to be implemented by the hal
-extern void low_level_init();
+extern void low_level_init(void);
 
 void SystemInit(void)
 {

libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/nRF51822.sct

@@ -12,8 +12,8 @@
 ;
 ;WITH SOFTDEVICE:
 
-LR_IROM1 0x16000 0x002A000  {
-  ER_IROM1 0x16000 0x002A000  {
+LR_IROM1 0x18000 0x0028000  {
+  ER_IROM1 0x18000 0x0028000  {
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
@@ -22,6 +22,3 @@ LR_IROM1 0x16000 0x002A000  {
    .ANY (+RW +ZI)
   }
 }
-
-
-

libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct

@@ -12,8 +12,8 @@
 ;
 ;WITH SOFTDEVICE:
 
-LR_IROM1 0x16000 0x002A000  {
-  ER_IROM1 0x16000 0x002A000  {
+LR_IROM1 0x18000 0x0028000  {
+  ER_IROM1 0x18000 0x0028000  {
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
@@ -22,6 +22,3 @@ LR_IROM1 0x16000 0x002A000  {
    .ANY (+RW +ZI)
   }
 }
-
-
-

libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_16K/NRF51822.ld

@@ -2,7 +2,7 @@
 
 MEMORY
 {
-  FLASH (rx) : ORIGIN = 0x00016000, LENGTH = 0x2A000
+  FLASH (rx) : ORIGIN = 0x00018000, LENGTH = 0x28000
   RAM (rwx) :  ORIGIN = 0x20002000, LENGTH = 0x2000
 }
 

libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld

@@ -2,7 +2,7 @@
 
 MEMORY
 {
-  FLASH (rx) : ORIGIN = 0x00016000, LENGTH = 0x2A000
+  FLASH (rx) : ORIGIN = 0x00018000, LENGTH = 0x28000
   RAM (rwx) :  ORIGIN = 0x20002000, LENGTH = 0x6000
 }
 

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/startup_LPC824.s

@@ -98,16 +98,28 @@ __isr_vector:
 /* LPC824 interrupts */
     .long    SPI0_IRQHandler                         // SPI0 controller
     .long    SPI1_IRQHandler                         // SPI1 controller
+    .long    0                                       // Reserved
     .long    UART0_IRQHandler                        // UART0
     .long    UART1_IRQHandler                        // UART1
     .long    UART2_IRQHandler                        // UART2
-    .long    I2C_IRQHandler                         // I2C controller
+    .long    0                                       // Reserved
+    .long    I2C1_IRQHandler                         // I2C ch1 controller
+    .long    I2C0_IRQHandler                         // I2C ch0 controller
     .long    SCT_IRQHandler                          // Smart Counter Timer
     .long    MRT_IRQHandler                          // Multi-Rate Timer
     .long    CMP_IRQHandler                          // Comparator
     .long    WDT_IRQHandler                          // PIO1 (0:11)
     .long    BOD_IRQHandler                          // Brown Out Detect
+    .long    Flash_IRQHandler                        // Flash interrupt
     .long    WKT_IRQHandler                          // Wakeup timer
+    .long    ADC_SEQA_IRQHandler                     // ADC sequence A completion
+    .long    ADC_SEQB_IRQHandler                     // ADC sequence B completion
+    .long    ADC_THCMP_IRQHandler                    // ADC threshold compare
+    .long    ADC_OVR_IRQHandler                      // ADC overrun
+    .long    DMA_IRQHandler                          // DMA interrupt
+    .long    I2C2_IRQHandler                         // I2C2 controller
+    .long    I2C3_IRQHandler                         // I2C3 controller
+    .long    0                                       // Reserved
     .long    PININT0_IRQHandler                      // PIO INT0
     .long    PININT1_IRQHandler                      // PIO INT1
     .long    PININT2_IRQHandler                      // PIO INT2
@@ -181,18 +193,28 @@ Reset_Handler:
     .weak     \handler_name
     .set      \handler_name, Default_Handler
     .endm
+
     def_irq_default_handler    SPI0_IRQHandler
     def_irq_default_handler    SPI1_IRQHandler
     def_irq_default_handler    UART0_IRQHandler
     def_irq_default_handler    UART1_IRQHandler
     def_irq_default_handler    UART2_IRQHandler
-    def_irq_default_handler    I2C_IRQHandler
+    def_irq_default_handler    I2C0_IRQHandler
+    def_irq_default_handler    I2C1_IRQHandler
+    def_irq_default_handler    I2C2_IRQHandler
+    def_irq_default_handler    I2C3_IRQHandler
     def_irq_default_handler    SCT_IRQHandler
     def_irq_default_handler    MRT_IRQHandler
     def_irq_default_handler    CMP_IRQHandler
     def_irq_default_handler    WDT_IRQHandler
     def_irq_default_handler    BOD_IRQHandler
+    def_irq_default_handler    Flash_IRQHandler
     def_irq_default_handler    WKT_IRQHandler
+    def_irq_default_handler    ADC_SEQA_IRQHandler
+    def_irq_default_handler    ADC_SEQB_IRQHandler
+    def_irq_default_handler    ADC_THCMP_IRQHandler
+    def_irq_default_handler    ADC_OVR_IRQHandler
+    def_irq_default_handler    DMA_IRQHandler
     def_irq_default_handler    PININT0_IRQHandler
     def_irq_default_handler    PININT1_IRQHandler
     def_irq_default_handler    PININT2_IRQHandler
@@ -200,7 +222,7 @@ Reset_Handler:
     def_irq_default_handler    PININT4_IRQHandler
     def_irq_default_handler    PININT5_IRQHandler
     def_irq_default_handler    PININT6_IRQHandler
-    def_irq_default_handler    PININT7_IRQHandler    
+    def_irq_default_handler    PININT7_IRQHandler
 
     .end
 

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/LPC824.ld

@@ -0,0 +1,152 @@
+/* Linker script for mbed LPC824-GCC-ARM based on LPC1114-GCC-ARM-LPC1114.ld */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  /* Define each memory region */
+  FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32K bytes */
+  RAM (rwx) : ORIGIN = 0x10000000+0xC0, LENGTH = 0x2000-0xC0 /* 8K bytes */
+
+
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+		*(.text.Reset_Handler)
+        *(.text.SystemInit)
+		. = 0x200;
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+        
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss :
+    {
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+    } > RAM
+    
+    .heap :
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy :
+    {
+        *(.stack)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+    
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/startup_LPC824.s

@@ -0,0 +1,228 @@
+/* File: startup_ARMCM0.S
+ * Purpose: startup file for Cortex-M0 devices. Should use with 
+ *   GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ * 
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the ARM Limited nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+    .syntax unified
+    .arch armv6-m
+
+/* Memory Model
+   The HEAP starts at the end of the DATA section and grows upward.
+   
+   The STACK starts at the end of the RAM and grows downward.
+   
+   The HEAP and stack STACK are only checked at compile time:
+   (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+   
+   This is just a check for the bare minimum for the Heap+Stack area before
+   aborting compilation, it is not the run time limit:
+   Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+    .section .stack
+    .align 3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0x80
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    Stack_Size
+    .size __StackLimit, . - __StackLimit
+__StackTop:
+    .size __StackTop, . - __StackTop
+
+    .section .heap
+    .align 3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x80
+#endif
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .space    Heap_Size
+    .size __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size __HeapLimit, . - __HeapLimit
+    
+    .section .isr_vector
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long    __StackTop            /* Top of Stack */
+    .long    Reset_Handler         /* Reset Handler */
+    .long    NMI_Handler           /* NMI Handler */
+    .long    HardFault_Handler     /* Hard Fault Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    SVC_Handler           /* SVCall Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    PendSV_Handler        /* PendSV Handler */
+    .long    SysTick_Handler       /* SysTick Handler */
+
+/* LPC824 interrupts */
+    .long    SPI0_IRQHandler                         // SPI0 controller
+    .long    SPI1_IRQHandler                         // SPI1 controller
+    .long    0                                       // Reserved
+    .long    UART0_IRQHandler                        // UART0
+    .long    UART1_IRQHandler                        // UART1
+    .long    UART2_IRQHandler                        // UART2
+    .long    0                                       // Reserved
+    .long    I2C1_IRQHandler                         // I2C ch1 controller
+    .long    I2C0_IRQHandler                         // I2C ch0 controller
+    .long    SCT_IRQHandler                          // Smart Counter Timer
+    .long    MRT_IRQHandler                          // Multi-Rate Timer
+    .long    CMP_IRQHandler                          // Comparator
+    .long    WDT_IRQHandler                          // PIO1 (0:11)
+    .long    BOD_IRQHandler                          // Brown Out Detect
+    .long    Flash_IRQHandler                        // Flash interrupt
+    .long    WKT_IRQHandler                          // Wakeup timer
+    .long    ADC_SEQA_IRQHandler                     // ADC sequence A completion
+    .long    ADC_SEQB_IRQHandler                     // ADC sequence B completion
+    .long    ADC_THCMP_IRQHandler                    // ADC threshold compare
+    .long    ADC_OVR_IRQHandler                      // ADC overrun
+    .long    DMA_IRQHandler                          // DMA interrupt
+    .long    I2C2_IRQHandler                         // I2C2 controller
+    .long    I2C3_IRQHandler                         // I2C3 controller
+    .long    0                                       // Reserved
+    .long    PININT0_IRQHandler                      // PIO INT0
+    .long    PININT1_IRQHandler                      // PIO INT1
+    .long    PININT2_IRQHandler                      // PIO INT2
+    .long    PININT3_IRQHandler                      // PIO INT3
+    .long    PININT4_IRQHandler                      // PIO INT4
+    .long    PININT5_IRQHandler                      // PIO INT5
+    .long    PININT6_IRQHandler                      // PIO INT6
+    .long    PININT7_IRQHandler                      // PIO INT7
+    
+    .size    __isr_vector, . - __isr_vector
+
+    .section .text.Reset_Handler
+    .thumb
+    .thumb_func
+    .align 2
+    .globl    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in 
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+    subs    r3, r2
+    ble    .Lflash_to_ram_loop_end
+
+    movs    r4, 0
+.Lflash_to_ram_loop:
+    ldr    r0, [r1,r4]
+    str    r0, [r2,r4]
+    adds    r4, 4
+    cmp    r4, r3
+    blt    .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+    ldr    r0, =SystemInit
+    blx    r0
+    ldr    r0, =_start
+    bx    r0
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+    
+    .text
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_default_handler    handler_name
+    .align 1
+    .thumb_func
+    .weak    \handler_name
+    .type    \handler_name, %function
+\handler_name :
+    b    .
+    .size    \handler_name, . - \handler_name
+    .endm
+
+    def_default_handler     NMI_Handler
+    def_default_handler     HardFault_Handler
+    def_default_handler     SVC_Handler
+    def_default_handler     PendSV_Handler
+    def_default_handler     SysTick_Handler
+    def_default_handler     Default_Handler
+
+    .macro    def_irq_default_handler    handler_name
+    .weak     \handler_name
+    .set      \handler_name, Default_Handler
+    .endm
+
+    def_irq_default_handler    SPI0_IRQHandler
+    def_irq_default_handler    SPI1_IRQHandler
+    def_irq_default_handler    UART0_IRQHandler
+    def_irq_default_handler    UART1_IRQHandler
+    def_irq_default_handler    UART2_IRQHandler
+    def_irq_default_handler    I2C0_IRQHandler
+    def_irq_default_handler    I2C1_IRQHandler
+    def_irq_default_handler    I2C2_IRQHandler
+    def_irq_default_handler    I2C3_IRQHandler
+    def_irq_default_handler    SCT_IRQHandler
+    def_irq_default_handler    MRT_IRQHandler
+    def_irq_default_handler    CMP_IRQHandler
+    def_irq_default_handler    WDT_IRQHandler
+    def_irq_default_handler    BOD_IRQHandler
+    def_irq_default_handler    Flash_IRQHandler
+    def_irq_default_handler    WKT_IRQHandler
+    def_irq_default_handler    ADC_SEQA_IRQHandler
+    def_irq_default_handler    ADC_SEQB_IRQHandler
+    def_irq_default_handler    ADC_THCMP_IRQHandler
+    def_irq_default_handler    ADC_OVR_IRQHandler
+    def_irq_default_handler    DMA_IRQHandler
+    def_irq_default_handler    PININT0_IRQHandler
+    def_irq_default_handler    PININT1_IRQHandler
+    def_irq_default_handler    PININT2_IRQHandler
+    def_irq_default_handler    PININT3_IRQHandler
+    def_irq_default_handler    PININT4_IRQHandler
+    def_irq_default_handler    PININT5_IRQHandler
+    def_irq_default_handler    PININT6_IRQHandler
+    def_irq_default_handler    PININT7_IRQHandler
+
+    .end
+

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c

@@ -209,6 +209,7 @@ void SystemInit(void)
   RCC->CIR = 0x00000000;
 
   /* Configure the Cube driver */
+  SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
   HAL_Init();
 
   /* Configure the System clock source, PLL Multiplier and Divider factors,

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c

@@ -226,6 +226,7 @@ void SystemInit(void)
   RCC->CIR = 0x00000000;
 
   /* Configure the Cube driver */
+  SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
   HAL_Init();
 
   /* Configure the System clock source, PLL Multiplier and Divider factors,

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c

@@ -159,7 +159,7 @@
   uint32_t SystemCoreClock         = 72000000;        /*!< System Clock Frequency (Core Clock) */
 #endif
 
-__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 /**
   * @}
   */

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/system_stm32f1xx.c

@@ -161,7 +161,7 @@
   uint32_t SystemCoreClock         = 72000000;        /*!< System Clock Frequency (Core Clock) */
 #endif
 
-__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 /**
   * @}
   */

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rcc.c

@@ -141,8 +141,8 @@
 
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-static __I uint16_t ADCPrescTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 0, 0, 0, 0 };
+const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint16_t ADCPrescTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 0, 0, 0, 0 };
 
 /* Private function prototypes -----------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/system_stm32f30x.c

@@ -143,7 +143,7 @@
 
 uint32_t SystemCoreClock = 64000000; /* Default with HSI. Will be updated if HSE is used */
 
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 
 /**
   * @}

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.c

@@ -155,7 +155,7 @@
                variable is updated automatically.
   */
   uint32_t SystemCoreClock = 168000000;
-  __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 
 /**
   * @}

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c

@@ -158,7 +158,7 @@
                variable is updated automatically.
   */
 uint32_t SystemCoreClock = 16000000;
-__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 
 /**
   * @}

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c

@@ -163,7 +163,7 @@
                variable is updated automatically.
   */
 uint32_t SystemCoreClock = 16000000;
-__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 
 /**
   * @}

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.c

@@ -27,15 +27,15 @@
   *                                    | 2- PLL_HSE_XTAL        |
   *                                    | (external 8 MHz xtal)  |
   *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 100                    | 100
+  * SYSCLK(MHz)                        | 96                     | 96
   *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 100                    | 100
+  * AHBCLK (MHz)                       | 96                     | 96
   *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 50                     | 50
+  * APB1CLK (MHz)                      | 48                     | 48
   *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 100                    | 100
+  * APB2CLK (MHz)                      | 96                     | 96
   *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | NO                     | NO
+  * USB capable (48 MHz precise clock) | YES                    | YES
   *-----------------------------------------------------------------------------  
   ******************************************************************************
   * @attention
@@ -157,7 +157,7 @@
                variable is updated automatically.
   */
 uint32_t SystemCoreClock = 16000000;
-__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 
 /**
   * @}
@@ -611,11 +611,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
   RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
   //RCC_OscInitStruct.PLL.PLLM          = 8;             // VCO input clock = 1 MHz (8 MHz / 8)
-  //RCC_OscInitStruct.PLL.PLLN          = 400;           // VCO output clock = 400 MHz (1 MHz * 400)
+  //RCC_OscInitStruct.PLL.PLLN          = 384;           // VCO output clock = 384 MHz (1 MHz * 384)
   RCC_OscInitStruct.PLL.PLLM            = 4;             // VCO input clock = 2 MHz (8 MHz / 4)
-  RCC_OscInitStruct.PLL.PLLN            = 200;           // VCO output clock = 400 MHz (2 MHz * 200)
-  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
-  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
+  RCC_OscInitStruct.PLL.PLLN            = 192;           // VCO output clock = 384 MHz (2 MHz * 192)
+  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
+  RCC_OscInitStruct.PLL.PLLQ            = 8;             // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
   {
     return 0; // FAIL
@@ -623,10 +623,10 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
  
   /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
   RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 100 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           //  50 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 100 MHz
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 96 MHz
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 48 MHz
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 96 MHz
   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
   {
     return 0; // FAIL
@@ -665,11 +665,11 @@ uint8_t SetSysClock_PLL_HSI(void)
   RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;   
   //RCC_OscInitStruct.PLL.PLLM          = 16;            // VCO input clock = 1 MHz (16 MHz / 16)
-  //RCC_OscInitStruct.PLL.PLLN          = 400;           // VCO output clock = 400 MHz (1 MHz * 400)
+  //RCC_OscInitStruct.PLL.PLLN          = 384;           // VCO output clock = 384 MHz (1 MHz * 384)
   RCC_OscInitStruct.PLL.PLLM            = 8;             // VCO input clock = 2 MHz (16 MHz / 8)
-  RCC_OscInitStruct.PLL.PLLN            = 200;           // VCO output clock = 400 MHz (2 MHz * 200)
-  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
-  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
+  RCC_OscInitStruct.PLL.PLLN            = 192;           // VCO output clock = 384 MHz (2 MHz * 192)
+  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
+  RCC_OscInitStruct.PLL.PLLQ            = 8;             // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
   {
     return 0; // FAIL
@@ -677,10 +677,10 @@ uint8_t SetSysClock_PLL_HSI(void)
  
   /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
   RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 100 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           //  50 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 100 MHz
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 96 MHz
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 48 MHz
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 96 MHz
   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
   {
     return 0; // FAIL

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c

@@ -157,7 +157,7 @@
                variable is updated automatically.
   */
 uint32_t SystemCoreClock = 16000000;
-__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 
 /**
   * @}

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h

@@ -190,7 +190,7 @@ typedef struct
 
 
 #define DBP_TIMEOUT_VALUE          ((uint32_t)100)
-#define LSE_TIMEOUT_VALUE          ((uint32_t)600)
+#define LSE_TIMEOUT_VALUE          ((uint32_t)5000)
 /**
   * @}
   */

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/system_stm32f4xx.c

@@ -184,7 +184,7 @@
 
   uint32_t SystemCoreClock = 168000000;
 
-  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 
 /**
   * @}

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.c

@@ -145,9 +145,9 @@
                is no need to call the 2 first functions listed above, since SystemCoreClock
                variable is updated automatically.
   */
-  uint32_t SystemCoreClock = 32000000;
-__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-__IO const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+uint32_t SystemCoreClock = 32000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
 
 /**
   * @}

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c

@@ -145,9 +145,9 @@
                is no need to call the 2 first functions listed above, since SystemCoreClock
                variable is updated automatically.
   */
-  uint32_t SystemCoreClock = 32000000;
-__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-__IO const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+uint32_t SystemCoreClock = 32000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
 
 /**
   * @}

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/system_stm32l0xx.c

@@ -145,9 +145,9 @@
                is no need to call the 2 first functions listed above, since SystemCoreClock
                variable is updated automatically.
   */
-  uint32_t SystemCoreClock = 32000000;
-__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-__IO const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+uint32_t SystemCoreClock = 32000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
 
 /**
   * @}

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_conf.h

@@ -123,7 +123,7 @@
 
    
 #if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)500)   /*!< Time out for LSE start up, in ms */
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
 #endif /* HSE_STARTUP_TIMEOUT */
 
    

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c

@@ -118,8 +118,8 @@
 /** @defgroup RCC_Private_Vatiables RCC Private Data
   * @{
   */ 
-static __IO const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
-static __IO const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
 
 /**
   * @}

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/startup_stm32l152xc.s

@@ -0,0 +1,325 @@
+; STM32L152RC Ultra Low Power High-density Devices vector table for MDK ARM_MICRO toolchain
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+                
+Stack_Mem       SPACE   Stack_Size
+__initial_sp    EQU     0x20008000 ; Top of RAM (32 KB)
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000400
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit    EQU (__initial_sp - Stack_Size)
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window Watchdog
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
+                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
+                DCD     FLASH_IRQHandler          ; FLASH
+                DCD     RCC_IRQHandler            ; RCC
+                DCD     EXTI0_IRQHandler          ; EXTI Line 0
+                DCD     EXTI1_IRQHandler          ; EXTI Line 1
+                DCD     EXTI2_IRQHandler          ; EXTI Line 2
+                DCD     EXTI3_IRQHandler          ; EXTI Line 3
+                DCD     EXTI4_IRQHandler          ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler           ; ADC1
+                DCD     USB_HP_IRQHandler         ; USB High Priority
+                DCD     USB_LP_IRQHandler         ; USB Low  Priority
+                DCD     DAC_IRQHandler            ; DAC
+                DCD     COMP_IRQHandler           ; COMP through EXTI Line
+                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
+                DCD     LCD_IRQHandler            ; LCD
+                DCD     TIM9_IRQHandler           ; TIM9
+                DCD     TIM10_IRQHandler          ; TIM10
+                DCD     TIM11_IRQHandler          ; TIM11
+                DCD     TIM2_IRQHandler           ; TIM2
+                DCD     TIM3_IRQHandler           ; TIM3
+                DCD     TIM4_IRQHandler           ; TIM4
+                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+                DCD     SPI1_IRQHandler           ; SPI1
+                DCD     SPI2_IRQHandler           ; SPI2
+                DCD     USART1_IRQHandler         ; USART1
+                DCD     USART2_IRQHandler         ; USART2
+                DCD     USART3_IRQHandler         ; USART3
+                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
+                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
+                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
+                DCD     TIM6_IRQHandler           ; TIM6
+                DCD     TIM7_IRQHandler           ; TIM7
+                DCD     0                         ; Reserved
+                DCD     TIM5_IRQHandler           ; TIM5
+                DCD     SPI3_IRQHandler           ; SPI3
+                DCD     UART4_IRQHandler          ; UART4
+                DCD     UART5_IRQHandler          ; UART5
+                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
+                DCD     0                         ; Reserved
+                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
+                
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_IRQHandler            [WEAK]
+                EXPORT  USB_HP_IRQHandler          [WEAK]
+                EXPORT  USB_LP_IRQHandler          [WEAK]
+                EXPORT  DAC_IRQHandler             [WEAK]
+                EXPORT  COMP_IRQHandler            [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  LCD_IRQHandler             [WEAK]
+                EXPORT  TIM9_IRQHandler            [WEAK]
+                EXPORT  TIM10_IRQHandler           [WEAK]
+                EXPORT  TIM11_IRQHandler           [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  USART3_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
+                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
+                EXPORT  TIM6_IRQHandler            [WEAK]
+                EXPORT  TIM7_IRQHandler            [WEAK]
+                EXPORT  TIM5_IRQHandler            [WEAK]                                
+                EXPORT  SPI3_IRQHandler            [WEAK]
+                EXPORT  UART4_IRQHandler           [WEAK]
+                EXPORT  UART5_IRQHandler           [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
+                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+DAC_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+LCD_IRQHandler
+TIM9_IRQHandler
+TIM10_IRQHandler
+TIM11_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+USB_FS_WKUP_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+COMP_ACQ_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/stm32l152rc.sct

@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32L152RC: 256KB FLASH + 32KB SRAM
+LR_IROM1 0x08000000 0x40000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x40000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x124) (0x8000-0x124)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+
+}
+

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/sys.cpp

@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model, 
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/startup_stm32l152xc.s

@@ -0,0 +1,298 @@
+; STM32L152RC Ultra Low Power High-density Devices vector table for MDK ARM_STD toolchain
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+__initial_sp    EQU     0x20008000 ; Top of RAM (32 KB)
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window Watchdog
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
+                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
+                DCD     FLASH_IRQHandler          ; FLASH
+                DCD     RCC_IRQHandler            ; RCC
+                DCD     EXTI0_IRQHandler          ; EXTI Line 0
+                DCD     EXTI1_IRQHandler          ; EXTI Line 1
+                DCD     EXTI2_IRQHandler          ; EXTI Line 2
+                DCD     EXTI3_IRQHandler          ; EXTI Line 3
+                DCD     EXTI4_IRQHandler          ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler           ; ADC1
+                DCD     USB_HP_IRQHandler         ; USB High Priority
+                DCD     USB_LP_IRQHandler         ; USB Low  Priority
+                DCD     DAC_IRQHandler            ; DAC
+                DCD     COMP_IRQHandler           ; COMP through EXTI Line
+                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
+                DCD     LCD_IRQHandler            ; LCD
+                DCD     TIM9_IRQHandler           ; TIM9
+                DCD     TIM10_IRQHandler          ; TIM10
+                DCD     TIM11_IRQHandler          ; TIM11
+                DCD     TIM2_IRQHandler           ; TIM2
+                DCD     TIM3_IRQHandler           ; TIM3
+                DCD     TIM4_IRQHandler           ; TIM4
+                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+                DCD     SPI1_IRQHandler           ; SPI1
+                DCD     SPI2_IRQHandler           ; SPI2
+                DCD     USART1_IRQHandler         ; USART1
+                DCD     USART2_IRQHandler         ; USART2
+                DCD     USART3_IRQHandler         ; USART3
+                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
+                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
+                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
+                DCD     TIM6_IRQHandler           ; TIM6
+                DCD     TIM7_IRQHandler           ; TIM7
+                DCD     0                         ; Reserved
+                DCD     TIM5_IRQHandler           ; TIM5
+                DCD     SPI3_IRQHandler           ; SPI3
+                DCD     UART4_IRQHandler          ; UART4
+                DCD     UART5_IRQHandler          ; UART5
+                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
+                DCD     0                         ; Reserved
+                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
+                
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_IRQHandler            [WEAK]
+                EXPORT  USB_HP_IRQHandler          [WEAK]
+                EXPORT  USB_LP_IRQHandler          [WEAK]
+                EXPORT  DAC_IRQHandler             [WEAK]
+                EXPORT  COMP_IRQHandler            [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  LCD_IRQHandler             [WEAK]
+                EXPORT  TIM9_IRQHandler            [WEAK]
+                EXPORT  TIM10_IRQHandler           [WEAK]
+                EXPORT  TIM11_IRQHandler           [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  USART3_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
+                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
+                EXPORT  TIM6_IRQHandler            [WEAK]
+                EXPORT  TIM7_IRQHandler            [WEAK]
+                EXPORT  TIM5_IRQHandler            [WEAK]                                
+                EXPORT  SPI3_IRQHandler            [WEAK]
+                EXPORT  UART4_IRQHandler           [WEAK]
+                EXPORT  UART5_IRQHandler           [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
+                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+DAC_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+LCD_IRQHandler
+TIM9_IRQHandler
+TIM10_IRQHandler
+TIM11_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+USB_FS_WKUP_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+COMP_ACQ_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/stm32l152rc.sct

@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32L152RC: 256KB FLASH + 32KB SRAM
+LR_IROM1 0x08000000 0x40000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x40000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x124) (0x8000-0x124)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+
+}
+

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/sys.cpp

@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model, 
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/STM32L152XC.ld

@@ -0,0 +1,156 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  /* 256KB FLASH, 32KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292
+   * bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138
+   */
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256k
+  RAM (rwx) : ORIGIN = 0x2000013C, LENGTH = 0x8000-0x13C
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+    _sidata = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        _sdata = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+        _edata = .;
+
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        _sbss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+        _ebss = .;
+    } > RAM
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/startup_stm32l152xc.s

@@ -0,0 +1,421 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l152xc.s
+  * @author    MCD Application Team
+  * @version   V2.0.0
+  * @date      5-September-2014
+  * @brief     STM32L152XC Devices vector table for 
+  *            Atollic toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ  BootRAM, 0xF108F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r3, =_sidata
+  ldr r3, [r3, r1]
+  str r3, [r0, r1]
+  adds r1, r1, #4
+
+LoopCopyDataInit:
+  ldr r0, =_sdata
+  ldr r3, =_edata
+  adds r2, r0, r1
+  cmp r2, r3
+  bcc CopyDataInit
+  ldr r2, =_sbss
+  b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs r3, #0
+  str r3, [r2], #4
+
+LoopFillZerobss:
+  ldr r3, = _ebss
+  cmp r2, r3
+  bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+    bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl main
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_IRQHandler
+  .word TAMPER_STAMP_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word DAC_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word LCD_IRQHandler  
+  .word TIM9_IRQHandler
+  .word TIM10_IRQHandler
+  .word TIM11_IRQHandler
+  .word TIM2_IRQHandler
+  .word TIM3_IRQHandler
+  .word TIM4_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C2_EV_IRQHandler
+  .word I2C2_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word USART2_IRQHandler
+  .word USART3_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word USB_FS_WKUP_IRQHandler
+  .word TIM6_IRQHandler
+  .word TIM7_IRQHandler
+  .word 0
+  .word TIM5_IRQHandler
+  .word SPI3_IRQHandler
+  .word 0
+  .word 0
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word 0
+  .word COMP_ACQ_IRQHandler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
+                            STM32L152XE devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak TAMPER_STAMP_IRQHandler
+  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+  .weak RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak DAC_IRQHandler
+  .thumb_set DAC_IRQHandler,Default_Handler
+
+  .weak COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak LCD_IRQHandler
+  .thumb_set LCD_IRQHandler,Default_Handler  
+
+  .weak TIM9_IRQHandler
+  .thumb_set TIM9_IRQHandler,Default_Handler
+
+  .weak TIM10_IRQHandler
+  .thumb_set TIM10_IRQHandler,Default_Handler
+
+  .weak TIM11_IRQHandler
+  .thumb_set TIM11_IRQHandler,Default_Handler
+
+  .weak TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak TIM4_IRQHandler
+  .thumb_set TIM4_IRQHandler,Default_Handler
+
+  .weak I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak USB_FS_WKUP_IRQHandler
+  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
+
+  .weak TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+
+  .weak TIM7_IRQHandler
+  .thumb_set TIM7_IRQHandler,Default_Handler
+
+  .weak TIM5_IRQHandler
+  .thumb_set TIM5_IRQHandler,Default_Handler
+  
+  .weak SPI3_IRQHandler
+  .thumb_set SPI3_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak COMP_ACQ_IRQHandler
+   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/startup_stm32l152xc.s

@@ -0,0 +1,536 @@
+;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name          : startup_stm32l152xc.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0
+;* Date               : 5-September-2014
+;* Description        : STM32L152XC Devices vector for EWARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == __iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      - Configure the system clock
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit        
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler           ; Window Watchdog
+        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
+        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
+        DCD     FLASH_IRQHandler          ; FLASH
+        DCD     RCC_IRQHandler            ; RCC
+        DCD     EXTI0_IRQHandler          ; EXTI Line 0
+        DCD     EXTI1_IRQHandler          ; EXTI Line 1
+        DCD     EXTI2_IRQHandler          ; EXTI Line 2
+        DCD     EXTI3_IRQHandler          ; EXTI Line 3
+        DCD     EXTI4_IRQHandler          ; EXTI Line 4
+        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
+        DCD     ADC1_IRQHandler           ; ADC1
+        DCD     USB_HP_IRQHandler         ; USB High Priority
+        DCD     USB_LP_IRQHandler         ; USB Low  Priority
+        DCD     DAC_IRQHandler            ; DAC
+        DCD     COMP_IRQHandler           ; COMP through EXTI Line
+        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
+        DCD     LCD_IRQHandler            ; LCD
+        DCD     TIM9_IRQHandler           ; TIM9
+        DCD     TIM10_IRQHandler          ; TIM10
+        DCD     TIM11_IRQHandler          ; TIM11
+        DCD     TIM2_IRQHandler           ; TIM2
+        DCD     TIM3_IRQHandler           ; TIM3
+        DCD     TIM4_IRQHandler           ; TIM4
+        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+        DCD     SPI1_IRQHandler           ; SPI1
+        DCD     SPI2_IRQHandler           ; SPI2
+        DCD     USART1_IRQHandler         ; USART1
+        DCD     USART2_IRQHandler         ; USART2
+        DCD     USART3_IRQHandler         ; USART3
+        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
+        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
+        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
+        DCD     TIM6_IRQHandler           ; TIM6
+        DCD     TIM7_IRQHandler           ; TIM7
+        DCD     0                         ; Reserved
+        DCD     TIM5_IRQHandler           ; TIM5
+        DCD     SPI3_IRQHandler           ; SPI3
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
+        DCD     0                         ; Reserved
+        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+        
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B NMI_Handler
+        
+        
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B HardFault_Handler
+        
+        
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B MemManage_Handler
+        
+                
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B BusFault_Handler
+        
+        
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B UsageFault_Handler
+        
+        
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B SVC_Handler
+        
+        
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B DebugMon_Handler
+        
+        
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B PendSV_Handler
+        
+        
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B SysTick_Handler
+        
+        
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+        
+        
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PVD_IRQHandler
+        B PVD_IRQHandler
+        
+        
+        PUBWEAK TAMPER_STAMP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TAMPER_STAMP_IRQHandler
+        B TAMPER_STAMP_IRQHandler
+        
+        
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+        
+        
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+        
+        
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+        
+        
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+        
+        
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+        
+        
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+        
+        
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+        
+        
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+        
+        
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+        
+        
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+        
+        
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+        
+        
+        PUBWEAK DAC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DAC_IRQHandler
+        B DAC_IRQHandler
+        
+        
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+        
+        
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+        
+        
+        PUBWEAK LCD_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+LCD_IRQHandler
+        B LCD_IRQHandler
+        
+        
+        PUBWEAK TIM9_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM9_IRQHandler
+        B TIM9_IRQHandler
+        
+        
+        PUBWEAK TIM10_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM10_IRQHandler
+        B TIM10_IRQHandler
+        
+        
+        PUBWEAK TIM11_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM11_IRQHandler
+        B TIM11_IRQHandler
+        
+        
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+        
+        
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+        
+        
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+        
+        
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+        
+        
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+        
+        
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+        
+        
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+        
+        
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+        
+        
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+        
+        
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+        
+        
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+        
+        
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+        
+        
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+        
+        
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+        
+        
+        PUBWEAK USB_FS_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USB_FS_WKUP_IRQHandler
+        B USB_FS_WKUP_IRQHandler
+        
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+        
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+
+        PUBWEAK COMP_ACQ_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+COMP_ACQ_IRQHandler
+        B COMP_ACQ_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/stm32l152xc.icf

@@ -0,0 +1,30 @@
+/* [ROM = 256kb = 0x40000] */
+define symbol __intvec_start__     = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__   = 0x0803FFFF;
+
+/* [RAM = 32kb = 0x8000] Vector table dynamic copy: 73 vectors = 292 bytes (0x124) to be reserved in RAM */
+define symbol __NVIC_start__          = 0x20000000;
+define symbol __NVIC_end__            = 0x20000127; /* Add 4 more bytes to be aligned on 8 bytes */
+define symbol __region_RAM_start__    = 0x20000128;
+define symbol __region_RAM_end__      = 0x20007FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x800;
+define symbol __size_heap__   = 0x800;
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, block STACKHEAP };

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis.h

@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32l1xx.h"
+#include "cmsis_nvic.h"
+
+#endif

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis_nvic.c

@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */ 
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000)  // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    uint32_t *vectors = (uint32_t *)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis_nvic.h

@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */ 
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32L152RC
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 57 vectors = 228 bytes from 0x40 to 0x123
+// Total: 73 vectors = 292 bytes (0x124) to be reserved in RAM
+#define NVIC_NUM_VECTORS      73
+#define NVIC_USER_IRQ_OFFSET  16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/hal_tick.c

@@ -0,0 +1,121 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.c
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#include "hal_tick.h"
+
+TIM_HandleTypeDef TimMasterHandle;
+uint32_t PreviousVal = 0;
+
+void us_ticker_irq_handler(void);
+
+void timer_irq_handler(void) {
+    // Channel 1 for mbed timeout
+    if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
+        us_ticker_irq_handler();
+    }
+
+    // Channel 2 for HAL tick
+    if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
+        __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
+        uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+        if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+            // Increment HAL variable
+            HAL_IncTick();
+            // Prepare next interrupt
+            __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+            PreviousVal = val;
+#if 0 // For DEBUG only
+            HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
+#endif
+        }
+    }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+    // Enable timer clock
+    TIM_MST_RCC;
+
+    // Reset timer
+    TIM_MST_RESET_ON;
+    TIM_MST_RESET_OFF;
+
+    // Update the SystemCoreClock variable
+    SystemCoreClockUpdate();
+
+    // Configure time base
+    TimMasterHandle.Instance = TIM_MST;
+    TimMasterHandle.Init.Period            = 0xFFFFFFFF;
+    TimMasterHandle.Init.Prescaler         = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
+    TimMasterHandle.Init.ClockDivision     = 0;
+    TimMasterHandle.Init.CounterMode       = TIM_COUNTERMODE_UP;
+    HAL_TIM_OC_Init(&TimMasterHandle);
+
+    NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+    NVIC_EnableIRQ(TIM_MST_IRQ);
+
+    // Channel 1 for mbed timeout
+    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+    // Channel 2 for HAL tick
+    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+    PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+    __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+
+#if 0 // For DEBUG only
+    __GPIOB_CLK_ENABLE();
+    GPIO_InitTypeDef GPIO_InitStruct;
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#endif
+
+    return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/hal_tick.h

@@ -0,0 +1,60 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.h
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32l1xx.h"
+#include "cmsis_nvic.h"
+   
+#define TIM_MST      TIM5
+#define TIM_MST_IRQ  TIM5_IRQn
+#define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l1xx.h

@@ -0,0 +1,247 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx.h
+  * @author  MCD Application Team
+  * @version V2.0.0
+  * @date    5-September-2014
+  * @brief   CMSIS STM32L1xx Device Peripheral Access Layer Header File. 
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *            - Configuration section that allows to select:
+  *              - The STM32L1xx device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral’s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l1xx
+  * @{
+  */
+    
+#ifndef __STM32L1XX_H
+#define __STM32L1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/* Uncomment the line below according to the target STM32L device used in your 
+   application 
+  */
+
+#if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \
+    !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xE) && \
+    !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xE) && \
+    !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xE)
+  /* #define STM32L100xB  */   /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */
+  /* #define STM32L100xBA */   /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */
+  /* #define STM32L100xC  */   /*!< STM32L100RC Devices */
+  /* #define STM32L151xB  */   /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */
+  /* #define STM32L151xBA */   /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */ 
+  /* #define STM32L151xC  */   /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */
+  /* #define STM32L151xCA */   /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */
+  /* #define STM32L151xD  */   /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */
+  /* #define STM32L151xE  */   /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */
+  /* #define STM32L152xB  */   /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */
+  /* #define STM32L152xBA */   /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */
+#define STM32L152xC    /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */
+  /* #define STM32L152xCA */   /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */
+  /* #define STM32L152xD  */   /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */  
+  /* #define STM32L152xE  */   /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */
+  /* #define STM32L162xC  */   /*!< STM32L162RC and STM32L162VC */
+  /* #define STM32L162xCA */   /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */
+  /* #define STM32L162xD  */   /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */
+  /* #define STM32L162xE  */   /*!< STM32L162RE, STM32L162VE and STM32L162ZE */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+  
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V2.0.0
+  */
+#define __STM32L1xx_CMSIS_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
+#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
+#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32L1xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32L1xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32L100xB)
+  #include "stm32l100xb.h"
+#elif defined(STM32L100xBA)
+  #include "stm32l100xba.h"
+#elif defined(STM32L100xC)
+  #include "stm32l100xc.h"
+#elif defined(STM32L151xB)
+  #include "stm32l151xb.h"
+#elif defined(STM32L151xBA)
+  #include "stm32l151xba.h"
+#elif defined(STM32L151xC)
+  #include "stm32l151xc.h"
+#elif defined(STM32L151xCA)
+  #include "stm32l151xca.h"
+#elif defined(STM32L151xD)
+  #include "stm32l151xd.h"
+#elif defined(STM32L151xE)
+  #include "stm32l151xe.h"
+#elif defined(STM32L152xB)
+  #include "stm32l152xb.h"
+#elif defined(STM32L152xBA)
+  #include "stm32l152xba.h"
+#elif defined(STM32L152xC)
+  #include "stm32l152xc.h"
+#elif defined(STM32L152xCA)
+  #include "stm32l152xca.h"
+#elif defined(STM32L152xD)
+  #include "stm32l152xd.h"
+#elif defined(STM32L152xE)
+  #include "stm32l152xe.h"
+#elif defined(STM32L162xC)
+  #include "stm32l162xc.h"
+#elif defined(STM32L162xCA)
+  #include "stm32l162xca.h"
+#elif defined(STM32L162xD)
+  #include "stm32l162xd.h"
+#elif defined(STM32L162xE)
+  #include "stm32l162xe.h"
+#else
+ #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */  
+typedef enum 
+{
+  RESET = 0, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum 
+{
+  DISABLE = 0, 
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum 
+{
+  ERROR = 0, 
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32l1xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L1xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c

@@ -0,0 +1,607 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l1xx.c
+  * @author  MCD Application Team
+  * @version V2.0.0
+  * @date    5-September-2014
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l1xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 16 MHz)
+  *                                    | 2- PLL_HSE_XTAL        |
+  *                                    | (external 8 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 24                     | 32
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 24                     | 32
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 24                     | 32
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 24                     | 32
+  *-----------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | YES                    | NO
+  *-----------------------------------------------------------------------------
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l1xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32L1xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l1xx.h"
+#include "hal_tick.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Defines
+  * @{
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Default value of the Internal oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM32L152D_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+  
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Macros
+  * @{
+  */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (0) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */
+const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /*!< Set MSION bit */
+  RCC->CR |= (uint32_t)0x00000100;
+
+  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+  RCC->CFGR &= (uint32_t)0x88FFC00C;
+  
+  /*!< Reset HSION, HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xEEFEFFFE;
+
+  /*!< Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+  RCC->CFGR &= (uint32_t)0xFF02FFFF;
+
+  /*!< Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+    
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+
+  /* Configure the Cube driver */
+  SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
+  HAL_Init();
+
+  /* Configure the System clock source, PLL Multiplier and Divider factors,
+     AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+  
+  /* Reset the timer to avoid issues after the RAM initialization */
+  TIM_MST_RESET_ON;
+  TIM_MST_RESET_OFF;
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
+  *             value as defined by the MSI range.
+  *                                   
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+    case 0x04:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x08:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x0C:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+      pllmul = PLLMulTable[(pllmul >> 18)];
+      plldiv = (plldiv >> 22) + 1;
+      
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock selected as PLL clock entry */
+        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+      }
+      else
+      {
+        /* HSE selected as PLL clock entry */
+        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+      }
+      break;
+    default: /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in SystemInit() function before jump to main.
+  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                   +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
+ | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
+ | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
+ | PD15 <-> FSMC_D1  |--------------------+ 
+ +-------------------+
+*/
+
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHBENR   = 0x000080D8;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CC00CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A0A;
+  /* Configure PDx pins speed to 40 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0F0F;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 40 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC00F;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 40 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x00000C00;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00200AAA;
+  /* Configure PGx pins speed to 40 MHz */ 
+  GPIOG->OSPEEDR = 0x00300FFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHBENR    = 0x400080D8;
+
+  /* Configure and enable Bank1_SRAM3 */
+  FSMC_Bank1->BTCR[4]  = 0x00001011;
+  FSMC_Bank1->BTCR[5]  = 0x00000300;
+  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
+/*
+  Bank1_SRAM3 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 3;
+  p.FSMC_BusTurnAroundDuration = 0;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
+
+  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+  /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+  if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+  {
+    /* 2- If fail try to start with HSE and external xtal */
+    #if USE_PLL_HSE_XTAL != 0
+    if (SetSysClock_PLL_HSE(0) == 0)
+    #endif
+    {
+      /* 3- If fail start with HSI clock */
+      if (SetSysClock_PLL_HSI() == 0)
+      {
+        while(1)
+        {
+          // [TODO] Put something here to tell the user that a problem occured...
+        }
+      }
+    }
+  }
+  
+  /* Output clock on MCO1 pin(PA8) for debugging purpose */
+  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
+    return 1;   // already on HSE PLL, could occur from deepsleep waking
+
+  /* Used to gain time after DeepSleep in case HSI is used */
+  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+  {
+    return 0;
+  }
+  
+  /* The voltage scaling allows optimizing the power consumption when the device is 
+     clocked below the maximum system frequency, to update the voltage scaling value 
+     regarding system frequency refer to product datasheet. */
+  __PWR_CLK_ENABLE();
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  
+  /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+  if (bypass == 0)
+  {
+    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+  }
+  else
+  {
+    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+  }
+  RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
+  // SYSCLK = 24 MHz ((8 MHz * 6) / 2)
+  // USBCLK = 48 MHz (8 MHz * 6) --> USB OK
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6;
+  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+ 
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 24 MHz
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+
+  /* Output clock on MCO1 pin(PA8) for debugging purpose */
+  //if (bypass == 0)
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+  //else
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+  
+  return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  /* The voltage scaling allows optimizing the power consumption when the device is 
+     clocked below the maximum system frequency, to update the voltage scaling value 
+     regarding system frequency refer to product datasheet. */
+  __PWR_CLK_ENABLE();
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  
+  /* Enable HSI oscillator and activate PLL with HSI as source */
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+  // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
+  // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
+  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+  
+  /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
+  while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+
+  /* Output clock on MCO1 pin(PA8) for debugging purpose */
+  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+  
+  return 1; // OK
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.h

@@ -0,0 +1,123 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l1xx.h
+  * @author  MCD Application Team
+  * @version V2.0.0
+  * @date    5-September-2014
+  * @brief   CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l1xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32L1XX_H
+#define __SYSTEM_STM32L1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32L1xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32L1xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32L1XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_conf.h

@@ -122,7 +122,7 @@
 
    
 #if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)500)   /*!< Time out for LSE start up, in ms */
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
 #endif /* HSE_STARTUP_TIMEOUT */