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STM32F4 warning compilation 

[-Wparentheses-equality]
pull/10793/head
jeromecoutant 2019-06-07 17:17:02 +02:00
parent 89f554fb53
commit 09a58b5203
5 changed files with 24 additions and 24 deletions
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2
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.c
View File

@ -1369,7 +1369,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
/* Enable the TSVREFE channel*/ /* Enable the TSVREFE channel*/
tmpADC_Common->CCR |= ADC_CCR_TSVREFE; tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
{ {
/* Delay for temperature sensor stabilization time */ /* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */ /* Compute number of CPU cycles to wait for */

4
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.c
View File

@ -1290,11 +1290,11 @@ static uint8_t FLASH_OB_GetRDP(void)
{ {
uint8_t readstatus = OB_RDP_LEVEL_0; uint8_t readstatus = OB_RDP_LEVEL_0;
if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2)) if(*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2)
{ {
readstatus = OB_RDP_LEVEL_2; readstatus = OB_RDP_LEVEL_2;
} }
else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_1)) else if(*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_1)
{ {
readstatus = OB_RDP_LEVEL_1; readstatus = OB_RDP_LEVEL_1;
} }

2
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.c
View File

@ -344,7 +344,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
{ {
/* MBED */ /* MBED */
if ((hhcd->hc[ch_num].ep_is_in != direction)) { if ((hhcd->hc[ch_num].ep_is_in != direction)) {
if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)){ if (hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL){
/* reconfigure the endpoint !!! from tx -> rx, and rx ->tx */ /* reconfigure the endpoint !!! from tx -> rx, and rx ->tx */
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
if (direction) if (direction)

28
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.c
View File

@ -396,11 +396,11 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if((pData == 0U) && (Length > 0)) if((pData == 0U) && (Length > 0))
{ {
@ -795,11 +795,11 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if(((uint32_t)pData == 0U) && (Length > 0)) if(((uint32_t)pData == 0U) && (Length > 0))
{ {
@ -1310,11 +1310,11 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if(((uint32_t)pData == 0U) && (Length > 0)) if(((uint32_t)pData == 0U) && (Length > 0))
{ {
@ -1798,11 +1798,11 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if((pData == 0U) && (Length > 0)) if((pData == 0U) && (Length > 0))
{ {
@ -2630,11 +2630,11 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0)) if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0))
{ {
@ -3383,11 +3383,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_LENGTH(BurstLength));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if((BurstBuffer == 0U) && (BurstLength > 0U)) if((BurstBuffer == 0U) && (BurstLength > 0U))
{ {
@ -3608,11 +3608,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_LENGTH(BurstLength));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if((BurstBuffer == 0U) && (BurstLength > 0U)) if((BurstBuffer == 0U) && (BurstLength > 0U))
{ {

12
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.c
View File

@ -386,11 +386,11 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if(((uint32_t)pData == 0U) && (Length > 0)) if(((uint32_t)pData == 0U) && (Length > 0))
{ {
@ -688,11 +688,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if(((uint32_t)pData == 0U) && (Length > 0)) if(((uint32_t)pData == 0U) && (Length > 0))
{ {
@ -1100,11 +1100,11 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if(((uint32_t)pData == 0U) && (Length > 0)) if(((uint32_t)pData == 0U) && (Length > 0))
{ {