From 09a58b5203c9d39adb9b0867cf1d80ab4ee8e874 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Fri, 7 Jun 2019 17:17:02 +0200 Subject: [PATCH] STM32F4 warning compilation [-Wparentheses-equality] --- .../TARGET_STM32F4/device/stm32f4xx_hal_adc.c | 2 +- .../device/stm32f4xx_hal_flash_ex.c | 4 +-- .../TARGET_STM32F4/device/stm32f4xx_hal_hcd.c | 2 +- .../TARGET_STM32F4/device/stm32f4xx_hal_tim.c | 28 +++++++++---------- .../device/stm32f4xx_hal_tim_ex.c | 12 ++++---- 5 files changed, 24 insertions(+), 24 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.c index d67cff8e59..5cffa256b0 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.c @@ -1369,7 +1369,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Enable the TSVREFE channel*/ tmpADC_Common->CCR |= ADC_CCR_TSVREFE; - if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) + if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.c index 7b5eff6949..629f0562f3 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.c @@ -1290,11 +1290,11 @@ static uint8_t FLASH_OB_GetRDP(void) { uint8_t readstatus = OB_RDP_LEVEL_0; - if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2)) + if(*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2) { readstatus = OB_RDP_LEVEL_2; } - else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_1)) + else if(*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_1) { readstatus = OB_RDP_LEVEL_1; } diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.c index d28654ea6a..9b4958f523 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.c @@ -344,7 +344,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, { /* MBED */ if ((hhcd->hc[ch_num].ep_is_in != direction)) { - if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)){ + if (hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL){ /* reconfigure the endpoint !!! from tx -> rx, and rx ->tx */ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; if (direction) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.c index 89db4b6165..c43d24a1ab 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.c @@ -396,11 +396,11 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if(htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if(htim->State == HAL_TIM_STATE_READY) { if((pData == 0U) && (Length > 0)) { @@ -795,11 +795,11 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if(htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if(htim->State == HAL_TIM_STATE_READY) { if(((uint32_t)pData == 0U) && (Length > 0)) { @@ -1310,11 +1310,11 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if(htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if(htim->State == HAL_TIM_STATE_READY) { if(((uint32_t)pData == 0U) && (Length > 0)) { @@ -1798,11 +1798,11 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if(htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if(htim->State == HAL_TIM_STATE_READY) { if((pData == 0U) && (Length > 0)) { @@ -2630,11 +2630,11 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Check the parameters */ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if(htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if(htim->State == HAL_TIM_STATE_READY) { if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0)) { @@ -3383,11 +3383,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if(htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if(htim->State == HAL_TIM_STATE_READY) { if((BurstBuffer == 0U) && (BurstLength > 0U)) { @@ -3608,11 +3608,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if(htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if(htim->State == HAL_TIM_STATE_READY) { if((BurstBuffer == 0U) && (BurstLength > 0U)) { diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.c index a77b21ded0..781e5a7fcf 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.c @@ -386,11 +386,11 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /* Check the parameters */ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if(htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if(htim->State == HAL_TIM_STATE_READY) { if(((uint32_t)pData == 0U) && (Length > 0)) { @@ -688,11 +688,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if(htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if(htim->State == HAL_TIM_STATE_READY) { if(((uint32_t)pData == 0U) && (Length > 0)) { @@ -1100,11 +1100,11 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if(htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if(htim->State == HAL_TIM_STATE_READY) { if(((uint32_t)pData == 0U) && (Length > 0)) {