mirror of https://github.com/ARMmbed/mbed-os.git
Merge remote-tracking branch 'refs/remotes/mbedmicro/master' into dev_xxxx_xxx
dbestm
commit
07f52ee8bf
|
|
@ -68,6 +68,7 @@ STMicroelectronics:
|
|||
* [Nucleo-F334R8](https://developer.mbed.org/platforms/ST-Nucleo-F334R8/) (Cortex-M4F)
|
||||
* [Nucleo-F401RE](https://developer.mbed.org/platforms/ST-Nucleo-F401RE/) (Cortex-M4F)
|
||||
* [Nucleo-F411RE](https://developer.mbed.org/platforms/ST-Nucleo-F411RE/) (Cortex-M4F)
|
||||
* [Nucleo-L476RG](https://developer.mbed.org/platforms/ST-Nucleo-L476RG/) (Cortex-M4F)
|
||||
* STM32F4XX (Cortex-M4F)
|
||||
* STM32F3XX (Cortex-M4F)
|
||||
* STM32F0-Discovery (Cortex-M0)
|
||||
|
|
@ -76,6 +77,7 @@ STMicroelectronics:
|
|||
* STM32F4-Discovery (Cortex-M4F)
|
||||
* STM32F429-Discovery (Cortex-M4F)
|
||||
* STM32L0-Discovery (Cortex-M0+)
|
||||
* [STM32L4-Discovery](https://developer.mbed.org/platforms/ST-Discovery-L476VG/) (Cortex-M4F)
|
||||
* [Arch Max](https://developer.mbed.org/platforms/Seeed-Arch-Max/) (Cortex-M4F)
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -136,10 +136,10 @@ LICENSE MANIFEST.in README.md libraries setup.py travis workspace_tools
|
|||
Directory structure we are interested in:
|
||||
```
|
||||
mbed/workspace_tools/ - test suite scripts, build scripts etc.
|
||||
mbed/library/tests/ - mbed SDK tests,
|
||||
mbed/library/tests/mbed/ - tests for mbed SDK and peripherals tests,
|
||||
mbed/library/tests/net/echo/ - tests for Ethernet interface,
|
||||
mbed/library/tests/rtos/mbed/ - tests for RTOS.
|
||||
mbed/libraries/tests/ - mbed SDK tests,
|
||||
mbed/libraries/tests/mbed/ - tests for mbed SDK and peripherals tests,
|
||||
mbed/libraries/tests/net/echo/ - tests for Ethernet interface,
|
||||
mbed/libraries/tests/rtos/mbed/ - tests for RTOS.
|
||||
```
|
||||
|
||||
### Workspace tools
|
||||
|
|
@ -334,7 +334,7 @@ Build successes:
|
|||
|
||||
* If you’re unsure which platforms and toolchains are supported please use switch ```-S``` to print simple matrix of platform to compiler dependencies.
|
||||
```
|
||||
$ python python build.py -S
|
||||
$ python build.py -S
|
||||
+-------------------------+-----------+-----------+-----------+-----------+-----------+-----------+------------+---------------+
|
||||
| Platform | ARM | uARM | GCC_ARM | IAR | GCC_CR | GCC_CS | GCC_CW_EWL | GCC_CW_NEWLIB |
|
||||
+-------------------------+-----------+-----------+-----------+-----------+-----------+-----------+------------+---------------+
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ Each test is supervised by python script called “host test” which will at le
|
|||
## What is host test?
|
||||
Test suite supports test supervisor concept. This concept is realized by separate Python script called ```host test```. Host tests can be found in ```mbed/workspace_tools/host_tests/``` directory. Note: In newer mbed versions (mbed OS) host tests will be separate library.
|
||||
|
||||
Host test script is executed in parallel with test runner to monitor test execution. Basic host test just monitors device's default serial port for test results returned by test runner. Simple tests will print test result on serial port. In other cases host tests can for example judge by test results returned by test runner is test passed or failed. It all depends on test itself.
|
||||
Host test script is executed in parallel with test runner to monitor test execution. Basic host test just monitors device's default serial port for test results returned by test runner. Simple tests will print test result on serial port. In other cases host tests can for example judge by test results returned by test runner if test passed or failed. It all depends on test itself.
|
||||
|
||||
In some cases host test can be TCP server echoing packets from test runner and judging packet loss. In other cases it can just check if values returned from accelerometer are actually valid (sane).
|
||||
|
||||
|
|
@ -37,7 +37,7 @@ After connecting boards to our host machine (PC) we can check which serial ports
|
|||
* ```NUCLEO_F103RB``` serial port is on ```COM11``` and disk drive is ```I:```.
|
||||
If you are working under Linux your port and disk could look like /dev/ttyACM5 and /media/usb5.
|
||||
|
||||
This information is needed to create ```muts_all.json``` configuration file. You can create in in ```mbed/workspace_tools/``` directory:
|
||||
This information is needed to create ```muts_all.json``` configuration file. You can create it in ```mbed/workspace_tools/``` directory:
|
||||
```
|
||||
$ touch muts_all.json
|
||||
```
|
||||
|
|
@ -289,13 +289,13 @@ $ python singletest.py -R -f RTOS
|
|||
```
|
||||
|
||||
* Shuffle your tests. We strongly encourage you to shuffle your test order each time you execute test suite script.
|
||||
Rationale: It is probable that tests executed in one particular order will pass and in other will fail. To shuffle your tests’ order please use option ```–u``` (or ```--shuffle```):
|
||||
Rationale: It is probable that tests executed in one particular order will pass and in other will fail. To shuffle your tests’ order please use option ```-u``` (or ```--shuffle```):
|
||||
```
|
||||
$ python singletest.py -i test_spec.json -M muts_all.json --shuffle
|
||||
```
|
||||
Above command with force test script to randomly generate shuffle seed and shuffle test order execution. Note: Shuffle seed is float in ```[0.0, 1.0)```.
|
||||
Above command will force test script to randomly generate shuffle seed and shuffle test order execution. Note: Shuffle seed is float in ```[0.0, 1.0)```.
|
||||
|
||||
You can always recreate particular test order by forcing shuffle (```-u``` or ```--shuffle```} switch) and passing shuffle seed back to test suite using ```--shuffle-seed``` switch:
|
||||
You can always recreate particular test order by forcing shuffle (```-u``` or ```--shuffle``` switch) and passing shuffle seed back to test suite using ```--shuffle-seed``` switch:
|
||||
```
|
||||
$ python singletest.py -i test_spec.json -M muts_all.json --shuffle --shuffle-seed 0.4041028336
|
||||
```
|
||||
|
|
@ -311,7 +311,7 @@ Shuffle Seed: 0.4041028336
|
|||
Completed in 234.85 sec
|
||||
```
|
||||
|
||||
### Exmple of device configuration (one device connected to host computer)
|
||||
### Example of device configuration (one device connected to host computer)
|
||||
|
||||
This example will show you how to configure single device, run general tests or only peripheral tests. We will also show some real test result examples.
|
||||
|
||||
|
|
@ -597,7 +597,7 @@ Note: In dependency section we've added library ```CPPUTEST_LIBRARY``` which is
|
|||
|
||||
### Tests are now divided into two types:
|
||||
#### 'Hello world' tests
|
||||
First type of test cases we call 'hello world' tests. They do not dependent on CppUTest library and are monolithic programs usually composed of one main function. Yo can find this tests in below example directories:
|
||||
First type of test cases we call 'hello world' tests. They do not dependent on CppUTest library and are monolithic programs usually composed of one main function. You can find this tests in below example directories:
|
||||
|
||||
* ```mbed/libraries/tests/mbed/```
|
||||
* ```mbed/libraries/tests/net/```
|
||||
|
|
@ -767,12 +767,12 @@ TEST(BusOut_digitalout_write, led_1_nc_2_nc_nc_3)
|
|||
```
|
||||
|
||||
## Example
|
||||
In below example we will run two example unit tests that are now available. tests ```UT_1``` and ```UT_2``` are unit tests used for now only to check if mbed SDK works with CppUTest library and if tests are being executed. In future number of unit tests will increase, nothing is also should stop you from writing and executing your own unit tests!
|
||||
In below example we will run two example unit tests that are now available. tests ```UT_1``` and ```UT_2``` are unit tests used for now only to check if mbed SDK works with CppUTest library and if tests are being executed. In future number of unit tests will increase, nothing is also stopping you from writing and executing your own unit tests!
|
||||
|
||||
### Example configuration
|
||||
By default unit tests ```UT_1``` and ```UT_2``` are not automated - simply test suite will ignore them. Also we do not want to create dependency to CppUTest library each time someone executes automation.
|
||||
|
||||
Note: To compile ```UT_1``` and ```UT_2``` tests CppUTest library described above installation is needed and not all users wish to add UT libs to their project. Also new to mbed users may find it difficult. This is why unit testing is an extra feature active only after you deliberately install and enable needed components.
|
||||
Note: To compile ```UT_1``` and ```UT_2``` tests CppUTest library described above, installation is needed and not all users wish to add UT libs to their project. Also new to mbed users may find it difficult. This is why unit testing is an extra feature active only after you deliberately install and enable needed components.
|
||||
|
||||
Bellow snippet shows how to modify 'automated' flag so test suite will consider unit tests ```UT_1``` and ```UT_2``` as part of "automated test portfolio". Just change flag 'automated' from ```False``` to ```True```.
|
||||
|
||||
|
|
|
|||
|
|
@ -199,7 +199,6 @@ static int32_t iso_trans_doing(hced_t *p_ed, uint32_t index);
|
|||
static void chk_iso_td_done(genelal_ed_t *p_g_ed);
|
||||
static int32_t chk_iso_ed(genelal_ed_t *p_g_ed);
|
||||
static void iso_trans_setting(genelal_ed_t *p_g_ed, uint32_t index);
|
||||
static uint32_t iso_chk_starting_frame(genelal_ed_t *p_g_ed);
|
||||
static void iso_trans(genelal_ed_t *p_g_ed);
|
||||
#endif
|
||||
static void connect_check(void);
|
||||
|
|
@ -215,6 +214,7 @@ static usb_ohci_reg_t *p_usb_reg = &usb_reg;
|
|||
static usbisr_fnc_t *p_usbisr_cb = NULL;
|
||||
static osSemaphoreId semid_cb = NULL;
|
||||
static uint32_t connect_change = 0xFFFFFFFF;
|
||||
static uint32_t connect_status = 0;
|
||||
static uint32_t init_end = 0;
|
||||
static genelal_ed_t ctl_ed;
|
||||
static genelal_ed_t blk_ed;
|
||||
|
|
@ -283,13 +283,13 @@ osThreadDef(int_ed_task_4, osPriorityNormal, 512);
|
|||
static void iso_ed_task_1(void const * argument) {
|
||||
iso_ed_task(argument);
|
||||
}
|
||||
osThreadDef(iso_ed_task_1, osPriorityNormal, 512);
|
||||
osThreadDef(iso_ed_task_1, osPriorityAboveNormal, 512);
|
||||
#endif
|
||||
#if (ISO_TRANS_MAX_NUM >= 2)
|
||||
static void iso_ed_task_2(void const * argument) {
|
||||
iso_ed_task(argument);
|
||||
}
|
||||
osThreadDef(iso_ed_task_2, osPriorityNormal, 512);
|
||||
osThreadDef(iso_ed_task_2, osPriorityAboveNormal, 512);
|
||||
#endif
|
||||
|
||||
void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc) {
|
||||
|
|
@ -878,7 +878,9 @@ static void control_trans(genelal_ed_t *p_g_ed) {
|
|||
p_g_ed->pipe_no = USB_HOST_PIPE0;
|
||||
|
||||
p_g_ed->trans_wait = 1;
|
||||
|
||||
if (connect_status == 0) {
|
||||
ohciwrapp_loc_TransEnd(p_g_ed->pipe_no, TD_CC_DEVICENOTRESPONDING);
|
||||
} else {
|
||||
if (td_info.direction == 0) {
|
||||
uint16_t Req = (p_td->currBufPtr[1] << 8) + p_td->currBufPtr[0];
|
||||
uint16_t Val = (p_td->currBufPtr[3] << 8) + p_td->currBufPtr[2];
|
||||
|
|
@ -898,6 +900,7 @@ static void control_trans(genelal_ed_t *p_g_ed) {
|
|||
p_g_ed->trans_wait = 0;
|
||||
RZA_IO_RegWrite_32(&p_td->control, TD_CC_DEVICENOTRESPONDING, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
|
||||
}
|
||||
}
|
||||
|
||||
g_usbx_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usbx_host_CmdStage |= USB_HOST_CMD_IDLE;
|
||||
|
|
@ -928,6 +931,9 @@ static void bulk_trans(genelal_ed_t *p_g_ed) {
|
|||
set_togle(p_g_ed->pipe_no, p_td, p_ed);
|
||||
|
||||
p_g_ed->trans_wait = 1;
|
||||
if (connect_status == 0) {
|
||||
ohciwrapp_loc_TransEnd(p_g_ed->pipe_no, TD_CC_DEVICENOTRESPONDING);
|
||||
} else {
|
||||
if (td_info.direction == 1) {
|
||||
usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
|
||||
} else {
|
||||
|
|
@ -937,6 +943,7 @@ static void bulk_trans(genelal_ed_t *p_g_ed) {
|
|||
(void)osSemaphoreWait(p_g_ed->semid_wait, BLK_TRANS_TIMEOUT);
|
||||
usbx_host_stop_transfer(p_g_ed->pipe_no);
|
||||
}
|
||||
}
|
||||
|
||||
static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) {
|
||||
hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
|
||||
|
|
@ -1023,12 +1030,16 @@ static void int_trans(genelal_ed_t *p_g_ed) {
|
|||
|
||||
get_td_info(p_g_ed, &td_info);
|
||||
p_g_ed->trans_wait = 1;
|
||||
if (connect_status == 0) {
|
||||
ohciwrapp_loc_TransEnd(p_g_ed->pipe_no, TD_CC_DEVICENOTRESPONDING);
|
||||
} else {
|
||||
if (td_info.direction == 1) {
|
||||
usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
|
||||
} else {
|
||||
usbx_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info) {
|
||||
hced_t *p_ed = p_g_ed->p_curr_ed;
|
||||
|
|
@ -1089,7 +1100,6 @@ static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed) {
|
|||
static void iso_ed_task(void const * argument) {
|
||||
genelal_ed_t *p_iso_ed = &iso_ed[(uint32_t)argument];
|
||||
uint32_t wait_cnt = 0;
|
||||
uint32_t wait_time = 0;
|
||||
hcca_t *p_hcca;
|
||||
hced_t *p_ed;
|
||||
|
||||
|
|
@ -1115,17 +1125,26 @@ static void iso_ed_task(void const * argument) {
|
|||
if (p_iso_ed->p_curr_ed != NULL) {
|
||||
while ((p_usb_reg->HcControl & OR_CONTROL_IE) != 0) {
|
||||
if (chk_iso_ed(p_iso_ed) != 0) {
|
||||
wait_time = iso_chk_starting_frame(p_iso_ed);
|
||||
if (wait_time != 0) {
|
||||
osDelay(wait_time);
|
||||
p_usb_reg->HcFmNumber += wait_time;
|
||||
p_usb_reg->HcFmNumber &= 0x0000FFFF;
|
||||
hcisotd_t *p_isotd = (hcisotd_t *)p_iso_ed->p_curr_td;
|
||||
uint32_t starting_frame = p_isotd->control & 0x0000FFFF;
|
||||
uint32_t wait_time = 0;
|
||||
uint32_t wk_HcFmNumber = p_usb_reg->HcFmNumber;
|
||||
|
||||
if (starting_frame > wk_HcFmNumber) {
|
||||
wait_time = starting_frame - wk_HcFmNumber;
|
||||
} else {
|
||||
wait_time = (0xFFFF - wk_HcFmNumber) + starting_frame;
|
||||
}
|
||||
if ((wait_time >= 2) && (wait_time <= 1000)) {
|
||||
for (int cnt = 0; cnt < (wait_time - 1); cnt++) {
|
||||
osDelay(1);
|
||||
p_usb_reg->HcFmNumber = (wk_HcFmNumber + cnt) & 0x0000FFFF;
|
||||
}
|
||||
}
|
||||
p_iso_ed->psw_idx = 0;
|
||||
iso_trans(p_iso_ed);
|
||||
(void)osSemaphoreWait(p_iso_ed->semid_wait, osWaitForever);
|
||||
usbx_host_stop_transfer(p_iso_ed->pipe_no);
|
||||
wait_cnt = 1;
|
||||
wait_cnt = 8;
|
||||
} else {
|
||||
if (wait_cnt > 0) {
|
||||
wait_cnt--;
|
||||
|
|
@ -1234,18 +1253,6 @@ static void iso_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) {
|
|||
usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
|
||||
}
|
||||
|
||||
static uint32_t iso_chk_starting_frame(genelal_ed_t *p_g_ed) {
|
||||
hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
|
||||
uint32_t starting_frame = p_isotd->control & 0x0000FFFF;
|
||||
uint32_t wait_time = 0;
|
||||
|
||||
if ((p_g_ed->psw_idx == 0) && (starting_frame > p_usb_reg->HcFmNumber)) {
|
||||
wait_time = starting_frame - p_usb_reg->HcFmNumber;
|
||||
}
|
||||
|
||||
return wait_time;
|
||||
}
|
||||
|
||||
static void iso_trans(genelal_ed_t *p_g_ed) {
|
||||
hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
|
||||
tdinfo_t td_info;
|
||||
|
|
@ -1268,12 +1275,16 @@ static void iso_trans(genelal_ed_t *p_g_ed) {
|
|||
|
||||
get_td_info(p_g_ed, &td_info);
|
||||
p_g_ed->trans_wait = 1;
|
||||
if (connect_status == 0) {
|
||||
ohciwrapp_loc_TransEnd(p_g_ed->pipe_no, TD_CC_DEVICENOTRESPONDING);
|
||||
} else {
|
||||
if (td_info.direction == 1) {
|
||||
usbx_host_start_send_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr);
|
||||
} else {
|
||||
usbx_host_start_receive_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static void connect_check(void) {
|
||||
|
|
@ -1326,6 +1337,7 @@ static void connect_check(void) {
|
|||
void ohciwrapp_loc_Connect(uint32_t type) {
|
||||
uint32_t cnt;
|
||||
|
||||
connect_status = type;
|
||||
connect_change = type;
|
||||
if (type == 0) {
|
||||
if (ctl_ed.trans_wait == 1) {
|
||||
|
|
@ -1445,11 +1457,7 @@ void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode) {
|
|||
|
||||
if (p_isotd != NULL) {
|
||||
usbx_host_stop_transfer(pipe);
|
||||
if (p_usb_reg->HcFmNumber < 0x0000FFFF) {
|
||||
p_usb_reg->HcFmNumber++;
|
||||
} else {
|
||||
p_usb_reg->HcFmNumber = 0;
|
||||
}
|
||||
p_usb_reg->HcFmNumber = ((p_isotd->control & 0x0000FFFF) + p_wait_ed->psw_idx) & 0x0000FFFF;
|
||||
|
||||
/* Size of packet */
|
||||
p_isotd->offsetPSW[p_wait_ed->psw_idx] -= g_usbx_host_data_count[pipe];
|
||||
|
|
@ -1469,11 +1477,9 @@ void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode) {
|
|||
p_wait_ed->psw_idx++;
|
||||
}
|
||||
if (chk_iso_ed(p_wait_ed) != 0) {
|
||||
if (iso_chk_starting_frame(p_wait_ed) == 0) {
|
||||
iso_trans(p_wait_ed);
|
||||
next_trans = 1;
|
||||
}
|
||||
}
|
||||
if (next_trans == 0) {
|
||||
p_wait_ed->trans_wait = 0;
|
||||
(void)osSemaphoreRelease(p_wait_ed->semid_wait);
|
||||
|
|
|
|||
|
|
@ -51,12 +51,12 @@ Exported global variables and functions (to be accessed by other files)
|
|||
/* Endpoint Configuration Data Format */
|
||||
/********************************************************************************************************/
|
||||
/* LINE1: Pipe Window Select Register */
|
||||
/* CPU Access PIPE : PIPE1 to PIPE9 [ ### SET ### ] */
|
||||
/* CPU Access PIPE : USB_HOST_PIPE1 to USB_HOST_PIPE9 [ ### SET ### ] */
|
||||
/* LINE2: Pipe Configuration Register */
|
||||
/* Transfer Type : USB_HOST_NONE [ USB_HOST_NONE ] */
|
||||
/* Buffer Ready interrupt : USB_HOST_NONE [ USB_HOST_NONE ] */
|
||||
/* Double Buffer Mode : USB_HOST_CNT_ON / USB_HOST_CNT_OFF [ ### SET ### ] */
|
||||
/* Continuous Transmit: : USB_HOST_CNT_ON / USB_HOST_CNT_OFF [ ### SET ### ] */
|
||||
/* Double Buffer Mode : USB_HOST_DBLBON / USB_HOST_DBLBOFF [ ### SET ### ] */
|
||||
/* Continuous Transmit: : USB_HOST_CNTMDON / USB_HOST_CNTMDOFF [ ### SET ### ] */
|
||||
/* Short NAK : USB_HOST_NONE [ USB_HOST_NONE ] */
|
||||
/* Transfer Direction : USB_HOST_NONE [ USB_HOST_NONE ] */
|
||||
/* Endpoint Number : USB_HOST_NONE [ USB_HOST_NONE ] */
|
||||
|
|
@ -73,7 +73,6 @@ Exported global variables and functions (to be accessed by other files)
|
|||
/* : USB_HOST_CUSE [ ### SET ### ] */
|
||||
/* : USB_HOST_D0USE / USB_HOST_D1USE */
|
||||
/* : USB_HOST_D0DMA / USB_HOST_D0DMA */
|
||||
/* LINE7: use FIFO port Endian : USB_HOST_FIFO_BIG / USB_HOST_FIFO_LITTLE [ #SET# ] */
|
||||
/********************************************************************************************************/
|
||||
|
||||
/* Device Address 1 */
|
||||
|
|
@ -105,7 +104,7 @@ USB_HOST_CFG_PIPETBL_t usb_host_int_ep_tbl1[ ] =
|
|||
{
|
||||
USB_HOST_PIPE6,
|
||||
/* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
|
||||
USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
|
||||
USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBOFF | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
|
||||
(uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(40),
|
||||
USB_HOST_NONE,
|
||||
USB_HOST_NONE,
|
||||
|
|
@ -115,7 +114,7 @@ USB_HOST_CFG_PIPETBL_t usb_host_int_ep_tbl1[ ] =
|
|||
{
|
||||
USB_HOST_PIPE7,
|
||||
/* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
|
||||
USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
|
||||
USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBOFF | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
|
||||
(uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(41),
|
||||
USB_HOST_NONE,
|
||||
USB_HOST_NONE,
|
||||
|
|
@ -125,7 +124,7 @@ USB_HOST_CFG_PIPETBL_t usb_host_int_ep_tbl1[ ] =
|
|||
{
|
||||
USB_HOST_PIPE8,
|
||||
/* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
|
||||
USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
|
||||
USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBOFF | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
|
||||
(uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(42),
|
||||
USB_HOST_NONE,
|
||||
USB_HOST_NONE,
|
||||
|
|
@ -135,7 +134,7 @@ USB_HOST_CFG_PIPETBL_t usb_host_int_ep_tbl1[ ] =
|
|||
{
|
||||
USB_HOST_PIPE9,
|
||||
/* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
|
||||
USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
|
||||
USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBOFF | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
|
||||
(uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(43),
|
||||
USB_HOST_NONE,
|
||||
USB_HOST_NONE,
|
||||
|
|
@ -158,7 +157,7 @@ USB_HOST_CFG_PIPETBL_t usb_host_iso_ep_tbl1[ ] =
|
|||
{
|
||||
USB_HOST_PIPE1,
|
||||
/* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
|
||||
USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
|
||||
USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
|
||||
(uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(44),
|
||||
USB_HOST_NONE,
|
||||
USB_HOST_NONE,
|
||||
|
|
@ -168,8 +167,8 @@ USB_HOST_CFG_PIPETBL_t usb_host_iso_ep_tbl1[ ] =
|
|||
{
|
||||
USB_HOST_PIPE2,
|
||||
/* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
|
||||
USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
|
||||
(uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(60),
|
||||
USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
|
||||
(uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(76),
|
||||
USB_HOST_NONE,
|
||||
USB_HOST_NONE,
|
||||
USB_HOST_D1USE
|
||||
|
|
|
|||
|
|
@ -261,17 +261,7 @@ void USBHALHost::UsbIrqhandler() {
|
|||
|
||||
//Root device disconnected
|
||||
else {
|
||||
|
||||
if (!(int_status & OR_INTR_STATUS_WDH)) {
|
||||
usb_hcca->DoneHead = 0;
|
||||
}
|
||||
|
||||
deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
|
||||
|
||||
if (int_status & OR_INTR_STATUS_WDH) {
|
||||
usb_hcca->DoneHead = 0;
|
||||
ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_WDH);
|
||||
}
|
||||
}
|
||||
}
|
||||
ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,14 @@
|
|||
# ignore files for targets that aren't supported by the yotta build (to
|
||||
# minimise the size of the published module)
|
||||
|
||||
TARGET_ARM_SSG
|
||||
TARGET_Freescale
|
||||
TARGET_RENESAS
|
||||
TARGET_Silicon_Labs
|
||||
TARGET_Atmel
|
||||
TARGET_Maxim
|
||||
TARGET_NXP
|
||||
TARGET_STM
|
||||
TARGET_WIZNET
|
||||
TOOLCHAIN_IAR
|
||||
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
#ifndef MBED_H
|
||||
#define MBED_H
|
||||
|
||||
#define MBED_LIBRARY_VERSION 106
|
||||
#define MBED_LIBRARY_VERSION 109
|
||||
|
||||
#include "platform.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,769 @@
|
|||
/**************************************************************************//**
|
||||
* @file CMSDK_BEID.h
|
||||
* @brief CMSIS Core Peripheral Access Layer Header File for
|
||||
* CMSDK_BEID Device
|
||||
* @version V3.02
|
||||
* @date 15. November 2013
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2011 - 2013 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef CMSDK_BEID_H
|
||||
#define CMSDK_BEID_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ------------------------- Interrupt Number Definition ------------------------ */
|
||||
|
||||
typedef enum IRQn
|
||||
{
|
||||
/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
|
||||
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
|
||||
|
||||
/* ---------------------- CMSDK_BEID Specific Interrupt Numbers ------------------ */
|
||||
UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
|
||||
UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */
|
||||
UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */
|
||||
UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */
|
||||
UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */
|
||||
UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */
|
||||
UARTRX3_IRQn = 6, /* Was PORT0_ALL_IRQn Port 1 combined Interrupt */
|
||||
UARTTX3_IRQn = 7, /* Was PORT1_ALL_IRQn Port 1 combined Interrupt */
|
||||
TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
|
||||
TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
|
||||
DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
|
||||
SPI_IRQn = 11, /* SPI Interrupt */
|
||||
UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
|
||||
ETHERNET_IRQn = 13, /* Ethernet Interrupt */
|
||||
I2S_IRQn = 14, /* I2S Interrupt */
|
||||
TSC_IRQn = 15, /* Touch Screen Interrupt */
|
||||
// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
|
||||
PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
|
||||
PORT0_1_IRQn = 17, /* There are 16 pins in total */
|
||||
PORT0_2_IRQn = 18,
|
||||
PORT0_3_IRQn = 19,
|
||||
PORT0_4_IRQn = 20,
|
||||
PORT0_5_IRQn = 21,
|
||||
PORT0_6_IRQn = 22,
|
||||
PORT0_7_IRQn = 23,
|
||||
PORT0_8_IRQn = 24,
|
||||
PORT0_9_IRQn = 25,
|
||||
PORT0_10_IRQn = 26,
|
||||
PORT0_11_IRQn = 27,
|
||||
PORT0_12_IRQn = 28,
|
||||
PORT0_13_IRQn = 29,
|
||||
PORT0_14_IRQn = 30,
|
||||
PORT0_15_IRQn = 31,
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Processor and Core Peripheral Section ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
/* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
|
||||
#define __CM3_REV 0x0201 /* Core revision r2p1 */
|
||||
#define __MPU_PRESENT 1 /* MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
|
||||
|
||||
#include <core_cm3.h> /* Processor and core peripherals */
|
||||
#include "system_CMSDK_BEID.h" /* System Header */
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Device Specific Peripheral Section ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
/* ------------------- Start of section using anonymous unions ------------------ */
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma push
|
||||
#pragma anon_unions
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma language=extended
|
||||
#elif defined(__GNUC__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#elif defined(__TMS470__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#elif defined(__TASKING__)
|
||||
#pragma warning 586
|
||||
#else
|
||||
#warning Not supported compiler type
|
||||
#endif
|
||||
|
||||
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
|
||||
__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
|
||||
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
|
||||
union {
|
||||
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
|
||||
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
|
||||
};
|
||||
__IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
|
||||
|
||||
} CMSDK_UART_TypeDef;
|
||||
|
||||
/* CMSDK_UART DATA Register Definitions */
|
||||
|
||||
#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
|
||||
#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
|
||||
|
||||
#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
|
||||
#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
|
||||
|
||||
#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
|
||||
#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
|
||||
|
||||
#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
|
||||
#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
|
||||
|
||||
#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
|
||||
#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
|
||||
|
||||
#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
|
||||
#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
|
||||
|
||||
#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
|
||||
#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
|
||||
|
||||
#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
|
||||
#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
|
||||
|
||||
#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
|
||||
#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
|
||||
|
||||
#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
|
||||
#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
|
||||
|
||||
#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
|
||||
#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
|
||||
|
||||
#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
|
||||
#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
|
||||
|
||||
#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
|
||||
#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
|
||||
|
||||
#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
|
||||
#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
|
||||
|
||||
#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
|
||||
#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
|
||||
|
||||
#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
|
||||
#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
|
||||
|
||||
#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
|
||||
#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
|
||||
|
||||
|
||||
/*----------------------------- Timer (TIMER) -------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
|
||||
__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
|
||||
__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
|
||||
union {
|
||||
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
|
||||
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
|
||||
};
|
||||
|
||||
} CMSDK_TIMER_TypeDef;
|
||||
|
||||
/* CMSDK_TIMER CTRL Register Definitions */
|
||||
|
||||
#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
|
||||
#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
|
||||
|
||||
#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
|
||||
#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
|
||||
|
||||
#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
|
||||
#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
|
||||
|
||||
#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
|
||||
#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
|
||||
|
||||
#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
|
||||
#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
|
||||
|
||||
#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
|
||||
#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
|
||||
|
||||
#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
|
||||
#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
|
||||
|
||||
#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
|
||||
#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
|
||||
|
||||
|
||||
/*------------- Timer (TIM) --------------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
|
||||
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
|
||||
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
|
||||
__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
|
||||
__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
|
||||
__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
|
||||
__IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
|
||||
uint32_t RESERVED0;
|
||||
__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
|
||||
__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
|
||||
__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
|
||||
__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
|
||||
__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
|
||||
__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
|
||||
__IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
|
||||
uint32_t RESERVED1[945];
|
||||
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
|
||||
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
|
||||
} CMSDK_DUALTIMER_BOTH_TypeDef;
|
||||
|
||||
#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
|
||||
#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
|
||||
#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
|
||||
#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
|
||||
#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
|
||||
#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
|
||||
#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
|
||||
#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
|
||||
#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
|
||||
#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
|
||||
#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
|
||||
#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
|
||||
#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
|
||||
#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
|
||||
#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
|
||||
#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
|
||||
#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
|
||||
#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
|
||||
#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
|
||||
#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
|
||||
#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
|
||||
#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
|
||||
#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
|
||||
#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
|
||||
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
|
||||
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
|
||||
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
|
||||
__O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
|
||||
__I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
|
||||
__I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
|
||||
__IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
|
||||
} CMSDK_DUALTIMER_SINGLE_TypeDef;
|
||||
|
||||
#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
|
||||
#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
|
||||
#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
|
||||
#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
|
||||
#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
|
||||
#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
|
||||
#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
|
||||
#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
|
||||
#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
|
||||
#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
|
||||
#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
|
||||
#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
|
||||
|
||||
#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
|
||||
#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
|
||||
|
||||
|
||||
/*-------------------- General Purpose Input Output (GPIO) -------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
|
||||
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
|
||||
uint32_t RESERVED0[2];
|
||||
__IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
|
||||
__IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
|
||||
__IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
|
||||
__IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
|
||||
__IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
|
||||
__IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
|
||||
__IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
|
||||
__IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
|
||||
__IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
|
||||
__IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
|
||||
union {
|
||||
__I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
|
||||
__O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
|
||||
};
|
||||
uint32_t RESERVED1[241];
|
||||
__IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
|
||||
__IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
|
||||
} CMSDK_GPIO_TypeDef;
|
||||
|
||||
#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
|
||||
#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
|
||||
|
||||
#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
|
||||
#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
|
||||
|
||||
#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
|
||||
#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
|
||||
|
||||
#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
|
||||
#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
|
||||
|
||||
#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
|
||||
#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
|
||||
|
||||
#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
|
||||
#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
|
||||
|
||||
#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
|
||||
#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
|
||||
|
||||
#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
|
||||
#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
|
||||
|
||||
#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
|
||||
#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
|
||||
|
||||
#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
|
||||
#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
|
||||
|
||||
#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
|
||||
#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
|
||||
|
||||
#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
|
||||
#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
|
||||
|
||||
#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
|
||||
#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
|
||||
|
||||
#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
|
||||
#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
|
||||
|
||||
#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
|
||||
#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
|
||||
|
||||
#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
|
||||
#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
|
||||
|
||||
|
||||
/*------------- System Control (SYSCON) --------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
|
||||
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
|
||||
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
|
||||
__IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
|
||||
__IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
|
||||
uint32_t RESERVED0[3];
|
||||
__IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */
|
||||
__IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */
|
||||
uint32_t RESERVED1[2];
|
||||
__IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */
|
||||
__IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */
|
||||
uint32_t RESERVED2[2];
|
||||
__IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */
|
||||
__IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */
|
||||
__IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */
|
||||
__IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */
|
||||
__IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */
|
||||
__IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */
|
||||
uint32_t RESERVED3[10];
|
||||
__IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */
|
||||
__IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */
|
||||
__IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */
|
||||
__IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */
|
||||
__IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */
|
||||
__IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */
|
||||
uint32_t RESERVED4[2];
|
||||
__IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */
|
||||
__IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */
|
||||
__IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */
|
||||
__IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */
|
||||
__IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */
|
||||
__IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */
|
||||
uint32_t RESERVED5[2];
|
||||
__IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */
|
||||
__IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */
|
||||
__IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */
|
||||
__IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */
|
||||
__IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */
|
||||
__IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */
|
||||
__IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */
|
||||
__IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */
|
||||
__O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */
|
||||
__IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */
|
||||
uint32_t RESERVED6[2];
|
||||
__IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */
|
||||
__IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */
|
||||
__I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */
|
||||
uint32_t RESERVED7[1];
|
||||
__IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */
|
||||
__IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */
|
||||
__IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */
|
||||
} CMSDK_SYSCON_TypeDef;
|
||||
|
||||
#define CMSDK_SYSCON_REMAP_Pos 0
|
||||
#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
|
||||
|
||||
#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
|
||||
#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
|
||||
|
||||
#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
|
||||
#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
|
||||
|
||||
#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
|
||||
#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
|
||||
|
||||
#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
|
||||
#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
|
||||
|
||||
#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
|
||||
#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
|
||||
|
||||
#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
|
||||
#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
|
||||
|
||||
#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
|
||||
#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
|
||||
|
||||
#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
|
||||
#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
|
||||
|
||||
#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
|
||||
#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
|
||||
|
||||
|
||||
/*------------- PL230 uDMA (PL230) --------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
|
||||
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
|
||||
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
|
||||
__I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
|
||||
__I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
|
||||
__O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
|
||||
__IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
|
||||
__O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
|
||||
__IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
|
||||
__O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
|
||||
__IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
|
||||
__O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
|
||||
__IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
|
||||
__O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
|
||||
__IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
|
||||
__O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
|
||||
uint32_t RESERVED0[3];
|
||||
__IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
|
||||
|
||||
} CMSDK_PL230_TypeDef;
|
||||
|
||||
#define PL230_DMA_CHNL_BITS 0
|
||||
|
||||
#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
|
||||
#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
|
||||
|
||||
#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
|
||||
#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
|
||||
|
||||
#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
|
||||
#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
|
||||
|
||||
#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
|
||||
#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
|
||||
|
||||
#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
|
||||
#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
|
||||
|
||||
#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
|
||||
#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
|
||||
|
||||
#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
|
||||
#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
|
||||
|
||||
#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
|
||||
#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
|
||||
|
||||
#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
|
||||
#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
|
||||
|
||||
#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
|
||||
#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
|
||||
|
||||
#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
|
||||
#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
|
||||
|
||||
#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
|
||||
#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
|
||||
|
||||
#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
|
||||
#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
|
||||
|
||||
#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
|
||||
#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
|
||||
|
||||
#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
|
||||
#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
|
||||
|
||||
#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
|
||||
#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
|
||||
|
||||
#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
|
||||
#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
|
||||
|
||||
#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
|
||||
#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
|
||||
|
||||
#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
|
||||
#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
|
||||
|
||||
#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
|
||||
#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
|
||||
|
||||
#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
|
||||
#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
|
||||
|
||||
#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
|
||||
#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
|
||||
|
||||
#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
|
||||
#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
|
||||
|
||||
|
||||
/*------------------- Watchdog ----------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
|
||||
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
|
||||
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
|
||||
__O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
|
||||
__I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
|
||||
__I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
|
||||
uint32_t RESERVED0[762];
|
||||
__IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
|
||||
uint32_t RESERVED1[191];
|
||||
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
|
||||
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
|
||||
}CMSDK_WATCHDOG_TypeDef;
|
||||
|
||||
#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
|
||||
#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
|
||||
|
||||
#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
|
||||
#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
|
||||
|
||||
#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
|
||||
#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
|
||||
|
||||
#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
|
||||
#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
|
||||
|
||||
#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
|
||||
#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
|
||||
|
||||
#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
|
||||
#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
|
||||
|
||||
#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
|
||||
#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
|
||||
|
||||
#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
|
||||
#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
|
||||
|
||||
#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
|
||||
#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
|
||||
|
||||
#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
|
||||
#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
|
||||
|
||||
|
||||
|
||||
/* -------------------- End of section using anonymous unions ------------------- */
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma pop
|
||||
#elif defined(__ICCARM__)
|
||||
/* leave anonymous unions enabled */
|
||||
#elif defined(__GNUC__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#elif defined(__TMS470__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#elif defined(__TASKING__)
|
||||
#pragma warning restore
|
||||
#else
|
||||
#warning Not supported compiler type
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Peripheral memory map ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
/* Peripheral and SRAM base address */
|
||||
#define CMSDK_FLASH_BASE (0x00000000UL)
|
||||
#define CMSDK_SRAM_BASE (0x20000000UL)
|
||||
#define CMSDK_PERIPH_BASE (0x40000000UL)
|
||||
|
||||
#define CMSDK_RAM_BASE (0x20000000UL)
|
||||
#define CMSDK_APB_BASE (0x40000000UL)
|
||||
#define CMSDK_AHB_BASE (0x40010000UL)
|
||||
|
||||
/* APB peripherals */
|
||||
#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
|
||||
#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
|
||||
#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
|
||||
#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
|
||||
#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
|
||||
#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x5000UL)
|
||||
#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x4000UL)
|
||||
#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
|
||||
#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL)
|
||||
#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
|
||||
#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
|
||||
|
||||
/* AHB peripherals */
|
||||
#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
|
||||
#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
|
||||
#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
|
||||
#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
|
||||
#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Peripheral declaration ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
|
||||
#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
|
||||
#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
|
||||
#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
|
||||
#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
|
||||
#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
|
||||
#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
|
||||
#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
|
||||
#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
|
||||
#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
|
||||
#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
|
||||
#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
|
||||
#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
|
||||
#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
|
||||
#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
|
||||
#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CMSDK_BEID_H */
|
||||
|
|
@ -0,0 +1,616 @@
|
|||
/*
|
||||
* Copyright:
|
||||
* ----------------------------------------------------------------
|
||||
* This confidential and proprietary software may be used only as
|
||||
* authorised by a licensing agreement from ARM Limited
|
||||
* (C) COPYRIGHT 2014 ARM Limited
|
||||
* ALL RIGHTS RESERVED
|
||||
* The entire notice above must be reproduced on all authorised
|
||||
* copies and copies may only be made to the extent permitted
|
||||
* by a licensing agreement from ARM Limited.
|
||||
* ----------------------------------------------------------------
|
||||
* File: smm_mps2.h
|
||||
* Release: Version 1.0
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#ifndef __SMM_MPS2_H
|
||||
#define __SMM_MPS2_H
|
||||
|
||||
#include "peripherallink.h" /* device specific header file */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/* FPGA System Register declaration */
|
||||
/******************************************************************************/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
|
||||
// [31:2] : Reserved
|
||||
// [1:0] : LEDs
|
||||
uint32_t RESERVED1[1];
|
||||
__IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
|
||||
// [31:2] : Reserved
|
||||
// [1:0] : Buttons
|
||||
uint32_t RESERVED2[1];
|
||||
__IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
|
||||
__IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
|
||||
__IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
|
||||
// Increments when 32-bit prescale counter reach zero
|
||||
uint32_t RESERVED3[1];
|
||||
__IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
|
||||
// Bit[31:0] : reload value for prescale counter
|
||||
__IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
|
||||
// current value of the pre-scaler counter
|
||||
// The Cycle Up Counter increment when the prescale down counter reach 0
|
||||
// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
|
||||
uint32_t RESERVED4[9];
|
||||
__IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
|
||||
// [31:10] : Reserved
|
||||
// [9] : SHIELD_1_SPI_nCS
|
||||
// [8] : SHIELD_0_SPI_nCS
|
||||
// [7] : ADC_SPI_nCS
|
||||
// [6] : CLCD_BL_CTRL
|
||||
// [5] : CLCD_RD
|
||||
// [4] : CLCD_RS
|
||||
// [3] : CLCD_RESET
|
||||
// [2] : RESERVED
|
||||
// [1] : SPI_nSS
|
||||
// [0] : CLCD_CS
|
||||
} MPS2_FPGAIO_TypeDef;
|
||||
|
||||
// MISC register bit definitions
|
||||
|
||||
#define CLCD_CS_Pos 0
|
||||
#define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
|
||||
#define SPI_nSS_Pos 1
|
||||
#define SPI_nSS_Msk (1UL<<SPI_nSS_Pos)
|
||||
#define CLCD_RESET_Pos 3
|
||||
#define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
|
||||
#define CLCD_RS_Pos 4
|
||||
#define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
|
||||
#define CLCD_RD_Pos 5
|
||||
#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
|
||||
#define CLCD_BL_Pos 6
|
||||
#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
|
||||
#define ADC_nCS_Pos 7
|
||||
#define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
|
||||
#define SHIELD_0_nCS_Pos 8
|
||||
#define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
|
||||
#define SHIELD_1_nCS_Pos 9
|
||||
#define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
|
||||
|
||||
/******************************************************************************/
|
||||
/* SCC Register declaration */
|
||||
/******************************************************************************/
|
||||
|
||||
typedef struct //
|
||||
{
|
||||
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
|
||||
// [31:1] : Reserved
|
||||
// [0] 1 : REMAP BlockRam to ZBT
|
||||
__IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
|
||||
// [31:8] : Reserved
|
||||
// [7:0] : MCC LEDs
|
||||
uint32_t RESERVED0[1];
|
||||
__I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
|
||||
// [31:8] : Reserved
|
||||
// [7:0] : These bits indicate state of the MCC switches
|
||||
__I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
|
||||
// [31:4] : Reserved
|
||||
// [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
|
||||
uint32_t RESERVED1[35];
|
||||
__IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
|
||||
// [31:0] : Data
|
||||
__IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
|
||||
// [31:0] : Data
|
||||
__IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
|
||||
// [31] : Start (generates interrupt on write to this bit)
|
||||
// [30] : R/W access
|
||||
// [29:26] : Reserved
|
||||
// [25:20] : Function value
|
||||
// [19:12] : Reserved
|
||||
// [11:0] : Device (value of 0/1/2 for supported clocks)
|
||||
__IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
|
||||
// [31:2] : Reserved
|
||||
// [1] : Error
|
||||
// [0] : Complete
|
||||
__IO uint32_t RESERVED2[20];
|
||||
__IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
|
||||
// [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
|
||||
// [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
|
||||
// [15:1] : Reserved
|
||||
// [0] : This bit indicates if all enabled DLLs are locked
|
||||
uint32_t RESERVED3[957];
|
||||
__I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
|
||||
// [31:24] : FPGA build number
|
||||
// [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
|
||||
// [19:11] : Reserved
|
||||
// [10] : if “1” SCC_SW register has been implemented
|
||||
// [9] : if “1” SCC_LED register has been implemented
|
||||
// [8] : if “1” DLL lock register has been implemented
|
||||
// [7:0] : number of SCC configuration register
|
||||
__I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
|
||||
// [31:24] : Implementer ID: 0x41 = ARM
|
||||
// [23:20] : Application note IP variant number
|
||||
// [19:16] : IP Architecture: 0x4 =AHB
|
||||
// [15:4] : Primary part number: 386 = AN386
|
||||
// [3:0] : Application note IP revision number
|
||||
} MPS2_SCC_TypeDef;
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* SSP Peripheral declaration */
|
||||
/******************************************************************************/
|
||||
|
||||
typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
|
||||
{
|
||||
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
|
||||
// [31:16] : Reserved
|
||||
// [15:8] : Serial clock rate
|
||||
// [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
|
||||
// [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
|
||||
// [5:4] : Frame format
|
||||
// [3:0] : Data Size Select
|
||||
__IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
|
||||
// [31:4] : Reserved
|
||||
// [3] : Slave-mode output disable
|
||||
// [2] : Master or slave mode select
|
||||
// [1] : Synchronous serial port enable
|
||||
// [0] : Loop back mode
|
||||
__IO uint32_t DR; // Offset: 0x008 (R/W) Data register
|
||||
// [31:16] : Reserved
|
||||
// [15:0] : Transmit/Receive FIFO
|
||||
__I uint32_t SR; // Offset: 0x00C (R/ ) Status register
|
||||
// [31:5] : Reserved
|
||||
// [4] : PrimeCell SSP busy flag
|
||||
// [3] : Receive FIFO full
|
||||
// [2] : Receive FIFO not empty
|
||||
// [1] : Transmit FIFO not full
|
||||
// [0] : Transmit FIFO empty
|
||||
__IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
|
||||
// [31:8] : Reserved
|
||||
// [8:0] : Clock prescale divisor
|
||||
__IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
|
||||
// [31:4] : Reserved
|
||||
// [3] : Transmit FIFO interrupt mask
|
||||
// [2] : Receive FIFO interrupt mask
|
||||
// [1] : Receive timeout interrupt mask
|
||||
// [0] : Receive overrun interrupt mask
|
||||
__I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
|
||||
// [31:4] : Reserved
|
||||
// [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
|
||||
// [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
|
||||
// [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
|
||||
// [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
|
||||
__I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
|
||||
// [31:4] : Reserved
|
||||
// [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
|
||||
// [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
|
||||
// [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
|
||||
// [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
|
||||
__O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
|
||||
// [31:2] : Reserved
|
||||
// [1] : Clears the SSPRTINTR interrupt
|
||||
// [0] : Clears the SSPRORINTR interrupt
|
||||
__IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
|
||||
// [31:2] : Reserved
|
||||
// [1] : Transmit DMA Enable
|
||||
// [0] : Receive DMA Enable
|
||||
} MPS2_SSP_TypeDef;
|
||||
|
||||
|
||||
// SSP_CR0 Control register 0
|
||||
#define SSP_CR0_DSS_Pos 0 // Data Size Select
|
||||
#define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
|
||||
#define SSP_CR0_FRF_Pos 4 // Frame Format Select
|
||||
#define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
|
||||
#define SSP_CR0_SPO_Pos 6 // SSPCLKOUT polarity
|
||||
#define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
|
||||
#define SSP_CR0_SPH_Pos 7 // SSPCLKOUT phase
|
||||
#define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
|
||||
#define SSP_CR0_SCR_Pos 8 // Serial Clock Rate (divide)
|
||||
#define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
|
||||
|
||||
#define SSP_CR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
|
||||
#define SSP_CR0_FRF_MOT 0x0000 // Frame format, Motorola
|
||||
#define SSP_CR0_DSS_8 0x0007 // Data packet size, 8bits
|
||||
#define SSP_CR0_DSS_16 0x000F // Data packet size, 16bits
|
||||
|
||||
// SSP_CR1 Control register 1
|
||||
#define SSP_CR1_LBM_Pos 0 // Loop Back Mode
|
||||
#define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
|
||||
#define SSP_CR1_SSE_Pos 1 // Serial port enable
|
||||
#define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
|
||||
#define SSP_CR1_MS_Pos 2 // Master or Slave mode
|
||||
#define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
|
||||
#define SSP_CR1_SOD_Pos 3 // Slave Output mode Disable
|
||||
#define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
|
||||
|
||||
// SSP_SR Status register
|
||||
#define SSP_SR_TFE_Pos 0 // Transmit FIFO empty
|
||||
#define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
|
||||
#define SSP_SR_TNF_Pos 1 // Transmit FIFO not full
|
||||
#define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
|
||||
#define SSP_SR_RNE_Pos 2 // Receive FIFO not empty
|
||||
#define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
|
||||
#define SSP_SR_RFF_Pos 3 // Receive FIFO full
|
||||
#define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
|
||||
#define SSP_SR_BSY_Pos 4 // Busy
|
||||
#define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
|
||||
|
||||
// SSP_CPSR Clock prescale register
|
||||
#define SSP_CPSR_CPD_Pos 0 // Clock prescale divisor
|
||||
#define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
|
||||
|
||||
#define SSP_CPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
|
||||
|
||||
// SSPIMSC Interrupt mask set and clear register
|
||||
#define SSP_IMSC_RORIM_Pos 0 // Receive overrun not Masked
|
||||
#define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
|
||||
#define SSP_IMSC_RTIM_Pos 1 // Receive timeout not Masked
|
||||
#define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
|
||||
#define SSP_IMSC_RXIM_Pos 2 // Receive FIFO not Masked
|
||||
#define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
|
||||
#define SSP_IMSC_TXIM_Pos 3 // Transmit FIFO not Masked
|
||||
#define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
|
||||
|
||||
// SSPRIS Raw interrupt status register
|
||||
#define SSP_RIS_RORRIS_Pos 0 // Raw Overrun interrupt flag
|
||||
#define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
|
||||
#define SSP_RIS_RTRIS_Pos 1 // Raw Timemout interrupt flag
|
||||
#define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
|
||||
#define SSP_RIS_RXRIS_Pos 2 // Raw Receive interrupt flag
|
||||
#define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
|
||||
#define SSP_RIS_TXRIS_Pos 3 // Raw Transmit interrupt flag
|
||||
#define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
|
||||
|
||||
// SSPMIS Masked interrupt status register
|
||||
#define SSP_MIS_RORMIS_Pos 0 // Masked Overrun interrupt flag
|
||||
#define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
|
||||
#define SSP_MIS_RTMIS_Pos 1 // Masked Timemout interrupt flag
|
||||
#define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
|
||||
#define SSP_MIS_RXMIS_Pos 2 // Masked Receive interrupt flag
|
||||
#define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
|
||||
#define SSP_MIS_TXMIS_Pos 3 // Masked Transmit interrupt flag
|
||||
#define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
|
||||
|
||||
// SSPICR Interrupt clear register
|
||||
#define SSP_ICR_RORIC_Pos 0 // Clears Overrun interrupt flag
|
||||
#define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
|
||||
#define SSP_ICR_RTIC_Pos 1 // Clears Timemout interrupt flag
|
||||
#define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
|
||||
|
||||
// SSPDMACR DMA control register
|
||||
#define SSP_DMACR_RXDMAE_Pos 0 // Enable Receive FIFO DMA
|
||||
#define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
|
||||
#define SSP_DMACR_TXDMAE_Pos 1 // Enable Transmit FIFO DMA
|
||||
#define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
|
||||
|
||||
/******************************************************************************/
|
||||
/* Audio and Touch Screen (I2C) Peripheral declaration */
|
||||
/******************************************************************************/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union {
|
||||
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
|
||||
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
|
||||
};
|
||||
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
|
||||
} MPS2_I2C_TypeDef;
|
||||
|
||||
#define SDA 1 << 1
|
||||
#define SCL 1 << 0
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* Audio I2S Peripheral declaration */
|
||||
/******************************************************************************/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/*!< Offset: 0x000 CONTROL Register (R/W) */
|
||||
__IO uint32_t CONTROL; // <h> CONTROL </h>
|
||||
// <o.0> TX Enable
|
||||
// <0=> TX disabled
|
||||
// <1=> TX enabled
|
||||
// <o.1> TX IRQ Enable
|
||||
// <0=> TX IRQ disabled
|
||||
// <1=> TX IRQ enabled
|
||||
// <o.2> RX Enable
|
||||
// <0=> RX disabled
|
||||
// <1=> RX enabled
|
||||
// <o.3> RX IRQ Enable
|
||||
// <0=> RX IRQ disabled
|
||||
// <1=> RX IRQ enabled
|
||||
// <o.10..8> TX Buffer Water Level
|
||||
// <0=> / IRQ triggers when any space available
|
||||
// <1=> / IRQ triggers when more than 1 space available
|
||||
// <2=> / IRQ triggers when more than 2 space available
|
||||
// <3=> / IRQ triggers when more than 3 space available
|
||||
// <4=> Undefined!
|
||||
// <5=> Undefined!
|
||||
// <6=> Undefined!
|
||||
// <7=> Undefined!
|
||||
// <o.14..12> RX Buffer Water Level
|
||||
// <0=> Undefined!
|
||||
// <1=> / IRQ triggers when less than 1 space available
|
||||
// <2=> / IRQ triggers when less than 2 space available
|
||||
// <3=> / IRQ triggers when less than 3 space available
|
||||
// <4=> / IRQ triggers when less than 4 space available
|
||||
// <5=> Undefined!
|
||||
// <6=> Undefined!
|
||||
// <7=> Undefined!
|
||||
// <o.16> FIFO reset
|
||||
// <0=> Normal operation
|
||||
// <1=> FIFO reset
|
||||
// <o.17> Audio Codec reset
|
||||
// <0=> Normal operation
|
||||
// <1=> Assert audio Codec reset
|
||||
/*!< Offset: 0x004 STATUS Register (R/ ) */
|
||||
__I uint32_t STATUS; // <h> STATUS </h>
|
||||
// <o.0> TX Buffer alert
|
||||
// <0=> TX buffer don't need service yet
|
||||
// <1=> TX buffer need service
|
||||
// <o.1> RX Buffer alert
|
||||
// <0=> RX buffer don't need service yet
|
||||
// <1=> RX buffer need service
|
||||
// <o.2> TX Buffer Empty
|
||||
// <0=> TX buffer have data
|
||||
// <1=> TX buffer empty
|
||||
// <o.3> TX Buffer Full
|
||||
// <0=> TX buffer not full
|
||||
// <1=> TX buffer full
|
||||
// <o.4> RX Buffer Empty
|
||||
// <0=> RX buffer have data
|
||||
// <1=> RX buffer empty
|
||||
// <o.5> RX Buffer Full
|
||||
// <0=> RX buffer not full
|
||||
// <1=> RX buffer full
|
||||
union {
|
||||
/*!< Offset: 0x008 Error Status Register (R/ ) */
|
||||
__I uint32_t ERROR; // <h> ERROR </h>
|
||||
// <o.0> TX error
|
||||
// <0=> Okay
|
||||
// <1=> TX overrun/underrun
|
||||
// <o.1> RX error
|
||||
// <0=> Okay
|
||||
// <1=> RX overrun/underrun
|
||||
/*!< Offset: 0x008 Error Clear Register ( /W) */
|
||||
__O uint32_t ERRORCLR; // <h> ERRORCLR </h>
|
||||
// <o.0> TX error
|
||||
// <0=> Okay
|
||||
// <1=> Clear TX error
|
||||
// <o.1> RX error
|
||||
// <0=> Okay
|
||||
// <1=> Clear RX error
|
||||
};
|
||||
/*!< Offset: 0x00C Divide ratio Register (R/W) */
|
||||
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
|
||||
// <o.9..0> TX error (default 0x80)
|
||||
/*!< Offset: 0x010 Transmit Buffer ( /W) */
|
||||
__O uint32_t TXBUF; // <h> Transmit buffer </h>
|
||||
// <o.15..0> Right channel
|
||||
// <o.31..16> Left channel
|
||||
/*!< Offset: 0x014 Receive Buffer (R/ ) */
|
||||
__I uint32_t RXBUF; // <h> Receive buffer </h>
|
||||
// <o.15..0> Right channel
|
||||
// <o.31..16> Left channel
|
||||
uint32_t RESERVED1[186];
|
||||
__IO uint32_t ITCR; // <h> Integration Test Control Register </h>
|
||||
// <o.0> ITEN
|
||||
// <0=> Normal operation
|
||||
// <1=> Integration Test mode enable
|
||||
__O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
|
||||
// <o.0> SDIN
|
||||
__O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
|
||||
// <o.0> SDOUT
|
||||
// <o.1> SCLK
|
||||
// <o.2> LRCK
|
||||
// <o.3> IRQOUT
|
||||
} MPS2_I2S_TypeDef;
|
||||
|
||||
#define I2S_CONTROL_TXEN_Pos 0
|
||||
#define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
|
||||
|
||||
#define I2S_CONTROL_TXIRQEN_Pos 1
|
||||
#define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
|
||||
|
||||
#define I2S_CONTROL_RXEN_Pos 2
|
||||
#define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
|
||||
|
||||
#define I2S_CONTROL_RXIRQEN_Pos 3
|
||||
#define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
|
||||
|
||||
#define I2S_CONTROL_TXWLVL_Pos 8
|
||||
#define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
|
||||
|
||||
#define I2S_CONTROL_RXWLVL_Pos 12
|
||||
#define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
|
||||
/* FIFO reset*/
|
||||
#define I2S_CONTROL_FIFORST_Pos 16
|
||||
#define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
|
||||
/* Codec reset*/
|
||||
#define I2S_CONTROL_CODECRST_Pos 17
|
||||
#define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
|
||||
|
||||
#define I2S_STATUS_TXIRQ_Pos 0
|
||||
#define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
|
||||
|
||||
#define I2S_STATUS_RXIRQ_Pos 1
|
||||
#define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
|
||||
|
||||
#define I2S_STATUS_TXEmpty_Pos 2
|
||||
#define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
|
||||
|
||||
#define I2S_STATUS_TXFull_Pos 3
|
||||
#define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
|
||||
|
||||
#define I2S_STATUS_RXEmpty_Pos 4
|
||||
#define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
|
||||
|
||||
#define I2S_STATUS_RXFull_Pos 5
|
||||
#define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
|
||||
|
||||
#define I2S_ERROR_TXERR_Pos 0
|
||||
#define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
|
||||
|
||||
#define I2S_ERROR_RXERR_Pos 1
|
||||
#define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
|
||||
|
||||
/******************************************************************************/
|
||||
/* SMSC9220 Register Definitions */
|
||||
/******************************************************************************/
|
||||
|
||||
typedef struct // SMSC LAN9220
|
||||
{
|
||||
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
|
||||
uint32_t RESERVED1[0x7];
|
||||
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
|
||||
uint32_t RESERVED2[0x7];
|
||||
|
||||
__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
|
||||
__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
|
||||
__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
|
||||
__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
|
||||
|
||||
__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
|
||||
__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
|
||||
__IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
|
||||
__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
|
||||
uint32_t RESERVED3; // Reserved for future use (offset 0x60)
|
||||
__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
|
||||
__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
|
||||
__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
|
||||
__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
|
||||
__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
|
||||
__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
|
||||
__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
|
||||
__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
|
||||
__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
|
||||
__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
|
||||
__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
|
||||
__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
|
||||
uint32_t RESERVED4; // Reserved for future use (offset 0x94)
|
||||
__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
|
||||
__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
|
||||
__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
|
||||
__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
|
||||
__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
|
||||
__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
|
||||
__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
|
||||
__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
|
||||
|
||||
} SMSC9220_TypeDef;
|
||||
|
||||
// SMSC9220 MAC Registers Indices
|
||||
#define SMSC9220_MAC_CR 0x1
|
||||
#define SMSC9220_MAC_ADDRH 0x2
|
||||
#define SMSC9220_MAC_ADDRL 0x3
|
||||
#define SMSC9220_MAC_HASHH 0x4
|
||||
#define SMSC9220_MAC_HASHL 0x5
|
||||
#define SMSC9220_MAC_MII_ACC 0x6
|
||||
#define SMSC9220_MAC_MII_DATA 0x7
|
||||
#define SMSC9220_MAC_FLOW 0x8
|
||||
#define SMSC9220_MAC_VLAN1 0x9
|
||||
#define SMSC9220_MAC_VLAN2 0xA
|
||||
#define SMSC9220_MAC_WUFF 0xB
|
||||
#define SMSC9220_MAC_WUCSR 0xC
|
||||
|
||||
// SMSC9220 PHY Registers Indices
|
||||
#define SMSC9220_PHY_BCONTROL 0x0
|
||||
#define SMSC9220_PHY_BSTATUS 0x1
|
||||
#define SMSC9220_PHY_ID1 0x2
|
||||
#define SMSC9220_PHY_ID2 0x3
|
||||
#define SMSC9220_PHY_ANEG_ADV 0x4
|
||||
#define SMSC9220_PHY_ANEG_LPA 0x5
|
||||
#define SMSC9220_PHY_ANEG_EXP 0x6
|
||||
#define SMSC9220_PHY_MCONTROL 0x17
|
||||
#define SMSC9220_PHY_MSTATUS 0x18
|
||||
#define SMSC9220_PHY_CSINDICATE 0x27
|
||||
#define SMSC9220_PHY_INTSRC 0x29
|
||||
#define SMSC9220_PHY_INTMASK 0x30
|
||||
#define SMSC9220_PHY_CS 0x31
|
||||
|
||||
/******************************************************************************/
|
||||
/* Peripheral memory map */
|
||||
/******************************************************************************/
|
||||
|
||||
#define MPS2_SSP0_BASE (0x40020000ul) /* User SSP Base Address */
|
||||
#define MPS2_SSP1_BASE (0x40021000ul) /* CLCD SSP Base Address */
|
||||
#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
|
||||
#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
|
||||
#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
|
||||
#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */
|
||||
#define MPS2_SSP3_BASE (0x40026000ul) /* shield 0 SSP Base Address */
|
||||
#define MPS2_SSP4_BASE (0x40027000ul) /* shield 1 SSP Base Address */
|
||||
#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
|
||||
#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Audio Interface I2C Base Address */
|
||||
#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Audio Interface I2C Base Address */
|
||||
#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
|
||||
|
||||
#ifdef CORTEX_M7
|
||||
#define SMSC9220_BASE (0xA0000000ul) /* Ethernet SMSC9220 Base Address */
|
||||
#else
|
||||
#define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
|
||||
#endif
|
||||
|
||||
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
|
||||
#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* Peripheral declaration */
|
||||
/******************************************************************************/
|
||||
|
||||
#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
|
||||
#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
|
||||
#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
|
||||
#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
|
||||
#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE )
|
||||
#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
|
||||
#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
|
||||
#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
|
||||
#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
|
||||
#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
|
||||
#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
|
||||
#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
|
||||
#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
|
||||
|
||||
//******************************************************************************/
|
||||
/* General MACRO Definitions */
|
||||
/******************************************************************************/
|
||||
|
||||
//#define DEBUG
|
||||
//#ifdef DEBUG
|
||||
// #define debug(...) printf(__VA_ARGS__)
|
||||
//#else
|
||||
// #define debug(...)
|
||||
//#endif // ifdef DEBUG
|
||||
|
||||
// Bit control macros
|
||||
//#define HW_REG(base,offset) *((volatile unsigned int *)((base) + (offset)))
|
||||
|
||||
#define CREATE_MASK(msb, lsb) (((1U << ((msb) - (lsb) + 1)) - 1) << (lsb))
|
||||
#define MASK_BITS(arg, msb, lsb) ((arg) & CREATE_MASK(msb, lsb))
|
||||
#define EXTRACT_BITS(arg, msb, lsb) (MASK_BITS(arg, msb, lsb) >> (lsb))
|
||||
#define INSERT_BITS(arg, msb, lsb, value) \
|
||||
((arg) = ((arg) & ~CREATE_MASK(msb, lsb)) | (((value) << (lsb)) & CREATE_MASK(msb, lsb)))
|
||||
|
||||
#define MASK_FIELD(arg, field) MASK_BITS(arg, field##_MSB, field##_LSB)
|
||||
#define EXTRACT_FIELD(arg, field) EXTRACT_BITS(arg, field##_MSB, field##_LSB)
|
||||
#define INSERT_FIELD(arg, field, value) INSERT_BITS(arg, field##_MSB, field##_LSB, value)
|
||||
|
||||
#define SET_BIT(arg, bit) ((arg) |= (1 << (bit)))
|
||||
#define CLEAR_BIT(arg, bit) ((arg) &= ~(1 << (bit)))
|
||||
#define TEST_BIT(arg, bit) ((arg) & (1 << (bit)))
|
||||
|
||||
#ifndef NoOfElements
|
||||
#define NoOfElements(array) (sizeof(array) / sizeof(array[0]))
|
||||
#endif
|
||||
|
||||
#endif /* __SMM_MPS2_H */
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x00000000 0x00400000 { ; load region size_region
|
||||
ER_IROM1 +0 { ; load address = execution address
|
||||
*.o (RESET, +FIRST)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 +0 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,291 @@
|
|||
;/**************************************************************************//**
|
||||
; * @file startup_CMSDK_CM3.s
|
||||
; * @brief CMSIS Core Device Startup File for
|
||||
; * CMSDK_CM3 Device
|
||||
; * @version V3.02
|
||||
; * @date 15. November 2013
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2014 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
;/* Copyright (c) 2011 - 2013 ARM LIMITED
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00004000
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00001000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD UARTRX0_Handler ; UART 0 RX Handler
|
||||
DCD UARTTX0_Handler ; UART 0 TX Handler
|
||||
DCD UARTRX1_Handler ; UART 1 RX Handler
|
||||
DCD UARTTX1_Handler ; UART 1 TX Handler
|
||||
DCD UARTRX2_Handler ; UART 2 RX Handler
|
||||
DCD UARTTX2_Handler ; UART 2 TX Handler
|
||||
DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
|
||||
DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler
|
||||
DCD TIMER0_Handler ; TIMER 0 handler
|
||||
DCD TIMER1_Handler ; TIMER 1 handler
|
||||
DCD DUALTIMER_HANDLER ; Dual timer handler
|
||||
DCD SPI_Handler ; SPI exceptions Handler
|
||||
DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler
|
||||
DCD ETHERNET_Handler ; Ethernet Overflow Handler
|
||||
DCD I2S_Handler ; I2S Handler
|
||||
DCD TSC_Handler ; Touch Screen handler
|
||||
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
|
||||
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
|
||||
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
|
||||
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
|
||||
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
|
||||
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
|
||||
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
|
||||
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
|
||||
DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler
|
||||
DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler
|
||||
DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler
|
||||
DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler
|
||||
DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler
|
||||
DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler
|
||||
DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler
|
||||
DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT UARTRX0_Handler [WEAK]
|
||||
EXPORT UARTTX0_Handler [WEAK]
|
||||
EXPORT UARTRX1_Handler [WEAK]
|
||||
EXPORT UARTTX1_Handler [WEAK]
|
||||
EXPORT UARTRX2_Handler [WEAK]
|
||||
EXPORT UARTTX2_Handler [WEAK]
|
||||
EXPORT PORT0_COMB_Handler [WEAK]
|
||||
EXPORT PORT1_COMB_Handler [WEAK]
|
||||
EXPORT TIMER0_Handler [WEAK]
|
||||
EXPORT TIMER1_Handler [WEAK]
|
||||
EXPORT DUALTIMER_HANDLER [WEAK]
|
||||
EXPORT SPI_Handler [WEAK]
|
||||
EXPORT UARTOVF_Handler [WEAK]
|
||||
EXPORT ETHERNET_Handler [WEAK]
|
||||
EXPORT I2S_Handler [WEAK]
|
||||
EXPORT TSC_Handler [WEAK]
|
||||
EXPORT PORT0_0_Handler [WEAK]
|
||||
EXPORT PORT0_1_Handler [WEAK]
|
||||
EXPORT PORT0_2_Handler [WEAK]
|
||||
EXPORT PORT0_3_Handler [WEAK]
|
||||
EXPORT PORT0_4_Handler [WEAK]
|
||||
EXPORT PORT0_5_Handler [WEAK]
|
||||
EXPORT PORT0_6_Handler [WEAK]
|
||||
EXPORT PORT0_7_Handler [WEAK]
|
||||
EXPORT PORT0_8_Handler [WEAK]
|
||||
EXPORT PORT0_9_Handler [WEAK]
|
||||
EXPORT PORT0_10_Handler [WEAK]
|
||||
EXPORT PORT0_11_Handler [WEAK]
|
||||
EXPORT PORT0_12_Handler [WEAK]
|
||||
EXPORT PORT0_13_Handler [WEAK]
|
||||
EXPORT PORT0_14_Handler [WEAK]
|
||||
EXPORT PORT0_15_Handler [WEAK]
|
||||
|
||||
UARTRX0_Handler
|
||||
UARTTX0_Handler
|
||||
UARTRX1_Handler
|
||||
UARTTX1_Handler
|
||||
UARTRX2_Handler
|
||||
UARTTX2_Handler
|
||||
PORT0_COMB_Handler
|
||||
PORT1_COMB_Handler
|
||||
TIMER0_Handler
|
||||
TIMER1_Handler
|
||||
DUALTIMER_HANDLER
|
||||
SPI_Handler
|
||||
UARTOVF_Handler
|
||||
ETHERNET_Handler
|
||||
I2S_Handler
|
||||
TSC_Handler
|
||||
PORT0_0_Handler
|
||||
PORT0_1_Handler
|
||||
PORT0_2_Handler
|
||||
PORT0_3_Handler
|
||||
PORT0_4_Handler
|
||||
PORT0_5_Handler
|
||||
PORT0_6_Handler
|
||||
PORT0_7_Handler
|
||||
PORT0_8_Handler
|
||||
PORT0_9_Handler
|
||||
PORT0_10_Handler
|
||||
PORT0_11_Handler
|
||||
PORT0_12_Handler
|
||||
PORT0_13_Handler
|
||||
PORT0_14_Handler
|
||||
PORT0_15_Handler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/* mbed Microcontroller Library - CMSIS
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* A generic CMSIS include header, pulling in LPC1768 specifics
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_H
|
||||
#define MBED_CMSIS_H
|
||||
|
||||
#include "CMSDK_BEID.h"
|
||||
#include "SMM_MPS2.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* mbed Microcontroller Library - cmsis_nvic for LCP1768
|
||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*/
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
||||
uint32_t i;
|
||||
|
||||
// Copy and switch to dynamic vectors if the first time called
|
||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
||||
uint32_t *old_vectors = vectors;
|
||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
||||
vectors[i] = old_vectors[i];
|
||||
}
|
||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
||||
}
|
||||
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
}
|
||||
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
||||
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/* mbed Microcontroller Library - cmsis_nvic
|
||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#define NVIC_NUM_VECTORS (16 + 32)
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/*-----------------------------------------------------------------------------
|
||||
* Name: Device.h
|
||||
* Purpose: Include the correct device header file
|
||||
*-----------------------------------------------------------------------------
|
||||
* This file is part of the uVision/ARM development tools.
|
||||
* This software may only be used under the terms of a valid, current,
|
||||
* end user licence from KEIL for a compatible version of KEIL software
|
||||
* development tools. Nothing else gives you the right to use this software.
|
||||
*
|
||||
* This software is supplied "AS IS" without warranties of any kind.
|
||||
*
|
||||
* Copyright (c) 2013 KEIL - An ARM Company. All rights reserved.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef __DEVICE_H
|
||||
#define __DEVICE_H
|
||||
|
||||
#if defined CMSDK_CM0
|
||||
#include "CMSDK_CM0.h" /* device specific header file */
|
||||
#elif defined CMSDK_CM0plus
|
||||
#include "CMSDK_CM0plus.h" /* device specific header file */
|
||||
#elif defined CMSDK_CM3
|
||||
#include "CMSDK_CM3.h" /* device specific header file */
|
||||
#elif defined CMSDK_CM4
|
||||
#include "CMSDK_CM4.h" /* device specific header file */
|
||||
#elif defined CMSDK_CM7
|
||||
#include "CMSDK_CM7.h" /* device specific header file */
|
||||
#elif defined CMSDK_BEID
|
||||
#include "CMSDK_BEID.h" /* device specific header file */
|
||||
#else
|
||||
#warning "no appropriate header file found!"
|
||||
#endif
|
||||
|
||||
#endif /* __DEVICE_H */
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/**************************************************************************//**
|
||||
* @file system_CMSDK_BEID.c
|
||||
* @brief CMSIS Device System Source File for
|
||||
* CMSDK_M3 Device
|
||||
* @version V3.02
|
||||
* @date 15. November 2013
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2011 - 2013 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#include "CMSDK_BEID.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __XTAL (50000000UL) /* Oscillator frequency */
|
||||
|
||||
#define __SYSTEM_CLOCK (__XTAL / 2)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
|
||||
#ifdef UNALIGNED_SUPPORT_DISABLE
|
||||
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
|
||||
#endif
|
||||
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
|
||||
// Enable AHB and APB clock
|
||||
CMSDK_SYSCON->AHBCLKCFG0SET = 0xF; // GPIO
|
||||
CMSDK_SYSCON->APBCLKCFG0SET = 0x37; // UART0, UART1, TIMER0, TIMER1, DUAL TIMER
|
||||
}
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
/**************************************************************************//**
|
||||
* @file system_CMSDK_BEID.h
|
||||
* @brief CMSIS Device Peripheral Access Layer Header File for
|
||||
* CMSDK_BEID Device
|
||||
* @version V3.02
|
||||
* @date 15. March 2013
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2011 - 2013 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef SYSTEM_CMSDK_BEID_H
|
||||
#define SYSTEM_CMSDK_BEID_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_CMSDK_BEID_H */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
;SAMD21G18A
|
||||
;256KB FLASH (0x40000) @ 0x000000000
|
||||
;2KB RAM (0x8000) @ 0x20000000
|
||||
|
||||
|
||||
;SAMD21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
|
||||
LR_IROM1 0x00000000 0x40000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
|
||||
RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,190 @@
|
|||
;/*****************************************************************************
|
||||
; * @file startup_SAMD21.s
|
||||
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
|
||||
; * Atmel SAMD21 Device Series
|
||||
; * @version V1.00
|
||||
; * @date 24. February 2014
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2014 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * @par
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * @par
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
__initial_sp EQU 0x20008000 ; Top of RAM
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD PM_Handler ; 0 Power Manager
|
||||
DCD SYSCTRL_Handler ; 1 System Control
|
||||
DCD WDT_Handler ; 2 Watchdog Timer
|
||||
DCD RTC_Handler ; 3 Real-Time Counter
|
||||
DCD EIC_Handler ; 4 External Interrupt Controller
|
||||
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
|
||||
DCD DMAC_Handler ; 6 Direct Memory Access Controller
|
||||
DCD USB_Handler ; 7 Universal Serial Bus
|
||||
DCD EVSYS_Handler ; 8 Event System Interface
|
||||
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
|
||||
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
|
||||
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
|
||||
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
|
||||
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
|
||||
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
|
||||
DCD TCC0_Handler ; 15 Timer Counter Control 0
|
||||
DCD TCC1_Handler ; 16 Timer Counter Control 1
|
||||
DCD TCC2_Handler ; 17 Timer Counter Control 2
|
||||
DCD TC3_Handler ; 18 Basic Timer Counter 0
|
||||
DCD TC4_Handler ; 19 Basic Timer Counter 1
|
||||
DCD TC5_Handler ; 20 Basic Timer Counter 2
|
||||
DCD TC6_Handler ; 21 Basic Timer Counter 3
|
||||
DCD TC7_Handler ; 22 Basic Timer Counter 4
|
||||
DCD ADC_Handler ; 23 Analog Digital Converter
|
||||
DCD AC_Handler ; 24 Analog Comparators
|
||||
DCD DAC_Handler ; 25 Digital Analog Converter
|
||||
DCD PTC_Handler ; 26 Peripheral Touch Controller
|
||||
DCD I2S_Handler ; 27 Inter-IC Sound Interface
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT PM_Handler [WEAK]
|
||||
EXPORT PM_Handler [WEAK]
|
||||
EXPORT SYSCTRL_Handler [WEAK]
|
||||
EXPORT WDT_Handler [WEAK]
|
||||
EXPORT RTC_Handler [WEAK]
|
||||
EXPORT EIC_Handler [WEAK]
|
||||
EXPORT NVMCTRL_Handler [WEAK]
|
||||
EXPORT DMAC_Handler [WEAK]
|
||||
EXPORT USB_Handler [WEAK]
|
||||
EXPORT EVSYS_Handler [WEAK]
|
||||
EXPORT SERCOM0_Handler [WEAK]
|
||||
EXPORT SERCOM1_Handler [WEAK]
|
||||
EXPORT SERCOM2_Handler [WEAK]
|
||||
EXPORT SERCOM3_Handler [WEAK]
|
||||
EXPORT SERCOM4_Handler [WEAK]
|
||||
EXPORT SERCOM5_Handler [WEAK]
|
||||
EXPORT TCC0_Handler [WEAK]
|
||||
EXPORT TCC1_Handler [WEAK]
|
||||
EXPORT TCC2_Handler [WEAK]
|
||||
EXPORT TC3_Handler [WEAK]
|
||||
EXPORT TC4_Handler [WEAK]
|
||||
EXPORT TC5_Handler [WEAK]
|
||||
EXPORT TC6_Handler [WEAK]
|
||||
EXPORT TC7_Handler [WEAK]
|
||||
EXPORT ADC_Handler [WEAK]
|
||||
EXPORT AC_Handler [WEAK]
|
||||
EXPORT DAC_Handler [WEAK]
|
||||
EXPORT PTC_Handler [WEAK]
|
||||
EXPORT I2S_Handler [WEAK]
|
||||
|
||||
PM_Handler
|
||||
SYSCTRL_Handler
|
||||
WDT_Handler
|
||||
RTC_Handler
|
||||
EIC_Handler
|
||||
NVMCTRL_Handler
|
||||
DMAC_Handler
|
||||
USB_Handler
|
||||
EVSYS_Handler
|
||||
SERCOM0_Handler
|
||||
SERCOM1_Handler
|
||||
SERCOM2_Handler
|
||||
SERCOM3_Handler
|
||||
SERCOM4_Handler
|
||||
SERCOM5_Handler
|
||||
TCC0_Handler
|
||||
TCC1_Handler
|
||||
TCC2_Handler
|
||||
TC3_Handler
|
||||
TC4_Handler
|
||||
TC5_Handler
|
||||
TC6_Handler
|
||||
TC7_Handler
|
||||
ADC_Handler
|
||||
AC_Handler
|
||||
DAC_Handler
|
||||
PTC_Handler
|
||||
I2S_Handler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
|
||||
{
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
;SAMD21G18A
|
||||
;256KB FLASH (0x40000) @ 0x000000000
|
||||
;2KB RAM (0x8000) @ 0x20000000
|
||||
|
||||
|
||||
;SAMD21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
|
||||
LR_IROM1 0x00000000 0x40000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
|
||||
RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,190 @@
|
|||
;/*****************************************************************************
|
||||
; * @file startup_SAMD21.s
|
||||
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
|
||||
; * Atmel SAMD21 Device Series
|
||||
; * @version V1.00
|
||||
; * @date 24. February 2014
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2014 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * @par
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * @par
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
__initial_sp EQU 0x20008000 ; Top of RAM
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD PM_Handler ; 0 Power Manager
|
||||
DCD SYSCTRL_Handler ; 1 System Control
|
||||
DCD WDT_Handler ; 2 Watchdog Timer
|
||||
DCD RTC_Handler ; 3 Real-Time Counter
|
||||
DCD EIC_Handler ; 4 External Interrupt Controller
|
||||
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
|
||||
DCD DMAC_Handler ; 6 Direct Memory Access Controller
|
||||
DCD USB_Handler ; 7 Universal Serial Bus
|
||||
DCD EVSYS_Handler ; 8 Event System Interface
|
||||
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
|
||||
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
|
||||
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
|
||||
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
|
||||
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
|
||||
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
|
||||
DCD TCC0_Handler ; 15 Timer Counter Control 0
|
||||
DCD TCC1_Handler ; 16 Timer Counter Control 1
|
||||
DCD TCC2_Handler ; 17 Timer Counter Control 2
|
||||
DCD TC3_Handler ; 18 Basic Timer Counter 0
|
||||
DCD TC4_Handler ; 19 Basic Timer Counter 1
|
||||
DCD TC5_Handler ; 20 Basic Timer Counter 2
|
||||
DCD TC6_Handler ; 21 Basic Timer Counter 3
|
||||
DCD TC7_Handler ; 22 Basic Timer Counter 4
|
||||
DCD ADC_Handler ; 23 Analog Digital Converter
|
||||
DCD AC_Handler ; 24 Analog Comparators
|
||||
DCD DAC_Handler ; 25 Digital Analog Converter
|
||||
DCD PTC_Handler ; 26 Peripheral Touch Controller
|
||||
DCD I2S_Handler ; 27 Inter-IC Sound Interface
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT PM_Handler [WEAK]
|
||||
EXPORT PM_Handler [WEAK]
|
||||
EXPORT SYSCTRL_Handler [WEAK]
|
||||
EXPORT WDT_Handler [WEAK]
|
||||
EXPORT RTC_Handler [WEAK]
|
||||
EXPORT EIC_Handler [WEAK]
|
||||
EXPORT NVMCTRL_Handler [WEAK]
|
||||
EXPORT DMAC_Handler [WEAK]
|
||||
EXPORT USB_Handler [WEAK]
|
||||
EXPORT EVSYS_Handler [WEAK]
|
||||
EXPORT SERCOM0_Handler [WEAK]
|
||||
EXPORT SERCOM1_Handler [WEAK]
|
||||
EXPORT SERCOM2_Handler [WEAK]
|
||||
EXPORT SERCOM3_Handler [WEAK]
|
||||
EXPORT SERCOM4_Handler [WEAK]
|
||||
EXPORT SERCOM5_Handler [WEAK]
|
||||
EXPORT TCC0_Handler [WEAK]
|
||||
EXPORT TCC1_Handler [WEAK]
|
||||
EXPORT TCC2_Handler [WEAK]
|
||||
EXPORT TC3_Handler [WEAK]
|
||||
EXPORT TC4_Handler [WEAK]
|
||||
EXPORT TC5_Handler [WEAK]
|
||||
EXPORT TC6_Handler [WEAK]
|
||||
EXPORT TC7_Handler [WEAK]
|
||||
EXPORT ADC_Handler [WEAK]
|
||||
EXPORT AC_Handler [WEAK]
|
||||
EXPORT DAC_Handler [WEAK]
|
||||
EXPORT PTC_Handler [WEAK]
|
||||
EXPORT I2S_Handler [WEAK]
|
||||
|
||||
PM_Handler
|
||||
SYSCTRL_Handler
|
||||
WDT_Handler
|
||||
RTC_Handler
|
||||
EIC_Handler
|
||||
NVMCTRL_Handler
|
||||
DMAC_Handler
|
||||
USB_Handler
|
||||
EVSYS_Handler
|
||||
SERCOM0_Handler
|
||||
SERCOM1_Handler
|
||||
SERCOM2_Handler
|
||||
SERCOM3_Handler
|
||||
SERCOM4_Handler
|
||||
SERCOM5_Handler
|
||||
TCC0_Handler
|
||||
TCC1_Handler
|
||||
TCC2_Handler
|
||||
TC3_Handler
|
||||
TC4_Handler
|
||||
TC5_Handler
|
||||
TC6_Handler
|
||||
TC7_Handler
|
||||
ADC_Handler
|
||||
AC_Handler
|
||||
DAC_Handler
|
||||
PTC_Handler
|
||||
I2S_Handler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
|
||||
{
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,118 @@
|
|||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY {
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
|
||||
ram (rwx) : ORIGIN = 0x20000000 + 0xB4, LENGTH = 0x00008000 - 0xB4
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS {
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate :
|
||||
AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
.heap (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__end__ = . ;
|
||||
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
}
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
;SAMD21J18A
|
||||
;256KB FLASH (0x40000) @ 0x000000000
|
||||
;2KB RAM (0x8000) @ 0x20000000
|
||||
|
||||
|
||||
;SAMD21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
|
||||
LR_IROM1 0x00000000 0x40000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
|
||||
RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,190 @@
|
|||
;/*****************************************************************************
|
||||
; * @file startup_SAMD21.s
|
||||
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
|
||||
; * Atmel SAMD21 Device Series
|
||||
; * @version V1.00
|
||||
; * @date 24. February 2014
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2014 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * @par
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * @par
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
__initial_sp EQU 0x20008000 ; Top of RAM
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD PM_Handler ; 0 Power Manager
|
||||
DCD SYSCTRL_Handler ; 1 System Control
|
||||
DCD WDT_Handler ; 2 Watchdog Timer
|
||||
DCD RTC_Handler ; 3 Real-Time Counter
|
||||
DCD EIC_Handler ; 4 External Interrupt Controller
|
||||
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
|
||||
DCD DMAC_Handler ; 6 Direct Memory Access Controller
|
||||
DCD USB_Handler ; 7 Universal Serial Bus
|
||||
DCD EVSYS_Handler ; 8 Event System Interface
|
||||
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
|
||||
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
|
||||
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
|
||||
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
|
||||
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
|
||||
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
|
||||
DCD TCC0_Handler ; 15 Timer Counter Control 0
|
||||
DCD TCC1_Handler ; 16 Timer Counter Control 1
|
||||
DCD TCC2_Handler ; 17 Timer Counter Control 2
|
||||
DCD TC3_Handler ; 18 Basic Timer Counter 0
|
||||
DCD TC4_Handler ; 19 Basic Timer Counter 1
|
||||
DCD TC5_Handler ; 20 Basic Timer Counter 2
|
||||
DCD TC6_Handler ; 21 Basic Timer Counter 3
|
||||
DCD TC7_Handler ; 22 Basic Timer Counter 4
|
||||
DCD ADC_Handler ; 23 Analog Digital Converter
|
||||
DCD AC_Handler ; 24 Analog Comparators
|
||||
DCD DAC_Handler ; 25 Digital Analog Converter
|
||||
DCD PTC_Handler ; 26 Peripheral Touch Controller
|
||||
DCD I2S_Handler ; 27 Inter-IC Sound Interface
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT PM_Handler [WEAK]
|
||||
EXPORT PM_Handler [WEAK]
|
||||
EXPORT SYSCTRL_Handler [WEAK]
|
||||
EXPORT WDT_Handler [WEAK]
|
||||
EXPORT RTC_Handler [WEAK]
|
||||
EXPORT EIC_Handler [WEAK]
|
||||
EXPORT NVMCTRL_Handler [WEAK]
|
||||
EXPORT DMAC_Handler [WEAK]
|
||||
EXPORT USB_Handler [WEAK]
|
||||
EXPORT EVSYS_Handler [WEAK]
|
||||
EXPORT SERCOM0_Handler [WEAK]
|
||||
EXPORT SERCOM1_Handler [WEAK]
|
||||
EXPORT SERCOM2_Handler [WEAK]
|
||||
EXPORT SERCOM3_Handler [WEAK]
|
||||
EXPORT SERCOM4_Handler [WEAK]
|
||||
EXPORT SERCOM5_Handler [WEAK]
|
||||
EXPORT TCC0_Handler [WEAK]
|
||||
EXPORT TCC1_Handler [WEAK]
|
||||
EXPORT TCC2_Handler [WEAK]
|
||||
EXPORT TC3_Handler [WEAK]
|
||||
EXPORT TC4_Handler [WEAK]
|
||||
EXPORT TC5_Handler [WEAK]
|
||||
EXPORT TC6_Handler [WEAK]
|
||||
EXPORT TC7_Handler [WEAK]
|
||||
EXPORT ADC_Handler [WEAK]
|
||||
EXPORT AC_Handler [WEAK]
|
||||
EXPORT DAC_Handler [WEAK]
|
||||
EXPORT PTC_Handler [WEAK]
|
||||
EXPORT I2S_Handler [WEAK]
|
||||
|
||||
PM_Handler
|
||||
SYSCTRL_Handler
|
||||
WDT_Handler
|
||||
RTC_Handler
|
||||
EIC_Handler
|
||||
NVMCTRL_Handler
|
||||
DMAC_Handler
|
||||
USB_Handler
|
||||
EVSYS_Handler
|
||||
SERCOM0_Handler
|
||||
SERCOM1_Handler
|
||||
SERCOM2_Handler
|
||||
SERCOM3_Handler
|
||||
SERCOM4_Handler
|
||||
SERCOM5_Handler
|
||||
TCC0_Handler
|
||||
TCC1_Handler
|
||||
TCC2_Handler
|
||||
TC3_Handler
|
||||
TC4_Handler
|
||||
TC5_Handler
|
||||
TC6_Handler
|
||||
TC7_Handler
|
||||
ADC_Handler
|
||||
AC_Handler
|
||||
DAC_Handler
|
||||
PTC_Handler
|
||||
I2S_Handler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
|
||||
{
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
;SAMD21J18A
|
||||
;256KB FLASH (0x40000) @ 0x000000000
|
||||
;2KB RAM (0x8000) @ 0x20000000
|
||||
|
||||
|
||||
;SAMD21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
|
||||
LR_IROM1 0x00000000 0x40000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
|
||||
RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,190 @@
|
|||
;/*****************************************************************************
|
||||
; * @file startup_SAMD21.s
|
||||
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
|
||||
; * Atmel SAMD21 Device Series
|
||||
; * @version V1.00
|
||||
; * @date 24. February 2014
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2014 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * @par
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * @par
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
__initial_sp EQU 0x20008000 ; Top of RAM
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD PM_Handler ; 0 Power Manager
|
||||
DCD SYSCTRL_Handler ; 1 System Control
|
||||
DCD WDT_Handler ; 2 Watchdog Timer
|
||||
DCD RTC_Handler ; 3 Real-Time Counter
|
||||
DCD EIC_Handler ; 4 External Interrupt Controller
|
||||
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
|
||||
DCD DMAC_Handler ; 6 Direct Memory Access Controller
|
||||
DCD USB_Handler ; 7 Universal Serial Bus
|
||||
DCD EVSYS_Handler ; 8 Event System Interface
|
||||
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
|
||||
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
|
||||
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
|
||||
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
|
||||
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
|
||||
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
|
||||
DCD TCC0_Handler ; 15 Timer Counter Control 0
|
||||
DCD TCC1_Handler ; 16 Timer Counter Control 1
|
||||
DCD TCC2_Handler ; 17 Timer Counter Control 2
|
||||
DCD TC3_Handler ; 18 Basic Timer Counter 0
|
||||
DCD TC4_Handler ; 19 Basic Timer Counter 1
|
||||
DCD TC5_Handler ; 20 Basic Timer Counter 2
|
||||
DCD TC6_Handler ; 21 Basic Timer Counter 3
|
||||
DCD TC7_Handler ; 22 Basic Timer Counter 4
|
||||
DCD ADC_Handler ; 23 Analog Digital Converter
|
||||
DCD AC_Handler ; 24 Analog Comparators
|
||||
DCD DAC_Handler ; 25 Digital Analog Converter
|
||||
DCD PTC_Handler ; 26 Peripheral Touch Controller
|
||||
DCD I2S_Handler ; 27 Inter-IC Sound Interface
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT PM_Handler [WEAK]
|
||||
EXPORT PM_Handler [WEAK]
|
||||
EXPORT SYSCTRL_Handler [WEAK]
|
||||
EXPORT WDT_Handler [WEAK]
|
||||
EXPORT RTC_Handler [WEAK]
|
||||
EXPORT EIC_Handler [WEAK]
|
||||
EXPORT NVMCTRL_Handler [WEAK]
|
||||
EXPORT DMAC_Handler [WEAK]
|
||||
EXPORT USB_Handler [WEAK]
|
||||
EXPORT EVSYS_Handler [WEAK]
|
||||
EXPORT SERCOM0_Handler [WEAK]
|
||||
EXPORT SERCOM1_Handler [WEAK]
|
||||
EXPORT SERCOM2_Handler [WEAK]
|
||||
EXPORT SERCOM3_Handler [WEAK]
|
||||
EXPORT SERCOM4_Handler [WEAK]
|
||||
EXPORT SERCOM5_Handler [WEAK]
|
||||
EXPORT TCC0_Handler [WEAK]
|
||||
EXPORT TCC1_Handler [WEAK]
|
||||
EXPORT TCC2_Handler [WEAK]
|
||||
EXPORT TC3_Handler [WEAK]
|
||||
EXPORT TC4_Handler [WEAK]
|
||||
EXPORT TC5_Handler [WEAK]
|
||||
EXPORT TC6_Handler [WEAK]
|
||||
EXPORT TC7_Handler [WEAK]
|
||||
EXPORT ADC_Handler [WEAK]
|
||||
EXPORT AC_Handler [WEAK]
|
||||
EXPORT DAC_Handler [WEAK]
|
||||
EXPORT PTC_Handler [WEAK]
|
||||
EXPORT I2S_Handler [WEAK]
|
||||
|
||||
PM_Handler
|
||||
SYSCTRL_Handler
|
||||
WDT_Handler
|
||||
RTC_Handler
|
||||
EIC_Handler
|
||||
NVMCTRL_Handler
|
||||
DMAC_Handler
|
||||
USB_Handler
|
||||
EVSYS_Handler
|
||||
SERCOM0_Handler
|
||||
SERCOM1_Handler
|
||||
SERCOM2_Handler
|
||||
SERCOM3_Handler
|
||||
SERCOM4_Handler
|
||||
SERCOM5_Handler
|
||||
TCC0_Handler
|
||||
TCC1_Handler
|
||||
TCC2_Handler
|
||||
TC3_Handler
|
||||
TC4_Handler
|
||||
TC5_Handler
|
||||
TC6_Handler
|
||||
TC7_Handler
|
||||
ADC_Handler
|
||||
AC_Handler
|
||||
DAC_Handler
|
||||
PTC_Handler
|
||||
I2S_Handler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
|
||||
{
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -3,18 +3,16 @@ OUTPUT_ARCH(arm)
|
|||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
MEMORY {
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
|
||||
ram (rwx) : ORIGIN = 0x20000000 + 0xB4, LENGTH = 0x00008000 - 0xB4
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
SECTIONS {
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
|
|
@ -75,14 +73,8 @@ SECTIONS
|
|||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.dvectors (NOLOAD) :
|
||||
{
|
||||
_sdvectors = .;
|
||||
. = . + 0xB0;
|
||||
_edvectors = .;
|
||||
} > ram
|
||||
|
||||
.relocate : AT (_etext)
|
||||
.relocate :
|
||||
AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
#include "samd21.h"
|
||||
|
||||
/* Initialize segments */
|
||||
extern uint32_t _sfixed;
|
||||
extern uint32_t _efixed;
|
||||
extern uint32_t _etext;
|
||||
extern uint32_t _srelocate;
|
||||
extern uint32_t _erelocate;
|
||||
extern uint32_t _szero;
|
||||
extern uint32_t _ezero;
|
||||
extern uint32_t _sstack;
|
||||
extern uint32_t _estack;
|
||||
|
||||
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
|
||||
int main(void);
|
||||
/** \endcond */
|
||||
|
||||
void __libc_init_array(void);
|
||||
|
||||
/* Default empty handler */
|
||||
void Dummy_Handler(void);
|
||||
|
||||
/* Cortex-M0+ core handlers */
|
||||
void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
|
||||
/* Exception Table */
|
||||
__attribute__ ((section(".vectors")))
|
||||
const DeviceVectors exception_table = {
|
||||
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
(void*) (&_estack),
|
||||
|
||||
(void*) Reset_Handler,
|
||||
(void*) NMI_Handler,
|
||||
(void*) HardFault_Handler,
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) SVC_Handler,
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) PendSV_Handler,
|
||||
(void*) SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
(void*) PM_Handler, /* 0 Power Manager */
|
||||
(void*) SYSCTRL_Handler, /* 1 System Control */
|
||||
(void*) WDT_Handler, /* 2 Watchdog Timer */
|
||||
(void*) RTC_Handler, /* 3 Real-Time Counter */
|
||||
(void*) EIC_Handler, /* 4 External Interrupt Controller */
|
||||
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
|
||||
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
|
||||
(void*) USB_Handler, /* 7 Universal Serial Bus */
|
||||
(void*) EVSYS_Handler, /* 8 Event System Interface */
|
||||
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
|
||||
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
|
||||
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
|
||||
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
|
||||
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
|
||||
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
|
||||
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
|
||||
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
|
||||
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
|
||||
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
|
||||
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
|
||||
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
|
||||
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
|
||||
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
|
||||
(void*) ADC_Handler, /* 23 Analog Digital Converter */
|
||||
(void*) AC_Handler, /* 24 Analog Comparators */
|
||||
(void*) DAC_Handler, /* 25 Digital Analog Converter */
|
||||
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
|
||||
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief This is the code that gets called on processor reset.
|
||||
* To initialize the device, and call the main() routine.
|
||||
*/
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
uint32_t *pSrc, *pDest;
|
||||
|
||||
/* Initialize the relocate segment */
|
||||
pSrc = &_etext;
|
||||
pDest = &_srelocate;
|
||||
|
||||
if (pSrc != pDest) {
|
||||
for (; pDest < &_erelocate;) {
|
||||
*pDest++ = *pSrc++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear the zero segment */
|
||||
for (pDest = &_szero; pDest < &_ezero;) {
|
||||
*pDest++ = 0;
|
||||
}
|
||||
|
||||
/* Set the vector table base address */
|
||||
pSrc = (uint32_t *) & _sfixed;
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
/* Initialize the C library */
|
||||
__libc_init_array();
|
||||
|
||||
/* Branch to main function */ // expected to be done by MBED OS
|
||||
main();
|
||||
|
||||
/* Infinite loop */
|
||||
while (1);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Default interrupt handler for unused IRQs.
|
||||
*/
|
||||
void Dummy_Handler(void)
|
||||
{
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
#include "samd21.h"
|
||||
|
||||
void __iar_program_start(void);
|
||||
int __low_level_init(void);
|
||||
|
||||
void Dummy_Handler(void);
|
||||
void Reset_Handler(void);
|
||||
|
||||
/**
|
||||
* \brief Default interrupt handler for unused IRQs.
|
||||
*/
|
||||
void Dummy_Handler(void)
|
||||
{
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* Cortex-M0+ core handlers */
|
||||
void NMI_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void SVC_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void SYSCTRL_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_Handler ( void );
|
||||
void NVMCTRL_Handler ( void );
|
||||
void DMAC_Handler ( void );
|
||||
void USB_Handler ( void );
|
||||
void EVSYS_Handler ( void );
|
||||
void SERCOM0_Handler ( void );
|
||||
void SERCOM1_Handler ( void );
|
||||
void SERCOM2_Handler ( void );
|
||||
void SERCOM3_Handler ( void );
|
||||
void SERCOM4_Handler ( void );
|
||||
void SERCOM5_Handler ( void );
|
||||
void TCC0_Handler ( void );
|
||||
void TCC1_Handler ( void );
|
||||
void TCC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void TC4_Handler ( void );
|
||||
void TC5_Handler ( void );
|
||||
void TC6_Handler ( void );
|
||||
void TC7_Handler ( void );
|
||||
void ADC_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_Handler ( void );
|
||||
void PTC_Handler ( void );
|
||||
void I2S_Handler ( void );
|
||||
|
||||
/* Cortex-M0+ core handlers */
|
||||
#pragma weak NMI_Handler = Dummy_Handler
|
||||
#pragma weak HardFault_Handler = Dummy_Handler
|
||||
#pragma weak SVC_Handler = Dummy_Handler
|
||||
#pragma weak PendSV_Handler = Dummy_Handler
|
||||
#pragma weak SysTick_Handler = Dummy_Handler
|
||||
|
||||
/* Peripherals handlers */
|
||||
#pragma weak PM_Handler = Dummy_Handler
|
||||
#pragma weak SYSCTRL_Handler = Dummy_Handler
|
||||
#pragma weak WDT_Handler = Dummy_Handler
|
||||
#pragma weak RTC_Handler = Dummy_Handler
|
||||
#pragma weak EIC_Handler = Dummy_Handler
|
||||
#pragma weak NVMCTRL_Handler = Dummy_Handler
|
||||
#pragma weak DMAC_Handler = Dummy_Handler
|
||||
#pragma weak USB_Handler = Dummy_Handler
|
||||
#pragma weak EVSYS_Handler = Dummy_Handler
|
||||
#pragma weak SERCOM0_Handler = Dummy_Handler
|
||||
#pragma weak SERCOM1_Handler = Dummy_Handler
|
||||
#pragma weak SERCOM2_Handler = Dummy_Handler
|
||||
#pragma weak SERCOM3_Handler = Dummy_Handler
|
||||
#pragma weak SERCOM4_Handler = Dummy_Handler
|
||||
#pragma weak SERCOM5_Handler = Dummy_Handler
|
||||
#pragma weak TCC0_Handler = Dummy_Handler
|
||||
#pragma weak TCC1_Handler = Dummy_Handler
|
||||
#pragma weak TCC2_Handler = Dummy_Handler
|
||||
#pragma weak TC3_Handler = Dummy_Handler
|
||||
#pragma weak TC4_Handler = Dummy_Handler
|
||||
#pragma weak TC5_Handler = Dummy_Handler
|
||||
#pragma weak TC6_Handler = Dummy_Handler
|
||||
#pragma weak TC7_Handler = Dummy_Handler
|
||||
#pragma weak ADC_Handler = Dummy_Handler
|
||||
#pragma weak AC_Handler = Dummy_Handler
|
||||
#pragma weak DAC_Handler = Dummy_Handler
|
||||
#pragma weak PTC_Handler = Dummy_Handler
|
||||
#pragma weak I2S_Handler = Dummy_Handler
|
||||
|
||||
/* Exception Table */
|
||||
#pragma language=extended
|
||||
#pragma segment="CSTACK"
|
||||
|
||||
/* The name "__vector_table" has special meaning for C-SPY: */
|
||||
/* it is where the SP start value is found, and the NVIC vector */
|
||||
/* table register (VTOR) is initialized to this address if != 0 */
|
||||
|
||||
#pragma section = ".intvec"
|
||||
#pragma location = ".intvec"
|
||||
//! [startup_vector_table]
|
||||
const DeviceVectors __vector_table[] = {
|
||||
__sfe("CSTACK"),
|
||||
(void*) __iar_program_start,
|
||||
(void*) NMI_Handler,
|
||||
(void*) HardFault_Handler,
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) SVC_Handler,
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) PendSV_Handler,
|
||||
(void*) SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
(void*) PM_Handler, /* 0 Power Manager */
|
||||
(void*) SYSCTRL_Handler, /* 1 System Control */
|
||||
(void*) WDT_Handler, /* 2 Watchdog Timer */
|
||||
(void*) RTC_Handler, /* 3 Real-Time Counter */
|
||||
(void*) EIC_Handler, /* 4 External Interrupt Controller */
|
||||
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
|
||||
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
|
||||
(void*) USB_Handler, /* 7 Universal Serial Bus */
|
||||
(void*) EVSYS_Handler, /* 8 Event System Interface */
|
||||
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
|
||||
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
|
||||
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
|
||||
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
|
||||
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
|
||||
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
|
||||
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
|
||||
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
|
||||
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
|
||||
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
|
||||
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
|
||||
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
|
||||
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
|
||||
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
|
||||
(void*) ADC_Handler, /* 23 Analog Digital Converter */
|
||||
(void*) AC_Handler, /* 24 Analog Comparators */
|
||||
(void*) DAC_Handler, /* 25 Digital Analog Converter */
|
||||
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
|
||||
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
|
||||
};
|
||||
//! [startup_vector_table]
|
||||
|
||||
/**------------------------------------------------------------------------------
|
||||
* This is the code that gets called on processor reset. To initialize the
|
||||
* device.
|
||||
*------------------------------------------------------------------------------*/
|
||||
int __low_level_init(void)
|
||||
{
|
||||
uint32_t *pSrc = __section_begin(".intvec");
|
||||
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
return 1; /* if return 0, the data sections will not be initialized */
|
||||
}
|
||||
|
||||
/**------------------------------------------------------------------------------
|
||||
* This is the code that gets called on processor reset. To initialize the
|
||||
* device.
|
||||
*------------------------------------------------------------------------------*/
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
__iar_program_start();
|
||||
}
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
;
|
||||
SAML21J18A
|
||||
;
|
||||
256KB FLASH (0x40000) @ 0x000000000
|
||||
;
|
||||
2KB RAM (0x8000) @ 0x20000000
|
||||
|
||||
|
||||
;
|
||||
SAML21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
|
||||
LR_IROM1 0x00000000 0x40000 { ;
|
||||
load region size_region
|
||||
ER_IROM1 0x00000000 0x40000 { ;
|
||||
load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
;
|
||||
[RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
|
||||
RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4)
|
||||
{
|
||||
;
|
||||
RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,194 @@
|
|||
;/**************************************************************************//**
|
||||
; * @file startup_SAML21.s
|
||||
; * @brief CMSIS Cortex-M4 Core Device Startup File for
|
||||
; * Atmel SAML21 Device Series
|
||||
; * @version V1.00
|
||||
; * @date 10. February 2015
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2015 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * @par
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * @par
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
__initial_sp EQU 0x20008000 ;Top of RAM
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
;Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ;Top of Stack
|
||||
DCD Reset_Handler ;Reset Handler
|
||||
DCD NMI_Handler ;NMI Handler
|
||||
DCD HardFault_Handler ;Hard Fault Handler
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD SVC_Handler ;SVCall Handler
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD PendSV_Handler ;PendSV Handler
|
||||
DCD SysTick_Handler ;SysTick Handler
|
||||
|
||||
;External Interrupts
|
||||
DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator
|
||||
DCD WDT_Handler ;1 Watchdog Timer
|
||||
DCD RTC_Handler ;2 Real-Time Counter
|
||||
DCD EIC_Handler ;3 External Interrupt Controller
|
||||
DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller
|
||||
DCD DMAC_Handler ;5 Direct Memory Access Controller
|
||||
DCD USB_Handler ;6 Universal Serial Bus
|
||||
DCD EVSYS_Handler ;7 Event System Interface
|
||||
DCD SERCOM0_Handler ;8 Serial Communication Interface 0
|
||||
DCD SERCOM1_Handler ;9 Serial Communication Interface 1
|
||||
DCD SERCOM2_Handler ;10 Serial Communication Interface 2
|
||||
DCD SERCOM3_Handler ;11 Serial Communication Interface 3
|
||||
DCD SERCOM4_Handler ;12 Serial Communication Interface 4
|
||||
DCD SERCOM5_Handler ;13 Serial Communication Interface 5
|
||||
DCD TCC0_Handler ;14 Timer Counter Control 0
|
||||
DCD TCC1_Handler ;15 Timer Counter Control 1
|
||||
DCD TCC2_Handler ;16 Timer Counter Control 2
|
||||
DCD TC0_Handler ;17 Basic Timer Counter 0
|
||||
DCD TC1_Handler ;18 Basic Timer Counter 1
|
||||
DCD TC2_Handler ;19 Basic Timer Counter 2
|
||||
DCD TC3_Handler ;20 Basic Timer Counter 3
|
||||
DCD TC4_Handler ;21 Basic Timer Counter 4
|
||||
DCD ADC_Handler ;22 Analog Digital Converter
|
||||
DCD AC_Handler ;23 Analog Comparators
|
||||
DCD DAC_Handler ;24 Digital-to-Analog Converter
|
||||
DCD PTC_Handler ;25 Peripheral Touch Controller
|
||||
DCD AES_Handler ;26 Advanced Encryption Standard
|
||||
DCD TRNG_Handler ;27 True Random Generator
|
||||
DCD PICOP_Handler ;28 PicoProcessor
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
;Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
;Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT SYSTEM_Handler [WEAK]
|
||||
EXPORT WDT_Handler [WEAK]
|
||||
EXPORT RTC_Handler [WEAK]
|
||||
EXPORT EIC_Handler [WEAK]
|
||||
EXPORT NVMCTRL_Handler [WEAK]
|
||||
EXPORT DMAC_Handler [WEAK]
|
||||
EXPORT USB_Handler [WEAK]
|
||||
EXPORT EVSYS_Handler [WEAK]
|
||||
EXPORT SERCOM0_Handler [WEAK]
|
||||
EXPORT SERCOM1_Handler [WEAK]
|
||||
EXPORT SERCOM2_Handler [WEAK]
|
||||
EXPORT SERCOM3_Handler [WEAK]
|
||||
EXPORT SERCOM4_Handler [WEAK]
|
||||
EXPORT SERCOM5_Handler [WEAK]
|
||||
EXPORT TCC0_Handler [WEAK]
|
||||
EXPORT TCC1_Handler [WEAK]
|
||||
EXPORT TCC2_Handler [WEAK]
|
||||
EXPORT TC0_Handler [WEAK]
|
||||
EXPORT TC1_Handler [WEAK]
|
||||
EXPORT TC2_Handler [WEAK]
|
||||
EXPORT TC3_Handler [WEAK]
|
||||
EXPORT TC4_Handler [WEAK]
|
||||
EXPORT ADC_Handler [WEAK]
|
||||
EXPORT AC_Handler [WEAK]
|
||||
EXPORT DAC_Handler [WEAK]
|
||||
EXPORT PTC_Handler [WEAK]
|
||||
EXPORT AES_Handler [WEAK]
|
||||
EXPORT TRNG_Handler [WEAK]
|
||||
EXPORT PICOP_Handler [WEAK]
|
||||
|
||||
SYSTEM_Handler
|
||||
WDT_Handler
|
||||
RTC_Handler
|
||||
EIC_Handler
|
||||
NVMCTRL_Handler
|
||||
DMAC_Handler
|
||||
USB_Handler
|
||||
EVSYS_Handler
|
||||
SERCOM0_Handler
|
||||
SERCOM1_Handler
|
||||
SERCOM2_Handler
|
||||
SERCOM3_Handler
|
||||
SERCOM4_Handler
|
||||
SERCOM5_Handler
|
||||
TCC0_Handler
|
||||
TCC1_Handler
|
||||
TCC2_Handler
|
||||
TC0_Handler
|
||||
TC1_Handler
|
||||
TC2_Handler
|
||||
TC3_Handler
|
||||
TC4_Handler
|
||||
ADC_Handler
|
||||
AC_Handler
|
||||
DAC_Handler
|
||||
PTC_Handler
|
||||
AES_Handler
|
||||
TRNG_Handler
|
||||
PICOP_Handler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
|
||||
{
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
;
|
||||
SAML21J18A
|
||||
;
|
||||
256KB FLASH (0x40000) @ 0x000000000
|
||||
;
|
||||
2KB RAM (0x8000) @ 0x20000000
|
||||
|
||||
|
||||
;
|
||||
SAML21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
|
||||
LR_IROM1 0x00000000 0x40000 { ;
|
||||
load region size_region
|
||||
ER_IROM1 0x00000000 0x40000 { ;
|
||||
load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
;
|
||||
[RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
|
||||
RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4)
|
||||
{
|
||||
;
|
||||
RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,194 @@
|
|||
;/**************************************************************************//**
|
||||
; * @file startup_SAML21.s
|
||||
; * @brief CMSIS Cortex-M4 Core Device Startup File for
|
||||
; * Atmel SAML21 Device Series
|
||||
; * @version V1.00
|
||||
; * @date 10. February 2015
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2015 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * @par
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * @par
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
__initial_sp EQU 0x20008000 ;Top of RAM
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
;Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ;Top of Stack
|
||||
DCD Reset_Handler ;Reset Handler
|
||||
DCD NMI_Handler ;NMI Handler
|
||||
DCD HardFault_Handler ;Hard Fault Handler
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD SVC_Handler ;SVCall Handler
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD PendSV_Handler ;PendSV Handler
|
||||
DCD SysTick_Handler ;SysTick Handler
|
||||
|
||||
;External Interrupts
|
||||
DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator
|
||||
DCD WDT_Handler ;1 Watchdog Timer
|
||||
DCD RTC_Handler ;2 Real-Time Counter
|
||||
DCD EIC_Handler ;3 External Interrupt Controller
|
||||
DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller
|
||||
DCD DMAC_Handler ;5 Direct Memory Access Controller
|
||||
DCD USB_Handler ;6 Universal Serial Bus
|
||||
DCD EVSYS_Handler ;7 Event System Interface
|
||||
DCD SERCOM0_Handler ;8 Serial Communication Interface 0
|
||||
DCD SERCOM1_Handler ;9 Serial Communication Interface 1
|
||||
DCD SERCOM2_Handler ;10 Serial Communication Interface 2
|
||||
DCD SERCOM3_Handler ;11 Serial Communication Interface 3
|
||||
DCD SERCOM4_Handler ;12 Serial Communication Interface 4
|
||||
DCD SERCOM5_Handler ;13 Serial Communication Interface 5
|
||||
DCD TCC0_Handler ;14 Timer Counter Control 0
|
||||
DCD TCC1_Handler ;15 Timer Counter Control 1
|
||||
DCD TCC2_Handler ;16 Timer Counter Control 2
|
||||
DCD TC0_Handler ;17 Basic Timer Counter 0
|
||||
DCD TC1_Handler ;18 Basic Timer Counter 1
|
||||
DCD TC2_Handler ;19 Basic Timer Counter 2
|
||||
DCD TC3_Handler ;20 Basic Timer Counter 3
|
||||
DCD TC4_Handler ;21 Basic Timer Counter 4
|
||||
DCD ADC_Handler ;22 Analog Digital Converter
|
||||
DCD AC_Handler ;23 Analog Comparators
|
||||
DCD DAC_Handler ;24 Digital-to-Analog Converter
|
||||
DCD PTC_Handler ;25 Peripheral Touch Controller
|
||||
DCD AES_Handler ;26 Advanced Encryption Standard
|
||||
DCD TRNG_Handler ;27 True Random Generator
|
||||
DCD PICOP_Handler ;28 PicoProcessor
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
;Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
;Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT SYSTEM_Handler [WEAK]
|
||||
EXPORT WDT_Handler [WEAK]
|
||||
EXPORT RTC_Handler [WEAK]
|
||||
EXPORT EIC_Handler [WEAK]
|
||||
EXPORT NVMCTRL_Handler [WEAK]
|
||||
EXPORT DMAC_Handler [WEAK]
|
||||
EXPORT USB_Handler [WEAK]
|
||||
EXPORT EVSYS_Handler [WEAK]
|
||||
EXPORT SERCOM0_Handler [WEAK]
|
||||
EXPORT SERCOM1_Handler [WEAK]
|
||||
EXPORT SERCOM2_Handler [WEAK]
|
||||
EXPORT SERCOM3_Handler [WEAK]
|
||||
EXPORT SERCOM4_Handler [WEAK]
|
||||
EXPORT SERCOM5_Handler [WEAK]
|
||||
EXPORT TCC0_Handler [WEAK]
|
||||
EXPORT TCC1_Handler [WEAK]
|
||||
EXPORT TCC2_Handler [WEAK]
|
||||
EXPORT TC0_Handler [WEAK]
|
||||
EXPORT TC1_Handler [WEAK]
|
||||
EXPORT TC2_Handler [WEAK]
|
||||
EXPORT TC3_Handler [WEAK]
|
||||
EXPORT TC4_Handler [WEAK]
|
||||
EXPORT ADC_Handler [WEAK]
|
||||
EXPORT AC_Handler [WEAK]
|
||||
EXPORT DAC_Handler [WEAK]
|
||||
EXPORT PTC_Handler [WEAK]
|
||||
EXPORT AES_Handler [WEAK]
|
||||
EXPORT TRNG_Handler [WEAK]
|
||||
EXPORT PICOP_Handler [WEAK]
|
||||
|
||||
SYSTEM_Handler
|
||||
WDT_Handler
|
||||
RTC_Handler
|
||||
EIC_Handler
|
||||
NVMCTRL_Handler
|
||||
DMAC_Handler
|
||||
USB_Handler
|
||||
EVSYS_Handler
|
||||
SERCOM0_Handler
|
||||
SERCOM1_Handler
|
||||
SERCOM2_Handler
|
||||
SERCOM3_Handler
|
||||
SERCOM4_Handler
|
||||
SERCOM5_Handler
|
||||
TCC0_Handler
|
||||
TCC1_Handler
|
||||
TCC2_Handler
|
||||
TC0_Handler
|
||||
TC1_Handler
|
||||
TC2_Handler
|
||||
TC3_Handler
|
||||
TC4_Handler
|
||||
ADC_Handler
|
||||
AC_Handler
|
||||
DAC_Handler
|
||||
PTC_Handler
|
||||
AES_Handler
|
||||
TRNG_Handler
|
||||
PICOP_Handler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
|
||||
{
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,118 @@
|
|||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY {
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
|
||||
ram (rwx) : ORIGIN = 0x20000000 + 0xB4, LENGTH = 0x00008000 - 0xB4
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS {
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate :
|
||||
AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
.heap (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__end__ = . ;
|
||||
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
}
|
||||
|
|
@ -0,0 +1,281 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief gcc starttup file for SAML21
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#include "saml21.h"
|
||||
|
||||
/* Initialize segments */
|
||||
extern uint32_t _sfixed;
|
||||
extern uint32_t _efixed;
|
||||
extern uint32_t _etext;
|
||||
extern uint32_t _srelocate;
|
||||
extern uint32_t _erelocate;
|
||||
extern uint32_t _szero;
|
||||
extern uint32_t _ezero;
|
||||
extern uint32_t _sstack;
|
||||
extern uint32_t _estack;
|
||||
|
||||
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
|
||||
int main(void);
|
||||
/** \endcond */
|
||||
|
||||
void __libc_init_array(void);
|
||||
|
||||
/* Default empty handler */
|
||||
void Dummy_Handler(void);
|
||||
|
||||
/* Cortex-M0+ core handlers */
|
||||
void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
|
||||
/* Peripherals handlers */
|
||||
void SYSTEM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* MCLK, OSCCTRL, OSC32KCTRL, PAC, PM, SUPC, TAL */
|
||||
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_USB
|
||||
void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_SERCOM4
|
||||
void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_SERCOM5
|
||||
void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_TC2
|
||||
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_TC3
|
||||
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_ADC
|
||||
void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_AC
|
||||
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_DAC
|
||||
void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_PTC
|
||||
void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_AES
|
||||
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_TRNG
|
||||
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_PICOP
|
||||
void PICOP_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
|
||||
/* Exception Table */
|
||||
__attribute__ ((section(".vectors")))
|
||||
const DeviceVectors exception_table = {
|
||||
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
(void*) (&_estack),
|
||||
|
||||
(void*) Reset_Handler,
|
||||
(void*) NMI_Handler,
|
||||
(void*) HardFault_Handler,
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) SVC_Handler,
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) PendSV_Handler,
|
||||
(void*) SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
(void*) SYSTEM_Handler, /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
|
||||
(void*) WDT_Handler, /* 1 Watchdog Timer */
|
||||
(void*) RTC_Handler, /* 2 Real-Time Counter */
|
||||
(void*) EIC_Handler, /* 3 External Interrupt Controller */
|
||||
(void*) NVMCTRL_Handler, /* 4 Non-Volatile Memory Controller */
|
||||
(void*) DMAC_Handler, /* 5 Direct Memory Access Controller */
|
||||
#ifdef ID_USB
|
||||
(void*) USB_Handler, /* 6 Universal Serial Bus */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved */
|
||||
#endif
|
||||
(void*) EVSYS_Handler, /* 7 Event System Interface */
|
||||
(void*) SERCOM0_Handler, /* 8 Serial Communication Interface 0 */
|
||||
(void*) SERCOM1_Handler, /* 9 Serial Communication Interface 1 */
|
||||
(void*) SERCOM2_Handler, /* 10 Serial Communication Interface 2 */
|
||||
(void*) SERCOM3_Handler, /* 11 Serial Communication Interface 3 */
|
||||
#ifdef ID_SERCOM4
|
||||
(void*) SERCOM4_Handler, /* 12 Serial Communication Interface 4 */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM5
|
||||
(void*) SERCOM5_Handler, /* 13 Serial Communication Interface 5 */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved */
|
||||
#endif
|
||||
(void*) TCC0_Handler, /* 14 Timer Counter Control 0 */
|
||||
(void*) TCC1_Handler, /* 15 Timer Counter Control 1 */
|
||||
(void*) TCC2_Handler, /* 16 Timer Counter Control 2 */
|
||||
(void*) TC0_Handler, /* 17 Basic Timer Counter 0 */
|
||||
(void*) TC1_Handler, /* 18 Basic Timer Counter 1 */
|
||||
#ifdef ID_TC2
|
||||
(void*) TC2_Handler, /* 19 Basic Timer Counter 2 */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC3
|
||||
(void*) TC3_Handler, /* 20 Basic Timer Counter 3 */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved */
|
||||
#endif
|
||||
(void*) TC4_Handler, /* 21 Basic Timer Counter 4 */
|
||||
#ifdef ID_ADC
|
||||
(void*) ADC_Handler, /* 22 Analog Digital Converter */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved */
|
||||
#endif
|
||||
#ifdef ID_AC
|
||||
(void*) AC_Handler, /* 23 Analog Comparators */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved */
|
||||
#endif
|
||||
#ifdef ID_DAC
|
||||
(void*) DAC_Handler, /* 24 Digital-to-Analog Converter */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved */
|
||||
#endif
|
||||
#ifdef ID_PTC
|
||||
(void*) PTC_Handler, /* 25 Peripheral Touch Controller */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved */
|
||||
#endif
|
||||
#ifdef ID_AES
|
||||
(void*) AES_Handler, /* 26 Advanced Encryption Standard */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved */
|
||||
#endif
|
||||
#ifdef ID_TRNG
|
||||
(void*) TRNG_Handler, /* 27 True Random Generator */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved */
|
||||
#endif
|
||||
#ifdef ID_PICOP
|
||||
(void*) PICOP_Handler /* 28 PicoProcessor */
|
||||
#else
|
||||
(void*) (0UL) /* Reserved */
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief This is the code that gets called on processor reset.
|
||||
* To initialize the device, and call the main() routine.
|
||||
*/
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
uint32_t *pSrc, *pDest;
|
||||
|
||||
/* Initialize the relocate segment */
|
||||
pSrc = &_etext;
|
||||
pDest = &_srelocate;
|
||||
|
||||
if (pSrc != pDest) {
|
||||
for (; pDest < &_erelocate;) {
|
||||
*pDest++ = *pSrc++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear the zero segment */
|
||||
for (pDest = &_szero; pDest < &_ezero;) {
|
||||
*pDest++ = 0;
|
||||
}
|
||||
|
||||
/* Set the vector table base address */
|
||||
pSrc = (uint32_t *) & _sfixed;
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
/* Initialize the C library */
|
||||
__libc_init_array();
|
||||
|
||||
/* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
|
||||
NVMCTRL->CTRLB.bit.MANW = 1;
|
||||
|
||||
/* Branch to main function */
|
||||
main();
|
||||
|
||||
/* Infinite loop */
|
||||
while (1);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Default interrupt handler for unused IRQs.
|
||||
*/
|
||||
void Dummy_Handler(void)
|
||||
{
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,261 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#include "saml21.h"
|
||||
|
||||
typedef void (*intfunc) (void);
|
||||
typedef union {
|
||||
intfunc __fun;
|
||||
void * __ptr;
|
||||
} intvec_elem;
|
||||
|
||||
void __iar_program_start(void);
|
||||
int __low_level_init(void);
|
||||
|
||||
/* Default empty handler */
|
||||
void Dummy_Handler(void);
|
||||
|
||||
/* Cortex-M0+ core handlers */
|
||||
#pragma weak NMI_Handler = Dummy_Handler
|
||||
#pragma weak HardFault_Handler = Dummy_Handler
|
||||
#pragma weak SVC_Handler = Dummy_Handler
|
||||
#pragma weak PendSV_Handler = Dummy_Handler
|
||||
#pragma weak SysTick_Handler = Dummy_Handler
|
||||
|
||||
/* Peripherals handlers */
|
||||
#pragma weak SYSTEM_Handler = Dummy_Handler /* MCLK, OSCCTRL, OSC32KCTRL, PAC, PM, SUPC, TAL */
|
||||
#pragma weak WDT_Handler = Dummy_Handler
|
||||
#pragma weak RTC_Handler = Dummy_Handler
|
||||
#pragma weak EIC_Handler = Dummy_Handler
|
||||
#pragma weak NVMCTRL_Handler = Dummy_Handler
|
||||
#pragma weak DMAC_Handler = Dummy_Handler
|
||||
#ifdef ID_USB
|
||||
#pragma weak USB_Handler = Dummy_Handler
|
||||
#endif
|
||||
#pragma weak EVSYS_Handler = Dummy_Handler
|
||||
#pragma weak SERCOM0_Handler = Dummy_Handler
|
||||
#pragma weak SERCOM1_Handler = Dummy_Handler
|
||||
#pragma weak SERCOM2_Handler = Dummy_Handler
|
||||
#pragma weak SERCOM3_Handler = Dummy_Handler
|
||||
#ifdef ID_SERCOM4
|
||||
#pragma weak SERCOM4_Handler = Dummy_Handler
|
||||
#endif
|
||||
#ifdef ID_SERCOM5
|
||||
#pragma weak SERCOM5_Handler = Dummy_Handler
|
||||
#endif
|
||||
#pragma weak TCC0_Handler = Dummy_Handler
|
||||
#pragma weak TCC1_Handler = Dummy_Handler
|
||||
#pragma weak TCC2_Handler = Dummy_Handler
|
||||
#pragma weak TC0_Handler = Dummy_Handler
|
||||
#pragma weak TC1_Handler = Dummy_Handler
|
||||
#ifdef ID_TC2
|
||||
#pragma weak TC2_Handler = Dummy_Handler
|
||||
#endif
|
||||
#ifdef ID_TC3
|
||||
#pragma weak TC3_Handler = Dummy_Handler
|
||||
#endif
|
||||
#pragma weak TC4_Handler = Dummy_Handler
|
||||
#ifdef ID_ADC
|
||||
#pragma weak ADC_Handler = Dummy_Handler
|
||||
#endif
|
||||
#ifdef ID_AC
|
||||
#pragma weak AC_Handler = Dummy_Handler
|
||||
#endif
|
||||
#ifdef ID_DAC
|
||||
#pragma weak DAC_Handler = Dummy_Handler
|
||||
#endif
|
||||
#ifdef ID_PTC
|
||||
#pragma weak PTC_Handler = Dummy_Handler
|
||||
#endif
|
||||
#ifdef ID_AES
|
||||
#pragma weak AES_Handler = Dummy_Handler
|
||||
#endif
|
||||
#ifdef ID_TRNG
|
||||
#pragma weak TRNG_Handler = Dummy_Handler
|
||||
#endif
|
||||
#ifdef ID_PICOP
|
||||
#pragma weak PICOP_Handler = Dummy_Handler
|
||||
#endif
|
||||
|
||||
/* Exception Table */
|
||||
#pragma language = extended
|
||||
#pragma segment = "CSTACK"
|
||||
|
||||
/* The name "__vector_table" has special meaning for C-SPY: */
|
||||
/* it is where the SP start value is found, and the NVIC vector */
|
||||
/* table register (VTOR) is initialized to this address if != 0 */
|
||||
|
||||
#pragma section = ".intvec"
|
||||
#pragma location = ".intvec"
|
||||
const DeviceVectors __vector_table[] = {
|
||||
__sfe("CSTACK"),
|
||||
(void*) __iar_program_start,
|
||||
(void*) NMI_Handler,
|
||||
(void*) HardFault_Handler,
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) SVC_Handler,
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) PendSV_Handler,
|
||||
(void*) SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
(void*) SYSTEM_Handler, /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
|
||||
(void*) WDT_Handler, /* 1 Watchdog Timer */
|
||||
(void*) RTC_Handler, /* 2 Real-Time Counter */
|
||||
(void*) EIC_Handler, /* 3 External Interrupt Controller */
|
||||
(void*) NVMCTRL_Handler, /* 4 Non-Volatile Memory Controller */
|
||||
(void*) DMAC_Handler, /* 5 Direct Memory Access Controller */
|
||||
#ifdef ID_USB
|
||||
(void*) USB_Handler, /* 6 Universal Serial Bus */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved*/
|
||||
#endif
|
||||
(void*) EVSYS_Handler, /* 7 Event System Interface */
|
||||
(void*) SERCOM0_Handler, /* 8 Serial Communication Interface 0 */
|
||||
(void*) SERCOM1_Handler, /* 9 Serial Communication Interface 1 */
|
||||
(void*) SERCOM2_Handler, /* 10 Serial Communication Interface 2 */
|
||||
(void*) SERCOM3_Handler, /* 11 Serial Communication Interface 3 */
|
||||
#ifdef ID_SERCOM4
|
||||
(void*) SERCOM4_Handler, /* 12 Serial Communication Interface 4 */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved*/
|
||||
#endif
|
||||
#ifdef ID_SERCOM5
|
||||
(void*) SERCOM5_Handler, /* 13 Serial Communication Interface 5 */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved*/
|
||||
#endif
|
||||
(void*) TCC0_Handler, /* 14 Timer Counter Control 0 */
|
||||
(void*) TCC1_Handler, /* 15 Timer Counter Control 1 */
|
||||
(void*) TCC2_Handler, /* 16 Timer Counter Control 2 */
|
||||
(void*) TC0_Handler, /* 17 Basic Timer Counter 0 */
|
||||
(void*) TC1_Handler, /* 18 Basic Timer Counter 1 */
|
||||
#ifdef ID_TC2
|
||||
(void*) TC2_Handler, /* 19 Basic Timer Counter 2 */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved*/
|
||||
#endif
|
||||
#ifdef ID_TC3
|
||||
(void*) TC3_Handler, /* 20 Basic Timer Counter 3 */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved*/
|
||||
#endif
|
||||
(void*) TC4_Handler, /* 21 Basic Timer Counter 4 */
|
||||
#ifdef ID_ADC
|
||||
(void*) ADC_Handler, /* 22 Analog Digital Converter */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved*/
|
||||
#endif
|
||||
#ifdef ID_AC
|
||||
(void*) AC_Handler, /* 23 Analog Comparators */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved*/
|
||||
#endif
|
||||
#ifdef ID_DAC
|
||||
(void*) DAC_Handler, /* 24 Digital-to-Analog Converter */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved*/
|
||||
#endif
|
||||
#ifdef ID_PTC
|
||||
(void*) PTC_Handler, /* 25 Peripheral Touch Controller */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved*/
|
||||
#endif
|
||||
#ifdef ID_AES
|
||||
(void*) AES_Handler, /* 26 Advanced Encryption Standard */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved*/
|
||||
#endif
|
||||
#ifdef ID_TRNG
|
||||
(void*) TRNG_Handler, /* 27 True Random Generator */
|
||||
#else
|
||||
(void*) (0UL), /* Reserved*/
|
||||
#endif
|
||||
#ifdef ID_PICOP
|
||||
(void*) PICOP_Handler /* 28 PicoProcessor */
|
||||
#else
|
||||
(void*) (0UL) /* Reserved*/
|
||||
#endif
|
||||
};
|
||||
|
||||
/**------------------------------------------------------------------------------
|
||||
* This is the code that gets called on processor reset. To initialize the
|
||||
* device.
|
||||
*------------------------------------------------------------------------------*/
|
||||
int __low_level_init(void)
|
||||
{
|
||||
uint32_t *pSrc = __section_begin(".intvec");
|
||||
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
return 1; /* if return 0, the data sections will not be initialized */
|
||||
}
|
||||
|
||||
/**------------------------------------------------------------------------------
|
||||
* This is the code that gets called on processor reset. To initialize the
|
||||
* device.
|
||||
*------------------------------------------------------------------------------*/
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
/* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
|
||||
NVMCTRL->CTRLB.bit.MANW = 1;
|
||||
|
||||
__iar_program_start();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Default interrupt handler for unused IRQs.
|
||||
*/
|
||||
void Dummy_Handler(void)
|
||||
{
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
/* mbed Microcontroller Library - CMSIS
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* A generic CMSIS include header, pulling in samr21j18a specifics
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_H
|
||||
#define MBED_CMSIS_H
|
||||
|
||||
#include "saml21.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -30,8 +30,8 @@
|
|||
*/
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
//#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
||||
extern uint32_t _sdvectors;
|
||||
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
||||
//extern uint32_t _sdvectors;
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
|
|
@ -42,11 +42,11 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|||
// Copy and switch to dynamic vectors if the first time called
|
||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
||||
uint32_t *old_vectors = vectors;
|
||||
vectors = (uint32_t*)&_sdvectors;
|
||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
||||
vectors[i] = old_vectors[i];
|
||||
}
|
||||
SCB->VTOR = (uint32_t)&_sdvectors;
|
||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
||||
}
|
||||
vectors[IRQn + 16] = vector;
|
||||
}
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
/* mbed Microcontroller Library
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
#define NVIC_NUM_VECTORS (16 +29) // CORE + MCU Peripherals
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
;SAMR21G18A
|
||||
;256KB FLASH (0x40000) @ 0x000000000
|
||||
;2KB RAM (0x8000) @ 0x20000000
|
||||
|
||||
|
||||
;SAMR21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
|
||||
LR_IROM1 0x00000000 0x40000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment
|
||||
RW_IRAM1 (0x20000000+0xB0) (0x8000-0xB0) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,189 @@
|
|||
;/*****************************************************************************
|
||||
; * @file startup_SAMR21.s
|
||||
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
|
||||
; * Atmel SAMR21 Device Series
|
||||
; * @version V1.00
|
||||
; * @date 24. February 2014
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2014 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * @par
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * @par
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
__initial_sp EQU 0x20008000 ; Top of RAM
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD PM_Handler ; 0 Power Manager
|
||||
DCD SYSCTRL_Handler ; 1 System Control
|
||||
DCD WDT_Handler ; 2 Watchdog Timer
|
||||
DCD RTC_Handler ; 3 Real-Time Counter
|
||||
DCD EIC_Handler ; 4 External Interrupt Controller
|
||||
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
|
||||
DCD DMAC_Handler ; 6 Direct Memory Access Controller
|
||||
DCD USB_Handler ; 7 Universal Serial Bus
|
||||
DCD EVSYS_Handler ; 8 Event System Interface
|
||||
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
|
||||
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
|
||||
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
|
||||
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
|
||||
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
|
||||
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
|
||||
DCD TCC0_Handler ; 15 Timer Counter Control 0
|
||||
DCD TCC1_Handler ; 16 Timer Counter Control 1
|
||||
DCD TCC2_Handler ; 17 Timer Counter Control 2
|
||||
DCD TC3_Handler ; 18 Basic Timer Counter 0
|
||||
DCD TC4_Handler ; 19 Basic Timer Counter 1
|
||||
DCD TC5_Handler ; 20 Basic Timer Counter 2
|
||||
DCD TC6_Handler ; 21 Basic Timer Counter 3
|
||||
DCD TC7_Handler ; 22 Basic Timer Counter 4
|
||||
DCD ADC_Handler ; 23 Analog Digital Converter
|
||||
DCD AC_Handler ; 24 Analog Comparators
|
||||
DCD DAC_Handler ; 25 Digital Analog Converter
|
||||
DCD PTC_Handler ; 26 Peripheral Touch Controller
|
||||
DCD I2S_Handler ; 27 Inter-IC Sound Interface
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT PM_Handler [WEAK]
|
||||
EXPORT SYSCTRL_Handler [WEAK]
|
||||
EXPORT WDT_Handler [WEAK]
|
||||
EXPORT RTC_Handler [WEAK]
|
||||
EXPORT EIC_Handler [WEAK]
|
||||
EXPORT NVMCTRL_Handler [WEAK]
|
||||
EXPORT DMAC_Handler [WEAK]
|
||||
EXPORT USB_Handler [WEAK]
|
||||
EXPORT EVSYS_Handler [WEAK]
|
||||
EXPORT SERCOM0_Handler [WEAK]
|
||||
EXPORT SERCOM1_Handler [WEAK]
|
||||
EXPORT SERCOM2_Handler [WEAK]
|
||||
EXPORT SERCOM3_Handler [WEAK]
|
||||
EXPORT SERCOM4_Handler [WEAK]
|
||||
EXPORT SERCOM5_Handler [WEAK]
|
||||
EXPORT TCC0_Handler [WEAK]
|
||||
EXPORT TCC1_Handler [WEAK]
|
||||
EXPORT TCC2_Handler [WEAK]
|
||||
EXPORT TC3_Handler [WEAK]
|
||||
EXPORT TC4_Handler [WEAK]
|
||||
EXPORT TC5_Handler [WEAK]
|
||||
EXPORT TC6_Handler [WEAK]
|
||||
EXPORT TC7_Handler [WEAK]
|
||||
EXPORT ADC_Handler [WEAK]
|
||||
EXPORT AC_Handler [WEAK]
|
||||
EXPORT DAC_Handler [WEAK]
|
||||
EXPORT PTC_Handler [WEAK]
|
||||
EXPORT I2S_Handler [WEAK]
|
||||
|
||||
PM_Handler
|
||||
SYSCTRL_Handler
|
||||
WDT_Handler
|
||||
RTC_Handler
|
||||
EIC_Handler
|
||||
NVMCTRL_Handler
|
||||
DMAC_Handler
|
||||
USB_Handler
|
||||
EVSYS_Handler
|
||||
SERCOM0_Handler
|
||||
SERCOM1_Handler
|
||||
SERCOM2_Handler
|
||||
SERCOM3_Handler
|
||||
SERCOM4_Handler
|
||||
SERCOM5_Handler
|
||||
TCC0_Handler
|
||||
TCC1_Handler
|
||||
TCC2_Handler
|
||||
TC3_Handler
|
||||
TC4_Handler
|
||||
TC5_Handler
|
||||
TC6_Handler
|
||||
TC7_Handler
|
||||
ADC_Handler
|
||||
AC_Handler
|
||||
DAC_Handler
|
||||
PTC_Handler
|
||||
I2S_Handler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
|
||||
{
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
;SAMR21G18A
|
||||
;256KB FLASH (0x40000) @ 0x000000000
|
||||
;2KB RAM (0x8000) @ 0x20000000
|
||||
|
||||
|
||||
;SAMR21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
|
||||
LR_IROM1 0x00000000 0x40000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment
|
||||
RW_IRAM1 (0x20000000+0xB0) (0x8000-0xB0) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,189 @@
|
|||
;/*****************************************************************************
|
||||
; * @file startup_SAMR21.s
|
||||
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
|
||||
; * Atmel SAMR21 Device Series
|
||||
; * @version V1.00
|
||||
; * @date 24. February 2014
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2014 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * @par
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * @par
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
__initial_sp EQU 0x20008000 ; Top of RAM
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD PM_Handler ; 0 Power Manager
|
||||
DCD SYSCTRL_Handler ; 1 System Control
|
||||
DCD WDT_Handler ; 2 Watchdog Timer
|
||||
DCD RTC_Handler ; 3 Real-Time Counter
|
||||
DCD EIC_Handler ; 4 External Interrupt Controller
|
||||
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
|
||||
DCD DMAC_Handler ; 6 Direct Memory Access Controller
|
||||
DCD USB_Handler ; 7 Universal Serial Bus
|
||||
DCD EVSYS_Handler ; 8 Event System Interface
|
||||
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
|
||||
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
|
||||
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
|
||||
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
|
||||
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
|
||||
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
|
||||
DCD TCC0_Handler ; 15 Timer Counter Control 0
|
||||
DCD TCC1_Handler ; 16 Timer Counter Control 1
|
||||
DCD TCC2_Handler ; 17 Timer Counter Control 2
|
||||
DCD TC3_Handler ; 18 Basic Timer Counter 0
|
||||
DCD TC4_Handler ; 19 Basic Timer Counter 1
|
||||
DCD TC5_Handler ; 20 Basic Timer Counter 2
|
||||
DCD TC6_Handler ; 21 Basic Timer Counter 3
|
||||
DCD TC7_Handler ; 22 Basic Timer Counter 4
|
||||
DCD ADC_Handler ; 23 Analog Digital Converter
|
||||
DCD AC_Handler ; 24 Analog Comparators
|
||||
DCD DAC_Handler ; 25 Digital Analog Converter
|
||||
DCD PTC_Handler ; 26 Peripheral Touch Controller
|
||||
DCD I2S_Handler ; 27 Inter-IC Sound Interface
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT PM_Handler [WEAK]
|
||||
EXPORT SYSCTRL_Handler [WEAK]
|
||||
EXPORT WDT_Handler [WEAK]
|
||||
EXPORT RTC_Handler [WEAK]
|
||||
EXPORT EIC_Handler [WEAK]
|
||||
EXPORT NVMCTRL_Handler [WEAK]
|
||||
EXPORT DMAC_Handler [WEAK]
|
||||
EXPORT USB_Handler [WEAK]
|
||||
EXPORT EVSYS_Handler [WEAK]
|
||||
EXPORT SERCOM0_Handler [WEAK]
|
||||
EXPORT SERCOM1_Handler [WEAK]
|
||||
EXPORT SERCOM2_Handler [WEAK]
|
||||
EXPORT SERCOM3_Handler [WEAK]
|
||||
EXPORT SERCOM4_Handler [WEAK]
|
||||
EXPORT SERCOM5_Handler [WEAK]
|
||||
EXPORT TCC0_Handler [WEAK]
|
||||
EXPORT TCC1_Handler [WEAK]
|
||||
EXPORT TCC2_Handler [WEAK]
|
||||
EXPORT TC3_Handler [WEAK]
|
||||
EXPORT TC4_Handler [WEAK]
|
||||
EXPORT TC5_Handler [WEAK]
|
||||
EXPORT TC6_Handler [WEAK]
|
||||
EXPORT TC7_Handler [WEAK]
|
||||
EXPORT ADC_Handler [WEAK]
|
||||
EXPORT AC_Handler [WEAK]
|
||||
EXPORT DAC_Handler [WEAK]
|
||||
EXPORT PTC_Handler [WEAK]
|
||||
EXPORT I2S_Handler [WEAK]
|
||||
|
||||
PM_Handler
|
||||
SYSCTRL_Handler
|
||||
WDT_Handler
|
||||
RTC_Handler
|
||||
EIC_Handler
|
||||
NVMCTRL_Handler
|
||||
DMAC_Handler
|
||||
USB_Handler
|
||||
EVSYS_Handler
|
||||
SERCOM0_Handler
|
||||
SERCOM1_Handler
|
||||
SERCOM2_Handler
|
||||
SERCOM3_Handler
|
||||
SERCOM4_Handler
|
||||
SERCOM5_Handler
|
||||
TCC0_Handler
|
||||
TCC1_Handler
|
||||
TCC2_Handler
|
||||
TC3_Handler
|
||||
TC4_Handler
|
||||
TC5_Handler
|
||||
TC6_Handler
|
||||
TC7_Handler
|
||||
ADC_Handler
|
||||
AC_Handler
|
||||
DAC_Handler
|
||||
PTC_Handler
|
||||
I2S_Handler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
|
||||
{
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -3,18 +3,16 @@ OUTPUT_ARCH(arm)
|
|||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
MEMORY {
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
|
||||
ram (rwx) : ORIGIN = 0x20000000 + 0xB0, LENGTH = 0x00008000 - 0xB0
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
SECTIONS {
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
|
|
@ -75,14 +73,8 @@ SECTIONS
|
|||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.dvectors (NOLOAD) :
|
||||
{
|
||||
_sdvectors = .;
|
||||
. = . + 0xB0;
|
||||
_edvectors = .;
|
||||
} > ram
|
||||
|
||||
.relocate : AT (_etext)
|
||||
.relocate :
|
||||
AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
|
|
@ -42,7 +42,10 @@
|
|||
#include "samr21.h"
|
||||
|
||||
typedef void (*intfunc) (void);
|
||||
typedef union { intfunc __fun; void * __ptr; } intvec_elem;
|
||||
typedef union {
|
||||
intfunc __fun;
|
||||
void * __ptr;
|
||||
} intvec_elem;
|
||||
|
||||
void __iar_program_start(void);
|
||||
int __low_level_init(void);
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/* mbed Microcontroller Library
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
||||
//extern uint32_t _sdvectors;
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
||||
uint32_t i;
|
||||
|
||||
// Copy and switch to dynamic vectors if the first time called
|
||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
||||
uint32_t *old_vectors = vectors;
|
||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
||||
vectors[i] = old_vectors[i];
|
||||
}
|
||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
||||
}
|
||||
vectors[IRQn + 16] = vector;
|
||||
}
|
||||
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
||||
return vectors[IRQn + 16];
|
||||
}
|
||||
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Reference in New Issue