mirror of https://github.com/ARMmbed/mbed-os.git
TARGET_NXP: Remove support for LPC55S69
Mbed OS 6 dropped support for all LPC55S69 targets. This commit removes all source files for those targets.pull/13921/head
Hugues Kamba
parent
f2278567d0
commit
07b6db2f0d
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/* mbed Microcontroller Library
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* Copyright (c) 2020 ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_PERIPHERALNAMES_H
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#define MBED_PERIPHERALNAMES_H
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#include "cmsis.h"
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#include "PortNames.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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OSC32KCLK = 0,
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} RTCName;
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typedef enum {
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UART_0 = Flexcomm0,
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UART_1 = Flexcomm2,
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UART_2 = Flexcomm6
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} UARTName;
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#define STDIO_UART_TX USBTX
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#define STDIO_UART_RX USBRX
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#define STDIO_UART UART_0
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typedef enum {
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I2C_0 = Flexcomm1,
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I2C_1 = Flexcomm4
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} I2CName;
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#define TPM_SHIFT 8
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typedef enum {
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PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
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PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
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PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
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PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
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PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
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PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
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PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
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PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
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PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
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PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
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PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2
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PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3
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PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4
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PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5
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PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6
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PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7
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PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0
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PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1
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PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2
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PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3
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PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4
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PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5
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PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6
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PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7
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PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0
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PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1
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PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2
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PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3
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PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4
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PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5
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PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6
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PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7
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} PWMName;
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#define ADC_INSTANCE_SHIFT 8
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#define ADC_B_CHANNEL_SHIFT 5
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typedef enum {
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ADC0_SE0 = 0,
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ADC0_SE1 = 1,
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ADC0_SE2 = 2,
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ADC0_SE3 = 3,
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ADC0_SE4 = 4,
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ADC0_SE5 = 5,
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ADC0_SE6 = 6,
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ADC0_SE7 = 7,
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ADC0_SE8 = 8,
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ADC0_SE9 = 9,
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ADC0_SE10 = 10,
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ADC0_SE11 = 11,
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ADC0_SE12 = 12,
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ADC0_SE13 = 13,
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ADC0_SE14 = 14,
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ADC0_SE15 = 15,
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ADC0_SE0_B = (1 << ADC_B_CHANNEL_SHIFT) | 0,
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ADC0_SE1_B = (1 << ADC_B_CHANNEL_SHIFT) | 1,
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ADC0_SE2_B = (1 << ADC_B_CHANNEL_SHIFT) | 2,
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ADC0_SE3_B = (1 << ADC_B_CHANNEL_SHIFT) | 3,
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ADC0_SE4_B = (1 << ADC_B_CHANNEL_SHIFT) | 4,
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ADC0_SE5_B = (1 << ADC_B_CHANNEL_SHIFT) | 5,
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ADC0_SE6_B = (1 << ADC_B_CHANNEL_SHIFT) | 6,
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ADC0_SE7_B = (1 << ADC_B_CHANNEL_SHIFT) | 7,
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ADC0_SE8_B = (1 << ADC_B_CHANNEL_SHIFT) | 8,
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ADC0_SE9_B = (1 << ADC_B_CHANNEL_SHIFT) | 9,
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ADC0_SE10_B = (1 << ADC_B_CHANNEL_SHIFT) | 10,
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ADC0_SE11_B = (1 << ADC_B_CHANNEL_SHIFT) | 11,
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ADC0_SE12_B = (1 << ADC_B_CHANNEL_SHIFT) | 12,
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ADC0_SE13_B = (1 << ADC_B_CHANNEL_SHIFT) | 13,
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ADC0_SE14_B = (1 << ADC_B_CHANNEL_SHIFT) | 14,
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ADC0_SE15_B = (1 << ADC_B_CHANNEL_SHIFT) | 15
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} ADCName;
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typedef enum {
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CAN_0 = 0,
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CAN_1 = 1
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} CANName;
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#define SSELNUM_SHIFT 16
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typedef enum {
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SPI_0 = Flexcomm3,
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SPI_1 = Flexcomm5,
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SPI_2 = Flexcomm8
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} SPIName;
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/* Flexcomm 8 on LPC55S69 is dedicated for HS-SPI and hence uses different naming convention */
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#define kFRO12M_to_FLEXCOMM8 (kFRO12M_to_HSLSPI)
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#define kFC8_RST_SHIFT_RSTn (kHSLSPI_RST_SHIFT_RSTn)
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -1,146 +0,0 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2020 ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_PERIPHERALPINMAPS_H
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#define MBED_PERIPHERALPINMAPS_H
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#include <mstd_cstddef>
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/************RTC***************/
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MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_RTC[] = {
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{NC, OSC32KCLK, 0},
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};
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/************ADC***************/
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MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_ADC[] = {
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{P0_23, ADC0_SE0, 0},
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{P0_10, ADC0_SE1, 0},
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{P0_31, ADC0_SE3, 0},
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{P1_8, ADC0_SE4, 0},
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{P2_0, ADC0_SE5, 0},
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{P2_13, ADC0_SE6, 0},
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{P2_11, ADC0_SE7, 0},
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{NC , NC , 0}
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};
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/************CAN***************/
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MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_CAN_TD[] = {
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{NC , NC , 0}
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};
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MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_CAN_RD[] = {
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{NC , NC , 0}
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};
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/************DAC***************/
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MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_DAC[] = {
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{NC , NC , 0}
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};
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/************I2C***************/
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MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_I2C_SDA[] = {
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{P0_13, I2C_0, 1},
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{P1_21, I2C_1, 5},
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{NC , NC , 0}
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};
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MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_I2C_SCL[] = {
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{P0_14, I2C_0, 1},
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{P1_20, I2C_1, 5},
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{NC , NC , 0}
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};
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/************UART***************/
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MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_TX[] = {
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{P0_30, UART_0, 1},
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{P1_6, UART_0, 1},
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{P0_27, UART_1, 1},
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{NC , NC , 0}
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};
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MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_RX[] = {
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{P0_29, UART_0, 1},
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{P1_5, UART_0, 1},
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{P1_24, UART_1, 1},
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{NC , NC , 0}
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};
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MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_CTS[] = {
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{P1_8, UART_0, 1},
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{P1_26, UART_1, 1},
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{NC , NC , 0}
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};
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MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_RTS[] = {
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{P1_7, UART_0, 1},
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{P1_27, UART_1, 1},
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{NC , NC , 0}
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};
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/************SPI***************/
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MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_SCLK[] = {
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{P0_6, SPI_0, 1},
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{P0_21, SPI_1, 7},
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{P1_2, SPI_2, 6},
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{NC , NC , 0}
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};
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MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_MOSI[] = {
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{P0_3, SPI_0, 1},
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{P0_20, SPI_1, 7},
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{P0_26, SPI_2, 9},
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{NC , NC , 0}
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};
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MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_MISO[] = {
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{P0_2, SPI_0, 1},
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{P0_19, SPI_1, 7},
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{P1_3, SPI_2, 6},
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{NC , NC , 0}
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};
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MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_SSEL[] = {
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{P0_4, SPI_0, 8},
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{P1_20, SPI_1, ((1 << SSELNUM_SHIFT) | 1)},
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{P1_1, SPI_2, ((1 << SSELNUM_SHIFT) | 5)},
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{NC , NC , 0}
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};
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/************PWM***************/
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MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_PWM[] = {
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{NC , NC , 0}
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};
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#define PINMAP_ANALOGIN PinMap_ADC
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#define PINMAP_ANALOGOUT PinMap_DAC
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#define PINMAP_I2C_SDA PinMap_I2C_SDA
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#define PINMAP_I2C_SCL PinMap_I2C_SCL
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#define PINMAP_UART_TX PinMap_UART_TX
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#define PINMAP_UART_RX PinMap_UART_RX
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#define PINMAP_UART_CTS PinMap_UART_CTS
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#define PINMAP_UART_RTS PinMap_UART_RTS
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#define PINMAP_SPI_SCLK PinMap_SPI_SCLK
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#define PINMAP_SPI_MOSI PinMap_SPI_MOSI
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#define PINMAP_SPI_MISO PinMap_SPI_MISO
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#define PINMAP_SPI_SSEL PinMap_SPI_SSEL
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#define PINMAP_PWM PinMap_PWM
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#define PINMAP_CAN_TD PinMap_CAN_TD
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#define PINMAP_CAN_RD PinMap_CAN_RD
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#endif
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/* mbed Microcontroller Library
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* Copyright (c) 2020 ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "PeripheralPins.h"
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#include "PeripheralPinMaps.h"
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/* mbed Microcontroller Library
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* Copyright (c) 2020 ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_PINNAMES_H
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#define MBED_PINNAMES_H
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* If this macro is defined, then constexpr utility functions for pin-map seach can be used. */
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#define STATIC_PINMAP_READY 0
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typedef enum {
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PIN_INPUT,
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PIN_OUTPUT
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} PinDirection;
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#define PORT_SHIFT 5
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typedef enum {
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P0_0 = (0 << PORT_SHIFT | 0),
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P0_1 = (0 << PORT_SHIFT | 1),
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P0_2 = (0 << PORT_SHIFT | 2),
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P0_3 = (0 << PORT_SHIFT | 3),
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|
||||||
P0_4 = (0 << PORT_SHIFT | 4),
|
|
||||||
P0_5 = (0 << PORT_SHIFT | 5),
|
|
||||||
P0_6 = (0 << PORT_SHIFT | 6),
|
|
||||||
P0_7 = (0 << PORT_SHIFT | 7),
|
|
||||||
P0_8 = (0 << PORT_SHIFT | 8),
|
|
||||||
P0_9 = (0 << PORT_SHIFT | 9),
|
|
||||||
P0_10 = (0 << PORT_SHIFT | 10),
|
|
||||||
P0_11 = (0 << PORT_SHIFT | 11),
|
|
||||||
P0_12 = (0 << PORT_SHIFT | 12),
|
|
||||||
P0_13 = (0 << PORT_SHIFT | 13),
|
|
||||||
P0_14 = (0 << PORT_SHIFT | 14),
|
|
||||||
P0_15 = (0 << PORT_SHIFT | 15),
|
|
||||||
P0_16 = (0 << PORT_SHIFT | 16),
|
|
||||||
P0_17 = (0 << PORT_SHIFT | 17),
|
|
||||||
P0_18 = (0 << PORT_SHIFT | 18),
|
|
||||||
P0_19 = (0 << PORT_SHIFT | 19),
|
|
||||||
P0_20 = (0 << PORT_SHIFT | 20),
|
|
||||||
P0_21 = (0 << PORT_SHIFT | 21),
|
|
||||||
P0_22 = (0 << PORT_SHIFT | 22),
|
|
||||||
P0_23 = (0 << PORT_SHIFT | 23),
|
|
||||||
P0_24 = (0 << PORT_SHIFT | 24),
|
|
||||||
P0_25 = (0 << PORT_SHIFT | 25),
|
|
||||||
P0_26 = (0 << PORT_SHIFT | 26),
|
|
||||||
P0_27 = (0 << PORT_SHIFT | 27),
|
|
||||||
P0_28 = (0 << PORT_SHIFT | 28),
|
|
||||||
P0_29 = (0 << PORT_SHIFT | 29),
|
|
||||||
P0_30 = (0 << PORT_SHIFT | 30),
|
|
||||||
P0_31 = (0 << PORT_SHIFT | 31),
|
|
||||||
|
|
||||||
P1_0 = (1 << PORT_SHIFT | 0),
|
|
||||||
P1_1 = (1 << PORT_SHIFT | 1),
|
|
||||||
P1_2 = (1 << PORT_SHIFT | 2),
|
|
||||||
P1_3 = (1 << PORT_SHIFT | 3),
|
|
||||||
P1_4 = (1 << PORT_SHIFT | 4),
|
|
||||||
P1_5 = (1 << PORT_SHIFT | 5),
|
|
||||||
P1_6 = (1 << PORT_SHIFT | 6),
|
|
||||||
P1_7 = (1 << PORT_SHIFT | 7),
|
|
||||||
P1_8 = (1 << PORT_SHIFT | 8),
|
|
||||||
P1_9 = (1 << PORT_SHIFT | 9),
|
|
||||||
P1_10 = (1 << PORT_SHIFT | 10),
|
|
||||||
P1_11 = (1 << PORT_SHIFT | 11),
|
|
||||||
P1_12 = (1 << PORT_SHIFT | 12),
|
|
||||||
P1_13 = (1 << PORT_SHIFT | 13),
|
|
||||||
P1_14 = (1 << PORT_SHIFT | 14),
|
|
||||||
P1_15 = (1 << PORT_SHIFT | 15),
|
|
||||||
P1_16 = (1 << PORT_SHIFT | 16),
|
|
||||||
P1_17 = (1 << PORT_SHIFT | 17),
|
|
||||||
P1_18 = (1 << PORT_SHIFT | 18),
|
|
||||||
P1_19 = (1 << PORT_SHIFT | 19),
|
|
||||||
P1_20 = (1 << PORT_SHIFT | 20),
|
|
||||||
P1_21 = (1 << PORT_SHIFT | 21),
|
|
||||||
P1_22 = (1 << PORT_SHIFT | 22),
|
|
||||||
P1_23 = (1 << PORT_SHIFT | 23),
|
|
||||||
P1_24 = (1 << PORT_SHIFT | 24),
|
|
||||||
P1_25 = (1 << PORT_SHIFT | 25),
|
|
||||||
P1_26 = (1 << PORT_SHIFT | 26),
|
|
||||||
P1_27 = (1 << PORT_SHIFT | 27),
|
|
||||||
P1_28 = (1 << PORT_SHIFT | 28),
|
|
||||||
P1_29 = (1 << PORT_SHIFT | 29),
|
|
||||||
P1_30 = (1 << PORT_SHIFT | 30),
|
|
||||||
P1_31 = (1 << PORT_SHIFT | 31),
|
|
||||||
|
|
||||||
P2_0 = (2 << PORT_SHIFT | 0),
|
|
||||||
P2_1 = (2 << PORT_SHIFT | 1),
|
|
||||||
P2_2 = (2 << PORT_SHIFT | 2),
|
|
||||||
P2_3 = (2 << PORT_SHIFT | 3),
|
|
||||||
P2_4 = (2 << PORT_SHIFT | 4),
|
|
||||||
P2_5 = (2 << PORT_SHIFT | 5),
|
|
||||||
P2_6 = (2 << PORT_SHIFT | 6),
|
|
||||||
P2_7 = (2 << PORT_SHIFT | 7),
|
|
||||||
P2_8 = (2 << PORT_SHIFT | 8),
|
|
||||||
P2_9 = (2 << PORT_SHIFT | 9),
|
|
||||||
P2_10 = (2 << PORT_SHIFT | 10),
|
|
||||||
P2_11 = (2 << PORT_SHIFT | 11),
|
|
||||||
P2_12 = (2 << PORT_SHIFT | 12),
|
|
||||||
P2_13 = (2 << PORT_SHIFT | 13),
|
|
||||||
P2_14 = (2 << PORT_SHIFT | 14),
|
|
||||||
P2_15 = (2 << PORT_SHIFT | 15),
|
|
||||||
P2_16 = (2 << PORT_SHIFT | 16),
|
|
||||||
P2_17 = (2 << PORT_SHIFT | 17),
|
|
||||||
P2_18 = (2 << PORT_SHIFT | 18),
|
|
||||||
P2_19 = (2 << PORT_SHIFT | 19),
|
|
||||||
P2_20 = (2 << PORT_SHIFT | 20),
|
|
||||||
P2_21 = (2 << PORT_SHIFT | 21),
|
|
||||||
P2_22 = (2 << PORT_SHIFT | 22),
|
|
||||||
P2_23 = (2 << PORT_SHIFT | 23),
|
|
||||||
P2_24 = (2 << PORT_SHIFT | 24),
|
|
||||||
P2_25 = (2 << PORT_SHIFT | 25),
|
|
||||||
P2_26 = (2 << PORT_SHIFT | 26),
|
|
||||||
P2_27 = (2 << PORT_SHIFT | 27),
|
|
||||||
P2_28 = (2 << PORT_SHIFT | 28),
|
|
||||||
P2_29 = (2 << PORT_SHIFT | 29),
|
|
||||||
P2_30 = (2 << PORT_SHIFT | 30),
|
|
||||||
P2_31 = (2 << PORT_SHIFT | 31),
|
|
||||||
|
|
||||||
P3_0 = (3 << PORT_SHIFT | 0),
|
|
||||||
P3_1 = (3 << PORT_SHIFT | 1),
|
|
||||||
P3_2 = (3 << PORT_SHIFT | 2),
|
|
||||||
P3_3 = (3 << PORT_SHIFT | 3),
|
|
||||||
P3_4 = (3 << PORT_SHIFT | 4),
|
|
||||||
P3_5 = (3 << PORT_SHIFT | 5),
|
|
||||||
|
|
||||||
LED_RED = P1_4,
|
|
||||||
LED_GREEN = P1_17,
|
|
||||||
LED_BLUE = P1_18,
|
|
||||||
BUZZER = P1_19,
|
|
||||||
|
|
||||||
// LED naming
|
|
||||||
LED1 = LED_RED,
|
|
||||||
LED2 = LED_BLUE,
|
|
||||||
|
|
||||||
// Push buttons
|
|
||||||
SW1 = P1_1,
|
|
||||||
|
|
||||||
// USB Pins
|
|
||||||
USBTX = P0_30,
|
|
||||||
USBRX = P0_29,
|
|
||||||
|
|
||||||
// Arduino Headers
|
|
||||||
D0 = P1_24,
|
|
||||||
D1 = P0_27,
|
|
||||||
D2 = P1_31,
|
|
||||||
D3 = P1_28,
|
|
||||||
D4 = P1_27,
|
|
||||||
D5 = P1_26,
|
|
||||||
D6 = P1_25,
|
|
||||||
D7 = P1_22,
|
|
||||||
|
|
||||||
D8 = P1_23,
|
|
||||||
D9 = P0_21,
|
|
||||||
D10 = P0_4,
|
|
||||||
D11 = P0_3,
|
|
||||||
D12 = P0_2,
|
|
||||||
D13 = P0_6,
|
|
||||||
D14 = P1_21,
|
|
||||||
D15 = P1_20,
|
|
||||||
|
|
||||||
I2C_SDA = D14,
|
|
||||||
I2C_SCL = D15,
|
|
||||||
|
|
||||||
A0 = P0_23,
|
|
||||||
A1 = P0_15,
|
|
||||||
A2 = P0_31,
|
|
||||||
A3 = P1_8,
|
|
||||||
A4 = P0_16,
|
|
||||||
A5 = P1_0,
|
|
||||||
|
|
||||||
// SPI Pins configuration
|
|
||||||
SPI_MOSI = D11,
|
|
||||||
SPI_MISO = D12,
|
|
||||||
SPI_SCK = D13,
|
|
||||||
SPI_CS = D10,
|
|
||||||
|
|
||||||
// Not connected
|
|
||||||
NC = (int)0xFFFFFFFF
|
|
||||||
|
|
||||||
} PinName;
|
|
||||||
|
|
||||||
|
|
||||||
typedef enum {
|
|
||||||
PullNone = 0,
|
|
||||||
PullDown = 1,
|
|
||||||
PullUp = 2,
|
|
||||||
PullDefault = PullUp
|
|
||||||
} PinMode;
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,228 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2020 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
/***********************************************************************************************************************
|
|
||||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
|
||||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
|
||||||
**********************************************************************************************************************/
|
|
||||||
/*
|
|
||||||
* How to set up clock using clock driver functions:
|
|
||||||
*
|
|
||||||
* 1. Setup clock sources.
|
|
||||||
*
|
|
||||||
* 2. Set up wait states of the flash.
|
|
||||||
*
|
|
||||||
* 3. Set up all dividers.
|
|
||||||
*
|
|
||||||
* 4. Set up all selectors to provide selected clocks.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* clang-format off */
|
|
||||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
|
||||||
!!GlobalInfo
|
|
||||||
product: Clocks v5.0
|
|
||||||
processor: LPC55S69
|
|
||||||
package_id: LPC55S69JBD100
|
|
||||||
mcu_data: ksdk2_0
|
|
||||||
processor_version: 0.0.6
|
|
||||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
|
||||||
/* clang-format on */
|
|
||||||
|
|
||||||
#include "fsl_power.h"
|
|
||||||
#include "fsl_clock.h"
|
|
||||||
#include "clock_config.h"
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables
|
|
||||||
******************************************************************************/
|
|
||||||
/* System clock frequency. */
|
|
||||||
extern uint32_t SystemCoreClock;
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
************************ BOARD_InitBootClocks function ************************
|
|
||||||
******************************************************************************/
|
|
||||||
void BOARD_InitBootClocks(void)
|
|
||||||
{
|
|
||||||
BOARD_BootClockFROHF96M();
|
|
||||||
}
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
******************** Configuration BOARD_BootClockFRO12M **********************
|
|
||||||
******************************************************************************/
|
|
||||||
/* clang-format off */
|
|
||||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
|
||||||
!!Configuration
|
|
||||||
name: BOARD_BootClockFRO12M
|
|
||||||
outputs:
|
|
||||||
- {id: System_clock.outFreq, value: 12 MHz}
|
|
||||||
settings:
|
|
||||||
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
|
|
||||||
sources:
|
|
||||||
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
|
|
||||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
|
||||||
/* clang-format on */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables for BOARD_BootClockFRO12M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code for BOARD_BootClockFRO12M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
void BOARD_BootClockFRO12M(void)
|
|
||||||
{
|
|
||||||
#ifndef SDK_SECONDARY_CORE
|
|
||||||
/*!< Set up the clock sources */
|
|
||||||
/*!< Configure FRO192M */
|
|
||||||
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
|
|
||||||
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
|
|
||||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
|
|
||||||
|
|
||||||
CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
|
|
||||||
|
|
||||||
POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
|
|
||||||
CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
|
|
||||||
|
|
||||||
/*!< Set up dividers */
|
|
||||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
|
|
||||||
|
|
||||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
|
||||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
|
|
||||||
|
|
||||||
/*< Set SystemCoreClock variable. */
|
|
||||||
SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
******************* Configuration BOARD_BootClockFROHF96M *********************
|
|
||||||
******************************************************************************/
|
|
||||||
/* clang-format off */
|
|
||||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
|
||||||
!!Configuration
|
|
||||||
name: BOARD_BootClockFROHF96M
|
|
||||||
called_from_default_init: true
|
|
||||||
outputs:
|
|
||||||
- {id: System_clock.outFreq, value: 96 MHz}
|
|
||||||
settings:
|
|
||||||
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
|
|
||||||
- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
|
|
||||||
sources:
|
|
||||||
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
|
|
||||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
|
||||||
/* clang-format on */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables for BOARD_BootClockFROHF96M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code for BOARD_BootClockFROHF96M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
void BOARD_BootClockFROHF96M(void)
|
|
||||||
{
|
|
||||||
#ifndef SDK_SECONDARY_CORE
|
|
||||||
/*!< Set up the clock sources */
|
|
||||||
/*!< Configure FRO192M */
|
|
||||||
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
|
|
||||||
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
|
|
||||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
|
|
||||||
|
|
||||||
CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
|
|
||||||
|
|
||||||
POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
|
|
||||||
CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
|
|
||||||
|
|
||||||
/*!< Set up dividers */
|
|
||||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
|
|
||||||
|
|
||||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
|
||||||
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
|
|
||||||
|
|
||||||
/*< Set SystemCoreClock variable. */
|
|
||||||
SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
******************** Configuration BOARD_BootClockPLL100M *********************
|
|
||||||
******************************************************************************/
|
|
||||||
/* clang-format off */
|
|
||||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
|
||||||
!!Configuration
|
|
||||||
name: BOARD_BootClockPLL100M
|
|
||||||
outputs:
|
|
||||||
- {id: System_clock.outFreq, value: 100 MHz}
|
|
||||||
settings:
|
|
||||||
- {id: PLL0_Mode, value: Normal}
|
|
||||||
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
|
|
||||||
- {id: ENABLE_CLKIN_ENA, value: Enabled}
|
|
||||||
- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
|
|
||||||
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
|
|
||||||
- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
|
|
||||||
- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
|
|
||||||
- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
|
|
||||||
- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
|
|
||||||
sources:
|
|
||||||
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
|
|
||||||
- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
|
|
||||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
|
||||||
/* clang-format on */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables for BOARD_BootClockPLL100M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code for BOARD_BootClockPLL100M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
void BOARD_BootClockPLL100M(void)
|
|
||||||
{
|
|
||||||
#ifndef SDK_SECONDARY_CORE
|
|
||||||
/*!< Set up the clock sources */
|
|
||||||
/*!< Configure FRO192M */
|
|
||||||
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
|
|
||||||
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
|
|
||||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
|
|
||||||
|
|
||||||
CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
|
|
||||||
|
|
||||||
POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
|
|
||||||
POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
|
|
||||||
CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
|
|
||||||
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
|
|
||||||
ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
|
|
||||||
|
|
||||||
POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
|
|
||||||
CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
|
|
||||||
|
|
||||||
/*!< Set up PLL */
|
|
||||||
CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
|
|
||||||
POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
|
|
||||||
POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
|
|
||||||
const pll_setup_t pll0Setup = {
|
|
||||||
.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(54U) | SYSCON_PLL0CTRL_SELP(26U),
|
|
||||||
.pllndec = SYSCON_PLL0NDEC_NDIV(4U),
|
|
||||||
.pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
|
|
||||||
.pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
|
|
||||||
.pllRate = 100000000U,
|
|
||||||
.flags = PLL_SETUPFLAG_WAITLOCK
|
|
||||||
};
|
|
||||||
CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
|
|
||||||
|
|
||||||
/*!< Set up dividers */
|
|
||||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
|
|
||||||
|
|
||||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
|
||||||
CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
|
|
||||||
|
|
||||||
/*< Set SystemCoreClock variable. */
|
|
||||||
SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -1,121 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2020 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
/***********************************************************************************************************************
|
|
||||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
|
||||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
|
||||||
**********************************************************************************************************************/
|
|
||||||
|
|
||||||
#ifndef _CLOCK_CONFIG_H_
|
|
||||||
#define _CLOCK_CONFIG_H_
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */
|
|
||||||
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
************************ BOARD_InitBootClocks function ************************
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif /* __cplusplus*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief This function executes default configuration of clocks.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void BOARD_InitBootClocks(void);
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif /* __cplusplus*/
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
******************** Configuration BOARD_BootClockFRO12M **********************
|
|
||||||
******************************************************************************/
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions for BOARD_BootClockFRO12M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
|
|
||||||
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API for BOARD_BootClockFRO12M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif /* __cplusplus*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief This function executes configuration of clocks.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void BOARD_BootClockFRO12M(void);
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif /* __cplusplus*/
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
******************* Configuration BOARD_BootClockFROHF96M *********************
|
|
||||||
******************************************************************************/
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions for BOARD_BootClockFROHF96M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
|
|
||||||
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API for BOARD_BootClockFROHF96M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif /* __cplusplus*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief This function executes configuration of clocks.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void BOARD_BootClockFROHF96M(void);
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif /* __cplusplus*/
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
******************** Configuration BOARD_BootClockPLL100M *********************
|
|
||||||
******************************************************************************/
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions for BOARD_BootClockPLL100M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */
|
|
||||||
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API for BOARD_BootClockPLL100M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif /* __cplusplus*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief This function executes configuration of clocks.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void BOARD_BootClockPLL100M(void);
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif /* __cplusplus*/
|
|
||||||
|
|
||||||
#endif /* _CLOCK_CONFIG_H_ */
|
|
||||||
|
|
||||||
|
|
@ -1,37 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* Copyright (c) 2020 ARM Limited
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
#ifndef MBED_DEVICE_H
|
|
||||||
#define MBED_DEVICE_H
|
|
||||||
|
|
||||||
#define NUMBER_OF_GPIO_INTS 8
|
|
||||||
|
|
||||||
#define LPADC_VREF_SOURCE kLPADC_ReferenceVoltageAlt2
|
|
||||||
#define LPADC_DO_OFFSET_CALIBRATION false
|
|
||||||
#define LPADC_OFFSET_VALUE_A 10U
|
|
||||||
#define LPADC_OFFSET_VALUE_B 10U
|
|
||||||
|
|
||||||
#define APP_EXCLUDE_FROM_DEEPSLEEP (kPDRUNCFG_PD_DCDC | kPDRUNCFG_PD_FRO192M | kPDRUNCFG_PD_FRO32K)
|
|
||||||
|
|
||||||
/* Defines used by the sleep code */
|
|
||||||
#define LPC_CLOCK_INTERNAL_IRC BOARD_BootClockFRO12M()
|
|
||||||
#define LPC_CLOCK_RUN BOARD_BootClockFROHF96M()
|
|
||||||
|
|
||||||
#define DEVICE_ID_LENGTH 24
|
|
||||||
|
|
||||||
#include "objects.h"
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,68 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* Copyright (c) 2020 ARM Limited
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
#include "gpio_api.h"
|
|
||||||
#include "clock_config.h"
|
|
||||||
#include "fsl_power.h"
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
// called before main
|
|
||||||
void mbed_sdk_init()
|
|
||||||
{
|
|
||||||
BOARD_BootClockFROHF96M();
|
|
||||||
}
|
|
||||||
|
|
||||||
// Enable the RTC oscillator if available on the board
|
|
||||||
void rtc_setup_oscillator(void)
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t us_ticker_get_clock()
|
|
||||||
{
|
|
||||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
|
||||||
/* Use 96 MHz clock us ticker timer */
|
|
||||||
CLOCK_AttachClk(kFRO_HF_to_CTIMER0);
|
|
||||||
return CLOCK_GetFreq(kCLOCK_CTmier0);;
|
|
||||||
#else
|
|
||||||
/* Use 96 MHz clock us ticker timer */
|
|
||||||
CLOCK_AttachClk(kFRO_HF_to_CTIMER1);
|
|
||||||
return CLOCK_GetFreq(kCLOCK_CTmier1);;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
void ADC_ClockPower_Configuration(void)
|
|
||||||
{
|
|
||||||
/* Set clock source for ADC0 */
|
|
||||||
CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, 16U, true);
|
|
||||||
CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK);
|
|
||||||
|
|
||||||
/* Disable LDOGPADC power down */
|
|
||||||
POWER_DisablePD(kPDRUNCFG_PD_LDOGPADC);
|
|
||||||
RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn);
|
|
||||||
}
|
|
||||||
|
|
||||||
void sdio_clock_setup(void)
|
|
||||||
{
|
|
||||||
/* Attach main clock to SDIF */
|
|
||||||
CLOCK_AttachClk(kMAIN_CLK_to_SDIO_CLK);
|
|
||||||
|
|
||||||
CLOCK_SetClkDiv(kCLOCK_DivSdioClk, 1U, true);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -1,139 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* Copyright (c) 2006-2013 ARM Limited
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
#ifndef MBED_PERIPHERALNAMES_H
|
|
||||||
#define MBED_PERIPHERALNAMES_H
|
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
#include "PortNames.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
typedef enum {
|
|
||||||
OSC32KCLK = 0,
|
|
||||||
} RTCName;
|
|
||||||
|
|
||||||
typedef enum {
|
|
||||||
UART_0 = Flexcomm0,
|
|
||||||
UART_1 = Flexcomm2
|
|
||||||
} UARTName;
|
|
||||||
|
|
||||||
#define STDIO_UART_TX USBTX
|
|
||||||
#define STDIO_UART_RX USBRX
|
|
||||||
#define STDIO_UART UART_0
|
|
||||||
|
|
||||||
typedef enum {
|
|
||||||
I2C_0 = Flexcomm1,
|
|
||||||
I2C_1 = Flexcomm4
|
|
||||||
} I2CName;
|
|
||||||
|
|
||||||
#define TPM_SHIFT 8
|
|
||||||
typedef enum {
|
|
||||||
PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
|
|
||||||
PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
|
|
||||||
PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
|
|
||||||
PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
|
|
||||||
PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
|
|
||||||
PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
|
|
||||||
PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
|
|
||||||
PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
|
|
||||||
PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
|
|
||||||
PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
|
|
||||||
PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2
|
|
||||||
PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3
|
|
||||||
PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4
|
|
||||||
PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5
|
|
||||||
PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6
|
|
||||||
PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7
|
|
||||||
PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0
|
|
||||||
PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1
|
|
||||||
PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2
|
|
||||||
PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3
|
|
||||||
PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4
|
|
||||||
PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5
|
|
||||||
PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6
|
|
||||||
PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7
|
|
||||||
PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0
|
|
||||||
PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1
|
|
||||||
PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2
|
|
||||||
PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3
|
|
||||||
PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4
|
|
||||||
PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5
|
|
||||||
PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6
|
|
||||||
PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7
|
|
||||||
} PWMName;
|
|
||||||
|
|
||||||
#define ADC_INSTANCE_SHIFT 8
|
|
||||||
#define ADC_B_CHANNEL_SHIFT 5
|
|
||||||
|
|
||||||
typedef enum {
|
|
||||||
ADC0_SE0 = 0,
|
|
||||||
ADC0_SE1 = 1,
|
|
||||||
ADC0_SE2 = 2,
|
|
||||||
ADC0_SE3 = 3,
|
|
||||||
ADC0_SE4 = 4,
|
|
||||||
ADC0_SE5 = 5,
|
|
||||||
ADC0_SE6 = 6,
|
|
||||||
ADC0_SE7 = 7,
|
|
||||||
ADC0_SE8 = 8,
|
|
||||||
ADC0_SE9 = 9,
|
|
||||||
ADC0_SE10 = 10,
|
|
||||||
ADC0_SE11 = 11,
|
|
||||||
ADC0_SE12 = 12,
|
|
||||||
ADC0_SE13 = 13,
|
|
||||||
ADC0_SE14 = 14,
|
|
||||||
ADC0_SE15 = 15,
|
|
||||||
ADC0_SE0_B = (1 << ADC_B_CHANNEL_SHIFT) | 0,
|
|
||||||
ADC0_SE1_B = (1 << ADC_B_CHANNEL_SHIFT) | 1,
|
|
||||||
ADC0_SE2_B = (1 << ADC_B_CHANNEL_SHIFT) | 2,
|
|
||||||
ADC0_SE3_B = (1 << ADC_B_CHANNEL_SHIFT) | 3,
|
|
||||||
ADC0_SE4_B = (1 << ADC_B_CHANNEL_SHIFT) | 4,
|
|
||||||
ADC0_SE5_B = (1 << ADC_B_CHANNEL_SHIFT) | 5,
|
|
||||||
ADC0_SE6_B = (1 << ADC_B_CHANNEL_SHIFT) | 6,
|
|
||||||
ADC0_SE7_B = (1 << ADC_B_CHANNEL_SHIFT) | 7,
|
|
||||||
ADC0_SE8_B = (1 << ADC_B_CHANNEL_SHIFT) | 8,
|
|
||||||
ADC0_SE9_B = (1 << ADC_B_CHANNEL_SHIFT) | 9,
|
|
||||||
ADC0_SE10_B = (1 << ADC_B_CHANNEL_SHIFT) | 10,
|
|
||||||
ADC0_SE11_B = (1 << ADC_B_CHANNEL_SHIFT) | 11,
|
|
||||||
ADC0_SE12_B = (1 << ADC_B_CHANNEL_SHIFT) | 12,
|
|
||||||
ADC0_SE13_B = (1 << ADC_B_CHANNEL_SHIFT) | 13,
|
|
||||||
ADC0_SE14_B = (1 << ADC_B_CHANNEL_SHIFT) | 14,
|
|
||||||
ADC0_SE15_B = (1 << ADC_B_CHANNEL_SHIFT) | 15
|
|
||||||
} ADCName;
|
|
||||||
|
|
||||||
typedef enum {
|
|
||||||
CAN_0 = 0,
|
|
||||||
CAN_1 = 1
|
|
||||||
} CANName;
|
|
||||||
|
|
||||||
#define SSELNUM_SHIFT 16
|
|
||||||
typedef enum {
|
|
||||||
SPI_0 = Flexcomm3,
|
|
||||||
SPI_1 = Flexcomm7,
|
|
||||||
SPI_2 = Flexcomm8
|
|
||||||
} SPIName;
|
|
||||||
|
|
||||||
/* Flexcomm 8 on LPC55S69 is dedicated for HS-SPI and hence uses different naming convention */
|
|
||||||
#define kFRO12M_to_FLEXCOMM8 (kFRO12M_to_HSLSPI)
|
|
||||||
#define kFC8_RST_SHIFT_RSTn (kHSLSPI_RST_SHIFT_RSTn)
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,146 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* Copyright (c) 2006-2013 ARM Limited
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef MBED_PERIPHERALPINMAPS_H
|
|
||||||
#define MBED_PERIPHERALPINMAPS_H
|
|
||||||
|
|
||||||
#include <mstd_cstddef>
|
|
||||||
|
|
||||||
/************RTC***************/
|
|
||||||
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_RTC[] = {
|
|
||||||
{NC, OSC32KCLK, 0},
|
|
||||||
};
|
|
||||||
|
|
||||||
/************ADC***************/
|
|
||||||
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_ADC[] = {
|
|
||||||
{P0_23, ADC0_SE0, 0},
|
|
||||||
{P0_10, ADC0_SE1, 0},
|
|
||||||
{P0_31, ADC0_SE3, 0},
|
|
||||||
{P1_8, ADC0_SE4, 0},
|
|
||||||
{P2_0, ADC0_SE5, 0},
|
|
||||||
{P2_13, ADC0_SE6, 0},
|
|
||||||
{P2_11, ADC0_SE7, 0},
|
|
||||||
{NC , NC , 0}
|
|
||||||
};
|
|
||||||
|
|
||||||
/************CAN***************/
|
|
||||||
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_CAN_TD[] = {
|
|
||||||
{NC , NC , 0}
|
|
||||||
};
|
|
||||||
|
|
||||||
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_CAN_RD[] = {
|
|
||||||
{NC , NC , 0}
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
/************DAC***************/
|
|
||||||
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_DAC[] = {
|
|
||||||
{NC , NC , 0}
|
|
||||||
};
|
|
||||||
|
|
||||||
/************I2C***************/
|
|
||||||
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_I2C_SDA[] = {
|
|
||||||
{P0_13, I2C_0, 1},
|
|
||||||
{P1_21, I2C_1, 5},
|
|
||||||
{NC , NC , 0}
|
|
||||||
};
|
|
||||||
|
|
||||||
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_I2C_SCL[] = {
|
|
||||||
{P0_14, I2C_0, 1},
|
|
||||||
{P1_20, I2C_1, 5},
|
|
||||||
{NC , NC , 0}
|
|
||||||
};
|
|
||||||
|
|
||||||
/************UART***************/
|
|
||||||
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_TX[] = {
|
|
||||||
{P0_30, UART_0, 1},
|
|
||||||
{P1_6, UART_0, 1},
|
|
||||||
{P0_27, UART_1, 1},
|
|
||||||
{NC , NC , 0}
|
|
||||||
};
|
|
||||||
|
|
||||||
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_RX[] = {
|
|
||||||
{P0_29, UART_0, 1},
|
|
||||||
{P1_5, UART_0, 1},
|
|
||||||
{P1_24, UART_1, 1},
|
|
||||||
{NC , NC , 0}
|
|
||||||
};
|
|
||||||
|
|
||||||
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_CTS[] = {
|
|
||||||
{P1_8, UART_0, 1},
|
|
||||||
{P1_26, UART_1, 1},
|
|
||||||
{NC , NC , 0}
|
|
||||||
};
|
|
||||||
|
|
||||||
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_RTS[] = {
|
|
||||||
{P1_7, UART_0, 1},
|
|
||||||
{P1_27, UART_1, 1},
|
|
||||||
{NC , NC , 0}
|
|
||||||
};
|
|
||||||
|
|
||||||
/************SPI***************/
|
|
||||||
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_SCLK[] = {
|
|
||||||
{P0_6, SPI_0, 1},
|
|
||||||
{P0_21, SPI_1, 7},
|
|
||||||
{P1_2, SPI_2, 6},
|
|
||||||
{NC , NC , 0}
|
|
||||||
};
|
|
||||||
|
|
||||||
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_MOSI[] = {
|
|
||||||
{P0_3, SPI_0, 1},
|
|
||||||
{P0_20, SPI_1, 7},
|
|
||||||
{P0_26, SPI_2, 9},
|
|
||||||
{NC , NC , 0}
|
|
||||||
};
|
|
||||||
|
|
||||||
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_MISO[] = {
|
|
||||||
{P0_2, SPI_0, 1},
|
|
||||||
{P0_19, SPI_1, 7},
|
|
||||||
{P1_3, SPI_2, 6},
|
|
||||||
{NC , NC , 0}
|
|
||||||
};
|
|
||||||
|
|
||||||
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_SSEL[] = {
|
|
||||||
{P0_4, SPI_0, 8},
|
|
||||||
{P1_20, SPI_1, ((1 << SSELNUM_SHIFT) | 1)},
|
|
||||||
{P1_1, SPI_2, ((1 << SSELNUM_SHIFT) | 5)},
|
|
||||||
{NC , NC , 0}
|
|
||||||
};
|
|
||||||
|
|
||||||
/************PWM***************/
|
|
||||||
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_PWM[] = {
|
|
||||||
{NC , NC , 0}
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
#define PINMAP_ANALOGIN PinMap_ADC
|
|
||||||
#define PINMAP_ANALOGOUT PinMap_DAC
|
|
||||||
#define PINMAP_I2C_SDA PinMap_I2C_SDA
|
|
||||||
#define PINMAP_I2C_SCL PinMap_I2C_SCL
|
|
||||||
#define PINMAP_UART_TX PinMap_UART_TX
|
|
||||||
#define PINMAP_UART_RX PinMap_UART_RX
|
|
||||||
#define PINMAP_UART_CTS PinMap_UART_CTS
|
|
||||||
#define PINMAP_UART_RTS PinMap_UART_RTS
|
|
||||||
#define PINMAP_SPI_SCLK PinMap_SPI_SCLK
|
|
||||||
#define PINMAP_SPI_MOSI PinMap_SPI_MOSI
|
|
||||||
#define PINMAP_SPI_MISO PinMap_SPI_MISO
|
|
||||||
#define PINMAP_SPI_SSEL PinMap_SPI_SSEL
|
|
||||||
#define PINMAP_PWM PinMap_PWM
|
|
||||||
#define PINMAP_CAN_TD PinMap_CAN_TD
|
|
||||||
#define PINMAP_CAN_RD PinMap_CAN_RD
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,40 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* Copyright (c) 2006-2013 ARM Limited
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "PeripheralPins.h"
|
|
||||||
#include "PeripheralPinMaps.h"
|
|
||||||
|
|
||||||
// List of GPIOs with limited functionality
|
|
||||||
const PinList *pinmap_gpio_restricted_pins()
|
|
||||||
{
|
|
||||||
static const PinName pins[] = {
|
|
||||||
A4, // fixed pull-up (for I2C)
|
|
||||||
A5, // fixed pull-up (for I2C)
|
|
||||||
D5, // fixed pull-up (for LED)
|
|
||||||
D3, // fixed pull-up (for LED)
|
|
||||||
D4, // fixed pull-up (for LED)
|
|
||||||
D7, // fixed pull-up
|
|
||||||
D15, // fixed pull-up (for I2C)
|
|
||||||
D14 // fixed pull-up (for I2C)
|
|
||||||
};
|
|
||||||
|
|
||||||
static const PinList pin_list = {
|
|
||||||
sizeof(pins) / sizeof(pins[0]),
|
|
||||||
pins
|
|
||||||
};
|
|
||||||
return &pin_list;
|
|
||||||
}
|
|
||||||
|
|
@ -1,209 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* Copyright (c) 2006-2013 ARM Limited
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
#ifndef MBED_PINNAMES_H
|
|
||||||
#define MBED_PINNAMES_H
|
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* If this macro is defined, then constexpr utility functions for pin-map seach can be used. */
|
|
||||||
#define STATIC_PINMAP_READY 1
|
|
||||||
|
|
||||||
typedef enum {
|
|
||||||
PIN_INPUT,
|
|
||||||
PIN_OUTPUT
|
|
||||||
} PinDirection;
|
|
||||||
|
|
||||||
#define PORT_SHIFT 5
|
|
||||||
|
|
||||||
typedef enum {
|
|
||||||
P0_0 = (0 << PORT_SHIFT | 0),
|
|
||||||
P0_1 = (0 << PORT_SHIFT | 1),
|
|
||||||
P0_2 = (0 << PORT_SHIFT | 2),
|
|
||||||
P0_3 = (0 << PORT_SHIFT | 3),
|
|
||||||
P0_4 = (0 << PORT_SHIFT | 4),
|
|
||||||
P0_5 = (0 << PORT_SHIFT | 5),
|
|
||||||
P0_6 = (0 << PORT_SHIFT | 6),
|
|
||||||
P0_7 = (0 << PORT_SHIFT | 7),
|
|
||||||
P0_8 = (0 << PORT_SHIFT | 8),
|
|
||||||
P0_9 = (0 << PORT_SHIFT | 9),
|
|
||||||
P0_10 = (0 << PORT_SHIFT | 10),
|
|
||||||
P0_11 = (0 << PORT_SHIFT | 11),
|
|
||||||
P0_12 = (0 << PORT_SHIFT | 12),
|
|
||||||
P0_13 = (0 << PORT_SHIFT | 13),
|
|
||||||
P0_14 = (0 << PORT_SHIFT | 14),
|
|
||||||
P0_15 = (0 << PORT_SHIFT | 15),
|
|
||||||
P0_16 = (0 << PORT_SHIFT | 16),
|
|
||||||
P0_17 = (0 << PORT_SHIFT | 17),
|
|
||||||
P0_18 = (0 << PORT_SHIFT | 18),
|
|
||||||
P0_19 = (0 << PORT_SHIFT | 19),
|
|
||||||
P0_20 = (0 << PORT_SHIFT | 20),
|
|
||||||
P0_21 = (0 << PORT_SHIFT | 21),
|
|
||||||
P0_22 = (0 << PORT_SHIFT | 22),
|
|
||||||
P0_23 = (0 << PORT_SHIFT | 23),
|
|
||||||
P0_24 = (0 << PORT_SHIFT | 24),
|
|
||||||
P0_25 = (0 << PORT_SHIFT | 25),
|
|
||||||
P0_26 = (0 << PORT_SHIFT | 26),
|
|
||||||
P0_27 = (0 << PORT_SHIFT | 27),
|
|
||||||
P0_28 = (0 << PORT_SHIFT | 28),
|
|
||||||
P0_29 = (0 << PORT_SHIFT | 29),
|
|
||||||
P0_30 = (0 << PORT_SHIFT | 30),
|
|
||||||
P0_31 = (0 << PORT_SHIFT | 31),
|
|
||||||
|
|
||||||
P1_0 = (1 << PORT_SHIFT | 0),
|
|
||||||
P1_1 = (1 << PORT_SHIFT | 1),
|
|
||||||
P1_2 = (1 << PORT_SHIFT | 2),
|
|
||||||
P1_3 = (1 << PORT_SHIFT | 3),
|
|
||||||
P1_4 = (1 << PORT_SHIFT | 4),
|
|
||||||
P1_5 = (1 << PORT_SHIFT | 5),
|
|
||||||
P1_6 = (1 << PORT_SHIFT | 6),
|
|
||||||
P1_7 = (1 << PORT_SHIFT | 7),
|
|
||||||
P1_8 = (1 << PORT_SHIFT | 8),
|
|
||||||
P1_9 = (1 << PORT_SHIFT | 9),
|
|
||||||
P1_10 = (1 << PORT_SHIFT | 10),
|
|
||||||
P1_11 = (1 << PORT_SHIFT | 11),
|
|
||||||
P1_12 = (1 << PORT_SHIFT | 12),
|
|
||||||
P1_13 = (1 << PORT_SHIFT | 13),
|
|
||||||
P1_14 = (1 << PORT_SHIFT | 14),
|
|
||||||
P1_15 = (1 << PORT_SHIFT | 15),
|
|
||||||
P1_16 = (1 << PORT_SHIFT | 16),
|
|
||||||
P1_17 = (1 << PORT_SHIFT | 17),
|
|
||||||
P1_18 = (1 << PORT_SHIFT | 18),
|
|
||||||
P1_19 = (1 << PORT_SHIFT | 19),
|
|
||||||
P1_20 = (1 << PORT_SHIFT | 20),
|
|
||||||
P1_21 = (1 << PORT_SHIFT | 21),
|
|
||||||
P1_22 = (1 << PORT_SHIFT | 22),
|
|
||||||
P1_23 = (1 << PORT_SHIFT | 23),
|
|
||||||
P1_24 = (1 << PORT_SHIFT | 24),
|
|
||||||
P1_25 = (1 << PORT_SHIFT | 25),
|
|
||||||
P1_26 = (1 << PORT_SHIFT | 26),
|
|
||||||
P1_27 = (1 << PORT_SHIFT | 27),
|
|
||||||
P1_28 = (1 << PORT_SHIFT | 28),
|
|
||||||
P1_29 = (1 << PORT_SHIFT | 29),
|
|
||||||
P1_30 = (1 << PORT_SHIFT | 30),
|
|
||||||
P1_31 = (1 << PORT_SHIFT | 31),
|
|
||||||
|
|
||||||
P2_0 = (2 << PORT_SHIFT | 0),
|
|
||||||
P2_1 = (2 << PORT_SHIFT | 1),
|
|
||||||
P2_2 = (2 << PORT_SHIFT | 2),
|
|
||||||
P2_3 = (2 << PORT_SHIFT | 3),
|
|
||||||
P2_4 = (2 << PORT_SHIFT | 4),
|
|
||||||
P2_5 = (2 << PORT_SHIFT | 5),
|
|
||||||
P2_6 = (2 << PORT_SHIFT | 6),
|
|
||||||
P2_7 = (2 << PORT_SHIFT | 7),
|
|
||||||
P2_8 = (2 << PORT_SHIFT | 8),
|
|
||||||
P2_9 = (2 << PORT_SHIFT | 9),
|
|
||||||
P2_10 = (2 << PORT_SHIFT | 10),
|
|
||||||
P2_11 = (2 << PORT_SHIFT | 11),
|
|
||||||
P2_12 = (2 << PORT_SHIFT | 12),
|
|
||||||
P2_13 = (2 << PORT_SHIFT | 13),
|
|
||||||
P2_14 = (2 << PORT_SHIFT | 14),
|
|
||||||
P2_15 = (2 << PORT_SHIFT | 15),
|
|
||||||
P2_16 = (2 << PORT_SHIFT | 16),
|
|
||||||
P2_17 = (2 << PORT_SHIFT | 17),
|
|
||||||
P2_18 = (2 << PORT_SHIFT | 18),
|
|
||||||
P2_19 = (2 << PORT_SHIFT | 19),
|
|
||||||
P2_20 = (2 << PORT_SHIFT | 20),
|
|
||||||
P2_21 = (2 << PORT_SHIFT | 21),
|
|
||||||
P2_22 = (2 << PORT_SHIFT | 22),
|
|
||||||
P2_23 = (2 << PORT_SHIFT | 23),
|
|
||||||
P2_24 = (2 << PORT_SHIFT | 24),
|
|
||||||
P2_25 = (2 << PORT_SHIFT | 25),
|
|
||||||
P2_26 = (2 << PORT_SHIFT | 26),
|
|
||||||
P2_27 = (2 << PORT_SHIFT | 27),
|
|
||||||
P2_28 = (2 << PORT_SHIFT | 28),
|
|
||||||
P2_29 = (2 << PORT_SHIFT | 29),
|
|
||||||
P2_30 = (2 << PORT_SHIFT | 30),
|
|
||||||
P2_31 = (2 << PORT_SHIFT | 31),
|
|
||||||
|
|
||||||
P3_0 = (3 << PORT_SHIFT | 0),
|
|
||||||
P3_1 = (3 << PORT_SHIFT | 1),
|
|
||||||
P3_2 = (3 << PORT_SHIFT | 2),
|
|
||||||
P3_3 = (3 << PORT_SHIFT | 3),
|
|
||||||
P3_4 = (3 << PORT_SHIFT | 4),
|
|
||||||
P3_5 = (3 << PORT_SHIFT | 5),
|
|
||||||
|
|
||||||
LED_RED = P1_4,
|
|
||||||
|
|
||||||
// mbed original LED naming
|
|
||||||
LED1 = P1_6,
|
|
||||||
LED2 = P1_7,
|
|
||||||
LED3 = LED_RED,
|
|
||||||
LED4 = LED_RED,
|
|
||||||
|
|
||||||
//Push buttons
|
|
||||||
SW2 = P1_18,
|
|
||||||
SW3 = P1_9,
|
|
||||||
|
|
||||||
// USB Pins
|
|
||||||
USBTX = P0_30,
|
|
||||||
USBRX = P0_29,
|
|
||||||
|
|
||||||
// Arduino Headers
|
|
||||||
D0 = P1_24,
|
|
||||||
D1 = P0_27,
|
|
||||||
D2 = P0_15,
|
|
||||||
D3 = P1_6,
|
|
||||||
D4 = P1_7,
|
|
||||||
D5 = P1_4,
|
|
||||||
D6 = P1_10,
|
|
||||||
D7 = P1_9,
|
|
||||||
D8 = P1_8,
|
|
||||||
D9 = P1_5,
|
|
||||||
D10 = P1_1,
|
|
||||||
D11 = P0_26,
|
|
||||||
D12 = P1_3,
|
|
||||||
D13 = P1_2,
|
|
||||||
D14 = P1_21,
|
|
||||||
D15 = P1_20,
|
|
||||||
|
|
||||||
I2C_SCL = D15,
|
|
||||||
I2C_SDA = D14,
|
|
||||||
|
|
||||||
A0 = P0_16,
|
|
||||||
A1 = P0_23,
|
|
||||||
A2 = P0_0,
|
|
||||||
A3 = P1_31,
|
|
||||||
A4 = P0_13,
|
|
||||||
A5 = P0_14,
|
|
||||||
|
|
||||||
//SPI Pins configuration
|
|
||||||
SPI_MOSI = D11,
|
|
||||||
SPI_MISO = D12,
|
|
||||||
SPI_SCK = D13,
|
|
||||||
SPI_CS = D10,
|
|
||||||
|
|
||||||
// Not connected
|
|
||||||
NC = (int)0xFFFFFFFF
|
|
||||||
} PinName;
|
|
||||||
|
|
||||||
|
|
||||||
typedef enum {
|
|
||||||
PullNone = 0,
|
|
||||||
PullDown = 1,
|
|
||||||
PullUp = 2,
|
|
||||||
PullDefault = PullUp
|
|
||||||
} PinMode;
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,228 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2017-2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
/***********************************************************************************************************************
|
|
||||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
|
||||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
|
||||||
**********************************************************************************************************************/
|
|
||||||
/*
|
|
||||||
* How to set up clock using clock driver functions:
|
|
||||||
*
|
|
||||||
* 1. Setup clock sources.
|
|
||||||
*
|
|
||||||
* 2. Set up wait states of the flash.
|
|
||||||
*
|
|
||||||
* 3. Set up all dividers.
|
|
||||||
*
|
|
||||||
* 4. Set up all selectors to provide selected clocks.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* clang-format off */
|
|
||||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
|
||||||
!!GlobalInfo
|
|
||||||
product: Clocks v5.0
|
|
||||||
processor: LPC55S69
|
|
||||||
package_id: LPC55S69JBD100
|
|
||||||
mcu_data: ksdk2_0
|
|
||||||
processor_version: 0.0.6
|
|
||||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
|
||||||
/* clang-format on */
|
|
||||||
|
|
||||||
#include "fsl_power.h"
|
|
||||||
#include "fsl_clock.h"
|
|
||||||
#include "clock_config.h"
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables
|
|
||||||
******************************************************************************/
|
|
||||||
/* System clock frequency. */
|
|
||||||
extern uint32_t SystemCoreClock;
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
************************ BOARD_InitBootClocks function ************************
|
|
||||||
******************************************************************************/
|
|
||||||
void BOARD_InitBootClocks(void)
|
|
||||||
{
|
|
||||||
BOARD_BootClockFROHF96M();
|
|
||||||
}
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
******************** Configuration BOARD_BootClockFRO12M **********************
|
|
||||||
******************************************************************************/
|
|
||||||
/* clang-format off */
|
|
||||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
|
||||||
!!Configuration
|
|
||||||
name: BOARD_BootClockFRO12M
|
|
||||||
outputs:
|
|
||||||
- {id: System_clock.outFreq, value: 12 MHz}
|
|
||||||
settings:
|
|
||||||
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
|
|
||||||
sources:
|
|
||||||
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
|
|
||||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
|
||||||
/* clang-format on */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables for BOARD_BootClockFRO12M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code for BOARD_BootClockFRO12M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
void BOARD_BootClockFRO12M(void)
|
|
||||||
{
|
|
||||||
#ifndef SDK_SECONDARY_CORE
|
|
||||||
/*!< Set up the clock sources */
|
|
||||||
/*!< Configure FRO192M */
|
|
||||||
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
|
|
||||||
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
|
|
||||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
|
|
||||||
|
|
||||||
CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
|
|
||||||
|
|
||||||
POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
|
|
||||||
CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
|
|
||||||
|
|
||||||
/*!< Set up dividers */
|
|
||||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
|
|
||||||
|
|
||||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
|
||||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
|
|
||||||
|
|
||||||
/*< Set SystemCoreClock variable. */
|
|
||||||
SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
******************* Configuration BOARD_BootClockFROHF96M *********************
|
|
||||||
******************************************************************************/
|
|
||||||
/* clang-format off */
|
|
||||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
|
||||||
!!Configuration
|
|
||||||
name: BOARD_BootClockFROHF96M
|
|
||||||
called_from_default_init: true
|
|
||||||
outputs:
|
|
||||||
- {id: System_clock.outFreq, value: 96 MHz}
|
|
||||||
settings:
|
|
||||||
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
|
|
||||||
- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
|
|
||||||
sources:
|
|
||||||
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
|
|
||||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
|
||||||
/* clang-format on */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables for BOARD_BootClockFROHF96M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code for BOARD_BootClockFROHF96M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
void BOARD_BootClockFROHF96M(void)
|
|
||||||
{
|
|
||||||
#ifndef SDK_SECONDARY_CORE
|
|
||||||
/*!< Set up the clock sources */
|
|
||||||
/*!< Configure FRO192M */
|
|
||||||
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
|
|
||||||
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
|
|
||||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
|
|
||||||
|
|
||||||
CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
|
|
||||||
|
|
||||||
POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
|
|
||||||
CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
|
|
||||||
|
|
||||||
/*!< Set up dividers */
|
|
||||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
|
|
||||||
|
|
||||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
|
||||||
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
|
|
||||||
|
|
||||||
/*< Set SystemCoreClock variable. */
|
|
||||||
SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
******************** Configuration BOARD_BootClockPLL100M *********************
|
|
||||||
******************************************************************************/
|
|
||||||
/* clang-format off */
|
|
||||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
|
||||||
!!Configuration
|
|
||||||
name: BOARD_BootClockPLL100M
|
|
||||||
outputs:
|
|
||||||
- {id: System_clock.outFreq, value: 100 MHz}
|
|
||||||
settings:
|
|
||||||
- {id: PLL0_Mode, value: Normal}
|
|
||||||
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
|
|
||||||
- {id: ENABLE_CLKIN_ENA, value: Enabled}
|
|
||||||
- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
|
|
||||||
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
|
|
||||||
- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
|
|
||||||
- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
|
|
||||||
- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
|
|
||||||
- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
|
|
||||||
sources:
|
|
||||||
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
|
|
||||||
- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
|
|
||||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
|
||||||
/* clang-format on */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables for BOARD_BootClockPLL100M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code for BOARD_BootClockPLL100M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
void BOARD_BootClockPLL100M(void)
|
|
||||||
{
|
|
||||||
#ifndef SDK_SECONDARY_CORE
|
|
||||||
/*!< Set up the clock sources */
|
|
||||||
/*!< Configure FRO192M */
|
|
||||||
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
|
|
||||||
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
|
|
||||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
|
|
||||||
|
|
||||||
CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
|
|
||||||
|
|
||||||
POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
|
|
||||||
POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
|
|
||||||
CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
|
|
||||||
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
|
|
||||||
ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
|
|
||||||
|
|
||||||
POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
|
|
||||||
CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
|
|
||||||
|
|
||||||
/*!< Set up PLL */
|
|
||||||
CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
|
|
||||||
POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
|
|
||||||
POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
|
|
||||||
const pll_setup_t pll0Setup = {
|
|
||||||
.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(54U) | SYSCON_PLL0CTRL_SELP(26U),
|
|
||||||
.pllndec = SYSCON_PLL0NDEC_NDIV(4U),
|
|
||||||
.pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
|
|
||||||
.pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
|
|
||||||
.pllRate = 100000000U,
|
|
||||||
.flags = PLL_SETUPFLAG_WAITLOCK
|
|
||||||
};
|
|
||||||
CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
|
|
||||||
|
|
||||||
/*!< Set up dividers */
|
|
||||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
|
|
||||||
|
|
||||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
|
||||||
CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
|
|
||||||
|
|
||||||
/*< Set SystemCoreClock variable. */
|
|
||||||
SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -1,121 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2017-2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
/***********************************************************************************************************************
|
|
||||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
|
||||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
|
||||||
**********************************************************************************************************************/
|
|
||||||
|
|
||||||
#ifndef _CLOCK_CONFIG_H_
|
|
||||||
#define _CLOCK_CONFIG_H_
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */
|
|
||||||
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
************************ BOARD_InitBootClocks function ************************
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif /* __cplusplus*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief This function executes default configuration of clocks.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void BOARD_InitBootClocks(void);
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif /* __cplusplus*/
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
******************** Configuration BOARD_BootClockFRO12M **********************
|
|
||||||
******************************************************************************/
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions for BOARD_BootClockFRO12M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
|
|
||||||
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API for BOARD_BootClockFRO12M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif /* __cplusplus*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief This function executes configuration of clocks.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void BOARD_BootClockFRO12M(void);
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif /* __cplusplus*/
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
******************* Configuration BOARD_BootClockFROHF96M *********************
|
|
||||||
******************************************************************************/
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions for BOARD_BootClockFROHF96M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
|
|
||||||
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API for BOARD_BootClockFROHF96M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif /* __cplusplus*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief This function executes configuration of clocks.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void BOARD_BootClockFROHF96M(void);
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif /* __cplusplus*/
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
******************** Configuration BOARD_BootClockPLL100M *********************
|
|
||||||
******************************************************************************/
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions for BOARD_BootClockPLL100M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */
|
|
||||||
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API for BOARD_BootClockPLL100M configuration
|
|
||||||
******************************************************************************/
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif /* __cplusplus*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief This function executes configuration of clocks.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void BOARD_BootClockPLL100M(void);
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif /* __cplusplus*/
|
|
||||||
|
|
||||||
#endif /* _CLOCK_CONFIG_H_ */
|
|
||||||
|
|
||||||
|
|
@ -1,39 +0,0 @@
|
||||||
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
|
|
||||||
// Check the 'features' section of the target description in 'targets.json' for more details.
|
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* Copyright (c) 2006-2013 ARM Limited
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
#ifndef MBED_DEVICE_H
|
|
||||||
#define MBED_DEVICE_H
|
|
||||||
|
|
||||||
#define NUMBER_OF_GPIO_INTS 8
|
|
||||||
|
|
||||||
#define LPADC_VREF_SOURCE kLPADC_ReferenceVoltageAlt2
|
|
||||||
#define LPADC_DO_OFFSET_CALIBRATION false
|
|
||||||
#define LPADC_OFFSET_VALUE_A 10U
|
|
||||||
#define LPADC_OFFSET_VALUE_B 10U
|
|
||||||
|
|
||||||
#define APP_EXCLUDE_FROM_DEEPSLEEP (kPDRUNCFG_PD_DCDC | kPDRUNCFG_PD_FRO192M | kPDRUNCFG_PD_FRO32K)
|
|
||||||
|
|
||||||
/* Defines used by the sleep code */
|
|
||||||
#define LPC_CLOCK_INTERNAL_IRC BOARD_BootClockFRO12M()
|
|
||||||
#define LPC_CLOCK_RUN BOARD_BootClockFROHF96M()
|
|
||||||
|
|
||||||
#define DEVICE_ID_LENGTH 24
|
|
||||||
|
|
||||||
#include "objects.h"
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,68 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* Copyright (c) 2006-2013 ARM Limited
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
#include "gpio_api.h"
|
|
||||||
#include "clock_config.h"
|
|
||||||
#include "fsl_power.h"
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
// called before main
|
|
||||||
void mbed_sdk_init()
|
|
||||||
{
|
|
||||||
BOARD_BootClockFROHF96M();
|
|
||||||
}
|
|
||||||
|
|
||||||
// Enable the RTC oscillator if available on the board
|
|
||||||
void rtc_setup_oscillator(void)
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t us_ticker_get_clock()
|
|
||||||
{
|
|
||||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
|
||||||
/* Use 96 MHz clock us ticker timer */
|
|
||||||
CLOCK_AttachClk(kFRO_HF_to_CTIMER0);
|
|
||||||
return CLOCK_GetFreq(kCLOCK_CTmier0);;
|
|
||||||
#else
|
|
||||||
/* Use 96 MHz clock us ticker timer */
|
|
||||||
CLOCK_AttachClk(kFRO_HF_to_CTIMER1);
|
|
||||||
return CLOCK_GetFreq(kCLOCK_CTmier1);;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
void ADC_ClockPower_Configuration(void)
|
|
||||||
{
|
|
||||||
/* Set clock source for ADC0 */
|
|
||||||
CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, 16U, true);
|
|
||||||
CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK);
|
|
||||||
|
|
||||||
/* Disable LDOGPADC power down */
|
|
||||||
POWER_DisablePD(kPDRUNCFG_PD_LDOGPADC);
|
|
||||||
RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn);
|
|
||||||
}
|
|
||||||
|
|
||||||
void sdio_clock_setup(void)
|
|
||||||
{
|
|
||||||
/* Attach main clock to SDIF */
|
|
||||||
CLOCK_AttachClk(kMAIN_CLK_to_SDIO_CLK);
|
|
||||||
|
|
||||||
CLOCK_SetClkDiv(kCLOCK_DivSdioClk, 1U, true);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -1,148 +0,0 @@
|
||||||
#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
|
|
||||||
/*
|
|
||||||
** ###################################################################
|
|
||||||
** Processors: LPC55S69JBD100_cm33_core0
|
|
||||||
** LPC55S69JET98_cm33_core0
|
|
||||||
**
|
|
||||||
** Compiler: Keil ARM C/C++ Compiler
|
|
||||||
** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018
|
|
||||||
** Version: rev. 1.0, 2018-08-22
|
|
||||||
** Build: b181008
|
|
||||||
**
|
|
||||||
** Abstract:
|
|
||||||
** Linker file for the Keil ARM C/C++ Compiler
|
|
||||||
**
|
|
||||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
|
||||||
** Copyright 2016-2018 NXP
|
|
||||||
** All rights reserved.
|
|
||||||
**
|
|
||||||
** SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
**
|
|
||||||
** http: www.nxp.com
|
|
||||||
** mail: support@nxp.com
|
|
||||||
**
|
|
||||||
** ###################################################################
|
|
||||||
*/
|
|
||||||
#include "../../../partition/region_defs.h"
|
|
||||||
|
|
||||||
#define __ram_vector_table__ 1
|
|
||||||
|
|
||||||
#if (defined(__ram_vector_table__))
|
|
||||||
#define __ram_vector_table_size__ 0x00000200
|
|
||||||
#else
|
|
||||||
#define __ram_vector_table_size__ 0x00000000
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* USB BDT size */
|
|
||||||
#define usb_bdt_size 0x0
|
|
||||||
|
|
||||||
/* Sizes */
|
|
||||||
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
|
|
||||||
# if defined(MBED_BOOT_STACK_SIZE)
|
|
||||||
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
|
|
||||||
# else
|
|
||||||
# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
|
|
||||||
# endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (defined(__stack_size__))
|
|
||||||
#define Stack_Size __stack_size__
|
|
||||||
#else
|
|
||||||
#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (defined(__heap_size__))
|
|
||||||
#define Heap_Size __heap_size__
|
|
||||||
#else
|
|
||||||
#define Heap_Size 0x0400
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_ROM_START)
|
|
||||||
#define MBED_ROM_START NS_CODE_START
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_APP_START)
|
|
||||||
#define MBED_APP_START MBED_ROM_START
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_ROM_SIZE)
|
|
||||||
#define MBED_ROM_SIZE NS_CODE_SIZE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_APP_SIZE)
|
|
||||||
#define MBED_APP_SIZE MBED_ROM_SIZE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_RAM_START)
|
|
||||||
#define MBED_RAM_START NS_DATA_START
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_RAM_SIZE)
|
|
||||||
#define MBED_RAM_SIZE NS_DATA_SIZE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(NVIC_INTERRUPT_NUM)
|
|
||||||
#define NVIC_INTERRUPT_NUM 60
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(EXCEPTION_VECT_NUM)
|
|
||||||
#define EXCEPTION_VECT_NUM 16
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MEMORY_ADDR_SIZE_IN_BYTE)
|
|
||||||
#define MEMORY_ADDR_SIZE_IN_BYTE 4
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define m_interrupts_start MBED_APP_START
|
|
||||||
#define m_interrupts_size ((NVIC_INTERRUPT_NUM + EXCEPTION_VECT_NUM) * MEMORY_ADDR_SIZE_IN_BYTE)
|
|
||||||
|
|
||||||
#define m_text_start MBED_APP_START + m_interrupts_size
|
|
||||||
#define m_text_size MBED_APP_SIZE - m_interrupts_size
|
|
||||||
|
|
||||||
#define m_interrupts_ram_start MBED_RAM_START
|
|
||||||
#define m_interrupts_ram_size __ram_vector_table_size__
|
|
||||||
|
|
||||||
#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
|
|
||||||
#define m_data_size (MBED_RAM_SIZE - m_interrupts_ram_size)
|
|
||||||
|
|
||||||
#define m_usb_sram_start 0x40100000
|
|
||||||
#define m_usb_sram_size 0x00004000
|
|
||||||
|
|
||||||
LR_IROM1 m_interrupts_start (AlignExpr(m_text_start, 8)+m_text_size-m_interrupts_start) { ; load region size_region
|
|
||||||
|
|
||||||
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
|
|
||||||
* (RESET,+FIRST)
|
|
||||||
}
|
|
||||||
|
|
||||||
ER_IROM1 AlignExpr(m_text_start, 8) FIXED m_text_size { ; load address = execution address
|
|
||||||
* (InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
|
|
||||||
#if (defined(__ram_vector_table__))
|
|
||||||
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
RW_m_data m_data_start m_data_size { ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
RW_IRAM1 ImageLimit(RW_m_data) {
|
|
||||||
}
|
|
||||||
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (m_data_start + m_data_size - Stack_Size - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
|
|
||||||
}
|
|
||||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
|
||||||
}
|
|
||||||
|
|
||||||
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
|
|
||||||
* (m_usb_bdt)
|
|
||||||
}
|
|
||||||
|
|
||||||
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
|
|
||||||
* (m_usb_global)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -1,727 +0,0 @@
|
||||||
;/*****************************************************************************
|
|
||||||
; * @file: startup_LPC55S69_cm33_core0.s
|
|
||||||
; * @purpose: CMSIS Cortex-M33 Core Device Startup File for the
|
|
||||||
; * LPC55S69_cm33_core0
|
|
||||||
; * @version: 1.0
|
|
||||||
; * @date: 2018-8-22
|
|
||||||
; *
|
|
||||||
; * Copyright 1997-2016 Freescale Semiconductor, Inc.
|
|
||||||
; * Copyright 2016-2019 NXP
|
|
||||||
; * All rights reserved.
|
|
||||||
; *
|
|
||||||
; * SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
; *
|
|
||||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
|
||||||
; *
|
|
||||||
; *****************************************************************************/
|
|
||||||
|
|
||||||
|
|
||||||
PRESERVE8
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
; Vector Table Mapped to Address 0 at Reset
|
|
||||||
AREA RESET, DATA, READONLY
|
|
||||||
EXPORT __Vectors
|
|
||||||
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
|
|
||||||
|
|
||||||
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
|
|
||||||
DCD NMI_Handler
|
|
||||||
DCD HardFault_Handler
|
|
||||||
DCD MemManage_Handler
|
|
||||||
DCD BusFault_Handler
|
|
||||||
DCD UsageFault_Handler
|
|
||||||
__vector_table_0x1c
|
|
||||||
DCD 0 ; Checksum of the first 7 words
|
|
||||||
DCD 0
|
|
||||||
DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot
|
|
||||||
DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot
|
|
||||||
DCD SVC_Handler
|
|
||||||
DCD DebugMon_Handler
|
|
||||||
DCD 0
|
|
||||||
DCD PendSV_Handler
|
|
||||||
DCD SysTick_Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt
|
|
||||||
DCD DMA0_IRQHandler ; DMA0 controller
|
|
||||||
DCD GINT0_IRQHandler ; GPIO group 0
|
|
||||||
DCD GINT1_IRQHandler ; GPIO group 1
|
|
||||||
DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0
|
|
||||||
DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1
|
|
||||||
DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2
|
|
||||||
DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3
|
|
||||||
DCD UTICK0_IRQHandler ; Micro-tick Timer
|
|
||||||
DCD MRT0_IRQHandler ; Multi-rate timer
|
|
||||||
DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0
|
|
||||||
DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1
|
|
||||||
DCD SCT0_IRQHandler ; SCTimer/PWM
|
|
||||||
DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3
|
|
||||||
DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM)
|
|
||||||
DCD ADC0_IRQHandler ; ADC0
|
|
||||||
DCD Reserved39_IRQHandler ; Reserved interrupt
|
|
||||||
DCD ACMP_IRQHandler ; ACMP interrupts
|
|
||||||
DCD Reserved41_IRQHandler ; Reserved interrupt
|
|
||||||
DCD Reserved42_IRQHandler ; Reserved interrupt
|
|
||||||
DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt
|
|
||||||
DCD USB0_IRQHandler ; USB device
|
|
||||||
DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts
|
|
||||||
DCD Reserved46_IRQHandler ; Reserved interrupt
|
|
||||||
DCD MAILBOX_IRQHandler ; WAKEUP,Mailbox interrupt (present on selected devices)
|
|
||||||
DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int
|
|
||||||
DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int
|
|
||||||
DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int
|
|
||||||
DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int
|
|
||||||
DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2
|
|
||||||
DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4
|
|
||||||
DCD OS_EVENT_IRQHandler ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts
|
|
||||||
DCD Reserved55_IRQHandler ; Reserved interrupt
|
|
||||||
DCD Reserved56_IRQHandler ; Reserved interrupt
|
|
||||||
DCD Reserved57_IRQHandler ; Reserved interrupt
|
|
||||||
DCD SDIO_IRQHandler ; SD/MMC
|
|
||||||
DCD Reserved59_IRQHandler ; Reserved interrupt
|
|
||||||
DCD Reserved60_IRQHandler ; Reserved interrupt
|
|
||||||
DCD Reserved61_IRQHandler ; Reserved interrupt
|
|
||||||
DCD USB1_UTMI_IRQHandler ; USB1_UTMI
|
|
||||||
DCD USB1_IRQHandler ; USB1 interrupt
|
|
||||||
DCD USB1_NEEDCLK_IRQHandler ; USB1 activity
|
|
||||||
DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt
|
|
||||||
DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt
|
|
||||||
DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt
|
|
||||||
DCD PLU_IRQHandler ; PLU interrupt
|
|
||||||
DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt
|
|
||||||
DCD HASHCRYPT_IRQHandler ; HASHCRYPT interrupt
|
|
||||||
DCD CASER_IRQHandler ; CASPER interrupt
|
|
||||||
DCD PUF_IRQHandler ; PUF interrupt
|
|
||||||
DCD PQ_IRQHandler ; PQ interrupt
|
|
||||||
DCD DMA1_IRQHandler ; DMA1 interrupt
|
|
||||||
DCD LSPI_HS_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM)
|
|
||||||
|
|
||||||
|
|
||||||
AREA |.text|, CODE, READONLY
|
|
||||||
|
|
||||||
; Reset Handler
|
|
||||||
Reset_Handler PROC
|
|
||||||
EXPORT Reset_Handler [WEAK]
|
|
||||||
IMPORT SystemInit
|
|
||||||
IMPORT __main
|
|
||||||
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base|
|
|
||||||
|
|
||||||
CPSID I ; Mask interrupts
|
|
||||||
LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Base|
|
|
||||||
MSR MSPLIM, R0
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
CPSIE I ; Unmask interrupts
|
|
||||||
LDR R0, =__main
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
|
||||||
NMI_Handler PROC
|
|
||||||
EXPORT NMI_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
HardFault_Handler \
|
|
||||||
PROC
|
|
||||||
EXPORT HardFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
MemManage_Handler PROC
|
|
||||||
EXPORT MemManage_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
BusFault_Handler PROC
|
|
||||||
EXPORT BusFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
UsageFault_Handler PROC
|
|
||||||
EXPORT UsageFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
SVC_Handler PROC
|
|
||||||
EXPORT SVC_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
DebugMon_Handler PROC
|
|
||||||
EXPORT DebugMon_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PendSV_Handler PROC
|
|
||||||
EXPORT PendSV_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
SysTick_Handler PROC
|
|
||||||
EXPORT SysTick_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
WDT_BOD_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT WDT_BOD_IRQHandler [WEAK]
|
|
||||||
LDR R0, =WDT_BOD_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
DMA0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT DMA0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =DMA0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
GINT0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT GINT0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =GINT0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
GINT1_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT GINT1_IRQHandler [WEAK]
|
|
||||||
LDR R0, =GINT1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PIN_INT0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PIN_INT0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PIN_INT0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PIN_INT1_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PIN_INT1_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PIN_INT1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PIN_INT2_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PIN_INT2_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PIN_INT2_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PIN_INT3_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PIN_INT3_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PIN_INT3_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
UTICK0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT UTICK0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =UTICK0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
MRT0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT MRT0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =MRT0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
CTIMER0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT CTIMER0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =CTIMER0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
CTIMER1_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT CTIMER1_IRQHandler [WEAK]
|
|
||||||
LDR R0, =CTIMER1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
SCT0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT SCT0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =SCT0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
CTIMER3_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT CTIMER3_IRQHandler [WEAK]
|
|
||||||
LDR R0, =CTIMER3_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
FLEXCOMM0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT FLEXCOMM0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =FLEXCOMM0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
FLEXCOMM1_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT FLEXCOMM1_IRQHandler [WEAK]
|
|
||||||
LDR R0, =FLEXCOMM1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
FLEXCOMM2_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT FLEXCOMM2_IRQHandler [WEAK]
|
|
||||||
LDR R0, =FLEXCOMM2_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
FLEXCOMM3_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT FLEXCOMM3_IRQHandler [WEAK]
|
|
||||||
LDR R0, =FLEXCOMM3_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
FLEXCOMM4_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT FLEXCOMM4_IRQHandler [WEAK]
|
|
||||||
LDR R0, =FLEXCOMM4_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
FLEXCOMM5_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT FLEXCOMM5_IRQHandler [WEAK]
|
|
||||||
LDR R0, =FLEXCOMM5_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
FLEXCOMM6_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT FLEXCOMM6_IRQHandler [WEAK]
|
|
||||||
LDR R0, =FLEXCOMM6_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
FLEXCOMM7_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT FLEXCOMM7_IRQHandler [WEAK]
|
|
||||||
LDR R0, =FLEXCOMM7_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
ADC0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT ADC0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =ADC0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved39_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved39_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved39_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
ACMP_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT ACMP_IRQHandler [WEAK]
|
|
||||||
LDR R0, =ACMP_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved41_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved41_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved41_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved42_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved42_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved42_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
USB0_NEEDCLK_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT USB0_NEEDCLK_IRQHandler [WEAK]
|
|
||||||
LDR R0, =USB0_NEEDCLK_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
USB0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT USB0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =USB0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
RTC_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT RTC_IRQHandler [WEAK]
|
|
||||||
LDR R0, =RTC_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved46_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved46_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved46_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
MAILBOX_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT MAILBOX_IRQHandler [WEAK]
|
|
||||||
LDR R0, =MAILBOX_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PIN_INT4_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PIN_INT4_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PIN_INT4_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PIN_INT5_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PIN_INT5_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PIN_INT5_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PIN_INT6_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PIN_INT6_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PIN_INT6_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PIN_INT7_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PIN_INT7_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PIN_INT7_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
CTIMER2_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT CTIMER2_IRQHandler [WEAK]
|
|
||||||
LDR R0, =CTIMER2_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
CTIMER4_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT CTIMER4_IRQHandler [WEAK]
|
|
||||||
LDR R0, =CTIMER4_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
OS_EVENT_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT OS_EVENT_IRQHandler [WEAK]
|
|
||||||
LDR R0, =OS_EVENT_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved55_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved55_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved55_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved56_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved56_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved56_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved57_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved57_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved57_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
SDIO_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT SDIO_IRQHandler [WEAK]
|
|
||||||
LDR R0, =SDIO_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved59_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved59_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved59_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved60_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved60_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved60_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved61_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved61_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved61_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
USB1_UTMI_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT USB1_UTMI_IRQHandler [WEAK]
|
|
||||||
LDR R0, =USB1_UTMI_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
USB1_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT USB1_IRQHandler [WEAK]
|
|
||||||
LDR R0, =USB1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
USB1_NEEDCLK_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT USB1_NEEDCLK_IRQHandler [WEAK]
|
|
||||||
LDR R0, =USB1_NEEDCLK_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
SEC_HYPERVISOR_CALL_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT SEC_HYPERVISOR_CALL_IRQHandler [WEAK]
|
|
||||||
LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
SEC_GPIO_INT0_IRQ0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT SEC_GPIO_INT0_IRQ0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
SEC_GPIO_INT0_IRQ1_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT SEC_GPIO_INT0_IRQ1_IRQHandler [WEAK]
|
|
||||||
LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PLU_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PLU_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PLU_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
SEC_VIO_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT SEC_VIO_IRQHandler [WEAK]
|
|
||||||
LDR R0, =SEC_VIO_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
HASHCRYPT_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT HASHCRYPT_IRQHandler [WEAK]
|
|
||||||
LDR R0, =HASHCRYPT_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
CASER_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT CASER_IRQHandler [WEAK]
|
|
||||||
LDR R0, =CASER_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PUF_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PUF_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PUF_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PQ_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PQ_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PQ_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
DMA1_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT DMA1_IRQHandler [WEAK]
|
|
||||||
LDR R0, =DMA1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
LSPI_HS_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT LSPI_HS_IRQHandler [WEAK]
|
|
||||||
LDR R0, =LSPI_HS_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Default_Handler PROC
|
|
||||||
EXPORT WDT_BOD_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT DMA0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT GINT0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT GINT1_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PIN_INT0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PIN_INT1_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PIN_INT2_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PIN_INT3_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT UTICK0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT MRT0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT CTIMER0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT CTIMER1_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT SCT0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT CTIMER3_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT FLEXCOMM0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT FLEXCOMM1_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT FLEXCOMM2_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT FLEXCOMM3_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT FLEXCOMM4_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT FLEXCOMM5_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT FLEXCOMM6_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT FLEXCOMM7_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT ADC0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved39_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT ACMP_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved41_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved42_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT USB0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT RTC_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved46_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT MAILBOX_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PIN_INT4_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PIN_INT5_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PIN_INT6_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PIN_INT7_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT CTIMER2_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT CTIMER4_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT OS_EVENT_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved55_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved56_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved57_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT SDIO_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved59_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved60_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved61_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT USB1_UTMI_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT USB1_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT USB1_NEEDCLK_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT SEC_HYPERVISOR_CALL_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT SEC_GPIO_INT0_IRQ0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT SEC_GPIO_INT0_IRQ1_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PLU_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT SEC_VIO_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT HASHCRYPT_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT CASER_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PUF_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PQ_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT LSPI_HS_DriverIRQHandler [WEAK]
|
|
||||||
|
|
||||||
WDT_BOD_DriverIRQHandler
|
|
||||||
DMA0_DriverIRQHandler
|
|
||||||
GINT0_DriverIRQHandler
|
|
||||||
GINT1_DriverIRQHandler
|
|
||||||
PIN_INT0_DriverIRQHandler
|
|
||||||
PIN_INT1_DriverIRQHandler
|
|
||||||
PIN_INT2_DriverIRQHandler
|
|
||||||
PIN_INT3_DriverIRQHandler
|
|
||||||
UTICK0_DriverIRQHandler
|
|
||||||
MRT0_DriverIRQHandler
|
|
||||||
CTIMER0_DriverIRQHandler
|
|
||||||
CTIMER1_DriverIRQHandler
|
|
||||||
SCT0_DriverIRQHandler
|
|
||||||
CTIMER3_DriverIRQHandler
|
|
||||||
FLEXCOMM0_DriverIRQHandler
|
|
||||||
FLEXCOMM1_DriverIRQHandler
|
|
||||||
FLEXCOMM2_DriverIRQHandler
|
|
||||||
FLEXCOMM3_DriverIRQHandler
|
|
||||||
FLEXCOMM4_DriverIRQHandler
|
|
||||||
FLEXCOMM5_DriverIRQHandler
|
|
||||||
FLEXCOMM6_DriverIRQHandler
|
|
||||||
FLEXCOMM7_DriverIRQHandler
|
|
||||||
ADC0_DriverIRQHandler
|
|
||||||
Reserved39_DriverIRQHandler
|
|
||||||
ACMP_DriverIRQHandler
|
|
||||||
Reserved41_DriverIRQHandler
|
|
||||||
Reserved42_DriverIRQHandler
|
|
||||||
USB0_NEEDCLK_DriverIRQHandler
|
|
||||||
USB0_DriverIRQHandler
|
|
||||||
RTC_DriverIRQHandler
|
|
||||||
Reserved46_DriverIRQHandler
|
|
||||||
MAILBOX_DriverIRQHandler
|
|
||||||
PIN_INT4_DriverIRQHandler
|
|
||||||
PIN_INT5_DriverIRQHandler
|
|
||||||
PIN_INT6_DriverIRQHandler
|
|
||||||
PIN_INT7_DriverIRQHandler
|
|
||||||
CTIMER2_DriverIRQHandler
|
|
||||||
CTIMER4_DriverIRQHandler
|
|
||||||
OS_EVENT_DriverIRQHandler
|
|
||||||
Reserved55_DriverIRQHandler
|
|
||||||
Reserved56_DriverIRQHandler
|
|
||||||
Reserved57_DriverIRQHandler
|
|
||||||
SDIO_DriverIRQHandler
|
|
||||||
Reserved59_DriverIRQHandler
|
|
||||||
Reserved60_DriverIRQHandler
|
|
||||||
Reserved61_DriverIRQHandler
|
|
||||||
USB1_UTMI_DriverIRQHandler
|
|
||||||
USB1_DriverIRQHandler
|
|
||||||
USB1_NEEDCLK_DriverIRQHandler
|
|
||||||
SEC_HYPERVISOR_CALL_DriverIRQHandler
|
|
||||||
SEC_GPIO_INT0_IRQ0_DriverIRQHandler
|
|
||||||
SEC_GPIO_INT0_IRQ1_DriverIRQHandler
|
|
||||||
PLU_DriverIRQHandler
|
|
||||||
SEC_VIO_DriverIRQHandler
|
|
||||||
HASHCRYPT_DriverIRQHandler
|
|
||||||
CASER_DriverIRQHandler
|
|
||||||
PUF_DriverIRQHandler
|
|
||||||
PQ_DriverIRQHandler
|
|
||||||
DMA1_DriverIRQHandler
|
|
||||||
LSPI_HS_DriverIRQHandler
|
|
||||||
|
|
||||||
B .
|
|
||||||
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
||||||
|
|
@ -1,284 +0,0 @@
|
||||||
/*
|
|
||||||
** ###################################################################
|
|
||||||
** Processors: LPC55S69JBD100_cm33_core0
|
|
||||||
** LPC55S69JET98_cm33_core0
|
|
||||||
**
|
|
||||||
** Compiler: GNU C Compiler
|
|
||||||
** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018
|
|
||||||
** Version: rev. 1.0, 2018-08-22
|
|
||||||
** Build: b180921
|
|
||||||
**
|
|
||||||
** Abstract:
|
|
||||||
** Linker file for the GNU C Compiler
|
|
||||||
**
|
|
||||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
|
||||||
** Copyright 2016-2018 NXP
|
|
||||||
** All rights reserved.
|
|
||||||
**
|
|
||||||
** SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
**
|
|
||||||
** http: www.nxp.com
|
|
||||||
** mail: support@nxp.com
|
|
||||||
**
|
|
||||||
** ###################################################################
|
|
||||||
*/
|
|
||||||
#include "../../../partition/region_defs.h"
|
|
||||||
|
|
||||||
/* Entry Point */
|
|
||||||
ENTRY(Reset_Handler)
|
|
||||||
|
|
||||||
__ram_vector_table__ = 1;
|
|
||||||
|
|
||||||
#if !defined(MBED_ROM_START)
|
|
||||||
#define MBED_ROM_START NS_CODE_START
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_APP_START)
|
|
||||||
#define MBED_APP_START MBED_ROM_START
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_ROM_SIZE)
|
|
||||||
#define MBED_ROM_SIZE NS_CODE_SIZE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_APP_SIZE)
|
|
||||||
#define MBED_APP_SIZE MBED_ROM_SIZE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_RAM_START)
|
|
||||||
#define MBED_RAM_START NS_DATA_START
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_RAM_SIZE)
|
|
||||||
#define MBED_RAM_SIZE NS_DATA_SIZE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
|
|
||||||
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(NVIC_INTERRUPT_NUM)
|
|
||||||
#define NVIC_INTERRUPT_NUM 60
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(EXCEPTION_VECT_NUM)
|
|
||||||
#define EXCEPTION_VECT_NUM 16
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MEMORY_ADDR_SIZE_IN_BYTE)
|
|
||||||
#define MEMORY_ADDR_SIZE_IN_BYTE 4
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_INTERRUPTS_SIZE)
|
|
||||||
#define MBED_INTERRUPTS_SIZE ((NVIC_INTERRUPT_NUM + EXCEPTION_VECT_NUM) * MEMORY_ADDR_SIZE_IN_BYTE)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
__stack_size__ = MBED_CONF_TARGET_BOOT_STACK_SIZE;
|
|
||||||
|
|
||||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
|
|
||||||
M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x200 : 0x0;
|
|
||||||
|
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
m_interrupts (RX) : ORIGIN = MBED_APP_START, LENGTH = MBED_INTERRUPTS_SIZE
|
|
||||||
m_text (RX) : ORIGIN = MBED_APP_START + MBED_INTERRUPTS_SIZE, LENGTH = MBED_APP_SIZE - MBED_INTERRUPTS_SIZE
|
|
||||||
m_data (RW) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
|
|
||||||
m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Define output sections */
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
/* The startup code goes first into internal flash */
|
|
||||||
.interrupts :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
KEEP(*(.isr_vector)) /* Startup code */
|
|
||||||
. = ALIGN(8);
|
|
||||||
} > m_interrupts
|
|
||||||
|
|
||||||
/* The program code and other data goes into internal flash */
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.text) /* .text sections (code) */
|
|
||||||
*(.text*) /* .text* sections (code) */
|
|
||||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
|
||||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
|
||||||
*(.glue_7) /* glue arm to thumb code */
|
|
||||||
*(.glue_7t) /* glue thumb to arm code */
|
|
||||||
*(.eh_frame)
|
|
||||||
KEEP (*(.init))
|
|
||||||
KEEP (*(.fini))
|
|
||||||
. = ALIGN(8);
|
|
||||||
} > m_text
|
|
||||||
|
|
||||||
#if (! defined(DOMAIN_NS)) || (! DOMAIN_NS)
|
|
||||||
/* section for veneer table */
|
|
||||||
.gnu.sgstubs :
|
|
||||||
{
|
|
||||||
. = ALIGN(32);
|
|
||||||
_start_sg = .;
|
|
||||||
*(.gnu.sgstubs*)
|
|
||||||
. = ALIGN(32);
|
|
||||||
_end_sg = .;
|
|
||||||
} > m_veneer_table
|
|
||||||
#endif
|
|
||||||
|
|
||||||
.ARM.extab :
|
|
||||||
{
|
|
||||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
|
||||||
} > m_text
|
|
||||||
|
|
||||||
.ARM :
|
|
||||||
{
|
|
||||||
__exidx_start = .;
|
|
||||||
*(.ARM.exidx*)
|
|
||||||
__exidx_end = .;
|
|
||||||
} > m_text
|
|
||||||
|
|
||||||
.ctors :
|
|
||||||
{
|
|
||||||
__CTOR_LIST__ = .;
|
|
||||||
/* gcc uses crtbegin.o to find the start of
|
|
||||||
the constructors, so we make sure it is
|
|
||||||
first. Because this is a wildcard, it
|
|
||||||
doesn't matter if the user does not
|
|
||||||
actually link against crtbegin.o; the
|
|
||||||
linker won't look for a file to match a
|
|
||||||
wildcard. The wildcard also means that it
|
|
||||||
doesn't matter which directory crtbegin.o
|
|
||||||
is in. */
|
|
||||||
KEEP (*crtbegin.o(.ctors))
|
|
||||||
KEEP (*crtbegin?.o(.ctors))
|
|
||||||
/* We don't want to include the .ctor section from
|
|
||||||
from the crtend.o file until after the sorted ctors.
|
|
||||||
The .ctor section from the crtend file contains the
|
|
||||||
end of ctors marker and it must be last */
|
|
||||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
|
|
||||||
KEEP (*(SORT(.ctors.*)))
|
|
||||||
KEEP (*(.ctors))
|
|
||||||
__CTOR_END__ = .;
|
|
||||||
} > m_text
|
|
||||||
|
|
||||||
.dtors :
|
|
||||||
{
|
|
||||||
__DTOR_LIST__ = .;
|
|
||||||
KEEP (*crtbegin.o(.dtors))
|
|
||||||
KEEP (*crtbegin?.o(.dtors))
|
|
||||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
|
|
||||||
KEEP (*(SORT(.dtors.*)))
|
|
||||||
KEEP (*(.dtors))
|
|
||||||
__DTOR_END__ = .;
|
|
||||||
} > m_text
|
|
||||||
|
|
||||||
.preinit_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
|
||||||
KEEP (*(.preinit_array*))
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
|
||||||
} > m_text
|
|
||||||
|
|
||||||
.init_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__init_array_start = .);
|
|
||||||
KEEP (*(SORT(.init_array.*)))
|
|
||||||
KEEP (*(.init_array*))
|
|
||||||
PROVIDE_HIDDEN (__init_array_end = .);
|
|
||||||
} > m_text
|
|
||||||
|
|
||||||
.fini_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
|
||||||
KEEP (*(SORT(.fini_array.*)))
|
|
||||||
KEEP (*(.fini_array*))
|
|
||||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
|
||||||
} > m_text
|
|
||||||
|
|
||||||
__etext = .; /* define a global symbol at end of code */
|
|
||||||
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
|
|
||||||
|
|
||||||
.interrupts_ram :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
__VECTOR_RAM__ = .;
|
|
||||||
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
|
|
||||||
*(.m_interrupts_ram) /* This is a user defined section */
|
|
||||||
. += M_VECTOR_RAM_SIZE;
|
|
||||||
. = ALIGN(8);
|
|
||||||
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
|
|
||||||
} > m_data
|
|
||||||
|
|
||||||
__VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
|
|
||||||
__RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
|
|
||||||
|
|
||||||
.data : AT(__DATA_ROM)
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
__DATA_RAM = .;
|
|
||||||
__data_start__ = .; /* create a global symbol at data start */
|
|
||||||
*(.ramfunc*) /* for functions in ram */
|
|
||||||
*(.data) /* .data sections */
|
|
||||||
*(.data*) /* .data* sections */
|
|
||||||
KEEP(*(.jcr*))
|
|
||||||
. = ALIGN(8);
|
|
||||||
__data_end__ = .; /* define a global symbol at data end */
|
|
||||||
} > m_data
|
|
||||||
|
|
||||||
__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
|
|
||||||
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
|
||||||
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
|
|
||||||
|
|
||||||
/* Uninitialized data section */
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
/* This is used by the startup in order to initialize the .bss section */
|
|
||||||
. = ALIGN(8);
|
|
||||||
__START_BSS = .;
|
|
||||||
__bss_start__ = .;
|
|
||||||
*(.bss)
|
|
||||||
*(.bss*)
|
|
||||||
*(COMMON)
|
|
||||||
. = ALIGN(8);
|
|
||||||
__bss_end__ = .;
|
|
||||||
__END_BSS = .;
|
|
||||||
} > m_data
|
|
||||||
|
|
||||||
.heap :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
__end__ = .;
|
|
||||||
PROVIDE(end = .);
|
|
||||||
__HeapBase = .;
|
|
||||||
. = ORIGIN(m_data) + LENGTH(m_data) - STACK_SIZE;
|
|
||||||
__HeapLimit = .;
|
|
||||||
__heap_limit = .; /* Add for _sbrk */
|
|
||||||
} > m_data
|
|
||||||
|
|
||||||
.stack :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
. += STACK_SIZE;
|
|
||||||
} > m_data
|
|
||||||
|
|
||||||
m_usb_bdt (NOLOAD) :
|
|
||||||
{
|
|
||||||
. = ALIGN(512);
|
|
||||||
*(m_usb_bdt)
|
|
||||||
} > m_usb_sram
|
|
||||||
|
|
||||||
m_usb_global (NOLOAD) :
|
|
||||||
{
|
|
||||||
*(m_usb_global)
|
|
||||||
} > m_usb_sram
|
|
||||||
|
|
||||||
/* Initializes stack on the end of block */
|
|
||||||
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
|
|
||||||
__StackLimit = __StackTop - STACK_SIZE;
|
|
||||||
PROVIDE(__stack = __StackTop);
|
|
||||||
|
|
||||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
|
||||||
|
|
||||||
ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -1,874 +0,0 @@
|
||||||
/* --------------------------------------------------------------------------*/
|
|
||||||
/* @file: startup_LPC55S69_cm33_core0.s */
|
|
||||||
/* @purpose: CMSIS Cortex-M33 Core Device Startup File */
|
|
||||||
/* LPC55S69_cm33_core0 */
|
|
||||||
/* @version: 1.0 */
|
|
||||||
/* @date: 2018-8-22 */
|
|
||||||
/* --------------------------------------------------------------------------*/
|
|
||||||
/* */
|
|
||||||
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
|
|
||||||
/* Copyright 2016-2019 NXP */
|
|
||||||
/* All rights reserved. */
|
|
||||||
/* */
|
|
||||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
|
||||||
/*****************************************************************************/
|
|
||||||
/* Version: GCC for ARM Embedded Processors */
|
|
||||||
/*****************************************************************************/
|
|
||||||
|
|
||||||
|
|
||||||
.syntax unified
|
|
||||||
.arch armv8-m.main
|
|
||||||
|
|
||||||
.section .isr_vector, "a"
|
|
||||||
.align 2
|
|
||||||
.globl __Vectors
|
|
||||||
__Vectors:
|
|
||||||
.long __StackTop /* Top of Stack */
|
|
||||||
.long Reset_Handler /* Reset Handler */
|
|
||||||
.long NMI_Handler /* NMI Handler*/
|
|
||||||
.long HardFault_Handler /* Hard Fault Handler*/
|
|
||||||
.long MemManage_Handler /* MPU Fault Handler*/
|
|
||||||
.long BusFault_Handler /* Bus Fault Handler*/
|
|
||||||
.long UsageFault_Handler /* Usage Fault Handler*/
|
|
||||||
.long 0 /* Reserved*/
|
|
||||||
.long 0 /* Reserved*/
|
|
||||||
.long 0 /* Reserved*/
|
|
||||||
.long 0 /* Reserved*/
|
|
||||||
.long SVC_Handler /* SVCall Handler*/
|
|
||||||
.long DebugMon_Handler /* Debug Monitor Handler*/
|
|
||||||
.long 0 /* Reserved*/
|
|
||||||
.long PendSV_Handler /* PendSV Handler*/
|
|
||||||
.long SysTick_Handler /* SysTick Handler*/
|
|
||||||
|
|
||||||
/* External Interrupts */
|
|
||||||
.long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */
|
|
||||||
.long DMA0_IRQHandler /* DMA0 controller */
|
|
||||||
.long GINT0_IRQHandler /* GPIO group 0 */
|
|
||||||
.long GINT1_IRQHandler /* GPIO group 1 */
|
|
||||||
.long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */
|
|
||||||
.long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */
|
|
||||||
.long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */
|
|
||||||
.long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */
|
|
||||||
.long UTICK0_IRQHandler /* Micro-tick Timer */
|
|
||||||
.long MRT0_IRQHandler /* Multi-rate timer */
|
|
||||||
.long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */
|
|
||||||
.long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */
|
|
||||||
.long SCT0_IRQHandler /* SCTimer/PWM */
|
|
||||||
.long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */
|
|
||||||
.long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
|
||||||
.long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
|
||||||
.long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
|
||||||
.long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
|
||||||
.long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
|
||||||
.long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
|
||||||
.long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
|
||||||
.long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
|
||||||
.long ADC0_IRQHandler /* ADC0 */
|
|
||||||
.long Reserved39_IRQHandler /* Reserved interrupt */
|
|
||||||
.long ACMP_IRQHandler /* ACMP interrupts */
|
|
||||||
.long Reserved41_IRQHandler /* Reserved interrupt */
|
|
||||||
.long Reserved42_IRQHandler /* Reserved interrupt */
|
|
||||||
.long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */
|
|
||||||
.long USB0_IRQHandler /* USB device */
|
|
||||||
.long RTC_IRQHandler /* RTC alarm and wake-up interrupts */
|
|
||||||
.long Reserved46_IRQHandler /* Reserved interrupt */
|
|
||||||
.long MAILBOX_IRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */
|
|
||||||
.long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */
|
|
||||||
.long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */
|
|
||||||
.long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */
|
|
||||||
.long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */
|
|
||||||
.long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */
|
|
||||||
.long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */
|
|
||||||
.long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
|
|
||||||
.long Reserved55_IRQHandler /* Reserved interrupt */
|
|
||||||
.long Reserved56_IRQHandler /* Reserved interrupt */
|
|
||||||
.long Reserved57_IRQHandler /* Reserved interrupt */
|
|
||||||
.long SDIO_IRQHandler /* SD/MMC */
|
|
||||||
.long Reserved59_IRQHandler /* Reserved interrupt */
|
|
||||||
.long Reserved60_IRQHandler /* Reserved interrupt */
|
|
||||||
.long Reserved61_IRQHandler /* Reserved interrupt */
|
|
||||||
.long USB1_UTMI_IRQHandler /* USB1_UTMI */
|
|
||||||
.long USB1_IRQHandler /* USB1 interrupt */
|
|
||||||
.long USB1_NEEDCLK_IRQHandler /* USB1 activity */
|
|
||||||
.long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */
|
|
||||||
.long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */
|
|
||||||
.long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */
|
|
||||||
.long PLU_IRQHandler /* PLU interrupt */
|
|
||||||
.long SEC_VIO_IRQHandler /* SEC_VIO interrupt */
|
|
||||||
.long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */
|
|
||||||
.long CASER_IRQHandler /* CASPER interrupt */
|
|
||||||
.long PUF_IRQHandler /* PUF interrupt */
|
|
||||||
.long PQ_IRQHandler /* PQ interrupt */
|
|
||||||
.long DMA1_IRQHandler /* DMA1 interrupt */
|
|
||||||
.long LSPI_HS_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */
|
|
||||||
|
|
||||||
.size __Vectors, . - __Vectors
|
|
||||||
|
|
||||||
.text
|
|
||||||
.thumb
|
|
||||||
|
|
||||||
/* Reset Handler */
|
|
||||||
.thumb_func
|
|
||||||
.align 2
|
|
||||||
.globl Reset_Handler
|
|
||||||
.weak Reset_Handler
|
|
||||||
.type Reset_Handler, %function
|
|
||||||
Reset_Handler:
|
|
||||||
#ifndef __NO_SYSTEM_INIT
|
|
||||||
ldr r0,=SystemInit
|
|
||||||
blx r0
|
|
||||||
#endif
|
|
||||||
/* Loop to copy data from read only memory to RAM. The ranges
|
|
||||||
* of copy from/to are specified by following symbols evaluated in
|
|
||||||
* linker script.
|
|
||||||
* __etext: End of code section, i.e., begin of data sections to copy from.
|
|
||||||
* __data_start__/__data_end__: RAM address range that data should be
|
|
||||||
* copied to. Both must be aligned to 4 bytes boundary. */
|
|
||||||
|
|
||||||
ldr r1, =__etext
|
|
||||||
ldr r2, =__data_start__
|
|
||||||
ldr r3, =__data_end__
|
|
||||||
|
|
||||||
#if 1
|
|
||||||
/* Here are two copies of loop implemenations. First one favors code size
|
|
||||||
* and the second one favors performance. Default uses the first one.
|
|
||||||
* Change to "#if 0" to use the second one */
|
|
||||||
.LC0:
|
|
||||||
cmp r2, r3
|
|
||||||
ittt lt
|
|
||||||
ldrlt r0, [r1], #4
|
|
||||||
strlt r0, [r2], #4
|
|
||||||
blt .LC0
|
|
||||||
#else
|
|
||||||
subs r3, r2
|
|
||||||
ble .LC1
|
|
||||||
.LC0:
|
|
||||||
subs r3, #4
|
|
||||||
ldr r0, [r1, r3]
|
|
||||||
str r0, [r2, r3]
|
|
||||||
bgt .LC0
|
|
||||||
.LC1:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef __STARTUP_CLEAR_BSS
|
|
||||||
/* This part of work usually is done in C library startup code. Otherwise,
|
|
||||||
* define this macro to enable it in this startup.
|
|
||||||
*
|
|
||||||
* Loop to zero out BSS section, which uses following symbols
|
|
||||||
* in linker script:
|
|
||||||
* __bss_start__: start of BSS section. Must align to 4
|
|
||||||
* __bss_end__: end of BSS section. Must align to 4
|
|
||||||
*/
|
|
||||||
ldr r1, =__bss_start__
|
|
||||||
ldr r2, =__bss_end__
|
|
||||||
|
|
||||||
movs r0, 0
|
|
||||||
.LC2:
|
|
||||||
cmp r1, r2
|
|
||||||
itt lt
|
|
||||||
strlt r0, [r1], #4
|
|
||||||
blt .LC2
|
|
||||||
#endif /* __STARTUP_CLEAR_BSS */
|
|
||||||
|
|
||||||
/* Add stack / heap initializaiton */
|
|
||||||
movs r0, 0
|
|
||||||
ldr r1, =__HeapBase
|
|
||||||
ldr r2, =__HeapLimit
|
|
||||||
.LC3:
|
|
||||||
cmp r1, r2
|
|
||||||
itt lt
|
|
||||||
strlt r0, [r1], #4
|
|
||||||
blt .LC3
|
|
||||||
|
|
||||||
ldr r1, =__StackLimit
|
|
||||||
ldr r2, =__StackTop
|
|
||||||
.LC4:
|
|
||||||
cmp r1, r2
|
|
||||||
itt lt
|
|
||||||
strlt r0, [r1], #4
|
|
||||||
blt .LC4
|
|
||||||
/*End of stack / heap initializaiton */
|
|
||||||
cpsie i /* Unmask interrupts */
|
|
||||||
|
|
||||||
#ifndef __START
|
|
||||||
#define __START _start
|
|
||||||
#endif
|
|
||||||
#ifndef __ATOLLIC__
|
|
||||||
ldr r0,=__START
|
|
||||||
blx r0
|
|
||||||
#else
|
|
||||||
ldr r0,=__libc_init_array
|
|
||||||
blx r0
|
|
||||||
ldr r0,=main
|
|
||||||
bx r0
|
|
||||||
#endif
|
|
||||||
.pool
|
|
||||||
.size Reset_Handler, . - Reset_Handler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak DefaultISR
|
|
||||||
.type DefaultISR, %function
|
|
||||||
DefaultISR:
|
|
||||||
b DefaultISR
|
|
||||||
.size DefaultISR, . - DefaultISR
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak NMI_Handler
|
|
||||||
.type NMI_Handler, %function
|
|
||||||
NMI_Handler:
|
|
||||||
ldr r0,=NMI_Handler
|
|
||||||
bx r0
|
|
||||||
.size NMI_Handler, . - NMI_Handler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak HardFault_Handler
|
|
||||||
.type HardFault_Handler, %function
|
|
||||||
HardFault_Handler:
|
|
||||||
ldr r0,=HardFault_Handler
|
|
||||||
bx r0
|
|
||||||
.size HardFault_Handler, . - HardFault_Handler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak SVC_Handler
|
|
||||||
.type SVC_Handler, %function
|
|
||||||
SVC_Handler:
|
|
||||||
ldr r0,=SVC_Handler
|
|
||||||
bx r0
|
|
||||||
.size SVC_Handler, . - SVC_Handler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak PendSV_Handler
|
|
||||||
.type PendSV_Handler, %function
|
|
||||||
PendSV_Handler:
|
|
||||||
ldr r0,=PendSV_Handler
|
|
||||||
bx r0
|
|
||||||
.size PendSV_Handler, . - PendSV_Handler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak SysTick_Handler
|
|
||||||
.type SysTick_Handler, %function
|
|
||||||
SysTick_Handler:
|
|
||||||
ldr r0,=SysTick_Handler
|
|
||||||
bx r0
|
|
||||||
.size SysTick_Handler, . - SysTick_Handler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak WDT_BOD_IRQHandler
|
|
||||||
.type WDT_BOD_IRQHandler, %function
|
|
||||||
WDT_BOD_IRQHandler:
|
|
||||||
ldr r0,=WDT_BOD_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak DMA0_IRQHandler
|
|
||||||
.type DMA0_IRQHandler, %function
|
|
||||||
DMA0_IRQHandler:
|
|
||||||
ldr r0,=DMA0_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size DMA0_IRQHandler, . - DMA0_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak GINT0_IRQHandler
|
|
||||||
.type GINT0_IRQHandler, %function
|
|
||||||
GINT0_IRQHandler:
|
|
||||||
ldr r0,=GINT0_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size GINT0_IRQHandler, . - GINT0_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak GINT1_IRQHandler
|
|
||||||
.type GINT1_IRQHandler, %function
|
|
||||||
GINT1_IRQHandler:
|
|
||||||
ldr r0,=GINT1_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size GINT1_IRQHandler, . - GINT1_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak PIN_INT0_IRQHandler
|
|
||||||
.type PIN_INT0_IRQHandler, %function
|
|
||||||
PIN_INT0_IRQHandler:
|
|
||||||
ldr r0,=PIN_INT0_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak PIN_INT1_IRQHandler
|
|
||||||
.type PIN_INT1_IRQHandler, %function
|
|
||||||
PIN_INT1_IRQHandler:
|
|
||||||
ldr r0,=PIN_INT1_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak PIN_INT2_IRQHandler
|
|
||||||
.type PIN_INT2_IRQHandler, %function
|
|
||||||
PIN_INT2_IRQHandler:
|
|
||||||
ldr r0,=PIN_INT2_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak PIN_INT3_IRQHandler
|
|
||||||
.type PIN_INT3_IRQHandler, %function
|
|
||||||
PIN_INT3_IRQHandler:
|
|
||||||
ldr r0,=PIN_INT3_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak UTICK0_IRQHandler
|
|
||||||
.type UTICK0_IRQHandler, %function
|
|
||||||
UTICK0_IRQHandler:
|
|
||||||
ldr r0,=UTICK0_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size UTICK0_IRQHandler, . - UTICK0_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak MRT0_IRQHandler
|
|
||||||
.type MRT0_IRQHandler, %function
|
|
||||||
MRT0_IRQHandler:
|
|
||||||
ldr r0,=MRT0_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size MRT0_IRQHandler, . - MRT0_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak CTIMER0_IRQHandler
|
|
||||||
.type CTIMER0_IRQHandler, %function
|
|
||||||
CTIMER0_IRQHandler:
|
|
||||||
ldr r0,=CTIMER0_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak CTIMER1_IRQHandler
|
|
||||||
.type CTIMER1_IRQHandler, %function
|
|
||||||
CTIMER1_IRQHandler:
|
|
||||||
ldr r0,=CTIMER1_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak SCT0_IRQHandler
|
|
||||||
.type SCT0_IRQHandler, %function
|
|
||||||
SCT0_IRQHandler:
|
|
||||||
ldr r0,=SCT0_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size SCT0_IRQHandler, . - SCT0_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak CTIMER3_IRQHandler
|
|
||||||
.type CTIMER3_IRQHandler, %function
|
|
||||||
CTIMER3_IRQHandler:
|
|
||||||
ldr r0,=CTIMER3_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak FLEXCOMM0_IRQHandler
|
|
||||||
.type FLEXCOMM0_IRQHandler, %function
|
|
||||||
FLEXCOMM0_IRQHandler:
|
|
||||||
ldr r0,=FLEXCOMM0_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak FLEXCOMM1_IRQHandler
|
|
||||||
.type FLEXCOMM1_IRQHandler, %function
|
|
||||||
FLEXCOMM1_IRQHandler:
|
|
||||||
ldr r0,=FLEXCOMM1_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak FLEXCOMM2_IRQHandler
|
|
||||||
.type FLEXCOMM2_IRQHandler, %function
|
|
||||||
FLEXCOMM2_IRQHandler:
|
|
||||||
ldr r0,=FLEXCOMM2_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak FLEXCOMM3_IRQHandler
|
|
||||||
.type FLEXCOMM3_IRQHandler, %function
|
|
||||||
FLEXCOMM3_IRQHandler:
|
|
||||||
ldr r0,=FLEXCOMM3_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak FLEXCOMM4_IRQHandler
|
|
||||||
.type FLEXCOMM4_IRQHandler, %function
|
|
||||||
FLEXCOMM4_IRQHandler:
|
|
||||||
ldr r0,=FLEXCOMM4_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak FLEXCOMM5_IRQHandler
|
|
||||||
.type FLEXCOMM5_IRQHandler, %function
|
|
||||||
FLEXCOMM5_IRQHandler:
|
|
||||||
ldr r0,=FLEXCOMM5_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak FLEXCOMM6_IRQHandler
|
|
||||||
.type FLEXCOMM6_IRQHandler, %function
|
|
||||||
FLEXCOMM6_IRQHandler:
|
|
||||||
ldr r0,=FLEXCOMM6_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak FLEXCOMM7_IRQHandler
|
|
||||||
.type FLEXCOMM7_IRQHandler, %function
|
|
||||||
FLEXCOMM7_IRQHandler:
|
|
||||||
ldr r0,=FLEXCOMM7_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak ADC0_IRQHandler
|
|
||||||
.type ADC0_IRQHandler, %function
|
|
||||||
ADC0_IRQHandler:
|
|
||||||
ldr r0,=ADC0_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size ADC0_IRQHandler, . - ADC0_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak Reserved39_IRQHandler
|
|
||||||
.type Reserved39_IRQHandler, %function
|
|
||||||
Reserved39_IRQHandler:
|
|
||||||
ldr r0,=Reserved39_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size Reserved39_IRQHandler, . - Reserved39_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak ACMP_IRQHandler
|
|
||||||
.type ACMP_IRQHandler, %function
|
|
||||||
ACMP_IRQHandler:
|
|
||||||
ldr r0,=ACMP_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size ACMP_IRQHandler, . - ACMP_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak Reserved41_IRQHandler
|
|
||||||
.type Reserved41_IRQHandler, %function
|
|
||||||
Reserved41_IRQHandler:
|
|
||||||
ldr r0,=Reserved41_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size Reserved41_IRQHandler, . - Reserved41_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak Reserved42_IRQHandler
|
|
||||||
.type Reserved42_IRQHandler, %function
|
|
||||||
Reserved42_IRQHandler:
|
|
||||||
ldr r0,=Reserved42_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size Reserved42_IRQHandler, . - Reserved42_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak USB0_NEEDCLK_IRQHandler
|
|
||||||
.type USB0_NEEDCLK_IRQHandler, %function
|
|
||||||
USB0_NEEDCLK_IRQHandler:
|
|
||||||
ldr r0,=USB0_NEEDCLK_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak USB0_IRQHandler
|
|
||||||
.type USB0_IRQHandler, %function
|
|
||||||
USB0_IRQHandler:
|
|
||||||
ldr r0,=USB0_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size USB0_IRQHandler, . - USB0_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak RTC_IRQHandler
|
|
||||||
.type RTC_IRQHandler, %function
|
|
||||||
RTC_IRQHandler:
|
|
||||||
ldr r0,=RTC_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size RTC_IRQHandler, . - RTC_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak Reserved46_IRQHandler
|
|
||||||
.type Reserved46_IRQHandler, %function
|
|
||||||
Reserved46_IRQHandler:
|
|
||||||
ldr r0,=Reserved46_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size Reserved46_IRQHandler, . - Reserved46_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak MAILBOX_IRQHandler
|
|
||||||
.type MAILBOX_IRQHandler, %function
|
|
||||||
MAILBOX_IRQHandler:
|
|
||||||
ldr r0,=MAILBOX_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak PIN_INT4_IRQHandler
|
|
||||||
.type PIN_INT4_IRQHandler, %function
|
|
||||||
PIN_INT4_IRQHandler:
|
|
||||||
ldr r0,=PIN_INT4_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak PIN_INT5_IRQHandler
|
|
||||||
.type PIN_INT5_IRQHandler, %function
|
|
||||||
PIN_INT5_IRQHandler:
|
|
||||||
ldr r0,=PIN_INT5_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak PIN_INT6_IRQHandler
|
|
||||||
.type PIN_INT6_IRQHandler, %function
|
|
||||||
PIN_INT6_IRQHandler:
|
|
||||||
ldr r0,=PIN_INT6_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak PIN_INT7_IRQHandler
|
|
||||||
.type PIN_INT7_IRQHandler, %function
|
|
||||||
PIN_INT7_IRQHandler:
|
|
||||||
ldr r0,=PIN_INT7_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak CTIMER2_IRQHandler
|
|
||||||
.type CTIMER2_IRQHandler, %function
|
|
||||||
CTIMER2_IRQHandler:
|
|
||||||
ldr r0,=CTIMER2_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak CTIMER4_IRQHandler
|
|
||||||
.type CTIMER4_IRQHandler, %function
|
|
||||||
CTIMER4_IRQHandler:
|
|
||||||
ldr r0,=CTIMER4_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak OS_EVENT_IRQHandler
|
|
||||||
.type OS_EVENT_IRQHandler, %function
|
|
||||||
OS_EVENT_IRQHandler:
|
|
||||||
ldr r0,=OS_EVENT_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak Reserved55_IRQHandler
|
|
||||||
.type Reserved55_IRQHandler, %function
|
|
||||||
Reserved55_IRQHandler:
|
|
||||||
ldr r0,=Reserved55_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size Reserved55_IRQHandler, . - Reserved55_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak Reserved56_IRQHandler
|
|
||||||
.type Reserved56_IRQHandler, %function
|
|
||||||
Reserved56_IRQHandler:
|
|
||||||
ldr r0,=Reserved56_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size Reserved56_IRQHandler, . - Reserved56_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak Reserved57_IRQHandler
|
|
||||||
.type Reserved57_IRQHandler, %function
|
|
||||||
Reserved57_IRQHandler:
|
|
||||||
ldr r0,=Reserved57_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size Reserved57_IRQHandler, . - Reserved57_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak SDIO_IRQHandler
|
|
||||||
.type SDIO_IRQHandler, %function
|
|
||||||
SDIO_IRQHandler:
|
|
||||||
ldr r0,=SDIO_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size SDIO_IRQHandler, . - SDIO_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak Reserved59_IRQHandler
|
|
||||||
.type Reserved59_IRQHandler, %function
|
|
||||||
Reserved59_IRQHandler:
|
|
||||||
ldr r0,=Reserved59_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size Reserved59_IRQHandler, . - Reserved59_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak Reserved60_IRQHandler
|
|
||||||
.type Reserved60_IRQHandler, %function
|
|
||||||
Reserved60_IRQHandler:
|
|
||||||
ldr r0,=Reserved60_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size Reserved60_IRQHandler, . - Reserved60_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak Reserved61_IRQHandler
|
|
||||||
.type Reserved61_IRQHandler, %function
|
|
||||||
Reserved61_IRQHandler:
|
|
||||||
ldr r0,=Reserved61_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size Reserved61_IRQHandler, . - Reserved61_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak USB1_UTMI_IRQHandler
|
|
||||||
.type USB1_UTMI_IRQHandler, %function
|
|
||||||
USB1_UTMI_IRQHandler:
|
|
||||||
ldr r0,=USB1_UTMI_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size USB1_UTMI_IRQHandler, . - USB1_UTMI_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak USB1_IRQHandler
|
|
||||||
.type USB1_IRQHandler, %function
|
|
||||||
USB1_IRQHandler:
|
|
||||||
ldr r0,=USB1_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size USB1_IRQHandler, . - USB1_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak USB1_NEEDCLK_IRQHandler
|
|
||||||
.type USB1_NEEDCLK_IRQHandler, %function
|
|
||||||
USB1_NEEDCLK_IRQHandler:
|
|
||||||
ldr r0,=USB1_NEEDCLK_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak SEC_HYPERVISOR_CALL_IRQHandler
|
|
||||||
.type SEC_HYPERVISOR_CALL_IRQHandler, %function
|
|
||||||
SEC_HYPERVISOR_CALL_IRQHandler:
|
|
||||||
ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak SEC_GPIO_INT0_IRQ0_IRQHandler
|
|
||||||
.type SEC_GPIO_INT0_IRQ0_IRQHandler, %function
|
|
||||||
SEC_GPIO_INT0_IRQ0_IRQHandler:
|
|
||||||
ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak SEC_GPIO_INT0_IRQ1_IRQHandler
|
|
||||||
.type SEC_GPIO_INT0_IRQ1_IRQHandler, %function
|
|
||||||
SEC_GPIO_INT0_IRQ1_IRQHandler:
|
|
||||||
ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak PLU_IRQHandler
|
|
||||||
.type PLU_IRQHandler, %function
|
|
||||||
PLU_IRQHandler:
|
|
||||||
ldr r0,=PLU_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size PLU_IRQHandler, . - PLU_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak SEC_VIO_IRQHandler
|
|
||||||
.type SEC_VIO_IRQHandler, %function
|
|
||||||
SEC_VIO_IRQHandler:
|
|
||||||
ldr r0,=SEC_VIO_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak HASHCRYPT_IRQHandler
|
|
||||||
.type HASHCRYPT_IRQHandler, %function
|
|
||||||
HASHCRYPT_IRQHandler:
|
|
||||||
ldr r0,=HASHCRYPT_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak CASER_IRQHandler
|
|
||||||
.type CASER_IRQHandler, %function
|
|
||||||
CASER_IRQHandler:
|
|
||||||
ldr r0,=CASER_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size CASER_IRQHandler, . - CASER_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak PUF_IRQHandler
|
|
||||||
.type PUF_IRQHandler, %function
|
|
||||||
PUF_IRQHandler:
|
|
||||||
ldr r0,=PUF_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size PUF_IRQHandler, . - PUF_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak PQ_IRQHandler
|
|
||||||
.type PQ_IRQHandler, %function
|
|
||||||
PQ_IRQHandler:
|
|
||||||
ldr r0,=PQ_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size PQ_IRQHandler, . - PQ_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak DMA1_IRQHandler
|
|
||||||
.type DMA1_IRQHandler, %function
|
|
||||||
DMA1_IRQHandler:
|
|
||||||
ldr r0,=DMA1_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size DMA1_IRQHandler, . - DMA1_IRQHandler
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
.thumb_func
|
|
||||||
.weak LSPI_HS_IRQHandler
|
|
||||||
.type LSPI_HS_IRQHandler, %function
|
|
||||||
LSPI_HS_IRQHandler:
|
|
||||||
ldr r0,=LSPI_HS_DriverIRQHandler
|
|
||||||
bx r0
|
|
||||||
.size LSPI_HS_IRQHandler, . - LSPI_HS_IRQHandler
|
|
||||||
|
|
||||||
/* Macro to define default handlers. Default handler
|
|
||||||
* will be weak symbol and just dead loops. They can be
|
|
||||||
* overwritten by other handlers */
|
|
||||||
.macro def_irq_handler handler_name
|
|
||||||
.weak \handler_name
|
|
||||||
.set \handler_name, DefaultISR
|
|
||||||
.endm
|
|
||||||
/* Exception Handlers */
|
|
||||||
def_irq_handler MemManage_Handler
|
|
||||||
def_irq_handler BusFault_Handler
|
|
||||||
def_irq_handler UsageFault_Handler
|
|
||||||
def_irq_handler DebugMon_Handler
|
|
||||||
def_irq_handler WDT_BOD_DriverIRQHandler
|
|
||||||
def_irq_handler DMA0_DriverIRQHandler
|
|
||||||
def_irq_handler GINT0_DriverIRQHandler
|
|
||||||
def_irq_handler GINT1_DriverIRQHandler
|
|
||||||
def_irq_handler PIN_INT0_DriverIRQHandler
|
|
||||||
def_irq_handler PIN_INT1_DriverIRQHandler
|
|
||||||
def_irq_handler PIN_INT2_DriverIRQHandler
|
|
||||||
def_irq_handler PIN_INT3_DriverIRQHandler
|
|
||||||
def_irq_handler UTICK0_DriverIRQHandler
|
|
||||||
def_irq_handler MRT0_DriverIRQHandler
|
|
||||||
def_irq_handler CTIMER0_DriverIRQHandler
|
|
||||||
def_irq_handler CTIMER1_DriverIRQHandler
|
|
||||||
def_irq_handler SCT0_DriverIRQHandler
|
|
||||||
def_irq_handler CTIMER3_DriverIRQHandler
|
|
||||||
def_irq_handler FLEXCOMM0_DriverIRQHandler
|
|
||||||
def_irq_handler FLEXCOMM1_DriverIRQHandler
|
|
||||||
def_irq_handler FLEXCOMM2_DriverIRQHandler
|
|
||||||
def_irq_handler FLEXCOMM3_DriverIRQHandler
|
|
||||||
def_irq_handler FLEXCOMM4_DriverIRQHandler
|
|
||||||
def_irq_handler FLEXCOMM5_DriverIRQHandler
|
|
||||||
def_irq_handler FLEXCOMM6_DriverIRQHandler
|
|
||||||
def_irq_handler FLEXCOMM7_DriverIRQHandler
|
|
||||||
def_irq_handler ADC0_DriverIRQHandler
|
|
||||||
def_irq_handler Reserved39_DriverIRQHandler
|
|
||||||
def_irq_handler ACMP_DriverIRQHandler
|
|
||||||
def_irq_handler Reserved41_DriverIRQHandler
|
|
||||||
def_irq_handler Reserved42_DriverIRQHandler
|
|
||||||
def_irq_handler USB0_NEEDCLK_DriverIRQHandler
|
|
||||||
def_irq_handler USB0_DriverIRQHandler
|
|
||||||
def_irq_handler RTC_DriverIRQHandler
|
|
||||||
def_irq_handler Reserved46_DriverIRQHandler
|
|
||||||
def_irq_handler MAILBOX_DriverIRQHandler
|
|
||||||
def_irq_handler PIN_INT4_DriverIRQHandler
|
|
||||||
def_irq_handler PIN_INT5_DriverIRQHandler
|
|
||||||
def_irq_handler PIN_INT6_DriverIRQHandler
|
|
||||||
def_irq_handler PIN_INT7_DriverIRQHandler
|
|
||||||
def_irq_handler CTIMER2_DriverIRQHandler
|
|
||||||
def_irq_handler CTIMER4_DriverIRQHandler
|
|
||||||
def_irq_handler OS_EVENT_DriverIRQHandler
|
|
||||||
def_irq_handler Reserved55_DriverIRQHandler
|
|
||||||
def_irq_handler Reserved56_DriverIRQHandler
|
|
||||||
def_irq_handler Reserved57_DriverIRQHandler
|
|
||||||
def_irq_handler SDIO_DriverIRQHandler
|
|
||||||
def_irq_handler Reserved59_DriverIRQHandler
|
|
||||||
def_irq_handler Reserved60_DriverIRQHandler
|
|
||||||
def_irq_handler Reserved61_DriverIRQHandler
|
|
||||||
def_irq_handler USB1_UTMI_DriverIRQHandler
|
|
||||||
def_irq_handler USB1_DriverIRQHandler
|
|
||||||
def_irq_handler USB1_NEEDCLK_DriverIRQHandler
|
|
||||||
def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler
|
|
||||||
def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler
|
|
||||||
def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler
|
|
||||||
def_irq_handler PLU_DriverIRQHandler
|
|
||||||
def_irq_handler SEC_VIO_DriverIRQHandler
|
|
||||||
def_irq_handler HASHCRYPT_DriverIRQHandler
|
|
||||||
def_irq_handler CASER_DriverIRQHandler
|
|
||||||
def_irq_handler PUF_DriverIRQHandler
|
|
||||||
def_irq_handler PQ_DriverIRQHandler
|
|
||||||
def_irq_handler DMA1_DriverIRQHandler
|
|
||||||
def_irq_handler LSPI_HS_DriverIRQHandler
|
|
||||||
|
|
||||||
.end
|
|
||||||
|
|
@ -1,156 +0,0 @@
|
||||||
/*
|
|
||||||
** ###################################################################
|
|
||||||
** Processors: LPC55S69JBD100_cm33_core0
|
|
||||||
** LPC55S69JET98_cm33_core0
|
|
||||||
**
|
|
||||||
** Compiler: IAR ANSI C/C++ Compiler for ARM
|
|
||||||
** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018
|
|
||||||
** Version: rev. 1.0, 2018-08-22
|
|
||||||
** Build: b180921
|
|
||||||
**
|
|
||||||
** Abstract:
|
|
||||||
** Linker file for the IAR ANSI C/C++ Compiler for ARM
|
|
||||||
**
|
|
||||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
|
||||||
** Copyright 2016-2018 NXP
|
|
||||||
** All rights reserved.
|
|
||||||
**
|
|
||||||
** SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
**
|
|
||||||
** http: www.nxp.com
|
|
||||||
** mail: support@nxp.com
|
|
||||||
**
|
|
||||||
** ###################################################################
|
|
||||||
*/
|
|
||||||
|
|
||||||
define symbol NS_CODE_START = 0x00030000;
|
|
||||||
define symbol NS_CODE_SIZE = 0x00068000;
|
|
||||||
define symbol NS_DATA_START = 0x20022000;
|
|
||||||
define symbol NS_DATA_SIZE = 0x00022000;
|
|
||||||
|
|
||||||
define symbol __ram_vector_table__ = 1;
|
|
||||||
|
|
||||||
if (!isdefinedsymbol(MBED_ROM_START)) {
|
|
||||||
define symbol MBED_ROM_START = NS_CODE_START;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!isdefinedsymbol(MBED_APP_START)) {
|
|
||||||
define symbol MBED_APP_START = MBED_ROM_START;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!isdefinedsymbol(MBED_ROM_SIZE)) {
|
|
||||||
define symbol MBED_ROM_SIZE = NS_CODE_SIZE;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!isdefinedsymbol(MBED_APP_SIZE)) {
|
|
||||||
define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!isdefinedsymbol(MBED_RAM_START)) {
|
|
||||||
define symbol MBED_RAM_START = NS_DATA_START;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!isdefinedsymbol(MBED_RAM_SIZE)) {
|
|
||||||
define symbol MBED_RAM_SIZE = NS_DATA_SIZE;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
|
|
||||||
define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
|
|
||||||
}
|
|
||||||
|
|
||||||
define symbol __stack_size__ = MBED_CONF_TARGET_BOOT_STACK_SIZE;
|
|
||||||
define symbol __heap_size__ = 0x4000;
|
|
||||||
|
|
||||||
define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000200 : 0;
|
|
||||||
define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000001FF : 0;
|
|
||||||
|
|
||||||
/* USB BDT size */
|
|
||||||
define symbol usb_bdt_size = 0x0;
|
|
||||||
|
|
||||||
/* Stack and Heap Sizes */
|
|
||||||
if (isdefinedsymbol(__stack_size__)) {
|
|
||||||
define symbol __size_cstack__ = __stack_size__;
|
|
||||||
} else {
|
|
||||||
define symbol __size_cstack__ = 0x0400;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (isdefinedsymbol(__heap_size__)) {
|
|
||||||
define symbol __size_heap__ = __heap_size__;
|
|
||||||
} else {
|
|
||||||
define symbol __size_heap__ = 0x0400;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!isdefinedsymbol(NVIC_INTERRUPT_NUM)) {
|
|
||||||
define symbol NVIC_INTERRUPT_NUM = 60;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!isdefinedsymbol(EXCEPTION_VECT_NUM)) {
|
|
||||||
define symbol EXCEPTION_VECT_NUM = 16;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!isdefinedsymbol(MEMORY_ADDR_SIZE_IN_BYTE)) {
|
|
||||||
define symbol MEMORY_ADDR_SIZE_IN_BYTE = 4;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!isdefinedsymbol(MBED_INTERRUPTS_SIZE)) {
|
|
||||||
define symbol MBED_INTERRUPTS_SIZE = ((NVIC_INTERRUPT_NUM + EXCEPTION_VECT_NUM) * MEMORY_ADDR_SIZE_IN_BYTE);
|
|
||||||
}
|
|
||||||
|
|
||||||
define symbol m_interrupts_start = MBED_APP_START;
|
|
||||||
define symbol m_interrupts_end = (MBED_APP_START + (MBED_INTERRUPTS_SIZE - 1));
|
|
||||||
|
|
||||||
define symbol m_text_start = (MBED_APP_START + MBED_INTERRUPTS_SIZE);
|
|
||||||
define symbol m_text_end = (MBED_APP_START + MBED_APP_SIZE - 1);
|
|
||||||
|
|
||||||
define symbol m_interrupts_ram_start = MBED_RAM_START;
|
|
||||||
define symbol m_interrupts_ram_end = (MBED_RAM_START + __ram_vector_table_size__ - 1);
|
|
||||||
|
|
||||||
define symbol m_data_start = (m_interrupts_ram_start + __ram_vector_table_size__);
|
|
||||||
define symbol m_data_end = (MBED_RAM_START + MBED_RAM_SIZE - 1);
|
|
||||||
|
|
||||||
define symbol m_usb_sram_start = 0x40100000;
|
|
||||||
define symbol m_usb_sram_end = 0x00004000;
|
|
||||||
|
|
||||||
|
|
||||||
define exported symbol __VECTOR_TABLE = m_interrupts_start;
|
|
||||||
define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
|
|
||||||
define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
|
|
||||||
|
|
||||||
define memory mem with size = 4G;
|
|
||||||
|
|
||||||
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
|
|
||||||
| mem:[from m_text_start to m_text_end];
|
|
||||||
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
|
|
||||||
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
|
|
||||||
|
|
||||||
define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
|
|
||||||
|
|
||||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
|
||||||
define block HEAP with expanding size, alignment = 8, minimum size = __heap_size__ { };
|
|
||||||
define block RW { readwrite };
|
|
||||||
define block ZI { zi };
|
|
||||||
|
|
||||||
/* regions for USB */
|
|
||||||
define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1];
|
|
||||||
define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end];
|
|
||||||
place in USB_BDT_region { section m_usb_bdt };
|
|
||||||
place in USB_SRAM_region { section m_usb_global };
|
|
||||||
|
|
||||||
initialize by copy { readwrite, section .textrw };
|
|
||||||
|
|
||||||
if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
|
|
||||||
{
|
|
||||||
/* Required in a multi-threaded application */
|
|
||||||
initialize by copy with packing = none { section __DLIB_PERTHREAD };
|
|
||||||
}
|
|
||||||
|
|
||||||
do not initialize { section .noinit, section m_usb_bdt, section m_usb_global };
|
|
||||||
|
|
||||||
place at address mem: m_interrupts_start { readonly section .intvec };
|
|
||||||
place in TEXT_region { readonly };
|
|
||||||
place in DATA_region { block RW };
|
|
||||||
place in DATA_region { block ZI };
|
|
||||||
place in DATA_region { last block HEAP };
|
|
||||||
place in CSTACK_region { block CSTACK };
|
|
||||||
place in m_interrupts_ram_region { section m_interrupts_ram };
|
|
||||||
|
|
||||||
|
|
@ -1,622 +0,0 @@
|
||||||
;/*****************************************************************************
|
|
||||||
; * @file: startup_LPC55S69_cm33_core0.s
|
|
||||||
; * @purpose: CMSIS Cortex-M33 Core Device Startup File
|
|
||||||
; * LPC55S69_cm33_core0
|
|
||||||
; * @version: 1.0
|
|
||||||
; * @date: 2018-8-22
|
|
||||||
; *----------------------------------------------------------------------------
|
|
||||||
; *
|
|
||||||
; Copyright 1997-2016 Freescale Semiconductor, Inc.
|
|
||||||
; Copyright 2016-2019 NXP
|
|
||||||
; All rights reserved.
|
|
||||||
;
|
|
||||||
; SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
;
|
|
||||||
; The modules in this file are included in the libraries, and may be replaced
|
|
||||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
|
||||||
; a user defined start symbol.
|
|
||||||
; To override the cstartup defined in the library, simply add your modified
|
|
||||||
; version to the workbench project.
|
|
||||||
;
|
|
||||||
; The vector table is normally located at address 0.
|
|
||||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
|
||||||
; The name "__vector_table" has special meaning for C-SPY:
|
|
||||||
; it is where the SP start value is found, and the NVIC vector
|
|
||||||
; table register (VTOR) is initialized to this address if != 0.
|
|
||||||
;
|
|
||||||
; Cortex-M version
|
|
||||||
;
|
|
||||||
|
|
||||||
MODULE ?cstartup
|
|
||||||
|
|
||||||
;; Forward declaration of sections.
|
|
||||||
SECTION CSTACK:DATA:NOROOT(3)
|
|
||||||
|
|
||||||
SECTION .intvec:CODE:NOROOT(2)
|
|
||||||
|
|
||||||
EXTERN __iar_program_start
|
|
||||||
EXTERN SystemInit
|
|
||||||
PUBLIC __vector_table
|
|
||||||
PUBLIC __vector_table_0x1c
|
|
||||||
PUBLIC __Vectors
|
|
||||||
PUBLIC __Vectors_End
|
|
||||||
PUBLIC __Vectors_Size
|
|
||||||
|
|
||||||
DATA
|
|
||||||
|
|
||||||
__vector_table
|
|
||||||
DCD sfe(CSTACK)
|
|
||||||
DCD Reset_Handler
|
|
||||||
|
|
||||||
DCD NMI_Handler
|
|
||||||
DCD HardFault_Handler
|
|
||||||
DCD MemManage_Handler
|
|
||||||
DCD BusFault_Handler
|
|
||||||
DCD UsageFault_Handler
|
|
||||||
__vector_table_0x1c
|
|
||||||
DCD 0
|
|
||||||
DCD 0
|
|
||||||
DCD 0
|
|
||||||
DCD 0
|
|
||||||
DCD SVC_Handler
|
|
||||||
DCD DebugMon_Handler
|
|
||||||
DCD 0
|
|
||||||
DCD PendSV_Handler
|
|
||||||
DCD SysTick_Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt
|
|
||||||
DCD DMA0_IRQHandler ; DMA0 controller
|
|
||||||
DCD GINT0_IRQHandler ; GPIO group 0
|
|
||||||
DCD GINT1_IRQHandler ; GPIO group 1
|
|
||||||
DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0
|
|
||||||
DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1
|
|
||||||
DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2
|
|
||||||
DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3
|
|
||||||
DCD UTICK0_IRQHandler ; Micro-tick Timer
|
|
||||||
DCD MRT0_IRQHandler ; Multi-rate timer
|
|
||||||
DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0
|
|
||||||
DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1
|
|
||||||
DCD SCT0_IRQHandler ; SCTimer/PWM
|
|
||||||
DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3
|
|
||||||
DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM)
|
|
||||||
DCD ADC0_IRQHandler ; ADC0
|
|
||||||
DCD Reserved39_IRQHandler ; Reserved interrupt
|
|
||||||
DCD ACMP_IRQHandler ; ACMP interrupts
|
|
||||||
DCD Reserved41_IRQHandler ; Reserved interrupt
|
|
||||||
DCD Reserved42_IRQHandler ; Reserved interrupt
|
|
||||||
DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt
|
|
||||||
DCD USB0_IRQHandler ; USB device
|
|
||||||
DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts
|
|
||||||
DCD Reserved46_IRQHandler ; Reserved interrupt
|
|
||||||
DCD MAILBOX_IRQHandler ; WAKEUP,Mailbox interrupt (present on selected devices)
|
|
||||||
DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int
|
|
||||||
DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int
|
|
||||||
DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int
|
|
||||||
DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int
|
|
||||||
DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2
|
|
||||||
DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4
|
|
||||||
DCD OS_EVENT_IRQHandler ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts
|
|
||||||
DCD Reserved55_IRQHandler ; Reserved interrupt
|
|
||||||
DCD Reserved56_IRQHandler ; Reserved interrupt
|
|
||||||
DCD Reserved57_IRQHandler ; Reserved interrupt
|
|
||||||
DCD SDIO_IRQHandler ; SD/MMC
|
|
||||||
DCD Reserved59_IRQHandler ; Reserved interrupt
|
|
||||||
DCD Reserved60_IRQHandler ; Reserved interrupt
|
|
||||||
DCD Reserved61_IRQHandler ; Reserved interrupt
|
|
||||||
DCD USB1_UTMI_IRQHandler ; USB1_UTMI
|
|
||||||
DCD USB1_IRQHandler ; USB1 interrupt
|
|
||||||
DCD USB1_NEEDCLK_IRQHandler ; USB1 activity
|
|
||||||
DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt
|
|
||||||
DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt
|
|
||||||
DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt
|
|
||||||
DCD PLU_IRQHandler ; PLU interrupt
|
|
||||||
DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt
|
|
||||||
DCD HASHCRYPT_IRQHandler ; HASHCRYPT interrupt
|
|
||||||
DCD CASER_IRQHandler ; CASPER interrupt
|
|
||||||
DCD PUF_IRQHandler ; PUF interrupt
|
|
||||||
DCD PQ_IRQHandler ; PQ interrupt
|
|
||||||
DCD DMA1_IRQHandler ; DMA1 interrupt
|
|
||||||
DCD LSPI_HS_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM)
|
|
||||||
__Vectors_End
|
|
||||||
|
|
||||||
|
|
||||||
__Vectors EQU __vector_table
|
|
||||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
|
||||||
|
|
||||||
|
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
||||||
;;
|
|
||||||
;; Default interrupt handlers.
|
|
||||||
;;
|
|
||||||
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
PUBWEAK Reset_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
Reset_Handler
|
|
||||||
CPSID I ; Mask interrupts
|
|
||||||
LDR R0, =sfb(CSTACK)
|
|
||||||
MSR MSPLIM, R0
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
CPSIE I ; Unmask interrupts
|
|
||||||
LDR R0, =__iar_program_start
|
|
||||||
BX R0
|
|
||||||
|
|
||||||
PUBWEAK NMI_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
NMI_Handler
|
|
||||||
B .
|
|
||||||
|
|
||||||
PUBWEAK HardFault_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
HardFault_Handler
|
|
||||||
B .
|
|
||||||
|
|
||||||
PUBWEAK MemManage_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
MemManage_Handler
|
|
||||||
B .
|
|
||||||
|
|
||||||
PUBWEAK BusFault_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
BusFault_Handler
|
|
||||||
B .
|
|
||||||
|
|
||||||
PUBWEAK UsageFault_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
UsageFault_Handler
|
|
||||||
B .
|
|
||||||
|
|
||||||
PUBWEAK SVC_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
SVC_Handler
|
|
||||||
B .
|
|
||||||
|
|
||||||
PUBWEAK DebugMon_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
DebugMon_Handler
|
|
||||||
B .
|
|
||||||
|
|
||||||
PUBWEAK PendSV_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
PendSV_Handler
|
|
||||||
B .
|
|
||||||
|
|
||||||
PUBWEAK SysTick_Handler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
|
||||||
SysTick_Handler
|
|
||||||
B .
|
|
||||||
|
|
||||||
PUBWEAK WDT_BOD_IRQHandler
|
|
||||||
PUBWEAK WDT_BOD_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
WDT_BOD_IRQHandler
|
|
||||||
LDR R0, =WDT_BOD_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK DMA0_IRQHandler
|
|
||||||
PUBWEAK DMA0_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
DMA0_IRQHandler
|
|
||||||
LDR R0, =DMA0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK GINT0_IRQHandler
|
|
||||||
PUBWEAK GINT0_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
GINT0_IRQHandler
|
|
||||||
LDR R0, =GINT0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK GINT1_IRQHandler
|
|
||||||
PUBWEAK GINT1_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
GINT1_IRQHandler
|
|
||||||
LDR R0, =GINT1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK PIN_INT0_IRQHandler
|
|
||||||
PUBWEAK PIN_INT0_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
PIN_INT0_IRQHandler
|
|
||||||
LDR R0, =PIN_INT0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK PIN_INT1_IRQHandler
|
|
||||||
PUBWEAK PIN_INT1_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
PIN_INT1_IRQHandler
|
|
||||||
LDR R0, =PIN_INT1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK PIN_INT2_IRQHandler
|
|
||||||
PUBWEAK PIN_INT2_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
PIN_INT2_IRQHandler
|
|
||||||
LDR R0, =PIN_INT2_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK PIN_INT3_IRQHandler
|
|
||||||
PUBWEAK PIN_INT3_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
PIN_INT3_IRQHandler
|
|
||||||
LDR R0, =PIN_INT3_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK UTICK0_IRQHandler
|
|
||||||
PUBWEAK UTICK0_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
UTICK0_IRQHandler
|
|
||||||
LDR R0, =UTICK0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK MRT0_IRQHandler
|
|
||||||
PUBWEAK MRT0_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
MRT0_IRQHandler
|
|
||||||
LDR R0, =MRT0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK CTIMER0_IRQHandler
|
|
||||||
PUBWEAK CTIMER0_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
CTIMER0_IRQHandler
|
|
||||||
LDR R0, =CTIMER0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK CTIMER1_IRQHandler
|
|
||||||
PUBWEAK CTIMER1_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
CTIMER1_IRQHandler
|
|
||||||
LDR R0, =CTIMER1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK SCT0_IRQHandler
|
|
||||||
PUBWEAK SCT0_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
SCT0_IRQHandler
|
|
||||||
LDR R0, =SCT0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK CTIMER3_IRQHandler
|
|
||||||
PUBWEAK CTIMER3_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
CTIMER3_IRQHandler
|
|
||||||
LDR R0, =CTIMER3_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK FLEXCOMM0_IRQHandler
|
|
||||||
PUBWEAK FLEXCOMM0_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
FLEXCOMM0_IRQHandler
|
|
||||||
LDR R0, =FLEXCOMM0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK FLEXCOMM1_IRQHandler
|
|
||||||
PUBWEAK FLEXCOMM1_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
FLEXCOMM1_IRQHandler
|
|
||||||
LDR R0, =FLEXCOMM1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK FLEXCOMM2_IRQHandler
|
|
||||||
PUBWEAK FLEXCOMM2_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
FLEXCOMM2_IRQHandler
|
|
||||||
LDR R0, =FLEXCOMM2_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK FLEXCOMM3_IRQHandler
|
|
||||||
PUBWEAK FLEXCOMM3_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
FLEXCOMM3_IRQHandler
|
|
||||||
LDR R0, =FLEXCOMM3_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK FLEXCOMM4_IRQHandler
|
|
||||||
PUBWEAK FLEXCOMM4_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
FLEXCOMM4_IRQHandler
|
|
||||||
LDR R0, =FLEXCOMM4_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK FLEXCOMM5_IRQHandler
|
|
||||||
PUBWEAK FLEXCOMM5_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
FLEXCOMM5_IRQHandler
|
|
||||||
LDR R0, =FLEXCOMM5_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK FLEXCOMM6_IRQHandler
|
|
||||||
PUBWEAK FLEXCOMM6_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
FLEXCOMM6_IRQHandler
|
|
||||||
LDR R0, =FLEXCOMM6_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK FLEXCOMM7_IRQHandler
|
|
||||||
PUBWEAK FLEXCOMM7_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
FLEXCOMM7_IRQHandler
|
|
||||||
LDR R0, =FLEXCOMM7_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK ADC0_IRQHandler
|
|
||||||
PUBWEAK ADC0_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
ADC0_IRQHandler
|
|
||||||
LDR R0, =ADC0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK Reserved39_IRQHandler
|
|
||||||
PUBWEAK Reserved39_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
Reserved39_IRQHandler
|
|
||||||
LDR R0, =Reserved39_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK ACMP_IRQHandler
|
|
||||||
PUBWEAK ACMP_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
ACMP_IRQHandler
|
|
||||||
LDR R0, =ACMP_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK Reserved41_IRQHandler
|
|
||||||
PUBWEAK Reserved41_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
Reserved41_IRQHandler
|
|
||||||
LDR R0, =Reserved41_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK Reserved42_IRQHandler
|
|
||||||
PUBWEAK Reserved42_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
Reserved42_IRQHandler
|
|
||||||
LDR R0, =Reserved42_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK USB0_NEEDCLK_IRQHandler
|
|
||||||
PUBWEAK USB0_NEEDCLK_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
USB0_NEEDCLK_IRQHandler
|
|
||||||
LDR R0, =USB0_NEEDCLK_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK USB0_IRQHandler
|
|
||||||
PUBWEAK USB0_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
USB0_IRQHandler
|
|
||||||
LDR R0, =USB0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK RTC_IRQHandler
|
|
||||||
PUBWEAK RTC_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
RTC_IRQHandler
|
|
||||||
LDR R0, =RTC_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK Reserved46_IRQHandler
|
|
||||||
PUBWEAK Reserved46_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
Reserved46_IRQHandler
|
|
||||||
LDR R0, =Reserved46_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK MAILBOX_IRQHandler
|
|
||||||
PUBWEAK MAILBOX_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
MAILBOX_IRQHandler
|
|
||||||
LDR R0, =MAILBOX_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK PIN_INT4_IRQHandler
|
|
||||||
PUBWEAK PIN_INT4_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
PIN_INT4_IRQHandler
|
|
||||||
LDR R0, =PIN_INT4_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK PIN_INT5_IRQHandler
|
|
||||||
PUBWEAK PIN_INT5_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
PIN_INT5_IRQHandler
|
|
||||||
LDR R0, =PIN_INT5_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK PIN_INT6_IRQHandler
|
|
||||||
PUBWEAK PIN_INT6_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
PIN_INT6_IRQHandler
|
|
||||||
LDR R0, =PIN_INT6_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK PIN_INT7_IRQHandler
|
|
||||||
PUBWEAK PIN_INT7_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
PIN_INT7_IRQHandler
|
|
||||||
LDR R0, =PIN_INT7_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK CTIMER2_IRQHandler
|
|
||||||
PUBWEAK CTIMER2_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
CTIMER2_IRQHandler
|
|
||||||
LDR R0, =CTIMER2_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK CTIMER4_IRQHandler
|
|
||||||
PUBWEAK CTIMER4_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
CTIMER4_IRQHandler
|
|
||||||
LDR R0, =CTIMER4_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK OS_EVENT_IRQHandler
|
|
||||||
PUBWEAK OS_EVENT_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
OS_EVENT_IRQHandler
|
|
||||||
LDR R0, =OS_EVENT_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK Reserved55_IRQHandler
|
|
||||||
PUBWEAK Reserved55_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
Reserved55_IRQHandler
|
|
||||||
LDR R0, =Reserved55_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK Reserved56_IRQHandler
|
|
||||||
PUBWEAK Reserved56_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
Reserved56_IRQHandler
|
|
||||||
LDR R0, =Reserved56_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK Reserved57_IRQHandler
|
|
||||||
PUBWEAK Reserved57_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
Reserved57_IRQHandler
|
|
||||||
LDR R0, =Reserved57_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK SDIO_IRQHandler
|
|
||||||
PUBWEAK SDIO_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
SDIO_IRQHandler
|
|
||||||
LDR R0, =SDIO_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK Reserved59_IRQHandler
|
|
||||||
PUBWEAK Reserved59_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
Reserved59_IRQHandler
|
|
||||||
LDR R0, =Reserved59_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK Reserved60_IRQHandler
|
|
||||||
PUBWEAK Reserved60_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
Reserved60_IRQHandler
|
|
||||||
LDR R0, =Reserved60_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK Reserved61_IRQHandler
|
|
||||||
PUBWEAK Reserved61_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
Reserved61_IRQHandler
|
|
||||||
LDR R0, =Reserved61_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK USB1_UTMI_IRQHandler
|
|
||||||
PUBWEAK USB1_UTMI_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
USB1_UTMI_IRQHandler
|
|
||||||
LDR R0, =USB1_UTMI_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK USB1_IRQHandler
|
|
||||||
PUBWEAK USB1_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
USB1_IRQHandler
|
|
||||||
LDR R0, =USB1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK USB1_NEEDCLK_IRQHandler
|
|
||||||
PUBWEAK USB1_NEEDCLK_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
USB1_NEEDCLK_IRQHandler
|
|
||||||
LDR R0, =USB1_NEEDCLK_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK SEC_HYPERVISOR_CALL_IRQHandler
|
|
||||||
PUBWEAK SEC_HYPERVISOR_CALL_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
SEC_HYPERVISOR_CALL_IRQHandler
|
|
||||||
LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK SEC_GPIO_INT0_IRQ0_IRQHandler
|
|
||||||
PUBWEAK SEC_GPIO_INT0_IRQ0_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
SEC_GPIO_INT0_IRQ0_IRQHandler
|
|
||||||
LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK SEC_GPIO_INT0_IRQ1_IRQHandler
|
|
||||||
PUBWEAK SEC_GPIO_INT0_IRQ1_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
SEC_GPIO_INT0_IRQ1_IRQHandler
|
|
||||||
LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK PLU_IRQHandler
|
|
||||||
PUBWEAK PLU_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
PLU_IRQHandler
|
|
||||||
LDR R0, =PLU_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK SEC_VIO_IRQHandler
|
|
||||||
PUBWEAK SEC_VIO_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
SEC_VIO_IRQHandler
|
|
||||||
LDR R0, =SEC_VIO_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK HASHCRYPT_IRQHandler
|
|
||||||
PUBWEAK HASHCRYPT_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
HASHCRYPT_IRQHandler
|
|
||||||
LDR R0, =HASHCRYPT_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK CASER_IRQHandler
|
|
||||||
PUBWEAK CASER_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
CASER_IRQHandler
|
|
||||||
LDR R0, =CASER_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK PUF_IRQHandler
|
|
||||||
PUBWEAK PUF_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
PUF_IRQHandler
|
|
||||||
LDR R0, =PUF_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK PQ_IRQHandler
|
|
||||||
PUBWEAK PQ_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
PQ_IRQHandler
|
|
||||||
LDR R0, =PQ_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK DMA1_IRQHandler
|
|
||||||
PUBWEAK DMA1_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
DMA1_IRQHandler
|
|
||||||
LDR R0, =DMA1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
PUBWEAK LSPI_HS_IRQHandler
|
|
||||||
PUBWEAK LSPI_HS_DriverIRQHandler
|
|
||||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
|
||||||
LSPI_HS_IRQHandler
|
|
||||||
LDR R0, =LSPI_HS_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
WDT_BOD_DriverIRQHandler
|
|
||||||
DMA0_DriverIRQHandler
|
|
||||||
GINT0_DriverIRQHandler
|
|
||||||
GINT1_DriverIRQHandler
|
|
||||||
PIN_INT0_DriverIRQHandler
|
|
||||||
PIN_INT1_DriverIRQHandler
|
|
||||||
PIN_INT2_DriverIRQHandler
|
|
||||||
PIN_INT3_DriverIRQHandler
|
|
||||||
UTICK0_DriverIRQHandler
|
|
||||||
MRT0_DriverIRQHandler
|
|
||||||
CTIMER0_DriverIRQHandler
|
|
||||||
CTIMER1_DriverIRQHandler
|
|
||||||
SCT0_DriverIRQHandler
|
|
||||||
CTIMER3_DriverIRQHandler
|
|
||||||
FLEXCOMM0_DriverIRQHandler
|
|
||||||
FLEXCOMM1_DriverIRQHandler
|
|
||||||
FLEXCOMM2_DriverIRQHandler
|
|
||||||
FLEXCOMM3_DriverIRQHandler
|
|
||||||
FLEXCOMM4_DriverIRQHandler
|
|
||||||
FLEXCOMM5_DriverIRQHandler
|
|
||||||
FLEXCOMM6_DriverIRQHandler
|
|
||||||
FLEXCOMM7_DriverIRQHandler
|
|
||||||
ADC0_DriverIRQHandler
|
|
||||||
Reserved39_DriverIRQHandler
|
|
||||||
ACMP_DriverIRQHandler
|
|
||||||
Reserved41_DriverIRQHandler
|
|
||||||
Reserved42_DriverIRQHandler
|
|
||||||
USB0_NEEDCLK_DriverIRQHandler
|
|
||||||
USB0_DriverIRQHandler
|
|
||||||
RTC_DriverIRQHandler
|
|
||||||
Reserved46_DriverIRQHandler
|
|
||||||
MAILBOX_DriverIRQHandler
|
|
||||||
PIN_INT4_DriverIRQHandler
|
|
||||||
PIN_INT5_DriverIRQHandler
|
|
||||||
PIN_INT6_DriverIRQHandler
|
|
||||||
PIN_INT7_DriverIRQHandler
|
|
||||||
CTIMER2_DriverIRQHandler
|
|
||||||
CTIMER4_DriverIRQHandler
|
|
||||||
OS_EVENT_DriverIRQHandler
|
|
||||||
Reserved55_DriverIRQHandler
|
|
||||||
Reserved56_DriverIRQHandler
|
|
||||||
Reserved57_DriverIRQHandler
|
|
||||||
SDIO_DriverIRQHandler
|
|
||||||
Reserved59_DriverIRQHandler
|
|
||||||
Reserved60_DriverIRQHandler
|
|
||||||
Reserved61_DriverIRQHandler
|
|
||||||
USB1_UTMI_DriverIRQHandler
|
|
||||||
USB1_DriverIRQHandler
|
|
||||||
USB1_NEEDCLK_DriverIRQHandler
|
|
||||||
SEC_HYPERVISOR_CALL_DriverIRQHandler
|
|
||||||
SEC_GPIO_INT0_IRQ0_DriverIRQHandler
|
|
||||||
SEC_GPIO_INT0_IRQ1_DriverIRQHandler
|
|
||||||
PLU_DriverIRQHandler
|
|
||||||
SEC_VIO_DriverIRQHandler
|
|
||||||
HASHCRYPT_DriverIRQHandler
|
|
||||||
CASER_DriverIRQHandler
|
|
||||||
PUF_DriverIRQHandler
|
|
||||||
PQ_DriverIRQHandler
|
|
||||||
DMA1_DriverIRQHandler
|
|
||||||
LSPI_HS_DriverIRQHandler
|
|
||||||
DefaultISR
|
|
||||||
B .
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
@ -1,46 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* CMSIS-style functionality to support dynamic vectors
|
|
||||||
*******************************************************************************
|
|
||||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_NVIC_H
|
|
||||||
#define MBED_CMSIS_NVIC_H
|
|
||||||
|
|
||||||
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
|
||||||
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
|
||||||
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
|
||||||
#else
|
|
||||||
extern uint32_t __VECTOR_RAM[];
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Symbols defined by the linker script */
|
|
||||||
#define NVIC_NUM_VECTORS (16 + 60) // CORE + MCU Peripherals
|
|
||||||
#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,61 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2018 Arm Limited
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
|
|
||||||
#ifndef NVIC_VIRTUAL_H
|
|
||||||
#define NVIC_VIRTUAL_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* NVIC functions */
|
|
||||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
|
||||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
|
||||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
|
||||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
|
||||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
|
||||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
|
||||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
|
||||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
|
||||||
#define NVIC_GetActive __NVIC_GetActive
|
|
||||||
#define NVIC_SetPriority __NVIC_SetPriority
|
|
||||||
#define NVIC_GetPriority __NVIC_GetPriority
|
|
||||||
#if MBED_CONF_PSA_PRESENT
|
|
||||||
#define NVIC_SystemReset __NVIC_TFMSystemReset
|
|
||||||
#else
|
|
||||||
#define NVIC_SystemReset __NVIC_SystemReset
|
|
||||||
#endif // MBED_CONF_PSA_PRESENT
|
|
||||||
|
|
||||||
|
|
||||||
#if MBED_CONF_PSA_PRESENT
|
|
||||||
/**
|
|
||||||
* \brief Overriding the default CMSIS system reset implementation by calling
|
|
||||||
* secure TFM service.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void __NVIC_TFMSystemReset(void);
|
|
||||||
|
|
||||||
#endif // MBED_CONF_PSA_PRESENT
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,49 +0,0 @@
|
||||||
Permissive Binary License
|
|
||||||
|
|
||||||
Version 1.0, December 2018
|
|
||||||
|
|
||||||
Redistribution. Redistribution and use in binary form, without
|
|
||||||
modification, are permitted provided that the following conditions are
|
|
||||||
met:
|
|
||||||
|
|
||||||
1) Redistributions must reproduce the above copyright notice and the
|
|
||||||
following disclaimer in the documentation and/or other materials
|
|
||||||
provided with the distribution.
|
|
||||||
|
|
||||||
2) Unless to the extent explicitly permitted by law, no reverse
|
|
||||||
engineering, decompilation, or disassembly of this software is
|
|
||||||
permitted.
|
|
||||||
|
|
||||||
3) Redistribution as part of a software development kit must include the
|
|
||||||
accompanying file named DEPENDENCIES and any dependencies listed in
|
|
||||||
that file.
|
|
||||||
|
|
||||||
4) Neither the name of the copyright holder nor the names of its
|
|
||||||
contributors may be used to endorse or promote products derived from
|
|
||||||
this software without specific prior written permission.
|
|
||||||
|
|
||||||
Limited patent license. The copyright holders (and contributors) grant a
|
|
||||||
worldwide, non-exclusive, no-charge, royalty-free patent license to
|
|
||||||
make, have made, use, offer to sell, sell, import, and otherwise
|
|
||||||
transfer this software, where such license applies only to those patent
|
|
||||||
claims licensable by the copyright holders (and contributors) that are
|
|
||||||
necessarily infringed by this software. This patent license shall not
|
|
||||||
apply to any combinations that include this software. No hardware is
|
|
||||||
licensed hereunder.
|
|
||||||
|
|
||||||
If you institute patent litigation against any entity (including a
|
|
||||||
cross-claim or counterclaim in a lawsuit) alleging that the software
|
|
||||||
itself infringes your patent(s), then your rights granted under this
|
|
||||||
license shall terminate as of the date such litigation is filed.
|
|
||||||
|
|
||||||
DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
|
|
||||||
CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
||||||
HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
||||||
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
|
|
||||||
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
|
||||||
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
|
||||||
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
|
|
@ -1,39 +0,0 @@
|
||||||
# LPC55S69_NS prebuilt secure binaries
|
|
||||||
|
|
||||||
This directory tree contains Secure images released under Permissive Binary License.
|
|
||||||
|
|
||||||
Built by mbed-cli using ARM Compiler 6.10.1
|
|
||||||
|
|
||||||
These images were compiled by the following command:
|
|
||||||
|
|
||||||
## tfm.bin
|
|
||||||
|
|
||||||
```sh
|
|
||||||
mbed compile -t ARMC6 -m LPC55S69_S --app-config mbed-os/tools/psa/tfm/mbed_app.json --profile release
|
|
||||||
```
|
|
||||||
|
|
||||||
## spm_smoke.bin
|
|
||||||
|
|
||||||
```sh
|
|
||||||
mbed test --compile -t ARMC6 -m LPC55S69_S --app-config mbed-os/tools/psa/tfm/mbed_app.json -n mbed-os-tests-psa-spm_smoke -DUSE_PSA_TEST_PARTITIONS -DUSE_SMOKE_TESTS_PART1 --profile release
|
|
||||||
```
|
|
||||||
|
|
||||||
## spm_client.bin
|
|
||||||
|
|
||||||
```sh
|
|
||||||
mbed test --compile -t ARMC6 -m LPC55S69_S --app-config mbed-os/tools/psa/tfm/mbed_app.json -n mbed-os-tests-psa-spm_client -DUSE_PSA_TEST_PARTITIONS -DUSE_CLIENT_TESTS_PART1 --profile release
|
|
||||||
```
|
|
||||||
|
|
||||||
## spm_server.bin
|
|
||||||
|
|
||||||
```sh
|
|
||||||
mbed test --compile -t ARMC6 -m LPC55S69_S --app-config mbed-os/tools/psa/tfm/mbed_app.json -n mbed-os-tests-psa-spm_server -DUSE_PSA_TEST_PARTITIONS -DUSE_SERVER_TESTS_PART1 -DUSE_SERVER_TESTS_PART2 --profile release
|
|
||||||
```
|
|
||||||
|
|
||||||
## crypto_access_control.bin
|
|
||||||
|
|
||||||
```sh
|
|
||||||
mbed test --compile -t ARMC6 -m LPC55S69_S --app-config mbed-os/tools/psa/tfm/mbed_app.json -n mbed-os-tests-psa-crypto_access_control -DUSE_PSA_TEST_PARTITIONS -DUSE_CRYPTO_ACL_TEST --profile release
|
|
||||||
```
|
|
||||||
|
|
||||||
To update the prebuilt binaries run the previous commands.
|
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,277 +0,0 @@
|
||||||
#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Copyright (c) 2018 ARM Limited
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "../../../partition/region_defs.h"
|
|
||||||
|
|
||||||
#if !defined(TFM_LVL)
|
|
||||||
#define TFM_LVL 1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_ROM_START)
|
|
||||||
#define MBED_ROM_START S_CODE_START
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_ROM_SIZE)
|
|
||||||
#define MBED_ROM_SIZE IMAGE_CODE_SIZE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_RAM_START)
|
|
||||||
#define MBED_RAM_START S_DATA_START
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MBED_RAM_SIZE)
|
|
||||||
#define MBED_RAM_SIZE S_DATA_SIZE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
LR_CODE MBED_ROM_START MBED_ROM_SIZE {
|
|
||||||
|
|
||||||
/**** This initial section contains common code for TEE */
|
|
||||||
ER_TFM_CODE MBED_ROM_START S_CODE_SIZE {
|
|
||||||
*.o (RESET +First)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
|
|
||||||
#if TFM_LVL == 1
|
|
||||||
|
|
||||||
/* MSP */
|
|
||||||
ARM_LIB_STACK_MSP MBED_RAM_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE {
|
|
||||||
}
|
|
||||||
|
|
||||||
/* PSP */
|
|
||||||
ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE {
|
|
||||||
}
|
|
||||||
|
|
||||||
ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE {
|
|
||||||
}
|
|
||||||
|
|
||||||
ER_TFM_DATA +0 {
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x1000 {
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
|
|
||||||
}
|
|
||||||
|
|
||||||
#else /* TFM_LVL == 1 */
|
|
||||||
|
|
||||||
/**** Unprivileged Secure code start here */
|
|
||||||
TFM_UNPRIV_CODE +0 ALIGN 32 {
|
|
||||||
tfm_spm_services.o (+RO)
|
|
||||||
dummy_crypto_keys.o (+RO)
|
|
||||||
dummy_nv_counters.o (+RO)
|
|
||||||
dummy_boot_seed.o (+RO)
|
|
||||||
dummy_device_id.o (+RO)
|
|
||||||
platform_retarget_dev.o (+RO)
|
|
||||||
*(SFN)
|
|
||||||
*armlib*
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_STORAGE +0 ALIGN 32 {
|
|
||||||
*tfm_storage* (+RO)
|
|
||||||
*(TFM_SP_STORAGE_ATTR_FN)
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_AUDIT_LOG +0 ALIGN 32 {
|
|
||||||
*tfm_audit* (+RO)
|
|
||||||
*(TFM_SP_AUDIT_LOG_ATTR_FN)
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_CRYPTO +0 ALIGN 32 {
|
|
||||||
*tfm_crypto* (+RO)
|
|
||||||
*(TFM_SP_CRYPTO_ATTR_FN)
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_PLATFORM +0 ALIGN 32 {
|
|
||||||
*tfm_platform* (+RO)
|
|
||||||
*(TFM_SP_PLATFORM_ATTR_FN)
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_INITIAL_ATTESTATION +0 ALIGN 32 {
|
|
||||||
*tfm_attest* (+RO)
|
|
||||||
*(TFM_SP_INITIAL_ATTESTATION_ATTR_FN)
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef TFM_PARTITION_TEST_CORE
|
|
||||||
TFM_SP_CORE_TEST +0 ALIGN 32 {
|
|
||||||
*tfm_ss_core_test.* (+RO)
|
|
||||||
*(TFM_SP_CORE_TEST_ATTR_FN)
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_CORE_TEST_2 +0 ALIGN 32 {
|
|
||||||
*tfm_ss_core_test_2.* (+RO)
|
|
||||||
*(TFM_SP_CORE_TEST_2_ATTR_FN)
|
|
||||||
}
|
|
||||||
#endif /* TFM_PARTITION_TEST_CORE */
|
|
||||||
|
|
||||||
#ifdef TFM_PARTITION_TEST_SST
|
|
||||||
TFM_SP_SST_TEST_PARTITION +0 ALIGN 32 {
|
|
||||||
*sst_test_service.* (+RO)
|
|
||||||
*(TFM_SP_SST_TEST_PARTITION_ATTR_FN)
|
|
||||||
}
|
|
||||||
#endif /* TFM_PARTITION_TEST_SST */
|
|
||||||
|
|
||||||
#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
|
|
||||||
TFM_SP_SECURE_TEST_PARTITION +0 ALIGN 32 {
|
|
||||||
*tfm_secure_client_service.* (+RO)
|
|
||||||
*test_framework* (+RO)
|
|
||||||
*uart_stdout.* (+RO)
|
|
||||||
*uart_pl011_drv.* (+RO)
|
|
||||||
*Driver_USART.* (+RO)
|
|
||||||
*secure_suites.* (+RO)
|
|
||||||
*attestation_s_interface_testsuite.* (+RO)
|
|
||||||
*(TFM_SP_SECURE_TEST_PARTITION_ATTR_FN)
|
|
||||||
}
|
|
||||||
#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
|
|
||||||
|
|
||||||
/* Shared area between BL2 and runtime to exchange data */
|
|
||||||
TFM_SHARED_DATA S_DATA_START ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
|
|
||||||
}
|
|
||||||
|
|
||||||
/* MSP */
|
|
||||||
ARM_LIB_STACK_MSP S_DATA_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE {
|
|
||||||
}
|
|
||||||
|
|
||||||
/* PSP */
|
|
||||||
ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE {
|
|
||||||
}
|
|
||||||
|
|
||||||
ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE {
|
|
||||||
}
|
|
||||||
|
|
||||||
ER_TFM_DATA +0 {
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_UNPRIV_RO_DATA +0 ALIGN 32 {
|
|
||||||
tfm_spm_services.o (+RW +ZI)
|
|
||||||
dummy_crypto_keys.o (+RW +ZI)
|
|
||||||
dummy_nv_counters.o (+RW +ZI)
|
|
||||||
dummy_boot_seed.o (+RW +ZI)
|
|
||||||
dummy_device_id.o (+RW +ZI)
|
|
||||||
platform_retarget_dev.o (+RW +ZI)
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_STORAGE_DATA +0 ALIGN 32 {
|
|
||||||
*tfm_storage* (+RW +ZI)
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_STORAGE_STACK +0 ALIGN 128 EMPTY 0x2000 {
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_AUDIT_LOG_DATA +0 ALIGN 32 {
|
|
||||||
*tfm_audit* (+RW +ZI)
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_AUDIT_LOG_STACK +0 ALIGN 128 EMPTY 0x1000 {
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_CRYPTO_DATA +0 ALIGN 32 {
|
|
||||||
*tfm_crypto* (+RW +ZI)
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_CRYPTO_STACK +0 ALIGN 128 EMPTY 0x2000 {
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_PLATFORM_DATA +0 ALIGN 32 {
|
|
||||||
*tfm_platform* (+RW +ZI)
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_PLATFORM_STACK +0 ALIGN 128 EMPTY 0x0400 {
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_INITIAL_ATTESTATION_DATA +0 ALIGN 32 {
|
|
||||||
*tfm_attest* (+RW +ZI)
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_INITIAL_ATTESTATION_STACK +0 ALIGN 128 EMPTY 0x400 {
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef TFM_PARTITION_TEST_CORE
|
|
||||||
TFM_SP_CORE_TEST_DATA +0 ALIGN 32 {
|
|
||||||
tfm_ss_core_test.o (+RW +ZI)
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_CORE_TEST_STACK +0 ALIGN 128 EMPTY 0x400 {
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_CORE_TEST_2_DATA +0 ALIGN 32 {
|
|
||||||
tfm_ss_core_test_2.o (+RW +ZI)
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_CORE_TEST_2_STACK +0 ALIGN 128 EMPTY 0x400 {
|
|
||||||
}
|
|
||||||
#endif /* TFM_PARTITION_TEST_CORE */
|
|
||||||
|
|
||||||
#ifdef TFM_PARTITION_TEST_SST
|
|
||||||
TFM_SP_SST_TEST_PARTITION_DATA +0 ALIGN 32 {
|
|
||||||
sst_test_service.o (+RW +ZI)
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_SST_TEST_PARTITION_STACK +0 ALIGN 128 EMPTY 0x400 {
|
|
||||||
}
|
|
||||||
#endif /* TFM_PARTITION_TEST_SST */
|
|
||||||
|
|
||||||
#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
|
|
||||||
TFM_SP_SECURE_TEST_PARTITION_DATA +0 ALIGN 32 {
|
|
||||||
*tfm_secure_client_service.* (+RW +ZI)
|
|
||||||
*test_framework* (+RW +ZI)
|
|
||||||
*uart_stdout.* (+RW +ZI)
|
|
||||||
*uart_pl011_drv.* (+RW +ZI)
|
|
||||||
*Driver_USART.* (+RW +ZI)
|
|
||||||
*secure_suites.* (+RW +ZI)
|
|
||||||
*attestation_s_interface_testsuite.* (+RW +ZI)
|
|
||||||
}
|
|
||||||
|
|
||||||
TFM_SP_SECURE_TEST_PARTITION_STACK +0 ALIGN 128 EMPTY 0x1000 {
|
|
||||||
}
|
|
||||||
#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
|
|
||||||
|
|
||||||
#endif /* TFM_LVL == 1 */
|
|
||||||
|
|
||||||
/* This empty, zero long execution region is here to mark the limit address
|
|
||||||
* of the last execution region that is allocated in SRAM.
|
|
||||||
*/
|
|
||||||
SRAM_WATERMARK +0 EMPTY 0x0 {
|
|
||||||
}
|
|
||||||
|
|
||||||
ER_CODE_CMSE_VENEER CMSE_VENEER_REGION_START FIXED PADVALUE 0xFFFFFFFF CMSE_VENEER_REGION_SIZE {
|
|
||||||
*(Veneer$$CMSE)
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Make sure that the sections allocated in the SRAM does not exceed the
|
|
||||||
* size of the SRAM available.
|
|
||||||
*/
|
|
||||||
ScatterAssert(ImageLimit(SRAM_WATERMARK) <= MBED_RAM_START + MBED_RAM_SIZE)
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
LR_NS_PARTITION NS_PARTITION_START {
|
|
||||||
/* Reserved place for NS application.
|
|
||||||
* No code will be placed here, just address of this region is used in the
|
|
||||||
* secure code to configure certain HW components.
|
|
||||||
*/
|
|
||||||
ER_NS_PARTITION NS_PARTITION_START EMPTY NS_PARTITION_SIZE {
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -1,787 +0,0 @@
|
||||||
;/*****************************************************************************
|
|
||||||
; * @file: startup_LPC55S69_cm33_core0.s
|
|
||||||
; * @purpose: CMSIS Cortex-M33 Core Device Startup File for the
|
|
||||||
; * LPC55S69_cm33_core0
|
|
||||||
; * @version: 1.0
|
|
||||||
; * @date: 2018-8-22
|
|
||||||
; *
|
|
||||||
; * Copyright 1997-2016 Freescale Semiconductor, Inc.
|
|
||||||
; * Copyright 2016-2018 NXP
|
|
||||||
; * All rights reserved.
|
|
||||||
; *
|
|
||||||
; * SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
; *
|
|
||||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
|
||||||
; *
|
|
||||||
; *****************************************************************************/
|
|
||||||
|
|
||||||
|
|
||||||
;PRESERVE8
|
|
||||||
;THUMB
|
|
||||||
|
|
||||||
; Vector Table Mapped to Address 0 at Reset
|
|
||||||
AREA RESET, DATA, READONLY
|
|
||||||
EXPORT __Vectors
|
|
||||||
EXPORT __Vectors_End
|
|
||||||
EXPORT __Vectors_Size
|
|
||||||
IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit|
|
|
||||||
;IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
|
|
||||||
|
|
||||||
;__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
|
|
||||||
;__Vectors DCD __initial_msp ; Top of Stack
|
|
||||||
__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
|
|
||||||
DCD NMI_Handler
|
|
||||||
DCD HardFault_Handler
|
|
||||||
DCD MemManage_Handler
|
|
||||||
DCD BusFault_Handler
|
|
||||||
DCD UsageFault_Handler
|
|
||||||
DCD SecureFault_Handler
|
|
||||||
__vector_table_0x1c
|
|
||||||
DCD 0 ; Checksum of the first 7 words
|
|
||||||
;DCD 0
|
|
||||||
DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot
|
|
||||||
DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot
|
|
||||||
DCD SVC_Handler
|
|
||||||
DCD DebugMon_Handler
|
|
||||||
DCD 0
|
|
||||||
DCD PendSV_Handler
|
|
||||||
DCD SysTick_Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt
|
|
||||||
DCD DMA0_IRQHandler ; DMA0 controller
|
|
||||||
DCD GINT0_IRQHandler ; GPIO group 0
|
|
||||||
DCD GINT1_IRQHandler ; GPIO group 1
|
|
||||||
DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0
|
|
||||||
DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1
|
|
||||||
DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2
|
|
||||||
DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3
|
|
||||||
DCD UTICK0_IRQHandler ; Micro-tick Timer
|
|
||||||
DCD MRT0_IRQHandler ; Multi-rate timer
|
|
||||||
DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0
|
|
||||||
DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1
|
|
||||||
DCD SCT0_IRQHandler ; SCTimer/PWM
|
|
||||||
DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3
|
|
||||||
DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)
|
|
||||||
DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)
|
|
||||||
DCD ADC0_IRQHandler ; ADC0
|
|
||||||
DCD Reserved39_IRQHandler ; Reserved interrupt
|
|
||||||
DCD ACMP_CAPT0_IRQHandler ; ACMP and CAPT0 interrupts
|
|
||||||
DCD Reserved41_IRQHandler ; Reserved interrupt
|
|
||||||
DCD Reserved42_IRQHandler ; Reserved interrupt
|
|
||||||
DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt
|
|
||||||
DCD USB0_IRQHandler ; USB device
|
|
||||||
DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts
|
|
||||||
DCD EZH_ARCH_B0_IRQHandler ; EZH_ARCH_B0
|
|
||||||
DCD MAILBOX_IRQHandler ; WAKEUP,Mailbox interrupt (present on selected devices)
|
|
||||||
DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int
|
|
||||||
DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int
|
|
||||||
DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int
|
|
||||||
DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int
|
|
||||||
DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2
|
|
||||||
DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4
|
|
||||||
DCD OS_EVENT_IRQHandler ; OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts
|
|
||||||
DCD Reserved55_IRQHandler ; Reserved interrupt
|
|
||||||
DCD Reserved56_IRQHandler ; Reserved interrupt
|
|
||||||
DCD Reserved57_IRQHandler ; Reserved interrupt
|
|
||||||
DCD SDIO_IRQHandler ; SD/MMC
|
|
||||||
DCD Reserved59_IRQHandler ; Reserved interrupt
|
|
||||||
DCD Reserved60_IRQHandler ; Reserved interrupt
|
|
||||||
DCD Reserved61_IRQHandler ; Reserved interrupt
|
|
||||||
DCD USB1_UTMI_IRQHandler ; USB1_UTMI
|
|
||||||
DCD USB1_IRQHandler ; USB1 interrupt
|
|
||||||
DCD USB1_NEEDCLK_IRQHandler ; USB1 activity
|
|
||||||
DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt
|
|
||||||
DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt
|
|
||||||
DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt
|
|
||||||
DCD PLU_IRQHandler ; PLU interrupt
|
|
||||||
DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt
|
|
||||||
DCD HASHCRYPT_IRQHandler ; HASHCRYPT interrupt
|
|
||||||
DCD CASER_IRQHandler ; CASPER interrupt
|
|
||||||
DCD PUF_IRQHandler ; PUF interrupt
|
|
||||||
DCD PQ_IRQHandler ; PQ interrupt
|
|
||||||
DCD DMA1_IRQHandler ; DMA1 interrupt
|
|
||||||
DCD LSPI_HS_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM)
|
|
||||||
DCD PVTVF0_AMBER_IRQHandler ; PVT interrupts
|
|
||||||
DCD PVTVF0_RED_IRQHandler ; PVT interrupts
|
|
||||||
DCD PVTVF1_AMBER_IRQHandler ; PVT interrupts
|
|
||||||
DCD PVTVF1_RED_IRQHandler ; PVT interrupts
|
|
||||||
|
|
||||||
__Vectors_End
|
|
||||||
|
|
||||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
|
||||||
|
|
||||||
|
|
||||||
AREA |.text|, CODE, READONLY
|
|
||||||
|
|
||||||
; Reset Handler
|
|
||||||
Reset_Handler PROC
|
|
||||||
EXPORT Reset_Handler [WEAK]
|
|
||||||
IMPORT SystemInit
|
|
||||||
IMPORT __main
|
|
||||||
;IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base|
|
|
||||||
|
|
||||||
CPSID I ; Mask interrupts
|
|
||||||
;LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Base|
|
|
||||||
;MSR MSPLIM, R0
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
MRS R0, control ; Get control value
|
|
||||||
ORR R0, R0, #2 ; Select switch to PSP
|
|
||||||
MSR control, R0
|
|
||||||
;CPSIE I ; Unmask interrupts
|
|
||||||
LDR R0, =__main
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
End_Of_Main
|
|
||||||
B .
|
|
||||||
|
|
||||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
|
||||||
NMI_Handler PROC
|
|
||||||
EXPORT NMI_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
HardFault_Handler \
|
|
||||||
PROC
|
|
||||||
EXPORT HardFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
MemManage_Handler PROC
|
|
||||||
EXPORT MemManage_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
BusFault_Handler PROC
|
|
||||||
EXPORT BusFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
UsageFault_Handler PROC
|
|
||||||
EXPORT UsageFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
SecureFault_Handler PROC
|
|
||||||
EXPORT SecureFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
SVC_Handler PROC
|
|
||||||
EXPORT SVC_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
DebugMon_Handler PROC
|
|
||||||
EXPORT DebugMon_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PendSV_Handler PROC
|
|
||||||
EXPORT PendSV_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
SysTick_Handler PROC
|
|
||||||
EXPORT SysTick_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
WDT_BOD_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT WDT_BOD_IRQHandler [WEAK]
|
|
||||||
LDR R0, =WDT_BOD_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
DMA0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT DMA0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =DMA0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
GINT0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT GINT0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =GINT0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
GINT1_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT GINT1_IRQHandler [WEAK]
|
|
||||||
LDR R0, =GINT1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PIN_INT0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PIN_INT0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PIN_INT0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PIN_INT1_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PIN_INT1_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PIN_INT1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PIN_INT2_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PIN_INT2_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PIN_INT2_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PIN_INT3_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PIN_INT3_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PIN_INT3_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
UTICK0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT UTICK0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =UTICK0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
MRT0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT MRT0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =MRT0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
CTIMER0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT CTIMER0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =CTIMER0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
CTIMER1_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT CTIMER1_IRQHandler [WEAK]
|
|
||||||
LDR R0, =CTIMER1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
SCT0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT SCT0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =SCT0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
CTIMER3_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT CTIMER3_IRQHandler [WEAK]
|
|
||||||
LDR R0, =CTIMER3_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
FLEXCOMM0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT FLEXCOMM0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =FLEXCOMM0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
FLEXCOMM1_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT FLEXCOMM1_IRQHandler [WEAK]
|
|
||||||
LDR R0, =FLEXCOMM1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
FLEXCOMM2_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT FLEXCOMM2_IRQHandler [WEAK]
|
|
||||||
LDR R0, =FLEXCOMM2_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
FLEXCOMM3_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT FLEXCOMM3_IRQHandler [WEAK]
|
|
||||||
LDR R0, =FLEXCOMM3_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
FLEXCOMM4_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT FLEXCOMM4_IRQHandler [WEAK]
|
|
||||||
LDR R0, =FLEXCOMM4_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
FLEXCOMM5_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT FLEXCOMM5_IRQHandler [WEAK]
|
|
||||||
LDR R0, =FLEXCOMM5_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
FLEXCOMM6_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT FLEXCOMM6_IRQHandler [WEAK]
|
|
||||||
LDR R0, =FLEXCOMM6_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
FLEXCOMM7_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT FLEXCOMM7_IRQHandler [WEAK]
|
|
||||||
LDR R0, =FLEXCOMM7_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
ADC0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT ADC0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =ADC0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved39_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved39_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved39_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
ACMP_CAPT0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT ACMP_CAPT0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =ACMP_CAPT0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved41_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved41_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved41_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved42_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved42_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved42_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
USB0_NEEDCLK_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT USB0_NEEDCLK_IRQHandler [WEAK]
|
|
||||||
LDR R0, =USB0_NEEDCLK_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
USB0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT USB0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =USB0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
RTC_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT RTC_IRQHandler [WEAK]
|
|
||||||
LDR R0, =RTC_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
EZH_ARCH_B0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT EZH_ARCH_B0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =EZH_ARCH_B0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
MAILBOX_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT MAILBOX_IRQHandler [WEAK]
|
|
||||||
LDR R0, =MAILBOX_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PIN_INT4_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PIN_INT4_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PIN_INT4_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PIN_INT5_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PIN_INT5_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PIN_INT5_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PIN_INT6_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PIN_INT6_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PIN_INT6_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PIN_INT7_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PIN_INT7_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PIN_INT7_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
CTIMER2_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT CTIMER2_IRQHandler [WEAK]
|
|
||||||
LDR R0, =CTIMER2_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
CTIMER4_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT CTIMER4_IRQHandler [WEAK]
|
|
||||||
LDR R0, =CTIMER4_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
OS_EVENT_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT OS_EVENT_IRQHandler [WEAK]
|
|
||||||
LDR R0, =OS_EVENT_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved55_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved55_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved55_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved56_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved56_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved56_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved57_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved57_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved57_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
SDIO_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT SDIO_IRQHandler [WEAK]
|
|
||||||
LDR R0, =SDIO_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved59_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved59_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved59_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved60_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved60_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved60_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Reserved61_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT Reserved61_IRQHandler [WEAK]
|
|
||||||
LDR R0, =Reserved61_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
USB1_UTMI_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT USB1_UTMI_IRQHandler [WEAK]
|
|
||||||
LDR R0, =USB1_UTMI_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
USB1_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT USB1_IRQHandler [WEAK]
|
|
||||||
LDR R0, =USB1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
USB1_NEEDCLK_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT USB1_NEEDCLK_IRQHandler [WEAK]
|
|
||||||
LDR R0, =USB1_NEEDCLK_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
SEC_HYPERVISOR_CALL_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT SEC_HYPERVISOR_CALL_IRQHandler [WEAK]
|
|
||||||
LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
SEC_GPIO_INT0_IRQ0_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT SEC_GPIO_INT0_IRQ0_IRQHandler [WEAK]
|
|
||||||
LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
SEC_GPIO_INT0_IRQ1_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT SEC_GPIO_INT0_IRQ1_IRQHandler [WEAK]
|
|
||||||
LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PLU_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PLU_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PLU_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
SEC_VIO_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT SEC_VIO_IRQHandler [WEAK]
|
|
||||||
LDR R0, =SEC_VIO_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
HASHCRYPT_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT HASHCRYPT_IRQHandler [WEAK]
|
|
||||||
LDR R0, =HASHCRYPT_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
CASER_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT CASER_IRQHandler [WEAK]
|
|
||||||
LDR R0, =CASER_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PUF_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PUF_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PUF_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PQ_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PQ_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PQ_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
DMA1_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT DMA1_IRQHandler [WEAK]
|
|
||||||
LDR R0, =DMA1_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
LSPI_HS_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT LSPI_HS_IRQHandler [WEAK]
|
|
||||||
LDR R0, =LSPI_HS_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PVTVF0_AMBER_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PVTVF0_AMBER_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PVTVF0_AMBER_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PVTVF0_RED_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PVTVF0_RED_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PVTVF0_RED_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PVTVF1_AMBER_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PVTVF1_AMBER_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PVTVF1_AMBER_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
PVTVF1_RED_IRQHandler\
|
|
||||||
PROC
|
|
||||||
EXPORT PVTVF1_RED_IRQHandler [WEAK]
|
|
||||||
LDR R0, =PVTVF1_RED_DriverIRQHandler
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Default_Handler PROC
|
|
||||||
EXPORT WDT_BOD_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT DMA0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT GINT0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT GINT1_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PIN_INT0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PIN_INT1_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PIN_INT2_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PIN_INT3_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT UTICK0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT MRT0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT CTIMER0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT CTIMER1_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT SCT0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT CTIMER3_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT FLEXCOMM0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT FLEXCOMM1_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT FLEXCOMM2_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT FLEXCOMM3_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT FLEXCOMM4_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT FLEXCOMM5_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT FLEXCOMM6_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT FLEXCOMM7_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT ADC0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved39_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT ACMP_CAPT0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved41_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved42_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT USB0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT RTC_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT EZH_ARCH_B0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT MAILBOX_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PIN_INT4_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PIN_INT5_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PIN_INT6_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PIN_INT7_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT CTIMER2_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT CTIMER4_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT OS_EVENT_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved55_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved56_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved57_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT SDIO_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved59_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved60_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT Reserved61_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT USB1_UTMI_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT USB1_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT USB1_NEEDCLK_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT SEC_HYPERVISOR_CALL_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT SEC_GPIO_INT0_IRQ0_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT SEC_GPIO_INT0_IRQ1_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PLU_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT SEC_VIO_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT HASHCRYPT_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT CASER_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PUF_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PQ_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT LSPI_HS_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PVTVF0_AMBER_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PVTVF0_RED_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PVTVF1_AMBER_DriverIRQHandler [WEAK]
|
|
||||||
EXPORT PVTVF1_RED_DriverIRQHandler [WEAK]
|
|
||||||
|
|
||||||
WDT_BOD_DriverIRQHandler
|
|
||||||
DMA0_DriverIRQHandler
|
|
||||||
GINT0_DriverIRQHandler
|
|
||||||
GINT1_DriverIRQHandler
|
|
||||||
PIN_INT0_DriverIRQHandler
|
|
||||||
PIN_INT1_DriverIRQHandler
|
|
||||||
PIN_INT2_DriverIRQHandler
|
|
||||||
PIN_INT3_DriverIRQHandler
|
|
||||||
UTICK0_DriverIRQHandler
|
|
||||||
MRT0_DriverIRQHandler
|
|
||||||
CTIMER0_DriverIRQHandler
|
|
||||||
CTIMER1_DriverIRQHandler
|
|
||||||
SCT0_DriverIRQHandler
|
|
||||||
CTIMER3_DriverIRQHandler
|
|
||||||
FLEXCOMM0_DriverIRQHandler
|
|
||||||
FLEXCOMM1_DriverIRQHandler
|
|
||||||
FLEXCOMM2_DriverIRQHandler
|
|
||||||
FLEXCOMM3_DriverIRQHandler
|
|
||||||
FLEXCOMM4_DriverIRQHandler
|
|
||||||
FLEXCOMM5_DriverIRQHandler
|
|
||||||
FLEXCOMM6_DriverIRQHandler
|
|
||||||
FLEXCOMM7_DriverIRQHandler
|
|
||||||
ADC0_DriverIRQHandler
|
|
||||||
Reserved39_DriverIRQHandler
|
|
||||||
ACMP_CAPT0_DriverIRQHandler
|
|
||||||
Reserved41_DriverIRQHandler
|
|
||||||
Reserved42_DriverIRQHandler
|
|
||||||
USB0_NEEDCLK_DriverIRQHandler
|
|
||||||
USB0_DriverIRQHandler
|
|
||||||
RTC_DriverIRQHandler
|
|
||||||
EZH_ARCH_B0_DriverIRQHandler
|
|
||||||
MAILBOX_DriverIRQHandler
|
|
||||||
PIN_INT4_DriverIRQHandler
|
|
||||||
PIN_INT5_DriverIRQHandler
|
|
||||||
PIN_INT6_DriverIRQHandler
|
|
||||||
PIN_INT7_DriverIRQHandler
|
|
||||||
CTIMER2_DriverIRQHandler
|
|
||||||
CTIMER4_DriverIRQHandler
|
|
||||||
OS_EVENT_DriverIRQHandler
|
|
||||||
Reserved55_DriverIRQHandler
|
|
||||||
Reserved56_DriverIRQHandler
|
|
||||||
Reserved57_DriverIRQHandler
|
|
||||||
SDIO_DriverIRQHandler
|
|
||||||
Reserved59_DriverIRQHandler
|
|
||||||
Reserved60_DriverIRQHandler
|
|
||||||
Reserved61_DriverIRQHandler
|
|
||||||
USB1_UTMI_DriverIRQHandler
|
|
||||||
USB1_DriverIRQHandler
|
|
||||||
USB1_NEEDCLK_DriverIRQHandler
|
|
||||||
SEC_HYPERVISOR_CALL_DriverIRQHandler
|
|
||||||
SEC_GPIO_INT0_IRQ0_DriverIRQHandler
|
|
||||||
SEC_GPIO_INT0_IRQ1_DriverIRQHandler
|
|
||||||
PLU_DriverIRQHandler
|
|
||||||
SEC_VIO_DriverIRQHandler
|
|
||||||
HASHCRYPT_DriverIRQHandler
|
|
||||||
CASER_DriverIRQHandler
|
|
||||||
PUF_DriverIRQHandler
|
|
||||||
PQ_DriverIRQHandler
|
|
||||||
DMA1_DriverIRQHandler
|
|
||||||
LSPI_HS_DriverIRQHandler
|
|
||||||
PVTVF0_AMBER_DriverIRQHandler
|
|
||||||
PVTVF0_RED_DriverIRQHandler
|
|
||||||
PVTVF1_AMBER_DriverIRQHandler
|
|
||||||
PVTVF1_RED_DriverIRQHandler
|
|
||||||
|
|
||||||
B .
|
|
||||||
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
||||||
|
|
@ -1,74 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2018, Arm Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stdio.h>
|
|
||||||
#include "platform/include/tfm_spm_hal.h"
|
|
||||||
#include "spm_api.h"
|
|
||||||
#include "spm_db.h"
|
|
||||||
#include "tfm_platform_core_api.h"
|
|
||||||
#include "target_cfg.h"
|
|
||||||
#include "region_defs.h"
|
|
||||||
#include "secure_utilities.h"
|
|
||||||
|
|
||||||
/* Get address of memory regions to configure MPU */
|
|
||||||
extern const struct memory_region_limits memory_regions;
|
|
||||||
|
|
||||||
void tfm_spm_hal_init_isolation_hw(void)
|
|
||||||
{
|
|
||||||
/* Configures non-secure memory spaces in the target */
|
|
||||||
sau_and_idau_cfg();
|
|
||||||
mpc_init_cfg();
|
|
||||||
ppc_init_cfg();
|
|
||||||
}
|
|
||||||
|
|
||||||
void tfm_spm_hal_configure_default_isolation(
|
|
||||||
const struct tfm_spm_partition_platform_data_t *platform_data)
|
|
||||||
{
|
|
||||||
/*if (platform_data) {
|
|
||||||
ppc_configure_to_secure(platform_data->periph_ppc_bank,
|
|
||||||
platform_data->periph_ppc_loc);
|
|
||||||
}*/
|
|
||||||
}
|
|
||||||
|
|
||||||
void tfm_spm_hal_setup_isolation_hw(void)
|
|
||||||
{
|
|
||||||
#if TFM_LVL != 1
|
|
||||||
if (tfm_spm_mpu_init() != SPM_ERR_OK) {
|
|
||||||
ERROR_MSG("Failed to set up initial MPU configuration! Halting.");
|
|
||||||
while (1) {
|
|
||||||
;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
void SEC_VIO_IRQHandler(void)
|
|
||||||
{
|
|
||||||
/* Clear interrupt flag and pending IRQ */
|
|
||||||
NVIC_ClearPendingIRQ(SEC_VIO_IRQn);
|
|
||||||
|
|
||||||
/* Print fault message and block execution */
|
|
||||||
LOG_MSG("Oops... MPC/PPC fault!!!");
|
|
||||||
|
|
||||||
/* Inform TF-M core that isolation boundary has been violated */
|
|
||||||
tfm_access_violation_handler();
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t tfm_spm_hal_get_ns_VTOR(void)
|
|
||||||
{
|
|
||||||
return memory_regions.non_secure_code_start;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t tfm_spm_hal_get_ns_MSP(void)
|
|
||||||
{
|
|
||||||
return *((uint32_t *)memory_regions.non_secure_code_start);
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t tfm_spm_hal_get_ns_entry_point(void)
|
|
||||||
{
|
|
||||||
return *((uint32_t *)(memory_regions.non_secure_code_start + 4));
|
|
||||||
}
|
|
||||||
|
|
@ -1,471 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2018 Arm Limited
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*
|
|
||||||
* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2019 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "cmsis.h"
|
|
||||||
#include "target_cfg.h"
|
|
||||||
#include "region_defs.h"
|
|
||||||
#include "tfm_secure_api.h"
|
|
||||||
#include <stdio.h>
|
|
||||||
|
|
||||||
/* Macros to pick linker symbols */
|
|
||||||
#define REGION(a, b, c) a##b##c
|
|
||||||
#define REGION_NAME(a, b, c) REGION(a, b, c)
|
|
||||||
#define REGION_DECLARE(a, b, c) extern uint32_t REGION_NAME(a, b, c)
|
|
||||||
|
|
||||||
/* The section names come from the scatter file */
|
|
||||||
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
|
|
||||||
REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
|
|
||||||
|
|
||||||
REGION_DECLARE(Image$$, ER_CODE_CMSE_VENEER, $$Base);
|
|
||||||
REGION_DECLARE(Image$$, ER_CODE_CMSE_VENEER, $$Limit);
|
|
||||||
|
|
||||||
|
|
||||||
const struct memory_region_limits memory_regions = {
|
|
||||||
.non_secure_code_start =
|
|
||||||
(uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
|
|
||||||
BL2_HEADER_SIZE,
|
|
||||||
|
|
||||||
.non_secure_partition_base =
|
|
||||||
(uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base),
|
|
||||||
|
|
||||||
.non_secure_partition_limit =
|
|
||||||
(uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
|
|
||||||
NS_PARTITION_SIZE - 1,
|
|
||||||
|
|
||||||
.veneer_base =
|
|
||||||
(uint32_t)®ION_NAME(Image$$, ER_CODE_CMSE_VENEER, $$Base),
|
|
||||||
|
|
||||||
.veneer_limit =
|
|
||||||
(uint32_t)®ION_NAME(Image$$, ER_CODE_CMSE_VENEER, $$Limit),
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Allows software, via SAU, to define the code region as a NSC */
|
|
||||||
#define NSCCFG_CODENSC 1
|
|
||||||
|
|
||||||
/* Define Peripherals NS address range for the platform */
|
|
||||||
#define PERIPHERALS_BASE_NS_START (0x40000000)
|
|
||||||
#define PERIPHERALS_BASE_NS_END (0x4010FFFF)
|
|
||||||
|
|
||||||
/* Enable system reset request for CPU 0 */
|
|
||||||
#define ENABLE_CPU0_SYSTEM_RESET_REQUEST (1U << 4U)
|
|
||||||
|
|
||||||
/* To write into AIRCR register, 0x5FA value must be write to the VECTKEY field,
|
|
||||||
* otherwise the processor ignores the write.
|
|
||||||
*/
|
|
||||||
#define SCB_AIRCR_WRITE_MASK ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos))
|
|
||||||
|
|
||||||
/* Debug configuration flags */
|
|
||||||
#define SPNIDEN_SEL_STATUS (0x01u << 7)
|
|
||||||
#define SPNIDEN_STATUS (0x01u << 6)
|
|
||||||
#define SPIDEN_SEL_STATUS (0x01u << 5)
|
|
||||||
#define SPIDEN_STATUS (0x01u << 4)
|
|
||||||
#define NIDEN_SEL_STATUS (0x01u << 3)
|
|
||||||
#define NIDEN_STATUS (0x01u << 2)
|
|
||||||
#define DBGEN_SEL_STATUS (0x01u << 1)
|
|
||||||
#define DBGEN_STATUS (0x01u << 0)
|
|
||||||
|
|
||||||
#define All_SEL_STATUS (SPNIDEN_SEL_STATUS | SPIDEN_SEL_STATUS | \
|
|
||||||
NIDEN_SEL_STATUS | DBGEN_SEL_STATUS)
|
|
||||||
|
|
||||||
void enable_fault_handlers(void)
|
|
||||||
{
|
|
||||||
/* Enables BUS, MEM, USG and Secure faults */
|
|
||||||
SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk
|
|
||||||
| SCB_SHCSR_BUSFAULTENA_Msk
|
|
||||||
| SCB_SHCSR_MEMFAULTENA_Msk
|
|
||||||
| SCB_SHCSR_SECUREFAULTENA_Msk;
|
|
||||||
}
|
|
||||||
|
|
||||||
void system_reset_cfg(void)
|
|
||||||
{
|
|
||||||
uint32_t reg_value = SCB->AIRCR;
|
|
||||||
|
|
||||||
/* Clear SCB_AIRCR_VECTKEY value */
|
|
||||||
reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk);
|
|
||||||
|
|
||||||
/* Enable system reset request only to the secure world */
|
|
||||||
reg_value |= (uint32_t)(SCB_AIRCR_WRITE_MASK | SCB_AIRCR_SYSRESETREQS_Msk);
|
|
||||||
|
|
||||||
SCB->AIRCR = reg_value;
|
|
||||||
}
|
|
||||||
|
|
||||||
void tfm_spm_hal_init_debug(void)
|
|
||||||
{
|
|
||||||
volatile struct sysctrl_t *sys_ctrl =
|
|
||||||
(struct sysctrl_t *)CMSDK_SYSCTRL_BASE_S;
|
|
||||||
|
|
||||||
#if defined(DAUTH_NONE)
|
|
||||||
/* Set all the debug enable selector bits to 1 */
|
|
||||||
sys_ctrl->secdbgset = All_SEL_STATUS;
|
|
||||||
/* Set all the debug enable bits to 0 */
|
|
||||||
sys_ctrl->secdbgclr =
|
|
||||||
DBGEN_STATUS | NIDEN_STATUS | SPIDEN_STATUS | SPNIDEN_STATUS;
|
|
||||||
#elif defined(DAUTH_NS_ONLY)
|
|
||||||
/* Set all the debug enable selector bits to 1 */
|
|
||||||
sys_ctrl->secdbgset = All_SEL_STATUS;
|
|
||||||
/* Set the debug enable bits to 1 for NS, and 0 for S mode */
|
|
||||||
sys_ctrl->secdbgset = DBGEN_STATUS | NIDEN_STATUS;
|
|
||||||
sys_ctrl->secdbgclr = SPIDEN_STATUS | SPNIDEN_STATUS;
|
|
||||||
#elif defined(DAUTH_FULL)
|
|
||||||
/* Set all the debug enable selector bits to 1 */
|
|
||||||
sys_ctrl->secdbgset = All_SEL_STATUS;
|
|
||||||
/* Set all the debug enable bits to 1 */
|
|
||||||
sys_ctrl->secdbgset =
|
|
||||||
DBGEN_STATUS | NIDEN_STATUS | SPIDEN_STATUS | SPNIDEN_STATUS;
|
|
||||||
#else
|
|
||||||
|
|
||||||
#if !defined(DAUTH_CHIP_DEFAULT)
|
|
||||||
#error "No debug authentication setting is provided."
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Set all the debug enable selector bits to 0 */
|
|
||||||
sys_ctrl->secdbgclr = All_SEL_STATUS;
|
|
||||||
|
|
||||||
/* No need to set any enable bits because the value depends on
|
|
||||||
* input signals.
|
|
||||||
*/
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/*----------------- NVIC interrupt target state to NS configuration ----------*/
|
|
||||||
void nvic_interrupt_target_state_cfg()
|
|
||||||
{
|
|
||||||
/* Target every interrupt to NS; unimplemented interrupts will be WI */
|
|
||||||
for (uint8_t i=0; i<sizeof(NVIC->ITNS)/sizeof(NVIC->ITNS[0]); i++) {
|
|
||||||
NVIC->ITNS[i] = 0xFFFFFFFF;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Make sure that MPC and PPC are targeted to S state */
|
|
||||||
NVIC_ClearTargetState(SEC_VIO_IRQn);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*----------------- NVIC interrupt enabling for S peripherals ----------------*/
|
|
||||||
void nvic_interrupt_enable()
|
|
||||||
{
|
|
||||||
NVIC_EnableIRQ(SEC_VIO_IRQn);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*------------------- SAU/IDAU configuration functions -----------------------*/
|
|
||||||
|
|
||||||
void sau_and_idau_cfg(void)
|
|
||||||
{
|
|
||||||
/* Disable SAU */
|
|
||||||
TZ_SAU_Disable();
|
|
||||||
|
|
||||||
/* Configures SAU regions to be non-secure */
|
|
||||||
SAU->RNR = TFM_NS_REGION_CODE;
|
|
||||||
SAU->RBAR = (memory_regions.non_secure_partition_base
|
|
||||||
& SAU_RBAR_BADDR_Msk);
|
|
||||||
SAU->RLAR = (memory_regions.non_secure_partition_limit
|
|
||||||
& SAU_RLAR_LADDR_Msk)
|
|
||||||
| SAU_RLAR_ENABLE_Msk;
|
|
||||||
|
|
||||||
SAU->RNR = TFM_NS_REGION_DATA;
|
|
||||||
SAU->RBAR = (NS_DATA_START & SAU_RBAR_BADDR_Msk);
|
|
||||||
SAU->RLAR = (NS_DATA_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
|
|
||||||
|
|
||||||
/* Configures veneers region to be non-secure callable */
|
|
||||||
SAU->RNR = TFM_NS_REGION_VENEER;
|
|
||||||
SAU->RBAR = (memory_regions.veneer_base & SAU_RBAR_BADDR_Msk);
|
|
||||||
SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk)
|
|
||||||
| SAU_RLAR_ENABLE_Msk
|
|
||||||
| SAU_RLAR_NSC_Msk;
|
|
||||||
|
|
||||||
/* Configure the peripherals space */
|
|
||||||
SAU->RNR = TFM_NS_REGION_PERIPH_1;
|
|
||||||
SAU->RBAR = (PERIPHERALS_BASE_NS_START & SAU_RBAR_BADDR_Msk);
|
|
||||||
SAU->RLAR = (PERIPHERALS_BASE_NS_END & SAU_RLAR_LADDR_Msk)
|
|
||||||
| SAU_RLAR_ENABLE_Msk;
|
|
||||||
|
|
||||||
#ifdef BL2
|
|
||||||
/* Secondary image partition */
|
|
||||||
SAU->RNR = TFM_NS_SECONDARY_IMAGE_REGION;
|
|
||||||
SAU->RBAR = (memory_regions.secondary_partition_base & SAU_RBAR_BADDR_Msk);
|
|
||||||
SAU->RLAR = (memory_regions.secondary_partition_limit & SAU_RLAR_LADDR_Msk)
|
|
||||||
| SAU_RLAR_ENABLE_Msk;
|
|
||||||
#endif /* BL2 */
|
|
||||||
|
|
||||||
/* Force memory writes before continuing */
|
|
||||||
__DSB();
|
|
||||||
/* Flush and refill pipeline with updated permissions */
|
|
||||||
__ISB();
|
|
||||||
|
|
||||||
/* Enable SAU */
|
|
||||||
TZ_SAU_Enable();
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/*------------------- Memory configuration functions -------------------------*/
|
|
||||||
|
|
||||||
void mpc_init_cfg(void)
|
|
||||||
{
|
|
||||||
uint32_t mpcIdx = 0;
|
|
||||||
uint32_t startRegionIdx = 0;
|
|
||||||
uint32_t endRegionIdx = 0;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Starts changing actual configuration so issue DMB to ensure every
|
|
||||||
* transaction has completed by now
|
|
||||||
*/
|
|
||||||
__DMB();
|
|
||||||
|
|
||||||
//FLASH memory configuration (all regions set to secure privilidged)
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[0] = 0x33333333U;
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[1] = 0x33333333U;
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[2] = 0x33333333U;
|
|
||||||
|
|
||||||
//FLASH memory configuration (set according to region_defs.h and flash_layout.h)
|
|
||||||
//The regions have to be alligned to 32 kB to cover the AHB Flash Region
|
|
||||||
if (((NS_PARTITION_START % FLASH_AREA_IMAGE_SECTOR_SIZE) == 0) && \
|
|
||||||
(((NS_PARTITION_START + NS_PARTITION_SIZE) % FLASH_AREA_IMAGE_SECTOR_SIZE) == 0)) {
|
|
||||||
startRegionIdx = NS_PARTITION_START / FLASH_AREA_IMAGE_SECTOR_SIZE;
|
|
||||||
endRegionIdx = (NS_PARTITION_START + NS_PARTITION_SIZE) / FLASH_AREA_IMAGE_SECTOR_SIZE;
|
|
||||||
|
|
||||||
for(mpcIdx = startRegionIdx; mpcIdx < endRegionIdx; mpcIdx++) {
|
|
||||||
if(mpcIdx < 8) {
|
|
||||||
//Set regions the ABH controller for flash memory 0x0000_0000 - 0x0004_0000
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[0] &= ~(0xF << (mpcIdx * 4));
|
|
||||||
}
|
|
||||||
if((mpcIdx >= 8) && (mpcIdx < 16)) {
|
|
||||||
//Set regions in the ABH controller for flash memory 0x0004_0000 - 0x0008_0000
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[1] &= ~(0xF << ((mpcIdx - 8) * 4));
|
|
||||||
}
|
|
||||||
if((mpcIdx >= 16) && (mpcIdx < 24)) {
|
|
||||||
//Set regions the ABH controller for flash memory 0x0008_0000 - 0x0009_8000
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[2] &= ~(0xF << ((mpcIdx - 16) * 4));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
ERROR_MSG("Failed to set up initial MPC configuration! NS Flash regions are not alligned to 32kB. Halting.");
|
|
||||||
while (1) {
|
|
||||||
;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
//ROM memory configuration (all secure)
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[0] = 0x33333333U;
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[1] = 0x33333333U;
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[2] = 0x33333333U;
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[3] = 0x33333333U;
|
|
||||||
|
|
||||||
//SRAM memory configuration (all secure)
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAMX[0].MEM_RULE[0]= 0x33333333U;
|
|
||||||
|
|
||||||
//RAM memory configuration
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[0]= 0x33333333U;
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[1]= 0x33333333U;
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[0]= 0x33333333U;
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[1]= 0x33333333U;
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[0]= 0x33333333U;
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[1]= 0x33333333U;
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[0]= 0x33333333U;
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[1]= 0x33333333U;
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM4[0].MEM_RULE[0]= 0x33333333U;
|
|
||||||
|
|
||||||
//RAM memory configuration (set according to region_defs.h and flash_layout.h)
|
|
||||||
//The regions have to be alligned to 4 kB to cover the AHB RAM Region
|
|
||||||
if (((S_DATA_SIZE % DATA_SUBREGION_SIZE) == 0) && \
|
|
||||||
(((S_DATA_SIZE + NS_DATA_SIZE) % DATA_SUBREGION_SIZE) == 0)) {
|
|
||||||
startRegionIdx = S_DATA_SIZE / DATA_SUBREGION_SIZE;
|
|
||||||
endRegionIdx = (S_DATA_SIZE + NS_DATA_SIZE) / DATA_SUBREGION_SIZE;
|
|
||||||
|
|
||||||
for(mpcIdx = startRegionIdx; mpcIdx < endRegionIdx; mpcIdx++) {
|
|
||||||
//Set regions the ABH controller for ram memory 0x0000_0000 - 0x0000_8000
|
|
||||||
if(mpcIdx < 8) {
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[0] &= ~(0xF << (mpcIdx*4));
|
|
||||||
}
|
|
||||||
//Set regions the ABH controller for ram memory 0x0000_8000 - 0x0001_0000
|
|
||||||
if((mpcIdx >= 8) && (mpcIdx < 16)) {
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[1] &= ~(0xF << ((mpcIdx-8)*4));
|
|
||||||
}
|
|
||||||
//Set regions the ABH controller for ram memory 0x0001_0000 - 0x0001_8000
|
|
||||||
if((mpcIdx >= 16) && (mpcIdx < 24)) {
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[0] &= ~(0xF << ((mpcIdx-16)*4));
|
|
||||||
}
|
|
||||||
//Set regions the ABH controller for ram memory 0x0001_8000 - 0x0002_0000
|
|
||||||
if((mpcIdx >= 24) && (mpcIdx < 32)) {
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[1] &= ~(0xF << ((mpcIdx-24)*4));
|
|
||||||
}
|
|
||||||
//Set regions the ABH controller for ram memory 0x0002_0000 - 0x0002_8000
|
|
||||||
if((mpcIdx >= 32) && (mpcIdx < 40)) {
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[0] &= ~(0xF << ((mpcIdx-32)*4));
|
|
||||||
}
|
|
||||||
//Set regions the ABH controller for ram memory 0x0002_8000 - 0x0003_0000
|
|
||||||
if((mpcIdx >= 40) && (mpcIdx < 48)) {
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[1] &= ~(0xF << ((mpcIdx-40)*4));
|
|
||||||
}
|
|
||||||
//Set regions the ABH controller for ram memory 0x0003_0000 - 0x0003_8000
|
|
||||||
if((mpcIdx >= 48) && (mpcIdx < 56)) {
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[0] &= ~(0xF << ((mpcIdx-48)*4));
|
|
||||||
}
|
|
||||||
//Set regions the ABH controller for ram memory 0x0003_8000 - 0x0004_0000
|
|
||||||
if((mpcIdx >= 56) && (mpcIdx < 64)) {
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[1] &= ~(0xF << ((mpcIdx-56)*4));
|
|
||||||
}
|
|
||||||
//Set regions the ABH controller for ram memory 0x0004_0000 - 0x0004_4000
|
|
||||||
if((mpcIdx >= 64) && (mpcIdx < 72)) {
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_RAM4[0].MEM_RULE[0] &= ~(0xF << ((mpcIdx-64)*4));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
ERROR_MSG("Failed to set up initial MPC configuration! NS RAM regions are not alligned to 4kB. Halting.");
|
|
||||||
while (1) {
|
|
||||||
;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Add barriers to assure the MPC configuration is done before continue
|
|
||||||
* the execution.
|
|
||||||
*/
|
|
||||||
__DSB();
|
|
||||||
__ISB();
|
|
||||||
}
|
|
||||||
|
|
||||||
/*---------------------- PPC configuration functions -------------------------*/
|
|
||||||
|
|
||||||
void ppc_init_cfg(void)
|
|
||||||
{
|
|
||||||
/* Secure access to Flash controller in the PPC */
|
|
||||||
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 =
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(0x3U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(0x0U);
|
|
||||||
|
|
||||||
/* Grant non-secure access to peripherals in the PPC */
|
|
||||||
|
|
||||||
/* APB settings for Bridge 0 */
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 =
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE(0x0U);
|
|
||||||
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 =
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(0x0U);
|
|
||||||
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 =
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE(0x0U);
|
|
||||||
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL3 =
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_CAPTOUCH_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_EZH_RULE(0x0U);
|
|
||||||
|
|
||||||
/* APB settings for Bridge 1 */
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 =
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PVT_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(0x0U);
|
|
||||||
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 =
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(0x0U);
|
|
||||||
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 =
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_ROMPC_RULE(0x0U);
|
|
||||||
|
|
||||||
/* AHB settings*/
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_AHB0_0_SLAVE_RULE =
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE(0x0U);
|
|
||||||
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_AHB0_1_SLAVE_RULE =
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE(0x0U);
|
|
||||||
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_AHB1_0_SLAVE_RULE =
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE(0x0U);
|
|
||||||
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_AHB1_1_SLAVE_RULE =
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE(0x0U);
|
|
||||||
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_AHB2[0].SEC_CTRL_AHB2_0_SLAVE_RULE =
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE(0x0U);
|
|
||||||
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_AHB2[0].SEC_CTRL_AHB2_1_SLAVE_RULE =
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE(0x0U);
|
|
||||||
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_AHB2[0].SEC_CTRL_AHB2_0_MEM_RULE[0] =
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(0x0U);
|
|
||||||
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_USB_HS[0].SLAVE_RULE =
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(0x0U);
|
|
||||||
|
|
||||||
AHB_SECURE_CTRL->SEC_CTRL_USB_HS[0].MEM_RULE[0] =
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE(0x0U) |
|
|
||||||
AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE(0x0U);
|
|
||||||
|
|
||||||
/* Enable AHB secure controller check and lock all rule registers */
|
|
||||||
AHB_SECURE_CTRL->MISC_CTRL_REG =
|
|
||||||
(AHB_SECURE_CTRL->MISC_CTRL_REG & ~(AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK |
|
|
||||||
AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)) |
|
|
||||||
AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(0x1U) |
|
|
||||||
AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(0x1U);
|
|
||||||
|
|
||||||
AHB_SECURE_CTRL->MISC_CTRL_DP_REG =
|
|
||||||
(AHB_SECURE_CTRL->MISC_CTRL_DP_REG & ~(AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK |
|
|
||||||
AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK |
|
|
||||||
AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK)) |
|
|
||||||
AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(0x1U) |
|
|
||||||
AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(0x1U) |
|
|
||||||
AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(0x1U);
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
@ -1,66 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2018 ARM Limited
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*
|
|
||||||
* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2019 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __TARGET_CFG_H__
|
|
||||||
#define __TARGET_CFG_H__
|
|
||||||
|
|
||||||
#include "tfm_peripherals_def.h"
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Store the addresses of memory regions
|
|
||||||
*/
|
|
||||||
struct memory_region_limits {
|
|
||||||
uint32_t non_secure_code_start;
|
|
||||||
uint32_t non_secure_partition_base;
|
|
||||||
uint32_t non_secure_partition_limit;
|
|
||||||
uint32_t veneer_base;
|
|
||||||
uint32_t veneer_limit;
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Holds the data necessary to do isolation for a specific peripheral.
|
|
||||||
*/
|
|
||||||
struct tfm_spm_partition_platform_data_t
|
|
||||||
{
|
|
||||||
uint32_t periph_start;
|
|
||||||
uint32_t periph_limit;
|
|
||||||
int16_t periph_ppc_bank;
|
|
||||||
int16_t periph_ppc_loc;
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Configures the Memory Protection Controller.
|
|
||||||
*/
|
|
||||||
void mpc_init_cfg(void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Configures the Peripheral Protection Controller.
|
|
||||||
*/
|
|
||||||
void ppc_init_cfg(void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Configures SAU and IDAU.
|
|
||||||
*/
|
|
||||||
void sau_and_idau_cfg(void);
|
|
||||||
|
|
||||||
|
|
||||||
#endif /* __TARGET_CFG_H__ */
|
|
||||||
|
|
@ -1,17 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2018, Arm Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __TFM_PERIPHERALS_DEF_H__
|
|
||||||
#define __TFM_PERIPHERALS_DEF_H__
|
|
||||||
|
|
||||||
struct tfm_spm_partition_platform_data_t;
|
|
||||||
|
|
||||||
extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart;
|
|
||||||
|
|
||||||
#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart)
|
|
||||||
|
|
||||||
#endif /* __TFM_PERIPHERALS_DEF_H__ */
|
|
||||||
|
|
@ -1,48 +0,0 @@
|
||||||
/* mbed Microcontroller Library
|
|
||||||
* Copyright (c) 2018 ARM Limited
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "trng_api.h"
|
|
||||||
|
|
||||||
#if defined(DEVICE_TRNG)
|
|
||||||
#include "fsl_rng.h"
|
|
||||||
|
|
||||||
void trng_init(trng_t *obj)
|
|
||||||
{
|
|
||||||
/* Init RNGA */
|
|
||||||
RNG_Init(RNG);
|
|
||||||
}
|
|
||||||
|
|
||||||
void trng_free(trng_t *obj)
|
|
||||||
{
|
|
||||||
RNG_Deinit(RNG);
|
|
||||||
}
|
|
||||||
|
|
||||||
int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
|
|
||||||
{
|
|
||||||
status_t status;
|
|
||||||
|
|
||||||
/* Get Random data*/
|
|
||||||
status = RNG_GetRandomData(RNG, output, length);
|
|
||||||
if (status == kStatus_Success) {
|
|
||||||
*output_length = length;
|
|
||||||
return 0;
|
|
||||||
} else {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,292 +0,0 @@
|
||||||
/*
|
|
||||||
** ###################################################################
|
|
||||||
** Version: rev. 1.0, 2018-08-22
|
|
||||||
** Build: b190122
|
|
||||||
**
|
|
||||||
** Abstract:
|
|
||||||
** Chip specific module features.
|
|
||||||
**
|
|
||||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
|
||||||
** Copyright 2016-2019 NXP
|
|
||||||
** All rights reserved.
|
|
||||||
**
|
|
||||||
** SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
**
|
|
||||||
** http: www.nxp.com
|
|
||||||
** mail: support@nxp.com
|
|
||||||
**
|
|
||||||
** Revisions:
|
|
||||||
** - rev. 1.0 (2018-08-22)
|
|
||||||
** Initial version based on v0.2UM
|
|
||||||
**
|
|
||||||
** ###################################################################
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _LPC55S69_cm33_core0_FEATURES_H_
|
|
||||||
#define _LPC55S69_cm33_core0_FEATURES_H_
|
|
||||||
|
|
||||||
/* SOC module features */
|
|
||||||
|
|
||||||
/* @brief CASPER availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_CASPER_COUNT (1)
|
|
||||||
/* @brief CRC availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_CRC_COUNT (1)
|
|
||||||
/* @brief CTIMER availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
|
|
||||||
/* @brief DMA availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_DMA_COUNT (2)
|
|
||||||
/* @brief FLASH availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_FLASH_COUNT (1)
|
|
||||||
/* @brief FLEXCOMM availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9)
|
|
||||||
/* @brief GINT availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_GINT_COUNT (2)
|
|
||||||
/* @brief GPIO availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_GPIO_COUNT (1)
|
|
||||||
/* @brief SECGPIO availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_SECGPIO_COUNT (1)
|
|
||||||
/* @brief HASHCRYPT availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1)
|
|
||||||
/* @brief I2C availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_I2C_COUNT (8)
|
|
||||||
/* @brief I2S availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_I2S_COUNT (8)
|
|
||||||
/* @brief INPUTMUX availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
|
|
||||||
/* @brief IOCON availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_IOCON_COUNT (1)
|
|
||||||
/* @brief LPADC availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_LPADC_COUNT (1)
|
|
||||||
/* @brief MAILBOX availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
|
|
||||||
/* @brief MRT availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_MRT_COUNT (1)
|
|
||||||
/* @brief OSTIMER availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
|
|
||||||
/* @brief PINT availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_PINT_COUNT (1)
|
|
||||||
/* @brief SECPINT availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_SECPINT_COUNT (1)
|
|
||||||
/* @brief PMC availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_PMC_COUNT (1)
|
|
||||||
/* @brief POWERQUAD availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
|
|
||||||
/* @brief PUF availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_PUF_COUNT (1)
|
|
||||||
/* @brief RNG1 availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
|
|
||||||
/* @brief RTC availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_RTC_COUNT (1)
|
|
||||||
/* @brief SCT availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_SCT_COUNT (1)
|
|
||||||
/* @brief SDIF availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_SDIF_COUNT (1)
|
|
||||||
/* @brief SPI availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_SPI_COUNT (9)
|
|
||||||
/* @brief SYSCON availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
|
|
||||||
/* @brief SYSCTL1 availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1)
|
|
||||||
/* @brief USART availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_USART_COUNT (8)
|
|
||||||
/* @brief USB availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_USB_COUNT (1)
|
|
||||||
/* @brief USBFSH availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
|
|
||||||
/* @brief USBHSD availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
|
|
||||||
/* @brief USBHSH availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
|
|
||||||
/* @brief USBPHY availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_USBPHY_COUNT (1)
|
|
||||||
/* @brief UTICK availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_UTICK_COUNT (1)
|
|
||||||
/* @brief WWDT availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_WWDT_COUNT (1)
|
|
||||||
|
|
||||||
/* LPADC module features */
|
|
||||||
|
|
||||||
/* @brief FIFO availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_LPADC_FIFO_COUNT (2)
|
|
||||||
/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
|
|
||||||
/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
|
|
||||||
/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)
|
|
||||||
/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)
|
|
||||||
/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
|
|
||||||
/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
|
|
||||||
/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1)
|
|
||||||
/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1)
|
|
||||||
/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1)
|
|
||||||
/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
|
|
||||||
/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
|
|
||||||
/* @brief Has calibration (bitfield CFG[CALOFS]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
|
|
||||||
/* @brief Has offset trim (register OFSTRIM). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
|
|
||||||
|
|
||||||
/* CASPER module features */
|
|
||||||
|
|
||||||
/* @brief Base address of the CASPER dedicated RAM */
|
|
||||||
#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)
|
|
||||||
/* @brief Interleaving of the CASPER dedicated RAM */
|
|
||||||
#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)
|
|
||||||
|
|
||||||
/* DMA module features */
|
|
||||||
|
|
||||||
/* @brief Number of channels */
|
|
||||||
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
|
|
||||||
|
|
||||||
/* HASHCRYPT module features */
|
|
||||||
|
|
||||||
/* @brief the address of alias offset */
|
|
||||||
#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000)
|
|
||||||
|
|
||||||
/* I2S module features */
|
|
||||||
|
|
||||||
/* @brief I2S support dual channel transfer. */
|
|
||||||
#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
|
|
||||||
|
|
||||||
/* IOCON module features */
|
|
||||||
|
|
||||||
/* @brief Func bit field width */
|
|
||||||
#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
|
|
||||||
|
|
||||||
/* MAILBOX module features */
|
|
||||||
|
|
||||||
/* @brief Mailbox side for current core */
|
|
||||||
#define FSL_FEATURE_MAILBOX_SIDE_A (1)
|
|
||||||
|
|
||||||
/* MRT module features */
|
|
||||||
|
|
||||||
/* @brief number of channels. */
|
|
||||||
#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
|
|
||||||
|
|
||||||
/* PINT module features */
|
|
||||||
|
|
||||||
/* @brief Number of connected outputs */
|
|
||||||
#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (10)
|
|
||||||
|
|
||||||
/* POWERLIB module features */
|
|
||||||
|
|
||||||
/* @brief Niobe4's Powerlib API is different with other LPC series devices. */
|
|
||||||
#define FSL_FEATURE_POWERLIB_NIOBE4_EXTEND (1)
|
|
||||||
|
|
||||||
/* POWERQUAD module features */
|
|
||||||
|
|
||||||
/* @brief Sine and Cossine fix errata */
|
|
||||||
#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1)
|
|
||||||
|
|
||||||
/* PUF module features */
|
|
||||||
|
|
||||||
/* @brief Number of PUF key slots available on device. */
|
|
||||||
#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4)
|
|
||||||
/* @brief the shift status value */
|
|
||||||
#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)
|
|
||||||
|
|
||||||
/* SCT module features */
|
|
||||||
|
|
||||||
/* @brief Number of events */
|
|
||||||
#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
|
|
||||||
/* @brief Number of states */
|
|
||||||
#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32)
|
|
||||||
/* @brief Number of match capture */
|
|
||||||
#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
|
|
||||||
/* @brief Number of outputs */
|
|
||||||
#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
|
|
||||||
|
|
||||||
/* SDIF module features */
|
|
||||||
|
|
||||||
/* @brief FIFO depth, every location is a WORD */
|
|
||||||
#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
|
|
||||||
/* @brief Max DMA buffer size */
|
|
||||||
#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
|
|
||||||
/* @brief Max source clock in HZ */
|
|
||||||
#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
|
|
||||||
/* @brief support 2 cards */
|
|
||||||
#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)
|
|
||||||
|
|
||||||
/* SECPINT module features */
|
|
||||||
|
|
||||||
/* @brief Number of connected outputs */
|
|
||||||
#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2)
|
|
||||||
|
|
||||||
/* SYSCON module features */
|
|
||||||
|
|
||||||
/* @brief Pointer to ROM IAP entry functions */
|
|
||||||
#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
|
|
||||||
/* @brief Flash page size in bytes */
|
|
||||||
#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
|
|
||||||
/* @brief Flash sector size in bytes */
|
|
||||||
#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
|
|
||||||
/* @brief Flash size in bytes */
|
|
||||||
#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592)
|
|
||||||
/* @brief Has Power Down mode */
|
|
||||||
#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)
|
|
||||||
/* @brief CCM_ANALOG availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
|
|
||||||
|
|
||||||
/* USB module features */
|
|
||||||
|
|
||||||
/* @brief Size of the USB dedicated RAM */
|
|
||||||
#define FSL_FEATURE_USB_USB_RAM (0x00004000)
|
|
||||||
/* @brief Base address of the USB dedicated RAM */
|
|
||||||
#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
|
|
||||||
/* @brief USB version */
|
|
||||||
#define FSL_FEATURE_USB_VERSION (200)
|
|
||||||
/* @brief Number of the endpoint in USB FS */
|
|
||||||
#define FSL_FEATURE_USB_EP_NUM (5)
|
|
||||||
|
|
||||||
/* USBFSH module features */
|
|
||||||
|
|
||||||
/* @brief Size of the USB dedicated RAM */
|
|
||||||
#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000)
|
|
||||||
/* @brief Base address of the USB dedicated RAM */
|
|
||||||
#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
|
|
||||||
/* @brief USBFSH version */
|
|
||||||
#define FSL_FEATURE_USBFSH_VERSION (200)
|
|
||||||
|
|
||||||
/* USBHSD module features */
|
|
||||||
|
|
||||||
/* @brief Size of the USB dedicated RAM */
|
|
||||||
#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000)
|
|
||||||
/* @brief Base address of the USB dedicated RAM */
|
|
||||||
#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
|
|
||||||
/* @brief USBHSD version */
|
|
||||||
#define FSL_FEATURE_USBHSD_VERSION (300)
|
|
||||||
/* @brief Number of the endpoint in USB HS */
|
|
||||||
#define FSL_FEATURE_USBHSD_EP_NUM (6)
|
|
||||||
|
|
||||||
/* USBHSH module features */
|
|
||||||
|
|
||||||
/* @brief Size of the USB dedicated RAM */
|
|
||||||
#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000)
|
|
||||||
/* @brief Base address of the USB dedicated RAM */
|
|
||||||
#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
|
|
||||||
/* @brief USBHSH version */
|
|
||||||
#define FSL_FEATURE_USBHSH_VERSION (300)
|
|
||||||
|
|
||||||
/* UTICK module features */
|
|
||||||
|
|
||||||
/* @brief UTICK does not support PD configure. */
|
|
||||||
#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
|
|
||||||
|
|
||||||
/* WWDT module features */
|
|
||||||
|
|
||||||
/* @brief WWDT does not support oscillator lock. */
|
|
||||||
#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
|
|
||||||
/* @brief WWDT does not support power down configure */
|
|
||||||
#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
|
|
||||||
|
|
||||||
#endif /* _LPC55S69_cm33_core0_FEATURES_H_ */
|
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,292 +0,0 @@
|
||||||
/*
|
|
||||||
** ###################################################################
|
|
||||||
** Version: rev. 1.0, 2018-08-22
|
|
||||||
** Build: b190122
|
|
||||||
**
|
|
||||||
** Abstract:
|
|
||||||
** Chip specific module features.
|
|
||||||
**
|
|
||||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
|
||||||
** Copyright 2016-2019 NXP
|
|
||||||
** All rights reserved.
|
|
||||||
**
|
|
||||||
** SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
**
|
|
||||||
** http: www.nxp.com
|
|
||||||
** mail: support@nxp.com
|
|
||||||
**
|
|
||||||
** Revisions:
|
|
||||||
** - rev. 1.0 (2018-08-22)
|
|
||||||
** Initial version based on v0.2UM
|
|
||||||
**
|
|
||||||
** ###################################################################
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _LPC55S69_cm33_core1_FEATURES_H_
|
|
||||||
#define _LPC55S69_cm33_core1_FEATURES_H_
|
|
||||||
|
|
||||||
/* SOC module features */
|
|
||||||
|
|
||||||
/* @brief CASPER availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_CASPER_COUNT (1)
|
|
||||||
/* @brief CRC availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_CRC_COUNT (1)
|
|
||||||
/* @brief CTIMER availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
|
|
||||||
/* @brief DMA availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_DMA_COUNT (2)
|
|
||||||
/* @brief FLASH availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_FLASH_COUNT (1)
|
|
||||||
/* @brief FLEXCOMM availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9)
|
|
||||||
/* @brief GINT availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_GINT_COUNT (2)
|
|
||||||
/* @brief GPIO availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_GPIO_COUNT (1)
|
|
||||||
/* @brief SECGPIO availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_SECGPIO_COUNT (1)
|
|
||||||
/* @brief HASHCRYPT availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1)
|
|
||||||
/* @brief I2C availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_I2C_COUNT (8)
|
|
||||||
/* @brief I2S availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_I2S_COUNT (8)
|
|
||||||
/* @brief INPUTMUX availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
|
|
||||||
/* @brief IOCON availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_IOCON_COUNT (1)
|
|
||||||
/* @brief LPADC availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_LPADC_COUNT (1)
|
|
||||||
/* @brief MAILBOX availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
|
|
||||||
/* @brief MRT availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_MRT_COUNT (1)
|
|
||||||
/* @brief OSTIMER availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
|
|
||||||
/* @brief PINT availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_PINT_COUNT (1)
|
|
||||||
/* @brief SECPINT availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_SECPINT_COUNT (1)
|
|
||||||
/* @brief PMC availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_PMC_COUNT (1)
|
|
||||||
/* @brief POWERQUAD availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
|
|
||||||
/* @brief PUF availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_PUF_COUNT (1)
|
|
||||||
/* @brief RNG1 availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
|
|
||||||
/* @brief RTC availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_RTC_COUNT (1)
|
|
||||||
/* @brief SCT availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_SCT_COUNT (1)
|
|
||||||
/* @brief SDIF availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_SDIF_COUNT (1)
|
|
||||||
/* @brief SPI availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_SPI_COUNT (9)
|
|
||||||
/* @brief SYSCON availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
|
|
||||||
/* @brief SYSCTL1 availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1)
|
|
||||||
/* @brief USART availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_USART_COUNT (8)
|
|
||||||
/* @brief USB availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_USB_COUNT (1)
|
|
||||||
/* @brief USBFSH availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
|
|
||||||
/* @brief USBHSD availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
|
|
||||||
/* @brief USBHSH availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
|
|
||||||
/* @brief USBPHY availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_USBPHY_COUNT (1)
|
|
||||||
/* @brief UTICK availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_UTICK_COUNT (1)
|
|
||||||
/* @brief WWDT availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_WWDT_COUNT (1)
|
|
||||||
|
|
||||||
/* LPADC module features */
|
|
||||||
|
|
||||||
/* @brief FIFO availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_LPADC_FIFO_COUNT (2)
|
|
||||||
/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
|
|
||||||
/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
|
|
||||||
/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)
|
|
||||||
/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)
|
|
||||||
/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
|
|
||||||
/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
|
|
||||||
/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1)
|
|
||||||
/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1)
|
|
||||||
/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1)
|
|
||||||
/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
|
|
||||||
/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
|
|
||||||
/* @brief Has calibration (bitfield CFG[CALOFS]). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
|
|
||||||
/* @brief Has offset trim (register OFSTRIM). */
|
|
||||||
#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
|
|
||||||
|
|
||||||
/* CASPER module features */
|
|
||||||
|
|
||||||
/* @brief Base address of the CASPER dedicated RAM */
|
|
||||||
#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)
|
|
||||||
/* @brief Interleaving of the CASPER dedicated RAM */
|
|
||||||
#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)
|
|
||||||
|
|
||||||
/* DMA module features */
|
|
||||||
|
|
||||||
/* @brief Number of channels */
|
|
||||||
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
|
|
||||||
|
|
||||||
/* HASHCRYPT module features */
|
|
||||||
|
|
||||||
/* @brief the address of alias offset */
|
|
||||||
#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000)
|
|
||||||
|
|
||||||
/* I2S module features */
|
|
||||||
|
|
||||||
/* @brief I2S support dual channel transfer. */
|
|
||||||
#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
|
|
||||||
|
|
||||||
/* IOCON module features */
|
|
||||||
|
|
||||||
/* @brief Func bit field width */
|
|
||||||
#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
|
|
||||||
|
|
||||||
/* MAILBOX module features */
|
|
||||||
|
|
||||||
/* @brief Mailbox side for current core */
|
|
||||||
#define FSL_FEATURE_MAILBOX_SIDE_B (1)
|
|
||||||
|
|
||||||
/* MRT module features */
|
|
||||||
|
|
||||||
/* @brief number of channels. */
|
|
||||||
#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
|
|
||||||
|
|
||||||
/* PINT module features */
|
|
||||||
|
|
||||||
/* @brief Number of connected outputs */
|
|
||||||
#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (10)
|
|
||||||
|
|
||||||
/* POWERLIB module features */
|
|
||||||
|
|
||||||
/* @brief Niobe4's Powerlib API is different with other LPC series devices. */
|
|
||||||
#define FSL_FEATURE_POWERLIB_NIOBE4_EXTEND (1)
|
|
||||||
|
|
||||||
/* POWERQUAD module features */
|
|
||||||
|
|
||||||
/* @brief Sine and Cossine fix errata */
|
|
||||||
#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1)
|
|
||||||
|
|
||||||
/* PUF module features */
|
|
||||||
|
|
||||||
/* @brief Number of PUF key slots available on device. */
|
|
||||||
#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4)
|
|
||||||
/* @brief the shift status value */
|
|
||||||
#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)
|
|
||||||
|
|
||||||
/* SCT module features */
|
|
||||||
|
|
||||||
/* @brief Number of events */
|
|
||||||
#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
|
|
||||||
/* @brief Number of states */
|
|
||||||
#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32)
|
|
||||||
/* @brief Number of match capture */
|
|
||||||
#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
|
|
||||||
/* @brief Number of outputs */
|
|
||||||
#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
|
|
||||||
|
|
||||||
/* SDIF module features */
|
|
||||||
|
|
||||||
/* @brief FIFO depth, every location is a WORD */
|
|
||||||
#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
|
|
||||||
/* @brief Max DMA buffer size */
|
|
||||||
#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
|
|
||||||
/* @brief Max source clock in HZ */
|
|
||||||
#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
|
|
||||||
/* @brief support 2 cards */
|
|
||||||
#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)
|
|
||||||
|
|
||||||
/* SECPINT module features */
|
|
||||||
|
|
||||||
/* @brief Number of connected outputs */
|
|
||||||
#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2)
|
|
||||||
|
|
||||||
/* SYSCON module features */
|
|
||||||
|
|
||||||
/* @brief Pointer to ROM IAP entry functions */
|
|
||||||
#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
|
|
||||||
/* @brief Flash page size in bytes */
|
|
||||||
#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
|
|
||||||
/* @brief Flash sector size in bytes */
|
|
||||||
#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
|
|
||||||
/* @brief Flash size in bytes */
|
|
||||||
#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592)
|
|
||||||
/* @brief Has Power Down mode */
|
|
||||||
#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)
|
|
||||||
/* @brief CCM_ANALOG availability on the SoC. */
|
|
||||||
#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
|
|
||||||
|
|
||||||
/* USB module features */
|
|
||||||
|
|
||||||
/* @brief Size of the USB dedicated RAM */
|
|
||||||
#define FSL_FEATURE_USB_USB_RAM (0x00004000)
|
|
||||||
/* @brief Base address of the USB dedicated RAM */
|
|
||||||
#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
|
|
||||||
/* @brief USB version */
|
|
||||||
#define FSL_FEATURE_USB_VERSION (200)
|
|
||||||
/* @brief Number of the endpoint in USB FS */
|
|
||||||
#define FSL_FEATURE_USB_EP_NUM (5)
|
|
||||||
|
|
||||||
/* USBFSH module features */
|
|
||||||
|
|
||||||
/* @brief Size of the USB dedicated RAM */
|
|
||||||
#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000)
|
|
||||||
/* @brief Base address of the USB dedicated RAM */
|
|
||||||
#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
|
|
||||||
/* @brief USBFSH version */
|
|
||||||
#define FSL_FEATURE_USBFSH_VERSION (200)
|
|
||||||
|
|
||||||
/* USBHSD module features */
|
|
||||||
|
|
||||||
/* @brief Size of the USB dedicated RAM */
|
|
||||||
#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000)
|
|
||||||
/* @brief Base address of the USB dedicated RAM */
|
|
||||||
#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
|
|
||||||
/* @brief USBHSD version */
|
|
||||||
#define FSL_FEATURE_USBHSD_VERSION (300)
|
|
||||||
/* @brief Number of the endpoint in USB HS */
|
|
||||||
#define FSL_FEATURE_USBHSD_EP_NUM (6)
|
|
||||||
|
|
||||||
/* USBHSH module features */
|
|
||||||
|
|
||||||
/* @brief Size of the USB dedicated RAM */
|
|
||||||
#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000)
|
|
||||||
/* @brief Base address of the USB dedicated RAM */
|
|
||||||
#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
|
|
||||||
/* @brief USBHSH version */
|
|
||||||
#define FSL_FEATURE_USBHSH_VERSION (300)
|
|
||||||
|
|
||||||
/* UTICK module features */
|
|
||||||
|
|
||||||
/* @brief UTICK does not support PD configure. */
|
|
||||||
#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
|
|
||||||
|
|
||||||
/* WWDT module features */
|
|
||||||
|
|
||||||
/* @brief WWDT does not support oscillator lock. */
|
|
||||||
#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
|
|
||||||
/* @brief WWDT does not support power down configure */
|
|
||||||
#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
|
|
||||||
|
|
||||||
#endif /* _LPC55S69_cm33_core1_FEATURES_H_ */
|
|
||||||
|
|
||||||
Binary file not shown.
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Binary file not shown.
|
|
@ -1,31 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (C) 2009-2017 ARM Limited. All rights reserved.
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*
|
|
||||||
* A generic CMSIS include header, pulling in LPC54608 specifics
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef MBED_CMSIS_H
|
|
||||||
#define MBED_CMSIS_H
|
|
||||||
|
|
||||||
#include "fsl_device_registers.h"
|
|
||||||
#include "platform_regs.h" /* Platform registers */
|
|
||||||
#include "platform_retarget.h" /* Peripherals base addresses */
|
|
||||||
|
|
||||||
#if defined(TARGET_LPC55S69_NS)
|
|
||||||
#include "cmsis_nvic.h"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,44 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2014-2016 Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __FSL_DEVICE_REGISTERS_H__
|
|
||||||
#define __FSL_DEVICE_REGISTERS_H__
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Include the cpu specific register header files.
|
|
||||||
*
|
|
||||||
* The CPU macro should be declared in the project or makefile.
|
|
||||||
*/
|
|
||||||
#if (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JET98_cm33_core0))
|
|
||||||
|
|
||||||
#define LPC55S69_cm33_core0_SERIES
|
|
||||||
|
|
||||||
/* CMSIS-style register definitions */
|
|
||||||
#include "LPC55S69_cm33_core0.h"
|
|
||||||
/* CPU specific feature definitions */
|
|
||||||
#include "LPC55S69_cm33_core0_features.h"
|
|
||||||
|
|
||||||
#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JET98_cm33_core1))
|
|
||||||
|
|
||||||
#define LPC55S69_cm33_core1_SERIES
|
|
||||||
|
|
||||||
/* CMSIS-style register definitions */
|
|
||||||
#include "LPC55S69_cm33_core1.h"
|
|
||||||
/* CPU specific feature definitions */
|
|
||||||
#include "LPC55S69_cm33_core1_features.h"
|
|
||||||
|
|
||||||
#else
|
|
||||||
#error "No valid CPU defined!"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __FSL_DEVICE_REGISTERS_H__ */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* EOF
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
@ -1,44 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016-2018 Arm Limited
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*
|
|
||||||
* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2019 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __ARM_LTD_NIOBE_REGS_H__
|
|
||||||
#define __ARM_LTD_NIOBE_REGS_H__
|
|
||||||
|
|
||||||
#include <stdint.h>
|
|
||||||
#include "platform_retarget.h"
|
|
||||||
|
|
||||||
/* Secure System Control (SYSCTRL) Alias */
|
|
||||||
#define CMSDK_SYSCTRL_BASE_S SYSCON_BASE + 0xFA4
|
|
||||||
|
|
||||||
/* sysctrl memory mapped register access structure */
|
|
||||||
struct sysctrl_t {
|
|
||||||
union {
|
|
||||||
volatile uint32_t secdbgstat; /* (R/ ) Secure Debug Configuration
|
|
||||||
* Status Register*/
|
|
||||||
volatile uint32_t secdbgset; /* ( /W) Secure Debug Configuration
|
|
||||||
* Set Register */
|
|
||||||
volatile uint32_t secdbgclr; /* ( /W) Secure Debug Configuration
|
|
||||||
* Clear Register */
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
#endif /* __ARM_LTD_NIOBE_REGS_H__ */
|
|
||||||
|
|
@ -1,76 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2017-2018 Arm Limited
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License Version 2.0 (the "License");
|
|
||||||
* you may not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing software
|
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS
|
|
||||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*
|
|
||||||
* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2019 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \file platform_retarget.h
|
|
||||||
* \brief This file defines all the peripheral base addresses for Niobe platform.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __ARM_LTD_NIOBE_RETARGET_H__
|
|
||||||
#define __ARM_LTD_NIOBE_RETARGET_H__
|
|
||||||
|
|
||||||
#include "platform_regs.h" /* Platform registers */
|
|
||||||
#include "LPC55S69_cm33_core0.h"
|
|
||||||
|
|
||||||
|
|
||||||
/* SRAM MPC ranges and limits */
|
|
||||||
/* Internal memory */
|
|
||||||
#define MPC_ISRAM0_RANGE_BASE_NS 0x20000000
|
|
||||||
#define MPC_ISRAM0_RANGE_LIMIT_NS 0x2000FFFF
|
|
||||||
#define MPC_ISRAM0_RANGE_BASE_S 0x30000000
|
|
||||||
#define MPC_ISRAM0_RANGE_LIMIT_S 0x3000FFFF
|
|
||||||
|
|
||||||
#define MPC_ISRAM1_RANGE_BASE_NS 0x20010000
|
|
||||||
#define MPC_ISRAM1_RANGE_LIMIT_NS 0x2001FFFF
|
|
||||||
#define MPC_ISRAM1_RANGE_BASE_S 0x30010000
|
|
||||||
#define MPC_ISRAM1_RANGE_LIMIT_S 0x3001FFFF
|
|
||||||
|
|
||||||
#define MPC_ISRAM2_RANGE_BASE_NS 0x20020000
|
|
||||||
#define MPC_ISRAM2_RANGE_LIMIT_NS 0x2002FFFF
|
|
||||||
#define MPC_ISRAM2_RANGE_BASE_S 0x30020000
|
|
||||||
#define MPC_ISRAM2_RANGE_LIMIT_S 0x3002FFFF
|
|
||||||
|
|
||||||
#define MPC_ISRAM3_RANGE_BASE_NS 0x20030000
|
|
||||||
#define MPC_ISRAM3_RANGE_LIMIT_NS 0x2003FFFF
|
|
||||||
#define MPC_ISRAM3_RANGE_BASE_S 0x30030000
|
|
||||||
#define MPC_ISRAM3_RANGE_LIMIT_S 0x3003FFFF
|
|
||||||
|
|
||||||
#define MPC_ISRAM4_RANGE_BASE_NS 0x20040000
|
|
||||||
#define MPC_ISRAM4_RANGE_LIMIT_NS 0x20043FFF
|
|
||||||
#define MPC_ISRAM4_RANGE_BASE_S 0x30040000
|
|
||||||
#define MPC_ISRAM4_RANGE_LIMIT_S 0x30043FFF
|
|
||||||
|
|
||||||
/* Code SRAM memory */
|
|
||||||
#define MPC_CODE_SRAM_RANGE_BASE_NS (0x04000000)
|
|
||||||
#define MPC_CODE_SRAM_RANGE_LIMIT_NS (0x04007FFF)
|
|
||||||
#define MPC_CODE_SRAM_RANGE_BASE_S (0x14000000)
|
|
||||||
#define MPC_CODE_SRAM_RANGE_LIMIT_S (0x14007FFF)
|
|
||||||
|
|
||||||
/* Internal Flash memory */
|
|
||||||
#define FLASH0_BASE_S (0x10000000)
|
|
||||||
#define FLASH0_BASE_NS (0x00000000)
|
|
||||||
#define FLASH0_SIZE (0x0009FFFF) /* 640 kB */
|
|
||||||
#define FLASH0_SECTOR_SIZE (0x00008000) /* 32 kB */
|
|
||||||
#define FLASH0_PAGE_SIZE (0x00000200) /* 512 B */
|
|
||||||
#define FLASH0_PROGRAM_UNIT (0x4) /* Minimum write size */
|
|
||||||
|
|
||||||
#endif /* __ARM_LTD_NIOBE_RETARGET_H__ */
|
|
||||||
|
|
@ -1,369 +0,0 @@
|
||||||
/*
|
|
||||||
** ###################################################################
|
|
||||||
** Processors: LPC55S69JBD100_cm33_core0
|
|
||||||
** LPC55S69JET98_cm33_core0
|
|
||||||
**
|
|
||||||
** Compilers: GNU C Compiler
|
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
|
||||||
** Keil ARM C/C++ Compiler
|
|
||||||
** MCUXpresso Compiler
|
|
||||||
**
|
|
||||||
** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018
|
|
||||||
** Version: rev. 1.0, 2018-08-22
|
|
||||||
** Build: b181219
|
|
||||||
**
|
|
||||||
** Abstract:
|
|
||||||
** Provides a system configuration function and a global variable that
|
|
||||||
** contains the system frequency. It configures the device and initializes
|
|
||||||
** the oscillator (PLL) that is part of the microcontroller device.
|
|
||||||
**
|
|
||||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
|
||||||
** Copyright 2016-2018 NXP
|
|
||||||
** All rights reserved.
|
|
||||||
**
|
|
||||||
** SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
**
|
|
||||||
** http: www.nxp.com
|
|
||||||
** mail: support@nxp.com
|
|
||||||
**
|
|
||||||
** Revisions:
|
|
||||||
** - rev. 1.0 (2018-08-22)
|
|
||||||
** Initial version based on v0.2UM
|
|
||||||
**
|
|
||||||
** ###################################################################
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @file LPC55S69_cm33_core0
|
|
||||||
* @version 1.0
|
|
||||||
* @date 2018-08-22
|
|
||||||
* @brief Device specific configuration file for LPC55S69_cm33_core0
|
|
||||||
* (implementation file)
|
|
||||||
*
|
|
||||||
* Provides a system configuration function and a global variable that contains
|
|
||||||
* the system frequency. It configures the device and initializes the oscillator
|
|
||||||
* (PLL) that is part of the microcontroller device.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stdint.h>
|
|
||||||
#include "fsl_device_registers.h"
|
|
||||||
|
|
||||||
/* PLL0 SSCG control1 */
|
|
||||||
#define PLL_SSCG_MD_FRACT_P 0U
|
|
||||||
#define PLL_SSCG_MD_INT_P 25U
|
|
||||||
#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P)
|
|
||||||
#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P)
|
|
||||||
|
|
||||||
/* Get predivider (N) from PLL0 NDEC setting */
|
|
||||||
static uint32_t findPll0PreDiv(void)
|
|
||||||
{
|
|
||||||
uint32_t preDiv = 1;
|
|
||||||
|
|
||||||
/* Direct input is not used? */
|
|
||||||
if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0)
|
|
||||||
{
|
|
||||||
preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK;
|
|
||||||
if (preDiv == 0)
|
|
||||||
{
|
|
||||||
preDiv = 1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return preDiv;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get postdivider (P) from PLL0 PDEC setting */
|
|
||||||
static uint32_t findPll0PostDiv(void)
|
|
||||||
{
|
|
||||||
uint32_t postDiv = 1;
|
|
||||||
|
|
||||||
if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0)
|
|
||||||
{
|
|
||||||
if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK)
|
|
||||||
{
|
|
||||||
postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK);
|
|
||||||
}
|
|
||||||
if (postDiv == 0)
|
|
||||||
{
|
|
||||||
postDiv = 2;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return postDiv;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */
|
|
||||||
static float findPll0MMult(void)
|
|
||||||
{
|
|
||||||
float mMult = 1;
|
|
||||||
float mMult_fract;
|
|
||||||
uint32_t mMult_int;
|
|
||||||
|
|
||||||
if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK)
|
|
||||||
{
|
|
||||||
mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P);
|
|
||||||
mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M)/(1 << PLL_SSCG_MD_INT_P));
|
|
||||||
mMult = (float)mMult_int + mMult_fract;
|
|
||||||
}
|
|
||||||
if (mMult == 0)
|
|
||||||
{
|
|
||||||
mMult = 1;
|
|
||||||
}
|
|
||||||
return mMult;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get predivider (N) from PLL1 NDEC setting */
|
|
||||||
static uint32_t findPll1PreDiv(void)
|
|
||||||
{
|
|
||||||
uint32_t preDiv = 1;
|
|
||||||
|
|
||||||
/* Direct input is not used? */
|
|
||||||
if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0)
|
|
||||||
{
|
|
||||||
preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK;
|
|
||||||
if (preDiv == 0)
|
|
||||||
{
|
|
||||||
preDiv = 1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return preDiv;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get postdivider (P) from PLL1 PDEC setting */
|
|
||||||
static uint32_t findPll1PostDiv(void)
|
|
||||||
{
|
|
||||||
uint32_t postDiv = 1;
|
|
||||||
|
|
||||||
if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0)
|
|
||||||
{
|
|
||||||
if (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK)
|
|
||||||
{
|
|
||||||
postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
postDiv = 2 * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK);
|
|
||||||
}
|
|
||||||
if (postDiv == 0)
|
|
||||||
{
|
|
||||||
postDiv = 2;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return postDiv;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get multiplier (M) from PLL1 MDEC settings */
|
|
||||||
static uint32_t findPll1MMult(void)
|
|
||||||
{
|
|
||||||
uint32_t mMult = 1;
|
|
||||||
|
|
||||||
mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK;
|
|
||||||
|
|
||||||
if (mMult == 0)
|
|
||||||
{
|
|
||||||
mMult = 1;
|
|
||||||
}
|
|
||||||
return mMult;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get FRO 12M Clk */
|
|
||||||
/*! brief Return Frequency of FRO 12MHz
|
|
||||||
* return Frequency of FRO 12MHz
|
|
||||||
*/
|
|
||||||
static uint32_t CLOCK_GetFro12MFreq(void)
|
|
||||||
{
|
|
||||||
return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?
|
|
||||||
0 :
|
|
||||||
(ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get FRO 1M Clk */
|
|
||||||
/*! brief Return Frequency of FRO 1MHz
|
|
||||||
* return Frequency of FRO 1MHz
|
|
||||||
*/
|
|
||||||
static uint32_t CLOCK_GetFro1MFreq(void)
|
|
||||||
{
|
|
||||||
return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get EXT OSC Clk */
|
|
||||||
/*! brief Return Frequency of External Clock
|
|
||||||
* return Frequency of External Clock. If no external clock is used returns 0.
|
|
||||||
*/
|
|
||||||
static uint32_t CLOCK_GetExtClkFreq(void)
|
|
||||||
{
|
|
||||||
return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? CLK_CLK_IN : 0U;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get HF FRO Clk */
|
|
||||||
/*! brief Return Frequency of High-Freq output of FRO
|
|
||||||
* return Frequency of High-Freq output of FRO
|
|
||||||
*/
|
|
||||||
static uint32_t CLOCK_GetFroHfFreq(void)
|
|
||||||
{
|
|
||||||
return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?
|
|
||||||
0 :
|
|
||||||
(ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get RTC OSC Clk */
|
|
||||||
/*! brief Return Frequency of 32kHz osc
|
|
||||||
* return Frequency of 32kHz osc
|
|
||||||
*/
|
|
||||||
static uint32_t CLOCK_GetOsc32KFreq(void)
|
|
||||||
{
|
|
||||||
return ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(0))) ?
|
|
||||||
CLK_RTC_32K_CLK :
|
|
||||||
((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(1))) ?
|
|
||||||
CLK_RTC_32K_CLK :
|
|
||||||
0U;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* ----------------------------------------------------------------------------
|
|
||||||
-- Core clock
|
|
||||||
---------------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
|
||||||
|
|
||||||
/* ----------------------------------------------------------------------------
|
|
||||||
-- SystemInit()
|
|
||||||
---------------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
__attribute__ ((weak)) void SystemInit (void) {
|
|
||||||
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
|
|
||||||
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
|
|
||||||
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
|
|
||||||
|
|
||||||
SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access (enable PowerQuad) */
|
|
||||||
|
|
||||||
SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */
|
|
||||||
|
|
||||||
#if defined(__MCUXPRESSO)
|
|
||||||
extern void(*const g_pfnVectors[]) (void);
|
|
||||||
SCB->VTOR = (uint32_t) &g_pfnVectors;
|
|
||||||
#else
|
|
||||||
extern void *__Vectors;
|
|
||||||
SCB->VTOR = (uint32_t) &__Vectors;
|
|
||||||
#endif
|
|
||||||
SYSCON->TRACECLKDIV = 0;
|
|
||||||
/* Optionally enable RAM banks that may be off by default at reset */
|
|
||||||
#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
|
|
||||||
SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK
|
|
||||||
| SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK;
|
|
||||||
#endif
|
|
||||||
SystemInitHook();
|
|
||||||
}
|
|
||||||
|
|
||||||
/* ----------------------------------------------------------------------------
|
|
||||||
-- SystemCoreClockUpdate()
|
|
||||||
---------------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
void SystemCoreClockUpdate (void) {
|
|
||||||
uint32_t clkRate = 0;
|
|
||||||
uint32_t prediv, postdiv;
|
|
||||||
float workRate;
|
|
||||||
uint64_t workRate1;
|
|
||||||
|
|
||||||
switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
|
|
||||||
{
|
|
||||||
case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
|
|
||||||
switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
|
|
||||||
{
|
|
||||||
case 0x00: /* FRO 12 MHz (fro_12m) */
|
|
||||||
clkRate = CLOCK_GetFro12MFreq();
|
|
||||||
break;
|
|
||||||
case 0x01: /* CLKIN (clk_in) */
|
|
||||||
clkRate = CLOCK_GetExtClkFreq();
|
|
||||||
break;
|
|
||||||
case 0x02: /* Fro 1MHz (fro_1m) */
|
|
||||||
clkRate = CLOCK_GetFro1MFreq();
|
|
||||||
break;
|
|
||||||
default: /* = 0x03 = FRO 96 MHz (fro_hf) */
|
|
||||||
clkRate = CLOCK_GetFroHfFreq();
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case 0x01: /* PLL0 clock (pll0_clk)*/
|
|
||||||
switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)
|
|
||||||
{
|
|
||||||
case 0x00: /* FRO 12 MHz (fro_12m) */
|
|
||||||
clkRate = CLOCK_GetFro12MFreq();
|
|
||||||
break;
|
|
||||||
case 0x01: /* CLKIN (clk_in) */
|
|
||||||
clkRate = CLOCK_GetExtClkFreq();
|
|
||||||
break;
|
|
||||||
case 0x02: /* Fro 1MHz (fro_1m) */
|
|
||||||
clkRate = CLOCK_GetFro1MFreq();
|
|
||||||
break;
|
|
||||||
case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
|
|
||||||
clkRate = CLOCK_GetOsc32KFreq();
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0))
|
|
||||||
{
|
|
||||||
prediv = findPll0PreDiv();
|
|
||||||
postdiv = findPll0PostDiv();
|
|
||||||
/* Adjust input clock */
|
|
||||||
clkRate = clkRate / prediv;
|
|
||||||
/* MDEC used for rate */
|
|
||||||
workRate = (float)clkRate * (float)findPll0MMult();
|
|
||||||
clkRate = (uint32_t)(workRate / ((float)postdiv));
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case 0x02: /* PLL1 clock (pll1_clk)*/
|
|
||||||
switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)
|
|
||||||
{
|
|
||||||
case 0x00: /* FRO 12 MHz (fro_12m) */
|
|
||||||
clkRate = CLOCK_GetFro12MFreq();
|
|
||||||
break;
|
|
||||||
case 0x01: /* CLKIN (clk_in) */
|
|
||||||
clkRate = CLOCK_GetExtClkFreq();
|
|
||||||
break;
|
|
||||||
case 0x02: /* Fro 1MHz (fro_1m) */
|
|
||||||
clkRate = CLOCK_GetFro1MFreq();
|
|
||||||
break;
|
|
||||||
case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
|
|
||||||
clkRate = CLOCK_GetOsc32KFreq();
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0))
|
|
||||||
{
|
|
||||||
/* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
|
|
||||||
prediv = findPll1PreDiv();
|
|
||||||
postdiv = findPll1PostDiv();
|
|
||||||
/* Adjust input clock */
|
|
||||||
clkRate = clkRate / prediv;
|
|
||||||
|
|
||||||
/* MDEC used for rate */
|
|
||||||
workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult();
|
|
||||||
clkRate = workRate1 / ((uint64_t)postdiv);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
|
|
||||||
clkRate = CLOCK_GetOsc32KFreq();
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* ----------------------------------------------------------------------------
|
|
||||||
-- SystemInitHook()
|
|
||||||
---------------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
__attribute__ ((weak)) void SystemInitHook (void) {
|
|
||||||
/* Void implementation of the weak function. */
|
|
||||||
}
|
|
||||||
|
|
@ -1,110 +0,0 @@
|
||||||
/*
|
|
||||||
** ###################################################################
|
|
||||||
** Processors: LPC55S69JBD100_cm33_core0
|
|
||||||
** LPC55S69JET98_cm33_core0
|
|
||||||
**
|
|
||||||
** Compilers: GNU C Compiler
|
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
|
||||||
** Keil ARM C/C++ Compiler
|
|
||||||
** MCUXpresso Compiler
|
|
||||||
**
|
|
||||||
** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018
|
|
||||||
** Version: rev. 1.0, 2018-08-22
|
|
||||||
** Build: b181219
|
|
||||||
**
|
|
||||||
** Abstract:
|
|
||||||
** Provides a system configuration function and a global variable that
|
|
||||||
** contains the system frequency. It configures the device and initializes
|
|
||||||
** the oscillator (PLL) that is part of the microcontroller device.
|
|
||||||
**
|
|
||||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
|
||||||
** Copyright 2016-2018 NXP
|
|
||||||
** All rights reserved.
|
|
||||||
**
|
|
||||||
** SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
**
|
|
||||||
** http: www.nxp.com
|
|
||||||
** mail: support@nxp.com
|
|
||||||
**
|
|
||||||
** Revisions:
|
|
||||||
** - rev. 1.0 (2018-08-22)
|
|
||||||
** Initial version based on v0.2UM
|
|
||||||
**
|
|
||||||
** ###################################################################
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @file LPC55S69_cm33_core0
|
|
||||||
* @version 1.0
|
|
||||||
* @date 2018-08-22
|
|
||||||
* @brief Device specific configuration file for LPC55S69_cm33_core0 (header
|
|
||||||
* file)
|
|
||||||
*
|
|
||||||
* Provides a system configuration function and a global variable that contains
|
|
||||||
* the system frequency. It configures the device and initializes the oscillator
|
|
||||||
* (PLL) that is part of the microcontroller device.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _SYSTEM_LPC55S69_cm33_core0_H_
|
|
||||||
#define _SYSTEM_LPC55S69_cm33_core0_H_ /**< Symbol preventing repeated inclusion */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include <stdint.h>
|
|
||||||
|
|
||||||
#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */
|
|
||||||
#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */
|
|
||||||
#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */
|
|
||||||
#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */
|
|
||||||
#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */
|
|
||||||
#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief System clock frequency (core clock)
|
|
||||||
*
|
|
||||||
* The system clock frequency supplied to the SysTick timer and the processor
|
|
||||||
* core clock. This variable can be used by the user application to setup the
|
|
||||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
|
||||||
* query the frequency of the debug timer or configure the trace clock speed
|
|
||||||
* SystemCoreClock is initialized with a correct predefined value.
|
|
||||||
*/
|
|
||||||
extern uint32_t SystemCoreClock;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Setup the microcontroller system.
|
|
||||||
*
|
|
||||||
* Typically this function configures the oscillator (PLL) that is part of the
|
|
||||||
* microcontroller device. For systems with variable clock speed it also updates
|
|
||||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
|
||||||
*/
|
|
||||||
void SystemInit (void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Updates the SystemCoreClock variable.
|
|
||||||
*
|
|
||||||
* It must be called whenever the core clock is changed during program
|
|
||||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
|
||||||
* the current core clock.
|
|
||||||
*/
|
|
||||||
void SystemCoreClockUpdate (void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief SystemInit function hook.
|
|
||||||
*
|
|
||||||
* This weak function allows to call specific initialization code during the
|
|
||||||
* SystemInit() execution.This can be used when an application specific code needs
|
|
||||||
* to be called as close to the reset entry as possible (for example the Multicore
|
|
||||||
* Manager MCMGR_EarlyInit() function call).
|
|
||||||
* NOTE: No global r/w variables can be used in this hook function because the
|
|
||||||
* initialization of these variables happens after this function.
|
|
||||||
*/
|
|
||||||
void SystemInitHook (void);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* _SYSTEM_LPC55S69_cm33_core0_H_ */
|
|
||||||
|
|
@ -1,110 +0,0 @@
|
||||||
/*
|
|
||||||
** ###################################################################
|
|
||||||
** Processors: LPC55S69JBD100_cm33_core1
|
|
||||||
** LPC55S69JET98_cm33_core1
|
|
||||||
**
|
|
||||||
** Compilers: GNU C Compiler
|
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
|
||||||
** Keil ARM C/C++ Compiler
|
|
||||||
** MCUXpresso Compiler
|
|
||||||
**
|
|
||||||
** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018
|
|
||||||
** Version: rev. 1.0, 2018-08-22
|
|
||||||
** Build: b181219
|
|
||||||
**
|
|
||||||
** Abstract:
|
|
||||||
** Provides a system configuration function and a global variable that
|
|
||||||
** contains the system frequency. It configures the device and initializes
|
|
||||||
** the oscillator (PLL) that is part of the microcontroller device.
|
|
||||||
**
|
|
||||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
|
||||||
** Copyright 2016-2018 NXP
|
|
||||||
** All rights reserved.
|
|
||||||
**
|
|
||||||
** SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
**
|
|
||||||
** http: www.nxp.com
|
|
||||||
** mail: support@nxp.com
|
|
||||||
**
|
|
||||||
** Revisions:
|
|
||||||
** - rev. 1.0 (2018-08-22)
|
|
||||||
** Initial version based on v0.2UM
|
|
||||||
**
|
|
||||||
** ###################################################################
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @file LPC55S69_cm33_core1
|
|
||||||
* @version 1.0
|
|
||||||
* @date 2018-08-22
|
|
||||||
* @brief Device specific configuration file for LPC55S69_cm33_core1 (header
|
|
||||||
* file)
|
|
||||||
*
|
|
||||||
* Provides a system configuration function and a global variable that contains
|
|
||||||
* the system frequency. It configures the device and initializes the oscillator
|
|
||||||
* (PLL) that is part of the microcontroller device.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _SYSTEM_LPC55S69_cm33_core1_H_
|
|
||||||
#define _SYSTEM_LPC55S69_cm33_core1_H_ /**< Symbol preventing repeated inclusion */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include <stdint.h>
|
|
||||||
|
|
||||||
#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */
|
|
||||||
#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */
|
|
||||||
#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */
|
|
||||||
#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */
|
|
||||||
#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */
|
|
||||||
#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief System clock frequency (core clock)
|
|
||||||
*
|
|
||||||
* The system clock frequency supplied to the SysTick timer and the processor
|
|
||||||
* core clock. This variable can be used by the user application to setup the
|
|
||||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
|
||||||
* query the frequency of the debug timer or configure the trace clock speed
|
|
||||||
* SystemCoreClock is initialized with a correct predefined value.
|
|
||||||
*/
|
|
||||||
extern uint32_t SystemCoreClock;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Setup the microcontroller system.
|
|
||||||
*
|
|
||||||
* Typically this function configures the oscillator (PLL) that is part of the
|
|
||||||
* microcontroller device. For systems with variable clock speed it also updates
|
|
||||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
|
||||||
*/
|
|
||||||
void SystemInit (void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Updates the SystemCoreClock variable.
|
|
||||||
*
|
|
||||||
* It must be called whenever the core clock is changed during program
|
|
||||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
|
||||||
* the current core clock.
|
|
||||||
*/
|
|
||||||
void SystemCoreClockUpdate (void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief SystemInit function hook.
|
|
||||||
*
|
|
||||||
* This weak function allows to call specific initialization code during the
|
|
||||||
* SystemInit() execution.This can be used when an application specific code needs
|
|
||||||
* to be called as close to the reset entry as possible (for example the Multicore
|
|
||||||
* Manager MCMGR_EarlyInit() function call).
|
|
||||||
* NOTE: No global r/w variables can be used in this hook function because the
|
|
||||||
* initialization of these variables happens after this function.
|
|
||||||
*/
|
|
||||||
void SystemInitHook (void);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* _SYSTEM_LPC55S69_cm33_core1_H_ */
|
|
||||||
|
|
@ -1,320 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2018, NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
#include "fsl_anactrl.h"
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.anactrl"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Prototypes
|
|
||||||
******************************************************************************/
|
|
||||||
/*!
|
|
||||||
* @brief Get instance number for ANACTRL module.
|
|
||||||
*
|
|
||||||
* @param base ANACTRL peripheral base address
|
|
||||||
*/
|
|
||||||
static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base);
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables
|
|
||||||
******************************************************************************/
|
|
||||||
/*! @brief Pointers to ANACTRL bases for each instance. */
|
|
||||||
static ANACTRL_Type *const s_anactrlBases[] = ANACTRL_BASE_PTRS;
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/*! @brief Pointers to ANACTRL clocks for each instance. */
|
|
||||||
static const clock_ip_name_t s_anactrlClocks[] = ANALOGCTRL_CLOCKS;
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code
|
|
||||||
******************************************************************************/
|
|
||||||
/*!
|
|
||||||
* brief Get the ANACTRL instance from peripheral base address.
|
|
||||||
*
|
|
||||||
* param base ANACTRL peripheral base address.
|
|
||||||
* return ANACTRL instance.
|
|
||||||
*/
|
|
||||||
static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t instance;
|
|
||||||
|
|
||||||
/* Find the instance index from base address mappings. */
|
|
||||||
for (instance = 0; instance < ARRAY_SIZE(s_anactrlBases); instance++)
|
|
||||||
{
|
|
||||||
if (s_anactrlBases[instance] == base)
|
|
||||||
{
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
assert(instance < ARRAY_SIZE(s_anactrlBases));
|
|
||||||
|
|
||||||
return instance;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enable the access to ANACTRL registers and initialize ANACTRL module.
|
|
||||||
*
|
|
||||||
* @param base ANACTRL peripheral base address.
|
|
||||||
*/
|
|
||||||
void ANACTRL_Init(ANACTRL_Type *base)
|
|
||||||
{
|
|
||||||
assert(NULL != base);
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Enable the clock for ANACTRL instance. */
|
|
||||||
CLOCK_EnableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief De-initialize ANACTRL module.
|
|
||||||
*
|
|
||||||
* @param base ANACTRL peripheral base address.
|
|
||||||
*/
|
|
||||||
void ANACTRL_Deinit(ANACTRL_Type *base)
|
|
||||||
{
|
|
||||||
assert(NULL != base);
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Disable the clock for ANACTRL instance. */
|
|
||||||
CLOCK_DisableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set the on-chip high-speed Free Running Oscillator.
|
|
||||||
*
|
|
||||||
* @param base ANACTRL peripheral base address.
|
|
||||||
* @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure.
|
|
||||||
*/
|
|
||||||
void ANACTRL_SetFro192M(ANACTRL_Type *base, anactrl_fro192M_config_t *config)
|
|
||||||
{
|
|
||||||
assert(NULL != config);
|
|
||||||
|
|
||||||
uint32_t tmp32 = 0;
|
|
||||||
|
|
||||||
/* Set FRO trim values. */
|
|
||||||
base->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_WRTRIM_MASK;
|
|
||||||
tmp32 |= ANACTRL_FRO192M_CTRL_BIAS_TRIM(config->biasTrim) | ANACTRL_FRO192M_CTRL_TEMP_TRIM(config->tempTrim) |
|
|
||||||
ANACTRL_FRO192M_CTRL_DAC_TRIM(config->dacTrim);
|
|
||||||
|
|
||||||
if (config->enable12MHzClk)
|
|
||||||
{
|
|
||||||
tmp32 |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK;
|
|
||||||
}
|
|
||||||
if (config->enable48MhzClk)
|
|
||||||
{
|
|
||||||
tmp32 |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK;
|
|
||||||
}
|
|
||||||
if (config->enable96MHzClk)
|
|
||||||
{
|
|
||||||
tmp32 |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (config->enableAnalogTestBus)
|
|
||||||
{
|
|
||||||
tmp32 |= ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
base->FRO192M_CTRL |= tmp32;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get the default configuration of FRO192M.
|
|
||||||
* The default values are:
|
|
||||||
* code
|
|
||||||
* config->biasTrim = 0x1AU;
|
|
||||||
* config->tempTrim = 0x20U;
|
|
||||||
* config->enable12MHzClk = true;
|
|
||||||
* config->enable48MhzClk = true;
|
|
||||||
* config->dacTrim = 0x80U;
|
|
||||||
* config->enableAnalogTestBus = false;
|
|
||||||
* config->enable96MHzClk = false;
|
|
||||||
* encode
|
|
||||||
* @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure.
|
|
||||||
*/
|
|
||||||
void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config)
|
|
||||||
{
|
|
||||||
assert(NULL != config);
|
|
||||||
|
|
||||||
/* Initializes the configure structure to zero. */
|
|
||||||
memset(config, 0, sizeof(*config));
|
|
||||||
|
|
||||||
config->biasTrim = 0x1AU;
|
|
||||||
config->tempTrim = 0x20U;
|
|
||||||
config->enable12MHzClk = true;
|
|
||||||
config->enable48MhzClk = true;
|
|
||||||
config->dacTrim = 0x80U;
|
|
||||||
config->enableAnalogTestBus = false;
|
|
||||||
config->enable96MHzClk = false;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set the 32 MHz Crystal oscillator.
|
|
||||||
*
|
|
||||||
* @param base ANACTRL peripheral base address.
|
|
||||||
* @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure.
|
|
||||||
*/
|
|
||||||
void ANACTRL_SetXo32M(ANACTRL_Type *base, anactrl_xo32M_config_t *config)
|
|
||||||
{
|
|
||||||
assert(NULL != config);
|
|
||||||
|
|
||||||
uint32_t tmp32 = 0U;
|
|
||||||
|
|
||||||
/* Set XO32M CTRL. */
|
|
||||||
if (config->enableACBufferBypass)
|
|
||||||
{
|
|
||||||
tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK;
|
|
||||||
}
|
|
||||||
if (config->enablePllUsbOutput)
|
|
||||||
{
|
|
||||||
tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;
|
|
||||||
}
|
|
||||||
if (config->enableSysCLkOutput)
|
|
||||||
{
|
|
||||||
tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;
|
|
||||||
}
|
|
||||||
base->XO32M_CTRL = tmp32;
|
|
||||||
|
|
||||||
/* Set LDO XO32M. */
|
|
||||||
tmp32 = ANACTRL_LDO_XO32M_HIGHZ(config->LDOOutputMode) | ANACTRL_LDO_XO32M_VOUT(config->LDOOutputLevel) |
|
|
||||||
ANACTRL_LDO_XO32M_IBIAS(config->bias) | ANACTRL_LDO_XO32M_STABMODE(config->stability);
|
|
||||||
if (config->enableLDOBypass)
|
|
||||||
{
|
|
||||||
tmp32 |= ANACTRL_LDO_XO32M_BYPASS_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
base->LDO_XO32M = tmp32;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get the default configuration of XO32M.
|
|
||||||
* The default values are:
|
|
||||||
* code
|
|
||||||
* config->enableACBufferBypass = false;
|
|
||||||
* config->enablePllUsbOutput = false;
|
|
||||||
* config->enableSysCLkOutput = false;
|
|
||||||
* config->enableLDOBypass = false;
|
|
||||||
* config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode;
|
|
||||||
* config->LDOOutputLevel = kANACTRL_LDOOutputLevel4;
|
|
||||||
* config->bias = 2U;
|
|
||||||
* config->stability = 3U;
|
|
||||||
* encode
|
|
||||||
* @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure.
|
|
||||||
*/
|
|
||||||
void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config)
|
|
||||||
{
|
|
||||||
assert(NULL != config);
|
|
||||||
|
|
||||||
/* Initializes the configure structure to zero. */
|
|
||||||
memset(config, 0, sizeof(*config));
|
|
||||||
|
|
||||||
config->enableACBufferBypass = false;
|
|
||||||
config->enablePllUsbOutput = false;
|
|
||||||
config->enableSysCLkOutput = false;
|
|
||||||
config->enableLDOBypass = false;
|
|
||||||
config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode;
|
|
||||||
config->LDOOutputLevel = kANACTRL_LDOOutputLevel4;
|
|
||||||
config->bias = 2U;
|
|
||||||
config->stability = 3U;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set the ring oscillators.
|
|
||||||
*
|
|
||||||
* @param base ANACTRL peripheral base address.
|
|
||||||
* @param config Pointer to ring osc configuration structure. Refer to "anactrl_ring_osc_config_t" structure.
|
|
||||||
*/
|
|
||||||
void ANACTRL_SetRingOsc(ANACTRL_Type *base, anactrl_ring_osc_config_t *config)
|
|
||||||
{
|
|
||||||
assert(NULL != config);
|
|
||||||
|
|
||||||
uint32_t tmp32 = 0U;
|
|
||||||
|
|
||||||
/* Configure the first ring oscillator. */
|
|
||||||
tmp32 = ANACTRL_RINGO0_CTRL_SL(config->ringOscSel) | ANACTRL_RINGO0_CTRL_FS(config->ringOscFreqOutputDiv) |
|
|
||||||
ANACTRL_RINGO0_CTRL_SWN_SWP(config->pnRingOscMode) | ANACTRL_RINGO0_CTRL_E_ND0_MASK |
|
|
||||||
ANACTRL_RINGO0_CTRL_E_ND1_MASK | ANACTRL_RINGO0_CTRL_E_NR0_MASK | ANACTRL_RINGO0_CTRL_E_NR1_MASK |
|
|
||||||
ANACTRL_RINGO0_CTRL_E_IV0_MASK | ANACTRL_RINGO0_CTRL_E_IV1_MASK | ANACTRL_RINGO0_CTRL_E_PN0_MASK |
|
|
||||||
ANACTRL_RINGO0_CTRL_E_PN1_MASK | ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK |
|
|
||||||
ANACTRL_RINGO0_CTRL_DIVISOR(config->ringOscOutClkDiv);
|
|
||||||
base->RINGO0_CTRL = tmp32;
|
|
||||||
|
|
||||||
/* Configure the second and third ring oscillator. */
|
|
||||||
tmp32 = ANACTRL_RINGO1_CTRL_S(config->ringOscSel) | ANACTRL_RINGO1_CTRL_FS(config->ringOscFreqOutputDiv) |
|
|
||||||
ANACTRL_RINGO1_CTRL_E_R24_MASK | ANACTRL_RINGO1_CTRL_E_R35_MASK | ANACTRL_RINGO1_CTRL_E_M2_MASK |
|
|
||||||
ANACTRL_RINGO1_CTRL_E_M3_MASK | ANACTRL_RINGO1_CTRL_E_M4_MASK | ANACTRL_RINGO1_CTRL_E_M5_MASK |
|
|
||||||
ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK | ANACTRL_RINGO1_CTRL_DIVISOR(config->ringOscOutClkDiv);
|
|
||||||
base->RINGO1_CTRL = tmp32;
|
|
||||||
base->RINGO2_CTRL = tmp32;
|
|
||||||
|
|
||||||
/* Ensure the Riongo module is enabled. */
|
|
||||||
base->RINGO0_CTRL &= ~ANACTRL_RINGO0_CTRL_PD_MASK;
|
|
||||||
base->RINGO1_CTRL &= ~ANACTRL_RINGO1_CTRL_PD_MASK;
|
|
||||||
base->RINGO2_CTRL &= ~ANACTRL_RINGO2_CTRL_PD_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get the default configuration of ring oscillators.
|
|
||||||
* The default values are:
|
|
||||||
* code
|
|
||||||
* config->ringOscSel = kANACTRL_ShortRingOsc;
|
|
||||||
* config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput;
|
|
||||||
* config->pnRingOscMode = kANACTRL_NormalMode;
|
|
||||||
* config->ringOscOutClkDiv = 0U;
|
|
||||||
* encode
|
|
||||||
* @param config Pointer to ring oscillator configuration structure. Refer to "anactrl_ring_osc_config_t" structure.
|
|
||||||
*/
|
|
||||||
void ANACTRL_GetDefaultRingOscConfig(anactrl_ring_osc_config_t *config)
|
|
||||||
{
|
|
||||||
assert(NULL != config);
|
|
||||||
|
|
||||||
/* Initializes the configure structure to zero. */
|
|
||||||
memset(config, 0, sizeof(*config));
|
|
||||||
|
|
||||||
config->ringOscSel = kANACTRL_ShortRingOsc;
|
|
||||||
config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput;
|
|
||||||
config->pnRingOscMode = kANACTRL_NormalMode;
|
|
||||||
config->ringOscOutClkDiv = 0U;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Measure Frequency
|
|
||||||
*
|
|
||||||
* This function measures target frequency according to a accurate reference frequency.The formula is:
|
|
||||||
* Ftarget = (CAPVAL * Freference) / ((1<<SCALE)-1)
|
|
||||||
*
|
|
||||||
* @param base ANACTRL peripheral base address.
|
|
||||||
* @scale Define the power of 2 count that ref counter counts to during measurement.
|
|
||||||
* @refClkFreq frequency of the reference clock.
|
|
||||||
* @return frequency of the target clock.
|
|
||||||
*
|
|
||||||
* @Note the minimum count (scale) is 2.
|
|
||||||
*/
|
|
||||||
uint32_t ANACTRL_MeasureFrequency(ANACTRL_Type *base, uint8_t scale, uint32_t refClkFreq)
|
|
||||||
{
|
|
||||||
assert(scale >= 2U);
|
|
||||||
|
|
||||||
uint32_t targetClkFreq = 0U;
|
|
||||||
uint32_t capval = 0U;
|
|
||||||
|
|
||||||
/* Init a measurement cycle. */
|
|
||||||
base->FREQ_ME_CTRL = ANACTRL_FREQ_ME_CTRL_PROG_MASK + ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(scale);
|
|
||||||
while (ANACTRL_FREQ_ME_CTRL_PROG_MASK == (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_PROG_MASK))
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Calculate the target clock frequency. */
|
|
||||||
capval = (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK);
|
|
||||||
targetClkFreq = (capval * refClkFreq) / ((1 << scale) - 1);
|
|
||||||
|
|
||||||
return targetClkFreq;
|
|
||||||
}
|
|
||||||
|
|
@ -1,458 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2018, NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __FSL_ANACTRL_H__
|
|
||||||
#define __FSL_ANACTRL_H__
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup anactrl
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
/*! @brief ANACTRL driver version. */
|
|
||||||
#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */`
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief ANACTRL interrupt flags
|
|
||||||
*/
|
|
||||||
enum _anactrl_interrupt_flags
|
|
||||||
{
|
|
||||||
kANACTRL_BodVbatFlag =
|
|
||||||
ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before Interrupt Enable. */
|
|
||||||
kANACTRL_BodVbatInterruptFlag =
|
|
||||||
ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status after Interrupt Enable. */
|
|
||||||
kANACTRL_BodVbatPowerFlag =
|
|
||||||
ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power status output. */
|
|
||||||
kANACTRL_BodCoreFlag =
|
|
||||||
ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before Interrupt Enable. */
|
|
||||||
kANACTRL_BodCoreInterruptFlag =
|
|
||||||
ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status after Interrupt Enable. */
|
|
||||||
kANACTRL_BodCorePowerFlag =
|
|
||||||
ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK, /*!< Current value of BOD CORE power status output. */
|
|
||||||
kANACTRL_DcdcFlag =
|
|
||||||
ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK, /*!< DCDC Interrupt status before Interrupt Enable. */
|
|
||||||
kANACTRL_DcdcInterruptFlag =
|
|
||||||
ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after Interrupt Enable. */
|
|
||||||
kANACTRL_DcdcPowerFlag =
|
|
||||||
ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK, /*!< Current value of DCDC power status output. */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief ANACTRL interrupt control
|
|
||||||
*/
|
|
||||||
enum _anactrl_interrupt
|
|
||||||
{
|
|
||||||
kANACTRL_BodVbatInterruptEnable =
|
|
||||||
ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt control. */
|
|
||||||
kANACTRL_BodCoreInterruptEnable =
|
|
||||||
ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK, /*!< BOD CORE interrupt control. */
|
|
||||||
kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK, /*!< DCDC interrupt control. */
|
|
||||||
kANACTRL_BodVbatInterruptClear =
|
|
||||||
ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK, /*!< BOD VBAT interrupt clear.1: Clear the interrupt.
|
|
||||||
Self-cleared bit. */
|
|
||||||
kANACTRL_BodCoreInterruptClear =
|
|
||||||
ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK, /*!< BOD CORE interrupt clear.1: Clear the interrupt.
|
|
||||||
Self-cleared bit. */
|
|
||||||
kANACTRL_DcdcInterruptClear = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK, /*!< DCDC interrupt clear.1: Clear the
|
|
||||||
interrupt. Self-cleared bit. */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief ANACTRL status flags
|
|
||||||
*/
|
|
||||||
enum _anactrl_flags
|
|
||||||
{
|
|
||||||
kANACTRL_PMUId = ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK, /*!< Power Management Unit (PMU) analog macro-bloc
|
|
||||||
identification number. */
|
|
||||||
kANACTRL_OSCId =
|
|
||||||
ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK, /*!< Oscillators analog macro-bloc identification number. */
|
|
||||||
kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK, /*!< Flash power-down status. */
|
|
||||||
kANACTRL_FlashInitErrorFlag =
|
|
||||||
ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization error status. */
|
|
||||||
kANACTRL_FinalTestFlag =
|
|
||||||
ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK, /*!< Indicates current status of final test. */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief ANACTRL FRO192M and XO32M status flags
|
|
||||||
*/
|
|
||||||
enum _anactrl_osc_flags
|
|
||||||
{
|
|
||||||
kANACTRL_OutputClkValidFlag = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK, /*!< Output clock valid signal. */
|
|
||||||
kANACTRL_CCOThresholdVoltageFlag =
|
|
||||||
ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK, /*!< CCO threshold voltage detector output (signal vcco_ok). */
|
|
||||||
kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK
|
|
||||||
<< 16U, /*!< Indicates XO out frequency statibilty. */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief LDO output mode
|
|
||||||
*/
|
|
||||||
typedef enum _anactrl_ldo_output_mode
|
|
||||||
{
|
|
||||||
kANACTRL_LDOOutputHighNormalMode = 0U, /*!< Output in High normal state. */
|
|
||||||
kANACTRL_LDOOutputHighImpedanceMode = 1U, /*!< Output in High Impedance state. */
|
|
||||||
} anactrl_ldo_output_mode_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief LDO output level
|
|
||||||
*/
|
|
||||||
typedef enum _anactrl_ldo_output_level
|
|
||||||
{
|
|
||||||
kANACTRL_LDOOutputLevel0 = 0U, /*!< Output level 0.750 V. */
|
|
||||||
kANACTRL_LDOOutputLevel1, /*!< Output level 0.775 V. */
|
|
||||||
kANACTRL_LDOOutputLevel2, /*!< Output level 0.800 V. */
|
|
||||||
kANACTRL_LDOOutputLevel3, /*!< Output level 0.825 V. */
|
|
||||||
kANACTRL_LDOOutputLevel4, /*!< Output level 0.850 V. */
|
|
||||||
kANACTRL_LDOOutputLevel5, /*!< Output level 0.875 V. */
|
|
||||||
kANACTRL_LDOOutputLevel6, /*!< Output level 0.900 V. */
|
|
||||||
kANACTRL_LDOOutputLevel7, /*!< Output level 0.925 V. */
|
|
||||||
} anactrl_ldo_output_level_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Select short or long ring osc
|
|
||||||
*/
|
|
||||||
typedef enum _anactrl_ring_osc_selector
|
|
||||||
{
|
|
||||||
kANACTRL_ShortRingOsc = 0U, /*!< Select short ring osc (few elements). */
|
|
||||||
kANACTRL_LongRingOsc = 1U, /*!< Select long ring osc (many elements). */
|
|
||||||
} anactrl_ring_osc_selector_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Ring osc frequency output divider
|
|
||||||
*/
|
|
||||||
typedef enum _anactrl_ring_osc_freq_output_divider
|
|
||||||
{
|
|
||||||
kANACTRL_HighFreqOutput = 0U, /*!< High frequency output (frequency lower than 100 MHz). */
|
|
||||||
kANACTRL_LowFreqOutput = 1U, /*!< Low frequency output (frequency lower than 10 MHz). */
|
|
||||||
} anactrl_ring_osc_freq_output_divider_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief PN-Ring osc (P-Transistor and N-Transistor processing) control.
|
|
||||||
*/
|
|
||||||
typedef enum _anactrl_pn_ring_osc_mode
|
|
||||||
{
|
|
||||||
kANACTRL_NormalMode = 0U, /*!< Normal mode. */
|
|
||||||
kANACTRL_PMonitorPTransistorMode = 1U, /*!< P-Monitor mode. Measure with weak P transistor. */
|
|
||||||
kANACTRL_PMonitorNTransistorMode = 2U, /*!< P-Monitor mode. Measure with weak N transistor. */
|
|
||||||
kANACTRL_NotUse = 3U, /*!< Do not use. */
|
|
||||||
} anactrl_pn_ring_osc_mode_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @breif Configuration for FRO192M
|
|
||||||
*
|
|
||||||
* This structure holds the configuration settings for the on-chip high-speed Free Running Oscillator. To initialize
|
|
||||||
* this structure to reasonable defaults, call the ANACTRL_GetDefaultFro192MConfig() function and pass a
|
|
||||||
* pointer to your config structure instance.
|
|
||||||
*/
|
|
||||||
typedef struct _anactrl_fro192M_config
|
|
||||||
{
|
|
||||||
uint8_t biasTrim; /*!< Set bias trimming value (course frequency trimming). */
|
|
||||||
uint8_t tempTrim; /*!< Set temperature coefficient trimming value. */
|
|
||||||
uint8_t dacTrim; /*!< Set curdac trimming value (fine frequency trimming) This trim is used to
|
|
||||||
adjust the frequency, given that the bias and temperature trim are set. */
|
|
||||||
bool enable12MHzClk; /*!< Enable 12MHz clock. */
|
|
||||||
bool enable48MhzClk; /*!< Enable 48MHz clock. */
|
|
||||||
bool enable96MHzClk; /*!< Enable 96MHz clock. */
|
|
||||||
bool enableAnalogTestBus; /*!< Enable analog test bus. */
|
|
||||||
} anactrl_fro192M_config_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @breif Configuration for XO32M
|
|
||||||
*
|
|
||||||
* This structure holds the configuration settings for the 32 MHz crystal oscillator. To initialize this
|
|
||||||
* structure to reasonable defaults, call the ANACTRL_GetDefaultXo32MConfig() function and pass a
|
|
||||||
* pointer to your config structure instance.
|
|
||||||
*/
|
|
||||||
typedef struct _anactrl_xo32M_config
|
|
||||||
{
|
|
||||||
bool enableACBufferBypass; /*!< Enable XO AC buffer bypass in pll and top level. */
|
|
||||||
bool enablePllUsbOutput; /*!< Enable XO 32 MHz output to USB HS PLL. */
|
|
||||||
bool enableSysCLkOutput; /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */
|
|
||||||
bool enableLDOBypass; /*!< Activate LDO bypass. */
|
|
||||||
anactrl_ldo_output_mode_t LDOOutputMode; /*!< Set LDO output mode. */
|
|
||||||
anactrl_ldo_output_level_t LDOOutputLevel; /*!< Set LDO output level. */
|
|
||||||
uint8_t bias; /*!< Adjust the biasing current. */
|
|
||||||
uint8_t stability; /*!< Stability configuration. */
|
|
||||||
} anactrl_xo32M_config_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @breif Configuration for ring oscillator
|
|
||||||
*
|
|
||||||
* This structure holds the configuration settings for the three ring oscillators. To initialize this
|
|
||||||
* structure to reasonable defaults, call the ANACTRL_GetDefaultRingOscConfig() function and pass a
|
|
||||||
* pointer to your config structure instance.
|
|
||||||
*/
|
|
||||||
typedef struct _anactrl_ring_osc_config
|
|
||||||
{
|
|
||||||
anactrl_ring_osc_selector_t ringOscSel;
|
|
||||||
anactrl_ring_osc_freq_output_divider_t ringOscFreqOutputDiv;
|
|
||||||
anactrl_pn_ring_osc_mode_t pnRingOscMode;
|
|
||||||
uint8_t ringOscOutClkDiv;
|
|
||||||
} anactrl_ring_osc_config_t;
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Initialization and deinitialization
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enable the access to ANACTRL registers and initialize ANACTRL module.
|
|
||||||
*
|
|
||||||
* @param base ANACTRL peripheral base address.
|
|
||||||
*/
|
|
||||||
void ANACTRL_Init(ANACTRL_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief De-initialize ANACTRL module.
|
|
||||||
*
|
|
||||||
* @param base ANACTRL peripheral base address.
|
|
||||||
*/
|
|
||||||
void ANACTRL_Deinit(ANACTRL_Type *base);
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Set oscillators
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set the on-chip high-speed Free Running Oscillator.
|
|
||||||
*
|
|
||||||
* @param base ANACTRL peripheral base address.
|
|
||||||
* @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure.
|
|
||||||
*/
|
|
||||||
void ANACTRL_SetFro192M(ANACTRL_Type *base, anactrl_fro192M_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get the default configuration of FRO192M.
|
|
||||||
* The default values are:
|
|
||||||
* code
|
|
||||||
* config->biasTrim = 0x1AU;
|
|
||||||
* config->tempTrim = 0x20U;
|
|
||||||
* config->enable12MHzClk = true;
|
|
||||||
* config->enable48MhzClk = true;
|
|
||||||
* config->dacTrim = 0x80U;
|
|
||||||
* config->enableAnalogTestBus = false;
|
|
||||||
* config->enable96MHzClk = false;
|
|
||||||
* encode
|
|
||||||
* @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure.
|
|
||||||
*/
|
|
||||||
void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set the 32 MHz Crystal oscillator.
|
|
||||||
*
|
|
||||||
* @param base ANACTRL peripheral base address.
|
|
||||||
* @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure.
|
|
||||||
*/
|
|
||||||
void ANACTRL_SetXo32M(ANACTRL_Type *base, anactrl_xo32M_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get the default configuration of XO32M.
|
|
||||||
* The default values are:
|
|
||||||
* code
|
|
||||||
* config->enableACBufferBypass = false;
|
|
||||||
* config->enablePllUsbOutput = false;
|
|
||||||
* config->enableSysCLkOutput = false;
|
|
||||||
* config->enableLDOBypass = false;
|
|
||||||
* config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode;
|
|
||||||
* config->LDOOutputLevel = kANACTRL_LDOOutputLevel4;
|
|
||||||
* config->bias = 2U;
|
|
||||||
* config->stability = 3U;
|
|
||||||
* encode
|
|
||||||
* @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure.
|
|
||||||
*/
|
|
||||||
void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set the ring oscillators.
|
|
||||||
*
|
|
||||||
* @param base ANACTRL peripheral base address.
|
|
||||||
* @param config Pointer to ring osc configuration structure. Refer to "anactrl_ring_osc_config_t" structure.
|
|
||||||
*/
|
|
||||||
void ANACTRL_SetRingOsc(ANACTRL_Type *base, anactrl_ring_osc_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get the default configuration of ring oscillators.
|
|
||||||
* The default values are:
|
|
||||||
* code
|
|
||||||
* config->ringOscSel = kANACTRL_ShortRingOsc;
|
|
||||||
* config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput;
|
|
||||||
* config->pnRingOscMode = kANACTRL_NormalMode;
|
|
||||||
* config->ringOscOutClkDiv = 0U;
|
|
||||||
* encode
|
|
||||||
* @param config Pointer to ring oscillator configuration structure. Refer to "anactrl_ring_osc_config_t" structure.
|
|
||||||
*/
|
|
||||||
void ANACTRL_GetDefaultRingOscConfig(anactrl_ring_osc_config_t *config);
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name ADC control
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enable VBAT divider branch.
|
|
||||||
*
|
|
||||||
* @param base ANACTRL peripheral base address.
|
|
||||||
* @param enable switcher to the function.
|
|
||||||
*/
|
|
||||||
static inline void ANACTRL_EnableAdcVBATDivider(ANACTRL_Type *base, bool enable)
|
|
||||||
{
|
|
||||||
if (enable)
|
|
||||||
{
|
|
||||||
base->ADC_CTRL |= ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
base->ADC_CTRL &= ~ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Measure Frequency
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Measure Frequency
|
|
||||||
*
|
|
||||||
* This function measures target frequency according to a accurate reference frequency.The formula is:
|
|
||||||
* Ftarget = (CAPVAL * Freference) / ((1<<SCALE)-1)
|
|
||||||
*
|
|
||||||
* @param base ANACTRL peripheral base address.
|
|
||||||
* @scale Define the power of 2 count that ref counter counts to during measurement.
|
|
||||||
* @refClkFreq frequency of the reference clock.
|
|
||||||
* @return frequency of the target clock.
|
|
||||||
*
|
|
||||||
* @Note the minimum count (scale) is 2.
|
|
||||||
*/
|
|
||||||
uint32_t ANACTRL_MeasureFrequency(ANACTRL_Type *base, uint8_t scale, uint32_t refClkFreq);
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Interrupt Interface
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enable the ANACTRL interrupts.
|
|
||||||
*
|
|
||||||
* @param bas ANACTRL peripheral base address.
|
|
||||||
* @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration.
|
|
||||||
*/
|
|
||||||
static inline void ANACTRL_EnableInterrupt(ANACTRL_Type *base, uint32_t mask)
|
|
||||||
{
|
|
||||||
base->BOD_DCDC_INT_CTRL |= (0x15U & mask);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Disable the ANACTRL interrupts.
|
|
||||||
*
|
|
||||||
* @param bas ANACTRL peripheral base address.
|
|
||||||
* @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration.
|
|
||||||
*/
|
|
||||||
static inline void ANACTRL_DisableInterrupt(ANACTRL_Type *base, uint32_t mask)
|
|
||||||
{
|
|
||||||
base->BOD_DCDC_INT_CTRL = (base->BOD_DCDC_INT_CTRL & ~0x2AU) | (mask & 0x2AU);
|
|
||||||
}
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Status Interface
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get ANACTRL status flags.
|
|
||||||
*
|
|
||||||
* This function gets Analog control status flags. The flags are returned as the logical
|
|
||||||
* OR value of the enumerators @ref _anactrl_flags. To check for a specific status,
|
|
||||||
* compare the return value with enumerators in the @ref _anactrl_flags.
|
|
||||||
* For example, to check whether the flash is in power down mode:
|
|
||||||
* @code
|
|
||||||
* if (kANACTRL_FlashPowerDownFlag & ANACTRL_ANACTRL_GetStatusFlags(ANACTRL))
|
|
||||||
* {
|
|
||||||
* ...
|
|
||||||
* }
|
|
||||||
* @endcode
|
|
||||||
*
|
|
||||||
* @param base ANACTRL peripheral base address.
|
|
||||||
* @return ANACTRL status flags which are given in the enumerators in the @ref _anactrl_flags.
|
|
||||||
*/
|
|
||||||
static inline uint32_t ANACTRL_GetStatusFlags(ANACTRL_Type *base)
|
|
||||||
{
|
|
||||||
return base->ANALOG_CTRL_STATUS;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get ANACTRL oscillators status flags.
|
|
||||||
*
|
|
||||||
* This function gets Anactrl oscillators status flags. The flags are returned as the logical
|
|
||||||
* OR value of the enumerators @ref _anactrl_osc_flags. To check for a specific status,
|
|
||||||
* compare the return value with enumerators in the @ref _anactrl_osc_flags.
|
|
||||||
* For example, to check whether the FRO192M clock output is valid:
|
|
||||||
* @code
|
|
||||||
* if (kANACTRL_OutputClkValidFlag & ANACTRL_ANACTRL_GetOscStatusFlags(ANACTRL))
|
|
||||||
* {
|
|
||||||
* ...
|
|
||||||
* }
|
|
||||||
* @endcode
|
|
||||||
*
|
|
||||||
* @param base ANACTRL peripheral base address.
|
|
||||||
* @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags.
|
|
||||||
*/
|
|
||||||
static inline uint32_t ANACTRL_GetOscStatusFlags(ANACTRL_Type *base)
|
|
||||||
{
|
|
||||||
return (base->FRO192M_STATUS & 0xFFU) | ((base->XO32M_STATUS & 0xFFU) << 16U);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get ANACTRL interrupt status flags.
|
|
||||||
*
|
|
||||||
* This function gets Anactrl interrupt status flags. The flags are returned as the logical
|
|
||||||
* OR value of the enumerators @ref _anactrl_interrupt_flags. To check for a specific status,
|
|
||||||
* compare the return value with enumerators in the @ref _anactrl_interrupt_flags.
|
|
||||||
* For example, to check whether the VBAT voltage level is above the threshold:
|
|
||||||
* @code
|
|
||||||
* if (kANACTRL_BodVbatPowerFlag & ANACTRL_ANACTRL_GetInterruptStatusFlags(ANACTRL))
|
|
||||||
* {
|
|
||||||
* ...
|
|
||||||
* }
|
|
||||||
* @endcode
|
|
||||||
*
|
|
||||||
* @param base ANACTRL peripheral base address.
|
|
||||||
* @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags.
|
|
||||||
*/
|
|
||||||
static inline uint32_t ANACTRL_GetInterruptStatusFlags(ANACTRL_Type *base)
|
|
||||||
{
|
|
||||||
return base->BOD_DCDC_INT_STATUS & 0x1FFU;
|
|
||||||
}
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* @}*/
|
|
||||||
|
|
||||||
#endif /* __FSL_ANACTRL_H__ */
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,301 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _FSL_CASPER_H_
|
|
||||||
#define _FSL_CASPER_H_
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*! @file */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
*******************************************************************************/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup casper_driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
/*! @brief CASPER driver version. Version 2.0.2.
|
|
||||||
*
|
|
||||||
* Current version: 2.0.2
|
|
||||||
*
|
|
||||||
* Change log:
|
|
||||||
* - Version 2.0.0
|
|
||||||
* - Initial version
|
|
||||||
* - Version 2.0.1
|
|
||||||
* - Bug fix KPSDK-24531 double_scalar_multiplication() result may be all zeroes for some specific input
|
|
||||||
* - Version 2.0.2
|
|
||||||
* - Bug fix KPSDK-25015 CASPER_MEMCPY hard-fault on LPC55xx when both source and destination buffers are outside of CASPER_RAM
|
|
||||||
*/
|
|
||||||
#define FSL_CASPER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*! @brief CASPER operation
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
typedef enum _casper_operation
|
|
||||||
{
|
|
||||||
kCASPER_OpMul6464NoSum = 0x01, /*! Walking 1 or more of J loop, doing r=a*b using 64x64=128*/
|
|
||||||
kCASPER_OpMul6464Sum =
|
|
||||||
0x02, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but assume inner j loop*/
|
|
||||||
kCASPER_OpMul6464FullSum =
|
|
||||||
0x03, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but sum all of w. */
|
|
||||||
kCASPER_OpMul6464Reduce =
|
|
||||||
0x04, /*! Walking 1 or more of J loop, doing c,r[-1]=r+a*b using 64x64=128, but skip 1st write*/
|
|
||||||
kCASPER_OpAdd64 = 0x08, /*! Walking add with off_AB, and in/out off_RES doing c,r=r+a+c using 64+64=65*/
|
|
||||||
kCASPER_OpSub64 = 0x09, /*! Walking subtract with off_AB, and in/out off_RES doing r=r-a uding 64-64=64, with last
|
|
||||||
borrow implicit if any*/
|
|
||||||
kCASPER_OpDouble64 = 0x0A, /*! Walking add to self with off_RES doing c,r=r+r+c using 64+64=65*/
|
|
||||||
kCASPER_OpXor64 = 0x0B, /*! Walking XOR with off_AB, and in/out off_RES doing r=r^a using 64^64=64*/
|
|
||||||
kCASPER_OpShiftLeft32 =
|
|
||||||
0x10, /*! Walking shift left doing r1,r=(b*D)|r1, where D is 2^amt and is loaded by app (off_CD not used)*/
|
|
||||||
kCASPER_OpShiftRight32 = 0x11, /*! Walking shift right doing r,r1=(b*D)|r1, where D is 2^(32-amt) and is loaded by
|
|
||||||
app (off_CD not used) and off_RES starts at MSW*/
|
|
||||||
kCASPER_OpCopy = 0x14, /*! Copy from ABoff to resoff, 64b at a time*/
|
|
||||||
kCASPER_OpRemask = 0x15, /*! Copy and mask from ABoff to resoff, 64b at a time*/
|
|
||||||
kCASPER_OpCompare = 0x16, /*! Compare two arrays, running all the way to the end*/
|
|
||||||
kCASPER_OpCompareFast = 0x17, /*! Compare two arrays, stopping on 1st !=*/
|
|
||||||
} casper_operation_t;
|
|
||||||
|
|
||||||
#define CASPER_CP 1
|
|
||||||
#define CASPER_CP_CTRL0 (0x0 >> 2)
|
|
||||||
#define CASPER_CP_CTRL1 (0x4 >> 2)
|
|
||||||
#define CASPER_CP_LOADER (0x8 >> 2)
|
|
||||||
#define CASPER_CP_STATUS (0xC >> 2)
|
|
||||||
#define CASPER_CP_INTENSET (0x10 >> 2)
|
|
||||||
#define CASPER_CP_INTENCLR (0x14 >> 2)
|
|
||||||
#define CASPER_CP_INTSTAT (0x18 >> 2)
|
|
||||||
#define CASPER_CP_AREG (0x20 >> 2)
|
|
||||||
#define CASPER_CP_BREG (0x24 >> 2)
|
|
||||||
#define CASPER_CP_CREG (0x28 >> 2)
|
|
||||||
#define CASPER_CP_DREG (0x2C >> 2)
|
|
||||||
#define CASPER_CP_RES0 (0x30 >> 2)
|
|
||||||
#define CASPER_CP_RES1 (0x34 >> 2)
|
|
||||||
#define CASPER_CP_RES2 (0x38 >> 2)
|
|
||||||
#define CASPER_CP_RES3 (0x3C >> 2)
|
|
||||||
#define CASPER_CP_MASK (0x60 >> 2)
|
|
||||||
#define CASPER_CP_REMASK (0x64 >> 2)
|
|
||||||
#define CASPER_CP_LOCK (0x80 >> 2)
|
|
||||||
#define CASPER_CP_ID (0xFFC >> 2)
|
|
||||||
/* mcr (cp, opc1, value, CRn, CRm, opc2) */
|
|
||||||
#define CASPER_Wr32b(value, off) __arm_mcr(CASPER_CP, 0, value, ((off >> 4)), (off), 0)
|
|
||||||
/* mcrr(coproc, opc1, value, CRm) */
|
|
||||||
#define CASPER_Wr64b(value, off) __arm_mcrr(CASPER_CP, 0, value, off)
|
|
||||||
/* mrc(coproc, opc1, CRn, CRm, opc2) */
|
|
||||||
#define CASPER_Rd32b(off) __arm_mrc(CASPER_CP, 0, ((off >> 4)), (off), 0)
|
|
||||||
|
|
||||||
/* The model for this algo is that it can be implemented for a fixed size RSA key */
|
|
||||||
/* for max speed. If this is made into a variable (to allow varying size), then */
|
|
||||||
/* it will be slower by a bit. */
|
|
||||||
/* The file is compiled with N_bitlen passed in as number of bits of the RSA key */
|
|
||||||
/* #define N_bitlen 2048 */
|
|
||||||
#define N_wordlen_max (4096 / 32)
|
|
||||||
|
|
||||||
#define CASPER_ECC_P256 1
|
|
||||||
#define CASPER_ECC_P384 0
|
|
||||||
|
|
||||||
#if CASPER_ECC_P256
|
|
||||||
#define N_bitlen 256
|
|
||||||
#endif /* CASPER_ECC_P256 */
|
|
||||||
|
|
||||||
#if CASPER_ECC_P384
|
|
||||||
#define N_bitlen 384
|
|
||||||
#endif /* CASPER_ECC_P256 */
|
|
||||||
|
|
||||||
#define NUM_LIMBS (N_bitlen / 32)
|
|
||||||
|
|
||||||
enum
|
|
||||||
{
|
|
||||||
kCASPER_RamOffset_Result = 0x0u,
|
|
||||||
kCASPER_RamOffset_Base = (N_wordlen_max + 8u),
|
|
||||||
kCASPER_RamOffset_TempBase = (2u * N_wordlen_max + 16u),
|
|
||||||
kCASPER_RamOffset_Modulus = (kCASPER_RamOffset_TempBase + N_wordlen_max + 4u),
|
|
||||||
kCASPER_RamOffset_M64 = 1022,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*! @} */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup casper_driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enables clock and disables reset for CASPER peripheral.
|
|
||||||
*
|
|
||||||
* Enable clock and disable reset for CASPER.
|
|
||||||
*
|
|
||||||
* @param base CASPER base address
|
|
||||||
*/
|
|
||||||
void CASPER_Init(CASPER_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Disables clock for CASPER peripheral.
|
|
||||||
*
|
|
||||||
* Disable clock and enable reset.
|
|
||||||
*
|
|
||||||
* @param base CASPER base address
|
|
||||||
*/
|
|
||||||
void CASPER_Deinit(CASPER_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
*@}
|
|
||||||
*/ /* end of casper_driver */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* PKHA API
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup casper_driver_pkha
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Performs modular exponentiation - (A^E) mod N.
|
|
||||||
*
|
|
||||||
* This function performs modular exponentiation.
|
|
||||||
*
|
|
||||||
* @param base CASPER base address
|
|
||||||
* @param signature first addend (in little endian format)
|
|
||||||
* @param pubN modulus (in little endian format)
|
|
||||||
* @param wordLen Size of pubN in bytes
|
|
||||||
* @param pubE exponent
|
|
||||||
* @param[out] plaintext Output array to store result of operation (in little endian format)
|
|
||||||
*/
|
|
||||||
void CASPER_ModExp(CASPER_Type *base,
|
|
||||||
const uint8_t *signature,
|
|
||||||
const uint8_t *pubN,
|
|
||||||
size_t wordLen,
|
|
||||||
uint32_t pubE,
|
|
||||||
uint8_t *plaintext);
|
|
||||||
|
|
||||||
void CASPER_ecc_init(void);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Performs ECC secp256r1 point single scalar multiplication
|
|
||||||
*
|
|
||||||
* This function performs ECC secp256r1 point single scalar multiplication
|
|
||||||
* [resX; resY] = scalar * [X; Y]
|
|
||||||
* Coordinates are affine in normal form, little endian.
|
|
||||||
* Scalars are little endian.
|
|
||||||
* All arrays are little endian byte arrays, uint32_t type is used
|
|
||||||
* only to enforce the 32-bit alignment (0-mod-4 address).
|
|
||||||
*
|
|
||||||
* @param base CASPER base address
|
|
||||||
* @param[out] resX Output X affine coordinate in normal form, little endian.
|
|
||||||
* @param[out] resY Output Y affine coordinate in normal form, little endian.
|
|
||||||
* @param X Input X affine coordinate in normal form, little endian.
|
|
||||||
* @param Y Input Y affine coordinate in normal form, little endian.
|
|
||||||
* @param scalar Input scalar integer, in normal form, little endian.
|
|
||||||
*/
|
|
||||||
void CASPER_ECC_SECP256R1_Mul(
|
|
||||||
CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Performs ECC secp256r1 point double scalar multiplication
|
|
||||||
*
|
|
||||||
* This function performs ECC secp256r1 point double scalar multiplication
|
|
||||||
* [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2]
|
|
||||||
* Coordinates are affine in normal form, little endian.
|
|
||||||
* Scalars are little endian.
|
|
||||||
* All arrays are little endian byte arrays, uint32_t type is used
|
|
||||||
* only to enforce the 32-bit alignment (0-mod-4 address).
|
|
||||||
*
|
|
||||||
* @param base CASPER base address
|
|
||||||
* @param[out] resX Output X affine coordinate.
|
|
||||||
* @param[out] resY Output Y affine coordinate.
|
|
||||||
* @param X1 Input X1 affine coordinate.
|
|
||||||
* @param Y1 Input Y1 affine coordinate.
|
|
||||||
* @param scalar1 Input scalar1 integer.
|
|
||||||
* @param X2 Input X2 affine coordinate.
|
|
||||||
* @param Y2 Input Y2 affine coordinate.
|
|
||||||
* @param scalar2 Input scalar2 integer.
|
|
||||||
*/
|
|
||||||
void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base,
|
|
||||||
uint32_t resX[8],
|
|
||||||
uint32_t resY[8],
|
|
||||||
uint32_t X1[8],
|
|
||||||
uint32_t Y1[8],
|
|
||||||
uint32_t scalar1[8],
|
|
||||||
uint32_t X2[8],
|
|
||||||
uint32_t Y2[8],
|
|
||||||
uint32_t scalar2[8]);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Performs ECC secp384r1 point single scalar multiplication
|
|
||||||
*
|
|
||||||
* This function performs ECC secp384r1 point single scalar multiplication
|
|
||||||
* [resX; resY] = scalar * [X; Y]
|
|
||||||
* Coordinates are affine in normal form, little endian.
|
|
||||||
* Scalars are little endian.
|
|
||||||
* All arrays are little endian byte arrays, uint32_t type is used
|
|
||||||
* only to enforce the 32-bit alignment (0-mod-4 address).
|
|
||||||
*
|
|
||||||
* @param base CASPER base address
|
|
||||||
* @param[out] resX Output X affine coordinate in normal form, little endian.
|
|
||||||
* @param[out] resY Output Y affine coordinate in normal form, little endian.
|
|
||||||
* @param X Input X affine coordinate in normal form, little endian.
|
|
||||||
* @param Y Input Y affine coordinate in normal form, little endian.
|
|
||||||
* @param scalar Input scalar integer, in normal form, little endian.
|
|
||||||
*/
|
|
||||||
void CASPER_ECC_SECP384R1_Mul(
|
|
||||||
CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Performs ECC secp384r1 point double scalar multiplication
|
|
||||||
*
|
|
||||||
* This function performs ECC secp384r1 point double scalar multiplication
|
|
||||||
* [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2]
|
|
||||||
* Coordinates are affine in normal form, little endian.
|
|
||||||
* Scalars are little endian.
|
|
||||||
* All arrays are little endian byte arrays, uint32_t type is used
|
|
||||||
* only to enforce the 32-bit alignment (0-mod-4 address).
|
|
||||||
*
|
|
||||||
* @param base CASPER base address
|
|
||||||
* @param[out] resX Output X affine coordinate.
|
|
||||||
* @param[out] resY Output Y affine coordinate.
|
|
||||||
* @param X1 Input X1 affine coordinate.
|
|
||||||
* @param Y1 Input Y1 affine coordinate.
|
|
||||||
* @param scalar1 Input scalar1 integer.
|
|
||||||
* @param X2 Input X2 affine coordinate.
|
|
||||||
* @param Y2 Input Y2 affine coordinate.
|
|
||||||
* @param scalar2 Input scalar2 integer.
|
|
||||||
*/
|
|
||||||
void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base,
|
|
||||||
uint32_t resX[12],
|
|
||||||
uint32_t resY[12],
|
|
||||||
uint32_t X1[12],
|
|
||||||
uint32_t Y1[12],
|
|
||||||
uint32_t scalar1[12],
|
|
||||||
uint32_t X2[12],
|
|
||||||
uint32_t Y2[12],
|
|
||||||
uint32_t scalar2[12]);
|
|
||||||
|
|
||||||
void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2);
|
|
||||||
void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
*@}
|
|
||||||
*/ /* end of casper_driver_pkha */
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* _FSL_CASPER_H_ */
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,55 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "fsl_cmp.h"
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.cmp_1"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Prototypes
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code
|
|
||||||
******************************************************************************/
|
|
||||||
void CMP_Init(cmp_config_t *config)
|
|
||||||
{
|
|
||||||
assert(NULL != config);
|
|
||||||
|
|
||||||
/*enable the clock to the register interface*/
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
CLOCK_EnableClock(kCLOCK_Comp);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
/*Clear reset to peripheral cmp*/
|
|
||||||
#if !(defined(FSL_FEATURE_CMP_HAS_NO_RESET) && FSL_TEATURE_CMP_HAS_NO_RESET)
|
|
||||||
RESET_ClearPeripheralReset(kCMP_RST_SHIFT_RSTn);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*clear COMP bits*/
|
|
||||||
PMC->COMP &= ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK);
|
|
||||||
|
|
||||||
PMC->COMP |= (config->enLowPower << PMC_COMP_LOWPOWER_SHIFT) /*Select if enter low power mode*/
|
|
||||||
| (config->enHysteris << PMC_COMP_HYST_SHIFT) /*select if enable hysteresis*/
|
|
||||||
| config->pmuxInput /*pmux input source select*/
|
|
||||||
| config->nmuxInput; /*nmux input source select */
|
|
||||||
}
|
|
||||||
|
|
||||||
void CMP_Deinit(void)
|
|
||||||
{
|
|
||||||
/*disable the clock to the register interface*/
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
CLOCK_DisableClock(kCLOCK_Comp);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
}
|
|
||||||
|
|
@ -1,293 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __FSL_CMP_H_
|
|
||||||
#define __FSL_CMP_H_
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup cmp_1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* Definitions.
|
|
||||||
*****************************************************************************/
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
/*! @brief Driver version 2.0.0. */
|
|
||||||
#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*! @brief VREF select */
|
|
||||||
enum _cmp_vref_select
|
|
||||||
{
|
|
||||||
KCMP_VREFSelectVDDA = 1U, /*!< Select VDDA as VREF*/
|
|
||||||
KCMP_VREFSelectInternalVREF = 0U, /*!< select internal VREF as VREF*/
|
|
||||||
};
|
|
||||||
|
|
||||||
/*! @brief cmp interrupt type */
|
|
||||||
typedef enum _cmp_interrupt_type
|
|
||||||
{
|
|
||||||
kCMP_EdgeDisable = 0U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< disable edge sensitive */
|
|
||||||
kCMP_EdgeRising = 2U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Edge sensitive, falling edge */
|
|
||||||
kCMP_EdgeFalling = 4U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Edge sensitive, rising edge */
|
|
||||||
kCMP_EdgeRisingFalling = 6U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Edge sensitive, rising and falling edge */
|
|
||||||
|
|
||||||
kCMP_LevelDisable = 1U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< disable level sensitive */
|
|
||||||
kCMP_LevelHigh = 3U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Level sensitive, high level */
|
|
||||||
kCMP_LevelLow = 5U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Level sensitive, low level */
|
|
||||||
kCMP_LevelDisable1 = 7U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< disable level sensitive */
|
|
||||||
} cmp_interrupt_type_t;
|
|
||||||
|
|
||||||
/*! @brief cmp Pmux input source */
|
|
||||||
typedef enum _cmp_pmux_input
|
|
||||||
{
|
|
||||||
kCMP_PInputVREF = 0U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from VREF */
|
|
||||||
kCMP_PInputP0_0 = 1U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P0_0 */
|
|
||||||
kCMP_PInputP0_9 = 2U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P0_9 */
|
|
||||||
kCMP_PInputP0_18 = 3U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P0_18 */
|
|
||||||
kCMP_PInputP1_14 = 4U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P1_14 */
|
|
||||||
kCMP_PInputP2_23 = 5U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P2_23 */
|
|
||||||
} cmp_pmux_input_t;
|
|
||||||
|
|
||||||
/*! @brief cmp Nmux input source */
|
|
||||||
typedef enum _cmp_nmux_input
|
|
||||||
{
|
|
||||||
kCMP_NInputVREF = 0U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from VREF */
|
|
||||||
kCMP_NInputP0_0 = 1U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P0_0 */
|
|
||||||
kCMP_NInputP0_9 = 2U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P0_9 */
|
|
||||||
kCMP_NInputP0_18 = 3U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P0_18 */
|
|
||||||
kCMP_NInputP1_14 = 4U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P1_14 */
|
|
||||||
kCMP_NInputP2_23 = 5U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P2_23 */
|
|
||||||
} cmp_nmux_input_t;
|
|
||||||
|
|
||||||
/*! @brief cmp configurataions */
|
|
||||||
typedef struct _cmp_config
|
|
||||||
{
|
|
||||||
bool enHysteris; /*!< low hysteresis */
|
|
||||||
bool enLowPower; /*!<low power mode*/
|
|
||||||
cmp_nmux_input_t nmuxInput; /*!<Nmux input select*/
|
|
||||||
cmp_pmux_input_t pmuxInput; /*!<Pmux input select*/
|
|
||||||
} cmp_config_t;
|
|
||||||
/*************************************************************************************************
|
|
||||||
* API
|
|
||||||
************************************************************************************************/
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Cmp Initialization and deinitialization
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief CMP intialization.
|
|
||||||
* Note: The cmp initial function not responsible for cmp power, application shall handle it.
|
|
||||||
*
|
|
||||||
* @param config init configurations.
|
|
||||||
*/
|
|
||||||
void CMP_Init(cmp_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief CMP deintialization.
|
|
||||||
* Note: The cmp deinit function not responsible for cmp power, application shall handle it.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void CMP_Deinit(void);
|
|
||||||
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name cmp functionality
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief select input source for pmux.
|
|
||||||
*
|
|
||||||
* @param pmux_select_source reference cmp_pmux_input_t above.
|
|
||||||
*/
|
|
||||||
static inline void CMP_PmuxSelect(cmp_pmux_input_t pmux_select_source)
|
|
||||||
{
|
|
||||||
PMC->COMP &= ~PMC_COMP_PMUX_MASK;
|
|
||||||
PMC->COMP |= pmux_select_source;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief select input source for nmux.
|
|
||||||
*
|
|
||||||
* @param nmux_select_source reference cmp_nmux_input_t above.
|
|
||||||
*/
|
|
||||||
static inline void CMP_NmuxSelect(cmp_nmux_input_t nmux_select_source)
|
|
||||||
{
|
|
||||||
PMC->COMP &= ~PMC_COMP_NMUX_MASK;
|
|
||||||
PMC->COMP |= nmux_select_source;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief switch cmp work mode.
|
|
||||||
*
|
|
||||||
* @param enable true is enter low power mode, false is enter fast mode
|
|
||||||
*/
|
|
||||||
static inline void CMP_EnableLowePowerMode(bool enable)
|
|
||||||
{
|
|
||||||
if (enable)
|
|
||||||
{
|
|
||||||
PMC->COMP |= PMC_COMP_LOWPOWER_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
PMC->COMP &= ~PMC_COMP_LOWPOWER_MASK;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Control reference voltage step, per steps of (VREFINPUT/31).
|
|
||||||
*
|
|
||||||
* @param step reference voltage step, per steps of (VREFINPUT/31).
|
|
||||||
*/
|
|
||||||
static inline void CMP_SetRefStep(uint32_t step)
|
|
||||||
{
|
|
||||||
PMC->COMP |= step << PMC_COMP_VREF_SHIFT;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief cmp enable hysteresis.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
static inline void CMP_EnableHysteresis(bool enable)
|
|
||||||
{
|
|
||||||
if (enable)
|
|
||||||
{
|
|
||||||
PMC->COMP |= PMC_COMP_HYST_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
PMC->COMP &= ~PMC_COMP_HYST_MASK;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief VREF select between internal VREF and VDDA (for the resistive ladder).
|
|
||||||
*
|
|
||||||
* @param select 1 is Select VDDA, 0 is Select internal VREF.
|
|
||||||
*/
|
|
||||||
static inline void CMP_VREFSelect(uint32_t select)
|
|
||||||
{
|
|
||||||
if (select)
|
|
||||||
{
|
|
||||||
PMC->COMP |= PMC_COMP_VREFINPUT_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
PMC->COMP &= ~PMC_COMP_VREFINPUT_MASK;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief comparator analog output.
|
|
||||||
*
|
|
||||||
* @return 1 indicates p is greater than n, 0 indicates n is greater than p.
|
|
||||||
*/
|
|
||||||
static inline uint32_t CMP_GetOutput(void)
|
|
||||||
{
|
|
||||||
return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK) ? 1 : 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name cmp interrupt
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief cmp enable interrupt.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
static inline void CMP_EnableInterrupt(void)
|
|
||||||
{
|
|
||||||
SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief cmp disable interrupt.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
static inline void CMP_DisableInterrupt(void)
|
|
||||||
{
|
|
||||||
SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Select which Analog comparator output (filtered or un-filtered) is used for interrupt detection.
|
|
||||||
*
|
|
||||||
* @param enable true is Select Analog Comparator raw output (unfiltered) as input for interrupt detection.
|
|
||||||
* false is Select Analog Comparator filtered output as input for interrupt detection.
|
|
||||||
*/
|
|
||||||
static inline void CMP_InterruptSourceSelect(bool enable)
|
|
||||||
{
|
|
||||||
if (enable)
|
|
||||||
{
|
|
||||||
SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief cmp get status.
|
|
||||||
*
|
|
||||||
* @return true is interrupt pending, false is no interrupt pending.
|
|
||||||
*/
|
|
||||||
static inline bool CMP_GetStatus(void)
|
|
||||||
{
|
|
||||||
return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK) ? true : false;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief cmp clear interrupt status.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
static inline void CMP_ClearStatus(void)
|
|
||||||
{
|
|
||||||
SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Comparator interrupt type select.
|
|
||||||
*
|
|
||||||
* @param type reference cmp_interrupt_type_t.
|
|
||||||
*/
|
|
||||||
static inline void CMP_InterruptTypeSelect(cmp_interrupt_type_t cmp_interrupt_type)
|
|
||||||
{
|
|
||||||
SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_CTRL_MASK;
|
|
||||||
SYSCON->COMP_INT_CTRL |= cmp_interrupt_type;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief cmp get interrupt status.
|
|
||||||
*
|
|
||||||
* @return true is interrupt pending, false is no interrupt pending.
|
|
||||||
*/
|
|
||||||
static inline bool CMP_GetInterruptStatus(void)
|
|
||||||
{
|
|
||||||
return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) ? true : false;
|
|
||||||
}
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*! @} */
|
|
||||||
#endif /* __FSL_CMP_H_ */
|
|
||||||
|
|
@ -1,147 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
#define SDK_MEM_MAGIC_NUMBER 12345U
|
|
||||||
|
|
||||||
typedef struct _mem_align_control_block
|
|
||||||
{
|
|
||||||
uint16_t identifier; /*!< Identifier for the memory control block. */
|
|
||||||
uint16_t offset; /*!< offset from aligned address to real address */
|
|
||||||
} mem_align_cb_t;
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.common"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef __GIC_PRIO_BITS
|
|
||||||
#if defined(ENABLE_RAM_VECTOR_TABLE)
|
|
||||||
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
|
|
||||||
{
|
|
||||||
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
|
|
||||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
|
||||||
extern uint32_t Image$$VECTOR_ROM$$Base[];
|
|
||||||
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
|
||||||
extern uint32_t Image$$RW_m_data$$Base[];
|
|
||||||
|
|
||||||
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
|
|
||||||
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
|
||||||
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
|
|
||||||
#elif defined(__ICCARM__)
|
|
||||||
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
|
|
||||||
extern uint32_t __VECTOR_TABLE[];
|
|
||||||
extern uint32_t __VECTOR_RAM[];
|
|
||||||
#elif defined(__GNUC__)
|
|
||||||
extern uint32_t __VECTOR_TABLE[];
|
|
||||||
extern uint32_t __VECTOR_RAM[];
|
|
||||||
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
|
|
||||||
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
|
|
||||||
#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
|
|
||||||
uint32_t n;
|
|
||||||
uint32_t ret;
|
|
||||||
uint32_t irqMaskValue;
|
|
||||||
|
|
||||||
irqMaskValue = DisableGlobalIRQ();
|
|
||||||
if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
|
|
||||||
{
|
|
||||||
/* Copy the vector table from ROM to RAM */
|
|
||||||
for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
|
|
||||||
{
|
|
||||||
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
|
|
||||||
}
|
|
||||||
/* Point the VTOR to the position of vector table */
|
|
||||||
SCB->VTOR = (uint32_t)__VECTOR_RAM;
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = __VECTOR_RAM[irq + 16];
|
|
||||||
/* make sure the __VECTOR_RAM is noncachable */
|
|
||||||
__VECTOR_RAM[irq + 16] = irqHandler;
|
|
||||||
|
|
||||||
EnableGlobalIRQ(irqMaskValue);
|
|
||||||
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
#endif /* ENABLE_RAM_VECTOR_TABLE. */
|
|
||||||
#endif /* __GIC_PRIO_BITS. */
|
|
||||||
|
|
||||||
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
|
||||||
#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
|
|
||||||
|
|
||||||
void EnableDeepSleepIRQ(IRQn_Type interrupt)
|
|
||||||
{
|
|
||||||
uint32_t intNumber = (uint32_t)interrupt;
|
|
||||||
|
|
||||||
uint32_t index = 0;
|
|
||||||
|
|
||||||
while (intNumber >= 32u)
|
|
||||||
{
|
|
||||||
index++;
|
|
||||||
intNumber -= 32u;
|
|
||||||
}
|
|
||||||
|
|
||||||
SYSCON->STARTERSET[index] = 1u << intNumber;
|
|
||||||
EnableIRQ(interrupt); /* also enable interrupt at NVIC */
|
|
||||||
}
|
|
||||||
|
|
||||||
void DisableDeepSleepIRQ(IRQn_Type interrupt)
|
|
||||||
{
|
|
||||||
uint32_t intNumber = (uint32_t)interrupt;
|
|
||||||
|
|
||||||
DisableIRQ(interrupt); /* also disable interrupt at NVIC */
|
|
||||||
uint32_t index = 0;
|
|
||||||
|
|
||||||
while (intNumber >= 32u)
|
|
||||||
{
|
|
||||||
index++;
|
|
||||||
intNumber -= 32u;
|
|
||||||
}
|
|
||||||
|
|
||||||
SYSCON->STARTERCLR[index] = 1u << intNumber;
|
|
||||||
}
|
|
||||||
#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
|
|
||||||
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
|
||||||
|
|
||||||
void *SDK_Malloc(size_t size, size_t alignbytes)
|
|
||||||
{
|
|
||||||
mem_align_cb_t *p_cb = NULL;
|
|
||||||
uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);
|
|
||||||
void *p_align_addr, *p_addr = malloc(alignedsize);
|
|
||||||
|
|
||||||
if (!p_addr)
|
|
||||||
{
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes);
|
|
||||||
|
|
||||||
p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4);
|
|
||||||
p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
|
|
||||||
p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr;
|
|
||||||
|
|
||||||
return (void *)p_align_addr;
|
|
||||||
}
|
|
||||||
|
|
||||||
void SDK_Free(void *ptr)
|
|
||||||
{
|
|
||||||
mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4);
|
|
||||||
|
|
||||||
if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
|
|
||||||
{
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
free((void *)((uint32_t)ptr - p_cb->offset));
|
|
||||||
}
|
|
||||||
|
|
@ -1,585 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _FSL_COMMON_H_
|
|
||||||
#define _FSL_COMMON_H_
|
|
||||||
|
|
||||||
#include <assert.h>
|
|
||||||
#include <stdbool.h>
|
|
||||||
#include <stdint.h>
|
|
||||||
#include <string.h>
|
|
||||||
#include <stdlib.h>
|
|
||||||
|
|
||||||
#if defined(__ICCARM__)
|
|
||||||
#include <stddef.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include "fsl_device_registers.h"
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup ksdk_common
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*! @brief Construct a status code value from a group and code number. */
|
|
||||||
#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
|
|
||||||
|
|
||||||
/*! @brief Construct the version number for drivers. */
|
|
||||||
#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
|
|
||||||
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
/*! @brief common driver version 2.0.1. */
|
|
||||||
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/* Debug console type definition. */
|
|
||||||
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
|
|
||||||
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */
|
|
||||||
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */
|
|
||||||
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */
|
|
||||||
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */
|
|
||||||
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */
|
|
||||||
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */
|
|
||||||
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */
|
|
||||||
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */
|
|
||||||
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */
|
|
||||||
|
|
||||||
/*! @brief Status group numbers. */
|
|
||||||
enum _status_groups
|
|
||||||
{
|
|
||||||
kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
|
|
||||||
kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
|
|
||||||
kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
|
|
||||||
kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
|
|
||||||
kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
|
|
||||||
kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
|
|
||||||
kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
|
|
||||||
kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
|
|
||||||
kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
|
|
||||||
kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
|
|
||||||
kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
|
|
||||||
kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
|
|
||||||
kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
|
|
||||||
kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
|
|
||||||
kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
|
|
||||||
kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
|
|
||||||
kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
|
|
||||||
kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
|
|
||||||
kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
|
|
||||||
kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
|
|
||||||
kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
|
|
||||||
kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
|
|
||||||
kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
|
|
||||||
kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
|
|
||||||
kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
|
|
||||||
kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
|
|
||||||
kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
|
|
||||||
kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
|
|
||||||
kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */
|
|
||||||
kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
|
|
||||||
kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
|
|
||||||
kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
|
|
||||||
kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
|
|
||||||
kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
|
|
||||||
kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
|
|
||||||
kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
|
|
||||||
kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
|
|
||||||
kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
|
|
||||||
kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
|
|
||||||
kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
|
|
||||||
kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
|
|
||||||
kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
|
|
||||||
kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
|
|
||||||
kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
|
|
||||||
kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
|
|
||||||
kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
|
|
||||||
kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
|
|
||||||
kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
|
|
||||||
kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
|
|
||||||
kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
|
|
||||||
kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
|
|
||||||
kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
|
|
||||||
kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
|
|
||||||
kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
|
|
||||||
kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/
|
|
||||||
kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/
|
|
||||||
kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
|
|
||||||
kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
|
|
||||||
kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
|
|
||||||
kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */
|
|
||||||
kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
|
|
||||||
kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
|
|
||||||
kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
|
|
||||||
kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
|
|
||||||
kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */
|
|
||||||
kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */
|
|
||||||
kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */
|
|
||||||
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
|
|
||||||
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
|
|
||||||
kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
|
|
||||||
kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
|
|
||||||
kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */
|
|
||||||
|
|
||||||
kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */
|
|
||||||
kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */
|
|
||||||
kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */
|
|
||||||
kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */
|
|
||||||
kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */
|
|
||||||
kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */
|
|
||||||
kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */
|
|
||||||
kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */
|
|
||||||
kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */
|
|
||||||
kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */
|
|
||||||
kStatusGroup_LED = 137, /*!< Group number for LED status codes. */
|
|
||||||
kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */
|
|
||||||
kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */
|
|
||||||
kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */
|
|
||||||
kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */
|
|
||||||
kStatusGroup_LIST = 142, /*!< Group number for List status codes. */
|
|
||||||
kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */
|
|
||||||
kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */
|
|
||||||
kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*! @brief Generic status return codes. */
|
|
||||||
enum _generic_status
|
|
||||||
{
|
|
||||||
kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
|
|
||||||
kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
|
|
||||||
kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
|
|
||||||
kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
|
|
||||||
kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
|
|
||||||
kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
|
|
||||||
kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
|
|
||||||
};
|
|
||||||
|
|
||||||
/*! @brief Type used for all status and error return values. */
|
|
||||||
typedef int32_t status_t;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
|
|
||||||
* defined in previous of this file.
|
|
||||||
*/
|
|
||||||
#include "fsl_clock.h"
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
|
|
||||||
*/
|
|
||||||
#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
|
|
||||||
(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
|
|
||||||
#include "fsl_reset.h"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Macro guard for whether to use default weak IRQ implementation in drivers
|
|
||||||
*/
|
|
||||||
#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
|
|
||||||
#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*! @name Min/max macros */
|
|
||||||
/* @{ */
|
|
||||||
#if !defined(MIN)
|
|
||||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(MAX)
|
|
||||||
#define MAX(a, b) ((a) > (b) ? (a) : (b))
|
|
||||||
#endif
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*! @brief Computes the number of elements in an array. */
|
|
||||||
#if !defined(ARRAY_SIZE)
|
|
||||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*! @name UINT16_MAX/UINT32_MAX value */
|
|
||||||
/* @{ */
|
|
||||||
#if !defined(UINT16_MAX)
|
|
||||||
#define UINT16_MAX ((uint16_t)-1)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(UINT32_MAX)
|
|
||||||
#define UINT32_MAX ((uint32_t)-1)
|
|
||||||
#endif
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*! @name Timer utilities */
|
|
||||||
/* @{ */
|
|
||||||
/*! Macro to convert a microsecond period to raw count value */
|
|
||||||
#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
|
|
||||||
/*! Macro to convert a raw count value to microsecond */
|
|
||||||
#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
|
|
||||||
|
|
||||||
/*! Macro to convert a millisecond period to raw count value */
|
|
||||||
#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
|
|
||||||
/*! Macro to convert a raw count value to millisecond */
|
|
||||||
#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*! @name Alignment variable definition macros */
|
|
||||||
/* @{ */
|
|
||||||
#if (defined(__ICCARM__))
|
|
||||||
/**
|
|
||||||
* Workaround to disable MISRA C message suppress warnings for IAR compiler.
|
|
||||||
* http://supp.iar.com/Support/?note=24725
|
|
||||||
*/
|
|
||||||
_Pragma("diag_suppress=Pm120")
|
|
||||||
#define SDK_PRAGMA(x) _Pragma(#x)
|
|
||||||
_Pragma("diag_error=Pm120")
|
|
||||||
/*! Macro to define a variable with alignbytes alignment */
|
|
||||||
#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
|
||||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
|
||||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
|
||||||
#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
|
|
||||||
#endif
|
|
||||||
/*! Macro to define a variable with L2 cache line size alignment */
|
|
||||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
|
||||||
#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
|
|
||||||
#endif
|
|
||||||
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
|
||||||
/*! Macro to define a variable with alignbytes alignment */
|
|
||||||
#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
|
|
||||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
|
||||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
|
||||||
#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var
|
|
||||||
#endif
|
|
||||||
/*! Macro to define a variable with L2 cache line size alignment */
|
|
||||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
|
||||||
#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var
|
|
||||||
#endif
|
|
||||||
#elif defined(__GNUC__)
|
|
||||||
/*! Macro to define a variable with alignbytes alignment */
|
|
||||||
#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
|
||||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
|
||||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
|
||||||
#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
|
|
||||||
#endif
|
|
||||||
/*! Macro to define a variable with L2 cache line size alignment */
|
|
||||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
|
||||||
#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
|
|
||||||
#endif
|
|
||||||
#else
|
|
||||||
#error Toolchain not supported
|
|
||||||
#define SDK_ALIGN(var, alignbytes) var
|
|
||||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
|
||||||
#define SDK_L1DCACHE_ALIGN(var) var
|
|
||||||
#endif
|
|
||||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
|
||||||
#define SDK_L2CACHE_ALIGN(var) var
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*! Macro to change a value to a given size aligned value */
|
|
||||||
#define SDK_SIZEALIGN(var, alignbytes) \
|
|
||||||
((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*! @name Non-cacheable region definition macros */
|
|
||||||
/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
|
|
||||||
* "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
|
|
||||||
* please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
|
|
||||||
* will be initialized to zero in system startup.
|
|
||||||
*/
|
|
||||||
/* @{ */
|
|
||||||
#if (defined(__ICCARM__))
|
|
||||||
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
|
|
||||||
#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
|
|
||||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
|
|
||||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
|
|
||||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
|
|
||||||
#else
|
|
||||||
#define AT_NONCACHEABLE_SECTION(var) var
|
|
||||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
|
||||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
|
||||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
|
||||||
#endif
|
|
||||||
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
|
||||||
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
|
|
||||||
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
|
|
||||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
|
||||||
__attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
|
|
||||||
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
|
|
||||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
|
|
||||||
__attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
|
|
||||||
#else
|
|
||||||
#define AT_NONCACHEABLE_SECTION(var) var
|
|
||||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
|
|
||||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
|
||||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var
|
|
||||||
#endif
|
|
||||||
#elif(defined(__GNUC__))
|
|
||||||
/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
|
|
||||||
* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
|
|
||||||
*/
|
|
||||||
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
|
|
||||||
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
|
|
||||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
|
|
||||||
__attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
|
|
||||||
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
|
|
||||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
|
||||||
__attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
|
|
||||||
#else
|
|
||||||
#define AT_NONCACHEABLE_SECTION(var) var
|
|
||||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
|
||||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
|
||||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
|
||||||
#endif
|
|
||||||
#else
|
|
||||||
#error Toolchain not supported.
|
|
||||||
#define AT_NONCACHEABLE_SECTION(var) var
|
|
||||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
|
|
||||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
|
||||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
|
|
||||||
#endif
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*! @name Time sensitive region */
|
|
||||||
/* @{ */
|
|
||||||
#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
|
|
||||||
#if (defined(__ICCARM__))
|
|
||||||
#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
|
|
||||||
#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
|
|
||||||
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
|
||||||
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
|
|
||||||
#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
|
|
||||||
#elif(defined(__GNUC__))
|
|
||||||
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
|
|
||||||
#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
|
|
||||||
#else
|
|
||||||
#error Toolchain not supported.
|
|
||||||
#endif /* defined(__ICCARM__) */
|
|
||||||
#else
|
|
||||||
#if (defined(__ICCARM__))
|
|
||||||
#define AT_QUICKACCESS_SECTION_CODE(func) func
|
|
||||||
#define AT_QUICKACCESS_SECTION_DATA(func) func
|
|
||||||
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
|
||||||
#define AT_QUICKACCESS_SECTION_CODE(func) func
|
|
||||||
#define AT_QUICKACCESS_SECTION_DATA(func) func
|
|
||||||
#elif(defined(__GNUC__))
|
|
||||||
#define AT_QUICKACCESS_SECTION_CODE(func) func
|
|
||||||
#define AT_QUICKACCESS_SECTION_DATA(func) func
|
|
||||||
#else
|
|
||||||
#error Toolchain not supported.
|
|
||||||
#endif
|
|
||||||
#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*! @name Ram Function */
|
|
||||||
#if (defined(__ICCARM__))
|
|
||||||
#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
|
|
||||||
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
|
||||||
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
|
|
||||||
#elif(defined(__GNUC__))
|
|
||||||
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
|
|
||||||
#else
|
|
||||||
#error Toolchain not supported.
|
|
||||||
#endif /* defined(__ICCARM__) */
|
|
||||||
/* @} */
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C"
|
|
||||||
{
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enable specific interrupt.
|
|
||||||
*
|
|
||||||
* Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
|
||||||
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
|
||||||
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
|
||||||
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
|
||||||
* to NVIC first then routed to core.
|
|
||||||
*
|
|
||||||
* This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
|
||||||
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
|
||||||
*
|
|
||||||
* @param interrupt The IRQ number.
|
|
||||||
* @retval kStatus_Success Interrupt enabled successfully
|
|
||||||
* @retval kStatus_Fail Failed to enable the interrupt
|
|
||||||
*/
|
|
||||||
static inline status_t EnableIRQ(IRQn_Type interrupt)
|
|
||||||
{
|
|
||||||
if (NotAvail_IRQn == interrupt)
|
|
||||||
{
|
|
||||||
return kStatus_Fail;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
|
||||||
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
|
||||||
{
|
|
||||||
return kStatus_Fail;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(__GIC_PRIO_BITS)
|
|
||||||
GIC_EnableIRQ(interrupt);
|
|
||||||
#else
|
|
||||||
NVIC_EnableIRQ(interrupt);
|
|
||||||
#endif
|
|
||||||
return kStatus_Success;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Disable specific interrupt.
|
|
||||||
*
|
|
||||||
* Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
|
||||||
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
|
||||||
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
|
||||||
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
|
||||||
* to NVIC first then routed to core.
|
|
||||||
*
|
|
||||||
* This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
|
||||||
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
|
||||||
*
|
|
||||||
* @param interrupt The IRQ number.
|
|
||||||
* @retval kStatus_Success Interrupt disabled successfully
|
|
||||||
* @retval kStatus_Fail Failed to disable the interrupt
|
|
||||||
*/
|
|
||||||
static inline status_t DisableIRQ(IRQn_Type interrupt)
|
|
||||||
{
|
|
||||||
if (NotAvail_IRQn == interrupt)
|
|
||||||
{
|
|
||||||
return kStatus_Fail;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
|
||||||
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
|
||||||
{
|
|
||||||
return kStatus_Fail;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(__GIC_PRIO_BITS)
|
|
||||||
GIC_DisableIRQ(interrupt);
|
|
||||||
#else
|
|
||||||
NVIC_DisableIRQ(interrupt);
|
|
||||||
#endif
|
|
||||||
return kStatus_Success;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Disable the global IRQ
|
|
||||||
*
|
|
||||||
* Disable the global interrupt and return the current primask register. User is required to provided the primask
|
|
||||||
* register for the EnableGlobalIRQ().
|
|
||||||
*
|
|
||||||
* @return Current primask value.
|
|
||||||
*/
|
|
||||||
static inline uint32_t DisableGlobalIRQ(void)
|
|
||||||
{
|
|
||||||
#if defined(CPSR_I_Msk)
|
|
||||||
uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
|
|
||||||
|
|
||||||
__disable_irq();
|
|
||||||
|
|
||||||
return cpsr;
|
|
||||||
#else
|
|
||||||
uint32_t regPrimask = __get_PRIMASK();
|
|
||||||
|
|
||||||
__disable_irq();
|
|
||||||
|
|
||||||
return regPrimask;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enable the global IRQ
|
|
||||||
*
|
|
||||||
* Set the primask register with the provided primask value but not just enable the primask. The idea is for the
|
|
||||||
* convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
|
|
||||||
* use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
|
|
||||||
*
|
|
||||||
* @param primask value of primask register to be restored. The primask value is supposed to be provided by the
|
|
||||||
* DisableGlobalIRQ().
|
|
||||||
*/
|
|
||||||
static inline void EnableGlobalIRQ(uint32_t primask)
|
|
||||||
{
|
|
||||||
#if defined(CPSR_I_Msk)
|
|
||||||
__set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
|
|
||||||
#else
|
|
||||||
__set_PRIMASK(primask);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(ENABLE_RAM_VECTOR_TABLE)
|
|
||||||
/*!
|
|
||||||
* @brief install IRQ handler
|
|
||||||
*
|
|
||||||
* @param irq IRQ number
|
|
||||||
* @param irqHandler IRQ handler address
|
|
||||||
* @return The old IRQ handler address
|
|
||||||
*/
|
|
||||||
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
|
||||||
#endif /* ENABLE_RAM_VECTOR_TABLE. */
|
|
||||||
|
|
||||||
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
|
||||||
/*!
|
|
||||||
* @brief Enable specific interrupt for wake-up from deep-sleep mode.
|
|
||||||
*
|
|
||||||
* Enable the interrupt for wake-up from deep sleep mode.
|
|
||||||
* Some interrupts are typically used in sleep mode only and will not occur during
|
|
||||||
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
|
||||||
* those clocks (significantly increasing power consumption in the reduced power mode),
|
|
||||||
* making these wake-ups possible.
|
|
||||||
*
|
|
||||||
* @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
|
|
||||||
*
|
|
||||||
* @param interrupt The IRQ number.
|
|
||||||
*/
|
|
||||||
void EnableDeepSleepIRQ(IRQn_Type interrupt);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Disable specific interrupt for wake-up from deep-sleep mode.
|
|
||||||
*
|
|
||||||
* Disable the interrupt for wake-up from deep sleep mode.
|
|
||||||
* Some interrupts are typically used in sleep mode only and will not occur during
|
|
||||||
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
|
||||||
* those clocks (significantly increasing power consumption in the reduced power mode),
|
|
||||||
* making these wake-ups possible.
|
|
||||||
*
|
|
||||||
* @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
|
|
||||||
*
|
|
||||||
* @param interrupt The IRQ number.
|
|
||||||
*/
|
|
||||||
void DisableDeepSleepIRQ(IRQn_Type interrupt);
|
|
||||||
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Allocate memory with given alignment and aligned size.
|
|
||||||
*
|
|
||||||
* This is provided to support the dynamically allocated memory
|
|
||||||
* used in cache-able region.
|
|
||||||
* @param size The length required to malloc.
|
|
||||||
* @param alignbytes The alignment size.
|
|
||||||
* @retval The allocated memory.
|
|
||||||
*/
|
|
||||||
void *SDK_Malloc(size_t size, size_t alignbytes);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Free memory.
|
|
||||||
*
|
|
||||||
* @param ptr The memory to be release.
|
|
||||||
*/
|
|
||||||
void SDK_Free(void *ptr);
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*! @} */
|
|
||||||
|
|
||||||
#endif /* _FSL_COMMON_H_ */
|
|
||||||
|
|
@ -1,172 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
#include "fsl_crc.h"
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.lpc_crc"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT
|
|
||||||
/* @brief Default user configuration structure for CRC-CCITT */
|
|
||||||
#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT
|
|
||||||
/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */
|
|
||||||
#define CRC_DRIVER_DEFAULT_REVERSE_IN false
|
|
||||||
/*< Default is no bit reverse */
|
|
||||||
#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false
|
|
||||||
/*< Default is without complement of written data */
|
|
||||||
#define CRC_DRIVER_DEFAULT_REVERSE_OUT false
|
|
||||||
/*< Default is no bit reverse */
|
|
||||||
#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false
|
|
||||||
/*< Default is without complement of CRC data register read data */
|
|
||||||
#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU
|
|
||||||
/*< Default initial checksum */
|
|
||||||
#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Enables and configures the CRC peripheral module.
|
|
||||||
*
|
|
||||||
* This functions enables the CRC peripheral clock in the LPC SYSCON block.
|
|
||||||
* It also configures the CRC engine and starts checksum computation by writing the seed.
|
|
||||||
*
|
|
||||||
* param base CRC peripheral address.
|
|
||||||
* param config CRC module configuration structure.
|
|
||||||
*/
|
|
||||||
void CRC_Init(CRC_Type *base, const crc_config_t *config)
|
|
||||||
{
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* enable clock to CRC */
|
|
||||||
CLOCK_EnableClock(kCLOCK_Crc);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_FEATURE_CRC_HAS_NO_RESET) && FSL_FEATURE_CRC_HAS_NO_RESET)
|
|
||||||
RESET_PeripheralReset(kCRC_RST_SHIFT_RSTn);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* configure CRC module and write the seed */
|
|
||||||
base->MODE = 0 | CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) |
|
|
||||||
CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) |
|
|
||||||
CRC_MODE_CMPL_SUM(config->complementOut);
|
|
||||||
base->SEED = config->seed;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Loads default values to CRC protocol configuration structure.
|
|
||||||
*
|
|
||||||
* Loads default values to CRC protocol configuration structure. The default values are:
|
|
||||||
* code
|
|
||||||
* config->polynomial = kCRC_Polynomial_CRC_CCITT;
|
|
||||||
* config->reverseIn = false;
|
|
||||||
* config->complementIn = false;
|
|
||||||
* config->reverseOut = false;
|
|
||||||
* config->complementOut = false;
|
|
||||||
* config->seed = 0xFFFFU;
|
|
||||||
* endcode
|
|
||||||
*
|
|
||||||
* param config CRC protocol configuration structure
|
|
||||||
*/
|
|
||||||
void CRC_GetDefaultConfig(crc_config_t *config)
|
|
||||||
{
|
|
||||||
/* Initializes the configure structure to zero. */
|
|
||||||
memset(config, 0, sizeof(*config));
|
|
||||||
|
|
||||||
static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN,
|
|
||||||
CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT,
|
|
||||||
CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED};
|
|
||||||
|
|
||||||
*config = default_config;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief resets CRC peripheral module.
|
|
||||||
*
|
|
||||||
* param base CRC peripheral address.
|
|
||||||
*/
|
|
||||||
void CRC_Reset(CRC_Type *base)
|
|
||||||
{
|
|
||||||
crc_config_t config;
|
|
||||||
CRC_GetDefaultConfig(&config);
|
|
||||||
CRC_Init(base, &config);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure.
|
|
||||||
*
|
|
||||||
* The values, including seed, can be used to resume CRC calculation later.
|
|
||||||
|
|
||||||
* param base CRC peripheral address.
|
|
||||||
* param config CRC protocol configuration structure
|
|
||||||
*/
|
|
||||||
void CRC_GetConfig(CRC_Type *base, crc_config_t *config)
|
|
||||||
{
|
|
||||||
/* extract CRC mode settings */
|
|
||||||
uint32_t mode = base->MODE;
|
|
||||||
config->polynomial = (crc_polynomial_t)((mode & CRC_MODE_CRC_POLY_MASK) >> CRC_MODE_CRC_POLY_SHIFT);
|
|
||||||
config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK);
|
|
||||||
config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK);
|
|
||||||
config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK);
|
|
||||||
config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK);
|
|
||||||
|
|
||||||
/* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */
|
|
||||||
base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT));
|
|
||||||
|
|
||||||
/* now we can obtain intermediate raw CRC sum value */
|
|
||||||
config->seed = base->SUM;
|
|
||||||
|
|
||||||
/* restore original CRC sum bit reverse and 1's complement setting */
|
|
||||||
base->MODE = mode;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Writes data to the CRC module.
|
|
||||||
*
|
|
||||||
* Writes input data buffer bytes to CRC data register.
|
|
||||||
*
|
|
||||||
* param base CRC peripheral address.
|
|
||||||
* param data Input data stream, MSByte in data[0].
|
|
||||||
* param dataSize Size of the input data buffer in bytes.
|
|
||||||
*/
|
|
||||||
void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
|
|
||||||
{
|
|
||||||
const uint32_t *data32;
|
|
||||||
|
|
||||||
/* 8-bit reads and writes till source address is aligned 4 bytes */
|
|
||||||
while ((dataSize) && ((uint32_t)data & 3U))
|
|
||||||
{
|
|
||||||
*((__O uint8_t *)&(base->WR_DATA)) = *data;
|
|
||||||
data++;
|
|
||||||
dataSize--;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* use 32-bit reads and writes as long as possible */
|
|
||||||
data32 = (const uint32_t *)data;
|
|
||||||
while (dataSize >= sizeof(uint32_t))
|
|
||||||
{
|
|
||||||
*((__O uint32_t *)&(base->WR_DATA)) = *data32;
|
|
||||||
data32++;
|
|
||||||
dataSize -= sizeof(uint32_t);
|
|
||||||
}
|
|
||||||
|
|
||||||
data = (const uint8_t *)data32;
|
|
||||||
|
|
||||||
/* 8-bit reads and writes till end of data buffer */
|
|
||||||
while (dataSize)
|
|
||||||
{
|
|
||||||
*((__O uint8_t *)&(base->WR_DATA)) = *data;
|
|
||||||
data++;
|
|
||||||
dataSize--;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,181 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _FSL_CRC_H_
|
|
||||||
#define _FSL_CRC_H_
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup crc
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @file */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
/*! @brief CRC driver version. Version 2.0.1.
|
|
||||||
*
|
|
||||||
* Current version: 2.0.1
|
|
||||||
*
|
|
||||||
* Change log:
|
|
||||||
* - Version 2.0.0
|
|
||||||
* - initial version
|
|
||||||
* - Version 2.0.1
|
|
||||||
* - add explicit type cast when writing to WR_DATA
|
|
||||||
*/
|
|
||||||
#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
#ifndef CRC_DRIVER_CUSTOM_DEFAULTS
|
|
||||||
/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */
|
|
||||||
#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*! @brief CRC polynomials to use. */
|
|
||||||
typedef enum _crc_polynomial
|
|
||||||
{
|
|
||||||
kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */
|
|
||||||
kCRC_Polynomial_CRC_16 = 1U, /*!< x^16+x^15+x^2+1 */
|
|
||||||
kCRC_Polynomial_CRC_32 = 2U /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */
|
|
||||||
} crc_polynomial_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief CRC protocol configuration.
|
|
||||||
*
|
|
||||||
* This structure holds the configuration for the CRC protocol.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
typedef struct _crc_config
|
|
||||||
{
|
|
||||||
crc_polynomial_t polynomial; /*!< CRC polynomial. */
|
|
||||||
bool reverseIn; /*!< Reverse bits on input. */
|
|
||||||
bool complementIn; /*!< Perform 1's complement on input. */
|
|
||||||
bool reverseOut; /*!< Reverse bits on output. */
|
|
||||||
bool complementOut; /*!< Perform 1's complement on output. */
|
|
||||||
uint32_t seed; /*!< Starting checksum value. */
|
|
||||||
} crc_config_t;
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enables and configures the CRC peripheral module.
|
|
||||||
*
|
|
||||||
* This functions enables the CRC peripheral clock in the LPC SYSCON block.
|
|
||||||
* It also configures the CRC engine and starts checksum computation by writing the seed.
|
|
||||||
*
|
|
||||||
* @param base CRC peripheral address.
|
|
||||||
* @param config CRC module configuration structure.
|
|
||||||
*/
|
|
||||||
void CRC_Init(CRC_Type *base, const crc_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Disables the CRC peripheral module.
|
|
||||||
*
|
|
||||||
* This functions disables the CRC peripheral clock in the LPC SYSCON block.
|
|
||||||
*
|
|
||||||
* @param base CRC peripheral address.
|
|
||||||
*/
|
|
||||||
static inline void CRC_Deinit(CRC_Type *base)
|
|
||||||
{
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* disable clock to CRC */
|
|
||||||
CLOCK_DisableClock(kCLOCK_Crc);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief resets CRC peripheral module.
|
|
||||||
*
|
|
||||||
* @param base CRC peripheral address.
|
|
||||||
*/
|
|
||||||
void CRC_Reset(CRC_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Loads default values to CRC protocol configuration structure.
|
|
||||||
*
|
|
||||||
* Loads default values to CRC protocol configuration structure. The default values are:
|
|
||||||
* @code
|
|
||||||
* config->polynomial = kCRC_Polynomial_CRC_CCITT;
|
|
||||||
* config->reverseIn = false;
|
|
||||||
* config->complementIn = false;
|
|
||||||
* config->reverseOut = false;
|
|
||||||
* config->complementOut = false;
|
|
||||||
* config->seed = 0xFFFFU;
|
|
||||||
* @endcode
|
|
||||||
*
|
|
||||||
* @param config CRC protocol configuration structure
|
|
||||||
*/
|
|
||||||
void CRC_GetDefaultConfig(crc_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure.
|
|
||||||
*
|
|
||||||
* The values, including seed, can be used to resume CRC calculation later.
|
|
||||||
|
|
||||||
* @param base CRC peripheral address.
|
|
||||||
* @param config CRC protocol configuration structure
|
|
||||||
*/
|
|
||||||
void CRC_GetConfig(CRC_Type *base, crc_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Writes data to the CRC module.
|
|
||||||
*
|
|
||||||
* Writes input data buffer bytes to CRC data register.
|
|
||||||
*
|
|
||||||
* @param base CRC peripheral address.
|
|
||||||
* @param data Input data stream, MSByte in data[0].
|
|
||||||
* @param dataSize Size of the input data buffer in bytes.
|
|
||||||
*/
|
|
||||||
void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Reads 32-bit checksum from the CRC module.
|
|
||||||
*
|
|
||||||
* Reads CRC data register.
|
|
||||||
*
|
|
||||||
* @param base CRC peripheral address.
|
|
||||||
* @return final 32-bit checksum, after configured bit reverse and complement operations.
|
|
||||||
*/
|
|
||||||
static inline uint32_t CRC_Get32bitResult(CRC_Type *base)
|
|
||||||
{
|
|
||||||
return base->SUM;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Reads 16-bit checksum from the CRC module.
|
|
||||||
*
|
|
||||||
* Reads CRC data register.
|
|
||||||
*
|
|
||||||
* @param base CRC peripheral address.
|
|
||||||
* @return final 16-bit checksum, after configured bit reverse and complement operations.
|
|
||||||
*/
|
|
||||||
static inline uint16_t CRC_Get16bitResult(CRC_Type *base)
|
|
||||||
{
|
|
||||||
return (uint16_t)base->SUM;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
*@}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#endif /* _FSL_CRC_H_ */
|
|
||||||
|
|
@ -1,544 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "fsl_ctimer.h"
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.ctimer"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Prototypes
|
|
||||||
******************************************************************************/
|
|
||||||
/*!
|
|
||||||
* @brief Gets the instance from the base address
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
*
|
|
||||||
* @return The Timer instance
|
|
||||||
*/
|
|
||||||
static uint32_t CTIMER_GetInstance(CTIMER_Type *base);
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables
|
|
||||||
******************************************************************************/
|
|
||||||
/*! @brief Pointers to Timer bases for each instance. */
|
|
||||||
static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS;
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/*! @brief Pointers to Timer clocks for each instance. */
|
|
||||||
static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS;
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET))
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
||||||
#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET
|
|
||||||
/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */
|
|
||||||
static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N;
|
|
||||||
#else
|
|
||||||
/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */
|
|
||||||
static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS;
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
||||||
|
|
||||||
/*! @brief Pointers real ISRs installed by drivers for each instance. */
|
|
||||||
static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0};
|
|
||||||
|
|
||||||
/*! @brief Callback type installed by drivers for each instance. */
|
|
||||||
static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback};
|
|
||||||
|
|
||||||
/*! @brief Array to map timer instance to IRQ number. */
|
|
||||||
static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS;
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code
|
|
||||||
******************************************************************************/
|
|
||||||
static uint32_t CTIMER_GetInstance(CTIMER_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t instance;
|
|
||||||
uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0]));
|
|
||||||
|
|
||||||
/* Find the instance index from base address mappings. */
|
|
||||||
for (instance = 0; instance < ctimerArrayCount; instance++)
|
|
||||||
{
|
|
||||||
if (s_ctimerBases[instance] == base)
|
|
||||||
{
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
assert(instance < ctimerArrayCount);
|
|
||||||
|
|
||||||
return instance;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Ungates the clock and configures the peripheral for basic operation.
|
|
||||||
*
|
|
||||||
* note This API should be called at the beginning of the application before using the driver.
|
|
||||||
*
|
|
||||||
* param base Ctimer peripheral base address
|
|
||||||
* param config Pointer to the user configuration structure.
|
|
||||||
*/
|
|
||||||
void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config)
|
|
||||||
{
|
|
||||||
assert(config);
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Enable the timer clock*/
|
|
||||||
CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
||||||
/* Reset the module. */
|
|
||||||
#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET))
|
|
||||||
RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]);
|
|
||||||
#endif
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
||||||
|
|
||||||
/* Setup the cimer mode and count select */
|
|
||||||
#if !defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE
|
|
||||||
base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input);
|
|
||||||
#endif
|
|
||||||
/* Setup the timer prescale value */
|
|
||||||
base->PR = CTIMER_PR_PRVAL(config->prescale);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Gates the timer clock.
|
|
||||||
*
|
|
||||||
* param base Ctimer peripheral base address
|
|
||||||
*/
|
|
||||||
void CTIMER_Deinit(CTIMER_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t index = CTIMER_GetInstance(base);
|
|
||||||
/* Stop the timer */
|
|
||||||
base->TCR &= ~CTIMER_TCR_CEN_MASK;
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Disable the timer clock*/
|
|
||||||
CLOCK_DisableClock(s_ctimerClocks[index]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
/* Disable IRQ at NVIC Level */
|
|
||||||
DisableIRQ(s_ctimerIRQ[index]);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Fills in the timers configuration structure with the default settings.
|
|
||||||
*
|
|
||||||
* The default values are:
|
|
||||||
* code
|
|
||||||
* config->mode = kCTIMER_TimerMode;
|
|
||||||
* config->input = kCTIMER_Capture_0;
|
|
||||||
* config->prescale = 0;
|
|
||||||
* endcode
|
|
||||||
* param config Pointer to the user configuration structure.
|
|
||||||
*/
|
|
||||||
void CTIMER_GetDefaultConfig(ctimer_config_t *config)
|
|
||||||
{
|
|
||||||
assert(config);
|
|
||||||
|
|
||||||
/* Initializes the configure structure to zero. */
|
|
||||||
memset(config, 0, sizeof(*config));
|
|
||||||
|
|
||||||
/* Run as a timer */
|
|
||||||
config->mode = kCTIMER_TimerMode;
|
|
||||||
/* This field is ignored when mode is timer */
|
|
||||||
config->input = kCTIMER_Capture_0;
|
|
||||||
/* Timer counter is incremented on every APB bus clock */
|
|
||||||
config->prescale = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Configures the PWM signal parameters.
|
|
||||||
*
|
|
||||||
* Enables PWM mode on the match channel passed in and will then setup the match value
|
|
||||||
* and other match parameters to generate a PWM signal.
|
|
||||||
* This function will assign match channel 3 to set the PWM cycle.
|
|
||||||
*
|
|
||||||
* note When setting PWM output from multiple output pins, all should use the same PWM
|
|
||||||
* frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution.
|
|
||||||
*
|
|
||||||
* param base Ctimer peripheral base address
|
|
||||||
* param matchChannel Match pin to be used to output the PWM signal
|
|
||||||
* param dutyCyclePercent PWM pulse width; the value should be between 0 to 100
|
|
||||||
* param pwmFreq_Hz PWM signal frequency in Hz
|
|
||||||
* param srcClock_Hz Timer counter clock in Hz
|
|
||||||
* param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse,
|
|
||||||
* if it is 0 then no interrupt is generated
|
|
||||||
*
|
|
||||||
* return kStatus_Success on success
|
|
||||||
* kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle
|
|
||||||
*/
|
|
||||||
status_t CTIMER_SetupPwm(CTIMER_Type *base,
|
|
||||||
ctimer_match_t matchChannel,
|
|
||||||
uint8_t dutyCyclePercent,
|
|
||||||
uint32_t pwmFreq_Hz,
|
|
||||||
uint32_t srcClock_Hz,
|
|
||||||
bool enableInt)
|
|
||||||
{
|
|
||||||
assert(pwmFreq_Hz > 0);
|
|
||||||
|
|
||||||
uint32_t reg;
|
|
||||||
uint32_t period, pulsePeriod = 0;
|
|
||||||
uint32_t timerClock = srcClock_Hz / (base->PR + 1);
|
|
||||||
uint32_t index = CTIMER_GetInstance(base);
|
|
||||||
|
|
||||||
if (matchChannel == kCTIMER_Match_3)
|
|
||||||
{
|
|
||||||
return kStatus_Fail;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Enable PWM mode on the channel */
|
|
||||||
base->PWMC |= (1U << matchChannel);
|
|
||||||
|
|
||||||
/* Clear the stop, reset and interrupt bits for this channel */
|
|
||||||
reg = base->MCR;
|
|
||||||
reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
|
|
||||||
|
|
||||||
/* If call back function is valid then enable match interrupt for the channel */
|
|
||||||
if (enableInt)
|
|
||||||
{
|
|
||||||
reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Reset the counter when match on channel 3 */
|
|
||||||
reg |= CTIMER_MCR_MR3R_MASK;
|
|
||||||
|
|
||||||
base->MCR = reg;
|
|
||||||
|
|
||||||
/* Calculate PWM period match value */
|
|
||||||
period = (timerClock / pwmFreq_Hz) - 1;
|
|
||||||
|
|
||||||
/* Calculate pulse width match value */
|
|
||||||
if (dutyCyclePercent == 0)
|
|
||||||
{
|
|
||||||
pulsePeriod = period + 1;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Match on channel 3 will define the PWM period */
|
|
||||||
base->MR[kCTIMER_Match_3] = period;
|
|
||||||
|
|
||||||
/* This will define the PWM pulse period */
|
|
||||||
base->MR[matchChannel] = pulsePeriod;
|
|
||||||
/* Clear status flags */
|
|
||||||
CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
|
|
||||||
/* If call back function is valid then enable interrupt and update the call back function */
|
|
||||||
if (enableInt)
|
|
||||||
{
|
|
||||||
EnableIRQ(s_ctimerIRQ[index]);
|
|
||||||
}
|
|
||||||
|
|
||||||
return kStatus_Success;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Configures the PWM signal parameters.
|
|
||||||
*
|
|
||||||
* Enables PWM mode on the match channel passed in and will then setup the match value
|
|
||||||
* and other match parameters to generate a PWM signal.
|
|
||||||
* This function will assign match channel 3 to set the PWM cycle.
|
|
||||||
*
|
|
||||||
* note When setting PWM output from multiple output pins, all should use the same PWM
|
|
||||||
* period
|
|
||||||
*
|
|
||||||
* param base Ctimer peripheral base address
|
|
||||||
* param matchChannel Match pin to be used to output the PWM signal
|
|
||||||
* param pwmPeriod PWM period match value
|
|
||||||
* param pulsePeriod Pulse width match value
|
|
||||||
* param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse,
|
|
||||||
* if it is 0 then no interrupt is generated
|
|
||||||
*
|
|
||||||
* return kStatus_Success on success
|
|
||||||
* kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period
|
|
||||||
*/
|
|
||||||
status_t CTIMER_SetupPwmPeriod(
|
|
||||||
CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt)
|
|
||||||
{
|
|
||||||
/* Some CTimers only have 16bits , so the value is limited*/
|
|
||||||
#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B
|
|
||||||
assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU)));
|
|
||||||
#endif
|
|
||||||
|
|
||||||
uint32_t reg;
|
|
||||||
uint32_t index = CTIMER_GetInstance(base);
|
|
||||||
|
|
||||||
if (matchChannel == kCTIMER_Match_3)
|
|
||||||
{
|
|
||||||
return kStatus_Fail;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Enable PWM mode on the channel */
|
|
||||||
base->PWMC |= (1U << matchChannel);
|
|
||||||
|
|
||||||
/* Clear the stop, reset and interrupt bits for this channel */
|
|
||||||
reg = base->MCR;
|
|
||||||
reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
|
|
||||||
|
|
||||||
/* If call back function is valid then enable match interrupt for the channel */
|
|
||||||
if (enableInt)
|
|
||||||
{
|
|
||||||
reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Reset the counter when match on channel 3 */
|
|
||||||
reg |= CTIMER_MCR_MR3R_MASK;
|
|
||||||
|
|
||||||
base->MCR = reg;
|
|
||||||
|
|
||||||
/* Match on channel 3 will define the PWM period */
|
|
||||||
base->MR[kCTIMER_Match_3] = pwmPeriod;
|
|
||||||
|
|
||||||
/* This will define the PWM pulse period */
|
|
||||||
base->MR[matchChannel] = pulsePeriod;
|
|
||||||
/* Clear status flags */
|
|
||||||
CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
|
|
||||||
/* If call back function is valid then enable interrupt and update the call back function */
|
|
||||||
if (enableInt)
|
|
||||||
{
|
|
||||||
EnableIRQ(s_ctimerIRQ[index]);
|
|
||||||
}
|
|
||||||
|
|
||||||
return kStatus_Success;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Updates the duty cycle of an active PWM signal.
|
|
||||||
*
|
|
||||||
* note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution.
|
|
||||||
*
|
|
||||||
* param base Ctimer peripheral base address
|
|
||||||
* param matchChannel Match pin to be used to output the PWM signal
|
|
||||||
* param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100
|
|
||||||
*/
|
|
||||||
void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent)
|
|
||||||
{
|
|
||||||
uint32_t pulsePeriod = 0, period;
|
|
||||||
|
|
||||||
/* Match channel 3 defines the PWM period */
|
|
||||||
period = base->MR[kCTIMER_Match_3];
|
|
||||||
|
|
||||||
/* Calculate pulse width match value */
|
|
||||||
pulsePeriod = (period * dutyCyclePercent) / 100;
|
|
||||||
|
|
||||||
/* For 0% dutycyle, make pulse period greater than period so the event will never occur */
|
|
||||||
if (dutyCyclePercent == 0)
|
|
||||||
{
|
|
||||||
pulsePeriod = period + 1;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Update dutycycle */
|
|
||||||
base->MR[matchChannel] = pulsePeriod;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Setup the match register.
|
|
||||||
*
|
|
||||||
* User configuration is used to setup the match value and action to be taken when a match occurs.
|
|
||||||
*
|
|
||||||
* param base Ctimer peripheral base address
|
|
||||||
* param matchChannel Match register to configure
|
|
||||||
* param config Pointer to the match configuration structure
|
|
||||||
*/
|
|
||||||
void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config)
|
|
||||||
{
|
|
||||||
/* Some CTimers only have 16bits , so the value is limited*/
|
|
||||||
#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B
|
|
||||||
assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU));
|
|
||||||
#endif
|
|
||||||
uint32_t reg;
|
|
||||||
uint32_t index = CTIMER_GetInstance(base);
|
|
||||||
|
|
||||||
/* Set the counter operation when a match on this channel occurs */
|
|
||||||
reg = base->MCR;
|
|
||||||
reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
|
|
||||||
reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3)));
|
|
||||||
reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3)));
|
|
||||||
reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
|
|
||||||
base->MCR = reg;
|
|
||||||
|
|
||||||
reg = base->EMR;
|
|
||||||
/* Set the match output operation when a match on this channel occurs */
|
|
||||||
reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2));
|
|
||||||
reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2));
|
|
||||||
|
|
||||||
/* Set the initial state of the EM bit/output */
|
|
||||||
reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel);
|
|
||||||
reg |= (uint32_t)config->outPinInitState << matchChannel;
|
|
||||||
base->EMR = reg;
|
|
||||||
|
|
||||||
/* Set the match value */
|
|
||||||
base->MR[matchChannel] = config->matchValue;
|
|
||||||
/* Clear status flags */
|
|
||||||
CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
|
|
||||||
/* If interrupt is enabled then enable interrupt and update the call back function */
|
|
||||||
if (config->enableInterrupt)
|
|
||||||
{
|
|
||||||
EnableIRQ(s_ctimerIRQ[index]);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
#if !defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE
|
|
||||||
/*!
|
|
||||||
* brief Setup the capture.
|
|
||||||
*
|
|
||||||
* param base Ctimer peripheral base address
|
|
||||||
* param capture Capture channel to configure
|
|
||||||
* param edge Edge on the channel that will trigger a capture
|
|
||||||
* param enableInt Flag to enable channel interrupts, if enabled then the registered call back
|
|
||||||
* is called upon capture
|
|
||||||
*/
|
|
||||||
void CTIMER_SetupCapture(CTIMER_Type *base,
|
|
||||||
ctimer_capture_channel_t capture,
|
|
||||||
ctimer_capture_edge_t edge,
|
|
||||||
bool enableInt)
|
|
||||||
{
|
|
||||||
uint32_t reg = base->CCR;
|
|
||||||
uint32_t index = CTIMER_GetInstance(base);
|
|
||||||
|
|
||||||
/* Set the capture edge */
|
|
||||||
reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3));
|
|
||||||
reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3));
|
|
||||||
/* Clear status flags */
|
|
||||||
CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture));
|
|
||||||
/* If call back function is valid then enable capture interrupt for the channel and update the call back function */
|
|
||||||
if (enableInt)
|
|
||||||
{
|
|
||||||
reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3);
|
|
||||||
EnableIRQ(s_ctimerIRQ[index]);
|
|
||||||
}
|
|
||||||
base->CCR = reg;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Register callback.
|
|
||||||
*
|
|
||||||
* param base Ctimer peripheral base address
|
|
||||||
* param cb_func callback function
|
|
||||||
* param cb_type callback function type, singular or multiple
|
|
||||||
*/
|
|
||||||
void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type)
|
|
||||||
{
|
|
||||||
uint32_t index = CTIMER_GetInstance(base);
|
|
||||||
s_ctimerCallback[index] = cb_func;
|
|
||||||
ctimerCallbackType[index] = cb_type;
|
|
||||||
}
|
|
||||||
|
|
||||||
void CTIMER_GenericIRQHandler(uint32_t index)
|
|
||||||
{
|
|
||||||
uint32_t int_stat, i, mask;
|
|
||||||
/* Get Interrupt status flags */
|
|
||||||
int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]);
|
|
||||||
/* Clear the status flags that were set */
|
|
||||||
CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat);
|
|
||||||
if (ctimerCallbackType[index] == kCTIMER_SingleCallback)
|
|
||||||
{
|
|
||||||
if (s_ctimerCallback[index][0])
|
|
||||||
{
|
|
||||||
s_ctimerCallback[index][0](int_stat);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE
|
|
||||||
for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++)
|
|
||||||
#else
|
|
||||||
#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT
|
|
||||||
for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++)
|
|
||||||
#else
|
|
||||||
for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++)
|
|
||||||
#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
|
|
||||||
#endif
|
|
||||||
{
|
|
||||||
mask = 0x01 << i;
|
|
||||||
/* For each status flag bit that was set call the callback function if it is valid */
|
|
||||||
if ((int_stat & mask) && (s_ctimerCallback[index][i]))
|
|
||||||
{
|
|
||||||
s_ctimerCallback[index][i](int_stat);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/* IRQ handler functions overloading weak symbols in the startup */
|
|
||||||
#if defined(CTIMER0)
|
|
||||||
void CTIMER0_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
CTIMER_GenericIRQHandler(0);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CTIMER1)
|
|
||||||
void CTIMER1_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
CTIMER_GenericIRQHandler(1);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CTIMER2)
|
|
||||||
void CTIMER2_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
CTIMER_GenericIRQHandler(2);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CTIMER3)
|
|
||||||
void CTIMER3_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
CTIMER_GenericIRQHandler(3);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CTIMER4)
|
|
||||||
void CTIMER4_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
CTIMER_GenericIRQHandler(4);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,488 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
#ifndef _FSL_CTIMER_H_
|
|
||||||
#define _FSL_CTIMER_H_
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup ctimer
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @file */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*! @brief List of Timer capture channels */
|
|
||||||
typedef enum _ctimer_capture_channel
|
|
||||||
{
|
|
||||||
kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */
|
|
||||||
kCTIMER_Capture_1, /*!< Timer capture channel 1 */
|
|
||||||
kCTIMER_Capture_2, /*!< Timer capture channel 2 */
|
|
||||||
#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
|
|
||||||
kCTIMER_Capture_3 /*!< Timer capture channel 3 */
|
|
||||||
#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
|
|
||||||
} ctimer_capture_channel_t;
|
|
||||||
|
|
||||||
/*! @brief List of capture edge options */
|
|
||||||
typedef enum _ctimer_capture_edge
|
|
||||||
{
|
|
||||||
kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */
|
|
||||||
kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */
|
|
||||||
kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */
|
|
||||||
} ctimer_capture_edge_t;
|
|
||||||
|
|
||||||
/*! @brief List of Timer match registers */
|
|
||||||
typedef enum _ctimer_match
|
|
||||||
{
|
|
||||||
kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */
|
|
||||||
kCTIMER_Match_1, /*!< Timer match register 1 */
|
|
||||||
kCTIMER_Match_2, /*!< Timer match register 2 */
|
|
||||||
kCTIMER_Match_3 /*!< Timer match register 3 */
|
|
||||||
} ctimer_match_t;
|
|
||||||
|
|
||||||
/*! @brief List of output control options */
|
|
||||||
typedef enum _ctimer_match_output_control
|
|
||||||
{
|
|
||||||
kCTIMER_Output_NoAction = 0U, /*!< No action is taken */
|
|
||||||
kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */
|
|
||||||
kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */
|
|
||||||
kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */
|
|
||||||
} ctimer_match_output_control_t;
|
|
||||||
|
|
||||||
/*! @brief List of Timer modes */
|
|
||||||
typedef enum _ctimer_timer_mode
|
|
||||||
{
|
|
||||||
kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */
|
|
||||||
kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */
|
|
||||||
kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */
|
|
||||||
kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */
|
|
||||||
} ctimer_timer_mode_t;
|
|
||||||
|
|
||||||
/*! @brief List of Timer interrupts */
|
|
||||||
typedef enum _ctimer_interrupt_enable
|
|
||||||
{
|
|
||||||
kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */
|
|
||||||
kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */
|
|
||||||
kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */
|
|
||||||
kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */
|
|
||||||
#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
|
|
||||||
kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */
|
|
||||||
kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */
|
|
||||||
kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */
|
|
||||||
#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
|
|
||||||
kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */
|
|
||||||
#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
|
|
||||||
#endif
|
|
||||||
} ctimer_interrupt_enable_t;
|
|
||||||
|
|
||||||
/*! @brief List of Timer flags */
|
|
||||||
typedef enum _ctimer_status_flags
|
|
||||||
{
|
|
||||||
kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */
|
|
||||||
kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */
|
|
||||||
kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */
|
|
||||||
kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */
|
|
||||||
#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
|
|
||||||
kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */
|
|
||||||
kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */
|
|
||||||
kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */
|
|
||||||
#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT
|
|
||||||
kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */
|
|
||||||
#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
|
|
||||||
#endif
|
|
||||||
} ctimer_status_flags_t;
|
|
||||||
|
|
||||||
typedef void (*ctimer_callback_t)(uint32_t flags);
|
|
||||||
|
|
||||||
/*! @brief Callback type when registering for a callback. When registering a callback
|
|
||||||
* an array of function pointers is passed the size could be 1 or 8, the callback
|
|
||||||
* type will tell that.
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer.
|
|
||||||
based on the status flags different channels needs to be handled differently */
|
|
||||||
kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel.
|
|
||||||
for both match/capture */
|
|
||||||
} ctimer_callback_type_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Match configuration
|
|
||||||
*
|
|
||||||
* This structure holds the configuration settings for each match register.
|
|
||||||
*/
|
|
||||||
typedef struct _ctimer_match_config
|
|
||||||
{
|
|
||||||
uint32_t matchValue; /*!< This is stored in the match register */
|
|
||||||
bool enableCounterReset; /*!< true: Match will reset the counter
|
|
||||||
false: Match will not reser the counter */
|
|
||||||
bool enableCounterStop; /*!< true: Match will stop the counter
|
|
||||||
false: Match will not stop the counter */
|
|
||||||
ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */
|
|
||||||
bool outPinInitState; /*!< Initial value of the EM bit/output */
|
|
||||||
bool enableInterrupt; /*!< true: Generate interrupt upon match
|
|
||||||
false: Do not generate interrupt on match */
|
|
||||||
|
|
||||||
} ctimer_match_config_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Timer configuration structure
|
|
||||||
*
|
|
||||||
* This structure holds the configuration settings for the Timer peripheral. To initialize this
|
|
||||||
* structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a
|
|
||||||
* pointer to the configuration structure instance.
|
|
||||||
*
|
|
||||||
* The configuration structure can be made constant so as to reside in flash.
|
|
||||||
*/
|
|
||||||
typedef struct _ctimer_config
|
|
||||||
{
|
|
||||||
ctimer_timer_mode_t mode; /*!< Timer mode */
|
|
||||||
ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer
|
|
||||||
modes that rely on this input signal to increment TC */
|
|
||||||
uint32_t prescale; /*!< Prescale value */
|
|
||||||
} ctimer_config_t;
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Initialization and deinitialization
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Ungates the clock and configures the peripheral for basic operation.
|
|
||||||
*
|
|
||||||
* @note This API should be called at the beginning of the application before using the driver.
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
* @param config Pointer to the user configuration structure.
|
|
||||||
*/
|
|
||||||
void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Gates the timer clock.
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
*/
|
|
||||||
void CTIMER_Deinit(CTIMER_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Fills in the timers configuration structure with the default settings.
|
|
||||||
*
|
|
||||||
* The default values are:
|
|
||||||
* @code
|
|
||||||
* config->mode = kCTIMER_TimerMode;
|
|
||||||
* config->input = kCTIMER_Capture_0;
|
|
||||||
* config->prescale = 0;
|
|
||||||
* @endcode
|
|
||||||
* @param config Pointer to the user configuration structure.
|
|
||||||
*/
|
|
||||||
void CTIMER_GetDefaultConfig(ctimer_config_t *config);
|
|
||||||
|
|
||||||
/*! @}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name PWM setup operations
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Configures the PWM signal parameters.
|
|
||||||
*
|
|
||||||
* Enables PWM mode on the match channel passed in and will then setup the match value
|
|
||||||
* and other match parameters to generate a PWM signal.
|
|
||||||
* This function will assign match channel 3 to set the PWM cycle.
|
|
||||||
*
|
|
||||||
* @note When setting PWM output from multiple output pins, all should use the same PWM
|
|
||||||
* period
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
* @param matchChannel Match pin to be used to output the PWM signal
|
|
||||||
* @param pwmPeriod PWM period match value
|
|
||||||
* @param pulsePeriod Pulse width match value
|
|
||||||
* @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse,
|
|
||||||
* if it is 0 then no interrupt is generated
|
|
||||||
*
|
|
||||||
* @return kStatus_Success on success
|
|
||||||
* kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period
|
|
||||||
*/
|
|
||||||
status_t CTIMER_SetupPwmPeriod(
|
|
||||||
CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Configures the PWM signal parameters.
|
|
||||||
*
|
|
||||||
* Enables PWM mode on the match channel passed in and will then setup the match value
|
|
||||||
* and other match parameters to generate a PWM signal.
|
|
||||||
* This function will assign match channel 3 to set the PWM cycle.
|
|
||||||
*
|
|
||||||
* @note When setting PWM output from multiple output pins, all should use the same PWM
|
|
||||||
* frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution.
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
* @param matchChannel Match pin to be used to output the PWM signal
|
|
||||||
* @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100
|
|
||||||
* @param pwmFreq_Hz PWM signal frequency in Hz
|
|
||||||
* @param srcClock_Hz Timer counter clock in Hz
|
|
||||||
* @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse,
|
|
||||||
* if it is 0 then no interrupt is generated
|
|
||||||
*
|
|
||||||
* @return kStatus_Success on success
|
|
||||||
* kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle
|
|
||||||
*/
|
|
||||||
status_t CTIMER_SetupPwm(CTIMER_Type *base,
|
|
||||||
ctimer_match_t matchChannel,
|
|
||||||
uint8_t dutyCyclePercent,
|
|
||||||
uint32_t pwmFreq_Hz,
|
|
||||||
uint32_t srcClock_Hz,
|
|
||||||
bool enableInt);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Updates the pulse period of an active PWM signal.
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
* @param matchChannel Match pin to be used to output the PWM signal
|
|
||||||
* @param pulsePeriod New PWM pulse width match value
|
|
||||||
*/
|
|
||||||
static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod)
|
|
||||||
{
|
|
||||||
/* Update PWM pulse period match value */
|
|
||||||
base->MR[matchChannel] = pulsePeriod;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Updates the duty cycle of an active PWM signal.
|
|
||||||
*
|
|
||||||
* @note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution.
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
* @param matchChannel Match pin to be used to output the PWM signal
|
|
||||||
* @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100
|
|
||||||
*/
|
|
||||||
void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent);
|
|
||||||
|
|
||||||
/*! @}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Setup the match register.
|
|
||||||
*
|
|
||||||
* User configuration is used to setup the match value and action to be taken when a match occurs.
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
* @param matchChannel Match register to configure
|
|
||||||
* @param config Pointer to the match configuration structure
|
|
||||||
*/
|
|
||||||
void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Setup the capture.
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
* @param capture Capture channel to configure
|
|
||||||
* @param edge Edge on the channel that will trigger a capture
|
|
||||||
* @param enableInt Flag to enable channel interrupts, if enabled then the registered call back
|
|
||||||
* is called upon capture
|
|
||||||
*/
|
|
||||||
void CTIMER_SetupCapture(CTIMER_Type *base,
|
|
||||||
ctimer_capture_channel_t capture,
|
|
||||||
ctimer_capture_edge_t edge,
|
|
||||||
bool enableInt);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get the timer count value from TC register.
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address.
|
|
||||||
* @return return the timer count value.
|
|
||||||
*/
|
|
||||||
static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base)
|
|
||||||
{
|
|
||||||
return (base->TC);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Register callback.
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
* @param cb_func callback function
|
|
||||||
* @param cb_type callback function type, singular or multiple
|
|
||||||
*/
|
|
||||||
void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Interrupt Interface
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enables the selected Timer interrupts.
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
* @param mask The interrupts to enable. This is a logical OR of members of the
|
|
||||||
* enumeration ::ctimer_interrupt_enable_t
|
|
||||||
*/
|
|
||||||
static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask)
|
|
||||||
{
|
|
||||||
/* Enable match interrupts */
|
|
||||||
base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK);
|
|
||||||
|
|
||||||
/* Enable capture interrupts */
|
|
||||||
#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
|
|
||||||
base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
|
|
||||||
#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
|
|
||||||
| CTIMER_CCR_CAP3I_MASK
|
|
||||||
#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
|
|
||||||
);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Disables the selected Timer interrupts.
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
* @param mask The interrupts to enable. This is a logical OR of members of the
|
|
||||||
* enumeration ::ctimer_interrupt_enable_t
|
|
||||||
*/
|
|
||||||
static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask)
|
|
||||||
{
|
|
||||||
/* Disable match interrupts */
|
|
||||||
base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK));
|
|
||||||
|
|
||||||
/* Disable capture interrupts */
|
|
||||||
#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
|
|
||||||
base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
|
|
||||||
#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
|
|
||||||
| CTIMER_CCR_CAP3I_MASK
|
|
||||||
#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
|
|
||||||
));
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Gets the enabled Timer interrupts.
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
*
|
|
||||||
* @return The enabled interrupts. This is the logical OR of members of the
|
|
||||||
* enumeration ::ctimer_interrupt_enable_t
|
|
||||||
*/
|
|
||||||
static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t enabledIntrs = 0;
|
|
||||||
|
|
||||||
/* Get all the match interrupts enabled */
|
|
||||||
enabledIntrs =
|
|
||||||
base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK);
|
|
||||||
|
|
||||||
/* Get all the capture interrupts enabled */
|
|
||||||
#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
|
|
||||||
enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
|
|
||||||
#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
|
|
||||||
| CTIMER_CCR_CAP3I_MASK
|
|
||||||
#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
|
|
||||||
);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
return enabledIntrs;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! @}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Status Interface
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Gets the Timer status flags.
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
*
|
|
||||||
* @return The status flags. This is the logical OR of members of the
|
|
||||||
* enumeration ::ctimer_status_flags_t
|
|
||||||
*/
|
|
||||||
static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base)
|
|
||||||
{
|
|
||||||
return base->IR;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Clears the Timer status flags.
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
* @param mask The status flags to clear. This is a logical OR of members of the
|
|
||||||
* enumeration ::ctimer_status_flags_t
|
|
||||||
*/
|
|
||||||
static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask)
|
|
||||||
{
|
|
||||||
base->IR = mask;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! @}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Counter Start and Stop
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Starts the Timer counter.
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
*/
|
|
||||||
static inline void CTIMER_StartTimer(CTIMER_Type *base)
|
|
||||||
{
|
|
||||||
base->TCR |= CTIMER_TCR_CEN_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Stops the Timer counter.
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
*/
|
|
||||||
static inline void CTIMER_StopTimer(CTIMER_Type *base)
|
|
||||||
{
|
|
||||||
base->TCR &= ~CTIMER_TCR_CEN_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! @}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Reset the counter.
|
|
||||||
*
|
|
||||||
* The timer counter and prescale counter are reset on the next positive edge of the APB clock.
|
|
||||||
*
|
|
||||||
* @param base Ctimer peripheral base address
|
|
||||||
*/
|
|
||||||
static inline void CTIMER_Reset(CTIMER_Type *base)
|
|
||||||
{
|
|
||||||
base->TCR |= CTIMER_TCR_CRST_MASK;
|
|
||||||
base->TCR &= ~CTIMER_TCR_CRST_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*! @}*/
|
|
||||||
|
|
||||||
#endif /* _FSL_CTIMER_H_ */
|
|
||||||
|
|
@ -1,734 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "fsl_dma.h"
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.lpc_dma"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Prototypes
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get instance number for DMA.
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
*/
|
|
||||||
static uint32_t DMA_GetInstance(DMA_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get virtual channel number.
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
*/
|
|
||||||
static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base);
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*! @brief Array to map DMA instance number to base pointer. */
|
|
||||||
static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS;
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/*! @brief Array to map DMA instance number to clock name. */
|
|
||||||
static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS;
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET)
|
|
||||||
/*! @brief Pointers to DMA resets for each instance. */
|
|
||||||
static const reset_ip_name_t s_dmaResets[] = DMA_RSTS_N;
|
|
||||||
#endif /*! @brief Array to map DMA instance number to IRQ number. */
|
|
||||||
static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS;
|
|
||||||
|
|
||||||
/*! @brief Pointers to transfer handle for each DMA channel. */
|
|
||||||
static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS];
|
|
||||||
|
|
||||||
SDK_ALIGN(dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS],
|
|
||||||
FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE);
|
|
||||||
#if defined(DMA1)
|
|
||||||
SDK_ALIGN(dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS],
|
|
||||||
FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE);
|
|
||||||
static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0, s_dma_descriptor_table1};
|
|
||||||
#else
|
|
||||||
static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0};
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
static uint32_t DMA_GetInstance(DMA_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t instance;
|
|
||||||
/* Find the instance index from base address mappings. */
|
|
||||||
for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++)
|
|
||||||
{
|
|
||||||
if (s_dmaBases[instance] == base)
|
|
||||||
{
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
assert(instance < ARRAY_SIZE(s_dmaBases));
|
|
||||||
|
|
||||||
return instance;
|
|
||||||
}
|
|
||||||
|
|
||||||
static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t startChannel = 0, instance = 0;
|
|
||||||
uint32_t i = 0;
|
|
||||||
|
|
||||||
instance = DMA_GetInstance(base);
|
|
||||||
|
|
||||||
/* Compute start channel */
|
|
||||||
for (i = 0; i < instance; i++)
|
|
||||||
{
|
|
||||||
startChannel += FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]);
|
|
||||||
}
|
|
||||||
|
|
||||||
return startChannel;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Initializes DMA peripheral.
|
|
||||||
*
|
|
||||||
* This function enable the DMA clock, set descriptor table and
|
|
||||||
* enable DMA peripheral.
|
|
||||||
*
|
|
||||||
* param base DMA peripheral base address.
|
|
||||||
*/
|
|
||||||
void DMA_Init(DMA_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t instance = DMA_GetInstance(base);
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* enable dma clock gate */
|
|
||||||
CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET)
|
|
||||||
/* Reset the DMA module */
|
|
||||||
RESET_PeripheralReset(s_dmaResets[DMA_GetInstance(base)]);
|
|
||||||
#endif
|
|
||||||
/* set descriptor table */
|
|
||||||
base->SRAMBASE = (uint32_t)s_dma_descriptor_table[instance];
|
|
||||||
/* enable dma peripheral */
|
|
||||||
base->CTRL |= DMA_CTRL_ENABLE_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Deinitializes DMA peripheral.
|
|
||||||
*
|
|
||||||
* This function gates the DMA clock.
|
|
||||||
*
|
|
||||||
* param base DMA peripheral base address.
|
|
||||||
*/
|
|
||||||
void DMA_Deinit(DMA_Type *base)
|
|
||||||
{
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
/* Disable DMA peripheral */
|
|
||||||
base->CTRL &= ~(DMA_CTRL_ENABLE_MASK);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Set trigger settings of DMA channel.
|
|
||||||
* deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig.
|
|
||||||
*
|
|
||||||
* param base DMA peripheral base address.
|
|
||||||
* param channel DMA channel number.
|
|
||||||
* param trigger trigger configuration.
|
|
||||||
*/
|
|
||||||
void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger)
|
|
||||||
{
|
|
||||||
assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger));
|
|
||||||
|
|
||||||
uint32_t tmp = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK |
|
|
||||||
DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK |
|
|
||||||
DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK);
|
|
||||||
tmp = base->CHANNEL[channel].CFG & (~tmp);
|
|
||||||
tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap);
|
|
||||||
base->CHANNEL[channel].CFG = tmp;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Gets the remaining bytes of the current DMA descriptor transfer.
|
|
||||||
*
|
|
||||||
* param base DMA peripheral base address.
|
|
||||||
* param channel DMA channel number.
|
|
||||||
* return The number of bytes which have not been transferred yet.
|
|
||||||
*/
|
|
||||||
uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
|
|
||||||
|
|
||||||
/* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes
|
|
||||||
* impossible to distinguish between:
|
|
||||||
* - transfer finishes (represented by value '0x3FF')
|
|
||||||
* - and remaining 1024 bytes to transfer (value 0x3FF)
|
|
||||||
* for all descriptor in chain, except the last one.
|
|
||||||
* If you decide to use this function, please use 1023 transfers as maximal value */
|
|
||||||
|
|
||||||
/* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */
|
|
||||||
if ((!DMA_ChannelIsActive(base, channel)) &&
|
|
||||||
(0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >>
|
|
||||||
DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)))
|
|
||||||
{
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
return ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >>
|
|
||||||
DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) +
|
|
||||||
1;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Verify and convert dma_xfercfg_t to XFERCFG register */
|
|
||||||
static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr)
|
|
||||||
{
|
|
||||||
assert(xfercfg != NULL);
|
|
||||||
/* check source increment */
|
|
||||||
assert((xfercfg->srcInc <= kDMA_AddressInterleave4xWidth) && (xfercfg->dstInc <= kDMA_AddressInterleave4xWidth));
|
|
||||||
/* check data width */
|
|
||||||
assert(xfercfg->byteWidth <= kDMA_Transfer32BitWidth);
|
|
||||||
/* check transfer count */
|
|
||||||
assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT);
|
|
||||||
|
|
||||||
uint32_t xfer = 0;
|
|
||||||
|
|
||||||
/* set valid flag - descriptor is ready now */
|
|
||||||
xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid);
|
|
||||||
/* set reload - allow link to next descriptor */
|
|
||||||
xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload);
|
|
||||||
/* set swtrig flag - start transfer */
|
|
||||||
xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig);
|
|
||||||
/* set transfer count */
|
|
||||||
xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig);
|
|
||||||
/* set INTA */
|
|
||||||
xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA);
|
|
||||||
/* set INTB */
|
|
||||||
xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB);
|
|
||||||
/* set data width */
|
|
||||||
xfer |= DMA_CHANNEL_XFERCFG_WIDTH(xfercfg->byteWidth == 4 ? 2 : xfercfg->byteWidth - 1);
|
|
||||||
/* set source increment value */
|
|
||||||
xfer |= DMA_CHANNEL_XFERCFG_SRCINC((xfercfg->srcInc == kDMA_AddressInterleave4xWidth) ? (xfercfg->srcInc - 1) :
|
|
||||||
xfercfg->srcInc);
|
|
||||||
/* set destination increment value */
|
|
||||||
xfer |= DMA_CHANNEL_XFERCFG_DSTINC((xfercfg->dstInc == kDMA_AddressInterleave4xWidth) ? (xfercfg->dstInc - 1) :
|
|
||||||
xfercfg->dstInc);
|
|
||||||
/* set transfer count */
|
|
||||||
xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1);
|
|
||||||
|
|
||||||
/* store xferCFG */
|
|
||||||
*xfercfg_addr = xfer;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief setup dma descriptor
|
|
||||||
*
|
|
||||||
* param desc DMA descriptor address.
|
|
||||||
* param xfercfg Transfer configuration for DMA descriptor.
|
|
||||||
* param srcStartAddr Start address of source address.
|
|
||||||
* param dstStartAddr Start address of destination address.
|
|
||||||
* param nextDesc Address of next descriptor in chain.
|
|
||||||
*/
|
|
||||||
void DMA_SetupDescriptor(
|
|
||||||
dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc)
|
|
||||||
{
|
|
||||||
assert(((uint32_t)nextDesc & (DMA_LINK_DESCRIPTOR_ADDRESS_ALIGN - 1)) == 0U);
|
|
||||||
|
|
||||||
uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0;
|
|
||||||
|
|
||||||
width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT;
|
|
||||||
srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT;
|
|
||||||
dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT;
|
|
||||||
transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U;
|
|
||||||
|
|
||||||
/* covert register value to actual value */
|
|
||||||
if (width == 2U)
|
|
||||||
{
|
|
||||||
width = kDMA_Transfer32BitWidth;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
width += 1U;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (srcInc == 3U)
|
|
||||||
{
|
|
||||||
srcInc = kDMA_AddressInterleave4xWidth;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (dstInc == 3U)
|
|
||||||
{
|
|
||||||
dstInc = kDMA_AddressInterleave4xWidth;
|
|
||||||
}
|
|
||||||
|
|
||||||
desc->xfercfg = xfercfg;
|
|
||||||
desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS(srcStartAddr, srcInc, transferCount * width, width);
|
|
||||||
desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS(dstStartAddr, dstInc, transferCount * width, width);
|
|
||||||
;
|
|
||||||
desc->linkToNextDesc = nextDesc;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Create application specific DMA descriptor
|
|
||||||
* to be used in a chain in transfer
|
|
||||||
* deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor
|
|
||||||
* param desc DMA descriptor address.
|
|
||||||
* param xfercfg Transfer configuration for DMA descriptor.
|
|
||||||
* param srcAddr Address of last item to transmit
|
|
||||||
* param dstAddr Address of last item to receive.
|
|
||||||
* param nextDesc Address of next descriptor in chain.
|
|
||||||
*/
|
|
||||||
void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc)
|
|
||||||
{
|
|
||||||
assert(((uint32_t)nextDesc & (DMA_LINK_DESCRIPTOR_ADDRESS_ALIGN - 1)) == 0U);
|
|
||||||
assert((NULL != srcAddr) && (0 == (uint32_t)srcAddr % xfercfg->byteWidth));
|
|
||||||
assert((NULL != dstAddr) && (0 == (uint32_t)dstAddr % xfercfg->byteWidth));
|
|
||||||
|
|
||||||
uint32_t xfercfg_reg = 0;
|
|
||||||
|
|
||||||
DMA_SetupXferCFG(xfercfg, &xfercfg_reg);
|
|
||||||
|
|
||||||
/* Set descriptor structure */
|
|
||||||
DMA_SetupDescriptor(desc, xfercfg_reg, srcAddr, dstAddr, nextDesc);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Abort running transfer by handle.
|
|
||||||
*
|
|
||||||
* This function aborts DMA transfer specified by handle.
|
|
||||||
*
|
|
||||||
* param handle DMA handle pointer.
|
|
||||||
*/
|
|
||||||
void DMA_AbortTransfer(dma_handle_t *handle)
|
|
||||||
{
|
|
||||||
assert(NULL != handle);
|
|
||||||
|
|
||||||
DMA_DisableChannel(handle->base, handle->channel);
|
|
||||||
while (DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & (1U << DMA_CHANNEL_INDEX(handle->channel)))
|
|
||||||
{
|
|
||||||
}
|
|
||||||
DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1U << DMA_CHANNEL_INDEX(handle->channel);
|
|
||||||
DMA_EnableChannel(handle->base, handle->channel);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Creates the DMA handle.
|
|
||||||
*
|
|
||||||
* This function is called if using transaction API for DMA. This function
|
|
||||||
* initializes the internal state of DMA handle.
|
|
||||||
*
|
|
||||||
* param handle DMA handle pointer. The DMA handle stores callback function and
|
|
||||||
* parameters.
|
|
||||||
* param base DMA peripheral base address.
|
|
||||||
* param channel DMA channel number.
|
|
||||||
*/
|
|
||||||
void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel)
|
|
||||||
{
|
|
||||||
assert((NULL != handle) && (channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)));
|
|
||||||
|
|
||||||
int32_t dmaInstance;
|
|
||||||
uint32_t startChannel = 0;
|
|
||||||
/* base address is invalid DMA instance */
|
|
||||||
dmaInstance = DMA_GetInstance(base);
|
|
||||||
startChannel = DMA_GetVirtualStartChannel(base);
|
|
||||||
|
|
||||||
memset(handle, 0, sizeof(*handle));
|
|
||||||
handle->base = base;
|
|
||||||
handle->channel = channel;
|
|
||||||
s_DMAHandle[startChannel + channel] = handle;
|
|
||||||
/* Enable NVIC interrupt */
|
|
||||||
EnableIRQ(s_dmaIRQNumber[dmaInstance]);
|
|
||||||
/* Enable channel interrupt */
|
|
||||||
DMA_EnableChannelInterrupts(handle->base, channel);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Installs a callback function for the DMA transfer.
|
|
||||||
*
|
|
||||||
* This callback is called in DMA IRQ handler. Use the callback to do something after
|
|
||||||
* the current major loop transfer completes.
|
|
||||||
*
|
|
||||||
* param handle DMA handle pointer.
|
|
||||||
* param callback DMA callback function pointer.
|
|
||||||
* param userData Parameter for callback function.
|
|
||||||
*/
|
|
||||||
void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData)
|
|
||||||
{
|
|
||||||
assert(handle != NULL);
|
|
||||||
|
|
||||||
handle->callback = callback;
|
|
||||||
handle->userData = userData;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Prepares the DMA transfer structure.
|
|
||||||
* deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer and
|
|
||||||
* DMA_PrepareChannelXfer.
|
|
||||||
* This function prepares the transfer configuration structure according to the user input.
|
|
||||||
*
|
|
||||||
* param config The user configuration structure of type dma_transfer_t.
|
|
||||||
* param srcAddr DMA transfer source address.
|
|
||||||
* param dstAddr DMA transfer destination address.
|
|
||||||
* param byteWidth DMA transfer destination address width(bytes).
|
|
||||||
* param transferBytes DMA transfer bytes to be transferred.
|
|
||||||
* param type DMA transfer type.
|
|
||||||
* param nextDesc Chain custom descriptor to transfer.
|
|
||||||
* note The data address and the data width must be consistent. For example, if the SRC
|
|
||||||
* is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in
|
|
||||||
* source address error(SAE).
|
|
||||||
*/
|
|
||||||
void DMA_PrepareTransfer(dma_transfer_config_t *config,
|
|
||||||
void *srcAddr,
|
|
||||||
void *dstAddr,
|
|
||||||
uint32_t byteWidth,
|
|
||||||
uint32_t transferBytes,
|
|
||||||
dma_transfer_type_t type,
|
|
||||||
void *nextDesc)
|
|
||||||
{
|
|
||||||
uint32_t xfer_count;
|
|
||||||
assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr));
|
|
||||||
assert((byteWidth == 1) || (byteWidth == 2) || (byteWidth == 4));
|
|
||||||
assert(((uint32_t)nextDesc & (DMA_LINK_DESCRIPTOR_ADDRESS_ALIGN - 1)) == 0U);
|
|
||||||
|
|
||||||
/* check max */
|
|
||||||
xfer_count = transferBytes / byteWidth;
|
|
||||||
assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0 == transferBytes % byteWidth));
|
|
||||||
|
|
||||||
memset(config, 0, sizeof(*config));
|
|
||||||
switch (type)
|
|
||||||
{
|
|
||||||
case kDMA_MemoryToMemory:
|
|
||||||
config->xfercfg.srcInc = 1;
|
|
||||||
config->xfercfg.dstInc = 1;
|
|
||||||
config->isPeriph = false;
|
|
||||||
break;
|
|
||||||
case kDMA_PeripheralToMemory:
|
|
||||||
/* Peripheral register - source doesn't increment */
|
|
||||||
config->xfercfg.srcInc = 0;
|
|
||||||
config->xfercfg.dstInc = 1;
|
|
||||||
config->isPeriph = true;
|
|
||||||
break;
|
|
||||||
case kDMA_MemoryToPeripheral:
|
|
||||||
/* Peripheral register - destination doesn't increment */
|
|
||||||
config->xfercfg.srcInc = 1;
|
|
||||||
config->xfercfg.dstInc = 0;
|
|
||||||
config->isPeriph = true;
|
|
||||||
break;
|
|
||||||
case kDMA_StaticToStatic:
|
|
||||||
config->xfercfg.srcInc = 0;
|
|
||||||
config->xfercfg.dstInc = 0;
|
|
||||||
config->isPeriph = true;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
config->dstAddr = (uint8_t *)dstAddr;
|
|
||||||
config->srcAddr = (uint8_t *)srcAddr;
|
|
||||||
config->nextDesc = (uint8_t *)nextDesc;
|
|
||||||
config->xfercfg.transferCount = xfer_count;
|
|
||||||
config->xfercfg.byteWidth = byteWidth;
|
|
||||||
config->xfercfg.intA = true;
|
|
||||||
config->xfercfg.reload = nextDesc != NULL;
|
|
||||||
config->xfercfg.valid = true;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief set channel config.
|
|
||||||
*
|
|
||||||
* This function provide a interface to configure channel configuration reisters.
|
|
||||||
*
|
|
||||||
* param base DMA base address.
|
|
||||||
* param channel DMA channel number.
|
|
||||||
* param config channel configurations structure.
|
|
||||||
*/
|
|
||||||
void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph)
|
|
||||||
{
|
|
||||||
assert(channel <= FSL_FEATURE_DMA_MAX_CHANNELS);
|
|
||||||
|
|
||||||
uint32_t tmp = DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
|
|
||||||
|
|
||||||
if (trigger != NULL)
|
|
||||||
{
|
|
||||||
tmp |= DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK |
|
|
||||||
DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK |
|
|
||||||
DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
tmp = base->CHANNEL[channel].CFG & (~tmp);
|
|
||||||
|
|
||||||
if (trigger != NULL)
|
|
||||||
{
|
|
||||||
tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap);
|
|
||||||
}
|
|
||||||
|
|
||||||
tmp |= DMA_CHANNEL_CFG_PERIPHREQEN(isPeriph);
|
|
||||||
|
|
||||||
base->CHANNEL[channel].CFG = tmp;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Prepare channel transfer configurations.
|
|
||||||
*
|
|
||||||
* This function used to prepare channel transfer configurations.
|
|
||||||
*
|
|
||||||
* param config Pointer to DMA channel transfer configuration structure.
|
|
||||||
* param srcStartAddr source start address.
|
|
||||||
* param dstStartAddr destination start address.
|
|
||||||
* param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value.
|
|
||||||
* param type transfer type.
|
|
||||||
* param trigger DMA channel trigger configurations.
|
|
||||||
* param nextDesc address of next descriptor.
|
|
||||||
*/
|
|
||||||
void DMA_PrepareChannelTransfer(dma_channel_config_t *config,
|
|
||||||
void *srcStartAddr,
|
|
||||||
void *dstStartAddr,
|
|
||||||
uint32_t xferCfg,
|
|
||||||
dma_transfer_type_t type,
|
|
||||||
dma_channel_trigger_t *trigger,
|
|
||||||
void *nextDesc)
|
|
||||||
{
|
|
||||||
assert((NULL != config) && (NULL != srcStartAddr) && (NULL != dstStartAddr));
|
|
||||||
assert(((uint32_t)nextDesc & (DMA_LINK_DESCRIPTOR_ADDRESS_ALIGN - 1)) == 0U);
|
|
||||||
|
|
||||||
/* check max */
|
|
||||||
memset(config, 0, sizeof(*config));
|
|
||||||
|
|
||||||
switch (type)
|
|
||||||
{
|
|
||||||
case kDMA_MemoryToMemory:
|
|
||||||
config->isPeriph = false;
|
|
||||||
break;
|
|
||||||
case kDMA_PeripheralToMemory:
|
|
||||||
config->isPeriph = true;
|
|
||||||
break;
|
|
||||||
case kDMA_MemoryToPeripheral:
|
|
||||||
config->isPeriph = true;
|
|
||||||
break;
|
|
||||||
case kDMA_StaticToStatic:
|
|
||||||
config->isPeriph = true;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
config->dstStartAddr = (uint8_t *)dstStartAddr;
|
|
||||||
config->srcStartAddr = (uint8_t *)srcStartAddr;
|
|
||||||
config->nextDesc = (uint8_t *)nextDesc;
|
|
||||||
config->trigger = trigger;
|
|
||||||
config->xferCfg = xferCfg;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Install DMA descriptor memory.
|
|
||||||
*
|
|
||||||
* This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong
|
|
||||||
* transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has
|
|
||||||
* a default DMA descriptor buffer, but it support one DMA descriptor for one channel only.
|
|
||||||
* User should be take care about the address of DMA descriptor pool which required align with 512BYTE.
|
|
||||||
*
|
|
||||||
* param handle Pointer to DMA channel transfer handle.
|
|
||||||
* param addr DMA descriptor address
|
|
||||||
* param num DMA descriptor number.
|
|
||||||
*/
|
|
||||||
void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr)
|
|
||||||
{
|
|
||||||
assert(addr != NULL);
|
|
||||||
assert(((uint32_t)addr & (FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE - 1U)) == 0U);
|
|
||||||
|
|
||||||
/* reconfigure the DMA descriptor base address */
|
|
||||||
base->SRAMBASE = (uint32_t)addr;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Submits the DMA channel transfer request.
|
|
||||||
*
|
|
||||||
* This function submits the DMA transfer request according to the transfer configuration structure.
|
|
||||||
* If the user submits the transfer request repeatedly, this function packs an unprocessed request as
|
|
||||||
* a TCD and enables scatter/gather feature to process it in the next time.
|
|
||||||
*
|
|
||||||
* param handle DMA handle pointer.
|
|
||||||
* param config Pointer to DMA transfer configuration structure.
|
|
||||||
* retval kStatus_DMA_Success It means submit transfer request succeed.
|
|
||||||
* retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
|
|
||||||
* retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later.
|
|
||||||
*/
|
|
||||||
status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config)
|
|
||||||
{
|
|
||||||
assert((NULL != handle) && (NULL != config));
|
|
||||||
assert(handle->channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base));
|
|
||||||
|
|
||||||
uint32_t instance = DMA_GetInstance(handle->base);
|
|
||||||
dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]);
|
|
||||||
|
|
||||||
/* Previous transfer has not finished */
|
|
||||||
if (DMA_ChannelIsActive(handle->base, handle->channel))
|
|
||||||
{
|
|
||||||
return kStatus_DMA_Busy;
|
|
||||||
}
|
|
||||||
|
|
||||||
DMA_SetupDescriptor(descriptor, config->xferCfg, config->srcStartAddr, config->dstStartAddr, config->nextDesc);
|
|
||||||
DMA_SetChannelConfig(handle->base, handle->channel, config->trigger, config->isPeriph);
|
|
||||||
/* Set channel XFERCFG register according first channel descriptor. */
|
|
||||||
handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg;
|
|
||||||
|
|
||||||
return kStatus_Success;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Submits the DMA transfer request.
|
|
||||||
* deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer.
|
|
||||||
*
|
|
||||||
* This function submits the DMA transfer request according to the transfer configuration structure.
|
|
||||||
* If the user submits the transfer request repeatedly, this function packs an unprocessed request as
|
|
||||||
* a TCD and enables scatter/gather feature to process it in the next time.
|
|
||||||
*
|
|
||||||
* param handle DMA handle pointer.
|
|
||||||
* param config Pointer to DMA transfer configuration structure.
|
|
||||||
* retval kStatus_DMA_Success It means submit transfer request succeed.
|
|
||||||
* retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
|
|
||||||
* retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later.
|
|
||||||
*/
|
|
||||||
status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config)
|
|
||||||
{
|
|
||||||
assert((NULL != handle) && (NULL != config));
|
|
||||||
assert(handle->channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base));
|
|
||||||
|
|
||||||
uint32_t instance = DMA_GetInstance(handle->base);
|
|
||||||
dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]);
|
|
||||||
|
|
||||||
/* Previous transfer has not finished */
|
|
||||||
if (DMA_ChannelIsActive(handle->base, handle->channel))
|
|
||||||
{
|
|
||||||
return kStatus_DMA_Busy;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* enable/disable peripheral request */
|
|
||||||
if (config->isPeriph)
|
|
||||||
{
|
|
||||||
DMA_EnableChannelPeriphRq(handle->base, handle->channel);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
DMA_DisableChannelPeriphRq(handle->base, handle->channel);
|
|
||||||
}
|
|
||||||
|
|
||||||
DMA_CreateDescriptor(descriptor, &config->xfercfg, config->srcAddr, config->dstAddr, config->nextDesc);
|
|
||||||
/* Set channel XFERCFG register according first channel descriptor. */
|
|
||||||
handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg;
|
|
||||||
|
|
||||||
return kStatus_Success;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief DMA start transfer.
|
|
||||||
*
|
|
||||||
* This function enables the channel request. User can call this function after submitting the transfer request
|
|
||||||
* or before submitting the transfer request.
|
|
||||||
*
|
|
||||||
* param handle DMA handle pointer.
|
|
||||||
*/
|
|
||||||
void DMA_StartTransfer(dma_handle_t *handle)
|
|
||||||
{
|
|
||||||
assert(NULL != handle);
|
|
||||||
|
|
||||||
uint32_t channel = handle->channel;
|
|
||||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base));
|
|
||||||
|
|
||||||
/* enable channel */
|
|
||||||
DMA_EnableChannel(handle->base, channel);
|
|
||||||
|
|
||||||
/* user software trigger if Peripheral request not enabled */
|
|
||||||
if (((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_TRIGBURST_MASK) != 0U) ||
|
|
||||||
((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_TRIGTYPE_MASK) != DMA_CHANNEL_CFG_TRIGTYPE(1U)))
|
|
||||||
{
|
|
||||||
handle->base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void DMA_IRQHandle(DMA_Type *base)
|
|
||||||
{
|
|
||||||
dma_handle_t *handle;
|
|
||||||
int32_t channel_index;
|
|
||||||
uint32_t startChannel = DMA_GetVirtualStartChannel(base);
|
|
||||||
uint32_t i = 0;
|
|
||||||
|
|
||||||
/* Find channels that have completed transfer */
|
|
||||||
for (i = 0; i < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++)
|
|
||||||
{
|
|
||||||
handle = s_DMAHandle[i + startChannel];
|
|
||||||
/* Handle is not present */
|
|
||||||
if (NULL == handle)
|
|
||||||
{
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
channel_index = DMA_CHANNEL_INDEX(handle->channel);
|
|
||||||
/* Channel uses INTA flag */
|
|
||||||
if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1U << channel_index))
|
|
||||||
{
|
|
||||||
/* Clear INTA flag */
|
|
||||||
DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1U << channel_index));
|
|
||||||
if (handle->callback)
|
|
||||||
{
|
|
||||||
(handle->callback)(handle, handle->userData, true, kDMA_IntA);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* Channel uses INTB flag */
|
|
||||||
if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1U << channel_index))
|
|
||||||
{
|
|
||||||
/* Clear INTB flag */
|
|
||||||
DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1U << channel_index));
|
|
||||||
if (handle->callback)
|
|
||||||
{
|
|
||||||
(handle->callback)(handle, handle->userData, true, kDMA_IntB);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* Error flag */
|
|
||||||
if (DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1U << channel_index))
|
|
||||||
{
|
|
||||||
/* Clear error flag */
|
|
||||||
DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1U << channel_index));
|
|
||||||
if (handle->callback)
|
|
||||||
{
|
|
||||||
(handle->callback)(handle, handle->userData, false, kDMA_IntError);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void DMA0_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
DMA_IRQHandle(DMA0);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(DMA1)
|
|
||||||
void DMA1_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
DMA_IRQHandle(DMA1);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,649 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _FSL_DMA_H_
|
|
||||||
#define _FSL_DMA_H_
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup dma
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @file */
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
/*! @brief DMA driver version */
|
|
||||||
#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1. */
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
#define DMA_MAX_TRANSFER_COUNT 0x400
|
|
||||||
|
|
||||||
#if defined FSL_FEATURE_DMA_NUMBER_OF_CHANNELS
|
|
||||||
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) FSL_FEATURE_DMA_NUMBER_OF_CHANNELS
|
|
||||||
#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS
|
|
||||||
#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT)
|
|
||||||
#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Channel group consists of 32 channels. channel_group = (channel / 32) */
|
|
||||||
#define DMA_CHANNEL_GROUP(channel) (((uint8_t)(channel)) >> 5U)
|
|
||||||
/* Channel index in channel group. channel_index = (channel % 32) */
|
|
||||||
#define DMA_CHANNEL_INDEX(channel) (((uint8_t)(channel)) & 0x1F)
|
|
||||||
/*! @brief DMA linked descriptor address algin size */
|
|
||||||
#define DMA_LINK_DESCRIPTOR_ADDRESS_ALIGN (16)
|
|
||||||
#define DMA_COMMON_REG_GET(base, channel, reg) \
|
|
||||||
(((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)])
|
|
||||||
#define DMA_COMMON_CONST_REG_GET(base, channel, reg) \
|
|
||||||
(((volatile const uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)])
|
|
||||||
#define DMA_COMMON_REG_SET(base, channel, reg, value) \
|
|
||||||
(((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value))
|
|
||||||
|
|
||||||
/*! @brief DMA descriptor end address calculate
|
|
||||||
* @param start, start address
|
|
||||||
* @param inc, address interleave size
|
|
||||||
* @param bytes, transfer bytes
|
|
||||||
* @param width, transfer width
|
|
||||||
*/
|
|
||||||
#define DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) ((void *)((uint32_t)(start) + inc * bytes - inc * width))
|
|
||||||
|
|
||||||
/*! @brief DMA channel transfer configurations macro
|
|
||||||
* @param reload, true is reload link descriptor after current exhaust, false is not
|
|
||||||
* @param clrTrig, true is clear trigger status, wait software trigger, false is not
|
|
||||||
* @param intA, enable interruptA
|
|
||||||
* @param intB, enable interruptB
|
|
||||||
* @param width,transfer width
|
|
||||||
* @param srcInc, source address interleave size
|
|
||||||
* @param dstInc, destination address interleave size
|
|
||||||
* @param bytes, transfer bytes
|
|
||||||
*/
|
|
||||||
#define DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes) \
|
|
||||||
DMA_CHANNEL_XFERCFG_CFGVALID_MASK | DMA_CHANNEL_XFERCFG_RELOAD(reload) | DMA_CHANNEL_XFERCFG_CLRTRIG(clrTrig) | \
|
|
||||||
DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) | \
|
|
||||||
DMA_CHANNEL_XFERCFG_WIDTH(width == 4 ? 2 : (width - 1)) | \
|
|
||||||
DMA_CHANNEL_XFERCFG_SRCINC(srcInc == 4 ? (srcInc - 1) : srcInc) | \
|
|
||||||
DMA_CHANNEL_XFERCFG_DSTINC(dstInc == 4 ? (srcInc - 1) : dstInc) | \
|
|
||||||
DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1)
|
|
||||||
|
|
||||||
/*! @brief DMA transfer status */
|
|
||||||
enum _dma_transfer_status
|
|
||||||
{
|
|
||||||
kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the
|
|
||||||
transfer request. */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*! @brief dma address interleave size */
|
|
||||||
enum _dma_addr_interleave_size
|
|
||||||
{
|
|
||||||
kDMA_AddressInterleave0xWidth = 0U, /*!< dma source/destination address no interleave */
|
|
||||||
kDMA_AddressInterleave1xWidth = 1U, /*!< dma source/destination address interleave 1xwidth */
|
|
||||||
kDMA_AddressInterleave2xWidth = 2U, /*!< dma source/destination address interleave 2xwidth */
|
|
||||||
kDMA_AddressInterleave4xWidth = 4U, /*!< dma source/destination address interleave 3xwidth */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*! @brief dma transfer width */
|
|
||||||
enum _dma_transfer_width
|
|
||||||
{
|
|
||||||
kDMA_Transfer8BitWidth = 1U, /*!< dma channel transfer bit width is 8 bit */
|
|
||||||
kDMA_Transfer16BitWidth = 2U, /*!< dma channel transfer bit width is 16 bit */
|
|
||||||
kDMA_Transfer32BitWidth = 4U, /*!< dma channel transfer bit width is 32 bit */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*! @brief DMA descriptor structure */
|
|
||||||
typedef struct _dma_descriptor
|
|
||||||
{
|
|
||||||
volatile uint32_t xfercfg; /*!< Transfer configuration */
|
|
||||||
void *srcEndAddr; /*!< Last source address of DMA transfer */
|
|
||||||
void *dstEndAddr; /*!< Last destination address of DMA transfer */
|
|
||||||
void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */
|
|
||||||
} dma_descriptor_t;
|
|
||||||
|
|
||||||
/*! @brief DMA transfer configuration */
|
|
||||||
typedef struct _dma_xfercfg
|
|
||||||
{
|
|
||||||
bool valid; /*!< Descriptor is ready to transfer */
|
|
||||||
bool reload; /*!< Reload channel configuration register after
|
|
||||||
current descriptor is exhausted */
|
|
||||||
bool swtrig; /*!< Perform software trigger. Transfer if fired
|
|
||||||
when 'valid' is set */
|
|
||||||
bool clrtrig; /*!< Clear trigger */
|
|
||||||
bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */
|
|
||||||
bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */
|
|
||||||
uint8_t byteWidth; /*!< Byte width of data to transfer */
|
|
||||||
uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */
|
|
||||||
uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */
|
|
||||||
uint16_t transferCount; /*!< Number of transfers */
|
|
||||||
} dma_xfercfg_t;
|
|
||||||
|
|
||||||
/*! @brief DMA channel priority */
|
|
||||||
typedef enum _dma_priority
|
|
||||||
{
|
|
||||||
kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */
|
|
||||||
kDMA_ChannelPriority1, /*!< Channel priority 1 */
|
|
||||||
kDMA_ChannelPriority2, /*!< Channel priority 2 */
|
|
||||||
kDMA_ChannelPriority3, /*!< Channel priority 3 */
|
|
||||||
kDMA_ChannelPriority4, /*!< Channel priority 4 */
|
|
||||||
kDMA_ChannelPriority5, /*!< Channel priority 5 */
|
|
||||||
kDMA_ChannelPriority6, /*!< Channel priority 6 */
|
|
||||||
kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */
|
|
||||||
} dma_priority_t;
|
|
||||||
|
|
||||||
/*! @brief DMA interrupt flags */
|
|
||||||
typedef enum _dma_int
|
|
||||||
{
|
|
||||||
kDMA_IntA, /*!< DMA interrupt flag A */
|
|
||||||
kDMA_IntB, /*!< DMA interrupt flag B */
|
|
||||||
kDMA_IntError, /*!< DMA interrupt flag error */
|
|
||||||
} dma_irq_t;
|
|
||||||
|
|
||||||
/*! @brief DMA trigger type*/
|
|
||||||
typedef enum _dma_trigger_type
|
|
||||||
{
|
|
||||||
kDMA_NoTrigger = 0, /*!< Trigger is disabled */
|
|
||||||
kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */
|
|
||||||
kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) |
|
|
||||||
DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */
|
|
||||||
kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */
|
|
||||||
kDMA_RisingEdgeTrigger =
|
|
||||||
DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */
|
|
||||||
} dma_trigger_type_t;
|
|
||||||
|
|
||||||
/*! @brief DMA trigger burst */
|
|
||||||
typedef enum _dma_trigger_burst
|
|
||||||
{
|
|
||||||
kDMA_SingleTransfer = 0, /*!< Single transfer */
|
|
||||||
kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */
|
|
||||||
kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */
|
|
||||||
kDMA_EdgeBurstTransfer2 =
|
|
||||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */
|
|
||||||
kDMA_EdgeBurstTransfer4 =
|
|
||||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */
|
|
||||||
kDMA_EdgeBurstTransfer8 =
|
|
||||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */
|
|
||||||
kDMA_EdgeBurstTransfer16 =
|
|
||||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */
|
|
||||||
kDMA_EdgeBurstTransfer32 =
|
|
||||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */
|
|
||||||
kDMA_EdgeBurstTransfer64 =
|
|
||||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */
|
|
||||||
kDMA_EdgeBurstTransfer128 =
|
|
||||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */
|
|
||||||
kDMA_EdgeBurstTransfer256 =
|
|
||||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */
|
|
||||||
kDMA_EdgeBurstTransfer512 =
|
|
||||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */
|
|
||||||
kDMA_EdgeBurstTransfer1024 =
|
|
||||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */
|
|
||||||
} dma_trigger_burst_t;
|
|
||||||
|
|
||||||
/*! @brief DMA burst wrapping */
|
|
||||||
typedef enum _dma_burst_wrap
|
|
||||||
{
|
|
||||||
kDMA_NoWrap = 0, /*!< Wrapping is disabled */
|
|
||||||
kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */
|
|
||||||
kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */
|
|
||||||
kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) |
|
|
||||||
DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */
|
|
||||||
} dma_burst_wrap_t;
|
|
||||||
|
|
||||||
/*! @brief DMA transfer type */
|
|
||||||
typedef enum _dma_transfer_type
|
|
||||||
{
|
|
||||||
kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */
|
|
||||||
kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */
|
|
||||||
kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/
|
|
||||||
kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */
|
|
||||||
} dma_transfer_type_t;
|
|
||||||
|
|
||||||
/*! @brief DMA channel trigger */
|
|
||||||
typedef struct _dma_channel_trigger
|
|
||||||
{
|
|
||||||
dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */
|
|
||||||
dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */
|
|
||||||
dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */
|
|
||||||
} dma_channel_trigger_t;
|
|
||||||
|
|
||||||
/*! @brief DMA channel trigger */
|
|
||||||
typedef struct _dma_channel_config
|
|
||||||
{
|
|
||||||
void *srcStartAddr; /*!< Source data address */
|
|
||||||
void *dstStartAddr; /*!< Destination data address */
|
|
||||||
void *nextDesc; /*!< Chain custom descriptor */
|
|
||||||
uint32_t xferCfg; /*!< channel transfer configurations */
|
|
||||||
dma_channel_trigger_t *trigger; /*!< DMA trigger type */
|
|
||||||
bool isPeriph; /*!< select the request type */
|
|
||||||
} dma_channel_config_t;
|
|
||||||
|
|
||||||
/*! @brief DMA transfer configuration */
|
|
||||||
typedef struct _dma_transfer_config
|
|
||||||
{
|
|
||||||
uint8_t *srcAddr; /*!< Source data address */
|
|
||||||
uint8_t *dstAddr; /*!< Destination data address */
|
|
||||||
uint8_t *nextDesc; /*!< Chain custom descriptor */
|
|
||||||
dma_xfercfg_t xfercfg; /*!< Transfer options */
|
|
||||||
bool isPeriph; /*!< DMA transfer is driven by peripheral */
|
|
||||||
} dma_transfer_config_t;
|
|
||||||
|
|
||||||
/*! @brief Callback for DMA */
|
|
||||||
struct _dma_handle;
|
|
||||||
|
|
||||||
/*! @brief Define Callback function for DMA. */
|
|
||||||
typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode);
|
|
||||||
|
|
||||||
/*! @brief DMA transfer handle structure */
|
|
||||||
typedef struct _dma_handle
|
|
||||||
{
|
|
||||||
dma_callback callback; /*!< Callback function. Invoked when transfer
|
|
||||||
of descriptor with interrupt flag finishes */
|
|
||||||
void *userData; /*!< Callback function parameter */
|
|
||||||
DMA_Type *base; /*!< DMA peripheral base address */
|
|
||||||
uint8_t channel; /*!< DMA channel number */
|
|
||||||
} dma_handle_t;
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* APIs
|
|
||||||
******************************************************************************/
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name DMA initialization and De-initialization
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initializes DMA peripheral.
|
|
||||||
*
|
|
||||||
* This function enable the DMA clock, set descriptor table and
|
|
||||||
* enable DMA peripheral.
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
*/
|
|
||||||
void DMA_Init(DMA_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Deinitializes DMA peripheral.
|
|
||||||
*
|
|
||||||
* This function gates the DMA clock.
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
*/
|
|
||||||
void DMA_Deinit(DMA_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Install DMA descriptor memory.
|
|
||||||
*
|
|
||||||
* This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong
|
|
||||||
* transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has
|
|
||||||
* a default DMA descriptor buffer, but it support one DMA descriptor for one channel only.
|
|
||||||
*
|
|
||||||
* @param base DMA base address.
|
|
||||||
* @param addr DMA descriptor address
|
|
||||||
*/
|
|
||||||
void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr);
|
|
||||||
|
|
||||||
/* @} */
|
|
||||||
/*!
|
|
||||||
* @name DMA Channel Operation
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Return whether DMA channel is processing transfer
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
* @param channel DMA channel number.
|
|
||||||
* @return True for active state, false otherwise.
|
|
||||||
*/
|
|
||||||
static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
|
|
||||||
return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enables the interrupt source for the DMA transfer.
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
* @param channel DMA channel number.
|
|
||||||
*/
|
|
||||||
static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
|
|
||||||
DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1U << DMA_CHANNEL_INDEX(channel);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Disables the interrupt source for the DMA transfer.
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
* @param channel DMA channel number.
|
|
||||||
*/
|
|
||||||
static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
|
|
||||||
DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1U << DMA_CHANNEL_INDEX(channel);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enable DMA channel.
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
* @param channel DMA channel number.
|
|
||||||
*/
|
|
||||||
static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
|
|
||||||
DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1U << DMA_CHANNEL_INDEX(channel);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Disable DMA channel.
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
* @param channel DMA channel number.
|
|
||||||
*/
|
|
||||||
static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
|
|
||||||
DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1U << DMA_CHANNEL_INDEX(channel);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set PERIPHREQEN of channel configuration register.
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
* @param channel DMA channel number.
|
|
||||||
*/
|
|
||||||
static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
|
|
||||||
base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get PERIPHREQEN value of channel configuration register.
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
* @param channel DMA channel number.
|
|
||||||
* @return True for enabled PeriphRq, false for disabled.
|
|
||||||
*/
|
|
||||||
static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
|
|
||||||
base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set trigger settings of DMA channel.
|
|
||||||
* @deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig.
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
* @param channel DMA channel number.
|
|
||||||
* @param trigger trigger configuration.
|
|
||||||
*/
|
|
||||||
void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief set channel config.
|
|
||||||
*
|
|
||||||
* This function provide a interface to configure channel configuration reisters.
|
|
||||||
*
|
|
||||||
* @param base DMA base address.
|
|
||||||
* @param channel DMA channel number.
|
|
||||||
* @param trigger channel configurations structure.
|
|
||||||
* @param isPeriph true is periph request, false is not.
|
|
||||||
*/
|
|
||||||
void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Gets the remaining bytes of the current DMA descriptor transfer.
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
* @param channel DMA channel number.
|
|
||||||
* @return The number of bytes which have not been transferred yet.
|
|
||||||
*/
|
|
||||||
uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set priority of channel configuration register.
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
* @param channel DMA channel number.
|
|
||||||
* @param priority Channel priority value.
|
|
||||||
*/
|
|
||||||
static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
|
|
||||||
base->CHANNEL[channel].CFG =
|
|
||||||
(base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get priority of channel configuration register.
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
* @param channel DMA channel number.
|
|
||||||
* @return Channel priority value.
|
|
||||||
*/
|
|
||||||
static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
|
|
||||||
return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >>
|
|
||||||
DMA_CHANNEL_CFG_CHPRIORITY_SHIFT);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set channel configuration valid..
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
* @param channel DMA channel number.
|
|
||||||
*/
|
|
||||||
static inline void DMA_SetChannelConfigValid(DMA_Type *base, uint32_t channel)
|
|
||||||
{
|
|
||||||
base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_CFGVALID_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Do software trigger for the channel.
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
* @param channel DMA channel number.
|
|
||||||
*/
|
|
||||||
static inline void DMA_DoChannelSoftwareTrigger(DMA_Type *base, uint32_t channel)
|
|
||||||
{
|
|
||||||
base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Load channel transfer configurations.
|
|
||||||
*
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
* @param channel DMA channel number.
|
|
||||||
* @param xfer transfer configurations.
|
|
||||||
*/
|
|
||||||
static inline void DMA_LoadChannelTransferConfig(DMA_Type *base, uint32_t channel, uint32_t xfer)
|
|
||||||
{
|
|
||||||
base->CHANNEL[channel].XFERCFG = xfer;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Create application specific DMA descriptor
|
|
||||||
* to be used in a chain in transfer
|
|
||||||
* @deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor.
|
|
||||||
* @param desc DMA descriptor address.
|
|
||||||
* @param xfercfg Transfer configuration for DMA descriptor.
|
|
||||||
* @param srcAddr Address of last item to transmit
|
|
||||||
* @param dstAddr Address of last item to receive.
|
|
||||||
* @param nextDesc Address of next descriptor in chain.
|
|
||||||
*/
|
|
||||||
void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief setup dma descriptor
|
|
||||||
*
|
|
||||||
* @param desc DMA descriptor address.
|
|
||||||
* @param xfercfg Transfer configuration for DMA descriptor.
|
|
||||||
* @param srcStartAddr Start address of source address.
|
|
||||||
* @param dstStartAddr Start address of destination address.
|
|
||||||
* @param nextDesc Address of next descriptor in chain.
|
|
||||||
*/
|
|
||||||
void DMA_SetupDescriptor(
|
|
||||||
dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc);
|
|
||||||
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name DMA Transactional Operation
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Abort running transfer by handle.
|
|
||||||
*
|
|
||||||
* This function aborts DMA transfer specified by handle.
|
|
||||||
*
|
|
||||||
* @param handle DMA handle pointer.
|
|
||||||
*/
|
|
||||||
void DMA_AbortTransfer(dma_handle_t *handle);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Creates the DMA handle.
|
|
||||||
*
|
|
||||||
* This function is called if using transaction API for DMA. This function
|
|
||||||
* initializes the internal state of DMA handle.
|
|
||||||
*
|
|
||||||
* @param handle DMA handle pointer. The DMA handle stores callback function and
|
|
||||||
* parameters.
|
|
||||||
* @param base DMA peripheral base address.
|
|
||||||
* @param channel DMA channel number.
|
|
||||||
*/
|
|
||||||
void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Installs a callback function for the DMA transfer.
|
|
||||||
*
|
|
||||||
* This callback is called in DMA IRQ handler. Use the callback to do something after
|
|
||||||
* the current major loop transfer completes.
|
|
||||||
*
|
|
||||||
* @param handle DMA handle pointer.
|
|
||||||
* @param callback DMA callback function pointer.
|
|
||||||
* @param userData Parameter for callback function.
|
|
||||||
*/
|
|
||||||
void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Prepares the DMA transfer structure.
|
|
||||||
* @deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer.
|
|
||||||
* This function prepares the transfer configuration structure according to the user input.
|
|
||||||
*
|
|
||||||
* @param config The user configuration structure of type dma_transfer_t.
|
|
||||||
* @param srcAddr DMA transfer source address.
|
|
||||||
* @param dstAddr DMA transfer destination address.
|
|
||||||
* @param byteWidth DMA transfer destination address width(bytes).
|
|
||||||
* @param transferBytes DMA transfer bytes to be transferred.
|
|
||||||
* @param type DMA transfer type.
|
|
||||||
* @param nextDesc Chain custom descriptor to transfer.
|
|
||||||
* @note The data address and the data width must be consistent. For example, if the SRC
|
|
||||||
* is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in
|
|
||||||
* source address error(SAE).
|
|
||||||
*/
|
|
||||||
void DMA_PrepareTransfer(dma_transfer_config_t *config,
|
|
||||||
void *srcAddr,
|
|
||||||
void *dstAddr,
|
|
||||||
uint32_t byteWidth,
|
|
||||||
uint32_t transferBytes,
|
|
||||||
dma_transfer_type_t type,
|
|
||||||
void *nextDesc);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Prepare channel transfer configurations.
|
|
||||||
*
|
|
||||||
* This function used to prepare channel transfer configurations.
|
|
||||||
*
|
|
||||||
* @param config Pointer to DMA channel transfer configuration structure.
|
|
||||||
* @param srcStartAddr source start address.
|
|
||||||
* @param dstStartAddr destination start address.
|
|
||||||
* @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value.
|
|
||||||
* @param type transfer type.
|
|
||||||
* @param trigger DMA channel trigger configurations.
|
|
||||||
* @param nextDesc address of next descriptor.
|
|
||||||
*/
|
|
||||||
void DMA_PrepareChannelTransfer(dma_channel_config_t *config,
|
|
||||||
void *srcStartAddr,
|
|
||||||
void *dstStartAddr,
|
|
||||||
uint32_t xferCfg,
|
|
||||||
dma_transfer_type_t type,
|
|
||||||
dma_channel_trigger_t *trigger,
|
|
||||||
void *nextDesc);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Submits the DMA transfer request.
|
|
||||||
* @deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer.
|
|
||||||
*
|
|
||||||
* This function submits the DMA transfer request according to the transfer configuration structure.
|
|
||||||
* If the user submits the transfer request repeatedly, this function packs an unprocessed request as
|
|
||||||
* a TCD and enables scatter/gather feature to process it in the next time.
|
|
||||||
*
|
|
||||||
* @param handle DMA handle pointer.
|
|
||||||
* @param config Pointer to DMA transfer configuration structure.
|
|
||||||
* @retval kStatus_DMA_Success It means submit transfer request succeed.
|
|
||||||
* @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
|
|
||||||
* @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later.
|
|
||||||
*/
|
|
||||||
status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Submits the DMA channel transfer request.
|
|
||||||
*
|
|
||||||
* This function submits the DMA transfer request according to the transfer configuration structure.
|
|
||||||
* If the user submits the transfer request repeatedly, this function packs an unprocessed request as
|
|
||||||
* a TCD and enables scatter/gather feature to process it in the next time.
|
|
||||||
* This function should use together with DMA_PrepareChannelTransfer.
|
|
||||||
*
|
|
||||||
* @param handle DMA handle pointer.
|
|
||||||
* @param config Pointer to DMA channel transfer configuration structure.
|
|
||||||
* @retval kStatus_DMA_Success It means submit transfer request succeed.
|
|
||||||
* @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
|
|
||||||
* @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later.
|
|
||||||
*/
|
|
||||||
status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief DMA start transfer.
|
|
||||||
*
|
|
||||||
* This function enables the channel request. User can call this function after submitting the transfer request
|
|
||||||
* or before submitting the transfer request.
|
|
||||||
*
|
|
||||||
* @param handle DMA handle pointer.
|
|
||||||
*/
|
|
||||||
void DMA_StartTransfer(dma_handle_t *handle);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief DMA IRQ handler for descriptor transfer complete.
|
|
||||||
*
|
|
||||||
* This function clears the channel major interrupt flag and call
|
|
||||||
* the callback function if it is not NULL.
|
|
||||||
*/
|
|
||||||
void DMA_HandleIRQ(void);
|
|
||||||
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
#endif /*_FSL_DMA_H_*/
|
|
||||||
|
|
@ -1,335 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
#include "fsl_flexcomm.h"
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.flexcomm"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Prototypes
|
|
||||||
******************************************************************************/
|
|
||||||
/*! @brief Set the FLEXCOMM mode . */
|
|
||||||
static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock);
|
|
||||||
|
|
||||||
/*! @brief check whether flexcomm supports peripheral type */
|
|
||||||
static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph);
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
|
|
||||||
static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
|
|
||||||
|
|
||||||
/*! @brief Pointers to handles for each instance to provide context to interrupt routines */
|
|
||||||
static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
|
|
||||||
|
|
||||||
/*! @brief Array to map FLEXCOMM instance number to IRQ number. */
|
|
||||||
IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS;
|
|
||||||
|
|
||||||
/*! @brief Array to map FLEXCOMM instance number to base address. */
|
|
||||||
static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS;
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/*! @brief IDs of clock for each FLEXCOMM module */
|
|
||||||
static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS;
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)
|
|
||||||
/*! @brief Pointers to FLEXCOMM resets for each instance. */
|
|
||||||
static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/* check whether flexcomm supports peripheral type */
|
|
||||||
static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph)
|
|
||||||
{
|
|
||||||
if (periph == FLEXCOMM_PERIPH_NONE)
|
|
||||||
{
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
else if (periph <= FLEXCOMM_PERIPH_I2S_TX)
|
|
||||||
{
|
|
||||||
return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > (uint32_t)0 ? true : false;
|
|
||||||
}
|
|
||||||
else if (periph == FLEXCOMM_PERIPH_I2S_RX)
|
|
||||||
{
|
|
||||||
return (base->PSELID & (1 << 7)) > (uint32_t)0 ? true : false;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get the index corresponding to the FLEXCOMM */
|
|
||||||
/*! brief Returns instance number for FLEXCOMM module with given base address. */
|
|
||||||
uint32_t FLEXCOMM_GetInstance(void *base)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
|
|
||||||
for (i = 0; i < FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++)
|
|
||||||
{
|
|
||||||
if ((uint32_t)base == s_flexcommBaseAddrs[i])
|
|
||||||
{
|
|
||||||
return i;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
assert(false);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Changes FLEXCOMM mode */
|
|
||||||
static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock)
|
|
||||||
{
|
|
||||||
/* Check whether peripheral type is present */
|
|
||||||
if (!FLEXCOMM_PeripheralIsPresent(base, periph))
|
|
||||||
{
|
|
||||||
return kStatus_OutOfRange;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Flexcomm is locked to different peripheral type than expected */
|
|
||||||
if ((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) && ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != periph))
|
|
||||||
{
|
|
||||||
return kStatus_Fail;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Check if we are asked to lock */
|
|
||||||
if (lock)
|
|
||||||
{
|
|
||||||
base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
base->PSELID = (uint32_t)periph;
|
|
||||||
}
|
|
||||||
|
|
||||||
return kStatus_Success;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
|
|
||||||
status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph)
|
|
||||||
{
|
|
||||||
int idx = FLEXCOMM_GetInstance(base);
|
|
||||||
|
|
||||||
if (idx < 0)
|
|
||||||
{
|
|
||||||
return kStatus_InvalidArgument;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Enable the peripheral clock */
|
|
||||||
CLOCK_EnableClock(s_flexcommClocks[idx]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)
|
|
||||||
/* Reset the FLEXCOMM module */
|
|
||||||
RESET_PeripheralReset(s_flexcommResets[idx]);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Set the FLEXCOMM to given peripheral */
|
|
||||||
return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
|
|
||||||
* mode */
|
|
||||||
void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle)
|
|
||||||
{
|
|
||||||
uint32_t instance;
|
|
||||||
|
|
||||||
/* Look up instance number */
|
|
||||||
instance = FLEXCOMM_GetInstance(base);
|
|
||||||
|
|
||||||
/* Clear handler first to avoid execution of the handler with wrong handle */
|
|
||||||
s_flexcommIrqHandler[instance] = NULL;
|
|
||||||
s_flexcommHandle[instance] = handle;
|
|
||||||
s_flexcommIrqHandler[instance] = handler;
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/* IRQ handler functions overloading weak symbols in the startup */
|
|
||||||
#if defined(FLEXCOMM0)
|
|
||||||
void FLEXCOMM0_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
assert(s_flexcommIrqHandler[0]);
|
|
||||||
s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(FLEXCOMM1)
|
|
||||||
void FLEXCOMM1_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
assert(s_flexcommIrqHandler[1]);
|
|
||||||
s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(FLEXCOMM2)
|
|
||||||
void FLEXCOMM2_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
assert(s_flexcommIrqHandler[2]);
|
|
||||||
s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(FLEXCOMM3)
|
|
||||||
void FLEXCOMM3_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
assert(s_flexcommIrqHandler[3]);
|
|
||||||
s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(FLEXCOMM4)
|
|
||||||
void FLEXCOMM4_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
assert(s_flexcommIrqHandler[4]);
|
|
||||||
s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(FLEXCOMM5)
|
|
||||||
void FLEXCOMM5_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
assert(s_flexcommIrqHandler[5]);
|
|
||||||
s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(FLEXCOMM6)
|
|
||||||
void FLEXCOMM6_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
assert(s_flexcommIrqHandler[6]);
|
|
||||||
s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(FLEXCOMM7)
|
|
||||||
void FLEXCOMM7_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
assert(s_flexcommIrqHandler[7]);
|
|
||||||
s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(FLEXCOMM8)
|
|
||||||
void FLEXCOMM8_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
assert(s_flexcommIrqHandler[8]);
|
|
||||||
s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(FLEXCOMM9)
|
|
||||||
void FLEXCOMM9_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
assert(s_flexcommIrqHandler[9]);
|
|
||||||
s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(FLEXCOMM14)
|
|
||||||
void FLEXCOMM14_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
uint32_t instance;
|
|
||||||
|
|
||||||
/* Look up instance number */
|
|
||||||
instance = FLEXCOMM_GetInstance(FLEXCOMM14);
|
|
||||||
assert(s_flexcommIrqHandler[instance]);
|
|
||||||
s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(FLEXCOMM15)
|
|
||||||
void FLEXCOMM15_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
uint32_t instance;
|
|
||||||
|
|
||||||
/* Look up instance number */
|
|
||||||
instance = FLEXCOMM_GetInstance(FLEXCOMM14);
|
|
||||||
assert(s_flexcommIrqHandler[instance]);
|
|
||||||
s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,53 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
#ifndef _FSL_FLEXCOMM_H_
|
|
||||||
#define _FSL_FLEXCOMM_H_
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup flexcomm_driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
/*! @brief FlexCOMM driver version 2.0.0. */
|
|
||||||
#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*! @brief FLEXCOMM peripheral modes. */
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
FLEXCOMM_PERIPH_NONE, /*!< No peripheral */
|
|
||||||
FLEXCOMM_PERIPH_USART, /*!< USART peripheral */
|
|
||||||
FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */
|
|
||||||
FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */
|
|
||||||
FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */
|
|
||||||
FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */
|
|
||||||
} FLEXCOMM_PERIPH_T;
|
|
||||||
|
|
||||||
/*! @brief Typedef for interrupt handler. */
|
|
||||||
typedef void (*flexcomm_irq_handler_t)(void *base, void *handle);
|
|
||||||
|
|
||||||
/*! @brief Array with IRQ number for each FLEXCOMM module. */
|
|
||||||
extern IRQn_Type const kFlexcommIrqs[];
|
|
||||||
|
|
||||||
/*! @brief Returns instance number for FLEXCOMM module with given base address. */
|
|
||||||
uint32_t FLEXCOMM_GetInstance(void *base);
|
|
||||||
|
|
||||||
/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
|
|
||||||
status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);
|
|
||||||
|
|
||||||
/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
|
|
||||||
* mode */
|
|
||||||
void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle);
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
#endif /* _FSL_FLEXCOMM_H_*/
|
|
||||||
|
|
@ -1,392 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "fsl_gint.h"
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.gint"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables
|
|
||||||
******************************************************************************/
|
|
||||||
/*! @brief Pointers to GINT bases for each instance. */
|
|
||||||
static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS;
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/*! @brief Clocks for each instance. */
|
|
||||||
static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS;
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
||||||
/*! @brief Resets for each instance. */
|
|
||||||
static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS;
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
||||||
|
|
||||||
/* @brief Irq number for each instance */
|
|
||||||
static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS;
|
|
||||||
|
|
||||||
/*! @brief Callback function array for GINT(s). */
|
|
||||||
static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT];
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
static uint32_t GINT_GetInstance(GINT_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t instance;
|
|
||||||
|
|
||||||
/* Find the instance index from base address mappings. */
|
|
||||||
for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++)
|
|
||||||
{
|
|
||||||
if (s_gintBases[instance] == base)
|
|
||||||
{
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
assert(instance < ARRAY_SIZE(s_gintBases));
|
|
||||||
|
|
||||||
return instance;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Initialize GINT peripheral.
|
|
||||||
|
|
||||||
* This function initializes the GINT peripheral and enables the clock.
|
|
||||||
*
|
|
||||||
* param base Base address of the GINT peripheral.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void GINT_Init(GINT_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t instance;
|
|
||||||
|
|
||||||
instance = GINT_GetInstance(base);
|
|
||||||
|
|
||||||
s_gintCallback[instance] = NULL;
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Enable the peripheral clock */
|
|
||||||
CLOCK_EnableClock(s_gintClocks[instance]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
||||||
/* Reset the module. */
|
|
||||||
RESET_PeripheralReset(s_gintResets[instance]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Setup GINT peripheral control parameters.
|
|
||||||
|
|
||||||
* This function sets the control parameters of GINT peripheral.
|
|
||||||
*
|
|
||||||
* param base Base address of the GINT peripheral.
|
|
||||||
* param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation.
|
|
||||||
* param trig Controls if the enabled inputs are level or edge sensitive based on polarity.
|
|
||||||
* param callback This function is called when configured group interrupt is generated.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback)
|
|
||||||
{
|
|
||||||
uint32_t instance;
|
|
||||||
|
|
||||||
instance = GINT_GetInstance(base);
|
|
||||||
|
|
||||||
base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig));
|
|
||||||
|
|
||||||
/* Save callback pointer */
|
|
||||||
s_gintCallback[instance] = callback;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Get GINT peripheral control parameters.
|
|
||||||
|
|
||||||
* This function returns the control parameters of GINT peripheral.
|
|
||||||
*
|
|
||||||
* param base Base address of the GINT peripheral.
|
|
||||||
* param comb Pointer to store combine input value.
|
|
||||||
* param trig Pointer to store trigger value.
|
|
||||||
* param callback Pointer to store callback function.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback)
|
|
||||||
{
|
|
||||||
uint32_t instance;
|
|
||||||
|
|
||||||
instance = GINT_GetInstance(base);
|
|
||||||
|
|
||||||
*comb = (gint_comb_t)((base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT);
|
|
||||||
*trig = (gint_trig_t)((base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT);
|
|
||||||
*callback = s_gintCallback[instance];
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Configure GINT peripheral pins.
|
|
||||||
|
|
||||||
* This function enables and controls the polarity of enabled pin(s) of a given port.
|
|
||||||
*
|
|
||||||
* param base Base address of the GINT peripheral.
|
|
||||||
* param port Port number.
|
|
||||||
* param polarityMask Each bit position selects the polarity of the corresponding enabled pin.
|
|
||||||
* 0 = The pin is active LOW. 1 = The pin is active HIGH.
|
|
||||||
* param enableMask Each bit position selects if the corresponding pin is enabled or not.
|
|
||||||
* 0 = The pin is disabled. 1 = The pin is enabled.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask)
|
|
||||||
{
|
|
||||||
base->PORT_POL[port] = polarityMask;
|
|
||||||
base->PORT_ENA[port] = enableMask;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Get GINT peripheral pin configuration.
|
|
||||||
|
|
||||||
* This function returns the pin configuration of a given port.
|
|
||||||
*
|
|
||||||
* param base Base address of the GINT peripheral.
|
|
||||||
* param port Port number.
|
|
||||||
* param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding
|
|
||||||
enabled pin.
|
|
||||||
* 0 = The pin is active LOW. 1 = The pin is active HIGH.
|
|
||||||
* param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled
|
|
||||||
or not.
|
|
||||||
* 0 = The pin is disabled. 1 = The pin is enabled.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask)
|
|
||||||
{
|
|
||||||
*polarityMask = base->PORT_POL[port];
|
|
||||||
*enableMask = base->PORT_ENA[port];
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Enable callback.
|
|
||||||
|
|
||||||
* This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored
|
|
||||||
* as soon as they are enabled, the callback function is not enabled until this function is called.
|
|
||||||
*
|
|
||||||
* param base Base address of the GINT peripheral.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void GINT_EnableCallback(GINT_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t instance;
|
|
||||||
|
|
||||||
instance = GINT_GetInstance(base);
|
|
||||||
/* If GINT is configured in "AND" mode a spurious interrupt is generated.
|
|
||||||
Clear status and pending interrupt before enabling the irq in NVIC. */
|
|
||||||
GINT_ClrStatus(base);
|
|
||||||
NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
|
|
||||||
EnableIRQ(s_gintIRQ[instance]);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Disable callback.
|
|
||||||
|
|
||||||
* This function disables the interrupt for the selected GINT peripheral. Although the pins are still
|
|
||||||
* being monitored but the callback function is not called.
|
|
||||||
*
|
|
||||||
* param base Base address of the peripheral.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void GINT_DisableCallback(GINT_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t instance;
|
|
||||||
|
|
||||||
instance = GINT_GetInstance(base);
|
|
||||||
DisableIRQ(s_gintIRQ[instance]);
|
|
||||||
GINT_ClrStatus(base);
|
|
||||||
NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Deinitialize GINT peripheral.
|
|
||||||
|
|
||||||
* This function disables the GINT clock.
|
|
||||||
*
|
|
||||||
* param base Base address of the GINT peripheral.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void GINT_Deinit(GINT_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t instance;
|
|
||||||
|
|
||||||
instance = GINT_GetInstance(base);
|
|
||||||
|
|
||||||
/* Cleanup */
|
|
||||||
GINT_DisableCallback(base);
|
|
||||||
s_gintCallback[instance] = NULL;
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
||||||
/* Reset the module. */
|
|
||||||
RESET_PeripheralReset(s_gintResets[instance]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Disable the peripheral clock */
|
|
||||||
CLOCK_DisableClock(s_gintClocks[instance]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
}
|
|
||||||
|
|
||||||
/* IRQ handler functions overloading weak symbols in the startup */
|
|
||||||
#if defined(GINT0)
|
|
||||||
void GINT0_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
/* Clear interrupt before callback */
|
|
||||||
s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK;
|
|
||||||
/* Call user function */
|
|
||||||
if (s_gintCallback[0] != NULL)
|
|
||||||
{
|
|
||||||
s_gintCallback[0]();
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(GINT1)
|
|
||||||
void GINT1_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
/* Clear interrupt before callback */
|
|
||||||
s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK;
|
|
||||||
/* Call user function */
|
|
||||||
if (s_gintCallback[1] != NULL)
|
|
||||||
{
|
|
||||||
s_gintCallback[1]();
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(GINT2)
|
|
||||||
void GINT2_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
/* Clear interrupt before callback */
|
|
||||||
s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK;
|
|
||||||
/* Call user function */
|
|
||||||
if (s_gintCallback[2] != NULL)
|
|
||||||
{
|
|
||||||
s_gintCallback[2]();
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(GINT3)
|
|
||||||
void GINT3_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
/* Clear interrupt before callback */
|
|
||||||
s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK;
|
|
||||||
/* Call user function */
|
|
||||||
if (s_gintCallback[3] != NULL)
|
|
||||||
{
|
|
||||||
s_gintCallback[3]();
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(GINT4)
|
|
||||||
void GINT4_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
/* Clear interrupt before callback */
|
|
||||||
s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK;
|
|
||||||
/* Call user function */
|
|
||||||
if (s_gintCallback[4] != NULL)
|
|
||||||
{
|
|
||||||
s_gintCallback[4]();
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(GINT5)
|
|
||||||
void GINT5_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
/* Clear interrupt before callback */
|
|
||||||
s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK;
|
|
||||||
/* Call user function */
|
|
||||||
if (s_gintCallback[5] != NULL)
|
|
||||||
{
|
|
||||||
s_gintCallback[5]();
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(GINT6)
|
|
||||||
void GINT6_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
/* Clear interrupt before callback */
|
|
||||||
s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK;
|
|
||||||
/* Call user function */
|
|
||||||
if (s_gintCallback[6] != NULL)
|
|
||||||
{
|
|
||||||
s_gintCallback[6]();
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(GINT7)
|
|
||||||
void GINT7_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
/* Clear interrupt before callback */
|
|
||||||
s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK;
|
|
||||||
/* Call user function */
|
|
||||||
if (s_gintCallback[7] != NULL)
|
|
||||||
{
|
|
||||||
s_gintCallback[7]();
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,222 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _FSL_GINT_H_
|
|
||||||
#define _FSL_GINT_H_
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup gint_driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @file */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*! @brief GINT combine inputs type */
|
|
||||||
typedef enum _gint_comb
|
|
||||||
{
|
|
||||||
kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */
|
|
||||||
kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */
|
|
||||||
} gint_comb_t;
|
|
||||||
|
|
||||||
/*! @brief GINT trigger type */
|
|
||||||
typedef enum _gint_trig
|
|
||||||
{
|
|
||||||
kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */
|
|
||||||
kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */
|
|
||||||
} gint_trig_t;
|
|
||||||
|
|
||||||
/* @brief GINT port type */
|
|
||||||
typedef enum _gint_port
|
|
||||||
{
|
|
||||||
kGINT_Port0 = 0U,
|
|
||||||
kGINT_Port1 = 1U,
|
|
||||||
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U)
|
|
||||||
kGINT_Port2 = 2U,
|
|
||||||
#endif
|
|
||||||
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U)
|
|
||||||
kGINT_Port3 = 3U,
|
|
||||||
#endif
|
|
||||||
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U)
|
|
||||||
kGINT_Port4 = 4U,
|
|
||||||
#endif
|
|
||||||
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U)
|
|
||||||
kGINT_Port5 = 5U,
|
|
||||||
#endif
|
|
||||||
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U)
|
|
||||||
kGINT_Port6 = 6U,
|
|
||||||
#endif
|
|
||||||
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U)
|
|
||||||
kGINT_Port7 = 7U,
|
|
||||||
#endif
|
|
||||||
} gint_port_t;
|
|
||||||
|
|
||||||
/*! @brief GINT Callback function. */
|
|
||||||
typedef void (*gint_cb_t)(void);
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initialize GINT peripheral.
|
|
||||||
|
|
||||||
* This function initializes the GINT peripheral and enables the clock.
|
|
||||||
*
|
|
||||||
* @param base Base address of the GINT peripheral.
|
|
||||||
*
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
void GINT_Init(GINT_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Setup GINT peripheral control parameters.
|
|
||||||
|
|
||||||
* This function sets the control parameters of GINT peripheral.
|
|
||||||
*
|
|
||||||
* @param base Base address of the GINT peripheral.
|
|
||||||
* @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation.
|
|
||||||
* @param trig Controls if the enabled inputs are level or edge sensitive based on polarity.
|
|
||||||
* @param callback This function is called when configured group interrupt is generated.
|
|
||||||
*
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get GINT peripheral control parameters.
|
|
||||||
|
|
||||||
* This function returns the control parameters of GINT peripheral.
|
|
||||||
*
|
|
||||||
* @param base Base address of the GINT peripheral.
|
|
||||||
* @param comb Pointer to store combine input value.
|
|
||||||
* @param trig Pointer to store trigger value.
|
|
||||||
* @param callback Pointer to store callback function.
|
|
||||||
*
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Configure GINT peripheral pins.
|
|
||||||
|
|
||||||
* This function enables and controls the polarity of enabled pin(s) of a given port.
|
|
||||||
*
|
|
||||||
* @param base Base address of the GINT peripheral.
|
|
||||||
* @param port Port number.
|
|
||||||
* @param polarityMask Each bit position selects the polarity of the corresponding enabled pin.
|
|
||||||
* 0 = The pin is active LOW. 1 = The pin is active HIGH.
|
|
||||||
* @param enableMask Each bit position selects if the corresponding pin is enabled or not.
|
|
||||||
* 0 = The pin is disabled. 1 = The pin is enabled.
|
|
||||||
*
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get GINT peripheral pin configuration.
|
|
||||||
|
|
||||||
* This function returns the pin configuration of a given port.
|
|
||||||
*
|
|
||||||
* @param base Base address of the GINT peripheral.
|
|
||||||
* @param port Port number.
|
|
||||||
* @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding
|
|
||||||
enabled pin.
|
|
||||||
* 0 = The pin is active LOW. 1 = The pin is active HIGH.
|
|
||||||
* @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled
|
|
||||||
or not.
|
|
||||||
* 0 = The pin is disabled. 1 = The pin is enabled.
|
|
||||||
*
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enable callback.
|
|
||||||
|
|
||||||
* This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored
|
|
||||||
* as soon as they are enabled, the callback function is not enabled until this function is called.
|
|
||||||
*
|
|
||||||
* @param base Base address of the GINT peripheral.
|
|
||||||
*
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
void GINT_EnableCallback(GINT_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Disable callback.
|
|
||||||
|
|
||||||
* This function disables the interrupt for the selected GINT peripheral. Although the pins are still
|
|
||||||
* being monitored but the callback function is not called.
|
|
||||||
*
|
|
||||||
* @param base Base address of the peripheral.
|
|
||||||
*
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
void GINT_DisableCallback(GINT_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Clear GINT status.
|
|
||||||
|
|
||||||
* This function clears the GINT status bit.
|
|
||||||
*
|
|
||||||
* @param base Base address of the GINT peripheral.
|
|
||||||
*
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
static inline void GINT_ClrStatus(GINT_Type *base)
|
|
||||||
{
|
|
||||||
base->CTRL |= GINT_CTRL_INT_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get GINT status.
|
|
||||||
|
|
||||||
* This function returns the GINT status.
|
|
||||||
*
|
|
||||||
* @param base Base address of the GINT peripheral.
|
|
||||||
*
|
|
||||||
* @retval status = 0 No group interrupt request. = 1 Group interrupt request active.
|
|
||||||
*/
|
|
||||||
static inline uint32_t GINT_GetStatus(GINT_Type *base)
|
|
||||||
{
|
|
||||||
return (base->CTRL & GINT_CTRL_INT_MASK);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Deinitialize GINT peripheral.
|
|
||||||
|
|
||||||
* This function disables the GINT clock.
|
|
||||||
*
|
|
||||||
* @param base Base address of the GINT peripheral.
|
|
||||||
*
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
void GINT_Deinit(GINT_Type *base);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
#endif /* _FSL_GINT_H_ */
|
|
||||||
|
|
@ -1,112 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "fsl_gpio.h"
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables
|
|
||||||
******************************************************************************/
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/*! @brief Array to map FGPIO instance number to clock name. */
|
|
||||||
static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS;
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
|
|
||||||
/*! @brief Pointers to GPIO resets for each instance. */
|
|
||||||
static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N;
|
|
||||||
#endif
|
|
||||||
/*******************************************************************************
|
|
||||||
* Prototypes
|
|
||||||
************ ******************************************************************/
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code
|
|
||||||
******************************************************************************/
|
|
||||||
/*!
|
|
||||||
* brief Initializes the GPIO peripheral.
|
|
||||||
*
|
|
||||||
* This function ungates the GPIO clock.
|
|
||||||
*
|
|
||||||
* param base GPIO peripheral base pointer.
|
|
||||||
* param port GPIO port number.
|
|
||||||
*/
|
|
||||||
void GPIO_PortInit(GPIO_Type *base, uint32_t port)
|
|
||||||
{
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
assert(port < ARRAY_SIZE(s_gpioClockName));
|
|
||||||
|
|
||||||
/* Upgate the GPIO clock */
|
|
||||||
CLOCK_EnableClock(s_gpioClockName[port]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
|
|
||||||
/* Reset the GPIO module */
|
|
||||||
RESET_PeripheralReset(s_gpioResets[port]);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Initializes a GPIO pin used by the board.
|
|
||||||
*
|
|
||||||
* To initialize the GPIO, define a pin configuration, either input or output, in the user file.
|
|
||||||
* Then, call the GPIO_PinInit() function.
|
|
||||||
*
|
|
||||||
* This is an example to define an input pin or output pin configuration:
|
|
||||||
* code
|
|
||||||
* // Define a digital input pin configuration,
|
|
||||||
* gpio_pin_config_t config =
|
|
||||||
* {
|
|
||||||
* kGPIO_DigitalInput,
|
|
||||||
* 0,
|
|
||||||
* }
|
|
||||||
* //Define a digital output pin configuration,
|
|
||||||
* gpio_pin_config_t config =
|
|
||||||
* {
|
|
||||||
* kGPIO_DigitalOutput,
|
|
||||||
* 0,
|
|
||||||
* }
|
|
||||||
* endcode
|
|
||||||
*
|
|
||||||
* param base GPIO peripheral base pointer(Typically GPIO)
|
|
||||||
* param port GPIO port number
|
|
||||||
* param pin GPIO pin number
|
|
||||||
* param config GPIO pin configuration pointer
|
|
||||||
*/
|
|
||||||
void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)
|
|
||||||
{
|
|
||||||
if (config->pinDirection == kGPIO_DigitalInput)
|
|
||||||
{
|
|
||||||
#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
|
|
||||||
base->DIRCLR[port] = 1U << pin;
|
|
||||||
#else
|
|
||||||
base->DIR[port] &= ~(1U << pin);
|
|
||||||
#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Set default output value */
|
|
||||||
if (config->outputLogic == 0U)
|
|
||||||
{
|
|
||||||
base->CLR[port] = (1U << pin);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
base->SET[port] = (1U << pin);
|
|
||||||
}
|
|
||||||
/* Set pin direction */
|
|
||||||
#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
|
|
||||||
base->DIRSET[port] = 1U << pin;
|
|
||||||
#else
|
|
||||||
base->DIR[port] |= 1U << pin;
|
|
||||||
#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,241 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _LPC_GPIO_H_
|
|
||||||
#define _LPC_GPIO_H_
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup lpc_gpio
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @file */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
/*! @brief LPC GPIO driver version 2.1.3. */
|
|
||||||
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*! @brief LPC GPIO direction definition */
|
|
||||||
typedef enum _gpio_pin_direction
|
|
||||||
{
|
|
||||||
kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/
|
|
||||||
kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
|
|
||||||
} gpio_pin_direction_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief The GPIO pin configuration structure.
|
|
||||||
*
|
|
||||||
* Every pin can only be configured as either output pin or input pin at a time.
|
|
||||||
* If configured as a input pin, then leave the outputConfig unused.
|
|
||||||
*/
|
|
||||||
typedef struct _gpio_pin_config
|
|
||||||
{
|
|
||||||
gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
|
|
||||||
/* Output configurations, please ignore if configured as a input one */
|
|
||||||
uint8_t outputLogic; /*!< Set default output logic, no use in input */
|
|
||||||
} gpio_pin_config_t;
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*! @name GPIO Configuration */
|
|
||||||
/*@{*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initializes the GPIO peripheral.
|
|
||||||
*
|
|
||||||
* This function ungates the GPIO clock.
|
|
||||||
*
|
|
||||||
* @param base GPIO peripheral base pointer.
|
|
||||||
* @param port GPIO port number.
|
|
||||||
*/
|
|
||||||
void GPIO_PortInit(GPIO_Type *base, uint32_t port);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initializes a GPIO pin used by the board.
|
|
||||||
*
|
|
||||||
* To initialize the GPIO, define a pin configuration, either input or output, in the user file.
|
|
||||||
* Then, call the GPIO_PinInit() function.
|
|
||||||
*
|
|
||||||
* This is an example to define an input pin or output pin configuration:
|
|
||||||
* @code
|
|
||||||
* // Define a digital input pin configuration,
|
|
||||||
* gpio_pin_config_t config =
|
|
||||||
* {
|
|
||||||
* kGPIO_DigitalInput,
|
|
||||||
* 0,
|
|
||||||
* }
|
|
||||||
* //Define a digital output pin configuration,
|
|
||||||
* gpio_pin_config_t config =
|
|
||||||
* {
|
|
||||||
* kGPIO_DigitalOutput,
|
|
||||||
* 0,
|
|
||||||
* }
|
|
||||||
* @endcode
|
|
||||||
*
|
|
||||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
|
||||||
* @param port GPIO port number
|
|
||||||
* @param pin GPIO pin number
|
|
||||||
* @param config GPIO pin configuration pointer
|
|
||||||
*/
|
|
||||||
void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config);
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*! @name GPIO Output Operations */
|
|
||||||
/*@{*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Sets the output level of the one GPIO pin to the logic 1 or 0.
|
|
||||||
*
|
|
||||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
|
||||||
* @param port GPIO port number
|
|
||||||
* @param pin GPIO pin number
|
|
||||||
* @param output GPIO pin output logic level.
|
|
||||||
* - 0: corresponding pin output low-logic level.
|
|
||||||
* - 1: corresponding pin output high-logic level.
|
|
||||||
*/
|
|
||||||
static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)
|
|
||||||
{
|
|
||||||
base->B[port][pin] = output;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
/*! @name GPIO Input Operations */
|
|
||||||
/*@{*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Reads the current input value of the GPIO PIN.
|
|
||||||
*
|
|
||||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
|
||||||
* @param port GPIO port number
|
|
||||||
* @param pin GPIO pin number
|
|
||||||
* @retval GPIO port input value
|
|
||||||
* - 0: corresponding pin input low-logic level.
|
|
||||||
* - 1: corresponding pin input high-logic level.
|
|
||||||
*/
|
|
||||||
static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin)
|
|
||||||
{
|
|
||||||
return (uint32_t)base->B[port][pin];
|
|
||||||
}
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Sets the output level of the multiple GPIO pins to the logic 1.
|
|
||||||
*
|
|
||||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
|
||||||
* @param port GPIO port number
|
|
||||||
* @param mask GPIO pin number macro
|
|
||||||
*/
|
|
||||||
static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask)
|
|
||||||
{
|
|
||||||
base->SET[port] = mask;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Sets the output level of the multiple GPIO pins to the logic 0.
|
|
||||||
*
|
|
||||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
|
||||||
* @param port GPIO port number
|
|
||||||
* @param mask GPIO pin number macro
|
|
||||||
*/
|
|
||||||
static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask)
|
|
||||||
{
|
|
||||||
base->CLR[port] = mask;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Reverses current output logic of the multiple GPIO pins.
|
|
||||||
*
|
|
||||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
|
||||||
* @param port GPIO port number
|
|
||||||
* @param mask GPIO pin number macro
|
|
||||||
*/
|
|
||||||
static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask)
|
|
||||||
{
|
|
||||||
base->NOT[port] = mask;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Reads the current input value of the whole GPIO port.
|
|
||||||
*
|
|
||||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
|
||||||
* @param port GPIO port number
|
|
||||||
*/
|
|
||||||
static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port)
|
|
||||||
{
|
|
||||||
return (uint32_t)base->PIN[port];
|
|
||||||
}
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
/*! @name GPIO Mask Operations */
|
|
||||||
/*@{*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Sets port mask, 0 - enable pin, 1 - disable pin.
|
|
||||||
*
|
|
||||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
|
||||||
* @param port GPIO port number
|
|
||||||
* @param mask GPIO pin number macro
|
|
||||||
*/
|
|
||||||
static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask)
|
|
||||||
{
|
|
||||||
base->MASK[port] = mask;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected.
|
|
||||||
*
|
|
||||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
|
||||||
* @param port GPIO port number
|
|
||||||
* @param output GPIO port output value.
|
|
||||||
*/
|
|
||||||
static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output)
|
|
||||||
{
|
|
||||||
base->MPIN[port] = output;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be
|
|
||||||
* affected.
|
|
||||||
*
|
|
||||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
|
||||||
* @param port GPIO port number
|
|
||||||
* @retval masked GPIO port value
|
|
||||||
*/
|
|
||||||
static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port)
|
|
||||||
{
|
|
||||||
return (uint32_t)base->MPIN[port];
|
|
||||||
}
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#endif /* _LPC_GPIO_H_*/
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,420 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2017-2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _FSL_HASHCRYPT_H_
|
|
||||||
#define _FSL_HASHCRYPT_H_
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*! @brief HASHCRYPT status return codes. */
|
|
||||||
enum _hashcrypt_status
|
|
||||||
{
|
|
||||||
kStatus_HASHCRYPT_Again =
|
|
||||||
MAKE_STATUS(kStatusGroup_HASHCRYPT, 0), /*!< Non-blocking function shall be called again. */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
*******************************************************************************/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup hashcrypt_driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
/*! @brief HASHCRYPT driver version. Version 2.0.0.
|
|
||||||
*
|
|
||||||
* Current version: 2.0.0
|
|
||||||
*
|
|
||||||
* Change log:
|
|
||||||
* - Version 2.0.0
|
|
||||||
* - Initial version
|
|
||||||
*/
|
|
||||||
#define FSL_HASHCRYPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*! @brief Algorithm used for Hashcrypt operation */
|
|
||||||
typedef enum _hashcrypt_algo_t
|
|
||||||
{
|
|
||||||
kHASHCRYPT_Sha1 = 1, /*!< SHA_1 */
|
|
||||||
kHASHCRYPT_Sha256 = 2, /*!< SHA_256 */
|
|
||||||
kHASHCRYPT_Sha512 = 3, /*!< SHA_512 */
|
|
||||||
kHASHCRYPT_Aes = 4, /*!< AES */
|
|
||||||
kHASHCRYPT_AesIcb = 5, /*!< AES_ICB */
|
|
||||||
} hashcrypt_algo_t;
|
|
||||||
|
|
||||||
/*! @} */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* AES Definitions
|
|
||||||
*******************************************************************************/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup hashcrypt_driver_aes
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! AES block size in bytes */
|
|
||||||
#define HASHCRYPT_AES_BLOCK_SIZE 16
|
|
||||||
#define AES_ENCRYPT 0
|
|
||||||
#define AES_DECRYPT 1
|
|
||||||
|
|
||||||
/*! @brief AES mode */
|
|
||||||
typedef enum _hashcrypt_aes_mode_t
|
|
||||||
{
|
|
||||||
kHASHCRYPT_AesEcb = 0U, /*!< AES ECB mode */
|
|
||||||
kHASHCRYPT_AesCbc = 1U, /*!< AES CBC mode */
|
|
||||||
kHASHCRYPT_AesCtr = 2U, /*!< AES CTR mode */
|
|
||||||
} hashcrypt_aes_mode_t;
|
|
||||||
|
|
||||||
/*! @brief Size of AES key */
|
|
||||||
typedef enum _hashcrypt_aes_keysize_t
|
|
||||||
{
|
|
||||||
kHASHCRYPT_Aes128 = 0U, /*!< AES 128 bit key */
|
|
||||||
kHASHCRYPT_Aes192 = 1U, /*!< AES 192 bit key */
|
|
||||||
kHASHCRYPT_Aes256 = 2U, /*!< AES 256 bit key */
|
|
||||||
kHASHCRYPT_InvalidKey = 3U, /*!< AES invalid key */
|
|
||||||
} hashcrypt_aes_keysize_t;
|
|
||||||
|
|
||||||
/*! @brief HASHCRYPT key source selection.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
typedef enum _hashcrypt_key
|
|
||||||
{
|
|
||||||
kHASHCRYPT_UserKey = 0xc3c3U, /*!< HASHCRYPT user key */
|
|
||||||
kHASHCRYPT_SecretKey = 0x3c3cU, /*!< HASHCRYPT secret key (dedicated hw bus from PUF) */
|
|
||||||
} hashcrypt_key_t;
|
|
||||||
|
|
||||||
/*! @brief Specify HASHCRYPT's key resource. */
|
|
||||||
typedef struct _hashcrypt_handle
|
|
||||||
{
|
|
||||||
uint32_t keyWord[8]; /*!< Copy of user key (set by HASHCRYPT_AES_SetKey(). */
|
|
||||||
hashcrypt_aes_keysize_t keySize;
|
|
||||||
hashcrypt_key_t keyType; /*!< For operations with key (such as AES encryption/decryption), specify key type. */
|
|
||||||
} hashcrypt_handle_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
*@}
|
|
||||||
*/ /* end of hashcrypt_driver_aes */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* HASH Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
/*!
|
|
||||||
* @addtogroup hashcrypt_driver_hash
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @brief HASHCRYPT HASH Context size. */
|
|
||||||
#define HASHCRYPT_HASH_CTX_SIZE 22
|
|
||||||
|
|
||||||
/*! @brief Storage type used to save hash context. */
|
|
||||||
typedef struct _hashcrypt_hash_ctx_t
|
|
||||||
{
|
|
||||||
uint32_t x[HASHCRYPT_HASH_CTX_SIZE]; /*!< storage */
|
|
||||||
} hashcrypt_hash_ctx_t;
|
|
||||||
|
|
||||||
/*! @brief HASHCRYPT background hash callback function. */
|
|
||||||
typedef void (*hashcrypt_callback_t)(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, status_t status, void *userData);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
*@}
|
|
||||||
*/ /* end of hashcrypt_driver_hash */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup hashcrypt_driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enables clock and disables reset for HASHCRYPT peripheral.
|
|
||||||
*
|
|
||||||
* Enable clock and disable reset for HASHCRYPT.
|
|
||||||
*
|
|
||||||
* @param base HASHCRYPT base address
|
|
||||||
*/
|
|
||||||
void HASHCRYPT_Init(HASHCRYPT_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Disables clock for HASHCRYPT peripheral.
|
|
||||||
*
|
|
||||||
* Disable clock and enable reset.
|
|
||||||
*
|
|
||||||
* @param base HASHCRYPT base address
|
|
||||||
*/
|
|
||||||
void HASHCRYPT_Deinit(HASHCRYPT_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
*@}
|
|
||||||
*/ /* end of hashcrypt_driver */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* AES API
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup hashcrypt_driver_aes
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set AES key to hashcrypt_handle_t struct and optionally to HASHCRYPT.
|
|
||||||
*
|
|
||||||
* Sets the AES key for encryption/decryption with the hashcrypt_handle_t structure.
|
|
||||||
* The hashcrypt_handle_t input argument specifies key source.
|
|
||||||
*
|
|
||||||
* @param base HASHCRYPT peripheral base address.
|
|
||||||
* @param handle Handle used for the request.
|
|
||||||
* @param key 0-mod-4 aligned pointer to AES key.
|
|
||||||
* @param keySize AES key size in bytes. Shall equal 16, 24 or 32.
|
|
||||||
* @return status from set key operation
|
|
||||||
*/
|
|
||||||
status_t HASHCRYPT_AES_SetKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *key, size_t keySize);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Encrypts AES on one or multiple 128-bit block(s).
|
|
||||||
*
|
|
||||||
* Encrypts AES.
|
|
||||||
* The source plaintext and destination ciphertext can overlap in system memory.
|
|
||||||
*
|
|
||||||
* @param base HASHCRYPT peripheral base address
|
|
||||||
* @param handle Handle used for this request.
|
|
||||||
* @param plaintext Input plain text to encrypt
|
|
||||||
* @param[out] ciphertext Output cipher text
|
|
||||||
* @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
|
|
||||||
* @return Status from encrypt operation
|
|
||||||
*/
|
|
||||||
status_t HASHCRYPT_AES_EncryptEcb(
|
|
||||||
HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Decrypts AES on one or multiple 128-bit block(s).
|
|
||||||
*
|
|
||||||
* Decrypts AES.
|
|
||||||
* The source ciphertext and destination plaintext can overlap in system memory.
|
|
||||||
*
|
|
||||||
* @param base HASHCRYPT peripheral base address
|
|
||||||
* @param handle Handle used for this request.
|
|
||||||
* @param ciphertext Input plain text to encrypt
|
|
||||||
* @param[out] plaintext Output cipher text
|
|
||||||
* @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
|
|
||||||
* @return Status from decrypt operation
|
|
||||||
*/
|
|
||||||
status_t HASHCRYPT_AES_DecryptEcb(
|
|
||||||
HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Encrypts AES using CBC block mode.
|
|
||||||
*
|
|
||||||
* @param base HASHCRYPT peripheral base address
|
|
||||||
* @param handle Handle used for this request.
|
|
||||||
* @param plaintext Input plain text to encrypt
|
|
||||||
* @param[out] ciphertext Output cipher text
|
|
||||||
* @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
|
|
||||||
* @param iv Input initial vector to combine with the first input block.
|
|
||||||
* @return Status from encrypt operation
|
|
||||||
*/
|
|
||||||
status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base,
|
|
||||||
hashcrypt_handle_t *handle,
|
|
||||||
const uint8_t *plaintext,
|
|
||||||
uint8_t *ciphertext,
|
|
||||||
size_t size,
|
|
||||||
const uint8_t iv[16]);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Decrypts AES using CBC block mode.
|
|
||||||
*
|
|
||||||
* @param base HASHCRYPT peripheral base address
|
|
||||||
* @param handle Handle used for this request.
|
|
||||||
* @param ciphertext Input cipher text to decrypt
|
|
||||||
* @param[out] plaintext Output plain text
|
|
||||||
* @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
|
|
||||||
* @param iv Input initial vector to combine with the first input block.
|
|
||||||
* @return Status from decrypt operation
|
|
||||||
*/
|
|
||||||
status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base,
|
|
||||||
hashcrypt_handle_t *handle,
|
|
||||||
const uint8_t *ciphertext,
|
|
||||||
uint8_t *plaintext,
|
|
||||||
size_t size,
|
|
||||||
const uint8_t iv[16]);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Encrypts or decrypts AES using CTR block mode.
|
|
||||||
*
|
|
||||||
* Encrypts or decrypts AES using CTR block mode.
|
|
||||||
* AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption.
|
|
||||||
* The only difference between encryption and decryption is that, for encryption, the input argument
|
|
||||||
* is plain text and the output argument is cipher text. For decryption, the input argument is cipher text
|
|
||||||
* and the output argument is plain text.
|
|
||||||
*
|
|
||||||
* @param base HASHCRYPT peripheral base address
|
|
||||||
* @param handle Handle used for this request.
|
|
||||||
* @param input Input data for CTR block mode
|
|
||||||
* @param[out] output Output data for CTR block mode
|
|
||||||
* @param size Size of input and output data in bytes
|
|
||||||
* @param[in,out] counter Input counter (updates on return)
|
|
||||||
* @param[out] counterlast Output cipher of last counter, for chained CTR calls (statefull encryption). NULL can be
|
|
||||||
* passed if chained calls are
|
|
||||||
* not used.
|
|
||||||
* @param[out] szLeft Output number of bytes in left unused in counterlast block. NULL can be passed if chained calls
|
|
||||||
* are not used.
|
|
||||||
* @return Status from encrypt operation
|
|
||||||
*/
|
|
||||||
status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base,
|
|
||||||
hashcrypt_handle_t *handle,
|
|
||||||
const uint8_t *input,
|
|
||||||
uint8_t *output,
|
|
||||||
size_t size,
|
|
||||||
uint8_t counter[HASHCRYPT_AES_BLOCK_SIZE],
|
|
||||||
uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE],
|
|
||||||
size_t *szLeft);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
*@}
|
|
||||||
*/ /* end of hashcrypt_driver_aes */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* HASH API
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup hashcrypt_driver_hash
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Create HASH on given data
|
|
||||||
*
|
|
||||||
* Perform the full SHA in one function call. The function is blocking.
|
|
||||||
*
|
|
||||||
* @param base HASHCRYPT peripheral base address
|
|
||||||
* @param algo Underlaying algorithm to use for hash computation.
|
|
||||||
* @param input Input data
|
|
||||||
* @param inputSize Size of input data in bytes
|
|
||||||
* @param[out] output Output hash data
|
|
||||||
* @param[out] outputSize Output parameter storing the size of the output hash in bytes
|
|
||||||
* @return Status of the one call hash operation.
|
|
||||||
*/
|
|
||||||
status_t HASHCRYPT_SHA(HASHCRYPT_Type *base,
|
|
||||||
hashcrypt_algo_t algo,
|
|
||||||
const uint8_t *input,
|
|
||||||
size_t inputSize,
|
|
||||||
uint8_t *output,
|
|
||||||
size_t *outputSize);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initialize HASH context
|
|
||||||
*
|
|
||||||
* This function initializes the HASH.
|
|
||||||
*
|
|
||||||
* @param base HASHCRYPT peripheral base address
|
|
||||||
* @param[out] ctx Output hash context
|
|
||||||
* @param algo Underlaying algorithm to use for hash computation.
|
|
||||||
* @return Status of initialization
|
|
||||||
*/
|
|
||||||
status_t HASHCRYPT_SHA_Init(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Add data to current HASH
|
|
||||||
*
|
|
||||||
* Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be
|
|
||||||
* hashed. The functions blocks. If it returns kStatus_Success, the running hash
|
|
||||||
* has been updated (HASHCRYPT has processed the input data), so the memory at \p input pointer
|
|
||||||
* can be released back to system. The HASHCRYPT context buffer is updated with the running hash
|
|
||||||
* and with all necessary information to support possible context switch.
|
|
||||||
*
|
|
||||||
* @param base HASHCRYPT peripheral base address
|
|
||||||
* @param[in,out] ctx HASH context
|
|
||||||
* @param input Input data
|
|
||||||
* @param inputSize Size of input data in bytes
|
|
||||||
* @return Status of the hash update operation
|
|
||||||
*/
|
|
||||||
status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Finalize hashing
|
|
||||||
*
|
|
||||||
* Outputs the final hash (computed by HASHCRYPT_HASH_Update()) and erases the context.
|
|
||||||
*
|
|
||||||
* @param base HASHCRYPT peripheral base address
|
|
||||||
* @param[in,out] ctx Input hash context
|
|
||||||
* @param[out] output Output hash data
|
|
||||||
* @param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of
|
|
||||||
* output[] buffer. On function return, it stores the number of updated output bytes.
|
|
||||||
* @return Status of the hash finish operation
|
|
||||||
*/
|
|
||||||
status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
*@}
|
|
||||||
*/ /* end of hashcrypt_driver_hash */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup hashcrypt_background_driver_hash
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initializes the HASHCRYPT handle for background hashing.
|
|
||||||
*
|
|
||||||
* This function initializes the hash context for background hashing
|
|
||||||
* (Non-blocking) APIs. This is less typical interface to hash function, but can be used
|
|
||||||
* for parallel processing, when main CPU has something else to do.
|
|
||||||
* Example is digital signature RSASSA-PKCS1-V1_5-VERIFY((n,e),M,S) algorithm, where
|
|
||||||
* background hashing of M can be started, then CPU can compute S^e mod n
|
|
||||||
* (in parallel with background hashing) and once the digest becomes available,
|
|
||||||
* CPU can proceed to comparison of EM with EM'.
|
|
||||||
*
|
|
||||||
* @param base HASHCRYPT peripheral base address.
|
|
||||||
* @param[out] ctx Hash context.
|
|
||||||
* @param callback Callback function.
|
|
||||||
* @param userData User data (to be passed as an argument to callback function, once callback is invoked from isr).
|
|
||||||
*/
|
|
||||||
void HASHCRYPT_SHA_SetCallback(HASHCRYPT_Type *base,
|
|
||||||
hashcrypt_hash_ctx_t *ctx,
|
|
||||||
hashcrypt_callback_t callback,
|
|
||||||
void *userData);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Create running hash on given data.
|
|
||||||
*
|
|
||||||
* Configures the HASHCRYPT to compute new running hash as AHB master
|
|
||||||
* and returns immediately. HASHCRYPT AHB Master mode supports only aligned \p input
|
|
||||||
* address and can be called only once per continuous block of data. Every call to this function
|
|
||||||
* must be preceded with HASHCRYPT_SHA_Init() and finished with HASHCRYPT_SHA_Finish().
|
|
||||||
* Once callback function is invoked by HASHCRYPT isr, it should set a flag
|
|
||||||
* for the main application to finalize the hashing (padding) and to read out the final digest
|
|
||||||
* by calling HASHCRYPT_SHA_Finish().
|
|
||||||
*
|
|
||||||
* @param base HASHCRYPT peripheral base address
|
|
||||||
* @param ctx Specifies callback. Last incomplete 512-bit block of the input is copied into clear buffer for padding.
|
|
||||||
* @param input 32-bit word aligned pointer to Input data.
|
|
||||||
* @param inputSize Size of input data in bytes (must be word aligned)
|
|
||||||
* @return Status of the hash update operation.
|
|
||||||
*/
|
|
||||||
status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base,
|
|
||||||
hashcrypt_hash_ctx_t *ctx,
|
|
||||||
const uint8_t *input,
|
|
||||||
size_t inputSize);
|
|
||||||
/*!
|
|
||||||
*@}
|
|
||||||
*/ /* end of hashcrypt_background_driver_hash */
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* _FSL_HASHCRYPT_H_ */
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,588 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "fsl_i2c_dma.h"
|
|
||||||
#include "fsl_flexcomm.h"
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_dma"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*<! @brief Structure definition for i2c_master_dma_handle_t. The structure is private. */
|
|
||||||
typedef struct _i2c_master_dma_private_handle
|
|
||||||
{
|
|
||||||
I2C_Type *base;
|
|
||||||
i2c_master_dma_handle_t *handle;
|
|
||||||
} i2c_master_dma_private_handle_t;
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Prototypes
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief DMA callback for I2C master DMA driver.
|
|
||||||
*
|
|
||||||
* @param handle DMA handler for I2C master DMA driver
|
|
||||||
* @param userData user param passed to the callback function
|
|
||||||
*/
|
|
||||||
static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set up master transfer, send slave address and sub address(if any), wait until the
|
|
||||||
* wait until address sent status return.
|
|
||||||
*
|
|
||||||
* @param base I2C peripheral base address.
|
|
||||||
* @param handle pointer to i2c_master_dma_handle_t structure which stores the transfer state.
|
|
||||||
* @param xfer pointer to i2c_master_transfer_t structure.
|
|
||||||
*/
|
|
||||||
static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
|
|
||||||
i2c_master_dma_handle_t *handle,
|
|
||||||
i2c_master_transfer_t *xfer);
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*<! Private handle only used for internally. */
|
|
||||||
static i2c_master_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_I2C_COUNT];
|
|
||||||
|
|
||||||
/*! @brief IRQ name array */
|
|
||||||
static const IRQn_Type s_i2cIRQ[] = I2C_IRQS;
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Codes
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Prepares the transfer state machine and fills in the command buffer.
|
|
||||||
* @param handle Master nonblocking driver handle.
|
|
||||||
*/
|
|
||||||
static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
|
|
||||||
i2c_master_dma_handle_t *handle,
|
|
||||||
i2c_master_transfer_t *xfer)
|
|
||||||
{
|
|
||||||
struct _i2c_master_transfer *transfer;
|
|
||||||
|
|
||||||
handle->transfer = *xfer;
|
|
||||||
transfer = &(handle->transfer);
|
|
||||||
|
|
||||||
handle->transferCount = 0;
|
|
||||||
handle->remainingBytesDMA = 0;
|
|
||||||
handle->buf = (uint8_t *)transfer->data;
|
|
||||||
handle->remainingSubaddr = 0;
|
|
||||||
|
|
||||||
if (transfer->flags & kI2C_TransferNoStartFlag)
|
|
||||||
{
|
|
||||||
/* Start condition shall be ommited, switch directly to next phase */
|
|
||||||
if (transfer->dataSize == 0)
|
|
||||||
{
|
|
||||||
handle->state = kStopState;
|
|
||||||
}
|
|
||||||
else if (handle->transfer.direction == kI2C_Write)
|
|
||||||
{
|
|
||||||
handle->state = xfer->dataSize = kTransmitDataState;
|
|
||||||
}
|
|
||||||
else if (handle->transfer.direction == kI2C_Read)
|
|
||||||
{
|
|
||||||
handle->state = (xfer->dataSize == 1) ? kReceiveLastDataState : kReceiveDataState;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
return kStatus_I2C_InvalidParameter;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
if (transfer->subaddressSize != 0)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
uint32_t subaddress;
|
|
||||||
|
|
||||||
if (transfer->subaddressSize > sizeof(handle->subaddrBuf))
|
|
||||||
{
|
|
||||||
return kStatus_I2C_InvalidParameter;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */
|
|
||||||
subaddress = xfer->subaddress;
|
|
||||||
for (i = xfer->subaddressSize - 1; i >= 0; i--)
|
|
||||||
{
|
|
||||||
handle->subaddrBuf[i] = subaddress & 0xff;
|
|
||||||
subaddress >>= 8;
|
|
||||||
}
|
|
||||||
handle->remainingSubaddr = transfer->subaddressSize;
|
|
||||||
}
|
|
||||||
|
|
||||||
handle->state = kStartState;
|
|
||||||
}
|
|
||||||
|
|
||||||
return kStatus_Success;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle)
|
|
||||||
{
|
|
||||||
int transfer_size;
|
|
||||||
dma_transfer_config_t xferConfig;
|
|
||||||
|
|
||||||
/* Update transfer count */
|
|
||||||
handle->transferCount = handle->buf - (uint8_t *)handle->transfer.data;
|
|
||||||
|
|
||||||
/* Check if there is anything to be transferred at all */
|
|
||||||
if (handle->remainingBytesDMA == 0)
|
|
||||||
{
|
|
||||||
/* No data to be transferrred, disable DMA */
|
|
||||||
base->MSTCTL = 0;
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Calculate transfer size */
|
|
||||||
transfer_size = handle->remainingBytesDMA;
|
|
||||||
if (transfer_size > I2C_MAX_DMA_TRANSFER_COUNT)
|
|
||||||
{
|
|
||||||
transfer_size = I2C_MAX_DMA_TRANSFER_COUNT;
|
|
||||||
}
|
|
||||||
|
|
||||||
switch (handle->transfer.direction)
|
|
||||||
{
|
|
||||||
case kI2C_Write:
|
|
||||||
DMA_PrepareTransfer(&xferConfig, handle->buf, (void *)&base->MSTDAT, sizeof(uint8_t), transfer_size,
|
|
||||||
kDMA_MemoryToPeripheral, NULL);
|
|
||||||
break;
|
|
||||||
|
|
||||||
case kI2C_Read:
|
|
||||||
DMA_PrepareTransfer(&xferConfig, (void *)&base->MSTDAT, handle->buf, sizeof(uint8_t), transfer_size,
|
|
||||||
kDMA_PeripheralToMemory, NULL);
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
/* This should never happen */
|
|
||||||
assert(0);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
|
|
||||||
DMA_StartTransfer(handle->dmaHandle);
|
|
||||||
|
|
||||||
handle->remainingBytesDMA -= transfer_size;
|
|
||||||
handle->buf += transfer_size;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Execute states until the transfer is done.
|
|
||||||
* @param handle Master nonblocking driver handle.
|
|
||||||
* @param[out] isDone Set to true if the transfer has completed.
|
|
||||||
* @retval #kStatus_Success
|
|
||||||
* @retval #kStatus_I2C_ArbitrationLost
|
|
||||||
* @retval #kStatus_I2C_Nak
|
|
||||||
*/
|
|
||||||
static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone)
|
|
||||||
{
|
|
||||||
uint32_t status;
|
|
||||||
uint32_t master_state;
|
|
||||||
struct _i2c_master_transfer *transfer;
|
|
||||||
dma_transfer_config_t xferConfig;
|
|
||||||
status_t err;
|
|
||||||
uint32_t start_flag = 0;
|
|
||||||
|
|
||||||
transfer = &(handle->transfer);
|
|
||||||
|
|
||||||
*isDone = false;
|
|
||||||
|
|
||||||
status = I2C_GetStatusFlags(base);
|
|
||||||
|
|
||||||
if (status & I2C_STAT_MSTARBLOSS_MASK)
|
|
||||||
{
|
|
||||||
I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK);
|
|
||||||
DMA_AbortTransfer(handle->dmaHandle);
|
|
||||||
base->MSTCTL = 0;
|
|
||||||
return kStatus_I2C_ArbitrationLost;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (status & I2C_STAT_MSTSTSTPERR_MASK)
|
|
||||||
{
|
|
||||||
I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK);
|
|
||||||
DMA_AbortTransfer(handle->dmaHandle);
|
|
||||||
base->MSTCTL = 0;
|
|
||||||
return kStatus_I2C_StartStopError;
|
|
||||||
}
|
|
||||||
|
|
||||||
if ((status & I2C_STAT_MSTPENDING_MASK) == 0)
|
|
||||||
{
|
|
||||||
return kStatus_I2C_Busy;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get the state of the I2C module */
|
|
||||||
master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
|
|
||||||
|
|
||||||
if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT))
|
|
||||||
{
|
|
||||||
/* Slave NACKed last byte, issue stop and return error */
|
|
||||||
DMA_AbortTransfer(handle->dmaHandle);
|
|
||||||
base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
|
|
||||||
handle->state = kWaitForCompletionState;
|
|
||||||
return kStatus_I2C_Nak;
|
|
||||||
}
|
|
||||||
|
|
||||||
err = kStatus_Success;
|
|
||||||
|
|
||||||
if (handle->state == kStartState)
|
|
||||||
{
|
|
||||||
/* set start flag for later use */
|
|
||||||
start_flag = I2C_MSTCTL_MSTSTART_MASK;
|
|
||||||
|
|
||||||
if (handle->remainingSubaddr)
|
|
||||||
{
|
|
||||||
base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
|
|
||||||
handle->state = kTransmitSubaddrState;
|
|
||||||
}
|
|
||||||
else if (transfer->direction == kI2C_Write)
|
|
||||||
{
|
|
||||||
base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
|
|
||||||
if (transfer->dataSize == 0)
|
|
||||||
{
|
|
||||||
/* No data to be transferred, initiate start and schedule stop */
|
|
||||||
base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
|
|
||||||
handle->state = kStopState;
|
|
||||||
return err;
|
|
||||||
}
|
|
||||||
handle->state = kTransmitDataState;
|
|
||||||
}
|
|
||||||
else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0))
|
|
||||||
{
|
|
||||||
base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u;
|
|
||||||
if (transfer->dataSize == 1)
|
|
||||||
{
|
|
||||||
/* The very last byte is always received by means of SW */
|
|
||||||
base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
|
|
||||||
handle->state = kReceiveLastDataState;
|
|
||||||
return err;
|
|
||||||
}
|
|
||||||
handle->state = kReceiveDataState;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
handle->state = kIdleState;
|
|
||||||
err = kStatus_I2C_UnexpectedState;
|
|
||||||
return err;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
switch (handle->state)
|
|
||||||
{
|
|
||||||
case kTransmitSubaddrState:
|
|
||||||
if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag))
|
|
||||||
{
|
|
||||||
return kStatus_I2C_UnexpectedState;
|
|
||||||
}
|
|
||||||
|
|
||||||
base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
|
|
||||||
|
|
||||||
/* Prepare and submit DMA transfer. */
|
|
||||||
DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (void *)&base->MSTDAT, sizeof(uint8_t),
|
|
||||||
handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL);
|
|
||||||
DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
|
|
||||||
DMA_StartTransfer(handle->dmaHandle);
|
|
||||||
handle->remainingSubaddr = 0;
|
|
||||||
if (transfer->dataSize)
|
|
||||||
{
|
|
||||||
/* There is data to be transferred, if there is write to read turnaround it is necessary to perform
|
|
||||||
* repeated start */
|
|
||||||
handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* No more data, schedule stop condition */
|
|
||||||
handle->state = kStopState;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case kTransmitDataState:
|
|
||||||
if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag))
|
|
||||||
{
|
|
||||||
return kStatus_I2C_UnexpectedState;
|
|
||||||
}
|
|
||||||
|
|
||||||
base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
|
|
||||||
handle->remainingBytesDMA = handle->transfer.dataSize;
|
|
||||||
|
|
||||||
I2C_RunDMATransfer(base, handle);
|
|
||||||
|
|
||||||
/* Schedule stop condition */
|
|
||||||
handle->state = kStopState;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case kReceiveDataState:
|
|
||||||
if ((master_state != I2C_STAT_MSTCODE_RXREADY) && (!start_flag))
|
|
||||||
{
|
|
||||||
return kStatus_I2C_UnexpectedState;
|
|
||||||
}
|
|
||||||
|
|
||||||
base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
|
|
||||||
handle->remainingBytesDMA = handle->transfer.dataSize - 1;
|
|
||||||
|
|
||||||
I2C_RunDMATransfer(base, handle);
|
|
||||||
|
|
||||||
/* Schedule reception of last data byte */
|
|
||||||
handle->state = kReceiveLastDataState;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case kReceiveLastDataState:
|
|
||||||
if (master_state != I2C_STAT_MSTCODE_RXREADY)
|
|
||||||
{
|
|
||||||
return kStatus_I2C_UnexpectedState;
|
|
||||||
}
|
|
||||||
|
|
||||||
((uint8_t *)transfer->data)[transfer->dataSize - 1] = base->MSTDAT;
|
|
||||||
handle->transferCount++;
|
|
||||||
|
|
||||||
/* No more data expected, issue NACK and STOP right away */
|
|
||||||
base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
|
|
||||||
handle->state = kWaitForCompletionState;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case kStopState:
|
|
||||||
if (transfer->flags & kI2C_TransferNoStopFlag)
|
|
||||||
{
|
|
||||||
/* Stop condition is omitted, we are done */
|
|
||||||
*isDone = true;
|
|
||||||
handle->state = kIdleState;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
/* Send stop condition */
|
|
||||||
base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
|
|
||||||
handle->state = kWaitForCompletionState;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case kWaitForCompletionState:
|
|
||||||
*isDone = true;
|
|
||||||
handle->state = kIdleState;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case kStartState:
|
|
||||||
case kIdleState:
|
|
||||||
default:
|
|
||||||
/* State machine shall not be invoked again once it enters the idle state */
|
|
||||||
err = kStatus_I2C_UnexpectedState;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return err;
|
|
||||||
}
|
|
||||||
|
|
||||||
void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle)
|
|
||||||
{
|
|
||||||
bool isDone;
|
|
||||||
status_t result;
|
|
||||||
|
|
||||||
/* Don't do anything if we don't have a valid handle. */
|
|
||||||
if (!handle)
|
|
||||||
{
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
result = I2C_RunTransferStateMachineDMA(base, handle, &isDone);
|
|
||||||
|
|
||||||
if (isDone || (result != kStatus_Success))
|
|
||||||
{
|
|
||||||
/* Disable internal IRQ enables. */
|
|
||||||
I2C_DisableInterrupts(base,
|
|
||||||
I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
|
|
||||||
|
|
||||||
/* Invoke callback. */
|
|
||||||
if (handle->completionCallback)
|
|
||||||
{
|
|
||||||
handle->completionCallback(base, handle, result, handle->userData);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData)
|
|
||||||
{
|
|
||||||
i2c_master_dma_private_handle_t *dmaPrivateHandle;
|
|
||||||
|
|
||||||
/* Don't do anything if we don't have a valid handle. */
|
|
||||||
if (!handle)
|
|
||||||
{
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData;
|
|
||||||
I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Init the I2C handle which is used in transcational functions
|
|
||||||
*
|
|
||||||
* param base I2C peripheral base address
|
|
||||||
* param handle pointer to i2c_master_dma_handle_t structure
|
|
||||||
* param callback pointer to user callback function
|
|
||||||
* param userData user param passed to the callback function
|
|
||||||
* param dmaHandle DMA handle pointer
|
|
||||||
*/
|
|
||||||
void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
|
|
||||||
i2c_master_dma_handle_t *handle,
|
|
||||||
i2c_master_dma_transfer_callback_t callback,
|
|
||||||
void *userData,
|
|
||||||
dma_handle_t *dmaHandle)
|
|
||||||
{
|
|
||||||
uint32_t instance;
|
|
||||||
|
|
||||||
assert(handle);
|
|
||||||
assert(dmaHandle);
|
|
||||||
|
|
||||||
/* Zero handle. */
|
|
||||||
memset(handle, 0, sizeof(*handle));
|
|
||||||
|
|
||||||
/* Look up instance number */
|
|
||||||
instance = I2C_GetInstance(base);
|
|
||||||
|
|
||||||
/* Set the user callback and userData. */
|
|
||||||
handle->completionCallback = callback;
|
|
||||||
handle->userData = userData;
|
|
||||||
|
|
||||||
FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_MasterTransferDMAHandleIRQ, handle);
|
|
||||||
|
|
||||||
/* Clear internal IRQ enables and enable NVIC IRQ. */
|
|
||||||
I2C_DisableInterrupts(base,
|
|
||||||
I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
|
|
||||||
EnableIRQ(s_i2cIRQ[instance]);
|
|
||||||
|
|
||||||
/* Set the handle for DMA. */
|
|
||||||
handle->dmaHandle = dmaHandle;
|
|
||||||
|
|
||||||
s_dmaPrivateHandle[instance].base = base;
|
|
||||||
s_dmaPrivateHandle[instance].handle = handle;
|
|
||||||
|
|
||||||
DMA_SetCallback(dmaHandle, (dma_callback)I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Performs a master dma non-blocking transfer on the I2C bus
|
|
||||||
*
|
|
||||||
* param base I2C peripheral base address
|
|
||||||
* param handle pointer to i2c_master_dma_handle_t structure
|
|
||||||
* param xfer pointer to transfer structure of i2c_master_transfer_t
|
|
||||||
* retval kStatus_Success Sucessully complete the data transmission.
|
|
||||||
* retval kStatus_I2C_Busy Previous transmission still not finished.
|
|
||||||
* retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
|
|
||||||
* retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
|
|
||||||
* retval kStataus_I2C_Nak Transfer error, receive Nak during transfer.
|
|
||||||
*/
|
|
||||||
status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer)
|
|
||||||
{
|
|
||||||
status_t result;
|
|
||||||
|
|
||||||
assert(handle);
|
|
||||||
assert(xfer);
|
|
||||||
assert(xfer->subaddressSize <= sizeof(xfer->subaddress));
|
|
||||||
|
|
||||||
/* Return busy if another transaction is in progress. */
|
|
||||||
if (handle->state != kIdleState)
|
|
||||||
{
|
|
||||||
return kStatus_I2C_Busy;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Prepare transfer state machine. */
|
|
||||||
result = I2C_InitTransferStateMachineDMA(base, handle, xfer);
|
|
||||||
|
|
||||||
/* Clear error flags. */
|
|
||||||
I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
|
|
||||||
|
|
||||||
/* Enable I2C internal IRQ sources */
|
|
||||||
I2C_EnableInterrupts(base,
|
|
||||||
I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_MSTPENDING_MASK);
|
|
||||||
|
|
||||||
return result;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Get master transfer status during a dma non-blocking transfer
|
|
||||||
*
|
|
||||||
* param base I2C peripheral base address
|
|
||||||
* param handle pointer to i2c_master_dma_handle_t structure
|
|
||||||
* param count Number of bytes transferred so far by the non-blocking transaction.
|
|
||||||
*/
|
|
||||||
status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count)
|
|
||||||
{
|
|
||||||
assert(handle);
|
|
||||||
|
|
||||||
if (!count)
|
|
||||||
{
|
|
||||||
return kStatus_InvalidArgument;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Catch when there is not an active transfer. */
|
|
||||||
if (handle->state == kIdleState)
|
|
||||||
{
|
|
||||||
*count = 0;
|
|
||||||
return kStatus_NoTransferInProgress;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* There is no necessity to disable interrupts as we read a single integer value */
|
|
||||||
*count = handle->transferCount;
|
|
||||||
return kStatus_Success;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Abort a master dma non-blocking transfer in a early time
|
|
||||||
*
|
|
||||||
* param base I2C peripheral base address
|
|
||||||
* param handle pointer to i2c_master_dma_handle_t structure
|
|
||||||
*/
|
|
||||||
void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle)
|
|
||||||
{
|
|
||||||
uint32_t status;
|
|
||||||
uint32_t master_state;
|
|
||||||
|
|
||||||
if (handle->state != kIdleState)
|
|
||||||
{
|
|
||||||
DMA_AbortTransfer(handle->dmaHandle);
|
|
||||||
|
|
||||||
/* Disable DMA */
|
|
||||||
base->MSTCTL = 0;
|
|
||||||
|
|
||||||
/* Disable internal IRQ enables. */
|
|
||||||
I2C_DisableInterrupts(base,
|
|
||||||
I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
|
|
||||||
|
|
||||||
/* Wait until module is ready */
|
|
||||||
do
|
|
||||||
{
|
|
||||||
status = I2C_GetStatusFlags(base);
|
|
||||||
} while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
|
|
||||||
|
|
||||||
/* Clear controller state. */
|
|
||||||
I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
|
|
||||||
|
|
||||||
/* Get the state of the I2C module */
|
|
||||||
master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
|
|
||||||
|
|
||||||
if (master_state != I2C_STAT_MSTCODE_IDLE)
|
|
||||||
{
|
|
||||||
/* Send a stop command to finalize the transfer. */
|
|
||||||
base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
|
|
||||||
|
|
||||||
/* Wait until module is ready */
|
|
||||||
do
|
|
||||||
{
|
|
||||||
status = I2C_GetStatusFlags(base);
|
|
||||||
} while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
|
|
||||||
|
|
||||||
/* Clear controller state. */
|
|
||||||
I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Reset the state to idle. */
|
|
||||||
handle->state = kIdleState;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,120 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
#ifndef _FSL_I2C_DMA_H_
|
|
||||||
#define _FSL_I2C_DMA_H_
|
|
||||||
|
|
||||||
#include "fsl_i2c.h"
|
|
||||||
#include "fsl_dma.h"
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup i2c_dma_driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
/*! @brief I2C DMA driver version 2.0.3. */
|
|
||||||
#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */
|
|
||||||
#define I2C_MAX_DMA_TRANSFER_COUNT 1024
|
|
||||||
|
|
||||||
/*! @brief I2C master dma handle typedef. */
|
|
||||||
typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t;
|
|
||||||
|
|
||||||
/*! @brief I2C master dma transfer callback typedef. */
|
|
||||||
typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base,
|
|
||||||
i2c_master_dma_handle_t *handle,
|
|
||||||
status_t status,
|
|
||||||
void *userData);
|
|
||||||
|
|
||||||
/*! @brief I2C master dma transfer structure. */
|
|
||||||
struct _i2c_master_dma_handle
|
|
||||||
{
|
|
||||||
uint8_t state; /*!< Transfer state machine current state. */
|
|
||||||
uint32_t transferCount; /*!< Indicates progress of the transfer */
|
|
||||||
uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */
|
|
||||||
uint8_t *buf; /*!< Buffer pointer for current state. */
|
|
||||||
uint32_t remainingSubaddr;
|
|
||||||
uint8_t subaddrBuf[4];
|
|
||||||
dma_handle_t *dmaHandle; /*!< The DMA handler used. */
|
|
||||||
i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */
|
|
||||||
i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */
|
|
||||||
void *userData; /*!< Callback parameter passed to callback function. */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif /*_cplusplus. */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name I2C Block DMA Transfer Operation
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Init the I2C handle which is used in transcational functions
|
|
||||||
*
|
|
||||||
* @param base I2C peripheral base address
|
|
||||||
* @param handle pointer to i2c_master_dma_handle_t structure
|
|
||||||
* @param callback pointer to user callback function
|
|
||||||
* @param userData user param passed to the callback function
|
|
||||||
* @param dmaHandle DMA handle pointer
|
|
||||||
*/
|
|
||||||
void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
|
|
||||||
i2c_master_dma_handle_t *handle,
|
|
||||||
i2c_master_dma_transfer_callback_t callback,
|
|
||||||
void *userData,
|
|
||||||
dma_handle_t *dmaHandle);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Performs a master dma non-blocking transfer on the I2C bus
|
|
||||||
*
|
|
||||||
* @param base I2C peripheral base address
|
|
||||||
* @param handle pointer to i2c_master_dma_handle_t structure
|
|
||||||
* @param xfer pointer to transfer structure of i2c_master_transfer_t
|
|
||||||
* @retval kStatus_Success Sucessully complete the data transmission.
|
|
||||||
* @retval kStatus_I2C_Busy Previous transmission still not finished.
|
|
||||||
* @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
|
|
||||||
* @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
|
|
||||||
* @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer.
|
|
||||||
*/
|
|
||||||
status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get master transfer status during a dma non-blocking transfer
|
|
||||||
*
|
|
||||||
* @param base I2C peripheral base address
|
|
||||||
* @param handle pointer to i2c_master_dma_handle_t structure
|
|
||||||
* @param count Number of bytes transferred so far by the non-blocking transaction.
|
|
||||||
*/
|
|
||||||
status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Abort a master dma non-blocking transfer in a early time
|
|
||||||
*
|
|
||||||
* @param base I2C peripheral base address
|
|
||||||
* @param handle pointer to i2c_master_dma_handle_t structure
|
|
||||||
*/
|
|
||||||
void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle);
|
|
||||||
|
|
||||||
/* @} */
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif /*_cplusplus. */
|
|
||||||
/*@}*/
|
|
||||||
#endif /*_FSL_I2C_DMA_H_*/
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,468 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
#ifndef _FSL_I2S_H_
|
|
||||||
#define _FSL_I2S_H_
|
|
||||||
|
|
||||||
#include "fsl_device_registers.h"
|
|
||||||
#include "fsl_common.h"
|
|
||||||
#include "fsl_flexcomm.h"
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup i2s_driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @file */
|
|
||||||
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
/*! @brief I2S driver version 2.0.2.
|
|
||||||
*
|
|
||||||
* Current version: 2.0.2
|
|
||||||
*
|
|
||||||
* Change log:
|
|
||||||
* - Version 2.0.2
|
|
||||||
* - Add ENABLE_IRQ handle after register i2s interrupt handle
|
|
||||||
* - Version 2.0.1
|
|
||||||
* - Unify component full name to FLEXCOMM I2S(DMA) Driver
|
|
||||||
* - Version 2.0.0
|
|
||||||
* - initial version
|
|
||||||
*/
|
|
||||||
#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
#ifndef I2S_NUM_BUFFERS
|
|
||||||
|
|
||||||
/*! @brief Number of buffers . */
|
|
||||||
#define I2S_NUM_BUFFERS (4)
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*! @brief I2S status codes. */
|
|
||||||
enum _i2s_status
|
|
||||||
{
|
|
||||||
kStatus_I2S_BufferComplete =
|
|
||||||
MAKE_STATUS(kStatusGroup_I2S, 0), /*!< Transfer from/into a single buffer has completed */
|
|
||||||
kStatus_I2S_Done = MAKE_STATUS(kStatusGroup_I2S, 1), /*!< All buffers transfers have completed */
|
|
||||||
kStatus_I2S_Busy =
|
|
||||||
MAKE_STATUS(kStatusGroup_I2S, 2), /*!< Already performing a transfer and cannot queue another buffer */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief I2S flags.
|
|
||||||
*
|
|
||||||
* @note These enums are meant to be OR'd together to form a bit mask.
|
|
||||||
*/
|
|
||||||
typedef enum _i2s_flags
|
|
||||||
{
|
|
||||||
kI2S_TxErrorFlag = I2S_FIFOINTENSET_TXERR_MASK, /*!< TX error interrupt */
|
|
||||||
kI2S_TxLevelFlag = I2S_FIFOINTENSET_TXLVL_MASK, /*!< TX level interrupt */
|
|
||||||
kI2S_RxErrorFlag = I2S_FIFOINTENSET_RXERR_MASK, /*!< RX error interrupt */
|
|
||||||
kI2S_RxLevelFlag = I2S_FIFOINTENSET_RXLVL_MASK /*!< RX level interrupt */
|
|
||||||
} i2s_flags_t;
|
|
||||||
|
|
||||||
/*! @brief Master / slave mode. */
|
|
||||||
typedef enum _i2s_master_slave
|
|
||||||
{
|
|
||||||
kI2S_MasterSlaveNormalSlave = 0x0, /*!< Normal slave */
|
|
||||||
kI2S_MasterSlaveWsSyncMaster = 0x1, /*!< WS synchronized master */
|
|
||||||
kI2S_MasterSlaveExtSckMaster = 0x2, /*!< Master using existing SCK */
|
|
||||||
kI2S_MasterSlaveNormalMaster = 0x3 /*!< Normal master */
|
|
||||||
} i2s_master_slave_t;
|
|
||||||
|
|
||||||
/*! @brief I2S mode. */
|
|
||||||
typedef enum _i2s_mode
|
|
||||||
{
|
|
||||||
kI2S_ModeI2sClassic = 0x0, /*!< I2S classic mode */
|
|
||||||
kI2S_ModeDspWs50 = 0x1, /*!< DSP mode, WS having 50% duty cycle */
|
|
||||||
kI2S_ModeDspWsShort = 0x2, /*!< DSP mode, WS having one clock long pulse */
|
|
||||||
kI2S_ModeDspWsLong = 0x3 /*!< DSP mode, WS having one data slot long pulse */
|
|
||||||
} i2s_mode_t;
|
|
||||||
|
|
||||||
/*! @brief I2S configuration structure. */
|
|
||||||
typedef struct _i2s_config
|
|
||||||
{
|
|
||||||
i2s_master_slave_t masterSlave; /*!< Master / slave configuration */
|
|
||||||
i2s_mode_t mode; /*!< I2S mode */
|
|
||||||
bool rightLow; /*!< Right channel data in low portion of FIFO */
|
|
||||||
bool leftJust; /*!< Left justify data in FIFO */
|
|
||||||
#if defined(I2S_CFG1_PDMDATA)
|
|
||||||
bool pdmData; /*!< Data source is the D-Mic subsystem */
|
|
||||||
#endif
|
|
||||||
bool sckPol; /*!< SCK polarity */
|
|
||||||
bool wsPol; /*!< WS polarity */
|
|
||||||
uint16_t divider; /*!< Flexcomm function clock divider (1 - 4096) */
|
|
||||||
bool oneChannel; /*!< true mono, false stereo */
|
|
||||||
uint8_t dataLength; /*!< Data length (4 - 32) */
|
|
||||||
uint16_t frameLength; /*!< Frame width (4 - 512) */
|
|
||||||
uint16_t position; /*!< Data position in the frame */
|
|
||||||
uint8_t watermark; /*!< FIFO trigger level */
|
|
||||||
bool txEmptyZero; /*!< Transmit zero when buffer becomes empty or last item */
|
|
||||||
bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit
|
|
||||||
values) */
|
|
||||||
} i2s_config_t;
|
|
||||||
|
|
||||||
/*! @brief Buffer to transfer from or receive audio data into. */
|
|
||||||
typedef struct _i2s_transfer
|
|
||||||
{
|
|
||||||
volatile uint8_t *data; /*!< Pointer to data buffer. */
|
|
||||||
volatile size_t dataSize; /*!< Buffer size in bytes. */
|
|
||||||
} i2s_transfer_t;
|
|
||||||
|
|
||||||
/*! @brief Transactional state of the intialized transfer or receive I2S operation. */
|
|
||||||
typedef struct _i2s_handle i2s_handle_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Callback function invoked from transactional API
|
|
||||||
* on completion of a single buffer transfer.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param handle pointer to I2S transaction.
|
|
||||||
* @param completionStatus status of the transaction.
|
|
||||||
* @param userData optional pointer to user arguments data.
|
|
||||||
*/
|
|
||||||
typedef void (*i2s_transfer_callback_t)(I2S_Type *base,
|
|
||||||
i2s_handle_t *handle,
|
|
||||||
status_t completionStatus,
|
|
||||||
void *userData);
|
|
||||||
|
|
||||||
/*! @brief Members not to be accessed / modified outside of the driver. */
|
|
||||||
struct _i2s_handle
|
|
||||||
{
|
|
||||||
uint32_t state; /*!< State of transfer */
|
|
||||||
i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */
|
|
||||||
void *userData; /*!< Application data passed to callback */
|
|
||||||
bool oneChannel; /*!< true mono, false stereo */
|
|
||||||
uint8_t dataLength; /*!< Data length (4 - 32) */
|
|
||||||
bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit
|
|
||||||
values) */
|
|
||||||
bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */
|
|
||||||
volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */
|
|
||||||
volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */
|
|
||||||
volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */
|
|
||||||
volatile uint32_t errorCount; /*!< Number of buffer underruns/overruns */
|
|
||||||
volatile uint32_t transferCount; /*!< Number of bytes transferred */
|
|
||||||
volatile uint8_t watermark; /*!< FIFO trigger level */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Initialization and deinitialization
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initializes the FLEXCOMM peripheral for I2S transmit functionality.
|
|
||||||
*
|
|
||||||
* Ungates the FLEXCOMM clock and configures the module
|
|
||||||
* for I2S transmission using a configuration structure.
|
|
||||||
* The configuration structure can be custom filled or set with default values by
|
|
||||||
* I2S_TxGetDefaultConfig().
|
|
||||||
*
|
|
||||||
* @note This API should be called at the beginning of the application to use
|
|
||||||
* the I2S driver.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param config pointer to I2S configuration structure.
|
|
||||||
*/
|
|
||||||
void I2S_TxInit(I2S_Type *base, const i2s_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initializes the FLEXCOMM peripheral for I2S receive functionality.
|
|
||||||
*
|
|
||||||
* Ungates the FLEXCOMM clock and configures the module
|
|
||||||
* for I2S receive using a configuration structure.
|
|
||||||
* The configuration structure can be custom filled or set with default values by
|
|
||||||
* I2S_RxGetDefaultConfig().
|
|
||||||
*
|
|
||||||
* @note This API should be called at the beginning of the application to use
|
|
||||||
* the I2S driver.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param config pointer to I2S configuration structure.
|
|
||||||
*/
|
|
||||||
void I2S_RxInit(I2S_Type *base, const i2s_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Sets the I2S Tx configuration structure to default values.
|
|
||||||
*
|
|
||||||
* This API initializes the configuration structure for use in I2S_TxInit().
|
|
||||||
* The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified
|
|
||||||
* before calling I2S_TxInit().
|
|
||||||
* Example:
|
|
||||||
@code
|
|
||||||
i2s_config_t config;
|
|
||||||
I2S_TxGetDefaultConfig(&config);
|
|
||||||
@endcode
|
|
||||||
*
|
|
||||||
* Default values:
|
|
||||||
* @code
|
|
||||||
* config->masterSlave = kI2S_MasterSlaveNormalMaster;
|
|
||||||
* config->mode = kI2S_ModeI2sClassic;
|
|
||||||
* config->rightLow = false;
|
|
||||||
* config->leftJust = false;
|
|
||||||
* config->pdmData = false;
|
|
||||||
* config->sckPol = false;
|
|
||||||
* config->wsPol = false;
|
|
||||||
* config->divider = 1;
|
|
||||||
* config->oneChannel = false;
|
|
||||||
* config->dataLength = 16;
|
|
||||||
* config->frameLength = 32;
|
|
||||||
* config->position = 0;
|
|
||||||
* config->watermark = 4;
|
|
||||||
* config->txEmptyZero = true;
|
|
||||||
* config->pack48 = false;
|
|
||||||
* @endcode
|
|
||||||
*
|
|
||||||
* @param config pointer to I2S configuration structure.
|
|
||||||
*/
|
|
||||||
void I2S_TxGetDefaultConfig(i2s_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Sets the I2S Rx configuration structure to default values.
|
|
||||||
*
|
|
||||||
* This API initializes the configuration structure for use in I2S_RxInit().
|
|
||||||
* The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified
|
|
||||||
* before calling I2S_RxInit().
|
|
||||||
* Example:
|
|
||||||
@code
|
|
||||||
i2s_config_t config;
|
|
||||||
I2S_RxGetDefaultConfig(&config);
|
|
||||||
@endcode
|
|
||||||
*
|
|
||||||
* Default values:
|
|
||||||
* @code
|
|
||||||
* config->masterSlave = kI2S_MasterSlaveNormalSlave;
|
|
||||||
* config->mode = kI2S_ModeI2sClassic;
|
|
||||||
* config->rightLow = false;
|
|
||||||
* config->leftJust = false;
|
|
||||||
* config->pdmData = false;
|
|
||||||
* config->sckPol = false;
|
|
||||||
* config->wsPol = false;
|
|
||||||
* config->divider = 1;
|
|
||||||
* config->oneChannel = false;
|
|
||||||
* config->dataLength = 16;
|
|
||||||
* config->frameLength = 32;
|
|
||||||
* config->position = 0;
|
|
||||||
* config->watermark = 4;
|
|
||||||
* config->txEmptyZero = false;
|
|
||||||
* config->pack48 = false;
|
|
||||||
* @endcode
|
|
||||||
*
|
|
||||||
* @param config pointer to I2S configuration structure.
|
|
||||||
*/
|
|
||||||
void I2S_RxGetDefaultConfig(i2s_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief De-initializes the I2S peripheral.
|
|
||||||
*
|
|
||||||
* This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit
|
|
||||||
* or I2S_RxInit is called to enable the clock.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
*/
|
|
||||||
void I2S_Deinit(I2S_Type *base);
|
|
||||||
|
|
||||||
/*! @} */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Non-blocking API
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initializes handle for transfer of audio data.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param handle pointer to handle structure.
|
|
||||||
* @param callback function to be called back when transfer is done or fails.
|
|
||||||
* @param userData pointer to data passed to callback.
|
|
||||||
*/
|
|
||||||
void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Begins or queue sending of the given data.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param handle pointer to handle structure.
|
|
||||||
* @param transfer data buffer.
|
|
||||||
*
|
|
||||||
* @retval kStatus_Success
|
|
||||||
* @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers.
|
|
||||||
*/
|
|
||||||
status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Aborts sending of data.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param handle pointer to handle structure.
|
|
||||||
*/
|
|
||||||
void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initializes handle for reception of audio data.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param handle pointer to handle structure.
|
|
||||||
* @param callback function to be called back when transfer is done or fails.
|
|
||||||
* @param userData pointer to data passed to callback.
|
|
||||||
*/
|
|
||||||
void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Begins or queue reception of data into given buffer.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param handle pointer to handle structure.
|
|
||||||
* @param transfer data buffer.
|
|
||||||
*
|
|
||||||
* @retval kStatus_Success
|
|
||||||
* @retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full.
|
|
||||||
*/
|
|
||||||
status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Aborts receiving of data.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param handle pointer to handle structure.
|
|
||||||
*/
|
|
||||||
void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Returns number of bytes transferred so far.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param handle pointer to handle structure.
|
|
||||||
* @param[out] count number of bytes transferred so far by the non-blocking transaction.
|
|
||||||
*
|
|
||||||
* @retval kStatus_Success
|
|
||||||
* @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress.
|
|
||||||
*/
|
|
||||||
status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Returns number of buffer underruns or overruns.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param handle pointer to handle structure.
|
|
||||||
* @param[out] count number of transmit errors encountered so far by the non-blocking transaction.
|
|
||||||
*
|
|
||||||
* @retval kStatus_Success
|
|
||||||
* @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress.
|
|
||||||
*/
|
|
||||||
status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count);
|
|
||||||
|
|
||||||
/*! @} */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Enable / disable
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enables I2S operation.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
*/
|
|
||||||
static inline void I2S_Enable(I2S_Type *base)
|
|
||||||
{
|
|
||||||
base->CFG1 |= I2S_CFG1_MAINENABLE(1U);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Disables I2S operation.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
*/
|
|
||||||
static inline void I2S_Disable(I2S_Type *base)
|
|
||||||
{
|
|
||||||
base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U));
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! @} */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Interrupts
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enables I2S FIFO interrupts.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set
|
|
||||||
* of constants that should be OR'd together to form the bit mask.
|
|
||||||
*/
|
|
||||||
static inline void I2S_EnableInterrupts(I2S_Type *base, uint32_t interruptMask)
|
|
||||||
{
|
|
||||||
base->FIFOINTENSET = interruptMask;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Disables I2S FIFO interrupts.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set
|
|
||||||
* of constants that should be OR'd together to form the bit mask.
|
|
||||||
*/
|
|
||||||
static inline void I2S_DisableInterrupts(I2S_Type *base, uint32_t interruptMask)
|
|
||||||
{
|
|
||||||
base->FIFOINTENCLR = interruptMask;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Returns the set of currently enabled I2S FIFO interrupts.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
*
|
|
||||||
* @return A bitmask composed of #i2s_flags_t enumerators OR'd together
|
|
||||||
* to indicate the set of enabled interrupts.
|
|
||||||
*/
|
|
||||||
static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base)
|
|
||||||
{
|
|
||||||
return base->FIFOINTENSET;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Invoked from interrupt handler when transmit FIFO level decreases.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param handle pointer to handle structure.
|
|
||||||
*/
|
|
||||||
void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Invoked from interrupt handler when receive FIFO level decreases.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param handle pointer to handle structure.
|
|
||||||
*/
|
|
||||||
void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle);
|
|
||||||
|
|
||||||
/*! @} */
|
|
||||||
|
|
||||||
/*! @} */
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* _FSL_I2S_H_ */
|
|
||||||
|
|
@ -1,665 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "fsl_dma.h"
|
|
||||||
#include "fsl_i2s_dma.h"
|
|
||||||
#include "fsl_flexcomm.h"
|
|
||||||
#include <string.h>
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s_dma"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t))
|
|
||||||
#define DMA_DESCRIPTORS (2U)
|
|
||||||
|
|
||||||
/*<! @brief Structure for statically allocated private data. */
|
|
||||||
typedef struct _i2s_dma_private_handle
|
|
||||||
{
|
|
||||||
I2S_Type *base; /*!< I2S base address */
|
|
||||||
i2s_dma_handle_t *handle; /*!< I2S handle */
|
|
||||||
|
|
||||||
volatile uint16_t enqueuedBytes[DMA_DESCRIPTORS]; /*!< Number of bytes being transferred by DMA descriptors */
|
|
||||||
volatile uint8_t enqueuedBytesStart; /*!< First item in enqueuedBytes (for reading) */
|
|
||||||
volatile uint8_t enqueuedBytesEnd; /*!< Last item in enqueuedBytes (for adding) */
|
|
||||||
|
|
||||||
volatile uint8_t
|
|
||||||
dmaDescriptorsUsed; /*!< Number of DMA descriptors with valid data (in queue, excluding initial descriptor) */
|
|
||||||
volatile uint8_t
|
|
||||||
descriptor; /*!< Index of next DMA descriptor in s_DmaDescriptors to be configured with data (does not include
|
|
||||||
I2S instance offset) */
|
|
||||||
|
|
||||||
volatile uint8_t queueDescriptor; /*!< Queue index of buffer to be actually consumed by DMA
|
|
||||||
* (queueUser - advanced when user adds a buffer,
|
|
||||||
* queueDescriptor - advanced when user buffer queued to DMA,
|
|
||||||
* queueDriver - advanced when DMA queued buffer sent out to I2S) */
|
|
||||||
volatile i2s_transfer_t descriptorQueue[I2S_NUM_BUFFERS]; /*!< Transfer data to be queued to DMA */
|
|
||||||
|
|
||||||
volatile bool intA; /*!< If next scheduled DMA transfer will cause interrupt A or B */
|
|
||||||
} i2s_dma_private_handle_t;
|
|
||||||
|
|
||||||
/*! @brief I2S DMA transfer private state. */
|
|
||||||
enum _i2s_dma_state
|
|
||||||
{
|
|
||||||
kI2S_DmaStateIdle = 0x0U, /*!< I2S is in idle state */
|
|
||||||
kI2S_DmaStateTx, /*!< I2S is busy transmitting data */
|
|
||||||
kI2S_DmaStateRx, /*!< I2S is busy receiving data */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Prototypes
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
static status_t I2S_EnqueueUserBuffer(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer);
|
|
||||||
static uint32_t I2S_GetInstance(I2S_Type *base);
|
|
||||||
static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle);
|
|
||||||
static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle);
|
|
||||||
static void I2S_TxEnableDMA(I2S_Type *base, bool enable);
|
|
||||||
static void I2S_RxEnableDMA(I2S_Type *base, bool enable);
|
|
||||||
static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer);
|
|
||||||
static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle);
|
|
||||||
static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle);
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*<! @brief DMA transfer descriptors. */
|
|
||||||
#if defined(__ICCARM__)
|
|
||||||
#pragma data_alignment = 16
|
|
||||||
static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
|
|
||||||
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
|
||||||
__attribute__((aligned(16))) static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
|
|
||||||
#elif defined(__GNUC__)
|
|
||||||
__attribute__((aligned(16))) static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*<! @brief Buffer with dummy TX data. */
|
|
||||||
#if defined(__ICCARM__)
|
|
||||||
#pragma data_alignment = 4
|
|
||||||
static uint32_t s_DummyBufferTx = 0U;
|
|
||||||
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
|
||||||
__attribute__((aligned(4))) static uint32_t s_DummyBufferTx = 0U;
|
|
||||||
#elif defined(__GNUC__)
|
|
||||||
__attribute__((aligned(4))) static uint32_t s_DummyBufferTx = 0U;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*<! @brief Buffer to fill with RX data to discard. */
|
|
||||||
#if defined(__ICCARM__)
|
|
||||||
#pragma data_alignment = 4
|
|
||||||
static uint32_t s_DummyBufferRx = 0U;
|
|
||||||
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
|
||||||
__attribute__((aligned(4))) static uint32_t s_DummyBufferRx = 0U;
|
|
||||||
#elif defined(__GNUC__)
|
|
||||||
__attribute__((aligned(4))) static uint32_t s_DummyBufferRx = 0U;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*<! @brief Private array of data associated with available I2S peripherals. */
|
|
||||||
static i2s_dma_private_handle_t s_DmaPrivateHandle[FSL_FEATURE_SOC_I2S_COUNT];
|
|
||||||
|
|
||||||
/*<! @brief Base addresses of available I2S peripherals. */
|
|
||||||
static const uint32_t s_I2sBaseAddrs[FSL_FEATURE_SOC_I2S_COUNT] = I2S_BASE_ADDRS;
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
static status_t I2S_EnqueueUserBuffer(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
|
|
||||||
{
|
|
||||||
uint32_t instance = I2S_GetInstance(base);
|
|
||||||
i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
|
|
||||||
|
|
||||||
/* Validate input data and tranfer buffer */
|
|
||||||
|
|
||||||
assert(handle);
|
|
||||||
if (!handle)
|
|
||||||
{
|
|
||||||
return kStatus_InvalidArgument;
|
|
||||||
}
|
|
||||||
|
|
||||||
assert((((uint32_t)transfer.data) % 4U) == 0U);
|
|
||||||
if ((((uint32_t)transfer.data) % 4U) != 0U)
|
|
||||||
{
|
|
||||||
/* Data not 4-bytes aligned */
|
|
||||||
return kStatus_InvalidArgument;
|
|
||||||
}
|
|
||||||
|
|
||||||
assert(transfer.dataSize != 0U);
|
|
||||||
if (transfer.dataSize == 0U)
|
|
||||||
{
|
|
||||||
/* No data to send or receive */
|
|
||||||
return kStatus_InvalidArgument;
|
|
||||||
}
|
|
||||||
|
|
||||||
assert((transfer.dataSize % 4U) == 0U);
|
|
||||||
if ((transfer.dataSize % 4U) != 0U)
|
|
||||||
{
|
|
||||||
/* Data length not multiply of 4 bytes */
|
|
||||||
return kStatus_InvalidArgument;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (handle->i2sQueue[handle->queueUser].dataSize)
|
|
||||||
{
|
|
||||||
/* Previously prepared buffers not processed yet, reject request */
|
|
||||||
return kStatus_I2S_Busy;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Enqueue data */
|
|
||||||
privateHandle->descriptorQueue[handle->queueUser].data = transfer.data;
|
|
||||||
privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize;
|
|
||||||
handle->i2sQueue[handle->queueUser].data = transfer.data;
|
|
||||||
handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize;
|
|
||||||
handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS;
|
|
||||||
|
|
||||||
return kStatus_Success;
|
|
||||||
}
|
|
||||||
|
|
||||||
static uint32_t I2S_GetInstance(I2S_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
for (i = 0U; i < ARRAY_SIZE(s_I2sBaseAddrs); i++)
|
|
||||||
{
|
|
||||||
if ((uint32_t)base == s_I2sBaseAddrs[i])
|
|
||||||
{
|
|
||||||
return i;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
assert(false);
|
|
||||||
return 0U;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle)
|
|
||||||
{
|
|
||||||
DMA_DisableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle)
|
|
||||||
{
|
|
||||||
if (handle->state != kI2S_DmaStateIdle)
|
|
||||||
{
|
|
||||||
DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Initializes handle for transfer of audio data.
|
|
||||||
*
|
|
||||||
* param base I2S base pointer.
|
|
||||||
* param handle pointer to handle structure.
|
|
||||||
* param dmaHandle pointer to dma handle structure.
|
|
||||||
* param callback function to be called back when transfer is done or fails.
|
|
||||||
* param userData pointer to data passed to callback.
|
|
||||||
*/
|
|
||||||
void I2S_TxTransferCreateHandleDMA(I2S_Type *base,
|
|
||||||
i2s_dma_handle_t *handle,
|
|
||||||
dma_handle_t *dmaHandle,
|
|
||||||
i2s_dma_transfer_callback_t callback,
|
|
||||||
void *userData)
|
|
||||||
{
|
|
||||||
assert(handle);
|
|
||||||
assert(dmaHandle);
|
|
||||||
|
|
||||||
uint32_t instance = I2S_GetInstance(base);
|
|
||||||
i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
|
|
||||||
|
|
||||||
memset(handle, 0U, sizeof(*handle));
|
|
||||||
handle->state = kI2S_DmaStateIdle;
|
|
||||||
handle->dmaHandle = dmaHandle;
|
|
||||||
handle->completionCallback = callback;
|
|
||||||
handle->userData = userData;
|
|
||||||
|
|
||||||
memset(privateHandle, 0U, sizeof(*privateHandle));
|
|
||||||
privateHandle->base = base;
|
|
||||||
privateHandle->handle = handle;
|
|
||||||
|
|
||||||
DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Begins or queue sending of the given data.
|
|
||||||
*
|
|
||||||
* param base I2S base pointer.
|
|
||||||
* param handle pointer to handle structure.
|
|
||||||
* param transfer data buffer.
|
|
||||||
*
|
|
||||||
* retval kStatus_Success
|
|
||||||
* retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers.
|
|
||||||
*/
|
|
||||||
status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
|
|
||||||
{
|
|
||||||
status_t status;
|
|
||||||
|
|
||||||
I2S_DisableDMAInterrupts(handle);
|
|
||||||
|
|
||||||
/* Enqueue transfer buffer */
|
|
||||||
status = I2S_EnqueueUserBuffer(base, handle, transfer);
|
|
||||||
if (status != kStatus_Success)
|
|
||||||
{
|
|
||||||
I2S_EnableDMAInterrupts(handle);
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Initialize DMA transfer */
|
|
||||||
if (handle->state == kI2S_DmaStateIdle)
|
|
||||||
{
|
|
||||||
handle->state = kI2S_DmaStateTx;
|
|
||||||
status = I2S_StartTransferDMA(base, handle);
|
|
||||||
if (status != kStatus_Success)
|
|
||||||
{
|
|
||||||
I2S_EnableDMAInterrupts(handle);
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
I2S_AddTransferDMA(base, handle);
|
|
||||||
I2S_EnableDMAInterrupts(handle);
|
|
||||||
|
|
||||||
return kStatus_Success;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Aborts transfer of data.
|
|
||||||
*
|
|
||||||
* param base I2S base pointer.
|
|
||||||
* param handle pointer to handle structure.
|
|
||||||
*/
|
|
||||||
void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle)
|
|
||||||
{
|
|
||||||
assert(handle);
|
|
||||||
assert(handle->dmaHandle);
|
|
||||||
|
|
||||||
uint32_t instance = I2S_GetInstance(base);
|
|
||||||
i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
|
|
||||||
|
|
||||||
I2S_DisableDMAInterrupts(handle);
|
|
||||||
|
|
||||||
/* Abort operation */
|
|
||||||
DMA_AbortTransfer(handle->dmaHandle);
|
|
||||||
|
|
||||||
if (handle->state == kI2S_DmaStateTx)
|
|
||||||
{
|
|
||||||
/* Wait until all transmitted data get out of FIFO */
|
|
||||||
while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
/* The last piece of valid data can be still being transmitted from I2S at this moment */
|
|
||||||
|
|
||||||
/* Write additional data to FIFO */
|
|
||||||
base->FIFOWR = 0U;
|
|
||||||
while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
/* At this moment the additional data are out of FIFO, starting being transmitted.
|
|
||||||
* This means the preceding valid data has been just transmitted and we can stop I2S. */
|
|
||||||
I2S_TxEnableDMA(base, false);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
I2S_RxEnableDMA(base, false);
|
|
||||||
}
|
|
||||||
|
|
||||||
I2S_Disable(base);
|
|
||||||
|
|
||||||
/* Reset state */
|
|
||||||
handle->state = kI2S_DmaStateIdle;
|
|
||||||
|
|
||||||
/* Clear transfer queue */
|
|
||||||
memset((void *)&(handle->i2sQueue), 0U, sizeof(handle->i2sQueue));
|
|
||||||
handle->queueDriver = 0U;
|
|
||||||
handle->queueUser = 0U;
|
|
||||||
|
|
||||||
/* Clear internal state */
|
|
||||||
memset((void *)&(privateHandle->descriptorQueue), 0U, sizeof(privateHandle->descriptorQueue));
|
|
||||||
memset((void *)&(privateHandle->enqueuedBytes), 0U, sizeof(privateHandle->enqueuedBytes));
|
|
||||||
privateHandle->enqueuedBytesStart = 0U;
|
|
||||||
privateHandle->enqueuedBytesEnd = 0U;
|
|
||||||
privateHandle->dmaDescriptorsUsed = 0U;
|
|
||||||
privateHandle->descriptor = 0U;
|
|
||||||
privateHandle->queueDescriptor = 0U;
|
|
||||||
privateHandle->intA = false;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Initializes handle for reception of audio data.
|
|
||||||
*
|
|
||||||
* param base I2S base pointer.
|
|
||||||
* param handle pointer to handle structure.
|
|
||||||
* param dmaHandle pointer to dma handle structure.
|
|
||||||
* param callback function to be called back when transfer is done or fails.
|
|
||||||
* param userData pointer to data passed to callback.
|
|
||||||
*/
|
|
||||||
void I2S_RxTransferCreateHandleDMA(I2S_Type *base,
|
|
||||||
i2s_dma_handle_t *handle,
|
|
||||||
dma_handle_t *dmaHandle,
|
|
||||||
i2s_dma_transfer_callback_t callback,
|
|
||||||
void *userData)
|
|
||||||
{
|
|
||||||
I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Begins or queue reception of data into given buffer.
|
|
||||||
*
|
|
||||||
* param base I2S base pointer.
|
|
||||||
* param handle pointer to handle structure.
|
|
||||||
* param transfer data buffer.
|
|
||||||
*
|
|
||||||
* retval kStatus_Success
|
|
||||||
* retval kStatus_I2S_Busy if all queue slots are occupied with buffers
|
|
||||||
* which are not full.
|
|
||||||
*/
|
|
||||||
status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
|
|
||||||
{
|
|
||||||
status_t status;
|
|
||||||
|
|
||||||
I2S_DisableDMAInterrupts(handle);
|
|
||||||
|
|
||||||
/* Enqueue transfer buffer */
|
|
||||||
status = I2S_EnqueueUserBuffer(base, handle, transfer);
|
|
||||||
if (status != kStatus_Success)
|
|
||||||
{
|
|
||||||
I2S_EnableDMAInterrupts(handle);
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Initialize DMA transfer */
|
|
||||||
if (handle->state == kI2S_DmaStateIdle)
|
|
||||||
{
|
|
||||||
handle->state = kI2S_DmaStateRx;
|
|
||||||
status = I2S_StartTransferDMA(base, handle);
|
|
||||||
if (status != kStatus_Success)
|
|
||||||
{
|
|
||||||
I2S_EnableDMAInterrupts(handle);
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
I2S_AddTransferDMA(base, handle);
|
|
||||||
I2S_EnableDMAInterrupts(handle);
|
|
||||||
|
|
||||||
return kStatus_Success;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void I2S_TxEnableDMA(I2S_Type *base, bool enable)
|
|
||||||
{
|
|
||||||
if (enable)
|
|
||||||
{
|
|
||||||
base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK);
|
|
||||||
base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void I2S_RxEnableDMA(I2S_Type *base, bool enable)
|
|
||||||
{
|
|
||||||
if (enable)
|
|
||||||
{
|
|
||||||
base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK);
|
|
||||||
base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer)
|
|
||||||
{
|
|
||||||
assert(transfer);
|
|
||||||
|
|
||||||
uint16_t transferBytes;
|
|
||||||
|
|
||||||
if (transfer->dataSize >= (2 * DMA_MAX_TRANSFER_BYTES))
|
|
||||||
{
|
|
||||||
transferBytes = DMA_MAX_TRANSFER_BYTES;
|
|
||||||
}
|
|
||||||
else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES)
|
|
||||||
{
|
|
||||||
transferBytes = transfer->dataSize / 2U;
|
|
||||||
if ((transferBytes % 4U) != 0U)
|
|
||||||
{
|
|
||||||
transferBytes -= (transferBytes % 4U);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
transferBytes = transfer->dataSize;
|
|
||||||
}
|
|
||||||
|
|
||||||
return transferBytes;
|
|
||||||
}
|
|
||||||
|
|
||||||
static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle)
|
|
||||||
{
|
|
||||||
status_t status;
|
|
||||||
dma_transfer_config_t xferConfig = {0};
|
|
||||||
i2s_dma_private_handle_t *privateHandle;
|
|
||||||
volatile i2s_transfer_t *transfer;
|
|
||||||
uint16_t transferBytes;
|
|
||||||
uint32_t instance;
|
|
||||||
int i;
|
|
||||||
dma_descriptor_t *descriptor;
|
|
||||||
dma_descriptor_t *nextDescriptor;
|
|
||||||
dma_xfercfg_t xfercfg;
|
|
||||||
|
|
||||||
instance = I2S_GetInstance(base);
|
|
||||||
privateHandle = &(s_DmaPrivateHandle[instance]);
|
|
||||||
transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]);
|
|
||||||
|
|
||||||
transferBytes = I2S_GetTransferBytes(transfer);
|
|
||||||
|
|
||||||
/* Prepare transfer of data via initial DMA transfer descriptor */
|
|
||||||
DMA_PrepareTransfer(
|
|
||||||
&xferConfig,
|
|
||||||
(void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)transfer->data : (uint32_t)(&(base->FIFORD))),
|
|
||||||
(void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)(&(base->FIFOWR)) : (uint32_t)transfer->data),
|
|
||||||
sizeof(uint32_t), transferBytes,
|
|
||||||
(handle->state == kI2S_DmaStateTx) ? kDMA_MemoryToPeripheral : kDMA_PeripheralToMemory,
|
|
||||||
(void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U]));
|
|
||||||
|
|
||||||
/* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */
|
|
||||||
privateHandle->dmaDescriptorsUsed = 1U;
|
|
||||||
privateHandle->intA = false;
|
|
||||||
|
|
||||||
privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes;
|
|
||||||
privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS;
|
|
||||||
|
|
||||||
transfer->dataSize -= transferBytes;
|
|
||||||
transfer->data += transferBytes;
|
|
||||||
|
|
||||||
if (transfer->dataSize == 0U)
|
|
||||||
{
|
|
||||||
transfer->data = NULL;
|
|
||||||
privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Link the DMA descriptors for the case when no additional transfer is queued before the initial one finishes */
|
|
||||||
for (i = 0; i < DMA_DESCRIPTORS; i++)
|
|
||||||
{
|
|
||||||
descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]);
|
|
||||||
nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1) % DMA_DESCRIPTORS)]);
|
|
||||||
|
|
||||||
xfercfg.valid = true;
|
|
||||||
xfercfg.reload = true;
|
|
||||||
xfercfg.swtrig = false;
|
|
||||||
xfercfg.clrtrig = false;
|
|
||||||
xfercfg.intA = false;
|
|
||||||
xfercfg.intB = false;
|
|
||||||
xfercfg.byteWidth = sizeof(uint32_t);
|
|
||||||
xfercfg.srcInc = 0U;
|
|
||||||
xfercfg.dstInc = 0U;
|
|
||||||
xfercfg.transferCount = 8U;
|
|
||||||
|
|
||||||
DMA_CreateDescriptor(
|
|
||||||
descriptor, &xfercfg,
|
|
||||||
((handle->state == kI2S_DmaStateTx) ? (void *)&s_DummyBufferTx : (void *)(uint32_t)(&(base->FIFORD))),
|
|
||||||
((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t)(&(base->FIFOWR)) : (void *)&s_DummyBufferRx),
|
|
||||||
(void *)nextDescriptor);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Submit and start initial DMA transfer */
|
|
||||||
|
|
||||||
if (handle->state == kI2S_DmaStateTx)
|
|
||||||
{
|
|
||||||
I2S_TxEnableDMA(base, true);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
I2S_RxEnableDMA(base, true);
|
|
||||||
}
|
|
||||||
|
|
||||||
status = DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
|
|
||||||
if (status != kStatus_Success)
|
|
||||||
{
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
|
|
||||||
DMA_StartTransfer(handle->dmaHandle);
|
|
||||||
|
|
||||||
I2S_Enable(base);
|
|
||||||
return kStatus_Success;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle)
|
|
||||||
{
|
|
||||||
dma_xfercfg_t xfercfg;
|
|
||||||
volatile i2s_transfer_t *transfer;
|
|
||||||
uint16_t transferBytes;
|
|
||||||
uint32_t instance;
|
|
||||||
i2s_dma_private_handle_t *privateHandle;
|
|
||||||
dma_descriptor_t *descriptor;
|
|
||||||
dma_descriptor_t *nextDescriptor;
|
|
||||||
uint32_t srcAddr = 0, destAddr = 0;
|
|
||||||
|
|
||||||
instance = I2S_GetInstance(base);
|
|
||||||
privateHandle = &(s_DmaPrivateHandle[instance]);
|
|
||||||
|
|
||||||
while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS)
|
|
||||||
{
|
|
||||||
transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]);
|
|
||||||
|
|
||||||
if (transfer->dataSize == 0U)
|
|
||||||
{
|
|
||||||
/* Nothing to be added */
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Determine currently configured descriptor and the other which it will link to */
|
|
||||||
descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]);
|
|
||||||
privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS;
|
|
||||||
nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]);
|
|
||||||
|
|
||||||
transferBytes = I2S_GetTransferBytes(transfer);
|
|
||||||
privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes;
|
|
||||||
privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS;
|
|
||||||
|
|
||||||
/* Configure descriptor */
|
|
||||||
|
|
||||||
xfercfg.valid = true;
|
|
||||||
xfercfg.reload = true;
|
|
||||||
xfercfg.swtrig = false;
|
|
||||||
xfercfg.clrtrig = false;
|
|
||||||
xfercfg.intA = privateHandle->intA;
|
|
||||||
xfercfg.intB = !privateHandle->intA;
|
|
||||||
xfercfg.byteWidth = sizeof(uint32_t);
|
|
||||||
xfercfg.srcInc = (handle->state == kI2S_DmaStateTx) ? 1U : 0U;
|
|
||||||
xfercfg.dstInc = (handle->state == kI2S_DmaStateTx) ? 0U : 1U;
|
|
||||||
xfercfg.transferCount = transferBytes / sizeof(uint32_t);
|
|
||||||
srcAddr = ((handle->state == kI2S_DmaStateTx) ? (uint32_t)transfer->data : (uint32_t) & (base->FIFORD));
|
|
||||||
destAddr = ((handle->state == kI2S_DmaStateTx) ? (uint32_t) & (base->FIFOWR) : (uint32_t)transfer->data);
|
|
||||||
|
|
||||||
DMA_CreateDescriptor(descriptor, &xfercfg, (void *)srcAddr, (void *)destAddr, (void *)nextDescriptor);
|
|
||||||
|
|
||||||
/* Advance internal state */
|
|
||||||
|
|
||||||
privateHandle->dmaDescriptorsUsed++;
|
|
||||||
privateHandle->intA = !privateHandle->intA;
|
|
||||||
|
|
||||||
transfer->dataSize -= transferBytes;
|
|
||||||
transfer->data += transferBytes;
|
|
||||||
if (transfer->dataSize == 0U)
|
|
||||||
{
|
|
||||||
transfer->data = NULL;
|
|
||||||
privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Invoked from DMA interrupt handler.
|
|
||||||
*
|
|
||||||
* param handle pointer to DMA handle structure.
|
|
||||||
* param userData argument for user callback.
|
|
||||||
* param transferDone if transfer was done.
|
|
||||||
* param tcds
|
|
||||||
*/
|
|
||||||
void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds)
|
|
||||||
{
|
|
||||||
i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData;
|
|
||||||
i2s_dma_handle_t *i2sHandle = privateHandle->handle;
|
|
||||||
I2S_Type *base = privateHandle->base;
|
|
||||||
|
|
||||||
if ((!transferDone) || (i2sHandle->state == kI2S_DmaStateIdle))
|
|
||||||
{
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (privateHandle->dmaDescriptorsUsed > 0U)
|
|
||||||
{
|
|
||||||
/* Finished descriptor, decrease amount of data to be processed */
|
|
||||||
|
|
||||||
i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize -=
|
|
||||||
privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart];
|
|
||||||
i2sHandle->i2sQueue[i2sHandle->queueDriver].data +=
|
|
||||||
privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart];
|
|
||||||
privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U;
|
|
||||||
privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS;
|
|
||||||
|
|
||||||
privateHandle->dmaDescriptorsUsed--;
|
|
||||||
|
|
||||||
if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U)
|
|
||||||
{
|
|
||||||
/* Entire user buffer sent or received - advance to next one */
|
|
||||||
i2sHandle->i2sQueue[i2sHandle->queueDriver].data = NULL;
|
|
||||||
i2sHandle->queueDriver = (i2sHandle->queueDriver + 1U) % I2S_NUM_BUFFERS;
|
|
||||||
|
|
||||||
/* Notify user about buffer completion */
|
|
||||||
if (i2sHandle->completionCallback)
|
|
||||||
{
|
|
||||||
(i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U)
|
|
||||||
{
|
|
||||||
/* All user buffers processed */
|
|
||||||
I2S_TransferAbortDMA(base, i2sHandle);
|
|
||||||
|
|
||||||
/* Notify user about completion of the final buffer */
|
|
||||||
if (i2sHandle->completionCallback)
|
|
||||||
{
|
|
||||||
(i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_Done, i2sHandle->userData);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */
|
|
||||||
I2S_AddTransferDMA(base, i2sHandle);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,161 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
#ifndef _FSL_I2S_DMA_H_
|
|
||||||
#define _FSL_I2S_DMA_H_
|
|
||||||
|
|
||||||
#include "fsl_device_registers.h"
|
|
||||||
#include "fsl_common.h"
|
|
||||||
#include "fsl_flexcomm.h"
|
|
||||||
|
|
||||||
#include "fsl_dma.h"
|
|
||||||
#include "fsl_i2s.h"
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup i2s_dma_driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
/*! @brief I2S DMA driver version 2.0.1. */
|
|
||||||
#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*! @brief Members not to be accessed / modified outside of the driver. */
|
|
||||||
typedef struct _i2s_dma_handle i2s_dma_handle_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Callback function invoked from DMA API on completion.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param handle pointer to I2S transaction.
|
|
||||||
* @param completionStatus status of the transaction.
|
|
||||||
* @param userData optional pointer to user arguments data.
|
|
||||||
*/
|
|
||||||
typedef void (*i2s_dma_transfer_callback_t)(I2S_Type *base,
|
|
||||||
i2s_dma_handle_t *handle,
|
|
||||||
status_t completionStatus,
|
|
||||||
void *userData);
|
|
||||||
|
|
||||||
struct _i2s_dma_handle
|
|
||||||
{
|
|
||||||
uint32_t state; /*!< Internal state of I2S DMA transfer */
|
|
||||||
i2s_dma_transfer_callback_t completionCallback; /*!< Callback function pointer */
|
|
||||||
void *userData; /*!< Application data passed to callback */
|
|
||||||
dma_handle_t *dmaHandle; /*!< DMA handle */
|
|
||||||
volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */
|
|
||||||
volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */
|
|
||||||
volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Initialization and deinitialization
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @} */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name DMA API
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initializes handle for transfer of audio data.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param handle pointer to handle structure.
|
|
||||||
* @param dmaHandle pointer to dma handle structure.
|
|
||||||
* @param callback function to be called back when transfer is done or fails.
|
|
||||||
* @param userData pointer to data passed to callback.
|
|
||||||
*/
|
|
||||||
void I2S_TxTransferCreateHandleDMA(I2S_Type *base,
|
|
||||||
i2s_dma_handle_t *handle,
|
|
||||||
dma_handle_t *dmaHandle,
|
|
||||||
i2s_dma_transfer_callback_t callback,
|
|
||||||
void *userData);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Begins or queue sending of the given data.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param handle pointer to handle structure.
|
|
||||||
* @param transfer data buffer.
|
|
||||||
*
|
|
||||||
* @retval kStatus_Success
|
|
||||||
* @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers.
|
|
||||||
*/
|
|
||||||
status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Aborts transfer of data.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param handle pointer to handle structure.
|
|
||||||
*/
|
|
||||||
void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initializes handle for reception of audio data.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param handle pointer to handle structure.
|
|
||||||
* @param dmaHandle pointer to dma handle structure.
|
|
||||||
* @param callback function to be called back when transfer is done or fails.
|
|
||||||
* @param userData pointer to data passed to callback.
|
|
||||||
*/
|
|
||||||
void I2S_RxTransferCreateHandleDMA(I2S_Type *base,
|
|
||||||
i2s_dma_handle_t *handle,
|
|
||||||
dma_handle_t *dmaHandle,
|
|
||||||
i2s_dma_transfer_callback_t callback,
|
|
||||||
void *userData);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Begins or queue reception of data into given buffer.
|
|
||||||
*
|
|
||||||
* @param base I2S base pointer.
|
|
||||||
* @param handle pointer to handle structure.
|
|
||||||
* @param transfer data buffer.
|
|
||||||
*
|
|
||||||
* @retval kStatus_Success
|
|
||||||
* @retval kStatus_I2S_Busy if all queue slots are occupied with buffers
|
|
||||||
* which are not full.
|
|
||||||
*/
|
|
||||||
status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Invoked from DMA interrupt handler.
|
|
||||||
*
|
|
||||||
* @param handle pointer to DMA handle structure.
|
|
||||||
* @param userData argument for user callback.
|
|
||||||
* @param transferDone if transfer was done.
|
|
||||||
* @param tcds
|
|
||||||
*/
|
|
||||||
void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds);
|
|
||||||
|
|
||||||
/*! @} */
|
|
||||||
|
|
||||||
/*! @} */
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* _FSL_I2S_DMA_H_ */
|
|
||||||
|
|
@ -1,289 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "fsl_iap.h"
|
|
||||||
#include "fsl_iap_ffr.h"
|
|
||||||
#include "fsl_device_registers.h"
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.iap1"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup flash_driver_api
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define ROM_API_TREE ((uint32_t *)0x130010f0)
|
|
||||||
#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)ROM_API_TREE)
|
|
||||||
|
|
||||||
static uint32_t S_Version_minor = 0;
|
|
||||||
|
|
||||||
typedef status_t (*EraseCommend_t)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key);
|
|
||||||
typedef status_t (*ProgramCommend_t)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
|
|
||||||
typedef status_t (*VerifyProgramCommend_t)(flash_config_t *config,
|
|
||||||
uint32_t start,
|
|
||||||
uint32_t lengthInBytes,
|
|
||||||
const uint8_t *expectedData,
|
|
||||||
uint32_t *failedAddress,
|
|
||||||
uint32_t *failedData);
|
|
||||||
typedef status_t (*FFR_CustomerPagesInit_t)(flash_config_t *config);
|
|
||||||
typedef status_t (*FFR_InfieldPageWrite_t)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len);
|
|
||||||
typedef status_t (*FFR_GetManufactureData_t)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
|
|
||||||
typedef status_t (*FFR_GetRompatchData_t)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
|
|
||||||
|
|
||||||
/*
|
|
||||||
*!@brief Structure of version property.
|
|
||||||
*
|
|
||||||
*!@ingroup bl_core
|
|
||||||
*/
|
|
||||||
typedef union BootloaderVersion
|
|
||||||
{
|
|
||||||
struct
|
|
||||||
{
|
|
||||||
uint32_t bugfix : 8; /*!< bugfix version [7:0] */
|
|
||||||
uint32_t minor : 8; /*!< minor version [15:8] */
|
|
||||||
uint32_t major : 8; /*!< major version [23:16] */
|
|
||||||
uint32_t name : 8; /*!< name [31:24] */
|
|
||||||
} B;
|
|
||||||
uint32_t version; /*!< combined version numbers. */
|
|
||||||
} standard_version_t;
|
|
||||||
|
|
||||||
/*! @brief Interface for the flash driver.*/
|
|
||||||
typedef struct FlashDriverInterface
|
|
||||||
{
|
|
||||||
standard_version_t version; /*!< flash driver API version number.*/
|
|
||||||
|
|
||||||
/*!< Flash driver.*/
|
|
||||||
status_t (*flash_init)(flash_config_t *config);
|
|
||||||
status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key);
|
|
||||||
status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
|
|
||||||
status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes);
|
|
||||||
status_t (*flash_verify_program)(flash_config_t *config,
|
|
||||||
uint32_t start,
|
|
||||||
uint32_t lengthInBytes,
|
|
||||||
const uint8_t *expectedData,
|
|
||||||
uint32_t *failedAddress,
|
|
||||||
uint32_t *failedData);
|
|
||||||
status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value);
|
|
||||||
/*!< Flash FFR driver*/
|
|
||||||
status_t (*ffr_init)(flash_config_t *config);
|
|
||||||
status_t (*ffr_deinit)(flash_config_t *config);
|
|
||||||
status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part);
|
|
||||||
status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid);
|
|
||||||
status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
|
|
||||||
status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore);
|
|
||||||
status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode);
|
|
||||||
status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex);
|
|
||||||
status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len);
|
|
||||||
status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
|
|
||||||
} flash_driver_interface_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Root of the bootloader API tree.
|
|
||||||
*
|
|
||||||
* An instance of this struct resides in read-only memory in the bootloader. It
|
|
||||||
* provides a user application access to APIs exported by the bootloader.
|
|
||||||
*
|
|
||||||
* @note The order of existing fields must not be changed.
|
|
||||||
*/
|
|
||||||
typedef struct BootloaderTree
|
|
||||||
{
|
|
||||||
void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing. */
|
|
||||||
standard_version_t bootloader_version; /*!< Bootloader version number. */
|
|
||||||
const char *copyright; /*!< Copyright string. */
|
|
||||||
const uint32_t *reserved; /*!< Do NOT use. */
|
|
||||||
const flash_driver_interface_t *flashDriver; /*!< Flash driver API. */
|
|
||||||
} bootloader_tree_t;
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*! @brief Global pointer to the flash driver API table in ROM. */
|
|
||||||
flash_driver_interface_t *FLASH_API_TREE;
|
|
||||||
/*! Get pointer to flash driver API table in ROM. */
|
|
||||||
#define FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*! See fsl_flash.h for documentation of this function. */
|
|
||||||
status_t FLASH_Init(flash_config_t *config)
|
|
||||||
{
|
|
||||||
assert(FLASH_API_TREE);
|
|
||||||
config->modeConfig.sysFreqInMHz = kSysToFlashFreq_defaultInMHz;
|
|
||||||
S_Version_minor = FLASH_API_TREE->version.B.minor;
|
|
||||||
return FLASH_API_TREE->flash_init(config);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! See fsl_flash.h for documentation of this function. */
|
|
||||||
status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key)
|
|
||||||
{
|
|
||||||
if (S_Version_minor == 0)
|
|
||||||
{
|
|
||||||
EraseCommend_t EraseCommand =
|
|
||||||
(EraseCommend_t)(0x1300413b); /*!< get the flash erase api location adress int rom */
|
|
||||||
return EraseCommand(config, start, lengthInBytes, key);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
assert(FLASH_API_TREE);
|
|
||||||
return FLASH_API_TREE->flash_erase(config, start, lengthInBytes, key);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! See fsl_flash.h for documentation of this function. */
|
|
||||||
status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes)
|
|
||||||
{
|
|
||||||
if (S_Version_minor == 0)
|
|
||||||
{
|
|
||||||
ProgramCommend_t ProgramCommend =
|
|
||||||
(ProgramCommend_t)(0x1300419d); /*!< get the flash program api location adress in rom*/
|
|
||||||
return ProgramCommend(config, start, src, lengthInBytes);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
assert(FLASH_API_TREE);
|
|
||||||
return FLASH_API_TREE->flash_program(config, start, src, lengthInBytes);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! See fsl_flash.h for documentation of this function. */
|
|
||||||
status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes)
|
|
||||||
{
|
|
||||||
assert(FLASH_API_TREE);
|
|
||||||
return FLASH_API_TREE->flash_verify_erase(config, start, lengthInBytes);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! See fsl_flash.h for documentation of this function. */
|
|
||||||
status_t FLASH_VerifyProgram(flash_config_t *config,
|
|
||||||
uint32_t start,
|
|
||||||
uint32_t lengthInBytes,
|
|
||||||
const uint8_t *expectedData,
|
|
||||||
uint32_t *failedAddress,
|
|
||||||
uint32_t *failedData)
|
|
||||||
{
|
|
||||||
if (S_Version_minor == 0)
|
|
||||||
{
|
|
||||||
VerifyProgramCommend_t VerifyProgramCommend =
|
|
||||||
(VerifyProgramCommend_t)(0x1300427d); /*!< get the flash verify program api location adress in rom*/
|
|
||||||
return VerifyProgramCommend(config, start, lengthInBytes, expectedData, failedAddress, failedData);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
assert(FLASH_API_TREE);
|
|
||||||
return FLASH_API_TREE->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress,
|
|
||||||
failedData);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! See fsl_flash.h for documentation of this function.*/
|
|
||||||
status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value)
|
|
||||||
{
|
|
||||||
assert(FLASH_API_TREE);
|
|
||||||
return FLASH_API_TREE->flash_get_property(config, whichProperty, value);
|
|
||||||
}
|
|
||||||
/********************************************************************************
|
|
||||||
* fsl_flash_ffr CODE
|
|
||||||
*******************************************************************************/
|
|
||||||
|
|
||||||
/*! See fsl_flash_ffr.h for documentation of this function. */
|
|
||||||
status_t FFR_Init(flash_config_t *config)
|
|
||||||
{
|
|
||||||
assert(FLASH_API_TREE);
|
|
||||||
return FLASH_API_TREE->ffr_init(config);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! See fsl_flash_ffr.h for documentation of this function. */
|
|
||||||
status_t FFR_Deinit(flash_config_t *config)
|
|
||||||
{
|
|
||||||
assert(FLASH_API_TREE);
|
|
||||||
return FLASH_API_TREE->ffr_deinit(config);
|
|
||||||
}
|
|
||||||
|
|
||||||
status_t FFR_CustomerPagesInit(flash_config_t *config)
|
|
||||||
{
|
|
||||||
assert(FLASH_API_TREE);
|
|
||||||
FFR_CustomerPagesInit_t FFR_CustomerPagesInit_cmd = (FFR_CustomerPagesInit_t)(0x13004951);
|
|
||||||
return FFR_CustomerPagesInit_cmd(config);
|
|
||||||
}
|
|
||||||
|
|
||||||
status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len)
|
|
||||||
{
|
|
||||||
FFR_InfieldPageWrite_t FFR_InfieldPageWrite_cmd = (FFR_InfieldPageWrite_t)(0x13004a0b);
|
|
||||||
return FFR_InfieldPageWrite_cmd(config, page_data, valid_len);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! See fsl_flash_ffr.h for documentation of this function. */
|
|
||||||
status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part)
|
|
||||||
{
|
|
||||||
assert(FLASH_API_TREE);
|
|
||||||
return FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! See fsl_flash_ffr.h for documentation of this function. */
|
|
||||||
status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len)
|
|
||||||
{
|
|
||||||
assert(FLASH_API_TREE);
|
|
||||||
return FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! See fsl_flash_ffr.h for documentation of this function. */
|
|
||||||
status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore)
|
|
||||||
{
|
|
||||||
assert(FLASH_API_TREE);
|
|
||||||
return FLASH_API_TREE->ffr_keystore_write(config, pKeyStore);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! See fsl_flash_ffr.h for documentation of this function. */
|
|
||||||
status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode)
|
|
||||||
{
|
|
||||||
assert(FLASH_API_TREE);
|
|
||||||
return FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! See fsl_flash_ffr.h for documentation of this function. */
|
|
||||||
status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex)
|
|
||||||
{
|
|
||||||
assert(FLASH_API_TREE);
|
|
||||||
return FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex);
|
|
||||||
}
|
|
||||||
|
|
||||||
status_t FFR_GetRompatchData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len)
|
|
||||||
{
|
|
||||||
FFR_GetRompatchData_t FFR_GetRompatchData_cmd = (FFR_GetRompatchData_t)(0x13004db3);
|
|
||||||
return FFR_GetRompatchData_cmd(config, pData, offset, len);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* APIs to access NMPA pages */
|
|
||||||
status_t FFR_GetManufactureData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len)
|
|
||||||
{
|
|
||||||
FFR_GetManufactureData_t FFR_GetManufactureData_cmd = (FFR_GetManufactureData_t)(0x13004e15);
|
|
||||||
return FFR_GetManufactureData_cmd(config, pData, offset, len);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! See fsl_flash_ffr.h for documentation of this function. */
|
|
||||||
status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid)
|
|
||||||
{
|
|
||||||
assert(FLASH_API_TREE);
|
|
||||||
return FLASH_API_TREE->ffr_get_uuid(config, uuid);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! See fsl_flash_ffr.h for documentation of this function. */
|
|
||||||
status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len)
|
|
||||||
{
|
|
||||||
assert(FLASH_API_TREE);
|
|
||||||
return FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len);
|
|
||||||
}
|
|
||||||
/*! @}*/
|
|
||||||
|
|
||||||
/********************************************************************************
|
|
||||||
* EOF
|
|
||||||
*******************************************************************************/
|
|
||||||
|
|
@ -1,516 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __FSL_IAP_H_
|
|
||||||
#define __FSL_IAP_H_
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
/*!
|
|
||||||
* @addtogroup iap_driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @file */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
/*!
|
|
||||||
* @name Flash version
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/*! @brief Constructs the version number for drivers. */
|
|
||||||
#if !defined(MAKE_VERSION)
|
|
||||||
#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*! @brief Flash driver version for SDK*/
|
|
||||||
#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
|
|
||||||
|
|
||||||
/*! @brief Flash driver version for ROM*/
|
|
||||||
enum _flash_driver_version_constants
|
|
||||||
{
|
|
||||||
kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/
|
|
||||||
kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/
|
|
||||||
kFLASH_DriverVersionMinor = 0, /*!< Minor flash driver version.*/
|
|
||||||
kFLASH_DriverVersionBugfix = 0 /*!< Bugfix for flash driver version.*/
|
|
||||||
};
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Flash configuration
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/*! @brief Flash IP Type. */
|
|
||||||
#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC)
|
|
||||||
#define FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC (1)
|
|
||||||
#endif
|
|
||||||
#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_FC)
|
|
||||||
#define FSL_FEATURE_FLASH_IP_IS_C040HD_FC (0)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Flash status
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/*! @brief Flash driver status group. */
|
|
||||||
#if defined(kStatusGroup_FlashDriver)
|
|
||||||
#define kStatusGroupGeneric kStatusGroup_Generic
|
|
||||||
#define kStatusGroupFlashDriver kStatusGroup_FlashDriver
|
|
||||||
#elif defined(kStatusGroup_FLASHIAP)
|
|
||||||
#define kStatusGroupGeneric kStatusGroup_Generic
|
|
||||||
#define kStatusGroupFlashDriver kStatusGroup_FLASH
|
|
||||||
#else
|
|
||||||
#define kStatusGroupGeneric 0
|
|
||||||
#define kStatusGroupFlashDriver 1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*! @brief Constructs a status code value from a group and a code number. */
|
|
||||||
#if !defined(MAKE_STATUS)
|
|
||||||
#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Flash driver status codes.
|
|
||||||
*/
|
|
||||||
enum _flash_status
|
|
||||||
{
|
|
||||||
kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/
|
|
||||||
kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/
|
|
||||||
kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/
|
|
||||||
kStatus_FLASH_AlignmentError =
|
|
||||||
MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/
|
|
||||||
kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */
|
|
||||||
kStatus_FLASH_AccessError =
|
|
||||||
MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */
|
|
||||||
kStatus_FLASH_ProtectionViolation = MAKE_STATUS(
|
|
||||||
kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */
|
|
||||||
kStatus_FLASH_CommandFailure =
|
|
||||||
MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */
|
|
||||||
kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/
|
|
||||||
kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/
|
|
||||||
kStatus_FLASH_RegionExecuteOnly =
|
|
||||||
MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/
|
|
||||||
kStatus_FLASH_ExecuteInRamFunctionNotReady =
|
|
||||||
MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/
|
|
||||||
|
|
||||||
kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Flash API is not supported.*/
|
|
||||||
kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< The flash property is read-only.*/
|
|
||||||
kStatus_FLASH_InvalidPropertyValue =
|
|
||||||
MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< The flash property value is out of range.*/
|
|
||||||
kStatus_FLASH_InvalidSpeculationOption =
|
|
||||||
MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< The option of flash prefetch speculation is invalid.*/
|
|
||||||
kStatus_FLASH_EccError = MAKE_STATUS(kStatusGroupFlashDriver,
|
|
||||||
0x10), /*!< A correctable or uncorrectable error during command execution. */
|
|
||||||
kStatus_FLASH_CompareError =
|
|
||||||
MAKE_STATUS(kStatusGroupFlashDriver, 0x11), /*!< Destination and source memory contents do not match. */
|
|
||||||
kStatus_FLASH_RegulationLoss = MAKE_STATUS(kStatusGroupFlashDriver, 0x12), /*!< A loss of regulation during read. */
|
|
||||||
kStatus_FLASH_InvalidWaitStateCycles =
|
|
||||||
MAKE_STATUS(kStatusGroupFlashDriver, 0x13), /*!< The wait state cycle set to r/w mode is invalid. */
|
|
||||||
|
|
||||||
kStatus_FLASH_OutOfDateCfpaPage =
|
|
||||||
MAKE_STATUS(kStatusGroupFlashDriver, 0x20), /*!< CFPA page version is out of date. */
|
|
||||||
kStatus_FLASH_BlankIfrPageData = MAKE_STATUS(kStatusGroupFlashDriver, 0x21), /*!< Blank page cannnot be read. */
|
|
||||||
kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce =
|
|
||||||
MAKE_STATUS(kStatusGroupFlashDriver, 0x22), /*!< Encrypted flash subregions are not erased at once. */
|
|
||||||
kStatus_FLASH_ProgramVerificationNotAllowed = MAKE_STATUS(
|
|
||||||
kStatusGroupFlashDriver, 0x23), /*!< Program verification is not allowed when the encryption is enabled. */
|
|
||||||
kStatus_FLASH_HashCheckError =
|
|
||||||
MAKE_STATUS(kStatusGroupFlashDriver, 0x24), /*!< Hash check of page data is failed. */
|
|
||||||
kStatus_FLASH_SealedFfrRegion = MAKE_STATUS(kStatusGroupFlashDriver, 0x25), /*!< The FFR region is sealed. */
|
|
||||||
kStatus_FLASH_FfrRegionWriteBroken = MAKE_STATUS(
|
|
||||||
kStatusGroupFlashDriver, 0x26), /*!< The FFR Spec region is not allowed to be written discontinuously. */
|
|
||||||
kStatus_FLASH_NmpaAccessNotAllowed =
|
|
||||||
MAKE_STATUS(kStatusGroupFlashDriver, 0x27), /*!< The NMPA region is not allowed to be read/written/erased. */
|
|
||||||
kStatus_FLASH_CmpaCfgDirectEraseNotAllowed =
|
|
||||||
MAKE_STATUS(kStatusGroupFlashDriver, 0x28), /*!< The CMPA Cfg region is not allowed to be erased directly. */
|
|
||||||
kStatus_FLASH_FfrBankIsLocked = MAKE_STATUS(kStatusGroupFlashDriver, 0x29), /*!< The FFR bank region is locked. */
|
|
||||||
};
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Flash API key
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/*! @brief Constructs the four character code for the Flash driver API key. */
|
|
||||||
#if !defined(FOUR_CHAR_CODE)
|
|
||||||
#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a)))
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enumeration for Flash driver API keys.
|
|
||||||
*
|
|
||||||
* @note The resulting value is built with a byte order such that the string
|
|
||||||
* being readable in expected order when viewed in a hex editor, if the value
|
|
||||||
* is treated as a 32-bit little endian value.
|
|
||||||
*/
|
|
||||||
enum _flash_driver_api_keys
|
|
||||||
{
|
|
||||||
kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/
|
|
||||||
};
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enumeration for various flash properties.
|
|
||||||
*/
|
|
||||||
typedef enum _flash_property_tag
|
|
||||||
{
|
|
||||||
kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/
|
|
||||||
kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/
|
|
||||||
kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/
|
|
||||||
kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/
|
|
||||||
kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/
|
|
||||||
|
|
||||||
kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/
|
|
||||||
kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency System Frequency.*/
|
|
||||||
|
|
||||||
kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/
|
|
||||||
kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/
|
|
||||||
kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/
|
|
||||||
kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/
|
|
||||||
} flash_property_tag_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enumeration for flash max pages to erase.
|
|
||||||
*/
|
|
||||||
enum _flash_max_erase_page_value
|
|
||||||
{
|
|
||||||
kFLASH_MaxPagesToErase = 100U /*!< The max value in pages to erase. */
|
|
||||||
};
|
|
||||||
|
|
||||||
enum _flash_freq_tag
|
|
||||||
{
|
|
||||||
kSysToFlashFreq_lowInMHz = 12u,
|
|
||||||
kSysToFlashFreq_defaultInMHz = 96u,
|
|
||||||
kSysToFlashFreq_100MHz = 100u
|
|
||||||
};
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enumeration for flash alignment property.
|
|
||||||
*/
|
|
||||||
enum _flash_alignment_property
|
|
||||||
{
|
|
||||||
kFLASH_AlignementUnitVerifyErase = 4, /*!< The alignment unit in bytes used for verify erase operation.*/
|
|
||||||
kFLASH_AlignementUnitProgram = 512, /*!< The alignment unit in bytes used for program operation.*/
|
|
||||||
/*kFLASH_AlignementUnitVerifyProgram = 4,*/ /*!< The alignment unit in bytes used for verify program operation.*/
|
|
||||||
kFLASH_AlignementUnitSingleWordRead = 16 /*!< The alignment unit in bytes used for SingleWordRead command.*/
|
|
||||||
};
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enumeration for flash read ecc option
|
|
||||||
*/
|
|
||||||
enum _flash_read_ecc_option
|
|
||||||
{
|
|
||||||
kFLASH_ReadWithEccOn = 0, /*! ECC is on */
|
|
||||||
kFLASH_ReadWithEccOff = 1, /*! ECC is off */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enumeration for flash read margin option
|
|
||||||
*/
|
|
||||||
enum _flash_read_margin_option
|
|
||||||
{
|
|
||||||
kFLASH_ReadMarginNormal = 0, /*!< Normal read */
|
|
||||||
kFLASH_ReadMarginVsProgram = 1, /*!< Margin vs. program */
|
|
||||||
kFLASH_ReadMarginVsErase = 2, /*!< Margin vs. erase */
|
|
||||||
kFLASH_ReadMarginIllegalBitCombination = 3 /*!< Illegal bit combination */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enumeration for flash read dmacc option
|
|
||||||
*/
|
|
||||||
enum _flash_read_dmacc_option
|
|
||||||
{
|
|
||||||
kFLASH_ReadDmaccDisabled = 0, /*!< Memory word */
|
|
||||||
kFLASH_ReadDmaccEnabled = 1, /*!< DMACC word */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enumeration for flash ramp control option
|
|
||||||
*/
|
|
||||||
enum _flash_ramp_control_option
|
|
||||||
{
|
|
||||||
kFLASH_RampControlDivisionFactorReserved = 0, /*!< Reserved */
|
|
||||||
kFLASH_RampControlDivisionFactor256 = 1, /*!< clk48mhz / 256 = 187.5KHz */
|
|
||||||
kFLASH_RampControlDivisionFactor128 = 2, /*!< clk48mhz / 128 = 375KHz */
|
|
||||||
kFLASH_RampControlDivisionFactor64 = 3 /*!< clk48mhz / 64 = 750KHz */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*! @brief Flash ECC log info. */
|
|
||||||
typedef struct _flash_ecc_log
|
|
||||||
{
|
|
||||||
uint32_t firstEccEventAddress;
|
|
||||||
uint32_t eccErrorCount;
|
|
||||||
uint32_t eccCorrectionCount;
|
|
||||||
uint32_t reserved;
|
|
||||||
} flash_ecc_log_t;
|
|
||||||
|
|
||||||
/*! @brief Flash controller paramter config. */
|
|
||||||
typedef struct _flash_mode_config
|
|
||||||
{
|
|
||||||
uint32_t sysFreqInMHz;
|
|
||||||
/* ReadSingleWord parameter. */
|
|
||||||
struct
|
|
||||||
{
|
|
||||||
uint8_t readWithEccOff : 1;
|
|
||||||
uint8_t readMarginLevel : 2;
|
|
||||||
uint8_t readDmaccWord : 1;
|
|
||||||
uint8_t reserved0 : 4;
|
|
||||||
uint8_t reserved1[3];
|
|
||||||
} readSingleWord;
|
|
||||||
/* SetWriteMode parameter. */
|
|
||||||
struct
|
|
||||||
{
|
|
||||||
uint8_t programRampControl;
|
|
||||||
uint8_t eraseRampControl;
|
|
||||||
uint8_t reserved[2];
|
|
||||||
} setWriteMode;
|
|
||||||
/* SetReadMode parameter. */
|
|
||||||
struct
|
|
||||||
{
|
|
||||||
uint16_t readInterfaceTimingTrim;
|
|
||||||
uint16_t readControllerTimingTrim;
|
|
||||||
uint8_t readWaitStates;
|
|
||||||
uint8_t reserved[3];
|
|
||||||
} setReadMode;
|
|
||||||
} flash_mode_config_t;
|
|
||||||
|
|
||||||
/*! @brief Flash controller paramter config. */
|
|
||||||
typedef struct _flash_ffr_config
|
|
||||||
{
|
|
||||||
uint32_t ffrBlockBase;
|
|
||||||
uint32_t ffrTotalSize;
|
|
||||||
uint32_t ffrPageSize;
|
|
||||||
uint32_t cfpaPageVersion;
|
|
||||||
uint32_t cfpaPageOffset;
|
|
||||||
} flash_ffr_config_t;
|
|
||||||
|
|
||||||
/*! @brief Flash driver state information.
|
|
||||||
*
|
|
||||||
* An instance of this structure is allocated by the user of the flash driver and
|
|
||||||
* passed into each of the driver APIs.
|
|
||||||
*/
|
|
||||||
typedef struct _flash_config
|
|
||||||
{
|
|
||||||
uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */
|
|
||||||
uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */
|
|
||||||
uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */
|
|
||||||
uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */
|
|
||||||
uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */
|
|
||||||
flash_ffr_config_t ffrConfig;
|
|
||||||
flash_mode_config_t modeConfig;
|
|
||||||
} flash_config_t;
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Initialization
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initializes the global flash properties structure members.
|
|
||||||
*
|
|
||||||
* This function checks and initializes the Flash module for the other Flash APIs.
|
|
||||||
*
|
|
||||||
* @param config Pointer to the storage for the driver runtime state.
|
|
||||||
*
|
|
||||||
* @retval #kStatus_FLASH_Success API was executed successfully.
|
|
||||||
* @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
|
|
||||||
* @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
|
|
||||||
* @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
|
|
||||||
* @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution.
|
|
||||||
*/
|
|
||||||
status_t FLASH_Init(flash_config_t *config);
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Erasing
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Erases the flash sectors encompassed by parameters passed into function.
|
|
||||||
*
|
|
||||||
* This function erases the appropriate number of flash sectors based on the
|
|
||||||
* desired start address and length.
|
|
||||||
*
|
|
||||||
* @param config The pointer to the storage for the driver runtime state.
|
|
||||||
* @param start The start address of the desired flash memory to be erased.
|
|
||||||
* The start address does not need to be sector-aligned.
|
|
||||||
* @param lengthInBytes The length, given in bytes (not words or long-words)
|
|
||||||
* to be erased. Must be word-aligned.
|
|
||||||
* @param key The value used to validate all flash erase APIs.
|
|
||||||
*
|
|
||||||
* @retval #kStatus_FLASH_Success API was executed successfully.
|
|
||||||
* @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
|
|
||||||
* @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline.
|
|
||||||
* @retval #kStatus_FLASH_AddressError The address is out of range.
|
|
||||||
* @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid.
|
|
||||||
* @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
|
|
||||||
* @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
|
|
||||||
* @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution.
|
|
||||||
*/
|
|
||||||
status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key);
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Programming
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Programs flash with data at locations passed in through parameters.
|
|
||||||
*
|
|
||||||
* This function programs the flash memory with the desired data for a given
|
|
||||||
* flash area as determined by the start address and the length.
|
|
||||||
*
|
|
||||||
* @param config A pointer to the storage for the driver runtime state.
|
|
||||||
* @param start The start address of the desired flash memory to be programmed. Must be
|
|
||||||
* word-aligned.
|
|
||||||
* @param src A pointer to the source buffer of data that is to be programmed
|
|
||||||
* into the flash.
|
|
||||||
* @param lengthInBytes The length, given in bytes (not words or long-words),
|
|
||||||
* to be programmed. Must be word-aligned.
|
|
||||||
*
|
|
||||||
* @retval #kStatus_FLASH_Success API was executed successfully.
|
|
||||||
* @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
|
|
||||||
* @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline.
|
|
||||||
* @retval #kStatus_FLASH_AddressError Address is out of range.
|
|
||||||
* @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
|
|
||||||
* @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
|
|
||||||
* @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
|
|
||||||
* @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
|
|
||||||
* @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution.
|
|
||||||
*/
|
|
||||||
status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Verification
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Verifies an erasure of the desired flash area at a specified margin level.
|
|
||||||
*
|
|
||||||
* This function checks the appropriate number of flash sectors based on
|
|
||||||
* the desired start address and length to check whether the flash is erased
|
|
||||||
* to the specified read margin level.
|
|
||||||
*
|
|
||||||
* @param config A pointer to the storage for the driver runtime state.
|
|
||||||
* @param start The start address of the desired flash memory to be verified.
|
|
||||||
* The start address does not need to be sector-aligned but must be word-aligned.
|
|
||||||
* @param lengthInBytes The length, given in bytes (not words or long-words),
|
|
||||||
* to be verified. Must be word-aligned.
|
|
||||||
* @param margin Read margin choice.
|
|
||||||
*
|
|
||||||
* @retval #kStatus_FLASH_Success API was executed successfully.
|
|
||||||
* @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
|
|
||||||
* @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
|
|
||||||
* @retval #kStatus_FLASH_AddressError Address is out of range.
|
|
||||||
* @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
|
|
||||||
* @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
|
|
||||||
* @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
|
|
||||||
* @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
|
|
||||||
* @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution.
|
|
||||||
*/
|
|
||||||
status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Verifies programming of the desired flash area at a specified margin level.
|
|
||||||
*
|
|
||||||
* This function verifies the data programed in the flash memory using the
|
|
||||||
* Flash Program Check Command and compares it to the expected data for a given
|
|
||||||
* flash area as determined by the start address and length.
|
|
||||||
*
|
|
||||||
* @param config A pointer to the storage for the driver runtime state.
|
|
||||||
* @param start The start address of the desired flash memory to be verified. Must be word-aligned.
|
|
||||||
* @param lengthInBytes The length, given in bytes (not words or long-words),
|
|
||||||
* to be verified. Must be word-aligned.
|
|
||||||
* @param expectedData A pointer to the expected data that is to be
|
|
||||||
* verified against.
|
|
||||||
* @param margin Read margin choice.
|
|
||||||
* @param failedAddress A pointer to the returned failing address.
|
|
||||||
* @param failedData A pointer to the returned failing data. Some derivatives do
|
|
||||||
* not include failed data as part of the FCCOBx registers. In this
|
|
||||||
* case, zeros are returned upon failure.
|
|
||||||
*
|
|
||||||
* @retval #kStatus_FLASH_Success API was executed successfully.
|
|
||||||
* @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
|
|
||||||
* @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
|
|
||||||
* @retval #kStatus_FLASH_AddressError Address is out of range.
|
|
||||||
* @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
|
|
||||||
* @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
|
|
||||||
* @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
|
|
||||||
* @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
|
|
||||||
* @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution.
|
|
||||||
*/
|
|
||||||
status_t FLASH_VerifyProgram(flash_config_t *config,
|
|
||||||
uint32_t start,
|
|
||||||
uint32_t lengthInBytes,
|
|
||||||
const uint8_t *expectedData,
|
|
||||||
uint32_t *failedAddress,
|
|
||||||
uint32_t *failedData);
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Properties
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Returns the desired flash property.
|
|
||||||
*
|
|
||||||
* @param config A pointer to the storage for the driver runtime state.
|
|
||||||
* @param whichProperty The desired property from the list of properties in
|
|
||||||
* enum flash_property_tag_t
|
|
||||||
* @param value A pointer to the value returned for the desired flash property.
|
|
||||||
*
|
|
||||||
* @retval #kStatus_FLASH_Success API was executed successfully.
|
|
||||||
* @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
|
|
||||||
* @retval #kStatus_FLASH_UnknownProperty An unknown property tag.
|
|
||||||
*/
|
|
||||||
status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Sets the desired flash property.
|
|
||||||
*
|
|
||||||
* @param config A pointer to the storage for the driver runtime state.
|
|
||||||
* @param whichProperty The desired property from the list of properties in
|
|
||||||
* enum flash_property_tag_t
|
|
||||||
* @param value A to set for the desired flash property.
|
|
||||||
*
|
|
||||||
* @retval #kStatus_FLASH_Success API was executed successfully.
|
|
||||||
* @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
|
|
||||||
* @retval #kStatus_FLASH_UnknownProperty An unknown property tag.
|
|
||||||
* @retval #kStatus_FLASH_ReadOnlyProperty An read-only property tag.
|
|
||||||
*/
|
|
||||||
status_t FLASH_SetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t value);
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
#endif /* __FLASH_FLASH_H_ */
|
|
||||||
|
|
@ -1,253 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __FSL_IAP_FFR_H_
|
|
||||||
#define __FSL_IAP_FFR_H_
|
|
||||||
|
|
||||||
#include "fsl_iap.h"
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup iap_ffr_driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @file */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
/*!
|
|
||||||
* @name Flash IFR version
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/*! @brief Flash IFR driver version for SDK*/
|
|
||||||
#define FSL_FLASH_IFR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*! @brief Alignment(down) utility. */
|
|
||||||
#if !defined(ALIGN_DOWN)
|
|
||||||
#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a))))
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*! @brief Alignment(up) utility. */
|
|
||||||
#if !defined(ALIGN_UP)
|
|
||||||
#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a))))))
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define FLASH_FFR_MAX_PAGE_SIZE (512u)
|
|
||||||
#define FLASH_FFR_HASH_DIGEST_SIZE (32u)
|
|
||||||
#define FLASH_FFR_IV_CODE_SIZE (52u)
|
|
||||||
|
|
||||||
enum _flash_ffr_page_offset
|
|
||||||
{
|
|
||||||
kFfrPageOffset_CFPA = 0, /*!< Customer In-Field programmed area*/
|
|
||||||
kFfrPageOffset_CFPA_Scratch = 0, /*!< CFPA Scratch page */
|
|
||||||
kFfrPageOffset_CFPA_Cfg = 1, /*!< CFPA Configuration area (Ping page)*/
|
|
||||||
kFfrPageOffset_CFPA_CfgPong = 2, /*!< Same as CFPA page (Pong page)*/
|
|
||||||
|
|
||||||
kFfrPageOffset_CMPA = 3, /*!< Customer Manufacturing programmed area*/
|
|
||||||
kFfrPageOffset_CMPA_Cfg = 3, /*!< CMPA Configuration area (Part of CMPA)*/
|
|
||||||
kFfrPageOffset_CMPA_Key = 4, /*!< Key Store area (Part of CMPA)*/
|
|
||||||
|
|
||||||
kFfrPageOffset_NMPA = 7, /*!< NXP Manufacturing programmed area*/
|
|
||||||
kFfrPageOffset_NMPA_Romcp = 7, /*!< ROM patch area (Part of NMPA)*/
|
|
||||||
kFfrPageOffset_NMPA_Repair = 9, /*!< Repair area (Part of NMPA)*/
|
|
||||||
kFfrPageOffset_NMPA_Cfg = 15, /*!< NMPA configuration area (Part of NMPA)*/
|
|
||||||
kFfrPageOffset_NMPA_End = 16, /*!< Reserved (Part of NMPA)*/
|
|
||||||
};
|
|
||||||
|
|
||||||
enum _flash_ffr_page_num
|
|
||||||
{
|
|
||||||
kFfrPageNum_CFPA = 3, /*!< Customer In-Field programmed area*/
|
|
||||||
kFfrPageNum_CMPA = 4, /*!< Customer Manufacturing programmed area*/
|
|
||||||
kFfrPageNum_NMPA = 10, /*!< NXP Manufacturing programmed area*/
|
|
||||||
|
|
||||||
kFfrPageNum_CMPA_Cfg = 1,
|
|
||||||
kFfrPageNum_CMPA_Key = 3,
|
|
||||||
kFfrPageNum_NMPA_Romcp = 2,
|
|
||||||
|
|
||||||
kFfrPageNum_SpecArea = kFfrPageNum_CFPA + kFfrPageNum_CMPA,
|
|
||||||
kFfrPageNum_Total = (kFfrPageNum_CFPA + kFfrPageNum_CMPA + kFfrPageNum_NMPA),
|
|
||||||
};
|
|
||||||
|
|
||||||
enum _flash_ffr_block_size
|
|
||||||
{
|
|
||||||
kFfrBlockSize_Key = 52u,
|
|
||||||
kFfrBlockSize_ActivationCode = 1192u,
|
|
||||||
};
|
|
||||||
|
|
||||||
typedef struct _cfpa_cfg_iv_code
|
|
||||||
{
|
|
||||||
uint32_t keycodeHeader;
|
|
||||||
uint8_t reserved[FLASH_FFR_IV_CODE_SIZE];
|
|
||||||
} cfpa_cfg_iv_code_t;
|
|
||||||
|
|
||||||
typedef struct _cfpa_cfg_info
|
|
||||||
{
|
|
||||||
uint32_t header; /*!< [0x000-0x003] */
|
|
||||||
uint32_t version; /*!< [0x004-0x007 */
|
|
||||||
uint32_t secureFwVersion; /*!< [0x008-0x00b */
|
|
||||||
uint32_t nsFwVersion; /*!< [0x00c-0x00f] */
|
|
||||||
uint32_t imageKeyRevoke; /*!< [0x010-0x013] */
|
|
||||||
uint8_t reserved0[4]; /*!< [0x014-0x017] */
|
|
||||||
uint32_t rotkhRevoke; /*!< [0x018-0x01b] */
|
|
||||||
uint32_t vendorUsage; /*!< [0x01c-0x01f] */
|
|
||||||
uint32_t dcfgNsPin; /*!< [0x020-0x013] */
|
|
||||||
uint32_t dcfgNsDflt; /*!< [0x024-0x017] */
|
|
||||||
uint32_t enableFaMode; /*!< [0x028-0x02b] */
|
|
||||||
uint8_t reserved1[4]; /*!< [0x02c-0x02f] */
|
|
||||||
cfpa_cfg_iv_code_t ivCodePrinceRegion[3]; /*!< [0x030-0x0d7] */
|
|
||||||
uint8_t reserved2[264]; /*!< [0x0d8-0x1df] */
|
|
||||||
uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */
|
|
||||||
} cfpa_cfg_info_t;
|
|
||||||
|
|
||||||
#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U)
|
|
||||||
#define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U)
|
|
||||||
#define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x0U)
|
|
||||||
#define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x1U)
|
|
||||||
|
|
||||||
#define FFR_USBID_VENDORID_MASK (0xFFFFU)
|
|
||||||
#define FFR_USBID_VENDORID_SHIFT (0U)
|
|
||||||
#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U)
|
|
||||||
#define FFR_USBID_PRODUCTID_SHIFT (16U)
|
|
||||||
|
|
||||||
typedef struct _cmpa_cfg_info
|
|
||||||
{
|
|
||||||
uint32_t bootCfg; /*!< [0x000-0x003] */
|
|
||||||
uint32_t spiFlashCfg; /*!< [0x004-0x007] */
|
|
||||||
struct
|
|
||||||
{
|
|
||||||
uint16_t vid;
|
|
||||||
uint16_t pid;
|
|
||||||
} usbId; /*!< [0x008-0x00b] */
|
|
||||||
uint32_t sdioCfg; /*!< [0x00c-0x00f] */
|
|
||||||
uint32_t dcfgPin; /*!< [0x010-0x013] */
|
|
||||||
uint32_t dcfgDflt; /*!< [0x014-0x017] */
|
|
||||||
uint32_t dapVendorUsage; /*!< [0x018-0x01b] */
|
|
||||||
uint32_t secureBootCfg; /*!< [0x01c-0x01f] */
|
|
||||||
uint32_t princeBaseAddr; /*!< [0x020-0x023] */
|
|
||||||
uint32_t princeSr[3]; /*!< [0x024-0x02f] */
|
|
||||||
uint8_t reserved0[32]; /*!< [0x030-0x04f] */
|
|
||||||
uint32_t rotkh[8]; /*!< [0x050-0x06f] */
|
|
||||||
uint8_t reserved1[368]; /*!< [0x070-0x1df] */
|
|
||||||
uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */
|
|
||||||
} cmpa_cfg_info_t;
|
|
||||||
|
|
||||||
typedef struct _cmpa_key_store_header
|
|
||||||
{
|
|
||||||
uint32_t header;
|
|
||||||
uint8_t reserved[4];
|
|
||||||
} cmpa_key_store_header_t;
|
|
||||||
|
|
||||||
#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U)
|
|
||||||
#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U)
|
|
||||||
#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U)
|
|
||||||
#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U)
|
|
||||||
#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U)
|
|
||||||
#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U)
|
|
||||||
|
|
||||||
#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU)
|
|
||||||
#define FFR_PERIPHERALCFG_PERI_SHIFT (0U)
|
|
||||||
#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U)
|
|
||||||
#define FFR_PERIPHERALCFG_COREEN_SHIFT (31U)
|
|
||||||
|
|
||||||
typedef struct _nmpa_cfg_info
|
|
||||||
{
|
|
||||||
uint16_t fro32kCfg; /*!< [0x000-0x001] */
|
|
||||||
uint8_t reserved0[6]; /*!< [0x002-0x007] */
|
|
||||||
uint8_t sysCfg; /*!< [0x008-0x008] */
|
|
||||||
uint8_t reserved1[7]; /*!< [0x009-0x00f] */
|
|
||||||
struct
|
|
||||||
{
|
|
||||||
uint32_t data;
|
|
||||||
uint32_t reserved[3];
|
|
||||||
} GpoInitData[3]; /*!< [0x010-0x03f] */
|
|
||||||
uint32_t GpoDataChecksum[4]; /*!< [0x040-0x04f] */
|
|
||||||
uint32_t finalTestBatchId[4]; /*!< [0x050-0x05f] */
|
|
||||||
uint32_t deviceType; /*!< [0x060-0x063] */
|
|
||||||
uint32_t finalTestProgVersion; /*!< [0x064-0x067] */
|
|
||||||
uint32_t finalTestDate; /*!< [0x068-0x06b] */
|
|
||||||
uint32_t finalTestTime; /*!< [0x06c-0x06f] */
|
|
||||||
uint32_t uuid[4]; /*!< [0x070-0x07f] */
|
|
||||||
uint8_t reserved2[32]; /*!< [0x080-0x09f] */
|
|
||||||
uint32_t peripheralCfg; /*!< [0x0a0-0x0a3] */
|
|
||||||
uint32_t ramSizeCfg; /*!< [0x0a4-0x0a7] */
|
|
||||||
uint32_t flashSizeCfg; /*!< [0x0a8-0x0ab] */
|
|
||||||
uint8_t reserved3[36]; /*!< [0x0ac-0x0cf] */
|
|
||||||
uint8_t fro1mCfg; /*!< [0x0d0-0x0d0] */
|
|
||||||
uint8_t reserved4[15]; /*!< [0x0d1-0x0df] */
|
|
||||||
uint32_t dcdc[4]; /*!< [0x0e0-0x0ef] */
|
|
||||||
uint32_t bod; /*!< [0x0f0-0x0f3] */
|
|
||||||
uint8_t reserved5[12]; /*!< [0x0f4-0x0ff] */
|
|
||||||
uint8_t calcHashReserved[192]; /*!< [0x100-0x1bf] */
|
|
||||||
uint8_t sha256[32]; /*!< [0x1c0-0x1df] */
|
|
||||||
uint32_t ecidBackup[4]; /*!< [0x1e0-0x1ef] */
|
|
||||||
uint32_t pageChecksum[4]; /*!< [0x1f0-0x1ff] */
|
|
||||||
} nmpa_cfg_info_t;
|
|
||||||
|
|
||||||
typedef struct _ffr_key_store
|
|
||||||
{
|
|
||||||
uint8_t reserved[3][FLASH_FFR_MAX_PAGE_SIZE];
|
|
||||||
} ffr_key_store_t;
|
|
||||||
|
|
||||||
typedef enum _ffr_key_type
|
|
||||||
{
|
|
||||||
kFFR_KeyTypeSbkek = 0x00U,
|
|
||||||
kFFR_KeyTypeUser = 0x01U,
|
|
||||||
kFFR_KeyTypeUds = 0x02U,
|
|
||||||
kFFR_KeyTypePrinceRegion0 = 0x03U,
|
|
||||||
kFFR_KeyTypePrinceRegion1 = 0x04U,
|
|
||||||
kFFR_KeyTypePrinceRegion2 = 0x05U,
|
|
||||||
} ffr_key_type_t;
|
|
||||||
|
|
||||||
typedef enum _ffr_bank_type
|
|
||||||
{
|
|
||||||
kFFR_BankTypeBank0_NMPA = 0x00U,
|
|
||||||
kFFR_BankTypeBank1_CMPA = 0x01U,
|
|
||||||
kFFR_BankTypeBank2_CFPA = 0x02U
|
|
||||||
} ffr_bank_type_t;
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*! Generic APIs for FFR */
|
|
||||||
status_t FFR_Init(flash_config_t *config);
|
|
||||||
status_t FFR_Deinit(flash_config_t *config);
|
|
||||||
|
|
||||||
/*! APIs to access CFPA pages */
|
|
||||||
status_t FFR_CustomerPagesInit(flash_config_t *config);
|
|
||||||
status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len);
|
|
||||||
/*! Read data stored in 'Customer In-field Page'. */
|
|
||||||
status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
|
|
||||||
|
|
||||||
/*! APIs to access CMPA pages */
|
|
||||||
status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part);
|
|
||||||
/*! Read data stored in 'Customer Factory CFG Page'. */
|
|
||||||
status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
|
|
||||||
status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore);
|
|
||||||
status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode);
|
|
||||||
status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex);
|
|
||||||
|
|
||||||
/*! APIs to access NMPA pages */
|
|
||||||
status_t FFR_NxpAreaCheckIntegrity(flash_config_t *config);
|
|
||||||
status_t FFR_GetRompatchData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
|
|
||||||
/*! Read data stored in 'NXP Manufacuring Programmed CFG Page'. */
|
|
||||||
status_t FFR_GetManufactureData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
|
|
||||||
status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
#endif /*! __FSL_FLASH_FFR_H_ */
|
|
||||||
|
|
@ -1,121 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "fsl_inputmux.h"
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.inputmux"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Initialize INPUTMUX peripheral.
|
|
||||||
|
|
||||||
* This function enables the INPUTMUX clock.
|
|
||||||
*
|
|
||||||
* param base Base address of the INPUTMUX peripheral.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void INPUTMUX_Init(INPUTMUX_Type *base)
|
|
||||||
{
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE
|
|
||||||
CLOCK_EnableClock(kCLOCK_Sct);
|
|
||||||
CLOCK_EnableClock(kCLOCK_Dma);
|
|
||||||
#else
|
|
||||||
CLOCK_EnableClock(kCLOCK_InputMux);
|
|
||||||
#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Attaches a signal
|
|
||||||
*
|
|
||||||
* This function gates the INPUTPMUX clock.
|
|
||||||
*
|
|
||||||
* param base Base address of the INPUTMUX peripheral.
|
|
||||||
* param index Destination peripheral to attach the signal to.
|
|
||||||
* param connection Selects connection.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection)
|
|
||||||
{
|
|
||||||
uint32_t pmux_id;
|
|
||||||
uint32_t output_id;
|
|
||||||
|
|
||||||
/* extract pmux to be used */
|
|
||||||
pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT;
|
|
||||||
/* extract function number */
|
|
||||||
output_id = ((uint32_t)(connection)) & 0xffffU;
|
|
||||||
/* programm signal */
|
|
||||||
*(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4)) = output_id;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA)
|
|
||||||
/*!
|
|
||||||
* brief Enable/disable a signal
|
|
||||||
*
|
|
||||||
* This function gates the INPUTPMUX clock.
|
|
||||||
*
|
|
||||||
* param base Base address of the INPUTMUX peripheral.
|
|
||||||
* param signal Enable signal register id and bit offset.
|
|
||||||
* param enable Selects enable or disable.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable)
|
|
||||||
{
|
|
||||||
uint32_t ena_id;
|
|
||||||
uint32_t bit_offset;
|
|
||||||
|
|
||||||
/* extract enable register to be used */
|
|
||||||
ena_id = ((uint32_t)(signal)) >> ENA_SHIFT;
|
|
||||||
/* extract enable bit offset */
|
|
||||||
bit_offset = ((uint32_t)(signal)) & 0xfU;
|
|
||||||
/* set signal */
|
|
||||||
if (enable)
|
|
||||||
{
|
|
||||||
*(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1U << bit_offset);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
*(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1U << bit_offset);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Deinitialize INPUTMUX peripheral.
|
|
||||||
|
|
||||||
* This function disables the INPUTMUX clock.
|
|
||||||
*
|
|
||||||
* param base Base address of the INPUTMUX peripheral.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void INPUTMUX_Deinit(INPUTMUX_Type *base)
|
|
||||||
{
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE
|
|
||||||
CLOCK_DisableClock(kCLOCK_Sct);
|
|
||||||
CLOCK_DisableClock(kCLOCK_Dma);
|
|
||||||
#else
|
|
||||||
CLOCK_DisableClock(kCLOCK_InputMux);
|
|
||||||
#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
}
|
|
||||||
|
|
@ -1,97 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _FSL_INPUTMUX_H_
|
|
||||||
#define _FSL_INPUTMUX_H_
|
|
||||||
|
|
||||||
#include "fsl_inputmux_connections.h"
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup inputmux_driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @file */
|
|
||||||
/*! @file fsl_inputmux_connections.h */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
/*! @brief Group interrupt driver version for SDK */
|
|
||||||
#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initialize INPUTMUX peripheral.
|
|
||||||
|
|
||||||
* This function enables the INPUTMUX clock.
|
|
||||||
*
|
|
||||||
* @param base Base address of the INPUTMUX peripheral.
|
|
||||||
*
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
void INPUTMUX_Init(INPUTMUX_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Attaches a signal
|
|
||||||
*
|
|
||||||
* This function gates the INPUTPMUX clock.
|
|
||||||
*
|
|
||||||
* @param base Base address of the INPUTMUX peripheral.
|
|
||||||
* @param index Destination peripheral to attach the signal to.
|
|
||||||
* @param connection Selects connection.
|
|
||||||
*
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection);
|
|
||||||
|
|
||||||
#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA)
|
|
||||||
/*!
|
|
||||||
* @brief Enable/disable a signal
|
|
||||||
*
|
|
||||||
* This function gates the INPUTPMUX clock.
|
|
||||||
*
|
|
||||||
* @param base Base address of the INPUTMUX peripheral.
|
|
||||||
* @param signal Enable signal register id and bit offset.
|
|
||||||
* @param enable Selects enable or disable.
|
|
||||||
*
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Deinitialize INPUTMUX peripheral.
|
|
||||||
|
|
||||||
* This function disables the INPUTMUX clock.
|
|
||||||
*
|
|
||||||
* @param base Base address of the INPUTMUX peripheral.
|
|
||||||
*
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
void INPUTMUX_Deinit(INPUTMUX_Type *base);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
#endif /* _FSL_INPUTMUX_H_ */
|
|
||||||
|
|
@ -1,410 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright (c) 2016, NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _FSL_INPUTMUX_CONNECTIONS_
|
|
||||||
#define _FSL_INPUTMUX_CONNECTIONS_
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup inputmux_driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Input multiplexing connections
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @brief Periphinmux IDs */
|
|
||||||
#define SCT0_INMUX0 0x00U
|
|
||||||
#define TIMER0CAPTSEL0 0x20U
|
|
||||||
#define TIMER1CAPTSEL0 0x40U
|
|
||||||
#define TIMER2CAPTSEL0 0x60U
|
|
||||||
#define PINTSEL0 0xC0U
|
|
||||||
#define DMA0_ITRIG_INMUX0 0xE0U
|
|
||||||
#define DMA0_OTRIG_INMUX0 0x160U
|
|
||||||
#define FREQMEAS_REF_REG 0x180U
|
|
||||||
#define FREQMEAS_TARGET_REG 0x184U
|
|
||||||
#define TIMER3CAPTSEL0 0x1A0U
|
|
||||||
#define TIMER4CAPTSEL0 0x1C0U
|
|
||||||
#define PINTSECSEL0 0x1E0U
|
|
||||||
#define DMA1_ITRIG_INMUX0 0x200U
|
|
||||||
#define DMA1_OTRIG_INMUX0 0x240U
|
|
||||||
#define PMUX_SHIFT 20U
|
|
||||||
|
|
||||||
/*! @brief INPUTMUX connections type */
|
|
||||||
typedef enum _inputmux_connection_t
|
|
||||||
{
|
|
||||||
/*!< SCT0 INMUX. */
|
|
||||||
kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer0M0ToSct0 = 8U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer1M0ToSct0 = 9U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer2M0ToSct0 = 10U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer3M0ToSct0 = 11U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer4M0ToSct0 = 12U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpiointBmatchToSct0 = 14U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CompOutToSct0 = 17U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_I2sSharedSck0ToSct0 = 18U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_I2sSharedSck1ToSct0 = 19U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_I2sSharedWs0ToSct0 = 20U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_I2sSharedWs1ToSct0 = 21U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_INMUX0 << PMUX_SHIFT),
|
|
||||||
|
|
||||||
/*!< TIMER0 CAPTSEL. */
|
|
||||||
kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp17ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp18ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp19ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Usb0FrameToggleToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Usb1FrameToggleToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CompOutToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_I2sSharedWs0ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_I2sSharedWs1ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
|
|
||||||
/*!< TIMER1 CAPTSEL. */
|
|
||||||
kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp17ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp18ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp19ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Usb0FrameToggleToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Usb1FrameToggleToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CompOutToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_I2sSharedWs0ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_I2sSharedWs1ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
|
|
||||||
/*!< TIMER2 CAPTSEL. */
|
|
||||||
kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp17ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp18ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp19ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Usb0FrameToggleToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Usb1FrameToggleToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CompOutToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_I2sSharedWs0ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_I2sSharedWs1ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
|
|
||||||
/*!< Pin interrupt select. */
|
|
||||||
kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT),
|
|
||||||
|
|
||||||
/*!< DMA0 Input trigger. */
|
|
||||||
kINPUTMUX_PinInt0ToDma0 = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_PinInt1ToDma0 = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_PinInt2ToDma0 = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_PinInt3ToDma0 = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CompOutToDma0 = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Otrig0ToDma0 = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Otrig1ToDma0 = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Otrig2ToDma0 = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Otrig3ToDma0 = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Sct0DmaReq0ToDma0 = 19U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Sct0DmaReq1ToDma0 = 20U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_HashDmaRxToDma0 = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
|
|
||||||
/*!< DMA0 output trigger. */
|
|
||||||
kINPUTMUX_Dma0Hash0TxTrigoutToTriginChannels = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0HsLspiRxTrigoutToTriginChannels = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0HsLspiTxTrigoutToTriginChannels = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Flexcomm2RxTrigoutToTriginChannels = 8U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Flexcomm2TxTrigoutToTriginChannels = 9U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Flexcomm3RxTrigoutToTriginChannels = 10U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Flexcomm3TxTrigoutToTriginChannels = 11U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Flexcomm4RxTrigoutToTriginChannels = 12U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Flexcomm4TxTrigoutToTriginChannels = 13U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Flexcomm5RxTrigoutToTriginChannels = 14U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Flexcomm5TxTrigoutToTriginChannels = 15U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Flexcomm6RxTrigoutToTriginChannels = 16U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Flexcomm6TxTrigoutToTriginChannels = 17U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Flexcomm7RxTrigoutToTriginChannels = 18U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Flexcomm7TxTrigoutToTriginChannels = 19U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Capt0TxTrigoutToTriginChannels = 20U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Adc0Ch0TrigoutToTriginChannels = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma0Adc0Ch1TrigoutToTriginChannels = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
|
|
||||||
/*!< Selection for frequency measurement reference clock. */
|
|
||||||
kINPUTMUX_ExternOscToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Fro12MhzToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Fro96MhzToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_WdtOscToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_32KhzOscToFreqmeasRef= 4u + (FREQMEAS_REF_REG << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_MainClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_FreqmeGpioClk_aRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_FreqmeGpioClk_bRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT),
|
|
||||||
|
|
||||||
/*!< Selection for frequency measurement target clock. */
|
|
||||||
kINPUTMUX_ExternOscToFreqmeasTarget = 0U + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Fro12MhzToFreqmeasTarget = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Fro96MhzToFreqmeasTarget = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_WdtOscToFreqmeasTarget = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_32KhzOscToFreqmeasTarget= 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_MainClkToFreqmeasTarget = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_FreqmeGpioClk_aTarget = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_FreqmeGpioClk_bTarget = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
|
|
||||||
|
|
||||||
/*!< TIMER3 CAPTSEL. */
|
|
||||||
kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp17ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp18ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp19ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Usb0FrameToggleToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Usb1FrameToggleToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CompOutToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_I2sSharedWs0ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_I2sSharedWs1ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
|
|
||||||
/*!< Timer4 CAPTSEL. */
|
|
||||||
kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp17ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp18ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CtimerInp19ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Usb0FrameToggleToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Usb1FrameToggleToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_CompOutToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_I2sSharedWs0ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_I2sSharedWs1ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
|
|
||||||
|
|
||||||
/*Pin interrupt secure select */
|
|
||||||
kINPUTMUX_GpioPort0Pin0ToPintSecsel = 0U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin1ToPintSecsel = 1U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin2ToPintSecsel = 2U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin3ToPintSecsel = 3U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin4ToPintSecsel = 4U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin5ToPintSecsel = 5U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin6ToPintSecsel = 6U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin7ToPintSecsel = 7U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin8ToPintSecsel = 8U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin9ToPintSecsel = 9U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin10ToPintSecsel = 10U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin11ToPintSecsel = 11U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin12ToPintSecsel = 12U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin13ToPintSecsel = 13U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin14ToPintSecsel = 14U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin15ToPintSecsel = 15U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin16ToPintSecsel = 16U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin17ToPintSecsel = 17U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin18ToPintSecsel = 18U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin19ToPintSecsel = 19U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin20ToPintSecsel = 20U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin21ToPintSecsel = 21U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin22ToPintSecsel = 22U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin23ToPintSecsel = 23U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin24ToPintSecsel = 24U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin25ToPintSecsel = 25U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin26ToPintSecsel = 26U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin27ToPintSecsel = 27U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin28ToPintSecsel = 28U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin29ToPintSecsel = 29U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin30ToPintSecsel = 30U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_GpioPort0Pin31ToPintSecsel = 31U + (PINTSECSEL0 << PMUX_SHIFT),
|
|
||||||
|
|
||||||
/*!< DMA1 Input trigger. */
|
|
||||||
kINPUTMUX_PinInt0ToDma1 = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_PinInt1ToDma1 = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_PinInt2ToDma1 = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_PinInt3ToDma1 = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer2M0ToDma1 = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Ctimer4M1ToDma1 = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Otrig0ToDma1 = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Otrig1ToDma1 = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Otrig2ToDma1 = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Otrig3ToDma1 = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Sct0DmaReq0ToDma1 = 12U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Sct0DmaReq1ToDma1 = 13U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_HashDmaRxToDma1 = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
|
|
||||||
/*!< DMA1 output trigger. */
|
|
||||||
kINPUTMUX_Dma1Hash0TxTrigoutToTriginChannels = 0U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma1Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma1Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma1Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma1Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma1Flexcomm2RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
kINPUTMUX_Dma1Flexcomm2TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
|
|
||||||
} inputmux_connection_t;
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
#endif /* _FSL_INPUTMUX_CONNECTIONS_ */
|
|
||||||
|
|
@ -1,288 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _FSL_IOCON_H_
|
|
||||||
#define _FSL_IOCON_H_
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup lpc_iocon
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @file */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
/*! @brief IOCON driver version 2.0.0. */
|
|
||||||
#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format
|
|
||||||
*/
|
|
||||||
typedef struct _iocon_group
|
|
||||||
{
|
|
||||||
uint32_t port : 8; /* Pin port */
|
|
||||||
uint32_t pin : 8; /* Pin number */
|
|
||||||
uint32_t ionumber : 8; /* IO number */
|
|
||||||
uint32_t modefunc : 16; /* Function and mode */
|
|
||||||
} iocon_group_t;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief IOCON function and mode selection definitions
|
|
||||||
* @note See the User Manual for specific modes and functions supported by the various pins.
|
|
||||||
*/
|
|
||||||
#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4)
|
|
||||||
#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
|
|
||||||
#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
|
|
||||||
#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
|
|
||||||
#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
|
|
||||||
#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
|
|
||||||
#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
|
|
||||||
#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
|
|
||||||
#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
|
|
||||||
#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */
|
|
||||||
#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */
|
|
||||||
#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */
|
|
||||||
#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */
|
|
||||||
#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */
|
|
||||||
#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */
|
|
||||||
#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */
|
|
||||||
#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */
|
|
||||||
#if defined(IOCON_PIO_MODE_SHIFT)
|
|
||||||
#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */
|
|
||||||
#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */
|
|
||||||
#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */
|
|
||||||
#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_I2CSLEW_SHIFT)
|
|
||||||
#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */
|
|
||||||
#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_EGP_SHIFT)
|
|
||||||
#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */
|
|
||||||
#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_SLEW_SHIFT)
|
|
||||||
#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */
|
|
||||||
#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_INVERT_SHIFT)
|
|
||||||
#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_DIGIMODE_SHIFT)
|
|
||||||
#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */
|
|
||||||
#define IOCON_DIGITAL_EN \
|
|
||||||
(0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_FILTEROFF_SHIFT)
|
|
||||||
#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */
|
|
||||||
#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_I2CDRIVE_SHIFT)
|
|
||||||
#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */
|
|
||||||
#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_OD_SHIFT)
|
|
||||||
#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_I2CFILTER_SHIFT)
|
|
||||||
#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */
|
|
||||||
#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_ASW_SHIFT)
|
|
||||||
#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_SSEL_SHIFT)
|
|
||||||
#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */
|
|
||||||
#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_ECS_SHIFT)
|
|
||||||
#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */
|
|
||||||
#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_S_MODE_SHIFT)
|
|
||||||
#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */
|
|
||||||
#define IOCON_S_MODE_1CLK \
|
|
||||||
(0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \
|
|
||||||
*/
|
|
||||||
#define IOCON_S_MODE_2CLK \
|
|
||||||
(0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \
|
|
||||||
*/
|
|
||||||
#define IOCON_S_MODE_3CLK \
|
|
||||||
(0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \
|
|
||||||
*/
|
|
||||||
#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_CLK_DIV_SHIFT)
|
|
||||||
#define IOCON_CLKDIV(div) \
|
|
||||||
((div) \
|
|
||||||
<< IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else
|
|
||||||
#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
|
|
||||||
#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
|
|
||||||
#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
|
|
||||||
#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
|
|
||||||
#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
|
|
||||||
#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
|
|
||||||
#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
|
|
||||||
#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_MODE_SHIFT)
|
|
||||||
#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */
|
|
||||||
#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */
|
|
||||||
#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */
|
|
||||||
#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_I2CSLEW_SHIFT)
|
|
||||||
#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */
|
|
||||||
#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_EGP_SHIFT)
|
|
||||||
#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */
|
|
||||||
#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_INVERT_SHIFT)
|
|
||||||
#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_DIGIMODE_SHIFT)
|
|
||||||
#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */
|
|
||||||
#define IOCON_DIGITAL_EN \
|
|
||||||
(0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_FILTEROFF_SHIFT)
|
|
||||||
#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */
|
|
||||||
#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_I2CDRIVE_SHIFT)
|
|
||||||
#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */
|
|
||||||
#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_OD_SHIFT)
|
|
||||||
#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_I2CFILTER_SHIFT)
|
|
||||||
#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */
|
|
||||||
#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_S_MODE_SHIFT)
|
|
||||||
#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */
|
|
||||||
#define IOCON_S_MODE_1CLK \
|
|
||||||
(0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \
|
|
||||||
*/
|
|
||||||
#define IOCON_S_MODE_2CLK \
|
|
||||||
(0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \
|
|
||||||
*/
|
|
||||||
#define IOCON_S_MODE_3CLK \
|
|
||||||
(0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \
|
|
||||||
*/
|
|
||||||
#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(IOCON_PIO_CLK_DIV_SHIFT)
|
|
||||||
#define IOCON_CLKDIV(div) \
|
|
||||||
((div) \
|
|
||||||
<< IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1))
|
|
||||||
/**
|
|
||||||
* @brief Sets I/O Control pin mux
|
|
||||||
* @param base : The base of IOCON peripheral on the chip
|
|
||||||
* @param ionumber : GPIO number to mux
|
|
||||||
* @param modefunc : OR'ed values of type IOCON_*
|
|
||||||
* @return Nothing
|
|
||||||
*/
|
|
||||||
__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc)
|
|
||||||
{
|
|
||||||
base->PIO[ionumber] = modefunc;
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
/**
|
|
||||||
* @brief Sets I/O Control pin mux
|
|
||||||
* @param base : The base of IOCON peripheral on the chip
|
|
||||||
* @param port : GPIO port to mux
|
|
||||||
* @param pin : GPIO pin to mux
|
|
||||||
* @param modefunc : OR'ed values of type IOCON_*
|
|
||||||
* @return Nothing
|
|
||||||
*/
|
|
||||||
__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc)
|
|
||||||
{
|
|
||||||
base->PIO[port][pin] = modefunc;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Set all I/O Control pin muxing
|
|
||||||
* @param base : The base of IOCON peripheral on the chip
|
|
||||||
* @param pinArray : Pointer to array of pin mux selections
|
|
||||||
* @param arrayLength : Number of entries in pinArray
|
|
||||||
* @return Nothing
|
|
||||||
*/
|
|
||||||
__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength)
|
|
||||||
{
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
for (i = 0; i < arrayLength; i++)
|
|
||||||
{
|
|
||||||
#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1))
|
|
||||||
IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc);
|
|
||||||
#else
|
|
||||||
IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc);
|
|
||||||
#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* _FSL_IOCON_H_ */
|
|
||||||
|
|
@ -1,611 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "fsl_lpadc.h"
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.lpadc"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Prototypes
|
|
||||||
******************************************************************************/
|
|
||||||
/*!
|
|
||||||
* @brief Get instance number for LPADC module.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address
|
|
||||||
*/
|
|
||||||
static uint32_t LPADC_GetInstance(ADC_Type *base);
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables
|
|
||||||
******************************************************************************/
|
|
||||||
/*! @brief Pointers to LPADC bases for each instance. */
|
|
||||||
static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS;
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/*! @brief Pointers to LPADC clocks for each instance. */
|
|
||||||
static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS;
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code
|
|
||||||
******************************************************************************/
|
|
||||||
static uint32_t LPADC_GetInstance(ADC_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t instance;
|
|
||||||
|
|
||||||
/* Find the instance index from base address mappings. */
|
|
||||||
for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++)
|
|
||||||
{
|
|
||||||
if (s_lpadcBases[instance] == base)
|
|
||||||
{
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
assert(instance < ARRAY_SIZE(s_lpadcBases));
|
|
||||||
|
|
||||||
return instance;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Initializes the LPADC module.
|
|
||||||
*
|
|
||||||
* param base LPADC peripheral base address.
|
|
||||||
* param config Pointer to configuration structure. See "lpadc_config_t".
|
|
||||||
*/
|
|
||||||
void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)
|
|
||||||
{
|
|
||||||
/* Check if the pointer is available. */
|
|
||||||
assert(config != NULL);
|
|
||||||
|
|
||||||
uint32_t tmp32 = 0U;
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Enable the clock for LPADC instance. */
|
|
||||||
CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
/* Reset the module. */
|
|
||||||
LPADC_DoResetConfig(base);
|
|
||||||
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
|
|
||||||
LPADC_DoResetFIFO0(base);
|
|
||||||
LPADC_DoResetFIFO1(base);
|
|
||||||
#else
|
|
||||||
LPADC_DoResetFIFO(base);
|
|
||||||
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
|
|
||||||
|
|
||||||
/* Disable the module before setting configuration. */
|
|
||||||
LPADC_Enable(base, false);
|
|
||||||
|
|
||||||
/* Configure the module generally. */
|
|
||||||
if (config->enableInDozeMode)
|
|
||||||
{
|
|
||||||
base->CTRL &= ~ADC_CTRL_DOZEN_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
base->CTRL |= ADC_CTRL_DOZEN_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
|
|
||||||
/* Set calibration average mode. */
|
|
||||||
base->CTRL |= ADC_CTRL_CAL_AVGS(config->conversionAverageMode);
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
|
|
||||||
|
|
||||||
/* ADCx_CFG. */
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN
|
|
||||||
if (config->enableInternalClock)
|
|
||||||
{
|
|
||||||
tmp32 |= ADC_CFG_ADCKEN_MASK;
|
|
||||||
}
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG
|
|
||||||
if (config->enableVref1LowVoltage)
|
|
||||||
{
|
|
||||||
tmp32 |= ADC_CFG_VREF1RNG_MASK;
|
|
||||||
}
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */
|
|
||||||
if (config->enableAnalogPreliminary)
|
|
||||||
{
|
|
||||||
tmp32 |= ADC_CFG_PWREN_MASK;
|
|
||||||
}
|
|
||||||
tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */
|
|
||||||
| ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */
|
|
||||||
| ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */
|
|
||||||
| ADC_CFG_TPRICTRL(config->triggerPrioirtyPolicy); /* Trigger priority policy. */
|
|
||||||
base->CFG = tmp32;
|
|
||||||
|
|
||||||
/* ADCx_PAUSE. */
|
|
||||||
if (config->enableConvPause)
|
|
||||||
{
|
|
||||||
base->PAUSE = ADC_PAUSE_PAUSEEN_MASK | ADC_PAUSE_PAUSEDLY(config->convPauseDelay);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
base->PAUSE = 0U;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
|
|
||||||
/* ADCx_FCTRL0. */
|
|
||||||
base->FCTRL[0] = ADC_FCTRL_FWMARK(config->FIFO0Watermark);
|
|
||||||
/* ADCx_FCTRL1. */
|
|
||||||
base->FCTRL[1] = ADC_FCTRL_FWMARK(config->FIFO1Watermark);
|
|
||||||
#else
|
|
||||||
/* ADCx_FCTRL. */
|
|
||||||
base->FCTRL = ADC_FCTRL_FWMARK(config->FIFOWatermark);
|
|
||||||
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
|
|
||||||
|
|
||||||
/* Enable the module after setting configuration. */
|
|
||||||
LPADC_Enable(base, true);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Gets an available pre-defined settings for initial configuration.
|
|
||||||
*
|
|
||||||
* This function initializes the converter configuration structure with an available settings. The default values are:
|
|
||||||
* code
|
|
||||||
* config->enableInDozeMode = true;
|
|
||||||
* config->conversionAverageMode = kLPADC_ConversionAverage1;
|
|
||||||
* config->enableAnalogPreliminary = false;
|
|
||||||
* config->powerUpDelay = 0x80;
|
|
||||||
* config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1;
|
|
||||||
* config->powerLevelMode = kLPADC_PowerLevelAlt1;
|
|
||||||
* config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately;
|
|
||||||
* config->enableConvPause = false;
|
|
||||||
* config->convPauseDelay = 0U;
|
|
||||||
* config->FIFO0Watermark = 0U;
|
|
||||||
* config->FIFO1Watermark = 0U;
|
|
||||||
* config->FIFOWatermark = 0U;
|
|
||||||
* endcode
|
|
||||||
* param config Pointer to configuration structure.
|
|
||||||
*/
|
|
||||||
void LPADC_GetDefaultConfig(lpadc_config_t *config)
|
|
||||||
{
|
|
||||||
/* Initializes the configure structure to zero. */
|
|
||||||
memset(config, 0, sizeof(*config));
|
|
||||||
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN
|
|
||||||
config->enableInternalClock = false;
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG
|
|
||||||
config->enableVref1LowVoltage = false;
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */
|
|
||||||
config->enableInDozeMode = true;
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
|
|
||||||
/* Set calibration average mode. */
|
|
||||||
config->conversionAverageMode = kLPADC_ConversionAverage1;
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
|
|
||||||
config->enableAnalogPreliminary = false;
|
|
||||||
config->powerUpDelay = 0x80;
|
|
||||||
config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1;
|
|
||||||
config->powerLevelMode = kLPADC_PowerLevelAlt1;
|
|
||||||
config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately;
|
|
||||||
config->enableConvPause = false;
|
|
||||||
config->convPauseDelay = 0U;
|
|
||||||
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
|
|
||||||
config->FIFO0Watermark = 0U;
|
|
||||||
config->FIFO1Watermark = 0U;
|
|
||||||
#else
|
|
||||||
config->FIFOWatermark = 0U;
|
|
||||||
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief De-initializes the LPADC module.
|
|
||||||
*
|
|
||||||
* param base LPADC peripheral base address.
|
|
||||||
*/
|
|
||||||
void LPADC_Deinit(ADC_Type *base)
|
|
||||||
{
|
|
||||||
/* Disable the module. */
|
|
||||||
LPADC_Enable(base, false);
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Gate the clock. */
|
|
||||||
CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
}
|
|
||||||
|
|
||||||
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
|
|
||||||
/*!
|
|
||||||
* brief Get the result in conversion FIFOn.
|
|
||||||
*
|
|
||||||
* param base LPADC peripheral base address.
|
|
||||||
* param result Pointer to structure variable that keeps the conversion result in conversion FIFOn.
|
|
||||||
* param index Result FIFO index.
|
|
||||||
*
|
|
||||||
* return Status whether FIFOn entry is valid.
|
|
||||||
*/
|
|
||||||
bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index)
|
|
||||||
{
|
|
||||||
assert(result != NULL); /* Check if the input pointer is available. */
|
|
||||||
|
|
||||||
uint32_t tmp32;
|
|
||||||
|
|
||||||
tmp32 = base->RESFIFO[index];
|
|
||||||
|
|
||||||
if (0U == (ADC_RESFIFO_VALID_MASK & tmp32))
|
|
||||||
{
|
|
||||||
return false; /* FIFO is empty. Discard any read from RESFIFO. */
|
|
||||||
}
|
|
||||||
|
|
||||||
result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT;
|
|
||||||
result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT;
|
|
||||||
result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT;
|
|
||||||
result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK);
|
|
||||||
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
/*!
|
|
||||||
* brief Get the result in conversion FIFO.
|
|
||||||
*
|
|
||||||
* param base LPADC peripheral base address.
|
|
||||||
* param result Pointer to structure variable that keeps the conversion result in conversion FIFO.
|
|
||||||
*
|
|
||||||
* return Status whether FIFO entry is valid.
|
|
||||||
*/
|
|
||||||
bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result)
|
|
||||||
{
|
|
||||||
assert(result != NULL); /* Check if the input pointer is available. */
|
|
||||||
|
|
||||||
uint32_t tmp32;
|
|
||||||
|
|
||||||
tmp32 = base->RESFIFO;
|
|
||||||
|
|
||||||
if (0U == (ADC_RESFIFO_VALID_MASK & tmp32))
|
|
||||||
{
|
|
||||||
return false; /* FIFO is empty. Discard any read from RESFIFO. */
|
|
||||||
}
|
|
||||||
|
|
||||||
result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT;
|
|
||||||
result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT;
|
|
||||||
result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT;
|
|
||||||
result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK);
|
|
||||||
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Configure the conversion trigger source.
|
|
||||||
*
|
|
||||||
* Each programmable trigger can launch the conversion command in command buffer.
|
|
||||||
*
|
|
||||||
* param base LPADC peripheral base address.
|
|
||||||
* param triggerId ID for each trigger. Typically, the available value range is from 0.
|
|
||||||
* param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t.
|
|
||||||
*/
|
|
||||||
void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config)
|
|
||||||
{
|
|
||||||
assert(triggerId < ADC_TCTRL_COUNT); /* Check if the triggerId is available in this device. */
|
|
||||||
assert(config != NULL); /* Check if the input pointer is available. */
|
|
||||||
|
|
||||||
uint32_t tmp32;
|
|
||||||
|
|
||||||
tmp32 = ADC_TCTRL_TCMD(config->targetCommandId) /* Trigger command select. */
|
|
||||||
| ADC_TCTRL_TDLY(config->delayPower) /* Trigger delay select. */
|
|
||||||
| ADC_TCTRL_TPRI(config->priority) /* Trigger priority setting. */
|
|
||||||
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
|
|
||||||
| ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect)
|
|
||||||
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
|
|
||||||
;
|
|
||||||
if (config->enableHardwareTrigger)
|
|
||||||
{
|
|
||||||
tmp32 |= ADC_TCTRL_HTEN_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
base->TCTRL[triggerId] = tmp32;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Gets an available pre-defined settings for trigger's configuration.
|
|
||||||
*
|
|
||||||
* This function initializes the trigger's configuration structure with an available settings. The default values are:
|
|
||||||
* code
|
|
||||||
* config->commandIdSource = 0U;
|
|
||||||
* config->loopCountIndex = 0U;
|
|
||||||
* config->triggerIdSource = 0U;
|
|
||||||
* config->enableHardwareTrigger = false;
|
|
||||||
* config->channelAFIFOSelect = 0U;
|
|
||||||
* config->channelBFIFOSelect = 0U;
|
|
||||||
* endcode
|
|
||||||
* param config Pointer to configuration structure.
|
|
||||||
*/
|
|
||||||
void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config)
|
|
||||||
{
|
|
||||||
assert(config != NULL); /* Check if the input pointer is available. */
|
|
||||||
|
|
||||||
/* Initializes the configure structure to zero. */
|
|
||||||
memset(config, 0, sizeof(*config));
|
|
||||||
|
|
||||||
config->targetCommandId = 0U;
|
|
||||||
config->delayPower = 0U;
|
|
||||||
config->priority = 0U;
|
|
||||||
#if defined(FSL_FEATURE_LPADC_FIFO_COUNT) && FSL_FEATURE_LPADC_FIFO_COUNT
|
|
||||||
config->channelAFIFOSelect = 0U;
|
|
||||||
config->channelBFIFOSelect = 0U;
|
|
||||||
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
|
|
||||||
config->enableHardwareTrigger = false;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Configure conversion command.
|
|
||||||
*
|
|
||||||
* param base LPADC peripheral base address.
|
|
||||||
* param commandId ID for command in command buffer. Typically, the available value range is 1 - 15.
|
|
||||||
* param config Pointer to configuration structure. See to #lpadc_conv_command_config_t.
|
|
||||||
*/
|
|
||||||
void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config)
|
|
||||||
{
|
|
||||||
assert(commandId < (ADC_CMDL_COUNT + 1U)); /* Check if the commandId is available on this device. */
|
|
||||||
assert(config != NULL); /* Check if the input pointer is available. */
|
|
||||||
|
|
||||||
uint32_t tmp32 = 0;
|
|
||||||
|
|
||||||
commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */
|
|
||||||
|
|
||||||
/* ADCx_CMDL. */
|
|
||||||
tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE
|
|
||||||
tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE
|
|
||||||
tmp32 |= ADC_CMDL_CTYPE(config->sampleChannelMode);
|
|
||||||
#else
|
|
||||||
switch (config->sampleChannelMode) /* Sample input. */
|
|
||||||
{
|
|
||||||
case kLPADC_SampleChannelSingleEndSideB:
|
|
||||||
tmp32 |= ADC_CMDL_ABSEL_MASK;
|
|
||||||
break;
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF
|
|
||||||
case kLPADC_SampleChannelDiffBothSideAB:
|
|
||||||
tmp32 |= ADC_CMDL_DIFF_MASK;
|
|
||||||
break;
|
|
||||||
case kLPADC_SampleChannelDiffBothSideBA:
|
|
||||||
tmp32 |= ADC_CMDL_ABSEL_MASK | ADC_CMDL_DIFF_MASK;
|
|
||||||
break;
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_DIFF */
|
|
||||||
default: /* kLPADC_SampleChannelSingleEndSideA. */
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE
|
|
||||||
tmp32 |= ADC_CMDL_MODE(config->conversionResoultuionMode);
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
|
|
||||||
base->CMD[commandId].CMDL = tmp32;
|
|
||||||
|
|
||||||
/* ADCx_CMDH. */
|
|
||||||
tmp32 = ADC_CMDH_NEXT(config->chainedNextCommandNumber) /* Next Command Select. */
|
|
||||||
| ADC_CMDH_LOOP(config->loopCount) /* Loop Count Select. */
|
|
||||||
| ADC_CMDH_AVGS(config->hardwareAverageMode) /* Hardware Average Select. */
|
|
||||||
| ADC_CMDH_STS(config->sampleTimeMode) /* Sample Time Select. */
|
|
||||||
| ADC_CMDH_CMPEN(config->hardwareCompareMode); /* Hardware compare enable. */
|
|
||||||
#if (defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG)
|
|
||||||
if (config->enableWaitTrigger)
|
|
||||||
{
|
|
||||||
tmp32 |= ADC_CMDH_WAIT_TRIG_MASK; /* Wait trigger enable. */
|
|
||||||
}
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */
|
|
||||||
|
|
||||||
if (config->enableAutoChannelIncrement)
|
|
||||||
{
|
|
||||||
tmp32 |= ADC_CMDH_LWI_MASK;
|
|
||||||
}
|
|
||||||
base->CMD[commandId].CMDH = tmp32;
|
|
||||||
|
|
||||||
/* Hardware compare settings.
|
|
||||||
* Not all Command Buffers have an associated Compare Value register. The compare function is only available on
|
|
||||||
* Command Buffers that have a corresponding Compare Value register.
|
|
||||||
*/
|
|
||||||
if (kLPADC_HardwareCompareDisabled != config->hardwareCompareMode)
|
|
||||||
{
|
|
||||||
/* Check if the hardware compare feature is available for indicated command buffer. */
|
|
||||||
assert(commandId < ADC_CV_COUNT);
|
|
||||||
|
|
||||||
/* Set CV register. */
|
|
||||||
base->CV[commandId] = ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */
|
|
||||||
| ADC_CV_CVL(config->hardwareCompareValueLow); /* Compare value low. */
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Gets an available pre-defined settings for conversion command's configuration.
|
|
||||||
*
|
|
||||||
* This function initializes the conversion command's configuration structure with an available settings. The default
|
|
||||||
* values are:
|
|
||||||
* code
|
|
||||||
* config->sampleScaleMode = kLPADC_SampleFullScale;
|
|
||||||
* config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA;
|
|
||||||
* config->channelNumber = 0U;
|
|
||||||
* config->chainedNextCmdNumber = 0U;
|
|
||||||
* config->enableAutoChannelIncrement = false;
|
|
||||||
* config->loopCount = 0U;
|
|
||||||
* config->hardwareAverageMode = kLPADC_HardwareAverageCount1;
|
|
||||||
* config->sampleTimeMode = kLPADC_SampleTimeADCK3;
|
|
||||||
* config->hardwareCompareMode = kLPADC_HardwareCompareDisabled;
|
|
||||||
* config->hardwareCompareValueHigh = 0U;
|
|
||||||
* config->hardwareCompareValueLow = 0U;
|
|
||||||
* config->conversionResoultuionMode = kLPADC_ConversionResolutionStandard;
|
|
||||||
* config->enableWaitTrigger = false;
|
|
||||||
* endcode
|
|
||||||
* param config Pointer to configuration structure.
|
|
||||||
*/
|
|
||||||
void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config)
|
|
||||||
{
|
|
||||||
assert(config != NULL); /* Check if the input pointer is available. */
|
|
||||||
|
|
||||||
/* Initializes the configure structure to zero. */
|
|
||||||
memset(config, 0, sizeof(*config));
|
|
||||||
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE
|
|
||||||
config->sampleScaleMode = kLPADC_SampleFullScale;
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */
|
|
||||||
config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA;
|
|
||||||
config->channelNumber = 0U;
|
|
||||||
config->chainedNextCommandNumber = 0U; /* No next command defined. */
|
|
||||||
config->enableAutoChannelIncrement = false;
|
|
||||||
config->loopCount = 0U;
|
|
||||||
config->hardwareAverageMode = kLPADC_HardwareAverageCount1;
|
|
||||||
config->sampleTimeMode = kLPADC_SampleTimeADCK3;
|
|
||||||
config->hardwareCompareMode = kLPADC_HardwareCompareDisabled;
|
|
||||||
config->hardwareCompareValueHigh = 0U; /* No used. */
|
|
||||||
config->hardwareCompareValueLow = 0U; /* No used. */
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE
|
|
||||||
config->conversionResoultuionMode = kLPADC_ConversionResolutionStandard;
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG
|
|
||||||
config->enableWaitTrigger = false;
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS
|
|
||||||
/*!
|
|
||||||
* brief Enable the calibration function.
|
|
||||||
*
|
|
||||||
* When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes
|
|
||||||
* a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value
|
|
||||||
* between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6-
|
|
||||||
* bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the
|
|
||||||
* OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction.
|
|
||||||
*
|
|
||||||
* param base LPADC peripheral base address.
|
|
||||||
* bool enable switcher to the calibration function.
|
|
||||||
*/
|
|
||||||
void LPADC_EnableCalibration(ADC_Type *base, bool enable)
|
|
||||||
{
|
|
||||||
LPADC_Enable(base, false);
|
|
||||||
if (enable)
|
|
||||||
{
|
|
||||||
base->CFG |= ADC_CFG_CALOFS_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
base->CFG &= ~ADC_CFG_CALOFS_MASK;
|
|
||||||
}
|
|
||||||
LPADC_Enable(base, true);
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM
|
|
||||||
/*!
|
|
||||||
* brief Do auto calibration.
|
|
||||||
*
|
|
||||||
* Calibration function should be executed before using converter in application. It used the software trigger and a
|
|
||||||
* dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API including:
|
|
||||||
* -LPADC_EnableCalibration(...)
|
|
||||||
* -LPADC_LPADC_SetOffsetValue(...)
|
|
||||||
* -LPADC_SetConvCommandConfig(...)
|
|
||||||
* -LPADC_SetConvTriggerConfig(...)
|
|
||||||
*
|
|
||||||
* param base LPADC peripheral base address.
|
|
||||||
*/
|
|
||||||
void LPADC_DoAutoCalibration(ADC_Type *base)
|
|
||||||
{
|
|
||||||
assert(0u == LPADC_GetConvResultCount(base));
|
|
||||||
|
|
||||||
uint32_t mLpadcCMDL;
|
|
||||||
uint32_t mLpadcCMDH;
|
|
||||||
uint32_t mLpadcTrigger;
|
|
||||||
lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct;
|
|
||||||
lpadc_conv_command_config_t mLpadcCommandConfigStruct;
|
|
||||||
lpadc_conv_result_t mLpadcResultConfigStruct;
|
|
||||||
|
|
||||||
/* Enable the calibration function. */
|
|
||||||
LPADC_EnableCalibration(base, true);
|
|
||||||
|
|
||||||
/* Keep the CMD and TRG state here and restore it later if the calibration completes.*/
|
|
||||||
mLpadcCMDL = base->CMD[0].CMDL; /* CMD1L. */
|
|
||||||
mLpadcCMDH = base->CMD[0].CMDH; /* CMD1H. */
|
|
||||||
mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */
|
|
||||||
|
|
||||||
/* Set trigger0 configuration - for software trigger. */
|
|
||||||
LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct);
|
|
||||||
mLpadcTriggerConfigStruct.targetCommandId = 1U; /* CMD1 is executed. */
|
|
||||||
LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */
|
|
||||||
|
|
||||||
/* Set conversion CMD configuration. */
|
|
||||||
LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct);
|
|
||||||
mLpadcCommandConfigStruct.hardwareAverageMode = kLPADC_HardwareAverageCount128;
|
|
||||||
LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); /* Set CMD1 configuration. */
|
|
||||||
|
|
||||||
/* Do calibration. */
|
|
||||||
LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */
|
|
||||||
while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct))
|
|
||||||
{
|
|
||||||
}
|
|
||||||
/* The valid bits of data are bits 14:3 in the RESFIFO register. */
|
|
||||||
LPADC_SetOffsetValue(base, (mLpadcResultConfigStruct.convValue) >> 3U);
|
|
||||||
/* Disable the calibration function. */
|
|
||||||
LPADC_EnableCalibration(base, false);
|
|
||||||
|
|
||||||
/* restore CMD and TRG registers. */
|
|
||||||
base->CMD[0].CMDL = mLpadcCMDL; /* CMD1L. */
|
|
||||||
base->CMD[0].CMDH = mLpadcCMDH; /* CMD1H. */
|
|
||||||
base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */
|
|
||||||
}
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */
|
|
||||||
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS
|
|
||||||
/*!
|
|
||||||
* brief Do offset calibration.
|
|
||||||
*
|
|
||||||
* param base LPADC peripheral base address.
|
|
||||||
*/
|
|
||||||
void LPADC_DoOffsetCalibration(ADC_Type *base)
|
|
||||||
{
|
|
||||||
LPADC_EnableOffsetCalibration(base, true);
|
|
||||||
while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK))
|
|
||||||
{
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ
|
|
||||||
/*!
|
|
||||||
* brief Do auto calibration.
|
|
||||||
*
|
|
||||||
* param base LPADC peripheral base address.
|
|
||||||
*/
|
|
||||||
void LPADC_DoAutoCalibration(ADC_Type *base)
|
|
||||||
{
|
|
||||||
assert((0u == LPADC_GetConvResultCount(base, 0)) && (0u == LPADC_GetConvResultCount(base, 1)));
|
|
||||||
|
|
||||||
uint32_t GCCa;
|
|
||||||
uint32_t GCCb;
|
|
||||||
uint32_t GCRa;
|
|
||||||
uint32_t GCRb;
|
|
||||||
|
|
||||||
/* Request gain calibration. */
|
|
||||||
base->CTRL |= ADC_CTRL_CAL_REQ_MASK;
|
|
||||||
while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) ||
|
|
||||||
(ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK)))
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Calculate gain offset. */
|
|
||||||
GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK);
|
|
||||||
GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK);
|
|
||||||
GCRa = (uint16_t)((GCCa << 16U) /
|
|
||||||
(0xFFFFU - GCCa)); /* Gain_CalA = (65536 / (65536-(ADC_GCC_GAIN_CAL(ADC0->GCC[0])). */
|
|
||||||
GCRb = (uint16_t)((GCCb << 16U) /
|
|
||||||
(0xFFFFU - GCCb)); /* Gain_CalB = (65536 / (65536-(ADC_GCC_GAIN_CAL(ADC0->GCC[1])). */
|
|
||||||
base->GCR[0] = ADC_GCR_GCALR(GCRa);
|
|
||||||
base->GCR[1] = ADC_GCR_GCALR(GCRb);
|
|
||||||
|
|
||||||
/* Indicate the values are valid. */
|
|
||||||
base->GCR[0] |= ADC_GCR_RDY_MASK;
|
|
||||||
base->GCR[1] |= ADC_GCR_RDY_MASK;
|
|
||||||
|
|
||||||
while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK))
|
|
||||||
{
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */
|
|
||||||
|
|
@ -1,844 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
#ifndef _FSL_LPADC_H_
|
|
||||||
#define _FSL_LPADC_H_
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup lpadc
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @file */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
/*! @brief LPADC driver version 2.0.3. */
|
|
||||||
#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Define the MACRO function to get command status from status value.
|
|
||||||
*
|
|
||||||
* The statusVal is the return value from LPADC_GetStatusFlags().
|
|
||||||
*/
|
|
||||||
#define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT)
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Define the MACRO function to get trigger status from status value.
|
|
||||||
*
|
|
||||||
* The statusVal is the return value from LPADC_GetStatusFlags().
|
|
||||||
*/
|
|
||||||
#define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT)
|
|
||||||
|
|
||||||
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
|
|
||||||
/*!
|
|
||||||
* @brief Define hardware flags of the module.
|
|
||||||
*/
|
|
||||||
enum _lpadc_status_flags
|
|
||||||
{
|
|
||||||
kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, /*!< Indicates that more data has been written to the Result
|
|
||||||
FIFO 0 than it can hold. */
|
|
||||||
kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result
|
|
||||||
FIFO 0 is greater than the setting watermark level. */
|
|
||||||
kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result
|
|
||||||
FIFO 1 than it can hold. */
|
|
||||||
kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result
|
|
||||||
FIFO 1 is greater than the setting watermark level. */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Define interrupt switchers of the module.
|
|
||||||
*/
|
|
||||||
enum _lpadc_interrupt_enable
|
|
||||||
{
|
|
||||||
kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, /*!< Configures ADC to generate overflow interrupt
|
|
||||||
requests when FOF0 flag is asserted. */
|
|
||||||
kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt
|
|
||||||
requests when RDY0 flag is asserted. */
|
|
||||||
kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt
|
|
||||||
requests when FOF1 flag is asserted. */
|
|
||||||
kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt
|
|
||||||
requests when RDY1 flag is asserted. */
|
|
||||||
};
|
|
||||||
#else
|
|
||||||
/*!
|
|
||||||
* @brief Define hardware flags of the module.
|
|
||||||
*/
|
|
||||||
enum _lpadc_status_flags
|
|
||||||
{
|
|
||||||
kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO
|
|
||||||
than it can hold. */
|
|
||||||
kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO
|
|
||||||
is greater than the setting watermark level. */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Define interrupt switchers of the module.
|
|
||||||
*/
|
|
||||||
enum _lpadc_interrupt_enable
|
|
||||||
{
|
|
||||||
kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt
|
|
||||||
requests when FOF flag is asserted. */
|
|
||||||
kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt
|
|
||||||
requests when RDY flag is asserted. */
|
|
||||||
};
|
|
||||||
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Define enumeration of sample scale mode.
|
|
||||||
*
|
|
||||||
* The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum
|
|
||||||
* possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the
|
|
||||||
* reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows
|
|
||||||
* conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode.
|
|
||||||
*/
|
|
||||||
typedef enum _lpadc_sample_scale_mode
|
|
||||||
{
|
|
||||||
kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. (Factor of 30/64). */
|
|
||||||
kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */
|
|
||||||
} lpadc_sample_scale_mode_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Define enumeration of channel sample mode.
|
|
||||||
*
|
|
||||||
* The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B.
|
|
||||||
*/
|
|
||||||
typedef enum _lpadc_sample_channel_mode
|
|
||||||
{
|
|
||||||
kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */
|
|
||||||
kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF
|
|
||||||
kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minue side. */
|
|
||||||
kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minue side. */
|
|
||||||
#elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE
|
|
||||||
kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */
|
|
||||||
kLPADC_SampleChannelDualSingleEndBothSide =
|
|
||||||
3U, /*!< Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */
|
|
||||||
#endif
|
|
||||||
} lpadc_sample_channel_mode_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Define enumeration of hardware average selection.
|
|
||||||
*
|
|
||||||
* It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to
|
|
||||||
* capture temporary results while the averaging iterations are executed.
|
|
||||||
*/
|
|
||||||
typedef enum _lpadc_hardware_average_mode
|
|
||||||
{
|
|
||||||
kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */
|
|
||||||
kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */
|
|
||||||
kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */
|
|
||||||
kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */
|
|
||||||
kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */
|
|
||||||
kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */
|
|
||||||
kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */
|
|
||||||
kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */
|
|
||||||
} lpadc_hardware_average_mode_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Define enumeration of sample time selection.
|
|
||||||
*
|
|
||||||
* The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher
|
|
||||||
* impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption
|
|
||||||
* when command looping and sequencing is configured and high conversion rates are not required.
|
|
||||||
*/
|
|
||||||
typedef enum _lpadc_sample_time_mode
|
|
||||||
{
|
|
||||||
kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */
|
|
||||||
kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */
|
|
||||||
kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */
|
|
||||||
kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */
|
|
||||||
kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */
|
|
||||||
kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */
|
|
||||||
kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */
|
|
||||||
kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */
|
|
||||||
} lpadc_sample_time_mode_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Define enumeration of hardware compare mode.
|
|
||||||
*
|
|
||||||
* After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting
|
|
||||||
* guides operation of the automatic compare function to optionally only store when the compare operation is true.
|
|
||||||
* When compare is enabled, the conversion result is compared to the compare values.
|
|
||||||
*/
|
|
||||||
typedef enum _lpadc_hardware_compare_mode
|
|
||||||
{
|
|
||||||
kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */
|
|
||||||
kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */
|
|
||||||
kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */
|
|
||||||
} lpadc_hardware_compare_mode_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Define enumeration of conversion resolution mode.
|
|
||||||
*
|
|
||||||
* Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to
|
|
||||||
* #_lpadc_sample_channel_mode
|
|
||||||
*/
|
|
||||||
typedef enum _lpadc_conversion_resolution_mode
|
|
||||||
{
|
|
||||||
kLPADC_ConversionResolutionStandard = 0U, /*!< Standard resolution. Single-ended 12-bit conversion, Differential
|
|
||||||
13-bit conversion with 2’s complement output. */
|
|
||||||
kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit
|
|
||||||
conversion with 2’s complement output. */
|
|
||||||
} lpadc_conversion_resolution_mode_t;
|
|
||||||
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
|
|
||||||
/*!
|
|
||||||
* @brief Define enumeration of conversion averages mode.
|
|
||||||
*
|
|
||||||
* Configure the converion average number for auto-calibration.
|
|
||||||
*/
|
|
||||||
typedef enum _lpadc_conversion_average_mode
|
|
||||||
{
|
|
||||||
kLPADC_ConversionAverage1 = 0U, /*!< Single conversion. */
|
|
||||||
kLPADC_ConversionAverage2 = 1U, /*!< 2 conversions averaged. */
|
|
||||||
kLPADC_ConversionAverage4 = 2U, /*!< 4 conversions averaged. */
|
|
||||||
kLPADC_ConversionAverage8 = 3U, /*!< 8 conversions averaged. */
|
|
||||||
kLPADC_ConversionAverage16 = 4U, /*!< 16 conversions averaged. */
|
|
||||||
kLPADC_ConversionAverage32 = 5U, /*!< 32 conversions averaged. */
|
|
||||||
kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */
|
|
||||||
kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */
|
|
||||||
} lpadc_conversion_average_mode_t;
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Define enumeration of reference voltage source.
|
|
||||||
*
|
|
||||||
* For detail information, need to check the SoC's specification.
|
|
||||||
*/
|
|
||||||
typedef enum _lpadc_reference_voltage_mode
|
|
||||||
{
|
|
||||||
kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */
|
|
||||||
kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */
|
|
||||||
kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */
|
|
||||||
} lpadc_reference_voltage_source_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Define enumeration of power configuration.
|
|
||||||
*
|
|
||||||
* Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be
|
|
||||||
* possible. Refer to the device data sheet for power and performance capabilities for each setting.
|
|
||||||
*/
|
|
||||||
typedef enum _lpadc_power_level_mode
|
|
||||||
{
|
|
||||||
kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */
|
|
||||||
kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */
|
|
||||||
kLPADC_PowerLevelAlt3 = 2U, /*!< ... */
|
|
||||||
kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */
|
|
||||||
} lpadc_power_level_mode_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Define enumeration of trigger priority policy.
|
|
||||||
*
|
|
||||||
* This selection controls how higher priority triggers are handled.
|
|
||||||
*/
|
|
||||||
typedef enum _lpadc_trigger_priority_policy
|
|
||||||
{
|
|
||||||
kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command
|
|
||||||
processing, the current conversion is aborted and the new
|
|
||||||
command specified by the trigger is started. */
|
|
||||||
kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing,
|
|
||||||
the current conversion is completed (including averaging iterations
|
|
||||||
and compare function if enabled) and stored to the result FIFO
|
|
||||||
before the higher priority trigger/command is initiated. */
|
|
||||||
kLPADC_TriggerPriorityPreemptSubsequently =
|
|
||||||
2U, /*!< If a higher priority trigger is received during command processing, the current
|
|
||||||
command will be completed (averaging, looping, compare) before servicing the
|
|
||||||
higher priority trigger. */
|
|
||||||
} lpadc_trigger_priority_policy_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @beief LPADC global configuration.
|
|
||||||
*
|
|
||||||
* This structure would used to keep the settings for initialization.
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN
|
|
||||||
bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock
|
|
||||||
selection logic at the chip level and is optionally used for the ADC clock source. */
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG
|
|
||||||
bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true".
|
|
||||||
If voltage reference option1 input is above 1.8V, it should be "false". */
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */
|
|
||||||
bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When
|
|
||||||
enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the
|
|
||||||
ADC will wait for the current averaging iteration/FIFO storage to complete before
|
|
||||||
acknowledging stop or wait mode entry. */
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
|
|
||||||
lpadc_conversion_average_mode_t conversionAverageMode; /*!< Auto-Calibration Averages. */
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
|
|
||||||
bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without
|
|
||||||
startup delays(at the cost of higher DC current consumption). */
|
|
||||||
uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered
|
|
||||||
while the ADC is active and there is a counted delay defined by this field after an
|
|
||||||
initial trigger transitions the ADC from its Idle state to allow time for the analog
|
|
||||||
circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must
|
|
||||||
result in a longer delay than the analog startup time. */
|
|
||||||
lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for
|
|
||||||
conversions.*/
|
|
||||||
lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */
|
|
||||||
lpadc_trigger_priority_policy_t triggerPrioirtyPolicy; /*!< Control how higher priority triggers are handled, see to
|
|
||||||
#lpadc_trigger_priority_policy_mode_t. */
|
|
||||||
bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during
|
|
||||||
command execution sequencing between LOOP iterations, between commands in a sequence, and
|
|
||||||
between conversions when command is executing in "Compare Until True" configuration. */
|
|
||||||
uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay
|
|
||||||
is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing
|
|
||||||
function is enabled. The available value range is in 9-bit. */
|
|
||||||
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
|
|
||||||
/* for FIFO0. */
|
|
||||||
uint32_t
|
|
||||||
FIFO0Watermark; /*!< FIFO0Watermark is a programmable threshold setting. When the number of datawords stored
|
|
||||||
in the ADC Result FIFO0 is greater than the value in this field, the ready flag would be
|
|
||||||
asserted to indicate stored data has reached the programmable threshold. */
|
|
||||||
/* for FIFO1. */
|
|
||||||
uint32_t
|
|
||||||
FIFO1Watermark; /*!< FIFO1Watermark is a programmable threshold setting. When the number of datawords stored
|
|
||||||
in the ADC Result FIFO1 is greater than the value in this field, the ready flag would be
|
|
||||||
asserted to indicate stored data has reached the programmable threshold. */
|
|
||||||
#else
|
|
||||||
/* for FIFO. */
|
|
||||||
uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored
|
|
||||||
in the ADC Result FIFO is greater than the value in this field, the ready flag would be
|
|
||||||
asserted to indicate stored data has reached the programmable threshold. */
|
|
||||||
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
|
|
||||||
} lpadc_config_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Define structure to keep the configuration for conversion command.
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE
|
|
||||||
lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */
|
|
||||||
lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */
|
|
||||||
uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */
|
|
||||||
uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes.
|
|
||||||
1-15 is available, 0 is to terminate the chain after this command. */
|
|
||||||
bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number
|
|
||||||
of times the selected channel is converted consecutively; when enabled, the
|
|
||||||
"loopCount" field defines how many consecutive channels are converted as part
|
|
||||||
of the command execution. */
|
|
||||||
uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next
|
|
||||||
command or Idle state. Command executes LOOP+1 times. 0-15 is available. */
|
|
||||||
lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */
|
|
||||||
lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */
|
|
||||||
|
|
||||||
lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */
|
|
||||||
uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */
|
|
||||||
uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE
|
|
||||||
lpadc_conversion_resolution_mode_t conversionResoultuionMode; /*!< Conversion resolution mode. */
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG
|
|
||||||
bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be
|
|
||||||
automatically executed; when enabled, the active trigger must be asserted again before
|
|
||||||
executing this command. */
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */
|
|
||||||
} lpadc_conv_command_config_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Define structure to keep the configuration for conversion trigger.
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated
|
|
||||||
trigger event. */
|
|
||||||
uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event.
|
|
||||||
When this field is clear, then no delay is incurred. When this field is set to a non-zero
|
|
||||||
value, the duration for the delay is 2^delayPower ADCK cycles. The available value range
|
|
||||||
is 4-bit. */
|
|
||||||
uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same
|
|
||||||
priority level setting, the lower order trigger event has the higher priority. The lower
|
|
||||||
value for this field is for the higher priority, the available value range is 1-bit. */
|
|
||||||
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
|
|
||||||
uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */
|
|
||||||
uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */
|
|
||||||
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
|
|
||||||
bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the
|
|
||||||
input trigger source or not. THe software trigger is always available. */
|
|
||||||
} lpadc_conv_trigger_config_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Define the structure to keep the conversion result.
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */
|
|
||||||
uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */
|
|
||||||
uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */
|
|
||||||
uint16_t convValue; /*!< Data result. */
|
|
||||||
} lpadc_conv_result_t;
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
/*!
|
|
||||||
* @name Initialization & de-initialization.
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initializes the LPADC module.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @param config Pointer to configuration structure. See "lpadc_config_t".
|
|
||||||
*/
|
|
||||||
void LPADC_Init(ADC_Type *base, const lpadc_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Gets an available pre-defined settings for initial configuration.
|
|
||||||
*
|
|
||||||
* This function initializes the converter configuration structure with an available settings. The default values are:
|
|
||||||
* @code
|
|
||||||
* config->enableInDozeMode = true;
|
|
||||||
* config->enableAnalogPreliminary = false;
|
|
||||||
* config->powerUpDelay = 0x80;
|
|
||||||
* config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1;
|
|
||||||
* config->powerLevelMode = kLPADC_PowerLevelAlt1;
|
|
||||||
* config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately;
|
|
||||||
* config->enableConvPause = false;
|
|
||||||
* config->convPauseDelay = 0U;
|
|
||||||
* config->FIFOWatermark = 0U;
|
|
||||||
* @endcode
|
|
||||||
* @param config Pointer to configuration structure.
|
|
||||||
*/
|
|
||||||
void LPADC_GetDefaultConfig(lpadc_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief De-initializes the LPADC module.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
*/
|
|
||||||
void LPADC_Deinit(ADC_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Switch on/off the LPADC module.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @param enable switcher to the module.
|
|
||||||
*/
|
|
||||||
static inline void LPADC_Enable(ADC_Type *base, bool enable)
|
|
||||||
{
|
|
||||||
if (enable)
|
|
||||||
{
|
|
||||||
base->CTRL |= ADC_CTRL_ADCEN_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
base->CTRL &= ~ADC_CTRL_ADCEN_MASK;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
|
|
||||||
/*!
|
|
||||||
* @brief Do reset the conversion FIFO0.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
*/
|
|
||||||
static inline void LPADC_DoResetFIFO0(ADC_Type *base)
|
|
||||||
{
|
|
||||||
base->CTRL |= ADC_CTRL_RSTFIFO0_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Do reset the conversion FIFO1.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
*/
|
|
||||||
static inline void LPADC_DoResetFIFO1(ADC_Type *base)
|
|
||||||
{
|
|
||||||
base->CTRL |= ADC_CTRL_RSTFIFO1_MASK;
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
/*!
|
|
||||||
* @brief Do reset the conversion FIFO.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
*/
|
|
||||||
static inline void LPADC_DoResetFIFO(ADC_Type *base)
|
|
||||||
{
|
|
||||||
base->CTRL |= ADC_CTRL_RSTFIFO_MASK;
|
|
||||||
}
|
|
||||||
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Do reset the module's configuration.
|
|
||||||
*
|
|
||||||
* Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL).
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
*/
|
|
||||||
static inline void LPADC_DoResetConfig(ADC_Type *base)
|
|
||||||
{
|
|
||||||
base->CTRL |= ADC_CTRL_RST_MASK;
|
|
||||||
base->CTRL &= ~ADC_CTRL_RST_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Status
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get status flags.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @return status flags' mask. See to #_lpadc_status_flags.
|
|
||||||
*/
|
|
||||||
static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base)
|
|
||||||
{
|
|
||||||
return base->STAT;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Clear status flags.
|
|
||||||
*
|
|
||||||
* Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags.
|
|
||||||
*/
|
|
||||||
static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
|
|
||||||
{
|
|
||||||
base->STAT = mask;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Interrupts
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enable interrupts.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @mask Mask value for interrupt events. See to #_lpadc_interrupt_enable.
|
|
||||||
*/
|
|
||||||
static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask)
|
|
||||||
{
|
|
||||||
base->IE |= mask;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Disable interrupts.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable.
|
|
||||||
*/
|
|
||||||
static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask)
|
|
||||||
{
|
|
||||||
base->IE &= ~mask;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name DMA Control
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
|
|
||||||
/*!
|
|
||||||
* @brief Switch on/off the DMA trigger for FIFO0 watermark event.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @param enable Switcher to the event.
|
|
||||||
*/
|
|
||||||
static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable)
|
|
||||||
{
|
|
||||||
if (enable)
|
|
||||||
{
|
|
||||||
base->DE |= ADC_DE_FWMDE0_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
base->DE &= ~ADC_DE_FWMDE0_MASK;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Switch on/off the DMA trigger for FIFO1 watermark event.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @param enable Switcher to the event.
|
|
||||||
*/
|
|
||||||
static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable)
|
|
||||||
{
|
|
||||||
if (enable)
|
|
||||||
{
|
|
||||||
base->DE |= ADC_DE_FWMDE1_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
base->DE &= ~ADC_DE_FWMDE1_MASK;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
/*!
|
|
||||||
* @brief Switch on/off the DMA trigger for FIFO watermark event.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @param enable Switcher to the event.
|
|
||||||
*/
|
|
||||||
static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable)
|
|
||||||
{
|
|
||||||
if (enable)
|
|
||||||
{
|
|
||||||
base->DE |= ADC_DE_FWMDE_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
base->DE &= ~ADC_DE_FWMDE_MASK;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Trigger and conversion with FIFO.
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
|
|
||||||
/*!
|
|
||||||
* @brief Get the count of result kept in conversion FIFOn.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @param index Result FIFO index.
|
|
||||||
* @return The count of result kept in conversion FIFOn.
|
|
||||||
*/
|
|
||||||
static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index)
|
|
||||||
{
|
|
||||||
return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Get the result in conversion FIFOn.
|
|
||||||
*
|
|
||||||
* param base LPADC peripheral base address.
|
|
||||||
* param result Pointer to structure variable that keeps the conversion result in conversion FIFOn.
|
|
||||||
* param index Result FIFO index.
|
|
||||||
*
|
|
||||||
* return Status whether FIFOn entry is valid.
|
|
||||||
*/
|
|
||||||
bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index);
|
|
||||||
#else
|
|
||||||
/*!
|
|
||||||
* @brief Get the count of result kept in conversion FIFO.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @return The count of result kept in conversion FIFO.
|
|
||||||
*/
|
|
||||||
static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base)
|
|
||||||
{
|
|
||||||
return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get the result in conversion FIFO.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @param result Pointer to structure variable that keeps the conversion result in conversion FIFO.
|
|
||||||
*
|
|
||||||
* @return Status whether FIFO entry is valid.
|
|
||||||
*/
|
|
||||||
bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result);
|
|
||||||
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Configure the conversion trigger source.
|
|
||||||
*
|
|
||||||
* Each programmable trigger can launch the conversion command in command buffer.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @param triggerId ID for each trigger. Typically, the available value range is from 0.
|
|
||||||
* @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t.
|
|
||||||
*/
|
|
||||||
void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Gets an available pre-defined settings for trigger's configuration.
|
|
||||||
*
|
|
||||||
* This function initializes the trigger's configuration structure with an available settings. The default values are:
|
|
||||||
* @code
|
|
||||||
* config->commandIdSource = 0U;
|
|
||||||
* config->loopCountIndex = 0U;
|
|
||||||
* config->triggerIdSource = 0U;
|
|
||||||
* config->enableHardwareTrigger = false;
|
|
||||||
* @endcode
|
|
||||||
* @param config Pointer to configuration structure.
|
|
||||||
*/
|
|
||||||
void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Do software trigger to conversion command.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @param triggerIdMask Mask value for software trigger indexes, which count from zero.
|
|
||||||
*/
|
|
||||||
static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask)
|
|
||||||
{
|
|
||||||
/* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */
|
|
||||||
base->SWTRIG = triggerIdMask;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Configure conversion command.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15.
|
|
||||||
* @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t.
|
|
||||||
*/
|
|
||||||
void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Gets an available pre-defined settings for conversion command's configuration.
|
|
||||||
*
|
|
||||||
* This function initializes the conversion command's configuration structure with an available settings. The default
|
|
||||||
* values are:
|
|
||||||
* @code
|
|
||||||
* config->sampleScaleMode = kLPADC_SampleFullScale;
|
|
||||||
* config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA;
|
|
||||||
* config->channelNumber = 0U;
|
|
||||||
* config->chainedNextCmdNumber = 0U;
|
|
||||||
* config->enableAutoChannelIncrement = false;
|
|
||||||
* config->loopCount = 0U;
|
|
||||||
* config->hardwareAverageMode = kLPADC_HardwareAverageCount1;
|
|
||||||
* config->sampleTimeMode = kLPADC_SampleTimeADCK3;
|
|
||||||
* config->hardwareCompareMode = kLPADC_HardwareCompareDisabled;
|
|
||||||
* config->hardwareCompareValueHigh = 0U;
|
|
||||||
* config->hardwareCompareValueLow = 0U;
|
|
||||||
* config->conversionResoultuionMode = kLPADC_ConversionResolutionStandard;
|
|
||||||
* config->enableWaitTrigger = false;
|
|
||||||
* @endcode
|
|
||||||
* @param config Pointer to configuration structure.
|
|
||||||
*/
|
|
||||||
void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config);
|
|
||||||
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS
|
|
||||||
/*!
|
|
||||||
* @brief Enable the calibration function.
|
|
||||||
*
|
|
||||||
* When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes
|
|
||||||
* a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value
|
|
||||||
* between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6-
|
|
||||||
* bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the
|
|
||||||
* OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @bool enable switcher to the calibration function.
|
|
||||||
*/
|
|
||||||
void LPADC_EnableCalibration(ADC_Type *base, bool enable);
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM
|
|
||||||
/*!
|
|
||||||
* @brief Set proper offset value to trim ADC.
|
|
||||||
*
|
|
||||||
* To minimize the offset during normal operation, software should read the conversion result from
|
|
||||||
* the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @param value Setting offset value.
|
|
||||||
*/
|
|
||||||
static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value)
|
|
||||||
{
|
|
||||||
base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Do auto calibration.
|
|
||||||
*
|
|
||||||
* Calibration function should be executed before using converter in application. It used the software trigger and a
|
|
||||||
* dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API including:
|
|
||||||
* -LPADC_EnableCalibration(...)
|
|
||||||
* -LPADC_LPADC_SetOffsetValue(...)
|
|
||||||
* -LPADC_SetConvCommandConfig(...)
|
|
||||||
* -LPADC_SetConvTriggerConfig(...)
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
*/
|
|
||||||
void LPADC_DoAutoCalibration(ADC_Type *base);
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */
|
|
||||||
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM
|
|
||||||
/*!
|
|
||||||
* @brief Set proper offset value to trim ADC.
|
|
||||||
*
|
|
||||||
* Set the offset trim value for offset calibration manually.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @param valueA Setting offset value A.
|
|
||||||
* @param valueB Setting offset value B.
|
|
||||||
* @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration.
|
|
||||||
*/
|
|
||||||
static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_t valueB)
|
|
||||||
{
|
|
||||||
base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB);
|
|
||||||
}
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enable the offset calibration function.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
* @bool enable switcher to the calibration function.
|
|
||||||
*/
|
|
||||||
static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable)
|
|
||||||
{
|
|
||||||
if (enable)
|
|
||||||
{
|
|
||||||
base->CTRL |= ADC_CTRL_CALOFS_MASK;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
base->CTRL &= ~ADC_CTRL_CALOFS_MASK;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Do offset calibration.
|
|
||||||
*
|
|
||||||
* @param base LPADC peripheral base address.
|
|
||||||
*/
|
|
||||||
void LPADC_DoOffsetCalibration(ADC_Type *base);
|
|
||||||
|
|
||||||
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ
|
|
||||||
/*!
|
|
||||||
* brief Do auto calibration.
|
|
||||||
*
|
|
||||||
* param base LPADC peripheral base address.
|
|
||||||
*/
|
|
||||||
void LPADC_DoAutoCalibration(ADC_Type *base);
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */
|
|
||||||
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
/*!
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
#endif /* _FSL_LPADC_H_ */
|
|
||||||
|
|
@ -1,214 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright(C) NXP Semiconductors, 2014
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _FSL_MAILBOX_H_
|
|
||||||
#define _FSL_MAILBOX_H_
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup mailbox
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @file */
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
*****************************************************************************/
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.mailbox"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
/*! @brief MAILBOX driver version 2.1.0. */
|
|
||||||
#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief CPU ID.
|
|
||||||
*/
|
|
||||||
#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES))
|
|
||||||
typedef enum _mailbox_cpu_id
|
|
||||||
{
|
|
||||||
kMAILBOX_CM33_Core1 = 0,
|
|
||||||
kMAILBOX_CM33_Core0
|
|
||||||
} mailbox_cpu_id_t;
|
|
||||||
#else
|
|
||||||
typedef enum _mailbox_cpu_id
|
|
||||||
{
|
|
||||||
kMAILBOX_CM0Plus = 0,
|
|
||||||
kMAILBOX_CM4
|
|
||||||
} mailbox_cpu_id_t;
|
|
||||||
#endif
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name MAILBOX initialization
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initializes the MAILBOX module.
|
|
||||||
*
|
|
||||||
* This function enables the MAILBOX clock only.
|
|
||||||
*
|
|
||||||
* @param base MAILBOX peripheral base address.
|
|
||||||
*/
|
|
||||||
static inline void MAILBOX_Init(MAILBOX_Type *base)
|
|
||||||
{
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
CLOCK_EnableClock(kCLOCK_Mailbox);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
#if !(defined(FSL_FEATURE_MAILBOX_HAS_NO_RESET) && FSL_FEATURE_MAILBOX_HAS_NO_RESET)
|
|
||||||
/* Reset the MAILBOX module */
|
|
||||||
RESET_PeripheralReset(kMAILBOX_RST_SHIFT_RSTn);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief De-initializes the MAILBOX module.
|
|
||||||
*
|
|
||||||
* This function disables the MAILBOX clock only.
|
|
||||||
*
|
|
||||||
* @param base MAILBOX peripheral base address.
|
|
||||||
*/
|
|
||||||
static inline void MAILBOX_Deinit(MAILBOX_Type *base)
|
|
||||||
{
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
CLOCK_DisableClock(kCLOCK_Mailbox);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
}
|
|
||||||
|
|
||||||
/* @} */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set data value in the mailbox based on the CPU ID.
|
|
||||||
*
|
|
||||||
* @param base MAILBOX peripheral base address.
|
|
||||||
* @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices,
|
|
||||||
* kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices.
|
|
||||||
* @param mboxData Data to send in the mailbox.
|
|
||||||
*
|
|
||||||
* @note Sets a data value to send via the MAILBOX to the other core.
|
|
||||||
*/
|
|
||||||
static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxData)
|
|
||||||
{
|
|
||||||
#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES))
|
|
||||||
assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
|
|
||||||
#else
|
|
||||||
assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
|
|
||||||
#endif
|
|
||||||
base->MBOXIRQ[cpu_id].IRQ = mboxData;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get data in the mailbox based on the CPU ID.
|
|
||||||
*
|
|
||||||
* @param base MAILBOX peripheral base address.
|
|
||||||
* @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices,
|
|
||||||
* kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices.
|
|
||||||
*
|
|
||||||
* @return Current mailbox data.
|
|
||||||
*/
|
|
||||||
static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id)
|
|
||||||
{
|
|
||||||
#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES))
|
|
||||||
assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
|
|
||||||
#else
|
|
||||||
assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
|
|
||||||
#endif
|
|
||||||
return base->MBOXIRQ[cpu_id].IRQ;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set data bits in the mailbox based on the CPU ID.
|
|
||||||
*
|
|
||||||
* @param base MAILBOX peripheral base address.
|
|
||||||
* @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices,
|
|
||||||
* kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices.
|
|
||||||
* @param mboxSetBits Data bits to set in the mailbox.
|
|
||||||
*
|
|
||||||
* @note Sets data bits to send via the MAILBOX to the other core. A value of 0 will
|
|
||||||
* do nothing. Only sets bits selected with a 1 in it's bit position.
|
|
||||||
*/
|
|
||||||
static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxSetBits)
|
|
||||||
{
|
|
||||||
#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES))
|
|
||||||
assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
|
|
||||||
#else
|
|
||||||
assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
|
|
||||||
#endif
|
|
||||||
base->MBOXIRQ[cpu_id].IRQSET = mboxSetBits;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Clear data bits in the mailbox based on the CPU ID.
|
|
||||||
*
|
|
||||||
* @param base MAILBOX peripheral base address.
|
|
||||||
* @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices,
|
|
||||||
* kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices.
|
|
||||||
* @param mboxClrBits Data bits to clear in the mailbox.
|
|
||||||
*
|
|
||||||
* @note Clear data bits to send via the MAILBOX to the other core. A value of 0 will
|
|
||||||
* do nothing. Only clears bits selected with a 1 in it's bit position.
|
|
||||||
*/
|
|
||||||
static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxClrBits)
|
|
||||||
{
|
|
||||||
#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES))
|
|
||||||
assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
|
|
||||||
#else
|
|
||||||
assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
|
|
||||||
#endif
|
|
||||||
base->MBOXIRQ[cpu_id].IRQCLR = mboxClrBits;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get MUTEX state and lock mutex
|
|
||||||
*
|
|
||||||
* @param base MAILBOX peripheral base address.
|
|
||||||
*
|
|
||||||
* @return See note
|
|
||||||
*
|
|
||||||
* @note Returns '1' if the mutex was taken or '0' if another resources has the
|
|
||||||
* mutex locked. Once a mutex is taken, it can be returned with the MAILBOX_SetMutex()
|
|
||||||
* function.
|
|
||||||
*/
|
|
||||||
static inline uint32_t MAILBOX_GetMutex(MAILBOX_Type *base)
|
|
||||||
{
|
|
||||||
return (base->MUTEX & MAILBOX_MUTEX_EX_MASK);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set MUTEX state
|
|
||||||
*
|
|
||||||
* @param base MAILBOX peripheral base address.
|
|
||||||
*
|
|
||||||
* @note Sets mutex state to '1' and allows other resources to get the mutex.
|
|
||||||
*/
|
|
||||||
static inline void MAILBOX_SetMutex(MAILBOX_Type *base)
|
|
||||||
{
|
|
||||||
base->MUTEX = MAILBOX_MUTEX_EX_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif /*_cplusplus*/
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
#endif /* _FSL_MAILBOX_H_ */
|
|
||||||
|
|
@ -1,150 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "fsl_mrt.h"
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.mrt"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Prototypes
|
|
||||||
******************************************************************************/
|
|
||||||
/*!
|
|
||||||
* @brief Gets the instance from the base address
|
|
||||||
*
|
|
||||||
* @param base Multi-Rate timer peripheral base address
|
|
||||||
*
|
|
||||||
* @return The MRT instance
|
|
||||||
*/
|
|
||||||
static uint32_t MRT_GetInstance(MRT_Type *base);
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables
|
|
||||||
******************************************************************************/
|
|
||||||
/*! @brief Pointers to MRT bases for each instance. */
|
|
||||||
static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS;
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/*! @brief Pointers to MRT clocks for each instance. */
|
|
||||||
static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS;
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
||||||
#if defined(FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET
|
|
||||||
/*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */
|
|
||||||
static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N;
|
|
||||||
#else
|
|
||||||
/*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */
|
|
||||||
static const reset_ip_name_t s_mrtResets[] = MRT_RSTS;
|
|
||||||
#endif
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code
|
|
||||||
******************************************************************************/
|
|
||||||
static uint32_t MRT_GetInstance(MRT_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t instance;
|
|
||||||
uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0]));
|
|
||||||
|
|
||||||
/* Find the instance index from base address mappings. */
|
|
||||||
for (instance = 0; instance < mrtArrayCount; instance++)
|
|
||||||
{
|
|
||||||
if (s_mrtBases[instance] == base)
|
|
||||||
{
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
assert(instance < mrtArrayCount);
|
|
||||||
|
|
||||||
return instance;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Ungates the MRT clock and configures the peripheral for basic operation.
|
|
||||||
*
|
|
||||||
* note This API should be called at the beginning of the application using the MRT driver.
|
|
||||||
*
|
|
||||||
* param base Multi-Rate timer peripheral base address
|
|
||||||
* param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in
|
|
||||||
* MODCFG reigster, param config is useless.
|
|
||||||
*/
|
|
||||||
void MRT_Init(MRT_Type *base, const mrt_config_t *config)
|
|
||||||
{
|
|
||||||
assert(config);
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Ungate the MRT clock */
|
|
||||||
CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
||||||
/* Reset the module. */
|
|
||||||
RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK)
|
|
||||||
/* Set timer operating mode */
|
|
||||||
base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Gate the MRT clock
|
|
||||||
*
|
|
||||||
* param base Multi-Rate timer peripheral base address
|
|
||||||
*/
|
|
||||||
void MRT_Deinit(MRT_Type *base)
|
|
||||||
{
|
|
||||||
/* Stop all the timers */
|
|
||||||
MRT_StopTimer(base, kMRT_Channel_0);
|
|
||||||
MRT_StopTimer(base, kMRT_Channel_1);
|
|
||||||
#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 2U)
|
|
||||||
MRT_StopTimer(base, kMRT_Channel_2);
|
|
||||||
#endif
|
|
||||||
#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 3U)
|
|
||||||
MRT_StopTimer(base, kMRT_Channel_3);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Gate the MRT clock*/
|
|
||||||
CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Used to update the timer period in units of count.
|
|
||||||
*
|
|
||||||
* The new value will be immediately loaded or will be loaded at the end of the current time
|
|
||||||
* interval. For one-shot interrupt mode the new value will be immediately loaded.
|
|
||||||
*
|
|
||||||
* note User can call the utility macros provided in fsl_common.h to convert to ticks
|
|
||||||
*
|
|
||||||
* param base Multi-Rate timer peripheral base address
|
|
||||||
* param channel Timer channel number
|
|
||||||
* param count Timer period in units of ticks
|
|
||||||
* param immediateLoad true: Load the new value immediately into the TIMER register;
|
|
||||||
* false: Load the new value at the end of current timer interval
|
|
||||||
*/
|
|
||||||
void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
|
|
||||||
|
|
||||||
uint32_t newValue = count;
|
|
||||||
if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == kMRT_OneShotMode) || (immediateLoad))
|
|
||||||
{
|
|
||||||
/* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */
|
|
||||||
newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Update the timer interval value */
|
|
||||||
base->CHANNEL[channel].INTVAL = newValue;
|
|
||||||
}
|
|
||||||
|
|
@ -1,365 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
#ifndef _FSL_MRT_H_
|
|
||||||
#define _FSL_MRT_H_
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup mrt
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @file */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*! @brief List of MRT channels */
|
|
||||||
typedef enum _mrt_chnl
|
|
||||||
{
|
|
||||||
kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/
|
|
||||||
kMRT_Channel_1, /*!< MRT channel number 1 */
|
|
||||||
kMRT_Channel_2, /*!< MRT channel number 2 */
|
|
||||||
kMRT_Channel_3 /*!< MRT channel number 3 */
|
|
||||||
} mrt_chnl_t;
|
|
||||||
|
|
||||||
/*! @brief List of MRT timer modes */
|
|
||||||
typedef enum _mrt_timer_mode
|
|
||||||
{
|
|
||||||
kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< Repeat Interrupt mode */
|
|
||||||
kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< One-shot Interrupt mode */
|
|
||||||
kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */
|
|
||||||
} mrt_timer_mode_t;
|
|
||||||
|
|
||||||
/*! @brief List of MRT interrupts */
|
|
||||||
typedef enum _mrt_interrupt_enable
|
|
||||||
{
|
|
||||||
kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/
|
|
||||||
} mrt_interrupt_enable_t;
|
|
||||||
|
|
||||||
/*! @brief List of MRT status flags */
|
|
||||||
typedef enum _mrt_status_flags
|
|
||||||
{
|
|
||||||
kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */
|
|
||||||
kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK, /*!< Indicates state of the timer */
|
|
||||||
} mrt_status_flags_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief MRT configuration structure
|
|
||||||
*
|
|
||||||
* This structure holds the configuration settings for the MRT peripheral. To initialize this
|
|
||||||
* structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a
|
|
||||||
* pointer to your config structure instance.
|
|
||||||
*
|
|
||||||
* The config struct can be made const so it resides in flash
|
|
||||||
*/
|
|
||||||
typedef struct _mrt_config
|
|
||||||
{
|
|
||||||
bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */
|
|
||||||
} mrt_config_t;
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Initialization and deinitialization
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Ungates the MRT clock and configures the peripheral for basic operation.
|
|
||||||
*
|
|
||||||
* @note This API should be called at the beginning of the application using the MRT driver.
|
|
||||||
*
|
|
||||||
* @param base Multi-Rate timer peripheral base address
|
|
||||||
* @param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in
|
|
||||||
* MODCFG reigster, param config is useless.
|
|
||||||
*/
|
|
||||||
void MRT_Init(MRT_Type *base, const mrt_config_t *config);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Gate the MRT clock
|
|
||||||
*
|
|
||||||
* @param base Multi-Rate timer peripheral base address
|
|
||||||
*/
|
|
||||||
void MRT_Deinit(MRT_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Fill in the MRT config struct with the default settings
|
|
||||||
*
|
|
||||||
* The default values are:
|
|
||||||
* @code
|
|
||||||
* config->enableMultiTask = false;
|
|
||||||
* @endcode
|
|
||||||
* @param config Pointer to user's MRT config structure.
|
|
||||||
*/
|
|
||||||
static inline void MRT_GetDefaultConfig(mrt_config_t *config)
|
|
||||||
{
|
|
||||||
assert(config);
|
|
||||||
#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK)
|
|
||||||
/* Use hardware status operating mode */
|
|
||||||
config->enableMultiTask = false;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Sets up an MRT channel mode.
|
|
||||||
*
|
|
||||||
* @param base Multi-Rate timer peripheral base address
|
|
||||||
* @param channel Channel that is being configured.
|
|
||||||
* @param mode Timer mode to use for the channel.
|
|
||||||
*/
|
|
||||||
static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
|
|
||||||
|
|
||||||
uint32_t reg = base->CHANNEL[channel].CTRL;
|
|
||||||
|
|
||||||
/* Clear old value */
|
|
||||||
reg &= ~MRT_CHANNEL_CTRL_MODE_MASK;
|
|
||||||
/* Add the new mode */
|
|
||||||
reg |= mode;
|
|
||||||
|
|
||||||
base->CHANNEL[channel].CTRL = reg;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! @}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Interrupt Interface
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Enables the MRT interrupt.
|
|
||||||
*
|
|
||||||
* @param base Multi-Rate timer peripheral base address
|
|
||||||
* @param channel Timer channel number
|
|
||||||
* @param mask The interrupts to enable. This is a logical OR of members of the
|
|
||||||
* enumeration ::mrt_interrupt_enable_t
|
|
||||||
*/
|
|
||||||
static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
|
|
||||||
base->CHANNEL[channel].CTRL |= mask;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Disables the selected MRT interrupt.
|
|
||||||
*
|
|
||||||
* @param base Multi-Rate timer peripheral base address
|
|
||||||
* @param channel Timer channel number
|
|
||||||
* @param mask The interrupts to disable. This is a logical OR of members of the
|
|
||||||
* enumeration ::mrt_interrupt_enable_t
|
|
||||||
*/
|
|
||||||
static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
|
|
||||||
base->CHANNEL[channel].CTRL &= ~mask;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Gets the enabled MRT interrupts.
|
|
||||||
*
|
|
||||||
* @param base Multi-Rate timer peripheral base address
|
|
||||||
* @param channel Timer channel number
|
|
||||||
*
|
|
||||||
* @return The enabled interrupts. This is the logical OR of members of the
|
|
||||||
* enumeration ::mrt_interrupt_enable_t
|
|
||||||
*/
|
|
||||||
static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
|
|
||||||
return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! @}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Status Interface
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Gets the MRT status flags
|
|
||||||
*
|
|
||||||
* @param base Multi-Rate timer peripheral base address
|
|
||||||
* @param channel Timer channel number
|
|
||||||
*
|
|
||||||
* @return The status flags. This is the logical OR of members of the
|
|
||||||
* enumeration ::mrt_status_flags_t
|
|
||||||
*/
|
|
||||||
static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
|
|
||||||
return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK));
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Clears the MRT status flags.
|
|
||||||
*
|
|
||||||
* @param base Multi-Rate timer peripheral base address
|
|
||||||
* @param channel Timer channel number
|
|
||||||
* @param mask The status flags to clear. This is a logical OR of members of the
|
|
||||||
* enumeration ::mrt_status_flags_t
|
|
||||||
*/
|
|
||||||
static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
|
|
||||||
base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! @}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Read and Write the timer period
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Used to update the timer period in units of count.
|
|
||||||
*
|
|
||||||
* The new value will be immediately loaded or will be loaded at the end of the current time
|
|
||||||
* interval. For one-shot interrupt mode the new value will be immediately loaded.
|
|
||||||
*
|
|
||||||
* @note User can call the utility macros provided in fsl_common.h to convert to ticks
|
|
||||||
*
|
|
||||||
* @param base Multi-Rate timer peripheral base address
|
|
||||||
* @param channel Timer channel number
|
|
||||||
* @param count Timer period in units of ticks
|
|
||||||
* @param immediateLoad true: Load the new value immediately into the TIMER register;
|
|
||||||
* false: Load the new value at the end of current timer interval
|
|
||||||
*/
|
|
||||||
void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Reads the current timer counting value.
|
|
||||||
*
|
|
||||||
* This function returns the real-time timer counting value, in a range from 0 to a
|
|
||||||
* timer period.
|
|
||||||
*
|
|
||||||
* @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
|
|
||||||
*
|
|
||||||
* @param base Multi-Rate timer peripheral base address
|
|
||||||
* @param channel Timer channel number
|
|
||||||
*
|
|
||||||
* @return Current timer counting value in ticks
|
|
||||||
*/
|
|
||||||
static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
|
|
||||||
return base->CHANNEL[channel].TIMER;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! @}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Timer Start and Stop
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Starts the timer counting.
|
|
||||||
*
|
|
||||||
* After calling this function, timers load period value, counts down to 0 and
|
|
||||||
* depending on the timer mode it will either load the respective start value again or stop.
|
|
||||||
*
|
|
||||||
* @note User can call the utility macros provided in fsl_common.h to convert to ticks
|
|
||||||
*
|
|
||||||
* @param base Multi-Rate timer peripheral base address
|
|
||||||
* @param channel Timer channel number.
|
|
||||||
* @param count Timer period in units of ticks
|
|
||||||
*/
|
|
||||||
static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
|
|
||||||
/* Write the timer interval value */
|
|
||||||
base->CHANNEL[channel].INTVAL = count;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Stops the timer counting.
|
|
||||||
*
|
|
||||||
* This function stops the timer from counting.
|
|
||||||
*
|
|
||||||
* @param base Multi-Rate timer peripheral base address
|
|
||||||
* @param channel Timer channel number.
|
|
||||||
*/
|
|
||||||
static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
|
|
||||||
/* Stop the timer immediately */
|
|
||||||
base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*! @}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Get & release channel
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Find the available channel.
|
|
||||||
*
|
|
||||||
* This function returns the lowest available channel number.
|
|
||||||
*
|
|
||||||
* @param base Multi-Rate timer peripheral base address
|
|
||||||
*/
|
|
||||||
static inline uint32_t MRT_GetIdleChannel(MRT_Type *base)
|
|
||||||
{
|
|
||||||
return base->IDLE_CH;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if !(defined(FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) && FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE)
|
|
||||||
/*!
|
|
||||||
* @brief Release the channel when the timer is using the multi-task mode.
|
|
||||||
*
|
|
||||||
* In multi-task mode, the INUSE flags allow more control over when MRT channels are released for
|
|
||||||
* further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as
|
|
||||||
* long as it is needed and release it by calling this function. This removes the need to ask for
|
|
||||||
* an available channel for every use.
|
|
||||||
*
|
|
||||||
* @param base Multi-Rate timer peripheral base address
|
|
||||||
* @param channel Timer channel number.
|
|
||||||
*/
|
|
||||||
static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel)
|
|
||||||
{
|
|
||||||
assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
|
|
||||||
|
|
||||||
uint32_t reg = base->CHANNEL[channel].STAT;
|
|
||||||
|
|
||||||
/* Clear flag bits to prevent accidentally clearing anything when writing back */
|
|
||||||
reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK;
|
|
||||||
reg |= MRT_CHANNEL_STAT_INUSE_MASK;
|
|
||||||
|
|
||||||
base->CHANNEL[channel].STAT = reg;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*! @}*/
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*! @}*/
|
|
||||||
|
|
||||||
#endif /* _FSL_MRT_H_ */
|
|
||||||
|
|
@ -1,272 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "fsl_ostimer.h"
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.ostimer"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Typedef for interrupt handler. */
|
|
||||||
typedef void (*ostimer_isr_t)(OSTIMER_Type *base, ostimer_callback_t cb);
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Prototypes
|
|
||||||
******************************************************************************/
|
|
||||||
/*!
|
|
||||||
* @brief Gets the instance from the base address
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address
|
|
||||||
*
|
|
||||||
* @return The OSTIMER instance
|
|
||||||
*/
|
|
||||||
static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base);
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables
|
|
||||||
******************************************************************************/
|
|
||||||
/* Array of OSTIMER handle. */
|
|
||||||
static ostimer_callback_t s_ostimerHandle[FSL_FEATURE_SOC_OSTIMER_COUNT];
|
|
||||||
/* Array of OSTIMER peripheral base address. */
|
|
||||||
static OSTIMER_Type *const s_ostimerBases[] = OSTIMER_BASE_PTRS;
|
|
||||||
/* Array of OSTIMER IRQ number. */
|
|
||||||
static const IRQn_Type s_ostimerIRQ[] = OSTIMER_IRQS;
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Array of OSTIMER clock name. */
|
|
||||||
static const clock_ip_name_t s_ostimerClock[] = OSTIMER_CLOCKS;
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
/* Array of OSTIMER reset name. */
|
|
||||||
static const reset_ip_name_t s_ostimerReset[] = OSTIMER_RSTS;
|
|
||||||
|
|
||||||
/* OSTIMER ISR for transactional APIs. */
|
|
||||||
static ostimer_isr_t s_ostimerIsr;
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/* @brief Function for getting the instance number of OS timer. */
|
|
||||||
static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t instance;
|
|
||||||
|
|
||||||
/* Find the instance index from base address mappings. */
|
|
||||||
for (instance = 0; instance < ARRAY_SIZE(s_ostimerBases); instance++)
|
|
||||||
{
|
|
||||||
if (s_ostimerBases[instance] == base)
|
|
||||||
{
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
assert(instance < ARRAY_SIZE(s_ostimerBases));
|
|
||||||
|
|
||||||
return instance;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* @brief Translate the value from gray-code to decimal. */
|
|
||||||
static uint64_t OSTIMER_GrayToDecimal(uint64_t gray)
|
|
||||||
{
|
|
||||||
uint64_t temp = gray;
|
|
||||||
while (temp)
|
|
||||||
{
|
|
||||||
temp >>= 1U;
|
|
||||||
gray ^= temp;
|
|
||||||
}
|
|
||||||
|
|
||||||
return gray;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* @brief Translate the value from decimal to gray-code. */
|
|
||||||
static uint64_t OSTIMER_DecimalToGray(uint64_t dec)
|
|
||||||
{
|
|
||||||
return (dec ^ (dec >> 1U));
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initializes an OSTIMER by turning it's clock on.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void OSTIMER_Init(OSTIMER_Type *base)
|
|
||||||
{
|
|
||||||
assert(base);
|
|
||||||
|
|
||||||
uint32_t instance = OSTIMER_GetInstance(base);
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Enable the OSTIMER 32k clock in PMC module. */
|
|
||||||
PMC->OSTIMERr |= PMC_OSTIMER_CLOCKENABLE_MASK;
|
|
||||||
PMC->OSTIMERr &= ~PMC_OSTIMER_OSC32KPD_MASK;
|
|
||||||
/* Enable clock for OSTIMER. */
|
|
||||||
CLOCK_EnableClock(s_ostimerClock[instance]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_FEATURE_OSTIMER_HAS_NO_RESET) && FSL_FEATURE_OSTIMER_HAS_NO_RESET)
|
|
||||||
/* Reset the OSTIMER. */
|
|
||||||
RESET_PeripheralReset(s_ostimerReset[instance]);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Deinitializes a OSTIMER instance.
|
|
||||||
*
|
|
||||||
* This function shuts down OSTIMER clock
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address.
|
|
||||||
*/
|
|
||||||
void OSTIMER_Deinit(OSTIMER_Type *base)
|
|
||||||
{
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Enable clock for OSTIMER. */
|
|
||||||
CLOCK_DisableClock(s_ostimerClock[OSTIMER_GetInstance(base)]);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get OSTIMER status Flags.
|
|
||||||
*
|
|
||||||
* This returns the status flag.
|
|
||||||
* Currently, only match interrupt flag can be got.
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address.
|
|
||||||
* @return status register value
|
|
||||||
*/
|
|
||||||
uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base)
|
|
||||||
{
|
|
||||||
return base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Clear Status Interrupt Flags.
|
|
||||||
*
|
|
||||||
* This clears intr status flag.
|
|
||||||
* Currently, only match interrupt flag can be cleared.
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address.
|
|
||||||
* @return none
|
|
||||||
*/
|
|
||||||
void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask)
|
|
||||||
{
|
|
||||||
base->OSEVENT_CTRL |= mask;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set the match raw value for OSTIMER.
|
|
||||||
*
|
|
||||||
* This function will set a match value for OSTIMER with an optional callback. And this callback
|
|
||||||
* will be called while the data in dedicated pair match register is equals to the value of central EVTIMER.
|
|
||||||
* Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue().
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address.
|
|
||||||
* @param count OSTIMER timer match value.(Value is gray-code format)
|
|
||||||
*
|
|
||||||
* @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)).
|
|
||||||
* @return none
|
|
||||||
*/
|
|
||||||
void OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb)
|
|
||||||
{
|
|
||||||
uint64_t tmp = count;
|
|
||||||
uint32_t instance = OSTIMER_GetInstance(base);
|
|
||||||
|
|
||||||
s_ostimerIsr = OSTIMER_HandleIRQ;
|
|
||||||
s_ostimerHandle[instance] = cb;
|
|
||||||
|
|
||||||
/* Set the match value. */
|
|
||||||
base->MATCHN_L = tmp;
|
|
||||||
base->MATCHN_H = tmp >> 32U;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Enable deep sleep IRQ directly for some times the OS timer may run in deep sleep mode.
|
|
||||||
* Please note that while enabling deep sleep IRQ, the NVIC will be also enabled.
|
|
||||||
*/
|
|
||||||
base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK;
|
|
||||||
PMC->OSTIMERr |= PMC_OSTIMER_DPDWAKEUPENABLE_MASK;
|
|
||||||
EnableDeepSleepIRQ(s_ostimerIRQ[instance]);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set the match value for OSTIMER.
|
|
||||||
*
|
|
||||||
* This function will set a match value for OSTIMER with an optional callback. And this callback
|
|
||||||
* will be called while the data in dedicated pair match register is equals to the value of central EVTIMER.
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address.
|
|
||||||
* @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code in
|
|
||||||
* API. )
|
|
||||||
* @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)).
|
|
||||||
* @return none
|
|
||||||
*/
|
|
||||||
void OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb)
|
|
||||||
{
|
|
||||||
uint64_t tmp = OSTIMER_DecimalToGray(count);
|
|
||||||
|
|
||||||
OSTIMER_SetMatchRawValue(base, tmp, cb);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get current timer count value from OSTIMER.
|
|
||||||
*
|
|
||||||
* This function will get a decimal timer count value.
|
|
||||||
* The RAW value of timer count is gray code format, will be translated to decimal data internally.
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address.
|
|
||||||
* @return Value of OSTIMER which will formated to decimal value.
|
|
||||||
*/
|
|
||||||
uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base)
|
|
||||||
{
|
|
||||||
uint64_t tmp = 0U;
|
|
||||||
|
|
||||||
tmp = OSTIMER_GetCurrentTimerRawValue(base);
|
|
||||||
|
|
||||||
return OSTIMER_GrayToDecimal(tmp);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get the capture value from OSTIMER.
|
|
||||||
*
|
|
||||||
* This function will get a capture decimal-value from OSTIMER.
|
|
||||||
* The RAW value of timer capture is gray code format, will be translated to decimal data internally.
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address.
|
|
||||||
* @return Value of capture register, data format is decimal.
|
|
||||||
*/
|
|
||||||
uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base)
|
|
||||||
{
|
|
||||||
uint64_t tmp = 0U;
|
|
||||||
|
|
||||||
tmp = OSTIMER_GetCaptureRawValue(base);
|
|
||||||
|
|
||||||
return OSTIMER_GrayToDecimal(tmp);
|
|
||||||
}
|
|
||||||
|
|
||||||
void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb)
|
|
||||||
{
|
|
||||||
/* Clear the match interrupt flag. */
|
|
||||||
OSTIMER_ClearStatusFlags(base, kOSTIMER_MatchInterruptFlag);
|
|
||||||
|
|
||||||
if (cb)
|
|
||||||
{
|
|
||||||
cb();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(OSTIMER)
|
|
||||||
void OS_EVENT_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
s_ostimerIsr(OSTIMER, s_ostimerHandle[0]);
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,219 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2018 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
#ifndef _FSL_OSTIMER_H_
|
|
||||||
#define _FSL_OSTIMER_H_
|
|
||||||
|
|
||||||
#include "fsl_common.h"
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @addtogroup ostimer
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*! @file*/
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Definitions
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*! @name Driver version */
|
|
||||||
/*@{*/
|
|
||||||
/*! @brief OSTIMER driver version 2.0.0. */
|
|
||||||
#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief OSTIMER status flags.
|
|
||||||
*/
|
|
||||||
enum _ostimer_flags
|
|
||||||
{
|
|
||||||
kOSTIMER_MatchInterruptFlag = (OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK), /*!< Match interrupt flag bit, sets if
|
|
||||||
the match value was reached. */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*! @brief ostimer callback function. */
|
|
||||||
typedef void (*ostimer_callback_t)(void);
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* API
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
extern "C" {
|
|
||||||
#endif /* _cplusplus */
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Initialization and deinitialization
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Initializes an OSTIMER by turning its bus clock on
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void OSTIMER_Init(OSTIMER_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Deinitializes a OSTIMER instance.
|
|
||||||
*
|
|
||||||
* This function shuts down OSTIMER bus clock
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address.
|
|
||||||
*/
|
|
||||||
void OSTIMER_Deinit(OSTIMER_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief OSTIMER software reset.
|
|
||||||
*
|
|
||||||
* This function will use software to trigger an OSTIMER reset.
|
|
||||||
* Please note that, the OS timer reset bit was in PMC->OSTIMERr register.
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address.
|
|
||||||
*/
|
|
||||||
static inline void OSTIMER_SoftwareReset(OSTIMER_Type *base)
|
|
||||||
{
|
|
||||||
PMC->OSTIMERr |= PMC_OSTIMER_SOFTRESET_MASK;
|
|
||||||
PMC->OSTIMERr &= ~PMC_OSTIMER_SOFTRESET_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get OSTIMER status Flags.
|
|
||||||
*
|
|
||||||
* This returns the status flag.
|
|
||||||
* Currently, only match interrupt flag can be got.
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address.
|
|
||||||
* @return status register value
|
|
||||||
*/
|
|
||||||
uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Clear Status Interrupt Flags.
|
|
||||||
*
|
|
||||||
* This clears intrrupt status flag.
|
|
||||||
* Currently, only match interrupt flag can be cleared.
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address.
|
|
||||||
* @return none
|
|
||||||
*/
|
|
||||||
void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set the match raw value for OSTIMER.
|
|
||||||
*
|
|
||||||
* This function will set a match value for OSTIMER with an optional callback. And this callback
|
|
||||||
* will be called while the data in dedicated pair match register is equals to the value of central EVTIMER.
|
|
||||||
* Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue().
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address.
|
|
||||||
* @param count OSTIMER timer match value.(Value is gray-code format)
|
|
||||||
*
|
|
||||||
* @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)).
|
|
||||||
* @return none
|
|
||||||
*/
|
|
||||||
void OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Set the match value for OSTIMER.
|
|
||||||
*
|
|
||||||
* This function will set a match value for OSTIMER with an optional callback. And this callback
|
|
||||||
* will be called while the data in dedicated pair match register is equals to the value of central OS TIMER.
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address.
|
|
||||||
* @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code
|
|
||||||
* internally.)
|
|
||||||
*
|
|
||||||
* @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)).
|
|
||||||
* @return none
|
|
||||||
*/
|
|
||||||
void OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get current timer raw count value from OSTIMER.
|
|
||||||
*
|
|
||||||
* This function will get a gray code type timer count value from OS timer register.
|
|
||||||
* The raw value of timer count is gray code format.
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address.
|
|
||||||
* @return Raw value of OSTIMER, gray code format.
|
|
||||||
*/
|
|
||||||
static inline uint64_t OSTIMER_GetCurrentTimerRawValue(OSTIMER_Type *base)
|
|
||||||
{
|
|
||||||
uint64_t tmp = 0U;
|
|
||||||
|
|
||||||
tmp = base->EVTIMERL;
|
|
||||||
tmp |= (uint64_t)(base->EVTIMERH) << 32U;
|
|
||||||
|
|
||||||
return tmp;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get current timer count value from OSTIMER.
|
|
||||||
*
|
|
||||||
* This function will get a decimal timer count value.
|
|
||||||
* The RAW value of timer count is gray code format, will be translated to decimal data internally.
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address.
|
|
||||||
* @return Value of OSTIMER which will be formated to decimal value.
|
|
||||||
*/
|
|
||||||
uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get the capture value from OSTIMER.
|
|
||||||
*
|
|
||||||
* This function will get a captured gray-code value from OSTIMER.
|
|
||||||
* The Raw value of timer capture is gray code format.
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address.
|
|
||||||
* @return Raw value of capture register, data format is gray code.
|
|
||||||
*/
|
|
||||||
static inline uint64_t OSTIMER_GetCaptureRawValue(OSTIMER_Type *base)
|
|
||||||
{
|
|
||||||
uint64_t tmp = 0U;
|
|
||||||
|
|
||||||
tmp = base->CAPTUREN_L;
|
|
||||||
tmp |= (uint64_t)(base->CAPTUREN_H) << 32U;
|
|
||||||
|
|
||||||
return tmp;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief Get the capture value from OSTIMER.
|
|
||||||
*
|
|
||||||
* This function will get a capture decimal-value from OSTIMER.
|
|
||||||
* The RAW value of timer capture is gray code format, will be translated to decimal data internally.
|
|
||||||
*
|
|
||||||
* @param base OSTIMER peripheral base address.
|
|
||||||
* @return Value of capture register, data format is decimal.
|
|
||||||
*/
|
|
||||||
uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base);
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief OS timer interrupt Service Handler.
|
|
||||||
*
|
|
||||||
* This function handles the interrupt and refers to the callback array in the driver to callback user (as per request
|
|
||||||
* in OSTIMER_SetMatchValue()).
|
|
||||||
* if no user callback is scheduled, the interrupt will simply be cleared.
|
|
||||||
*
|
|
||||||
* @param base OS timer peripheral base address.
|
|
||||||
* @param cb callback scheduled for this instance of OS timer
|
|
||||||
* @return none
|
|
||||||
*/
|
|
||||||
void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb);
|
|
||||||
/*!
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#endif /* _FSL_OSTIMER_H_ */
|
|
||||||
|
|
@ -1,805 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
||||||
* Copyright 2016-2017 NXP
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "fsl_pint.h"
|
|
||||||
|
|
||||||
/* Component ID definition, used by tools. */
|
|
||||||
#ifndef FSL_COMPONENT_ID
|
|
||||||
#define FSL_COMPONENT_ID "platform.drivers.pint"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Variables
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*! @brief Irq number array */
|
|
||||||
static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS;
|
|
||||||
/*! @brief Callback function array for PINT(s). */
|
|
||||||
static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS];
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* Code
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Initialize PINT peripheral.
|
|
||||||
|
|
||||||
* This function initializes the PINT peripheral and enables the clock.
|
|
||||||
*
|
|
||||||
* param base Base address of the PINT peripheral.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void PINT_Init(PINT_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t i;
|
|
||||||
uint32_t pmcfg;
|
|
||||||
|
|
||||||
assert(base);
|
|
||||||
|
|
||||||
pmcfg = 0;
|
|
||||||
for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
|
|
||||||
{
|
|
||||||
s_pintCallback[i] = NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (base == SECPINT)
|
|
||||||
{
|
|
||||||
/* Disable all bit slices for secure pint*/
|
|
||||||
for (i = 0; i < SEC_PINT_PIN_INT_COUNT; i++)
|
|
||||||
{
|
|
||||||
pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U)));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Disable all bit slices for pint*/
|
|
||||||
for (i = 0; i < PINT_PIN_INT_COUNT; i++)
|
|
||||||
{
|
|
||||||
pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U)));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1)
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Enable the clock. */
|
|
||||||
CLOCK_EnableClock(kCLOCK_GpioInt);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
||||||
/* Reset the module. */
|
|
||||||
RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
||||||
|
|
||||||
#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0)
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Enable the clock. */
|
|
||||||
CLOCK_EnableClock(kCLOCK_Gpio0);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
||||||
/* Reset the module. */
|
|
||||||
RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Enable the clock. */
|
|
||||||
CLOCK_EnableClock(kCLOCK_Gpio_Sec);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
||||||
/* Reset the module. */
|
|
||||||
RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
||||||
|
|
||||||
#else
|
|
||||||
/* if need config SECURE PINT device,then enable secure pint interrupt clock */
|
|
||||||
if (base == SECPINT)
|
|
||||||
{
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Enable the clock. */
|
|
||||||
CLOCK_EnableClock(kCLOCK_Gpio_sec_Int);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
||||||
/* Reset the module. */
|
|
||||||
RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Enable the clock. */
|
|
||||||
CLOCK_EnableClock(kCLOCK_Pint);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
||||||
/* Reset the module. */
|
|
||||||
RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
||||||
}
|
|
||||||
#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE && FSL_FEATURE_CLOCK_HAS_NO_GPIOINT_CLOCK_SOURCE*/
|
|
||||||
|
|
||||||
/* Disable all pattern match bit slices */
|
|
||||||
base->PMCFG = pmcfg;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Configure PINT peripheral pin interrupt.
|
|
||||||
|
|
||||||
* This function configures a given pin interrupt.
|
|
||||||
*
|
|
||||||
* param base Base address of the PINT peripheral.
|
|
||||||
* param intr Pin interrupt.
|
|
||||||
* param enable Selects detection logic.
|
|
||||||
* param callback Callback.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback)
|
|
||||||
{
|
|
||||||
assert(base);
|
|
||||||
|
|
||||||
/* Clear Rise and Fall flags first */
|
|
||||||
PINT_PinInterruptClrRiseFlag(base, intr);
|
|
||||||
PINT_PinInterruptClrFallFlag(base, intr);
|
|
||||||
|
|
||||||
/* select level or edge sensitive */
|
|
||||||
base->ISEL = (base->ISEL & ~(1U << intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1U << intr) : 0U);
|
|
||||||
|
|
||||||
/* enable rising or level interrupt */
|
|
||||||
if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE))
|
|
||||||
{
|
|
||||||
base->SIENR = 1U << intr;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
base->CIENR = 1U << intr;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Enable falling or select high level */
|
|
||||||
if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
|
|
||||||
{
|
|
||||||
base->SIENF = 1U << intr;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
base->CIENF = 1U << intr;
|
|
||||||
}
|
|
||||||
/* Handle secure pint interrupt*/
|
|
||||||
if ((base == SECPINT) && (intr == kPINT_PinInt0))
|
|
||||||
{
|
|
||||||
intr = kPINT_SecPinInt0;
|
|
||||||
}
|
|
||||||
else if ((base == SECPINT) && (intr == kPINT_PinInt1))
|
|
||||||
{
|
|
||||||
intr = kPINT_SecPinInt1;
|
|
||||||
}
|
|
||||||
s_pintCallback[intr] = callback;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Get PINT peripheral pin interrupt configuration.
|
|
||||||
|
|
||||||
* This function returns the configuration of a given pin interrupt.
|
|
||||||
*
|
|
||||||
* param base Base address of the PINT peripheral.
|
|
||||||
* param pintr Pin interrupt.
|
|
||||||
* param enable Pointer to store the detection logic.
|
|
||||||
* param callback Callback.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback)
|
|
||||||
{
|
|
||||||
uint32_t mask;
|
|
||||||
bool level;
|
|
||||||
|
|
||||||
assert(base);
|
|
||||||
|
|
||||||
*enable = kPINT_PinIntEnableNone;
|
|
||||||
level = false;
|
|
||||||
|
|
||||||
mask = 1U << pintr;
|
|
||||||
if (base->ISEL & mask)
|
|
||||||
{
|
|
||||||
/* Pin interrupt is level sensitive */
|
|
||||||
level = true;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (base->IENR & mask)
|
|
||||||
{
|
|
||||||
if (level)
|
|
||||||
{
|
|
||||||
/* Level interrupt is enabled */
|
|
||||||
*enable = kPINT_PinIntEnableLowLevel;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Rising edge interrupt */
|
|
||||||
*enable = kPINT_PinIntEnableRiseEdge;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (base->IENF & mask)
|
|
||||||
{
|
|
||||||
if (level)
|
|
||||||
{
|
|
||||||
/* Level interrupt is active high */
|
|
||||||
*enable = kPINT_PinIntEnableHighLevel;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Either falling or both edge */
|
|
||||||
if (*enable == kPINT_PinIntEnableRiseEdge)
|
|
||||||
{
|
|
||||||
/* Rising and faling edge */
|
|
||||||
*enable = kPINT_PinIntEnableBothEdges;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Falling edge */
|
|
||||||
*enable = kPINT_PinIntEnableFallEdge;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
*callback = s_pintCallback[pintr];
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Configure PINT pattern match.
|
|
||||||
|
|
||||||
* This function configures a given pattern match bit slice.
|
|
||||||
*
|
|
||||||
* param base Base address of the PINT peripheral.
|
|
||||||
* param bslice Pattern match bit slice number.
|
|
||||||
* param cfg Pointer to bit slice configuration.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
|
|
||||||
{
|
|
||||||
uint32_t src_shift;
|
|
||||||
uint32_t cfg_shift;
|
|
||||||
uint32_t pmcfg;
|
|
||||||
|
|
||||||
assert(base);
|
|
||||||
|
|
||||||
src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U);
|
|
||||||
cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U);
|
|
||||||
|
|
||||||
/* Input source selection for selected bit slice */
|
|
||||||
base->PMSRC = (base->PMSRC & ~(PININT_BITSLICE_SRC_MASK << src_shift)) | (cfg->bs_src << src_shift);
|
|
||||||
|
|
||||||
/* Bit slice configuration */
|
|
||||||
pmcfg = base->PMCFG;
|
|
||||||
pmcfg = (pmcfg & ~(PININT_BITSLICE_CFG_MASK << cfg_shift)) | (cfg->bs_cfg << cfg_shift);
|
|
||||||
|
|
||||||
/* If end point is true, enable the bits */
|
|
||||||
if (bslice != 7U)
|
|
||||||
{
|
|
||||||
if (cfg->end_point)
|
|
||||||
{
|
|
||||||
pmcfg |= (0x1U << bslice);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
pmcfg &= ~(0x1U << bslice);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
base->PMCFG = pmcfg;
|
|
||||||
/* Handle secure pint pattern match*/
|
|
||||||
if ((base == SECPINT) && (bslice == kPINT_PatternMatchBSlice0))
|
|
||||||
{
|
|
||||||
bslice = kSECPINT_PatternMatchBSlice0;
|
|
||||||
}
|
|
||||||
else if ((base == SECPINT) && (bslice == kPINT_PatternMatchBSlice1))
|
|
||||||
{
|
|
||||||
bslice = kSECPINT_PatternMatchBSlice1;
|
|
||||||
}
|
|
||||||
/* Save callback pointer */
|
|
||||||
s_pintCallback[bslice] = cfg->callback;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Get PINT pattern match configuration.
|
|
||||||
|
|
||||||
* This function returns the configuration of a given pattern match bit slice.
|
|
||||||
*
|
|
||||||
* param base Base address of the PINT peripheral.
|
|
||||||
* param bslice Pattern match bit slice number.
|
|
||||||
* param cfg Pointer to bit slice configuration.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
|
|
||||||
{
|
|
||||||
uint32_t src_shift;
|
|
||||||
uint32_t cfg_shift;
|
|
||||||
|
|
||||||
assert(base);
|
|
||||||
|
|
||||||
src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U);
|
|
||||||
cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U);
|
|
||||||
|
|
||||||
cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (PININT_BITSLICE_SRC_MASK << src_shift)) >> src_shift);
|
|
||||||
cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (PININT_BITSLICE_CFG_MASK << cfg_shift)) >> cfg_shift);
|
|
||||||
|
|
||||||
if (bslice == 7U)
|
|
||||||
{
|
|
||||||
cfg->end_point = true;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
cfg->end_point = (base->PMCFG & (0x1U << bslice)) >> bslice;
|
|
||||||
}
|
|
||||||
cfg->callback = s_pintCallback[bslice];
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Reset pattern match detection logic.
|
|
||||||
|
|
||||||
* This function resets the pattern match detection logic if any of the product term is matching.
|
|
||||||
*
|
|
||||||
* param base Base address of the PINT peripheral.
|
|
||||||
*
|
|
||||||
* retval pmstatus Each bit position indicates the match status of corresponding bit slice.
|
|
||||||
* = 0 Match was detected. = 1 Match was not detected.
|
|
||||||
*/
|
|
||||||
uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t pmctrl;
|
|
||||||
uint32_t pmstatus;
|
|
||||||
uint32_t pmsrc;
|
|
||||||
|
|
||||||
pmctrl = base->PMCTRL;
|
|
||||||
pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT;
|
|
||||||
if (pmstatus)
|
|
||||||
{
|
|
||||||
/* Reset Pattern match engine detection logic */
|
|
||||||
pmsrc = base->PMSRC;
|
|
||||||
base->PMSRC = pmsrc;
|
|
||||||
}
|
|
||||||
return (pmstatus);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Enable callback.
|
|
||||||
|
|
||||||
* This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored
|
|
||||||
* as soon as they are enabled, the callback function is not enabled until this function is called.
|
|
||||||
*
|
|
||||||
* param base Base address of the PINT peripheral.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void PINT_EnableCallback(PINT_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
assert(base);
|
|
||||||
|
|
||||||
PINT_PinInterruptClrStatusAll(base);
|
|
||||||
for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
|
|
||||||
{
|
|
||||||
NVIC_ClearPendingIRQ(s_pintIRQ[i]);
|
|
||||||
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
|
|
||||||
EnableIRQ(s_pintIRQ[i]);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief enable callback by pin index.
|
|
||||||
|
|
||||||
* This function enables callback by pin index instead of enabling all pins.
|
|
||||||
*
|
|
||||||
* param base Base address of the peripheral.
|
|
||||||
* param pinIdx pin index.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx)
|
|
||||||
{
|
|
||||||
assert(base);
|
|
||||||
|
|
||||||
if (base == SECPINT)
|
|
||||||
{
|
|
||||||
pintIdx += 8;
|
|
||||||
}
|
|
||||||
NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]);
|
|
||||||
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx);
|
|
||||||
EnableIRQ(s_pintIRQ[pintIdx]);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief Disable callback.
|
|
||||||
|
|
||||||
* This function disables the interrupt for the selected PINT peripheral. Although the pins are still
|
|
||||||
* being monitored but the callback function is not called.
|
|
||||||
*
|
|
||||||
* param base Base address of the peripheral.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void PINT_DisableCallback(PINT_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
assert(base);
|
|
||||||
|
|
||||||
for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
|
|
||||||
{
|
|
||||||
DisableIRQ(s_pintIRQ[i]);
|
|
||||||
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
|
|
||||||
NVIC_ClearPendingIRQ(s_pintIRQ[i]);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* brief disable callback by pin index.
|
|
||||||
|
|
||||||
* This function disables callback by pin index instead of disabling all pins.
|
|
||||||
*
|
|
||||||
* param base Base address of the peripheral.
|
|
||||||
* param pinIdx pin index.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx)
|
|
||||||
{
|
|
||||||
assert(base);
|
|
||||||
|
|
||||||
if (base == SECPINT)
|
|
||||||
{
|
|
||||||
pintIdx += 8;
|
|
||||||
}
|
|
||||||
DisableIRQ(s_pintIRQ[pintIdx]);
|
|
||||||
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx);
|
|
||||||
NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]);
|
|
||||||
}
|
|
||||||
/*!
|
|
||||||
* brief Deinitialize PINT peripheral.
|
|
||||||
|
|
||||||
* This function disables the PINT clock.
|
|
||||||
*
|
|
||||||
* param base Base address of the PINT peripheral.
|
|
||||||
*
|
|
||||||
* retval None.
|
|
||||||
*/
|
|
||||||
void PINT_Deinit(PINT_Type *base)
|
|
||||||
{
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
assert(base);
|
|
||||||
|
|
||||||
/* Cleanup */
|
|
||||||
PINT_DisableCallback(base);
|
|
||||||
for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
|
|
||||||
{
|
|
||||||
s_pintCallback[i] = NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1)
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
||||||
/* Reset the module. */
|
|
||||||
RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Disable the clock. */
|
|
||||||
CLOCK_DisableClock(kCLOCK_GpioInt);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0)
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
||||||
/* Reset the module. */
|
|
||||||
RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Disable the clock. */
|
|
||||||
CLOCK_DisableClock(kCLOCK_Gpio0);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
||||||
/* Reset the module. */
|
|
||||||
RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Enable the clock. */
|
|
||||||
CLOCK_DisableClock(kCLOCK_Gpio_Sec);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
|
|
||||||
#else
|
|
||||||
if (base == SECPINT)
|
|
||||||
{
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
||||||
/* Reset the module. */
|
|
||||||
RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Disable the clock. */
|
|
||||||
CLOCK_DisableClock(kCLOCK_Gpio_sec_Int);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
|
|
||||||
/* Reset the module. */
|
|
||||||
RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
|
|
||||||
|
|
||||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
||||||
/* Disable the clock. */
|
|
||||||
CLOCK_DisableClock(kCLOCK_Pint);
|
|
||||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
||||||
}
|
|
||||||
#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */
|
|
||||||
}
|
|
||||||
|
|
||||||
/* IRQ handler functions overloading weak symbols in the startup */
|
|
||||||
void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
uint32_t pmstatus = 0;
|
|
||||||
|
|
||||||
/* Reset pattern match detection */
|
|
||||||
pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT);
|
|
||||||
/* Call user function */
|
|
||||||
if (s_pintCallback[kPINT_SecPinInt0] != NULL)
|
|
||||||
{
|
|
||||||
s_pintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus);
|
|
||||||
}
|
|
||||||
if ((SECPINT->ISEL & 0x1U) == 0x0U)
|
|
||||||
{
|
|
||||||
/* Edge sensitive: clear Pin interrupt after callback */
|
|
||||||
PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0);
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
|
|
||||||
/* IRQ handler functions overloading weak symbols in the startup */
|
|
||||||
void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
uint32_t pmstatus;
|
|
||||||
|
|
||||||
/* Reset pattern match detection */
|
|
||||||
pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT);
|
|
||||||
/* Call user function */
|
|
||||||
if (s_pintCallback[kPINT_SecPinInt1] != NULL)
|
|
||||||
{
|
|
||||||
s_pintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus);
|
|
||||||
}
|
|
||||||
if ((SECPINT->ISEL & 0x1U) == 0x0U)
|
|
||||||
{
|
|
||||||
/* Edge sensitive: clear Pin interrupt after callback */
|
|
||||||
PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1);
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
/* IRQ handler functions overloading weak symbols in the startup */
|
|
||||||
void PIN_INT0_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
uint32_t pmstatus;
|
|
||||||
|
|
||||||
/* Reset pattern match detection */
|
|
||||||
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
|
||||||
/* Call user function */
|
|
||||||
if (s_pintCallback[kPINT_PinInt0] != NULL)
|
|
||||||
{
|
|
||||||
s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus);
|
|
||||||
}
|
|
||||||
if ((PINT->ISEL & 0x1U) == 0x0U)
|
|
||||||
{
|
|
||||||
/* Edge sensitive: clear Pin interrupt after callback */
|
|
||||||
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0);
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
|
|
||||||
void PIN_INT1_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
uint32_t pmstatus;
|
|
||||||
|
|
||||||
/* Reset pattern match detection */
|
|
||||||
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
|
||||||
/* Call user function */
|
|
||||||
if (s_pintCallback[kPINT_PinInt1] != NULL)
|
|
||||||
{
|
|
||||||
s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus);
|
|
||||||
}
|
|
||||||
if ((PINT->ISEL & 0x2U) == 0x0U)
|
|
||||||
{
|
|
||||||
/* Edge sensitive: clear Pin interrupt after callback */
|
|
||||||
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1);
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
|
|
||||||
void PIN_INT2_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
uint32_t pmstatus;
|
|
||||||
|
|
||||||
/* Reset pattern match detection */
|
|
||||||
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
|
||||||
/* Call user function */
|
|
||||||
if (s_pintCallback[kPINT_PinInt2] != NULL)
|
|
||||||
{
|
|
||||||
s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus);
|
|
||||||
}
|
|
||||||
if ((PINT->ISEL & 0x4U) == 0x0U)
|
|
||||||
{
|
|
||||||
/* Edge sensitive: clear Pin interrupt after callback */
|
|
||||||
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2);
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
|
|
||||||
void PIN_INT3_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
uint32_t pmstatus;
|
|
||||||
|
|
||||||
/* Reset pattern match detection */
|
|
||||||
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
|
||||||
/* Call user function */
|
|
||||||
if (s_pintCallback[kPINT_PinInt3] != NULL)
|
|
||||||
{
|
|
||||||
s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus);
|
|
||||||
}
|
|
||||||
if ((PINT->ISEL & 0x8U) == 0x0U)
|
|
||||||
{
|
|
||||||
/* Edge sensitive: clear Pin interrupt after callback */
|
|
||||||
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3);
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
|
|
||||||
void PIN_INT4_DriverIRQHandler(void)
|
|
||||||
{
|
|
||||||
uint32_t pmstatus;
|
|
||||||
|
|
||||||
/* Reset pattern match detection */
|
|
||||||
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
|
||||||
/* Call user function */
|
|
||||||
if (s_pintCallback[kPINT_PinInt4] != NULL)
|
|
||||||
{
|
|
||||||
s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus);
|
|
||||||
}
|
|
||||||
if ((PINT->ISEL & 0x10U) == 0x0U)
|
|
||||||
{
|
|
||||||
/* Edge sensitive: clear Pin interrupt after callback */
|
|
||||||
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4);
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
|
|
||||||
#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER
|
|
||||||
void PIN_INT5_DAC1_IRQHandler(void)
|
|
||||||
#else
|
|
||||||
void PIN_INT5_DriverIRQHandler(void)
|
|
||||||
#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */
|
|
||||||
{
|
|
||||||
uint32_t pmstatus;
|
|
||||||
|
|
||||||
/* Reset pattern match detection */
|
|
||||||
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
|
||||||
/* Call user function */
|
|
||||||
if (s_pintCallback[kPINT_PinInt5] != NULL)
|
|
||||||
{
|
|
||||||
s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus);
|
|
||||||
}
|
|
||||||
if ((PINT->ISEL & 0x20U) == 0x0U)
|
|
||||||
{
|
|
||||||
/* Edge sensitive: clear Pin interrupt after callback */
|
|
||||||
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5);
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
|
|
||||||
#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER
|
|
||||||
void PIN_INT6_USART3_IRQHandler(void)
|
|
||||||
#else
|
|
||||||
void PIN_INT6_DriverIRQHandler(void)
|
|
||||||
#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */
|
|
||||||
{
|
|
||||||
uint32_t pmstatus;
|
|
||||||
|
|
||||||
/* Reset pattern match detection */
|
|
||||||
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
|
||||||
/* Call user function */
|
|
||||||
if (s_pintCallback[kPINT_PinInt6] != NULL)
|
|
||||||
{
|
|
||||||
s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus);
|
|
||||||
}
|
|
||||||
if ((PINT->ISEL & 0x40U) == 0x0U)
|
|
||||||
{
|
|
||||||
/* Edge sensitive: clear Pin interrupt after callback */
|
|
||||||
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6);
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
|
|
||||||
#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER
|
|
||||||
void PIN_INT7_USART4_IRQHandler(void)
|
|
||||||
#else
|
|
||||||
void PIN_INT7_DriverIRQHandler(void)
|
|
||||||
#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */
|
|
||||||
{
|
|
||||||
uint32_t pmstatus;
|
|
||||||
|
|
||||||
/* Reset pattern match detection */
|
|
||||||
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
|
||||||
/* Call user function */
|
|
||||||
if (s_pintCallback[kPINT_PinInt7] != NULL)
|
|
||||||
{
|
|
||||||
s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus);
|
|
||||||
}
|
|
||||||
if ((PINT->ISEL & 0x80U) == 0x0U)
|
|
||||||
{
|
|
||||||
/* Edge sensitive: clear Pin interrupt after callback */
|
|
||||||
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7);
|
|
||||||
}
|
|
||||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
||||||
exception return operation might vector to incorrect interrupt */
|
|
||||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
||||||
__DSB();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue