From 07b6db2f0da57de5e88d716e36fb65cff6a3ef85 Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Wed, 18 Nov 2020 14:51:49 +0000 Subject: [PATCH] TARGET_NXP: Remove support for LPC55S69 Mbed OS 6 dropped support for all LPC55S69 targets. This commit removes all source files for those targets. --- .../TARGET_HANI_IOT/PeripheralNames.h | 140 - .../TARGET_HANI_IOT/PeripheralPinMaps.h | 146 - .../TARGET_HANI_IOT/PeripheralPins.c | 19 - .../TARGET_HANI_IOT/PinNames.h | 211 - .../TARGET_HANI_IOT/clock_config.c | 228 - .../TARGET_HANI_IOT/clock_config.h | 121 - .../TARGET_LPC55S69/TARGET_HANI_IOT/device.h | 37 - .../TARGET_HANI_IOT/mbed_overrides.c | 68 - .../TARGET_LPCXpresso/PeripheralNames.h | 139 - .../TARGET_LPCXpresso/PeripheralPinMaps.h | 146 - .../TARGET_LPCXpresso/PeripheralPins.c | 40 - .../TARGET_LPCXpresso/PinNames.h | 209 - .../TARGET_LPCXpresso/clock_config.c | 228 - .../TARGET_LPCXpresso/clock_config.h | 121 - .../TARGET_LPCXpresso/device.h | 39 - .../TARGET_LPCXpresso/mbed_overrides.c | 68 - .../LPC55S69_cm33_core0_flash.sct | 148 - .../startup_LPC55S69_cm33_core0.S | 727 - .../LPC55S69_cm33_core0_flash.ld | 284 - .../startup_LPC55S69_cm33_core0.S | 874 - .../LPC55S69_cm33_core0_flash.icf | 156 - .../startup_LPC55S69_cm33_core0.S | 622 - .../TARGET_M33_NS/device/cmsis_nvic.h | 46 - .../TARGET_M33_NS/device/cmsis_nvic_virtual.h | 61 - .../LICENSE-permissive-binary-license-1.0.txt | 49 - .../TARGET_M33_NS/prebuilt/README.md | 39 - .../TARGET_M33_NS/prebuilt/cmse_lib.o | Bin 768 -> 0 bytes .../prebuilt/crypto_access_control.bin | Bin 163520 -> 0 bytes .../TARGET_M33_NS/prebuilt/spm_client.bin | Bin 163520 -> 0 bytes .../TARGET_M33_NS/prebuilt/spm_server.bin | Bin 163520 -> 0 bytes .../TARGET_M33_NS/prebuilt/spm_smoke.bin | Bin 163520 -> 0 bytes .../TARGET_M33_NS/prebuilt/tfm.bin | Bin 163520 -> 0 bytes .../LPC55S69_cm33_core0_flash.sct | 277 - .../startup_LPC55S69_cm33_core0.S | 787 - .../TARGET_LPC55S69/TARGET_M33_S/spm_hal.c | 74 - .../TARGET_LPC55S69/TARGET_M33_S/target_cfg.c | 471 - .../TARGET_LPC55S69/TARGET_M33_S/target_cfg.h | 66 - .../TARGET_M33_S/tfm_peripherals_def.h | 17 - .../TARGET_LPC55S69/TARGET_M33_S/trng_api.c | 48 - .../device/LPC55S69_cm33_core0.h | 24755 --------------- .../device/LPC55S69_cm33_core0_features.h | 292 - .../device/LPC55S69_cm33_core1.h | 24757 ---------------- .../device/LPC55S69_cm33_core1_features.h | 292 - .../device/TOOLCHAIN_ARMC6/lib_power.ar | Bin 8468 -> 0 bytes .../device/TOOLCHAIN_GCC_ARM/libpower.a | Bin 51052 -> 0 bytes .../device/TOOLCHAIN_IAR/lib_power.a | Bin 13646 -> 0 bytes .../TARGET_LPC55S69/device/cmsis.h | 31 - .../device/fsl_device_registers.h | 44 - .../TARGET_LPC55S69/device/platform_regs.h | 44 - .../device/platform_retarget.h | 76 - .../device/system_LPC55S69_cm33_core0.c | 369 - .../device/system_LPC55S69_cm33_core0.h | 110 - .../device/system_LPC55S69_cm33_core1.h | 110 - .../TARGET_LPC55S69/drivers/fsl_anactrl.c | 320 - .../TARGET_LPC55S69/drivers/fsl_anactrl.h | 458 - .../TARGET_LPC55S69/drivers/fsl_casper.c | 2662 -- .../TARGET_LPC55S69/drivers/fsl_casper.h | 301 - .../TARGET_LPC55S69/drivers/fsl_clock.c | 1988 -- .../TARGET_LPC55S69/drivers/fsl_clock.h | 1288 - .../TARGET_LPC55S69/drivers/fsl_cmp.c | 55 - .../TARGET_LPC55S69/drivers/fsl_cmp.h | 293 - .../TARGET_LPC55S69/drivers/fsl_common.c | 147 - .../TARGET_LPC55S69/drivers/fsl_common.h | 585 - .../TARGET_LPC55S69/drivers/fsl_crc.c | 172 - .../TARGET_LPC55S69/drivers/fsl_crc.h | 181 - .../TARGET_LPC55S69/drivers/fsl_ctimer.c | 544 - .../TARGET_LPC55S69/drivers/fsl_ctimer.h | 488 - .../TARGET_LPC55S69/drivers/fsl_dma.c | 734 - .../TARGET_LPC55S69/drivers/fsl_dma.h | 649 - .../TARGET_LPC55S69/drivers/fsl_flexcomm.c | 335 - .../TARGET_LPC55S69/drivers/fsl_flexcomm.h | 53 - .../TARGET_LPC55S69/drivers/fsl_gint.c | 392 - .../TARGET_LPC55S69/drivers/fsl_gint.h | 222 - .../TARGET_LPC55S69/drivers/fsl_gpio.c | 112 - .../TARGET_LPC55S69/drivers/fsl_gpio.h | 241 - .../TARGET_LPC55S69/drivers/fsl_hashcrypt.c | 1307 - .../TARGET_LPC55S69/drivers/fsl_hashcrypt.h | 420 - .../TARGET_LPC55S69/drivers/fsl_i2c.c | 1856 -- .../TARGET_LPC55S69/drivers/fsl_i2c.h | 1042 - .../TARGET_LPC55S69/drivers/fsl_i2c_dma.c | 588 - .../TARGET_LPC55S69/drivers/fsl_i2c_dma.h | 120 - .../TARGET_LPC55S69/drivers/fsl_i2s.c | 1053 - .../TARGET_LPC55S69/drivers/fsl_i2s.h | 468 - .../TARGET_LPC55S69/drivers/fsl_i2s_dma.c | 665 - .../TARGET_LPC55S69/drivers/fsl_i2s_dma.h | 161 - .../TARGET_LPC55S69/drivers/fsl_iap.c | 289 - .../TARGET_LPC55S69/drivers/fsl_iap.h | 516 - .../TARGET_LPC55S69/drivers/fsl_iap_ffr.h | 253 - .../TARGET_LPC55S69/drivers/fsl_inputmux.c | 121 - .../TARGET_LPC55S69/drivers/fsl_inputmux.h | 97 - .../drivers/fsl_inputmux_connections.h | 410 - .../TARGET_LPC55S69/drivers/fsl_iocon.h | 288 - .../TARGET_LPC55S69/drivers/fsl_lpadc.c | 611 - .../TARGET_LPC55S69/drivers/fsl_lpadc.h | 844 - .../TARGET_LPC55S69/drivers/fsl_mailbox.h | 214 - .../TARGET_LPC55S69/drivers/fsl_mrt.c | 150 - .../TARGET_LPC55S69/drivers/fsl_mrt.h | 365 - .../TARGET_LPC55S69/drivers/fsl_ostimer.c | 272 - .../TARGET_LPC55S69/drivers/fsl_ostimer.h | 219 - .../TARGET_LPC55S69/drivers/fsl_pint.c | 805 - .../TARGET_LPC55S69/drivers/fsl_pint.h | 585 - .../TARGET_LPC55S69/drivers/fsl_plu.c | 97 - .../TARGET_LPC55S69/drivers/fsl_plu.h | 266 - .../TARGET_LPC55S69/drivers/fsl_power.c | 19 - .../TARGET_LPC55S69/drivers/fsl_power.h | 724 - .../TARGET_LPC55S69/drivers/fsl_powerquad.h | 2764 -- .../drivers/fsl_powerquad_basic.c | 126 - .../drivers/fsl_powerquad_data.c | 584 - .../drivers/fsl_powerquad_data.h | 49 - .../drivers/fsl_powerquad_filter.c | 373 - .../drivers/fsl_powerquad_math.c | 887 - .../drivers/fsl_powerquad_matrix.c | 134 - .../drivers/fsl_powerquad_transform.c | 103 - .../TARGET_LPC55S69/drivers/fsl_prince.c | 454 - .../TARGET_LPC55S69/drivers/fsl_prince.h | 238 - .../TARGET_LPC55S69/drivers/fsl_puf.c | 815 - .../TARGET_LPC55S69/drivers/fsl_puf.h | 231 - .../TARGET_LPC55S69/drivers/fsl_reset.c | 99 - .../TARGET_LPC55S69/drivers/fsl_reset.h | 281 - .../TARGET_LPC55S69/drivers/fsl_rng.c | 96 - .../TARGET_LPC55S69/drivers/fsl_rng.h | 95 - .../TARGET_LPC55S69/drivers/fsl_rtc.c | 321 - .../TARGET_LPC55S69/drivers/fsl_rtc.h | 318 - .../TARGET_LPC55S69/drivers/fsl_sctimer.c | 702 - .../TARGET_LPC55S69/drivers/fsl_sctimer.h | 808 - .../TARGET_LPC55S69/drivers/fsl_sdif.c | 1536 - .../TARGET_LPC55S69/drivers/fsl_sdif.h | 995 - .../TARGET_LPC55S69/drivers/fsl_spi.c | 1035 - .../TARGET_LPC55S69/drivers/fsl_spi.h | 725 - .../TARGET_LPC55S69/drivers/fsl_spi_dma.c | 554 - .../TARGET_LPC55S69/drivers/fsl_spi_dma.h | 208 - .../TARGET_LPC55S69/drivers/fsl_sysctl.c | 206 - .../TARGET_LPC55S69/drivers/fsl_sysctl.h | 186 - .../TARGET_LPC55S69/drivers/fsl_usart.c | 918 - .../TARGET_LPC55S69/drivers/fsl_usart.h | 660 - .../TARGET_LPC55S69/drivers/fsl_usart_dma.c | 307 - .../TARGET_LPC55S69/drivers/fsl_usart_dma.h | 161 - .../TARGET_LPC55S69/drivers/fsl_utick.c | 220 - .../TARGET_LPC55S69/drivers/fsl_utick.h | 118 - .../TARGET_LPC55S69/drivers/fsl_wwdt.c | 248 - .../TARGET_LPC55S69/drivers/fsl_wwdt.h | 263 - .../TARGET_LPC55S69/flash_api.c | 209 - .../TARGET_LPC55S69/partition/flash_layout.h | 118 - .../TARGET_LPC55S69/partition/region_defs.h | 127 - 144 files changed, 102903 deletions(-) delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PeripheralNames.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PeripheralPinMaps.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PeripheralPins.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PinNames.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/clock_config.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/clock_config.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/device.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/mbed_overrides.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralNames.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralPinMaps.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralPins.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PinNames.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/clock_config.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/clock_config.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/device.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/mbed_overrides.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_ARMC6/LPC55S69_cm33_core0_flash.sct delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_ARMC6/startup_LPC55S69_cm33_core0.S delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_GCC_ARM/LPC55S69_cm33_core0_flash.ld delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_GCC_ARM/startup_LPC55S69_cm33_core0.S delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_IAR/LPC55S69_cm33_core0_flash.icf delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_IAR/startup_LPC55S69_cm33_core0.S delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/cmsis_nvic.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/cmsis_nvic_virtual.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/LICENSE-permissive-binary-license-1.0.txt delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/README.md delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/cmse_lib.o delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/crypto_access_control.bin delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/spm_client.bin delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/spm_server.bin delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/spm_smoke.bin delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/tfm.bin delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/device/TOOLCHAIN_ARMC6/LPC55S69_cm33_core0_flash.sct delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/device/TOOLCHAIN_ARMC6/startup_LPC55S69_cm33_core0.S delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/spm_hal.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/target_cfg.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/target_cfg.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/tfm_peripherals_def.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/trng_api.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core0.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core0_features.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core1.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core1_features.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/TOOLCHAIN_ARMC6/lib_power.ar delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/TOOLCHAIN_GCC_ARM/libpower.a delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/TOOLCHAIN_IAR/lib_power.a delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/cmsis.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/fsl_device_registers.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/platform_regs.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/platform_retarget.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/system_LPC55S69_cm33_core0.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/system_LPC55S69_cm33_core0.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/system_LPC55S69_cm33_core1.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_anactrl.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_anactrl.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_casper.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_casper.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_clock.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_clock.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_cmp.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_cmp.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_common.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_common.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_crc.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_crc.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_ctimer.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_ctimer.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_dma.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_dma.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_flexcomm.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_flexcomm.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_gint.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_gint.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_gpio.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_gpio.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_hashcrypt.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_hashcrypt.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2c.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2c.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2c_dma.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2c_dma.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2s.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2s.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2s_dma.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2s_dma.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_iap.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_iap.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_iap_ffr.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_inputmux.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_inputmux.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_inputmux_connections.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_iocon.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_lpadc.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_lpadc.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_mailbox.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_mrt.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_mrt.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_ostimer.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_ostimer.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_pint.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_pint.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_plu.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_plu.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_power.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_power.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad.h delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_basic.c delete mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_data.c delete mode 100644 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a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PeripheralNames.h +++ /dev/null @@ -1,140 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2020 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" -#include "PortNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - OSC32KCLK = 0, -} RTCName; - -typedef enum { - UART_0 = Flexcomm0, - UART_1 = Flexcomm2, - UART_2 = Flexcomm6 -} UARTName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_0 - -typedef enum { - I2C_0 = Flexcomm1, - I2C_1 = Flexcomm4 -} I2CName; - -#define TPM_SHIFT 8 -typedef enum { - PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 - PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 - PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 - PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 - PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 - PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 - PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 - PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 - PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 - PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 - PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2 - PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3 - PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4 - PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5 - PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6 - PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7 - PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 - PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 - PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2 - PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3 - PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4 - PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5 - PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6 - PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7 - PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 - PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 - PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 - PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 - PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 - PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 - PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 - PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 -} PWMName; - -#define ADC_INSTANCE_SHIFT 8 -#define ADC_B_CHANNEL_SHIFT 5 - -typedef enum { - ADC0_SE0 = 0, - ADC0_SE1 = 1, - ADC0_SE2 = 2, - ADC0_SE3 = 3, - ADC0_SE4 = 4, - ADC0_SE5 = 5, - ADC0_SE6 = 6, - ADC0_SE7 = 7, - ADC0_SE8 = 8, - ADC0_SE9 = 9, - ADC0_SE10 = 10, - ADC0_SE11 = 11, - ADC0_SE12 = 12, - ADC0_SE13 = 13, - ADC0_SE14 = 14, - ADC0_SE15 = 15, - ADC0_SE0_B = (1 << ADC_B_CHANNEL_SHIFT) | 0, - ADC0_SE1_B = (1 << ADC_B_CHANNEL_SHIFT) | 1, - ADC0_SE2_B = (1 << ADC_B_CHANNEL_SHIFT) | 2, - ADC0_SE3_B = (1 << ADC_B_CHANNEL_SHIFT) | 3, - ADC0_SE4_B = (1 << ADC_B_CHANNEL_SHIFT) | 4, - ADC0_SE5_B = (1 << ADC_B_CHANNEL_SHIFT) | 5, - ADC0_SE6_B = (1 << ADC_B_CHANNEL_SHIFT) | 6, - ADC0_SE7_B = (1 << ADC_B_CHANNEL_SHIFT) | 7, - ADC0_SE8_B = (1 << ADC_B_CHANNEL_SHIFT) | 8, - ADC0_SE9_B = (1 << ADC_B_CHANNEL_SHIFT) | 9, - ADC0_SE10_B = (1 << ADC_B_CHANNEL_SHIFT) | 10, - ADC0_SE11_B = (1 << ADC_B_CHANNEL_SHIFT) | 11, - ADC0_SE12_B = (1 << ADC_B_CHANNEL_SHIFT) | 12, - ADC0_SE13_B = (1 << ADC_B_CHANNEL_SHIFT) | 13, - ADC0_SE14_B = (1 << ADC_B_CHANNEL_SHIFT) | 14, - ADC0_SE15_B = (1 << ADC_B_CHANNEL_SHIFT) | 15 -} ADCName; - -typedef enum { - CAN_0 = 0, - CAN_1 = 1 -} CANName; - -#define SSELNUM_SHIFT 16 -typedef enum { - SPI_0 = Flexcomm3, - SPI_1 = Flexcomm5, - SPI_2 = Flexcomm8 -} SPIName; - -/* Flexcomm 8 on LPC55S69 is dedicated for HS-SPI and hence uses different naming convention */ -#define kFRO12M_to_FLEXCOMM8 (kFRO12M_to_HSLSPI) -#define kFC8_RST_SHIFT_RSTn (kHSLSPI_RST_SHIFT_RSTn) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PeripheralPinMaps.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PeripheralPinMaps.h deleted file mode 100644 index ac143541f5..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PeripheralPinMaps.h +++ /dev/null @@ -1,146 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2020 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PERIPHERALPINMAPS_H -#define MBED_PERIPHERALPINMAPS_H - -#include - -/************RTC***************/ -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_RTC[] = { - {NC, OSC32KCLK, 0}, -}; - -/************ADC***************/ -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_ADC[] = { - {P0_23, ADC0_SE0, 0}, - {P0_10, ADC0_SE1, 0}, - {P0_31, ADC0_SE3, 0}, - {P1_8, ADC0_SE4, 0}, - {P2_0, ADC0_SE5, 0}, - {P2_13, ADC0_SE6, 0}, - {P2_11, ADC0_SE7, 0}, - {NC , NC , 0} -}; - -/************CAN***************/ -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_CAN_TD[] = { - {NC , NC , 0} -}; - -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_CAN_RD[] = { - {NC , NC , 0} -}; - - -/************DAC***************/ -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_DAC[] = { - {NC , NC , 0} -}; - -/************I2C***************/ -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_I2C_SDA[] = { - {P0_13, I2C_0, 1}, - {P1_21, I2C_1, 5}, - {NC , NC , 0} -}; - -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_I2C_SCL[] = { - {P0_14, I2C_0, 1}, - {P1_20, I2C_1, 5}, - {NC , NC , 0} -}; - -/************UART***************/ -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_TX[] = { - {P0_30, UART_0, 1}, - {P1_6, UART_0, 1}, - {P0_27, UART_1, 1}, - {NC , NC , 0} -}; - -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_RX[] = { - {P0_29, UART_0, 1}, - {P1_5, UART_0, 1}, - {P1_24, UART_1, 1}, - {NC , NC , 0} -}; - -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_CTS[] = { - {P1_8, UART_0, 1}, - {P1_26, UART_1, 1}, - {NC , NC , 0} -}; - -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_RTS[] = { - {P1_7, UART_0, 1}, - {P1_27, UART_1, 1}, - {NC , NC , 0} -}; - -/************SPI***************/ -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_SCLK[] = { - {P0_6, SPI_0, 1}, - {P0_21, SPI_1, 7}, - {P1_2, SPI_2, 6}, - {NC , NC , 0} -}; - -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_MOSI[] = { - {P0_3, SPI_0, 1}, - {P0_20, SPI_1, 7}, - {P0_26, SPI_2, 9}, - {NC , NC , 0} -}; - -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_MISO[] = { - {P0_2, SPI_0, 1}, - {P0_19, SPI_1, 7}, - {P1_3, SPI_2, 6}, - {NC , NC , 0} -}; - -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_SSEL[] = { - {P0_4, SPI_0, 8}, - {P1_20, SPI_1, ((1 << SSELNUM_SHIFT) | 1)}, - {P1_1, SPI_2, ((1 << SSELNUM_SHIFT) | 5)}, - {NC , NC , 0} -}; - -/************PWM***************/ -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_PWM[] = { - {NC , NC , 0} -}; - - -#define PINMAP_ANALOGIN PinMap_ADC -#define PINMAP_ANALOGOUT PinMap_DAC -#define PINMAP_I2C_SDA PinMap_I2C_SDA -#define PINMAP_I2C_SCL PinMap_I2C_SCL -#define PINMAP_UART_TX PinMap_UART_TX -#define PINMAP_UART_RX PinMap_UART_RX -#define PINMAP_UART_CTS PinMap_UART_CTS -#define PINMAP_UART_RTS PinMap_UART_RTS -#define PINMAP_SPI_SCLK PinMap_SPI_SCLK -#define PINMAP_SPI_MOSI PinMap_SPI_MOSI -#define PINMAP_SPI_MISO PinMap_SPI_MISO -#define PINMAP_SPI_SSEL PinMap_SPI_SSEL -#define PINMAP_PWM PinMap_PWM -#define PINMAP_CAN_TD PinMap_CAN_TD -#define PINMAP_CAN_RD PinMap_CAN_RD - -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PeripheralPins.c deleted file mode 100644 index b0e201f10c..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PeripheralPins.c +++ /dev/null @@ -1,19 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2020 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" -#include "PeripheralPinMaps.h" diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PinNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PinNames.h deleted file mode 100644 index a89db9eeed..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PinNames.h +++ /dev/null @@ -1,211 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2020 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* If this macro is defined, then constexpr utility functions for pin-map seach can be used. */ -#define STATIC_PINMAP_READY 0 - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 5 - -typedef enum { - P0_0 = (0 << PORT_SHIFT | 0), - P0_1 = (0 << PORT_SHIFT | 1), - P0_2 = (0 << PORT_SHIFT | 2), - P0_3 = (0 << PORT_SHIFT | 3), - P0_4 = (0 << PORT_SHIFT | 4), - P0_5 = (0 << PORT_SHIFT | 5), - P0_6 = (0 << PORT_SHIFT | 6), - P0_7 = (0 << PORT_SHIFT | 7), - P0_8 = (0 << PORT_SHIFT | 8), - P0_9 = (0 << PORT_SHIFT | 9), - P0_10 = (0 << PORT_SHIFT | 10), - P0_11 = (0 << PORT_SHIFT | 11), - P0_12 = (0 << PORT_SHIFT | 12), - P0_13 = (0 << PORT_SHIFT | 13), - P0_14 = (0 << PORT_SHIFT | 14), - P0_15 = (0 << PORT_SHIFT | 15), - P0_16 = (0 << PORT_SHIFT | 16), - P0_17 = (0 << PORT_SHIFT | 17), - P0_18 = (0 << PORT_SHIFT | 18), - P0_19 = (0 << PORT_SHIFT | 19), - P0_20 = (0 << PORT_SHIFT | 20), - P0_21 = (0 << PORT_SHIFT | 21), - P0_22 = (0 << PORT_SHIFT | 22), - P0_23 = (0 << PORT_SHIFT | 23), - P0_24 = (0 << PORT_SHIFT | 24), - P0_25 = (0 << PORT_SHIFT | 25), - P0_26 = (0 << PORT_SHIFT | 26), - P0_27 = (0 << PORT_SHIFT | 27), - P0_28 = (0 << PORT_SHIFT | 28), - P0_29 = (0 << PORT_SHIFT | 29), - P0_30 = (0 << PORT_SHIFT | 30), - P0_31 = (0 << PORT_SHIFT | 31), - - P1_0 = (1 << PORT_SHIFT | 0), - P1_1 = (1 << PORT_SHIFT | 1), - P1_2 = (1 << PORT_SHIFT | 2), - P1_3 = (1 << PORT_SHIFT | 3), - P1_4 = (1 << PORT_SHIFT | 4), - P1_5 = (1 << PORT_SHIFT | 5), - P1_6 = (1 << PORT_SHIFT | 6), - P1_7 = (1 << PORT_SHIFT | 7), - P1_8 = (1 << PORT_SHIFT | 8), - P1_9 = (1 << PORT_SHIFT | 9), - P1_10 = (1 << PORT_SHIFT | 10), - P1_11 = (1 << PORT_SHIFT | 11), - P1_12 = (1 << PORT_SHIFT | 12), - P1_13 = (1 << PORT_SHIFT | 13), - P1_14 = (1 << PORT_SHIFT | 14), - P1_15 = (1 << PORT_SHIFT | 15), - P1_16 = (1 << PORT_SHIFT | 16), - P1_17 = (1 << PORT_SHIFT | 17), - P1_18 = (1 << PORT_SHIFT | 18), - P1_19 = (1 << PORT_SHIFT | 19), - P1_20 = (1 << PORT_SHIFT | 20), - P1_21 = (1 << PORT_SHIFT | 21), - P1_22 = (1 << PORT_SHIFT | 22), - P1_23 = (1 << PORT_SHIFT | 23), - P1_24 = (1 << PORT_SHIFT | 24), - P1_25 = (1 << PORT_SHIFT | 25), - P1_26 = (1 << PORT_SHIFT | 26), - P1_27 = (1 << PORT_SHIFT | 27), - P1_28 = (1 << PORT_SHIFT | 28), - P1_29 = (1 << PORT_SHIFT | 29), - P1_30 = (1 << PORT_SHIFT | 30), - P1_31 = (1 << PORT_SHIFT | 31), - - P2_0 = (2 << PORT_SHIFT | 0), - P2_1 = (2 << PORT_SHIFT | 1), - P2_2 = (2 << PORT_SHIFT | 2), - P2_3 = (2 << PORT_SHIFT | 3), - P2_4 = (2 << PORT_SHIFT | 4), - P2_5 = (2 << PORT_SHIFT | 5), - P2_6 = (2 << PORT_SHIFT | 6), - P2_7 = (2 << PORT_SHIFT | 7), - P2_8 = (2 << PORT_SHIFT | 8), - P2_9 = (2 << PORT_SHIFT | 9), - P2_10 = (2 << PORT_SHIFT | 10), - P2_11 = (2 << PORT_SHIFT | 11), - P2_12 = (2 << PORT_SHIFT | 12), - P2_13 = (2 << PORT_SHIFT | 13), - P2_14 = (2 << PORT_SHIFT | 14), - P2_15 = (2 << PORT_SHIFT | 15), - P2_16 = (2 << PORT_SHIFT | 16), - P2_17 = (2 << PORT_SHIFT | 17), - P2_18 = (2 << PORT_SHIFT | 18), - P2_19 = (2 << PORT_SHIFT | 19), - P2_20 = (2 << PORT_SHIFT | 20), - P2_21 = (2 << PORT_SHIFT | 21), - P2_22 = (2 << PORT_SHIFT | 22), - P2_23 = (2 << PORT_SHIFT | 23), - P2_24 = (2 << PORT_SHIFT | 24), - P2_25 = (2 << PORT_SHIFT | 25), - P2_26 = (2 << PORT_SHIFT | 26), - P2_27 = (2 << PORT_SHIFT | 27), - P2_28 = (2 << PORT_SHIFT | 28), - P2_29 = (2 << PORT_SHIFT | 29), - P2_30 = (2 << PORT_SHIFT | 30), - P2_31 = (2 << PORT_SHIFT | 31), - - P3_0 = (3 << PORT_SHIFT | 0), - P3_1 = (3 << PORT_SHIFT | 1), - P3_2 = (3 << PORT_SHIFT | 2), - P3_3 = (3 << PORT_SHIFT | 3), - P3_4 = (3 << PORT_SHIFT | 4), - P3_5 = (3 << PORT_SHIFT | 5), - - LED_RED = P1_4, - LED_GREEN = P1_17, - LED_BLUE = P1_18, - BUZZER = P1_19, - - // LED naming - LED1 = LED_RED, - LED2 = LED_BLUE, - - // Push buttons - SW1 = P1_1, - - // USB Pins - USBTX = P0_30, - USBRX = P0_29, - - // Arduino Headers - D0 = P1_24, - D1 = P0_27, - D2 = P1_31, - D3 = P1_28, - D4 = P1_27, - D5 = P1_26, - D6 = P1_25, - D7 = P1_22, - - D8 = P1_23, - D9 = P0_21, - D10 = P0_4, - D11 = P0_3, - D12 = P0_2, - D13 = P0_6, - D14 = P1_21, - D15 = P1_20, - - I2C_SDA = D14, - I2C_SCL = D15, - - A0 = P0_23, - A1 = P0_15, - A2 = P0_31, - A3 = P1_8, - A4 = P0_16, - A5 = P1_0, - - // SPI Pins configuration - SPI_MOSI = D11, - SPI_MISO = D12, - SPI_SCK = D13, - SPI_CS = D10, - - // Not connected - NC = (int)0xFFFFFFFF - -} PinName; - - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 2, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/clock_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/clock_config.c deleted file mode 100644 index 72deaf210a..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/clock_config.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ -/* - * How to set up clock using clock driver functions: - * - * 1. Setup clock sources. - * - * 2. Set up wait states of the flash. - * - * 3. Set up all dividers. - * - * 4. Set up all selectors to provide selected clocks. - */ - -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Clocks v5.0 -processor: LPC55S69 -package_id: LPC55S69JBD100 -mcu_data: ksdk2_0 -processor_version: 0.0.6 - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -#include "fsl_power.h" -#include "fsl_clock.h" -#include "clock_config.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ -void BOARD_InitBootClocks(void) -{ - BOARD_BootClockFROHF96M(); -} - -/******************************************************************************* - ******************** Configuration BOARD_BootClockFRO12M ********************** - ******************************************************************************/ -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockFRO12M -outputs: -- {id: System_clock.outFreq, value: 12 MHz} -settings: -- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} -sources: -- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -/******************************************************************************* - * Variables for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -void BOARD_BootClockFRO12M(void) -{ -#ifndef SDK_SECONDARY_CORE - /*!< Set up the clock sources */ - /*!< Configure FRO192M */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ - CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ - - CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ - - POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ - CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ - - /*!< Set up dividers */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ - - /*< Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; -#endif -} - -/******************************************************************************* - ******************* Configuration BOARD_BootClockFROHF96M ********************* - ******************************************************************************/ -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockFROHF96M -called_from_default_init: true -outputs: -- {id: System_clock.outFreq, value: 96 MHz} -settings: -- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} -- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk} -sources: -- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -/******************************************************************************* - * Variables for BOARD_BootClockFROHF96M configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockFROHF96M configuration - ******************************************************************************/ -void BOARD_BootClockFROHF96M(void) -{ -#ifndef SDK_SECONDARY_CORE - /*!< Set up the clock sources */ - /*!< Configure FRO192M */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ - CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ - - CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ - - POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ - CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ - - /*!< Set up dividers */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ - - /*< Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; -#endif -} - -/******************************************************************************* - ******************** Configuration BOARD_BootClockPLL100M ********************* - ******************************************************************************/ -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockPLL100M -outputs: -- {id: System_clock.outFreq, value: 100 MHz} -settings: -- {id: PLL0_Mode, value: Normal} -- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} -- {id: ENABLE_CLKIN_ENA, value: Enabled} -- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} -- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} -- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} -- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true} -- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true} -- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true} -sources: -- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} -- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -/******************************************************************************* - * Variables for BOARD_BootClockPLL100M configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockPLL100M configuration - ******************************************************************************/ -void BOARD_BootClockPLL100M(void) -{ -#ifndef SDK_SECONDARY_CORE - /*!< Set up the clock sources */ - /*!< Configure FRO192M */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ - CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ - - CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ - - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ - CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ - - POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ - CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */ - - /*!< Set up PLL */ - CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ - POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ - POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); - const pll_setup_t pll0Setup = { - .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(54U) | SYSCON_PLL0CTRL_SELP(26U), - .pllndec = SYSCON_PLL0NDEC_NDIV(4U), - .pllpdec = SYSCON_PLL0PDEC_PDIV(2U), - .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, - .pllRate = 100000000U, - .flags = PLL_SETUPFLAG_WAITLOCK - }; - CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ - - /*!< Set up dividers */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ - - /*< Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK; -#endif -} - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/clock_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/clock_config.h deleted file mode 100644 index f8e76a3c87..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/clock_config.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */ -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************** Configuration BOARD_BootClockFRO12M ********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ - - -/******************************************************************************* - * API for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockFRO12M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************* Configuration BOARD_BootClockFROHF96M ********************* - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockFROHF96M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ - - -/******************************************************************************* - * API for BOARD_BootClockFROHF96M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockFROHF96M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************** Configuration BOARD_BootClockPLL100M ********************* - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockPLL100M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ - - -/******************************************************************************* - * API for BOARD_BootClockPLL100M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockPLL100M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/device.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/device.h deleted file mode 100644 index 95b285785f..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/device.h +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2020 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define NUMBER_OF_GPIO_INTS 8 - -#define LPADC_VREF_SOURCE kLPADC_ReferenceVoltageAlt2 -#define LPADC_DO_OFFSET_CALIBRATION false -#define LPADC_OFFSET_VALUE_A 10U -#define LPADC_OFFSET_VALUE_B 10U - -#define APP_EXCLUDE_FROM_DEEPSLEEP (kPDRUNCFG_PD_DCDC | kPDRUNCFG_PD_FRO192M | kPDRUNCFG_PD_FRO32K) - -/* Defines used by the sleep code */ -#define LPC_CLOCK_INTERNAL_IRC BOARD_BootClockFRO12M() -#define LPC_CLOCK_RUN BOARD_BootClockFROHF96M() - -#define DEVICE_ID_LENGTH 24 - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/mbed_overrides.c deleted file mode 100644 index 46364b5c68..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/mbed_overrides.c +++ /dev/null @@ -1,68 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2020 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" -#include "clock_config.h" -#include "fsl_power.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -// called before main -void mbed_sdk_init() -{ - BOARD_BootClockFROHF96M(); -} - -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(void) -{ - -} - -uint32_t us_ticker_get_clock() -{ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* Use 96 MHz clock us ticker timer */ - CLOCK_AttachClk(kFRO_HF_to_CTIMER0); - return CLOCK_GetFreq(kCLOCK_CTmier0);; -#else - /* Use 96 MHz clock us ticker timer */ - CLOCK_AttachClk(kFRO_HF_to_CTIMER1); - return CLOCK_GetFreq(kCLOCK_CTmier1);; -#endif -} - -void ADC_ClockPower_Configuration(void) -{ - /* Set clock source for ADC0 */ - CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, 16U, true); - CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); - - /* Disable LDOGPADC power down */ - POWER_DisablePD(kPDRUNCFG_PD_LDOGPADC); - RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn); -} - -void sdio_clock_setup(void) -{ - /* Attach main clock to SDIF */ - CLOCK_AttachClk(kMAIN_CLK_to_SDIO_CLK); - - CLOCK_SetClkDiv(kCLOCK_DivSdioClk, 1U, true); -} - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralNames.h deleted file mode 100644 index f3137e9523..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralNames.h +++ /dev/null @@ -1,139 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" -#include "PortNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - OSC32KCLK = 0, -} RTCName; - -typedef enum { - UART_0 = Flexcomm0, - UART_1 = Flexcomm2 -} UARTName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_0 - -typedef enum { - I2C_0 = Flexcomm1, - I2C_1 = Flexcomm4 -} I2CName; - -#define TPM_SHIFT 8 -typedef enum { - PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 - PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 - PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 - PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 - PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 - PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 - PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 - PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 - PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 - PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 - PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2 - PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3 - PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4 - PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5 - PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6 - PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7 - PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 - PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 - PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2 - PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3 - PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4 - PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5 - PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6 - PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7 - PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 - PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 - PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 - PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 - PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 - PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 - PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 - PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 -} PWMName; - -#define ADC_INSTANCE_SHIFT 8 -#define ADC_B_CHANNEL_SHIFT 5 - -typedef enum { - ADC0_SE0 = 0, - ADC0_SE1 = 1, - ADC0_SE2 = 2, - ADC0_SE3 = 3, - ADC0_SE4 = 4, - ADC0_SE5 = 5, - ADC0_SE6 = 6, - ADC0_SE7 = 7, - ADC0_SE8 = 8, - ADC0_SE9 = 9, - ADC0_SE10 = 10, - ADC0_SE11 = 11, - ADC0_SE12 = 12, - ADC0_SE13 = 13, - ADC0_SE14 = 14, - ADC0_SE15 = 15, - ADC0_SE0_B = (1 << ADC_B_CHANNEL_SHIFT) | 0, - ADC0_SE1_B = (1 << ADC_B_CHANNEL_SHIFT) | 1, - ADC0_SE2_B = (1 << ADC_B_CHANNEL_SHIFT) | 2, - ADC0_SE3_B = (1 << ADC_B_CHANNEL_SHIFT) | 3, - ADC0_SE4_B = (1 << ADC_B_CHANNEL_SHIFT) | 4, - ADC0_SE5_B = (1 << ADC_B_CHANNEL_SHIFT) | 5, - ADC0_SE6_B = (1 << ADC_B_CHANNEL_SHIFT) | 6, - ADC0_SE7_B = (1 << ADC_B_CHANNEL_SHIFT) | 7, - ADC0_SE8_B = (1 << ADC_B_CHANNEL_SHIFT) | 8, - ADC0_SE9_B = (1 << ADC_B_CHANNEL_SHIFT) | 9, - ADC0_SE10_B = (1 << ADC_B_CHANNEL_SHIFT) | 10, - ADC0_SE11_B = (1 << ADC_B_CHANNEL_SHIFT) | 11, - ADC0_SE12_B = (1 << ADC_B_CHANNEL_SHIFT) | 12, - ADC0_SE13_B = (1 << ADC_B_CHANNEL_SHIFT) | 13, - ADC0_SE14_B = (1 << ADC_B_CHANNEL_SHIFT) | 14, - ADC0_SE15_B = (1 << ADC_B_CHANNEL_SHIFT) | 15 -} ADCName; - -typedef enum { - CAN_0 = 0, - CAN_1 = 1 -} CANName; - -#define SSELNUM_SHIFT 16 -typedef enum { - SPI_0 = Flexcomm3, - SPI_1 = Flexcomm7, - SPI_2 = Flexcomm8 -} SPIName; - -/* Flexcomm 8 on LPC55S69 is dedicated for HS-SPI and hence uses different naming convention */ -#define kFRO12M_to_FLEXCOMM8 (kFRO12M_to_HSLSPI) -#define kFC8_RST_SHIFT_RSTn (kHSLSPI_RST_SHIFT_RSTn) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralPinMaps.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralPinMaps.h deleted file mode 100644 index afe265115a..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralPinMaps.h +++ /dev/null @@ -1,146 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PERIPHERALPINMAPS_H -#define MBED_PERIPHERALPINMAPS_H - -#include - -/************RTC***************/ -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_RTC[] = { - {NC, OSC32KCLK, 0}, -}; - -/************ADC***************/ -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_ADC[] = { - {P0_23, ADC0_SE0, 0}, - {P0_10, ADC0_SE1, 0}, - {P0_31, ADC0_SE3, 0}, - {P1_8, ADC0_SE4, 0}, - {P2_0, ADC0_SE5, 0}, - {P2_13, ADC0_SE6, 0}, - {P2_11, ADC0_SE7, 0}, - {NC , NC , 0} -}; - -/************CAN***************/ -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_CAN_TD[] = { - {NC , NC , 0} -}; - -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_CAN_RD[] = { - {NC , NC , 0} -}; - - -/************DAC***************/ -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_DAC[] = { - {NC , NC , 0} -}; - -/************I2C***************/ -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_I2C_SDA[] = { - {P0_13, I2C_0, 1}, - {P1_21, I2C_1, 5}, - {NC , NC , 0} -}; - -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_I2C_SCL[] = { - {P0_14, I2C_0, 1}, - {P1_20, I2C_1, 5}, - {NC , NC , 0} -}; - -/************UART***************/ -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_TX[] = { - {P0_30, UART_0, 1}, - {P1_6, UART_0, 1}, - {P0_27, UART_1, 1}, - {NC , NC , 0} -}; - -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_RX[] = { - {P0_29, UART_0, 1}, - {P1_5, UART_0, 1}, - {P1_24, UART_1, 1}, - {NC , NC , 0} -}; - -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_CTS[] = { - {P1_8, UART_0, 1}, - {P1_26, UART_1, 1}, - {NC , NC , 0} -}; - -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_RTS[] = { - {P1_7, UART_0, 1}, - {P1_27, UART_1, 1}, - {NC , NC , 0} -}; - -/************SPI***************/ -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_SCLK[] = { - {P0_6, SPI_0, 1}, - {P0_21, SPI_1, 7}, - {P1_2, SPI_2, 6}, - {NC , NC , 0} -}; - -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_MOSI[] = { - {P0_3, SPI_0, 1}, - {P0_20, SPI_1, 7}, - {P0_26, SPI_2, 9}, - {NC , NC , 0} -}; - -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_MISO[] = { - {P0_2, SPI_0, 1}, - {P0_19, SPI_1, 7}, - {P1_3, SPI_2, 6}, - {NC , NC , 0} -}; - -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_SSEL[] = { - {P0_4, SPI_0, 8}, - {P1_20, SPI_1, ((1 << SSELNUM_SHIFT) | 1)}, - {P1_1, SPI_2, ((1 << SSELNUM_SHIFT) | 5)}, - {NC , NC , 0} -}; - -/************PWM***************/ -MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_PWM[] = { - {NC , NC , 0} -}; - - -#define PINMAP_ANALOGIN PinMap_ADC -#define PINMAP_ANALOGOUT PinMap_DAC -#define PINMAP_I2C_SDA PinMap_I2C_SDA -#define PINMAP_I2C_SCL PinMap_I2C_SCL -#define PINMAP_UART_TX PinMap_UART_TX -#define PINMAP_UART_RX PinMap_UART_RX -#define PINMAP_UART_CTS PinMap_UART_CTS -#define PINMAP_UART_RTS PinMap_UART_RTS -#define PINMAP_SPI_SCLK PinMap_SPI_SCLK -#define PINMAP_SPI_MOSI PinMap_SPI_MOSI -#define PINMAP_SPI_MISO PinMap_SPI_MISO -#define PINMAP_SPI_SSEL PinMap_SPI_SSEL -#define PINMAP_PWM PinMap_PWM -#define PINMAP_CAN_TD PinMap_CAN_TD -#define PINMAP_CAN_RD PinMap_CAN_RD - -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralPins.c deleted file mode 100644 index 8ace3dd9a2..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralPins.c +++ /dev/null @@ -1,40 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" -#include "PeripheralPinMaps.h" - -// List of GPIOs with limited functionality -const PinList *pinmap_gpio_restricted_pins() -{ - static const PinName pins[] = { - A4, // fixed pull-up (for I2C) - A5, // fixed pull-up (for I2C) - D5, // fixed pull-up (for LED) - D3, // fixed pull-up (for LED) - D4, // fixed pull-up (for LED) - D7, // fixed pull-up - D15, // fixed pull-up (for I2C) - D14 // fixed pull-up (for I2C) - }; - - static const PinList pin_list = { - sizeof(pins) / sizeof(pins[0]), - pins - }; - return &pin_list; -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PinNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PinNames.h deleted file mode 100644 index 91557fd877..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PinNames.h +++ /dev/null @@ -1,209 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* If this macro is defined, then constexpr utility functions for pin-map seach can be used. */ -#define STATIC_PINMAP_READY 1 - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 5 - -typedef enum { - P0_0 = (0 << PORT_SHIFT | 0), - P0_1 = (0 << PORT_SHIFT | 1), - P0_2 = (0 << PORT_SHIFT | 2), - P0_3 = (0 << PORT_SHIFT | 3), - P0_4 = (0 << PORT_SHIFT | 4), - P0_5 = (0 << PORT_SHIFT | 5), - P0_6 = (0 << PORT_SHIFT | 6), - P0_7 = (0 << PORT_SHIFT | 7), - P0_8 = (0 << PORT_SHIFT | 8), - P0_9 = (0 << PORT_SHIFT | 9), - P0_10 = (0 << PORT_SHIFT | 10), - P0_11 = (0 << PORT_SHIFT | 11), - P0_12 = (0 << PORT_SHIFT | 12), - P0_13 = (0 << PORT_SHIFT | 13), - P0_14 = (0 << PORT_SHIFT | 14), - P0_15 = (0 << PORT_SHIFT | 15), - P0_16 = (0 << PORT_SHIFT | 16), - P0_17 = (0 << PORT_SHIFT | 17), - P0_18 = (0 << PORT_SHIFT | 18), - P0_19 = (0 << PORT_SHIFT | 19), - P0_20 = (0 << PORT_SHIFT | 20), - P0_21 = (0 << PORT_SHIFT | 21), - P0_22 = (0 << PORT_SHIFT | 22), - P0_23 = (0 << PORT_SHIFT | 23), - P0_24 = (0 << PORT_SHIFT | 24), - P0_25 = (0 << PORT_SHIFT | 25), - P0_26 = (0 << PORT_SHIFT | 26), - P0_27 = (0 << PORT_SHIFT | 27), - P0_28 = (0 << PORT_SHIFT | 28), - P0_29 = (0 << PORT_SHIFT | 29), - P0_30 = (0 << PORT_SHIFT | 30), - P0_31 = (0 << PORT_SHIFT | 31), - - P1_0 = (1 << PORT_SHIFT | 0), - P1_1 = (1 << PORT_SHIFT | 1), - P1_2 = (1 << PORT_SHIFT | 2), - P1_3 = (1 << PORT_SHIFT | 3), - P1_4 = (1 << PORT_SHIFT | 4), - P1_5 = (1 << PORT_SHIFT | 5), - P1_6 = (1 << PORT_SHIFT | 6), - P1_7 = (1 << PORT_SHIFT | 7), - P1_8 = (1 << PORT_SHIFT | 8), - P1_9 = (1 << PORT_SHIFT | 9), - P1_10 = (1 << PORT_SHIFT | 10), - P1_11 = (1 << PORT_SHIFT | 11), - P1_12 = (1 << PORT_SHIFT | 12), - P1_13 = (1 << PORT_SHIFT | 13), - P1_14 = (1 << PORT_SHIFT | 14), - P1_15 = (1 << PORT_SHIFT | 15), - P1_16 = (1 << PORT_SHIFT | 16), - P1_17 = (1 << PORT_SHIFT | 17), - P1_18 = (1 << PORT_SHIFT | 18), - P1_19 = (1 << PORT_SHIFT | 19), - P1_20 = (1 << PORT_SHIFT | 20), - P1_21 = (1 << PORT_SHIFT | 21), - P1_22 = (1 << PORT_SHIFT | 22), - P1_23 = (1 << PORT_SHIFT | 23), - P1_24 = (1 << PORT_SHIFT | 24), - P1_25 = (1 << PORT_SHIFT | 25), - P1_26 = (1 << PORT_SHIFT | 26), - P1_27 = (1 << PORT_SHIFT | 27), - P1_28 = (1 << PORT_SHIFT | 28), - P1_29 = (1 << PORT_SHIFT | 29), - P1_30 = (1 << PORT_SHIFT | 30), - P1_31 = (1 << PORT_SHIFT | 31), - - P2_0 = (2 << PORT_SHIFT | 0), - P2_1 = (2 << PORT_SHIFT | 1), - P2_2 = (2 << PORT_SHIFT | 2), - P2_3 = (2 << PORT_SHIFT | 3), - P2_4 = (2 << PORT_SHIFT | 4), - P2_5 = (2 << PORT_SHIFT | 5), - P2_6 = (2 << PORT_SHIFT | 6), - P2_7 = (2 << PORT_SHIFT | 7), - P2_8 = (2 << PORT_SHIFT | 8), - P2_9 = (2 << PORT_SHIFT | 9), - P2_10 = (2 << PORT_SHIFT | 10), - P2_11 = (2 << PORT_SHIFT | 11), - P2_12 = (2 << PORT_SHIFT | 12), - P2_13 = (2 << PORT_SHIFT | 13), - P2_14 = (2 << PORT_SHIFT | 14), - P2_15 = (2 << PORT_SHIFT | 15), - P2_16 = (2 << PORT_SHIFT | 16), - P2_17 = (2 << PORT_SHIFT | 17), - P2_18 = (2 << PORT_SHIFT | 18), - P2_19 = (2 << PORT_SHIFT | 19), - P2_20 = (2 << PORT_SHIFT | 20), - P2_21 = (2 << PORT_SHIFT | 21), - P2_22 = (2 << PORT_SHIFT | 22), - P2_23 = (2 << PORT_SHIFT | 23), - P2_24 = (2 << PORT_SHIFT | 24), - P2_25 = (2 << PORT_SHIFT | 25), - P2_26 = (2 << PORT_SHIFT | 26), - P2_27 = (2 << PORT_SHIFT | 27), - P2_28 = (2 << PORT_SHIFT | 28), - P2_29 = (2 << PORT_SHIFT | 29), - P2_30 = (2 << PORT_SHIFT | 30), - P2_31 = (2 << PORT_SHIFT | 31), - - P3_0 = (3 << PORT_SHIFT | 0), - P3_1 = (3 << PORT_SHIFT | 1), - P3_2 = (3 << PORT_SHIFT | 2), - P3_3 = (3 << PORT_SHIFT | 3), - P3_4 = (3 << PORT_SHIFT | 4), - P3_5 = (3 << PORT_SHIFT | 5), - - LED_RED = P1_4, - - // mbed original LED naming - LED1 = P1_6, - LED2 = P1_7, - LED3 = LED_RED, - LED4 = LED_RED, - - //Push buttons - SW2 = P1_18, - SW3 = P1_9, - - // USB Pins - USBTX = P0_30, - USBRX = P0_29, - - // Arduino Headers - D0 = P1_24, - D1 = P0_27, - D2 = P0_15, - D3 = P1_6, - D4 = P1_7, - D5 = P1_4, - D6 = P1_10, - D7 = P1_9, - D8 = P1_8, - D9 = P1_5, - D10 = P1_1, - D11 = P0_26, - D12 = P1_3, - D13 = P1_2, - D14 = P1_21, - D15 = P1_20, - - I2C_SCL = D15, - I2C_SDA = D14, - - A0 = P0_16, - A1 = P0_23, - A2 = P0_0, - A3 = P1_31, - A4 = P0_13, - A5 = P0_14, - - //SPI Pins configuration - SPI_MOSI = D11, - SPI_MISO = D12, - SPI_SCK = D13, - SPI_CS = D10, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 2, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/clock_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/clock_config.c deleted file mode 100644 index 731e8ceed1..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/clock_config.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright 2017-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ -/* - * How to set up clock using clock driver functions: - * - * 1. Setup clock sources. - * - * 2. Set up wait states of the flash. - * - * 3. Set up all dividers. - * - * 4. Set up all selectors to provide selected clocks. - */ - -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Clocks v5.0 -processor: LPC55S69 -package_id: LPC55S69JBD100 -mcu_data: ksdk2_0 -processor_version: 0.0.6 - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -#include "fsl_power.h" -#include "fsl_clock.h" -#include "clock_config.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ -void BOARD_InitBootClocks(void) -{ - BOARD_BootClockFROHF96M(); -} - -/******************************************************************************* - ******************** Configuration BOARD_BootClockFRO12M ********************** - ******************************************************************************/ -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockFRO12M -outputs: -- {id: System_clock.outFreq, value: 12 MHz} -settings: -- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} -sources: -- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -/******************************************************************************* - * Variables for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -void BOARD_BootClockFRO12M(void) -{ -#ifndef SDK_SECONDARY_CORE - /*!< Set up the clock sources */ - /*!< Configure FRO192M */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ - CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ - - CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ - - POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ - CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ - - /*!< Set up dividers */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ - - /*< Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; -#endif -} - -/******************************************************************************* - ******************* Configuration BOARD_BootClockFROHF96M ********************* - ******************************************************************************/ -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockFROHF96M -called_from_default_init: true -outputs: -- {id: System_clock.outFreq, value: 96 MHz} -settings: -- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} -- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk} -sources: -- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -/******************************************************************************* - * Variables for BOARD_BootClockFROHF96M configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockFROHF96M configuration - ******************************************************************************/ -void BOARD_BootClockFROHF96M(void) -{ -#ifndef SDK_SECONDARY_CORE - /*!< Set up the clock sources */ - /*!< Configure FRO192M */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ - CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ - - CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ - - POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ - CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ - - /*!< Set up dividers */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ - - /*< Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; -#endif -} - -/******************************************************************************* - ******************** Configuration BOARD_BootClockPLL100M ********************* - ******************************************************************************/ -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockPLL100M -outputs: -- {id: System_clock.outFreq, value: 100 MHz} -settings: -- {id: PLL0_Mode, value: Normal} -- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} -- {id: ENABLE_CLKIN_ENA, value: Enabled} -- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} -- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} -- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} -- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true} -- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true} -- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true} -sources: -- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} -- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -/******************************************************************************* - * Variables for BOARD_BootClockPLL100M configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockPLL100M configuration - ******************************************************************************/ -void BOARD_BootClockPLL100M(void) -{ -#ifndef SDK_SECONDARY_CORE - /*!< Set up the clock sources */ - /*!< Configure FRO192M */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ - CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ - - CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ - - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ - CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ - - POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ - CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */ - - /*!< Set up PLL */ - CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ - POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ - POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); - const pll_setup_t pll0Setup = { - .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(54U) | SYSCON_PLL0CTRL_SELP(26U), - .pllndec = SYSCON_PLL0NDEC_NDIV(4U), - .pllpdec = SYSCON_PLL0PDEC_PDIV(2U), - .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, - .pllRate = 100000000U, - .flags = PLL_SETUPFLAG_WAITLOCK - }; - CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ - - /*!< Set up dividers */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ - - /*< Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK; -#endif -} - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/clock_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/clock_config.h deleted file mode 100644 index 84414bce39..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/clock_config.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright 2017-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */ -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************** Configuration BOARD_BootClockFRO12M ********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ - - -/******************************************************************************* - * API for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockFRO12M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************* Configuration BOARD_BootClockFROHF96M ********************* - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockFROHF96M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ - - -/******************************************************************************* - * API for BOARD_BootClockFROHF96M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockFROHF96M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************** Configuration BOARD_BootClockPLL100M ********************* - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockPLL100M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ - - -/******************************************************************************* - * API for BOARD_BootClockPLL100M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockPLL100M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/device.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/device.h deleted file mode 100644 index 58ffeeb74a..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/device.h +++ /dev/null @@ -1,39 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define NUMBER_OF_GPIO_INTS 8 - -#define LPADC_VREF_SOURCE kLPADC_ReferenceVoltageAlt2 -#define LPADC_DO_OFFSET_CALIBRATION false -#define LPADC_OFFSET_VALUE_A 10U -#define LPADC_OFFSET_VALUE_B 10U - -#define APP_EXCLUDE_FROM_DEEPSLEEP (kPDRUNCFG_PD_DCDC | kPDRUNCFG_PD_FRO192M | kPDRUNCFG_PD_FRO32K) - -/* Defines used by the sleep code */ -#define LPC_CLOCK_INTERNAL_IRC BOARD_BootClockFRO12M() -#define LPC_CLOCK_RUN BOARD_BootClockFROHF96M() - -#define DEVICE_ID_LENGTH 24 - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/mbed_overrides.c deleted file mode 100644 index 2b2cf5168a..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/mbed_overrides.c +++ /dev/null @@ -1,68 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" -#include "clock_config.h" -#include "fsl_power.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -// called before main -void mbed_sdk_init() -{ - BOARD_BootClockFROHF96M(); -} - -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(void) -{ - -} - -uint32_t us_ticker_get_clock() -{ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* Use 96 MHz clock us ticker timer */ - CLOCK_AttachClk(kFRO_HF_to_CTIMER0); - return CLOCK_GetFreq(kCLOCK_CTmier0);; -#else - /* Use 96 MHz clock us ticker timer */ - CLOCK_AttachClk(kFRO_HF_to_CTIMER1); - return CLOCK_GetFreq(kCLOCK_CTmier1);; -#endif -} - -void ADC_ClockPower_Configuration(void) -{ - /* Set clock source for ADC0 */ - CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, 16U, true); - CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); - - /* Disable LDOGPADC power down */ - POWER_DisablePD(kPDRUNCFG_PD_LDOGPADC); - RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn); -} - -void sdio_clock_setup(void) -{ - /* Attach main clock to SDIF */ - CLOCK_AttachClk(kMAIN_CLK_to_SDIO_CLK); - - CLOCK_SetClkDiv(kCLOCK_DivSdioClk, 1U, true); -} - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_ARMC6/LPC55S69_cm33_core0_flash.sct b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_ARMC6/LPC55S69_cm33_core0_flash.sct deleted file mode 100644 index 4dc1afc672..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_ARMC6/LPC55S69_cm33_core0_flash.sct +++ /dev/null @@ -1,148 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b181008 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ -#include "../../../partition/region_defs.h" - -#define __ram_vector_table__ 1 - -#if (defined(__ram_vector_table__)) - #define __ram_vector_table_size__ 0x00000200 -#else - #define __ram_vector_table_size__ 0x00000000 -#endif - -/* USB BDT size */ -#define usb_bdt_size 0x0 - -/* Sizes */ -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif -#endif - -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START NS_CODE_START -#endif - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE NS_CODE_SIZE -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START NS_DATA_START -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE NS_DATA_SIZE -#endif - -#if !defined(NVIC_INTERRUPT_NUM) - #define NVIC_INTERRUPT_NUM 60 -#endif - -#if !defined(EXCEPTION_VECT_NUM) - #define EXCEPTION_VECT_NUM 16 -#endif - -#if !defined(MEMORY_ADDR_SIZE_IN_BYTE) - #define MEMORY_ADDR_SIZE_IN_BYTE 4 -#endif - -#define m_interrupts_start MBED_APP_START -#define m_interrupts_size ((NVIC_INTERRUPT_NUM + EXCEPTION_VECT_NUM) * MEMORY_ADDR_SIZE_IN_BYTE) - -#define m_text_start MBED_APP_START + m_interrupts_size -#define m_text_size MBED_APP_SIZE - m_interrupts_size - -#define m_interrupts_ram_start MBED_RAM_START -#define m_interrupts_ram_size __ram_vector_table_size__ - -#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size) -#define m_data_size (MBED_RAM_SIZE - m_interrupts_ram_size) - -#define m_usb_sram_start 0x40100000 -#define m_usb_sram_size 0x00004000 - -LR_IROM1 m_interrupts_start (AlignExpr(m_text_start, 8)+m_text_size-m_interrupts_start) { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) - } - - ER_IROM1 AlignExpr(m_text_start, 8) FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - -#if (defined(__ram_vector_table__)) - VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size { - } -#else - VECTOR_RAM m_interrupts_start EMPTY 0 { - } -#endif - - RW_m_data m_data_start m_data_size { ; RW data - .ANY (+RW +ZI) - } - RW_IRAM1 ImageLimit(RW_m_data) { - } - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (m_data_start + m_data_size - Stack_Size - AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - - RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (m_usb_bdt) - } - - RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (m_usb_global) - } -} - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_ARMC6/startup_LPC55S69_cm33_core0.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_ARMC6/startup_LPC55S69_cm33_core0.S deleted file mode 100644 index 4c0b7b442a..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_ARMC6/startup_LPC55S69_cm33_core0.S +++ /dev/null @@ -1,727 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC55S69_cm33_core0.s -; * @purpose: CMSIS Cortex-M33 Core Device Startup File for the -; * LPC55S69_cm33_core0 -; * @version: 1.0 -; * @date: 2018-8-22 -; * -; * Copyright 1997-2016 Freescale Semiconductor, Inc. -; * Copyright 2016-2019 NXP -; * All rights reserved. -; * -; * SPDX-License-Identifier: BSD-3-Clause -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 ; Checksum of the first 7 words - DCD 0 - DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot - DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt - DCD DMA0_IRQHandler ; DMA0 controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD ADC0_IRQHandler ; ADC0 - DCD Reserved39_IRQHandler ; Reserved interrupt - DCD ACMP_IRQHandler ; ACMP interrupts - DCD Reserved41_IRQHandler ; Reserved interrupt - DCD Reserved42_IRQHandler ; Reserved interrupt - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD Reserved46_IRQHandler ; Reserved interrupt - DCD MAILBOX_IRQHandler ; WAKEUP,Mailbox interrupt (present on selected devices) - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD OS_EVENT_IRQHandler ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts - DCD Reserved55_IRQHandler ; Reserved interrupt - DCD Reserved56_IRQHandler ; Reserved interrupt - DCD Reserved57_IRQHandler ; Reserved interrupt - DCD SDIO_IRQHandler ; SD/MMC - DCD Reserved59_IRQHandler ; Reserved interrupt - DCD Reserved60_IRQHandler ; Reserved interrupt - DCD Reserved61_IRQHandler ; Reserved interrupt - DCD USB1_UTMI_IRQHandler ; USB1_UTMI - DCD USB1_IRQHandler ; USB1 interrupt - DCD USB1_NEEDCLK_IRQHandler ; USB1 activity - DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt - DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt - DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt - DCD PLU_IRQHandler ; PLU interrupt - DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt - DCD HASHCRYPT_IRQHandler ; HASHCRYPT interrupt - DCD CASER_IRQHandler ; CASPER interrupt - DCD PUF_IRQHandler ; PUF interrupt - DCD PQ_IRQHandler ; PQ interrupt - DCD DMA1_IRQHandler ; DMA1 interrupt - DCD LSPI_HS_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM) - - - AREA |.text|, CODE, READONLY - -; Reset Handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| - - CPSID I ; Mask interrupts - LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Base| - MSR MSPLIM, R0 - LDR R0, =SystemInit - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler \ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -WDT_BOD_IRQHandler\ - PROC - EXPORT WDT_BOD_IRQHandler [WEAK] - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - ENDP - -DMA0_IRQHandler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - LDR R0, =DMA0_DriverIRQHandler - BX R0 - ENDP - -GINT0_IRQHandler\ - PROC - EXPORT GINT0_IRQHandler [WEAK] - LDR R0, =GINT0_DriverIRQHandler - BX R0 - ENDP - -GINT1_IRQHandler\ - PROC - EXPORT GINT1_IRQHandler [WEAK] - LDR R0, =GINT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT0_IRQHandler\ - PROC - EXPORT PIN_INT0_IRQHandler [WEAK] - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - ENDP - -PIN_INT1_IRQHandler\ - PROC - EXPORT PIN_INT1_IRQHandler [WEAK] - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT2_IRQHandler\ - PROC - EXPORT PIN_INT2_IRQHandler [WEAK] - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - ENDP - -PIN_INT3_IRQHandler\ - PROC - EXPORT PIN_INT3_IRQHandler [WEAK] - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - ENDP - -UTICK0_IRQHandler\ - PROC - EXPORT UTICK0_IRQHandler [WEAK] - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - ENDP - -MRT0_IRQHandler\ - PROC - EXPORT MRT0_IRQHandler [WEAK] - LDR R0, =MRT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER0_IRQHandler\ - PROC - EXPORT CTIMER0_IRQHandler [WEAK] - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - ENDP - -CTIMER1_IRQHandler\ - PROC - EXPORT CTIMER1_IRQHandler [WEAK] - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - ENDP - -SCT0_IRQHandler\ - PROC - EXPORT SCT0_IRQHandler [WEAK] - LDR R0, =SCT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER3_IRQHandler\ - PROC - EXPORT CTIMER3_IRQHandler [WEAK] - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM0_IRQHandler\ - PROC - EXPORT FLEXCOMM0_IRQHandler [WEAK] - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM1_IRQHandler\ - PROC - EXPORT FLEXCOMM1_IRQHandler [WEAK] - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM2_IRQHandler\ - PROC - EXPORT FLEXCOMM2_IRQHandler [WEAK] - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM3_IRQHandler\ - PROC - EXPORT FLEXCOMM3_IRQHandler [WEAK] - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM4_IRQHandler\ - PROC - EXPORT FLEXCOMM4_IRQHandler [WEAK] - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM5_IRQHandler\ - PROC - EXPORT FLEXCOMM5_IRQHandler [WEAK] - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM6_IRQHandler\ - PROC - EXPORT FLEXCOMM6_IRQHandler [WEAK] - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM7_IRQHandler\ - PROC - EXPORT FLEXCOMM7_IRQHandler [WEAK] - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - ENDP - -ADC0_IRQHandler\ - PROC - EXPORT ADC0_IRQHandler [WEAK] - LDR R0, =ADC0_DriverIRQHandler - BX R0 - ENDP - -Reserved39_IRQHandler\ - PROC - EXPORT Reserved39_IRQHandler [WEAK] - LDR R0, =Reserved39_DriverIRQHandler - BX R0 - ENDP - -ACMP_IRQHandler\ - PROC - EXPORT ACMP_IRQHandler [WEAK] - LDR R0, =ACMP_DriverIRQHandler - BX R0 - ENDP - -Reserved41_IRQHandler\ - PROC - EXPORT Reserved41_IRQHandler [WEAK] - LDR R0, =Reserved41_DriverIRQHandler - BX R0 - ENDP - -Reserved42_IRQHandler\ - PROC - EXPORT Reserved42_IRQHandler [WEAK] - LDR R0, =Reserved42_DriverIRQHandler - BX R0 - ENDP - -USB0_NEEDCLK_IRQHandler\ - PROC - EXPORT USB0_NEEDCLK_IRQHandler [WEAK] - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - ENDP - -USB0_IRQHandler\ - PROC - EXPORT USB0_IRQHandler [WEAK] - LDR R0, =USB0_DriverIRQHandler - BX R0 - ENDP - -RTC_IRQHandler\ - PROC - EXPORT RTC_IRQHandler [WEAK] - LDR R0, =RTC_DriverIRQHandler - BX R0 - ENDP - -Reserved46_IRQHandler\ - PROC - EXPORT Reserved46_IRQHandler [WEAK] - LDR R0, =Reserved46_DriverIRQHandler - BX R0 - ENDP - -MAILBOX_IRQHandler\ - PROC - EXPORT MAILBOX_IRQHandler [WEAK] - LDR R0, =MAILBOX_DriverIRQHandler - BX R0 - ENDP - -PIN_INT4_IRQHandler\ - PROC - EXPORT PIN_INT4_IRQHandler [WEAK] - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - ENDP - -PIN_INT5_IRQHandler\ - PROC - EXPORT PIN_INT5_IRQHandler [WEAK] - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - ENDP - -PIN_INT6_IRQHandler\ - PROC - EXPORT PIN_INT6_IRQHandler [WEAK] - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - ENDP - -PIN_INT7_IRQHandler\ - PROC - EXPORT PIN_INT7_IRQHandler [WEAK] - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - ENDP - -CTIMER2_IRQHandler\ - PROC - EXPORT CTIMER2_IRQHandler [WEAK] - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - ENDP - -CTIMER4_IRQHandler\ - PROC - EXPORT CTIMER4_IRQHandler [WEAK] - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - ENDP - -OS_EVENT_IRQHandler\ - PROC - EXPORT OS_EVENT_IRQHandler [WEAK] - LDR R0, =OS_EVENT_DriverIRQHandler - BX R0 - ENDP - -Reserved55_IRQHandler\ - PROC - EXPORT Reserved55_IRQHandler [WEAK] - LDR R0, =Reserved55_DriverIRQHandler - BX R0 - ENDP - -Reserved56_IRQHandler\ - PROC - EXPORT Reserved56_IRQHandler [WEAK] - LDR R0, =Reserved56_DriverIRQHandler - BX R0 - ENDP - -Reserved57_IRQHandler\ - PROC - EXPORT Reserved57_IRQHandler [WEAK] - LDR R0, =Reserved57_DriverIRQHandler - BX R0 - ENDP - -SDIO_IRQHandler\ - PROC - EXPORT SDIO_IRQHandler [WEAK] - LDR R0, =SDIO_DriverIRQHandler - BX R0 - ENDP - -Reserved59_IRQHandler\ - PROC - EXPORT Reserved59_IRQHandler [WEAK] - LDR R0, =Reserved59_DriverIRQHandler - BX R0 - ENDP - -Reserved60_IRQHandler\ - PROC - EXPORT Reserved60_IRQHandler [WEAK] - LDR R0, =Reserved60_DriverIRQHandler - BX R0 - ENDP - -Reserved61_IRQHandler\ - PROC - EXPORT Reserved61_IRQHandler [WEAK] - LDR R0, =Reserved61_DriverIRQHandler - BX R0 - ENDP - -USB1_UTMI_IRQHandler\ - PROC - EXPORT USB1_UTMI_IRQHandler [WEAK] - LDR R0, =USB1_UTMI_DriverIRQHandler - BX R0 - ENDP - -USB1_IRQHandler\ - PROC - EXPORT USB1_IRQHandler [WEAK] - LDR R0, =USB1_DriverIRQHandler - BX R0 - ENDP - -USB1_NEEDCLK_IRQHandler\ - PROC - EXPORT USB1_NEEDCLK_IRQHandler [WEAK] - LDR R0, =USB1_NEEDCLK_DriverIRQHandler - BX R0 - ENDP - -SEC_HYPERVISOR_CALL_IRQHandler\ - PROC - EXPORT SEC_HYPERVISOR_CALL_IRQHandler [WEAK] - LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler - BX R0 - ENDP - -SEC_GPIO_INT0_IRQ0_IRQHandler\ - PROC - EXPORT SEC_GPIO_INT0_IRQ0_IRQHandler [WEAK] - LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler - BX R0 - ENDP - -SEC_GPIO_INT0_IRQ1_IRQHandler\ - PROC - EXPORT SEC_GPIO_INT0_IRQ1_IRQHandler [WEAK] - LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler - BX R0 - ENDP - -PLU_IRQHandler\ - PROC - EXPORT PLU_IRQHandler [WEAK] - LDR R0, =PLU_DriverIRQHandler - BX R0 - ENDP - -SEC_VIO_IRQHandler\ - PROC - EXPORT SEC_VIO_IRQHandler [WEAK] - LDR R0, =SEC_VIO_DriverIRQHandler - BX R0 - ENDP - -HASHCRYPT_IRQHandler\ - PROC - EXPORT HASHCRYPT_IRQHandler [WEAK] - LDR R0, =HASHCRYPT_DriverIRQHandler - BX R0 - ENDP - -CASER_IRQHandler\ - PROC - EXPORT CASER_IRQHandler [WEAK] - LDR R0, =CASER_DriverIRQHandler - BX R0 - ENDP - -PUF_IRQHandler\ - PROC - EXPORT PUF_IRQHandler [WEAK] - LDR R0, =PUF_DriverIRQHandler - BX R0 - ENDP - -PQ_IRQHandler\ - PROC - EXPORT PQ_IRQHandler [WEAK] - LDR R0, =PQ_DriverIRQHandler - BX R0 - ENDP - -DMA1_IRQHandler\ - PROC - EXPORT DMA1_IRQHandler [WEAK] - LDR R0, =DMA1_DriverIRQHandler - BX R0 - ENDP - -LSPI_HS_IRQHandler\ - PROC - EXPORT LSPI_HS_IRQHandler [WEAK] - LDR R0, =LSPI_HS_DriverIRQHandler - BX R0 - ENDP - -Default_Handler PROC - EXPORT WDT_BOD_DriverIRQHandler [WEAK] - EXPORT DMA0_DriverIRQHandler [WEAK] - EXPORT GINT0_DriverIRQHandler [WEAK] - EXPORT GINT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT0_DriverIRQHandler [WEAK] - EXPORT PIN_INT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT2_DriverIRQHandler [WEAK] - EXPORT PIN_INT3_DriverIRQHandler [WEAK] - EXPORT UTICK0_DriverIRQHandler [WEAK] - EXPORT MRT0_DriverIRQHandler [WEAK] - EXPORT CTIMER0_DriverIRQHandler [WEAK] - EXPORT CTIMER1_DriverIRQHandler [WEAK] - EXPORT SCT0_DriverIRQHandler [WEAK] - EXPORT CTIMER3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM0_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM1_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM2_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM4_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM5_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM6_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM7_DriverIRQHandler [WEAK] - EXPORT ADC0_DriverIRQHandler [WEAK] - EXPORT Reserved39_DriverIRQHandler [WEAK] - EXPORT ACMP_DriverIRQHandler [WEAK] - EXPORT Reserved41_DriverIRQHandler [WEAK] - EXPORT Reserved42_DriverIRQHandler [WEAK] - EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK] - EXPORT USB0_DriverIRQHandler [WEAK] - EXPORT RTC_DriverIRQHandler [WEAK] - EXPORT Reserved46_DriverIRQHandler [WEAK] - EXPORT MAILBOX_DriverIRQHandler [WEAK] - EXPORT PIN_INT4_DriverIRQHandler [WEAK] - EXPORT PIN_INT5_DriverIRQHandler [WEAK] - EXPORT PIN_INT6_DriverIRQHandler [WEAK] - EXPORT PIN_INT7_DriverIRQHandler [WEAK] - EXPORT CTIMER2_DriverIRQHandler [WEAK] - EXPORT CTIMER4_DriverIRQHandler [WEAK] - EXPORT OS_EVENT_DriverIRQHandler [WEAK] - EXPORT Reserved55_DriverIRQHandler [WEAK] - EXPORT Reserved56_DriverIRQHandler [WEAK] - EXPORT Reserved57_DriverIRQHandler [WEAK] - EXPORT SDIO_DriverIRQHandler [WEAK] - EXPORT Reserved59_DriverIRQHandler [WEAK] - EXPORT Reserved60_DriverIRQHandler [WEAK] - EXPORT Reserved61_DriverIRQHandler [WEAK] - EXPORT USB1_UTMI_DriverIRQHandler [WEAK] - EXPORT USB1_DriverIRQHandler [WEAK] - EXPORT USB1_NEEDCLK_DriverIRQHandler [WEAK] - EXPORT SEC_HYPERVISOR_CALL_DriverIRQHandler [WEAK] - EXPORT SEC_GPIO_INT0_IRQ0_DriverIRQHandler [WEAK] - EXPORT SEC_GPIO_INT0_IRQ1_DriverIRQHandler [WEAK] - EXPORT PLU_DriverIRQHandler [WEAK] - EXPORT SEC_VIO_DriverIRQHandler [WEAK] - EXPORT HASHCRYPT_DriverIRQHandler [WEAK] - EXPORT CASER_DriverIRQHandler [WEAK] - EXPORT PUF_DriverIRQHandler [WEAK] - EXPORT PQ_DriverIRQHandler [WEAK] - EXPORT DMA1_DriverIRQHandler [WEAK] - EXPORT LSPI_HS_DriverIRQHandler [WEAK] - -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_DriverIRQHandler -Reserved39_DriverIRQHandler -ACMP_DriverIRQHandler -Reserved41_DriverIRQHandler -Reserved42_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -Reserved46_DriverIRQHandler -MAILBOX_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -OS_EVENT_DriverIRQHandler -Reserved55_DriverIRQHandler -Reserved56_DriverIRQHandler -Reserved57_DriverIRQHandler -SDIO_DriverIRQHandler -Reserved59_DriverIRQHandler -Reserved60_DriverIRQHandler -Reserved61_DriverIRQHandler -USB1_UTMI_DriverIRQHandler -USB1_DriverIRQHandler -USB1_NEEDCLK_DriverIRQHandler -SEC_HYPERVISOR_CALL_DriverIRQHandler -SEC_GPIO_INT0_IRQ0_DriverIRQHandler -SEC_GPIO_INT0_IRQ1_DriverIRQHandler -PLU_DriverIRQHandler -SEC_VIO_DriverIRQHandler -HASHCRYPT_DriverIRQHandler -CASER_DriverIRQHandler -PUF_DriverIRQHandler -PQ_DriverIRQHandler -DMA1_DriverIRQHandler -LSPI_HS_DriverIRQHandler - - B . - - ENDP - - - ALIGN - - - END - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_GCC_ARM/LPC55S69_cm33_core0_flash.ld b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_GCC_ARM/LPC55S69_cm33_core0_flash.ld deleted file mode 100644 index 56a01130b8..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_GCC_ARM/LPC55S69_cm33_core0_flash.ld +++ /dev/null @@ -1,284 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 -** -** Compiler: GNU C Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ -#include "../../../partition/region_defs.h" - -/* Entry Point */ -ENTRY(Reset_Handler) - -__ram_vector_table__ = 1; - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START NS_CODE_START -#endif - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE NS_CODE_SIZE -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START NS_DATA_START -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE NS_DATA_SIZE -#endif - -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -#endif - -#if !defined(NVIC_INTERRUPT_NUM) - #define NVIC_INTERRUPT_NUM 60 -#endif - -#if !defined(EXCEPTION_VECT_NUM) - #define EXCEPTION_VECT_NUM 16 -#endif - -#if !defined(MEMORY_ADDR_SIZE_IN_BYTE) - #define MEMORY_ADDR_SIZE_IN_BYTE 4 -#endif - -#if !defined(MBED_INTERRUPTS_SIZE) - #define MBED_INTERRUPTS_SIZE ((NVIC_INTERRUPT_NUM + EXCEPTION_VECT_NUM) * MEMORY_ADDR_SIZE_IN_BYTE) -#endif - -__stack_size__ = MBED_CONF_TARGET_BOOT_STACK_SIZE; - -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; -M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x200 : 0x0; - -MEMORY -{ - m_interrupts (RX) : ORIGIN = MBED_APP_START, LENGTH = MBED_INTERRUPTS_SIZE - m_text (RX) : ORIGIN = MBED_APP_START + MBED_INTERRUPTS_SIZE, LENGTH = MBED_APP_SIZE - MBED_INTERRUPTS_SIZE - m_data (RW) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE - m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into internal flash */ - .interrupts : - { - . = ALIGN(8); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(8); - } > m_interrupts - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(8); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(8); - } > m_text - -#if (! defined(DOMAIN_NS)) || (! DOMAIN_NS) - /* section for veneer table */ - .gnu.sgstubs : - { - . = ALIGN(32); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > m_veneer_table -#endif - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .interrupts_ram : - { - . = ALIGN(8); - __VECTOR_RAM__ = .; - __interrupts_ram_start__ = .; /* Create a global symbol at data start */ - *(.m_interrupts_ram) /* This is a user defined section */ - . += M_VECTOR_RAM_SIZE; - . = ALIGN(8); - __interrupts_ram_end__ = .; /* Define a global symbol at data end */ - } > m_data - - __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); - __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; - - .data : AT(__DATA_ROM) - { - . = ALIGN(8); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.ramfunc*) /* for functions in ram */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(8); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(8); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . = ORIGIN(m_data) + LENGTH(m_data) - STACK_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - m_usb_bdt (NOLOAD) : - { - . = ALIGN(512); - *(m_usb_bdt) - } > m_usb_sram - - m_usb_global (NOLOAD) : - { - *(m_usb_global) - } > m_usb_sram - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_GCC_ARM/startup_LPC55S69_cm33_core0.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_GCC_ARM/startup_LPC55S69_cm33_core0.S deleted file mode 100644 index 77b0913989..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_GCC_ARM/startup_LPC55S69_cm33_core0.S +++ /dev/null @@ -1,874 +0,0 @@ -/* --------------------------------------------------------------------------*/ -/* @file: startup_LPC55S69_cm33_core0.s */ -/* @purpose: CMSIS Cortex-M33 Core Device Startup File */ -/* LPC55S69_cm33_core0 */ -/* @version: 1.0 */ -/* @date: 2018-8-22 */ -/* --------------------------------------------------------------------------*/ -/* */ -/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2019 NXP */ -/* All rights reserved. */ -/* */ -/* SPDX-License-Identifier: BSD-3-Clause */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - - - .syntax unified - .arch armv8-m.main - - .section .isr_vector, "a" - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts */ - .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ - .long DMA0_IRQHandler /* DMA0 controller */ - .long GINT0_IRQHandler /* GPIO group 0 */ - .long GINT1_IRQHandler /* GPIO group 1 */ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - .long UTICK0_IRQHandler /* Micro-tick Timer */ - .long MRT0_IRQHandler /* Multi-rate timer */ - .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ - .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ - .long SCT0_IRQHandler /* SCTimer/PWM */ - .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ - .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - .long ADC0_IRQHandler /* ADC0 */ - .long Reserved39_IRQHandler /* Reserved interrupt */ - .long ACMP_IRQHandler /* ACMP interrupts */ - .long Reserved41_IRQHandler /* Reserved interrupt */ - .long Reserved42_IRQHandler /* Reserved interrupt */ - .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ - .long USB0_IRQHandler /* USB device */ - .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ - .long Reserved46_IRQHandler /* Reserved interrupt */ - .long MAILBOX_IRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */ - .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ - .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ - .long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ - .long Reserved55_IRQHandler /* Reserved interrupt */ - .long Reserved56_IRQHandler /* Reserved interrupt */ - .long Reserved57_IRQHandler /* Reserved interrupt */ - .long SDIO_IRQHandler /* SD/MMC */ - .long Reserved59_IRQHandler /* Reserved interrupt */ - .long Reserved60_IRQHandler /* Reserved interrupt */ - .long Reserved61_IRQHandler /* Reserved interrupt */ - .long USB1_UTMI_IRQHandler /* USB1_UTMI */ - .long USB1_IRQHandler /* USB1 interrupt */ - .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ - .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ - .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ - .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ - .long PLU_IRQHandler /* PLU interrupt */ - .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ - .long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */ - .long CASER_IRQHandler /* CASPER interrupt */ - .long PUF_IRQHandler /* PUF interrupt */ - .long PQ_IRQHandler /* PQ interrupt */ - .long DMA1_IRQHandler /* DMA1 interrupt */ - .long LSPI_HS_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ - - .size __Vectors, . - __Vectors - - .text - .thumb - -/* Reset Handler */ - .thumb_func - .align 2 - .globl Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -#ifndef __NO_SYSTEM_INIT - ldr r0,=SystemInit - blx r0 -#endif -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -#if 1 -/* Here are two copies of loop implemenations. First one favors code size - * and the second one favors performance. Default uses the first one. - * Change to "#if 0" to use the second one */ -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 -#else - subs r3, r2 - ble .LC1 -.LC0: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC0 -.LC1: -#endif - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.LC2: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC2 -#endif /* __STARTUP_CLEAR_BSS */ - -/* Add stack / heap initializaiton */ - movs r0, 0 - ldr r1, =__HeapBase - ldr r2, =__HeapLimit -.LC3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC3 - - ldr r1, =__StackLimit - ldr r2, =__StackTop -.LC4: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC4 -/*End of stack / heap initializaiton */ - cpsie i /* Unmask interrupts */ - -#ifndef __START -#define __START _start -#endif -#ifndef __ATOLLIC__ - ldr r0,=__START - blx r0 -#else - ldr r0,=__libc_init_array - blx r0 - ldr r0,=main - bx r0 -#endif - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - - .align 1 - .thumb_func - .weak WDT_BOD_IRQHandler - .type WDT_BOD_IRQHandler, %function -WDT_BOD_IRQHandler: - ldr r0,=WDT_BOD_DriverIRQHandler - bx r0 - .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak GINT0_IRQHandler - .type GINT0_IRQHandler, %function -GINT0_IRQHandler: - ldr r0,=GINT0_DriverIRQHandler - bx r0 - .size GINT0_IRQHandler, . - GINT0_IRQHandler - - .align 1 - .thumb_func - .weak GINT1_IRQHandler - .type GINT1_IRQHandler, %function -GINT1_IRQHandler: - ldr r0,=GINT1_DriverIRQHandler - bx r0 - .size GINT1_IRQHandler, . - GINT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak UTICK0_IRQHandler - .type UTICK0_IRQHandler, %function -UTICK0_IRQHandler: - ldr r0,=UTICK0_DriverIRQHandler - bx r0 - .size UTICK0_IRQHandler, . - UTICK0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER0_IRQHandler - .type CTIMER0_IRQHandler, %function -CTIMER0_IRQHandler: - ldr r0,=CTIMER0_DriverIRQHandler - bx r0 - .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER1_IRQHandler - .type CTIMER1_IRQHandler, %function -CTIMER1_IRQHandler: - ldr r0,=CTIMER1_DriverIRQHandler - bx r0 - .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER3_IRQHandler - .type CTIMER3_IRQHandler, %function -CTIMER3_IRQHandler: - ldr r0,=CTIMER3_DriverIRQHandler - bx r0 - .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM0_IRQHandler - .type FLEXCOMM0_IRQHandler, %function -FLEXCOMM0_IRQHandler: - ldr r0,=FLEXCOMM0_DriverIRQHandler - bx r0 - .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM1_IRQHandler - .type FLEXCOMM1_IRQHandler, %function -FLEXCOMM1_IRQHandler: - ldr r0,=FLEXCOMM1_DriverIRQHandler - bx r0 - .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM2_IRQHandler - .type FLEXCOMM2_IRQHandler, %function -FLEXCOMM2_IRQHandler: - ldr r0,=FLEXCOMM2_DriverIRQHandler - bx r0 - .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM3_IRQHandler - .type FLEXCOMM3_IRQHandler, %function -FLEXCOMM3_IRQHandler: - ldr r0,=FLEXCOMM3_DriverIRQHandler - bx r0 - .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM4_IRQHandler - .type FLEXCOMM4_IRQHandler, %function -FLEXCOMM4_IRQHandler: - ldr r0,=FLEXCOMM4_DriverIRQHandler - bx r0 - .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM5_IRQHandler - .type FLEXCOMM5_IRQHandler, %function -FLEXCOMM5_IRQHandler: - ldr r0,=FLEXCOMM5_DriverIRQHandler - bx r0 - .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM6_IRQHandler - .type FLEXCOMM6_IRQHandler, %function -FLEXCOMM6_IRQHandler: - ldr r0,=FLEXCOMM6_DriverIRQHandler - bx r0 - .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM7_IRQHandler - .type FLEXCOMM7_IRQHandler, %function -FLEXCOMM7_IRQHandler: - ldr r0,=FLEXCOMM7_DriverIRQHandler - bx r0 - .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_IRQHandler - .type ADC0_IRQHandler, %function -ADC0_IRQHandler: - ldr r0,=ADC0_DriverIRQHandler - bx r0 - .size ADC0_IRQHandler, . - ADC0_IRQHandler - - .align 1 - .thumb_func - .weak Reserved39_IRQHandler - .type Reserved39_IRQHandler, %function -Reserved39_IRQHandler: - ldr r0,=Reserved39_DriverIRQHandler - bx r0 - .size Reserved39_IRQHandler, . - Reserved39_IRQHandler - - .align 1 - .thumb_func - .weak ACMP_IRQHandler - .type ACMP_IRQHandler, %function -ACMP_IRQHandler: - ldr r0,=ACMP_DriverIRQHandler - bx r0 - .size ACMP_IRQHandler, . - ACMP_IRQHandler - - .align 1 - .thumb_func - .weak Reserved41_IRQHandler - .type Reserved41_IRQHandler, %function -Reserved41_IRQHandler: - ldr r0,=Reserved41_DriverIRQHandler - bx r0 - .size Reserved41_IRQHandler, . - Reserved41_IRQHandler - - .align 1 - .thumb_func - .weak Reserved42_IRQHandler - .type Reserved42_IRQHandler, %function -Reserved42_IRQHandler: - ldr r0,=Reserved42_DriverIRQHandler - bx r0 - .size Reserved42_IRQHandler, . - Reserved42_IRQHandler - - .align 1 - .thumb_func - .weak USB0_NEEDCLK_IRQHandler - .type USB0_NEEDCLK_IRQHandler, %function -USB0_NEEDCLK_IRQHandler: - ldr r0,=USB0_NEEDCLK_DriverIRQHandler - bx r0 - .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak USB0_IRQHandler - .type USB0_IRQHandler, %function -USB0_IRQHandler: - ldr r0,=USB0_DriverIRQHandler - bx r0 - .size USB0_IRQHandler, . - USB0_IRQHandler - - .align 1 - .thumb_func - .weak RTC_IRQHandler - .type RTC_IRQHandler, %function -RTC_IRQHandler: - ldr r0,=RTC_DriverIRQHandler - bx r0 - .size RTC_IRQHandler, . - RTC_IRQHandler - - .align 1 - .thumb_func - .weak Reserved46_IRQHandler - .type Reserved46_IRQHandler, %function -Reserved46_IRQHandler: - ldr r0,=Reserved46_DriverIRQHandler - bx r0 - .size Reserved46_IRQHandler, . - Reserved46_IRQHandler - - .align 1 - .thumb_func - .weak MAILBOX_IRQHandler - .type MAILBOX_IRQHandler, %function -MAILBOX_IRQHandler: - ldr r0,=MAILBOX_DriverIRQHandler - bx r0 - .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT4_IRQHandler - .type PIN_INT4_IRQHandler, %function -PIN_INT4_IRQHandler: - ldr r0,=PIN_INT4_DriverIRQHandler - bx r0 - .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT5_IRQHandler - .type PIN_INT5_IRQHandler, %function -PIN_INT5_IRQHandler: - ldr r0,=PIN_INT5_DriverIRQHandler - bx r0 - .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT6_IRQHandler - .type PIN_INT6_IRQHandler, %function -PIN_INT6_IRQHandler: - ldr r0,=PIN_INT6_DriverIRQHandler - bx r0 - .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT7_IRQHandler - .type PIN_INT7_IRQHandler, %function -PIN_INT7_IRQHandler: - ldr r0,=PIN_INT7_DriverIRQHandler - bx r0 - .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER2_IRQHandler - .type CTIMER2_IRQHandler, %function -CTIMER2_IRQHandler: - ldr r0,=CTIMER2_DriverIRQHandler - bx r0 - .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER4_IRQHandler - .type CTIMER4_IRQHandler, %function -CTIMER4_IRQHandler: - ldr r0,=CTIMER4_DriverIRQHandler - bx r0 - .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler - - .align 1 - .thumb_func - .weak OS_EVENT_IRQHandler - .type OS_EVENT_IRQHandler, %function -OS_EVENT_IRQHandler: - ldr r0,=OS_EVENT_DriverIRQHandler - bx r0 - .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler - - .align 1 - .thumb_func - .weak Reserved55_IRQHandler - .type Reserved55_IRQHandler, %function -Reserved55_IRQHandler: - ldr r0,=Reserved55_DriverIRQHandler - bx r0 - .size Reserved55_IRQHandler, . - Reserved55_IRQHandler - - .align 1 - .thumb_func - .weak Reserved56_IRQHandler - .type Reserved56_IRQHandler, %function -Reserved56_IRQHandler: - ldr r0,=Reserved56_DriverIRQHandler - bx r0 - .size Reserved56_IRQHandler, . - Reserved56_IRQHandler - - .align 1 - .thumb_func - .weak Reserved57_IRQHandler - .type Reserved57_IRQHandler, %function -Reserved57_IRQHandler: - ldr r0,=Reserved57_DriverIRQHandler - bx r0 - .size Reserved57_IRQHandler, . - Reserved57_IRQHandler - - .align 1 - .thumb_func - .weak SDIO_IRQHandler - .type SDIO_IRQHandler, %function -SDIO_IRQHandler: - ldr r0,=SDIO_DriverIRQHandler - bx r0 - .size SDIO_IRQHandler, . - SDIO_IRQHandler - - .align 1 - .thumb_func - .weak Reserved59_IRQHandler - .type Reserved59_IRQHandler, %function -Reserved59_IRQHandler: - ldr r0,=Reserved59_DriverIRQHandler - bx r0 - .size Reserved59_IRQHandler, . - Reserved59_IRQHandler - - .align 1 - .thumb_func - .weak Reserved60_IRQHandler - .type Reserved60_IRQHandler, %function -Reserved60_IRQHandler: - ldr r0,=Reserved60_DriverIRQHandler - bx r0 - .size Reserved60_IRQHandler, . - Reserved60_IRQHandler - - .align 1 - .thumb_func - .weak Reserved61_IRQHandler - .type Reserved61_IRQHandler, %function -Reserved61_IRQHandler: - ldr r0,=Reserved61_DriverIRQHandler - bx r0 - .size Reserved61_IRQHandler, . - Reserved61_IRQHandler - - .align 1 - .thumb_func - .weak USB1_UTMI_IRQHandler - .type USB1_UTMI_IRQHandler, %function -USB1_UTMI_IRQHandler: - ldr r0,=USB1_UTMI_DriverIRQHandler - bx r0 - .size USB1_UTMI_IRQHandler, . - USB1_UTMI_IRQHandler - - .align 1 - .thumb_func - .weak USB1_IRQHandler - .type USB1_IRQHandler, %function -USB1_IRQHandler: - ldr r0,=USB1_DriverIRQHandler - bx r0 - .size USB1_IRQHandler, . - USB1_IRQHandler - - .align 1 - .thumb_func - .weak USB1_NEEDCLK_IRQHandler - .type USB1_NEEDCLK_IRQHandler, %function -USB1_NEEDCLK_IRQHandler: - ldr r0,=USB1_NEEDCLK_DriverIRQHandler - bx r0 - .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak SEC_HYPERVISOR_CALL_IRQHandler - .type SEC_HYPERVISOR_CALL_IRQHandler, %function -SEC_HYPERVISOR_CALL_IRQHandler: - ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler - bx r0 - .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ0_IRQHandler - .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function -SEC_GPIO_INT0_IRQ0_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak SEC_GPIO_INT0_IRQ1_IRQHandler - .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function -SEC_GPIO_INT0_IRQ1_IRQHandler: - ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler - bx r0 - .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak PLU_IRQHandler - .type PLU_IRQHandler, %function -PLU_IRQHandler: - ldr r0,=PLU_DriverIRQHandler - bx r0 - .size PLU_IRQHandler, . - PLU_IRQHandler - - .align 1 - .thumb_func - .weak SEC_VIO_IRQHandler - .type SEC_VIO_IRQHandler, %function -SEC_VIO_IRQHandler: - ldr r0,=SEC_VIO_DriverIRQHandler - bx r0 - .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler - - .align 1 - .thumb_func - .weak HASHCRYPT_IRQHandler - .type HASHCRYPT_IRQHandler, %function -HASHCRYPT_IRQHandler: - ldr r0,=HASHCRYPT_DriverIRQHandler - bx r0 - .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler - - .align 1 - .thumb_func - .weak CASER_IRQHandler - .type CASER_IRQHandler, %function -CASER_IRQHandler: - ldr r0,=CASER_DriverIRQHandler - bx r0 - .size CASER_IRQHandler, . - CASER_IRQHandler - - .align 1 - .thumb_func - .weak PUF_IRQHandler - .type PUF_IRQHandler, %function -PUF_IRQHandler: - ldr r0,=PUF_DriverIRQHandler - bx r0 - .size PUF_IRQHandler, . - PUF_IRQHandler - - .align 1 - .thumb_func - .weak PQ_IRQHandler - .type PQ_IRQHandler, %function -PQ_IRQHandler: - ldr r0,=PQ_DriverIRQHandler - bx r0 - .size PQ_IRQHandler, . - PQ_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_IRQHandler - .type DMA1_IRQHandler, %function -DMA1_IRQHandler: - ldr r0,=DMA1_DriverIRQHandler - bx r0 - .size DMA1_IRQHandler, . - DMA1_IRQHandler - - .align 1 - .thumb_func - .weak LSPI_HS_IRQHandler - .type LSPI_HS_IRQHandler, %function -LSPI_HS_IRQHandler: - ldr r0,=LSPI_HS_DriverIRQHandler - bx r0 - .size LSPI_HS_IRQHandler, . - LSPI_HS_IRQHandler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm -/* Exception Handlers */ - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler DebugMon_Handler - def_irq_handler WDT_BOD_DriverIRQHandler - def_irq_handler DMA0_DriverIRQHandler - def_irq_handler GINT0_DriverIRQHandler - def_irq_handler GINT1_DriverIRQHandler - def_irq_handler PIN_INT0_DriverIRQHandler - def_irq_handler PIN_INT1_DriverIRQHandler - def_irq_handler PIN_INT2_DriverIRQHandler - def_irq_handler PIN_INT3_DriverIRQHandler - def_irq_handler UTICK0_DriverIRQHandler - def_irq_handler MRT0_DriverIRQHandler - def_irq_handler CTIMER0_DriverIRQHandler - def_irq_handler CTIMER1_DriverIRQHandler - def_irq_handler SCT0_DriverIRQHandler - def_irq_handler CTIMER3_DriverIRQHandler - def_irq_handler FLEXCOMM0_DriverIRQHandler - def_irq_handler FLEXCOMM1_DriverIRQHandler - def_irq_handler FLEXCOMM2_DriverIRQHandler - def_irq_handler FLEXCOMM3_DriverIRQHandler - def_irq_handler FLEXCOMM4_DriverIRQHandler - def_irq_handler FLEXCOMM5_DriverIRQHandler - def_irq_handler FLEXCOMM6_DriverIRQHandler - def_irq_handler FLEXCOMM7_DriverIRQHandler - def_irq_handler ADC0_DriverIRQHandler - def_irq_handler Reserved39_DriverIRQHandler - def_irq_handler ACMP_DriverIRQHandler - def_irq_handler Reserved41_DriverIRQHandler - def_irq_handler Reserved42_DriverIRQHandler - def_irq_handler USB0_NEEDCLK_DriverIRQHandler - def_irq_handler USB0_DriverIRQHandler - def_irq_handler RTC_DriverIRQHandler - def_irq_handler Reserved46_DriverIRQHandler - def_irq_handler MAILBOX_DriverIRQHandler - def_irq_handler PIN_INT4_DriverIRQHandler - def_irq_handler PIN_INT5_DriverIRQHandler - def_irq_handler PIN_INT6_DriverIRQHandler - def_irq_handler PIN_INT7_DriverIRQHandler - def_irq_handler CTIMER2_DriverIRQHandler - def_irq_handler CTIMER4_DriverIRQHandler - def_irq_handler OS_EVENT_DriverIRQHandler - def_irq_handler Reserved55_DriverIRQHandler - def_irq_handler Reserved56_DriverIRQHandler - def_irq_handler Reserved57_DriverIRQHandler - def_irq_handler SDIO_DriverIRQHandler - def_irq_handler Reserved59_DriverIRQHandler - def_irq_handler Reserved60_DriverIRQHandler - def_irq_handler Reserved61_DriverIRQHandler - def_irq_handler USB1_UTMI_DriverIRQHandler - def_irq_handler USB1_DriverIRQHandler - def_irq_handler USB1_NEEDCLK_DriverIRQHandler - def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler - def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler - def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler - def_irq_handler PLU_DriverIRQHandler - def_irq_handler SEC_VIO_DriverIRQHandler - def_irq_handler HASHCRYPT_DriverIRQHandler - def_irq_handler CASER_DriverIRQHandler - def_irq_handler PUF_DriverIRQHandler - def_irq_handler PQ_DriverIRQHandler - def_irq_handler DMA1_DriverIRQHandler - def_irq_handler LSPI_HS_DriverIRQHandler - - .end diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_IAR/LPC55S69_cm33_core0_flash.icf b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_IAR/LPC55S69_cm33_core0_flash.icf deleted file mode 100644 index e7a3506845..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_IAR/LPC55S69_cm33_core0_flash.icf +++ /dev/null @@ -1,156 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol NS_CODE_START = 0x00030000; -define symbol NS_CODE_SIZE = 0x00068000; -define symbol NS_DATA_START = 0x20022000; -define symbol NS_DATA_SIZE = 0x00022000; - -define symbol __ram_vector_table__ = 1; - -if (!isdefinedsymbol(MBED_ROM_START)) { - define symbol MBED_ROM_START = NS_CODE_START; -} - -if (!isdefinedsymbol(MBED_APP_START)) { - define symbol MBED_APP_START = MBED_ROM_START; -} - -if (!isdefinedsymbol(MBED_ROM_SIZE)) { - define symbol MBED_ROM_SIZE = NS_CODE_SIZE; -} - -if (!isdefinedsymbol(MBED_APP_SIZE)) { - define symbol MBED_APP_SIZE = MBED_ROM_SIZE; -} - -if (!isdefinedsymbol(MBED_RAM_START)) { - define symbol MBED_RAM_START = NS_DATA_START; -} - -if (!isdefinedsymbol(MBED_RAM_SIZE)) { - define symbol MBED_RAM_SIZE = NS_DATA_SIZE; -} - -if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; -} - -define symbol __stack_size__ = MBED_CONF_TARGET_BOOT_STACK_SIZE; -define symbol __heap_size__ = 0x4000; - -define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000200 : 0; -define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000001FF : 0; - -/* USB BDT size */ -define symbol usb_bdt_size = 0x0; - -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -if (!isdefinedsymbol(NVIC_INTERRUPT_NUM)) { - define symbol NVIC_INTERRUPT_NUM = 60; -} - -if (!isdefinedsymbol(EXCEPTION_VECT_NUM)) { - define symbol EXCEPTION_VECT_NUM = 16; -} - -if (!isdefinedsymbol(MEMORY_ADDR_SIZE_IN_BYTE)) { - define symbol MEMORY_ADDR_SIZE_IN_BYTE = 4; -} - -if (!isdefinedsymbol(MBED_INTERRUPTS_SIZE)) { - define symbol MBED_INTERRUPTS_SIZE = ((NVIC_INTERRUPT_NUM + EXCEPTION_VECT_NUM) * MEMORY_ADDR_SIZE_IN_BYTE); -} - -define symbol m_interrupts_start = MBED_APP_START; -define symbol m_interrupts_end = (MBED_APP_START + (MBED_INTERRUPTS_SIZE - 1)); - -define symbol m_text_start = (MBED_APP_START + MBED_INTERRUPTS_SIZE); -define symbol m_text_end = (MBED_APP_START + MBED_APP_SIZE - 1); - -define symbol m_interrupts_ram_start = MBED_RAM_START; -define symbol m_interrupts_ram_end = (MBED_RAM_START + __ram_vector_table_size__ - 1); - -define symbol m_data_start = (m_interrupts_ram_start + __ram_vector_table_size__); -define symbol m_data_end = (MBED_RAM_START + MBED_RAM_SIZE - 1); - -define symbol m_usb_sram_start = 0x40100000; -define symbol m_usb_sram_end = 0x00004000; - - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; - -define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with expanding size, alignment = 8, minimum size = __heap_size__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -/* regions for USB */ -define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; -define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; -place in USB_BDT_region { section m_usb_bdt }; -place in USB_SRAM_region { section m_usb_global }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -place in m_interrupts_ram_region { section m_interrupts_ram }; - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_IAR/startup_LPC55S69_cm33_core0.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_IAR/startup_LPC55S69_cm33_core0.S deleted file mode 100644 index 8fd1d2ddc0..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_IAR/startup_LPC55S69_cm33_core0.S +++ /dev/null @@ -1,622 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC55S69_cm33_core0.s -; * @purpose: CMSIS Cortex-M33 Core Device Startup File -; * LPC55S69_cm33_core0 -; * @version: 1.0 -; * @date: 2018-8-22 -; *---------------------------------------------------------------------------- -; * -; Copyright 1997-2016 Freescale Semiconductor, Inc. -; Copyright 2016-2019 NXP -; All rights reserved. -; -; SPDX-License-Identifier: BSD-3-Clause -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt - DCD DMA0_IRQHandler ; DMA0 controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD ADC0_IRQHandler ; ADC0 - DCD Reserved39_IRQHandler ; Reserved interrupt - DCD ACMP_IRQHandler ; ACMP interrupts - DCD Reserved41_IRQHandler ; Reserved interrupt - DCD Reserved42_IRQHandler ; Reserved interrupt - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD Reserved46_IRQHandler ; Reserved interrupt - DCD MAILBOX_IRQHandler ; WAKEUP,Mailbox interrupt (present on selected devices) - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD OS_EVENT_IRQHandler ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts - DCD Reserved55_IRQHandler ; Reserved interrupt - DCD Reserved56_IRQHandler ; Reserved interrupt - DCD Reserved57_IRQHandler ; Reserved interrupt - DCD SDIO_IRQHandler ; SD/MMC - DCD Reserved59_IRQHandler ; Reserved interrupt - DCD Reserved60_IRQHandler ; Reserved interrupt - DCD Reserved61_IRQHandler ; Reserved interrupt - DCD USB1_UTMI_IRQHandler ; USB1_UTMI - DCD USB1_IRQHandler ; USB1 interrupt - DCD USB1_NEEDCLK_IRQHandler ; USB1 activity - DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt - DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt - DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt - DCD PLU_IRQHandler ; PLU interrupt - DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt - DCD HASHCRYPT_IRQHandler ; HASHCRYPT interrupt - DCD CASER_IRQHandler ; CASPER interrupt - DCD PUF_IRQHandler ; PUF interrupt - DCD PQ_IRQHandler ; PQ interrupt - DCD DMA1_IRQHandler ; DMA1 interrupt - DCD LSPI_HS_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM) -__Vectors_End - - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =sfb(CSTACK) - MSR MSPLIM, R0 - LDR R0, =SystemInit - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK WDT_BOD_IRQHandler - PUBWEAK WDT_BOD_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -WDT_BOD_IRQHandler - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT0_IRQHandler - LDR R0, =GINT0_DriverIRQHandler - BX R0 - PUBWEAK GINT1_IRQHandler - PUBWEAK GINT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT1_IRQHandler - LDR R0, =GINT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT0_IRQHandler - PUBWEAK PIN_INT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT0_IRQHandler - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT1_IRQHandler - PUBWEAK PIN_INT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT1_IRQHandler - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT2_IRQHandler - PUBWEAK PIN_INT2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT2_IRQHandler - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT3_IRQHandler - PUBWEAK PIN_INT3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT3_IRQHandler - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - PUBWEAK UTICK0_IRQHandler - PUBWEAK UTICK0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UTICK0_IRQHandler - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - PUBWEAK MRT0_IRQHandler - PUBWEAK MRT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -MRT0_IRQHandler - LDR R0, =MRT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER0_IRQHandler - PUBWEAK CTIMER0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER0_IRQHandler - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER1_IRQHandler - PUBWEAK CTIMER1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER1_IRQHandler - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - PUBWEAK SCT0_IRQHandler - PUBWEAK SCT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SCT0_IRQHandler - LDR R0, =SCT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER3_IRQHandler - PUBWEAK CTIMER3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER3_IRQHandler - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM0_IRQHandler - PUBWEAK FLEXCOMM0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM0_IRQHandler - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM1_IRQHandler - PUBWEAK FLEXCOMM1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM1_IRQHandler - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM2_IRQHandler - PUBWEAK FLEXCOMM2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM2_IRQHandler - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM3_IRQHandler - PUBWEAK FLEXCOMM3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM3_IRQHandler - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM4_IRQHandler - PUBWEAK FLEXCOMM4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM4_IRQHandler - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM5_IRQHandler - PUBWEAK FLEXCOMM5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM5_IRQHandler - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM6_IRQHandler - PUBWEAK FLEXCOMM6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM6_IRQHandler - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM7_IRQHandler - PUBWEAK FLEXCOMM7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM7_IRQHandler - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - PUBWEAK ADC0_IRQHandler - PUBWEAK ADC0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_IRQHandler - LDR R0, =ADC0_DriverIRQHandler - BX R0 - PUBWEAK Reserved39_IRQHandler - PUBWEAK Reserved39_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved39_IRQHandler - LDR R0, =Reserved39_DriverIRQHandler - BX R0 - PUBWEAK ACMP_IRQHandler - PUBWEAK ACMP_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ACMP_IRQHandler - LDR R0, =ACMP_DriverIRQHandler - BX R0 - PUBWEAK Reserved41_IRQHandler - PUBWEAK Reserved41_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved41_IRQHandler - LDR R0, =Reserved41_DriverIRQHandler - BX R0 - PUBWEAK Reserved42_IRQHandler - PUBWEAK Reserved42_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved42_IRQHandler - LDR R0, =Reserved42_DriverIRQHandler - BX R0 - PUBWEAK USB0_NEEDCLK_IRQHandler - PUBWEAK USB0_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_NEEDCLK_IRQHandler - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK USB0_IRQHandler - PUBWEAK USB0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_IRQHandler - LDR R0, =USB0_DriverIRQHandler - BX R0 - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -RTC_IRQHandler - LDR R0, =RTC_DriverIRQHandler - BX R0 - PUBWEAK Reserved46_IRQHandler - PUBWEAK Reserved46_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved46_IRQHandler - LDR R0, =Reserved46_DriverIRQHandler - BX R0 - PUBWEAK MAILBOX_IRQHandler - PUBWEAK MAILBOX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -MAILBOX_IRQHandler - LDR R0, =MAILBOX_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT4_IRQHandler - PUBWEAK PIN_INT4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT4_IRQHandler - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT5_IRQHandler - PUBWEAK PIN_INT5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT5_IRQHandler - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT6_IRQHandler - PUBWEAK PIN_INT6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT6_IRQHandler - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT7_IRQHandler - PUBWEAK PIN_INT7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT7_IRQHandler - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - PUBWEAK CTIMER2_IRQHandler - PUBWEAK CTIMER2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER2_IRQHandler - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - PUBWEAK CTIMER4_IRQHandler - PUBWEAK CTIMER4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER4_IRQHandler - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - PUBWEAK OS_EVENT_IRQHandler - PUBWEAK OS_EVENT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -OS_EVENT_IRQHandler - LDR R0, =OS_EVENT_DriverIRQHandler - BX R0 - PUBWEAK Reserved55_IRQHandler - PUBWEAK Reserved55_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved55_IRQHandler - LDR R0, =Reserved55_DriverIRQHandler - BX R0 - PUBWEAK Reserved56_IRQHandler - PUBWEAK Reserved56_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved56_IRQHandler - LDR R0, =Reserved56_DriverIRQHandler - BX R0 - PUBWEAK Reserved57_IRQHandler - PUBWEAK Reserved57_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved57_IRQHandler - LDR R0, =Reserved57_DriverIRQHandler - BX R0 - PUBWEAK SDIO_IRQHandler - PUBWEAK SDIO_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SDIO_IRQHandler - LDR R0, =SDIO_DriverIRQHandler - BX R0 - PUBWEAK Reserved59_IRQHandler - PUBWEAK Reserved59_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved59_IRQHandler - LDR R0, =Reserved59_DriverIRQHandler - BX R0 - PUBWEAK Reserved60_IRQHandler - PUBWEAK Reserved60_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved60_IRQHandler - LDR R0, =Reserved60_DriverIRQHandler - BX R0 - PUBWEAK Reserved61_IRQHandler - PUBWEAK Reserved61_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved61_IRQHandler - LDR R0, =Reserved61_DriverIRQHandler - BX R0 - PUBWEAK USB1_UTMI_IRQHandler - PUBWEAK USB1_UTMI_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_UTMI_IRQHandler - LDR R0, =USB1_UTMI_DriverIRQHandler - BX R0 - PUBWEAK USB1_IRQHandler - PUBWEAK USB1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_IRQHandler - LDR R0, =USB1_DriverIRQHandler - BX R0 - PUBWEAK USB1_NEEDCLK_IRQHandler - PUBWEAK USB1_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_NEEDCLK_IRQHandler - LDR R0, =USB1_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK SEC_HYPERVISOR_CALL_IRQHandler - PUBWEAK SEC_HYPERVISOR_CALL_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_HYPERVISOR_CALL_IRQHandler - LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler - BX R0 - PUBWEAK SEC_GPIO_INT0_IRQ0_IRQHandler - PUBWEAK SEC_GPIO_INT0_IRQ0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_GPIO_INT0_IRQ0_IRQHandler - LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler - BX R0 - PUBWEAK SEC_GPIO_INT0_IRQ1_IRQHandler - PUBWEAK SEC_GPIO_INT0_IRQ1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_GPIO_INT0_IRQ1_IRQHandler - LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler - BX R0 - PUBWEAK PLU_IRQHandler - PUBWEAK PLU_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PLU_IRQHandler - LDR R0, =PLU_DriverIRQHandler - BX R0 - PUBWEAK SEC_VIO_IRQHandler - PUBWEAK SEC_VIO_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SEC_VIO_IRQHandler - LDR R0, =SEC_VIO_DriverIRQHandler - BX R0 - PUBWEAK HASHCRYPT_IRQHandler - PUBWEAK HASHCRYPT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -HASHCRYPT_IRQHandler - LDR R0, =HASHCRYPT_DriverIRQHandler - BX R0 - PUBWEAK CASER_IRQHandler - PUBWEAK CASER_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CASER_IRQHandler - LDR R0, =CASER_DriverIRQHandler - BX R0 - PUBWEAK PUF_IRQHandler - PUBWEAK PUF_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PUF_IRQHandler - LDR R0, =PUF_DriverIRQHandler - BX R0 - PUBWEAK PQ_IRQHandler - PUBWEAK PQ_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PQ_IRQHandler - LDR R0, =PQ_DriverIRQHandler - BX R0 - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA1_IRQHandler - LDR R0, =DMA1_DriverIRQHandler - BX R0 - PUBWEAK LSPI_HS_IRQHandler - PUBWEAK LSPI_HS_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LSPI_HS_IRQHandler - LDR R0, =LSPI_HS_DriverIRQHandler - BX R0 -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_DriverIRQHandler -Reserved39_DriverIRQHandler -ACMP_DriverIRQHandler -Reserved41_DriverIRQHandler -Reserved42_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -Reserved46_DriverIRQHandler -MAILBOX_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -OS_EVENT_DriverIRQHandler -Reserved55_DriverIRQHandler -Reserved56_DriverIRQHandler -Reserved57_DriverIRQHandler -SDIO_DriverIRQHandler -Reserved59_DriverIRQHandler -Reserved60_DriverIRQHandler -Reserved61_DriverIRQHandler -USB1_UTMI_DriverIRQHandler -USB1_DriverIRQHandler -USB1_NEEDCLK_DriverIRQHandler -SEC_HYPERVISOR_CALL_DriverIRQHandler -SEC_GPIO_INT0_IRQ0_DriverIRQHandler -SEC_GPIO_INT0_IRQ1_DriverIRQHandler -PLU_DriverIRQHandler -SEC_VIO_DriverIRQHandler -HASHCRYPT_DriverIRQHandler -CASER_DriverIRQHandler -PUF_DriverIRQHandler -PQ_DriverIRQHandler -DMA1_DriverIRQHandler -LSPI_HS_DriverIRQHandler -DefaultISR - B . - - END diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/cmsis_nvic.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/cmsis_nvic.h deleted file mode 100644 index fb5fdf9db4..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/cmsis_nvic.h +++ /dev/null @@ -1,46 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -extern uint32_t Image$$VECTOR_RAM$$Base[]; -#define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#else -extern uint32_t __VECTOR_RAM[]; -#endif - -/* Symbols defined by the linker script */ -#define NVIC_NUM_VECTORS (16 + 60) // CORE + MCU Peripherals -#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM - -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/cmsis_nvic_virtual.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/cmsis_nvic_virtual.h deleted file mode 100644 index ae4bc530bc..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/cmsis_nvic_virtual.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2018 Arm Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "cmsis.h" - -#ifndef NVIC_VIRTUAL_H -#define NVIC_VIRTUAL_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* NVIC functions */ -#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping -#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#if MBED_CONF_PSA_PRESENT -#define NVIC_SystemReset __NVIC_TFMSystemReset -#else -#define NVIC_SystemReset __NVIC_SystemReset -#endif // MBED_CONF_PSA_PRESENT - - -#if MBED_CONF_PSA_PRESENT -/** - * \brief Overriding the default CMSIS system reset implementation by calling - * secure TFM service. - * - */ -void __NVIC_TFMSystemReset(void); - -#endif // MBED_CONF_PSA_PRESENT - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/LICENSE-permissive-binary-license-1.0.txt b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/LICENSE-permissive-binary-license-1.0.txt deleted file mode 100644 index 8acf76a4b1..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/LICENSE-permissive-binary-license-1.0.txt +++ /dev/null @@ -1,49 +0,0 @@ -Permissive Binary License - -Version 1.0, December 2018 - -Redistribution. Redistribution and use in binary form, without -modification, are permitted provided that the following conditions are -met: - -1) Redistributions must reproduce the above copyright notice and the - following disclaimer in the documentation and/or other materials - provided with the distribution. - -2) Unless to the extent explicitly permitted by law, no reverse - engineering, decompilation, or disassembly of this software is - permitted. - -3) Redistribution as part of a software development kit must include the - accompanying file named DEPENDENCIES and any dependencies listed in - that file. - -4) Neither the name of the copyright holder nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - -Limited patent license. The copyright holders (and contributors) grant a -worldwide, non-exclusive, no-charge, royalty-free patent license to -make, have made, use, offer to sell, sell, import, and otherwise -transfer this software, where such license applies only to those patent -claims licensable by the copyright holders (and contributors) that are -necessarily infringed by this software. This patent license shall not -apply to any combinations that include this software. No hardware is -licensed hereunder. - -If you institute patent litigation against any entity (including a -cross-claim or counterclaim in a lawsuit) alleging that the software -itself infringes your patent(s), then your rights granted under this -license shall terminate as of the date such litigation is filed. - -DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND -CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT -NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/README.md b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/README.md deleted file mode 100644 index fc1711088f..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/README.md +++ /dev/null @@ -1,39 +0,0 @@ -# LPC55S69_NS prebuilt secure binaries - -This directory tree contains Secure images released under Permissive Binary License. - -Built by mbed-cli using ARM Compiler 6.10.1 - -These images were compiled by the following command: - -## tfm.bin - -```sh -mbed compile -t ARMC6 -m LPC55S69_S --app-config mbed-os/tools/psa/tfm/mbed_app.json --profile release -``` - -## spm_smoke.bin - -```sh -mbed test --compile -t ARMC6 -m LPC55S69_S --app-config mbed-os/tools/psa/tfm/mbed_app.json -n mbed-os-tests-psa-spm_smoke -DUSE_PSA_TEST_PARTITIONS -DUSE_SMOKE_TESTS_PART1 --profile release -``` - -## spm_client.bin - -```sh -mbed test --compile -t ARMC6 -m LPC55S69_S --app-config mbed-os/tools/psa/tfm/mbed_app.json -n mbed-os-tests-psa-spm_client -DUSE_PSA_TEST_PARTITIONS -DUSE_CLIENT_TESTS_PART1 --profile release -``` - -## spm_server.bin - -```sh -mbed test --compile -t ARMC6 -m LPC55S69_S --app-config mbed-os/tools/psa/tfm/mbed_app.json -n mbed-os-tests-psa-spm_server -DUSE_PSA_TEST_PARTITIONS -DUSE_SERVER_TESTS_PART1 -DUSE_SERVER_TESTS_PART2 --profile release -``` - -## crypto_access_control.bin - -```sh -mbed test --compile -t ARMC6 -m LPC55S69_S --app-config mbed-os/tools/psa/tfm/mbed_app.json -n mbed-os-tests-psa-crypto_access_control -DUSE_PSA_TEST_PARTITIONS -DUSE_CRYPTO_ACL_TEST --profile release -``` - -To update the prebuilt binaries run the previous commands. diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/cmse_lib.o b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/cmse_lib.o deleted file mode 100644 index 2f34372c88431f95ebc440a40be64a692d5ad463..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 768 zcma))ze)o^5XSdn6a|Z*rJ#*Pu&}Zf31T1+3rQMn&h>7R9Byvo?nX_cq!er{EmQgc zK7+5|Tc}T<-zIlv5)d31W`5s%yL*53{-|CJfcfpz9UUQqp!pLo&|Vp3!Y1yJ1hZDU*^kaal`7S_&;i zP8;D`uvr;ild*|TQB$I++`=|=qs`@ChDfI=cA8%oDUCDcHjAWExz;=j8#td1b?WHW zg$)6vu4OzU)bP}q&=^=p-HESih>msKSF_72O6h1`$9Md1ti#A}mcMVG$OWYTA4Oyd cxq|ds9@`jhFq?bd4~1*1$p8QV diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/crypto_access_control.bin b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/crypto_access_control.bin deleted file mode 100644 index 3333c906af6f17873a002870665f33e8b28ab8f0..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 163520 zcmd?SeS8$v-8X#B?CkFB=4}!JY+iubB*5~%AZkRcn@yN(03{$;TJ>^+VrK)$O0`DY z>tX|_!DVn6k)e?X&Nobf4$-xp^VSt9GkuMFYM`-u}q zH6IWRYTfvO6WiQ>JLa#(1eKC9GLcLY=Q%DO9^UKqPg-FG?N2+`qYvHSb5cV0&NZvN%xdr;@)`)^-~ z$6xI~NSywT)XPI;75x}hthQZlTWEpT z5SgkN<=iUjbtn}DJKe>hwO)T$o#OM_6`{(3`OrrS$GkUc}*zqPZZ9-^oV)F$< z!q{JyFkbvOS6*mL<(|Z*3mkIZiAl!sp^}7gsH!iMm#)0Ik6*l`FTctby0aLi1td$e z`<|#F^O|F1NImS{AiAev$EL`}l0gWS(dgWLxh zgN6^fi|&bL(t|x2GACEa9=YqR_VZC4C`XX!?(-zjb+*{WXiv@?e2v&)*u}LFZPc)M z;5I#furzb-b6_opN)vRPQR5R;?R<@kDwC0NVfv z%m;&zr0+sx%0`(^HHIAx0TVgV=Od+@N=uFEEyYi{xufc>#4!+Q^L=jXE^MoF)Z3~Y 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z0d)n`6;M||T>*6k)D=)yKwSZK1=JN#S3q3>bp_NFP**@*0d)n`6;M||T>*6k{y(a~ z#P<{5r{`2pEbbSV^ope7%Uw(Q>qUKbPEdjvpPjR-r2l!U__B9Nzpki%o>M&ii<|++ R#Pu(7_LcOC>> ------------------ -; * -; *****************************************************************************/ - - - ;PRESERVE8 - ;THUMB - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| - ;IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -;__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack -;__Vectors DCD __initial_msp ; Top of Stack -__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler - DCD SecureFault_Handler -__vector_table_0x1c - DCD 0 ; Checksum of the first 7 words - ;DCD 0 - DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot - DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt - DCD DMA0_IRQHandler ; DMA0 controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) - DCD ADC0_IRQHandler ; ADC0 - DCD Reserved39_IRQHandler ; Reserved interrupt - DCD ACMP_CAPT0_IRQHandler ; ACMP and CAPT0 interrupts - DCD Reserved41_IRQHandler ; Reserved interrupt - DCD Reserved42_IRQHandler ; Reserved interrupt - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD EZH_ARCH_B0_IRQHandler ; EZH_ARCH_B0 - DCD MAILBOX_IRQHandler ; WAKEUP,Mailbox interrupt (present on selected devices) - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD OS_EVENT_IRQHandler ; OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts - DCD Reserved55_IRQHandler ; Reserved interrupt - DCD Reserved56_IRQHandler ; Reserved interrupt - DCD Reserved57_IRQHandler ; Reserved interrupt - DCD SDIO_IRQHandler ; SD/MMC - DCD Reserved59_IRQHandler ; Reserved interrupt - DCD Reserved60_IRQHandler ; Reserved interrupt - DCD Reserved61_IRQHandler ; Reserved interrupt - DCD USB1_UTMI_IRQHandler ; USB1_UTMI - DCD USB1_IRQHandler ; USB1 interrupt - DCD USB1_NEEDCLK_IRQHandler ; USB1 activity - DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt - DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt - DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt - DCD PLU_IRQHandler ; PLU interrupt - DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt - DCD HASHCRYPT_IRQHandler ; HASHCRYPT interrupt - DCD CASER_IRQHandler ; CASPER interrupt - DCD PUF_IRQHandler ; PUF interrupt - DCD PQ_IRQHandler ; PQ interrupt - DCD DMA1_IRQHandler ; DMA1 interrupt - DCD LSPI_HS_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM) - DCD PVTVF0_AMBER_IRQHandler ; PVT interrupts - DCD PVTVF0_RED_IRQHandler ; PVT interrupts - DCD PVTVF1_AMBER_IRQHandler ; PVT interrupts - DCD PVTVF1_RED_IRQHandler ; PVT interrupts - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - - AREA |.text|, CODE, READONLY - -; Reset Handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - ;IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| - - CPSID I ; Mask interrupts - ;LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Base| - ;MSR MSPLIM, R0 - LDR R0, =SystemInit - BLX R0 - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 - ;CPSIE I ; Unmask interrupts - LDR R0, =__main - BX R0 - ENDP -End_Of_Main - B . - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler \ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP - -SecureFault_Handler PROC - EXPORT SecureFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -WDT_BOD_IRQHandler\ - PROC - EXPORT WDT_BOD_IRQHandler [WEAK] - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - ENDP - -DMA0_IRQHandler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - LDR R0, =DMA0_DriverIRQHandler - BX R0 - ENDP - -GINT0_IRQHandler\ - PROC - EXPORT GINT0_IRQHandler [WEAK] - LDR R0, =GINT0_DriverIRQHandler - BX R0 - ENDP - -GINT1_IRQHandler\ - PROC - EXPORT GINT1_IRQHandler [WEAK] - LDR R0, =GINT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT0_IRQHandler\ - PROC - EXPORT PIN_INT0_IRQHandler [WEAK] - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - ENDP - -PIN_INT1_IRQHandler\ - PROC - EXPORT PIN_INT1_IRQHandler [WEAK] - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT2_IRQHandler\ - PROC - EXPORT PIN_INT2_IRQHandler [WEAK] - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - ENDP - -PIN_INT3_IRQHandler\ - PROC - EXPORT PIN_INT3_IRQHandler [WEAK] - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - ENDP - -UTICK0_IRQHandler\ - PROC - EXPORT UTICK0_IRQHandler [WEAK] - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - ENDP - -MRT0_IRQHandler\ - PROC - EXPORT MRT0_IRQHandler [WEAK] - LDR R0, =MRT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER0_IRQHandler\ - PROC - EXPORT CTIMER0_IRQHandler [WEAK] - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - ENDP - -CTIMER1_IRQHandler\ - PROC - EXPORT CTIMER1_IRQHandler [WEAK] - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - ENDP - -SCT0_IRQHandler\ - PROC - EXPORT SCT0_IRQHandler [WEAK] - LDR R0, =SCT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER3_IRQHandler\ - PROC - EXPORT CTIMER3_IRQHandler [WEAK] - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM0_IRQHandler\ - PROC - EXPORT FLEXCOMM0_IRQHandler [WEAK] - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM1_IRQHandler\ - PROC - EXPORT FLEXCOMM1_IRQHandler [WEAK] - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM2_IRQHandler\ - PROC - EXPORT FLEXCOMM2_IRQHandler [WEAK] - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM3_IRQHandler\ - PROC - EXPORT FLEXCOMM3_IRQHandler [WEAK] - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM4_IRQHandler\ - PROC - EXPORT FLEXCOMM4_IRQHandler [WEAK] - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM5_IRQHandler\ - PROC - EXPORT FLEXCOMM5_IRQHandler [WEAK] - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM6_IRQHandler\ - PROC - EXPORT FLEXCOMM6_IRQHandler [WEAK] - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM7_IRQHandler\ - PROC - EXPORT FLEXCOMM7_IRQHandler [WEAK] - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - ENDP - -ADC0_IRQHandler\ - PROC - EXPORT ADC0_IRQHandler [WEAK] - LDR R0, =ADC0_DriverIRQHandler - BX R0 - ENDP - -Reserved39_IRQHandler\ - PROC - EXPORT Reserved39_IRQHandler [WEAK] - LDR R0, =Reserved39_DriverIRQHandler - BX R0 - ENDP - -ACMP_CAPT0_IRQHandler\ - PROC - EXPORT ACMP_CAPT0_IRQHandler [WEAK] - LDR R0, =ACMP_CAPT0_DriverIRQHandler - BX R0 - ENDP - -Reserved41_IRQHandler\ - PROC - EXPORT Reserved41_IRQHandler [WEAK] - LDR R0, =Reserved41_DriverIRQHandler - BX R0 - ENDP - -Reserved42_IRQHandler\ - PROC - EXPORT Reserved42_IRQHandler [WEAK] - LDR R0, =Reserved42_DriverIRQHandler - BX R0 - ENDP - -USB0_NEEDCLK_IRQHandler\ - PROC - EXPORT USB0_NEEDCLK_IRQHandler [WEAK] - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - ENDP - -USB0_IRQHandler\ - PROC - EXPORT USB0_IRQHandler [WEAK] - LDR R0, =USB0_DriverIRQHandler - BX R0 - ENDP - -RTC_IRQHandler\ - PROC - EXPORT RTC_IRQHandler [WEAK] - LDR R0, =RTC_DriverIRQHandler - BX R0 - ENDP - -EZH_ARCH_B0_IRQHandler\ - PROC - EXPORT EZH_ARCH_B0_IRQHandler [WEAK] - LDR R0, =EZH_ARCH_B0_DriverIRQHandler - BX R0 - ENDP - -MAILBOX_IRQHandler\ - PROC - EXPORT MAILBOX_IRQHandler [WEAK] - LDR R0, =MAILBOX_DriverIRQHandler - BX R0 - ENDP - -PIN_INT4_IRQHandler\ - PROC - EXPORT PIN_INT4_IRQHandler [WEAK] - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - ENDP - -PIN_INT5_IRQHandler\ - PROC - EXPORT PIN_INT5_IRQHandler [WEAK] - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - ENDP - -PIN_INT6_IRQHandler\ - PROC - EXPORT PIN_INT6_IRQHandler [WEAK] - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - ENDP - -PIN_INT7_IRQHandler\ - PROC - EXPORT PIN_INT7_IRQHandler [WEAK] - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - ENDP - -CTIMER2_IRQHandler\ - PROC - EXPORT CTIMER2_IRQHandler [WEAK] - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - ENDP - -CTIMER4_IRQHandler\ - PROC - EXPORT CTIMER4_IRQHandler [WEAK] - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - ENDP - -OS_EVENT_IRQHandler\ - PROC - EXPORT OS_EVENT_IRQHandler [WEAK] - LDR R0, =OS_EVENT_DriverIRQHandler - BX R0 - ENDP - -Reserved55_IRQHandler\ - PROC - EXPORT Reserved55_IRQHandler [WEAK] - LDR R0, =Reserved55_DriverIRQHandler - BX R0 - ENDP - -Reserved56_IRQHandler\ - PROC - EXPORT Reserved56_IRQHandler [WEAK] - LDR R0, =Reserved56_DriverIRQHandler - BX R0 - ENDP - -Reserved57_IRQHandler\ - PROC - EXPORT Reserved57_IRQHandler [WEAK] - LDR R0, =Reserved57_DriverIRQHandler - BX R0 - ENDP - -SDIO_IRQHandler\ - PROC - EXPORT SDIO_IRQHandler [WEAK] - LDR R0, =SDIO_DriverIRQHandler - BX R0 - ENDP - -Reserved59_IRQHandler\ - PROC - EXPORT Reserved59_IRQHandler [WEAK] - LDR R0, =Reserved59_DriverIRQHandler - BX R0 - ENDP - -Reserved60_IRQHandler\ - PROC - EXPORT Reserved60_IRQHandler [WEAK] - LDR R0, =Reserved60_DriverIRQHandler - BX R0 - ENDP - -Reserved61_IRQHandler\ - PROC - EXPORT Reserved61_IRQHandler [WEAK] - LDR R0, =Reserved61_DriverIRQHandler - BX R0 - ENDP - -USB1_UTMI_IRQHandler\ - PROC - EXPORT USB1_UTMI_IRQHandler [WEAK] - LDR R0, =USB1_UTMI_DriverIRQHandler - BX R0 - ENDP - -USB1_IRQHandler\ - PROC - EXPORT USB1_IRQHandler [WEAK] - LDR R0, =USB1_DriverIRQHandler - BX R0 - ENDP - -USB1_NEEDCLK_IRQHandler\ - PROC - EXPORT USB1_NEEDCLK_IRQHandler [WEAK] - LDR R0, =USB1_NEEDCLK_DriverIRQHandler - BX R0 - ENDP - -SEC_HYPERVISOR_CALL_IRQHandler\ - PROC - EXPORT SEC_HYPERVISOR_CALL_IRQHandler [WEAK] - LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler - BX R0 - ENDP - -SEC_GPIO_INT0_IRQ0_IRQHandler\ - PROC - EXPORT SEC_GPIO_INT0_IRQ0_IRQHandler [WEAK] - LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler - BX R0 - ENDP - -SEC_GPIO_INT0_IRQ1_IRQHandler\ - PROC - EXPORT SEC_GPIO_INT0_IRQ1_IRQHandler [WEAK] - LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler - BX R0 - ENDP - -PLU_IRQHandler\ - PROC - EXPORT PLU_IRQHandler [WEAK] - LDR R0, =PLU_DriverIRQHandler - BX R0 - ENDP - -SEC_VIO_IRQHandler\ - PROC - EXPORT SEC_VIO_IRQHandler [WEAK] - LDR R0, =SEC_VIO_DriverIRQHandler - BX R0 - ENDP - -HASHCRYPT_IRQHandler\ - PROC - EXPORT HASHCRYPT_IRQHandler [WEAK] - LDR R0, =HASHCRYPT_DriverIRQHandler - BX R0 - ENDP - -CASER_IRQHandler\ - PROC - EXPORT CASER_IRQHandler [WEAK] - LDR R0, =CASER_DriverIRQHandler - BX R0 - ENDP - -PUF_IRQHandler\ - PROC - EXPORT PUF_IRQHandler [WEAK] - LDR R0, =PUF_DriverIRQHandler - BX R0 - ENDP - -PQ_IRQHandler\ - PROC - EXPORT PQ_IRQHandler [WEAK] - LDR R0, =PQ_DriverIRQHandler - BX R0 - ENDP - -DMA1_IRQHandler\ - PROC - EXPORT DMA1_IRQHandler [WEAK] - LDR R0, =DMA1_DriverIRQHandler - BX R0 - ENDP - -LSPI_HS_IRQHandler\ - PROC - EXPORT LSPI_HS_IRQHandler [WEAK] - LDR R0, =LSPI_HS_DriverIRQHandler - BX R0 - ENDP - -PVTVF0_AMBER_IRQHandler\ - PROC - EXPORT PVTVF0_AMBER_IRQHandler [WEAK] - LDR R0, =PVTVF0_AMBER_DriverIRQHandler - BX R0 - ENDP - -PVTVF0_RED_IRQHandler\ - PROC - EXPORT PVTVF0_RED_IRQHandler [WEAK] - LDR R0, =PVTVF0_RED_DriverIRQHandler - BX R0 - ENDP - -PVTVF1_AMBER_IRQHandler\ - PROC - EXPORT PVTVF1_AMBER_IRQHandler [WEAK] - LDR R0, =PVTVF1_AMBER_DriverIRQHandler - BX R0 - ENDP - -PVTVF1_RED_IRQHandler\ - PROC - EXPORT PVTVF1_RED_IRQHandler [WEAK] - LDR R0, =PVTVF1_RED_DriverIRQHandler - BX R0 - ENDP - -Default_Handler PROC - EXPORT WDT_BOD_DriverIRQHandler [WEAK] - EXPORT DMA0_DriverIRQHandler [WEAK] - EXPORT GINT0_DriverIRQHandler [WEAK] - EXPORT GINT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT0_DriverIRQHandler [WEAK] - EXPORT PIN_INT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT2_DriverIRQHandler [WEAK] - EXPORT PIN_INT3_DriverIRQHandler [WEAK] - EXPORT UTICK0_DriverIRQHandler [WEAK] - EXPORT MRT0_DriverIRQHandler [WEAK] - EXPORT CTIMER0_DriverIRQHandler [WEAK] - EXPORT CTIMER1_DriverIRQHandler [WEAK] - EXPORT SCT0_DriverIRQHandler [WEAK] - EXPORT CTIMER3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM0_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM1_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM2_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM4_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM5_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM6_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM7_DriverIRQHandler [WEAK] - EXPORT ADC0_DriverIRQHandler [WEAK] - EXPORT Reserved39_DriverIRQHandler [WEAK] - EXPORT ACMP_CAPT0_DriverIRQHandler [WEAK] - EXPORT Reserved41_DriverIRQHandler [WEAK] - EXPORT Reserved42_DriverIRQHandler [WEAK] - EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK] - EXPORT USB0_DriverIRQHandler [WEAK] - EXPORT RTC_DriverIRQHandler [WEAK] - EXPORT EZH_ARCH_B0_DriverIRQHandler [WEAK] - EXPORT MAILBOX_DriverIRQHandler [WEAK] - EXPORT PIN_INT4_DriverIRQHandler [WEAK] - EXPORT PIN_INT5_DriverIRQHandler [WEAK] - EXPORT PIN_INT6_DriverIRQHandler [WEAK] - EXPORT PIN_INT7_DriverIRQHandler [WEAK] - EXPORT CTIMER2_DriverIRQHandler [WEAK] - EXPORT CTIMER4_DriverIRQHandler [WEAK] - EXPORT OS_EVENT_DriverIRQHandler [WEAK] - EXPORT Reserved55_DriverIRQHandler [WEAK] - EXPORT Reserved56_DriverIRQHandler [WEAK] - EXPORT Reserved57_DriverIRQHandler [WEAK] - EXPORT SDIO_DriverIRQHandler [WEAK] - EXPORT Reserved59_DriverIRQHandler [WEAK] - EXPORT Reserved60_DriverIRQHandler [WEAK] - EXPORT Reserved61_DriverIRQHandler [WEAK] - EXPORT USB1_UTMI_DriverIRQHandler [WEAK] - EXPORT USB1_DriverIRQHandler [WEAK] - EXPORT USB1_NEEDCLK_DriverIRQHandler [WEAK] - EXPORT SEC_HYPERVISOR_CALL_DriverIRQHandler [WEAK] - EXPORT SEC_GPIO_INT0_IRQ0_DriverIRQHandler [WEAK] - EXPORT SEC_GPIO_INT0_IRQ1_DriverIRQHandler [WEAK] - EXPORT PLU_DriverIRQHandler [WEAK] - EXPORT SEC_VIO_DriverIRQHandler [WEAK] - EXPORT HASHCRYPT_DriverIRQHandler [WEAK] - EXPORT CASER_DriverIRQHandler [WEAK] - EXPORT PUF_DriverIRQHandler [WEAK] - EXPORT PQ_DriverIRQHandler [WEAK] - EXPORT DMA1_DriverIRQHandler [WEAK] - EXPORT LSPI_HS_DriverIRQHandler [WEAK] - EXPORT PVTVF0_AMBER_DriverIRQHandler [WEAK] - EXPORT PVTVF0_RED_DriverIRQHandler [WEAK] - EXPORT PVTVF1_AMBER_DriverIRQHandler [WEAK] - EXPORT PVTVF1_RED_DriverIRQHandler [WEAK] - -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_DriverIRQHandler -Reserved39_DriverIRQHandler -ACMP_CAPT0_DriverIRQHandler -Reserved41_DriverIRQHandler -Reserved42_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -EZH_ARCH_B0_DriverIRQHandler -MAILBOX_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -OS_EVENT_DriverIRQHandler -Reserved55_DriverIRQHandler -Reserved56_DriverIRQHandler -Reserved57_DriverIRQHandler -SDIO_DriverIRQHandler -Reserved59_DriverIRQHandler -Reserved60_DriverIRQHandler -Reserved61_DriverIRQHandler -USB1_UTMI_DriverIRQHandler -USB1_DriverIRQHandler -USB1_NEEDCLK_DriverIRQHandler -SEC_HYPERVISOR_CALL_DriverIRQHandler -SEC_GPIO_INT0_IRQ0_DriverIRQHandler -SEC_GPIO_INT0_IRQ1_DriverIRQHandler -PLU_DriverIRQHandler -SEC_VIO_DriverIRQHandler -HASHCRYPT_DriverIRQHandler -CASER_DriverIRQHandler -PUF_DriverIRQHandler -PQ_DriverIRQHandler -DMA1_DriverIRQHandler -LSPI_HS_DriverIRQHandler -PVTVF0_AMBER_DriverIRQHandler -PVTVF0_RED_DriverIRQHandler -PVTVF1_AMBER_DriverIRQHandler -PVTVF1_RED_DriverIRQHandler - - B . - - ENDP - - - ALIGN - - - END - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/spm_hal.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/spm_hal.c deleted file mode 100644 index 8dee58f74b..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/spm_hal.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include -#include "platform/include/tfm_spm_hal.h" -#include "spm_api.h" -#include "spm_db.h" -#include "tfm_platform_core_api.h" -#include "target_cfg.h" -#include "region_defs.h" -#include "secure_utilities.h" - -/* Get address of memory regions to configure MPU */ -extern const struct memory_region_limits memory_regions; - -void tfm_spm_hal_init_isolation_hw(void) -{ - /* Configures non-secure memory spaces in the target */ - sau_and_idau_cfg(); - mpc_init_cfg(); - ppc_init_cfg(); -} - -void tfm_spm_hal_configure_default_isolation( - const struct tfm_spm_partition_platform_data_t *platform_data) -{ - /*if (platform_data) { - ppc_configure_to_secure(platform_data->periph_ppc_bank, - platform_data->periph_ppc_loc); - }*/ -} - -void tfm_spm_hal_setup_isolation_hw(void) -{ -#if TFM_LVL != 1 - if (tfm_spm_mpu_init() != SPM_ERR_OK) { - ERROR_MSG("Failed to set up initial MPU configuration! Halting."); - while (1) { - ; - } - } -#endif -} - -void SEC_VIO_IRQHandler(void) -{ - /* Clear interrupt flag and pending IRQ */ - NVIC_ClearPendingIRQ(SEC_VIO_IRQn); - - /* Print fault message and block execution */ - LOG_MSG("Oops... MPC/PPC fault!!!"); - - /* Inform TF-M core that isolation boundary has been violated */ - tfm_access_violation_handler(); -} - -uint32_t tfm_spm_hal_get_ns_VTOR(void) -{ - return memory_regions.non_secure_code_start; -} - -uint32_t tfm_spm_hal_get_ns_MSP(void) -{ - return *((uint32_t *)memory_regions.non_secure_code_start); -} - -uint32_t tfm_spm_hal_get_ns_entry_point(void) -{ - return *((uint32_t *)(memory_regions.non_secure_code_start + 4)); -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/target_cfg.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/target_cfg.c deleted file mode 100644 index e6fc81a6a4..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/target_cfg.c +++ /dev/null @@ -1,471 +0,0 @@ -/* - * Copyright (c) 2018 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "cmsis.h" -#include "target_cfg.h" -#include "region_defs.h" -#include "tfm_secure_api.h" -#include - -/* Macros to pick linker symbols */ -#define REGION(a, b, c) a##b##c -#define REGION_NAME(a, b, c) REGION(a, b, c) -#define REGION_DECLARE(a, b, c) extern uint32_t REGION_NAME(a, b, c) - -/* The section names come from the scatter file */ -REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base); -REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base); - -REGION_DECLARE(Image$$, ER_CODE_CMSE_VENEER, $$Base); -REGION_DECLARE(Image$$, ER_CODE_CMSE_VENEER, $$Limit); - - -const struct memory_region_limits memory_regions = { - .non_secure_code_start = - (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) + - BL2_HEADER_SIZE, - - .non_secure_partition_base = - (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base), - - .non_secure_partition_limit = - (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) + - NS_PARTITION_SIZE - 1, - - .veneer_base = - (uint32_t)®ION_NAME(Image$$, ER_CODE_CMSE_VENEER, $$Base), - - .veneer_limit = - (uint32_t)®ION_NAME(Image$$, ER_CODE_CMSE_VENEER, $$Limit), -}; - -/* Allows software, via SAU, to define the code region as a NSC */ -#define NSCCFG_CODENSC 1 - -/* Define Peripherals NS address range for the platform */ -#define PERIPHERALS_BASE_NS_START (0x40000000) -#define PERIPHERALS_BASE_NS_END (0x4010FFFF) - -/* Enable system reset request for CPU 0 */ -#define ENABLE_CPU0_SYSTEM_RESET_REQUEST (1U << 4U) - -/* To write into AIRCR register, 0x5FA value must be write to the VECTKEY field, - * otherwise the processor ignores the write. - */ -#define SCB_AIRCR_WRITE_MASK ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)) - -/* Debug configuration flags */ -#define SPNIDEN_SEL_STATUS (0x01u << 7) -#define SPNIDEN_STATUS (0x01u << 6) -#define SPIDEN_SEL_STATUS (0x01u << 5) -#define SPIDEN_STATUS (0x01u << 4) -#define NIDEN_SEL_STATUS (0x01u << 3) -#define NIDEN_STATUS (0x01u << 2) -#define DBGEN_SEL_STATUS (0x01u << 1) -#define DBGEN_STATUS (0x01u << 0) - -#define All_SEL_STATUS (SPNIDEN_SEL_STATUS | SPIDEN_SEL_STATUS | \ - NIDEN_SEL_STATUS | DBGEN_SEL_STATUS) - -void enable_fault_handlers(void) -{ - /* Enables BUS, MEM, USG and Secure faults */ - SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk - | SCB_SHCSR_BUSFAULTENA_Msk - | SCB_SHCSR_MEMFAULTENA_Msk - | SCB_SHCSR_SECUREFAULTENA_Msk; -} - -void system_reset_cfg(void) -{ - uint32_t reg_value = SCB->AIRCR; - - /* Clear SCB_AIRCR_VECTKEY value */ - reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk); - - /* Enable system reset request only to the secure world */ - reg_value |= (uint32_t)(SCB_AIRCR_WRITE_MASK | SCB_AIRCR_SYSRESETREQS_Msk); - - SCB->AIRCR = reg_value; -} - -void tfm_spm_hal_init_debug(void) -{ - volatile struct sysctrl_t *sys_ctrl = - (struct sysctrl_t *)CMSDK_SYSCTRL_BASE_S; - -#if defined(DAUTH_NONE) - /* Set all the debug enable selector bits to 1 */ - sys_ctrl->secdbgset = All_SEL_STATUS; - /* Set all the debug enable bits to 0 */ - sys_ctrl->secdbgclr = - DBGEN_STATUS | NIDEN_STATUS | SPIDEN_STATUS | SPNIDEN_STATUS; -#elif defined(DAUTH_NS_ONLY) - /* Set all the debug enable selector bits to 1 */ - sys_ctrl->secdbgset = All_SEL_STATUS; - /* Set the debug enable bits to 1 for NS, and 0 for S mode */ - sys_ctrl->secdbgset = DBGEN_STATUS | NIDEN_STATUS; - sys_ctrl->secdbgclr = SPIDEN_STATUS | SPNIDEN_STATUS; -#elif defined(DAUTH_FULL) - /* Set all the debug enable selector bits to 1 */ - sys_ctrl->secdbgset = All_SEL_STATUS; - /* Set all the debug enable bits to 1 */ - sys_ctrl->secdbgset = - DBGEN_STATUS | NIDEN_STATUS | SPIDEN_STATUS | SPNIDEN_STATUS; -#else - -#if !defined(DAUTH_CHIP_DEFAULT) -#error "No debug authentication setting is provided." -#endif - - /* Set all the debug enable selector bits to 0 */ - sys_ctrl->secdbgclr = All_SEL_STATUS; - - /* No need to set any enable bits because the value depends on - * input signals. - */ -#endif -} - -/*----------------- NVIC interrupt target state to NS configuration ----------*/ -void nvic_interrupt_target_state_cfg() -{ - /* Target every interrupt to NS; unimplemented interrupts will be WI */ - for (uint8_t i=0; iITNS)/sizeof(NVIC->ITNS[0]); i++) { - NVIC->ITNS[i] = 0xFFFFFFFF; - } - - /* Make sure that MPC and PPC are targeted to S state */ - NVIC_ClearTargetState(SEC_VIO_IRQn); -} - -/*----------------- NVIC interrupt enabling for S peripherals ----------------*/ -void nvic_interrupt_enable() -{ - NVIC_EnableIRQ(SEC_VIO_IRQn); -} - - -/*------------------- SAU/IDAU configuration functions -----------------------*/ - -void sau_and_idau_cfg(void) -{ - /* Disable SAU */ - TZ_SAU_Disable(); - - /* Configures SAU regions to be non-secure */ - SAU->RNR = TFM_NS_REGION_CODE; - SAU->RBAR = (memory_regions.non_secure_partition_base - & SAU_RBAR_BADDR_Msk); - SAU->RLAR = (memory_regions.non_secure_partition_limit - & SAU_RLAR_LADDR_Msk) - | SAU_RLAR_ENABLE_Msk; - - SAU->RNR = TFM_NS_REGION_DATA; - SAU->RBAR = (NS_DATA_START & SAU_RBAR_BADDR_Msk); - SAU->RLAR = (NS_DATA_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; - - /* Configures veneers region to be non-secure callable */ - SAU->RNR = TFM_NS_REGION_VENEER; - SAU->RBAR = (memory_regions.veneer_base & SAU_RBAR_BADDR_Msk); - SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk) - | SAU_RLAR_ENABLE_Msk - | SAU_RLAR_NSC_Msk; - - /* Configure the peripherals space */ - SAU->RNR = TFM_NS_REGION_PERIPH_1; - SAU->RBAR = (PERIPHERALS_BASE_NS_START & SAU_RBAR_BADDR_Msk); - SAU->RLAR = (PERIPHERALS_BASE_NS_END & SAU_RLAR_LADDR_Msk) - | SAU_RLAR_ENABLE_Msk; - -#ifdef BL2 - /* Secondary image partition */ - SAU->RNR = TFM_NS_SECONDARY_IMAGE_REGION; - SAU->RBAR = (memory_regions.secondary_partition_base & SAU_RBAR_BADDR_Msk); - SAU->RLAR = (memory_regions.secondary_partition_limit & SAU_RLAR_LADDR_Msk) - | SAU_RLAR_ENABLE_Msk; -#endif /* BL2 */ - - /* Force memory writes before continuing */ - __DSB(); - /* Flush and refill pipeline with updated permissions */ - __ISB(); - - /* Enable SAU */ - TZ_SAU_Enable(); - -} - -/*------------------- Memory configuration functions -------------------------*/ - -void mpc_init_cfg(void) -{ - uint32_t mpcIdx = 0; - uint32_t startRegionIdx = 0; - uint32_t endRegionIdx = 0; - - /* - * Starts changing actual configuration so issue DMB to ensure every - * transaction has completed by now - */ - __DMB(); - - //FLASH memory configuration (all regions set to secure privilidged) - AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[0] = 0x33333333U; - AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[1] = 0x33333333U; - AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[2] = 0x33333333U; - - //FLASH memory configuration (set according to region_defs.h and flash_layout.h) - //The regions have to be alligned to 32 kB to cover the AHB Flash Region - if (((NS_PARTITION_START % FLASH_AREA_IMAGE_SECTOR_SIZE) == 0) && \ - (((NS_PARTITION_START + NS_PARTITION_SIZE) % FLASH_AREA_IMAGE_SECTOR_SIZE) == 0)) { - startRegionIdx = NS_PARTITION_START / FLASH_AREA_IMAGE_SECTOR_SIZE; - endRegionIdx = (NS_PARTITION_START + NS_PARTITION_SIZE) / FLASH_AREA_IMAGE_SECTOR_SIZE; - - for(mpcIdx = startRegionIdx; mpcIdx < endRegionIdx; mpcIdx++) { - if(mpcIdx < 8) { - //Set regions the ABH controller for flash memory 0x0000_0000 - 0x0004_0000 - AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[0] &= ~(0xF << (mpcIdx * 4)); - } - if((mpcIdx >= 8) && (mpcIdx < 16)) { - //Set regions in the ABH controller for flash memory 0x0004_0000 - 0x0008_0000 - AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[1] &= ~(0xF << ((mpcIdx - 8) * 4)); - } - if((mpcIdx >= 16) && (mpcIdx < 24)) { - //Set regions the ABH controller for flash memory 0x0008_0000 - 0x0009_8000 - AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[2] &= ~(0xF << ((mpcIdx - 16) * 4)); - } - } - } else { - ERROR_MSG("Failed to set up initial MPC configuration! NS Flash regions are not alligned to 32kB. Halting."); - while (1) { - ; - } - } - - //ROM memory configuration (all secure) - AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[0] = 0x33333333U; - AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[1] = 0x33333333U; - AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[2] = 0x33333333U; - AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[3] = 0x33333333U; - - //SRAM memory configuration (all secure) - AHB_SECURE_CTRL->SEC_CTRL_RAMX[0].MEM_RULE[0]= 0x33333333U; - - //RAM memory configuration - AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[0]= 0x33333333U; - AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[1]= 0x33333333U; - AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[0]= 0x33333333U; - AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[1]= 0x33333333U; - AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[0]= 0x33333333U; - AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[1]= 0x33333333U; - AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[0]= 0x33333333U; - AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[1]= 0x33333333U; - AHB_SECURE_CTRL->SEC_CTRL_RAM4[0].MEM_RULE[0]= 0x33333333U; - - //RAM memory configuration (set according to region_defs.h and flash_layout.h) - //The regions have to be alligned to 4 kB to cover the AHB RAM Region - if (((S_DATA_SIZE % DATA_SUBREGION_SIZE) == 0) && \ - (((S_DATA_SIZE + NS_DATA_SIZE) % DATA_SUBREGION_SIZE) == 0)) { - startRegionIdx = S_DATA_SIZE / DATA_SUBREGION_SIZE; - endRegionIdx = (S_DATA_SIZE + NS_DATA_SIZE) / DATA_SUBREGION_SIZE; - - for(mpcIdx = startRegionIdx; mpcIdx < endRegionIdx; mpcIdx++) { - //Set regions the ABH controller for ram memory 0x0000_0000 - 0x0000_8000 - if(mpcIdx < 8) { - AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[0] &= ~(0xF << (mpcIdx*4)); - } - //Set regions the ABH controller for ram memory 0x0000_8000 - 0x0001_0000 - if((mpcIdx >= 8) && (mpcIdx < 16)) { - AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[1] &= ~(0xF << ((mpcIdx-8)*4)); - } - //Set regions the ABH controller for ram memory 0x0001_0000 - 0x0001_8000 - if((mpcIdx >= 16) && (mpcIdx < 24)) { - AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[0] &= ~(0xF << ((mpcIdx-16)*4)); - } - //Set regions the ABH controller for ram memory 0x0001_8000 - 0x0002_0000 - if((mpcIdx >= 24) && (mpcIdx < 32)) { - AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[1] &= ~(0xF << ((mpcIdx-24)*4)); - } - //Set regions the ABH controller for ram memory 0x0002_0000 - 0x0002_8000 - if((mpcIdx >= 32) && (mpcIdx < 40)) { - AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[0] &= ~(0xF << ((mpcIdx-32)*4)); - } - //Set regions the ABH controller for ram memory 0x0002_8000 - 0x0003_0000 - if((mpcIdx >= 40) && (mpcIdx < 48)) { - AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[1] &= ~(0xF << ((mpcIdx-40)*4)); - } - //Set regions the ABH controller for ram memory 0x0003_0000 - 0x0003_8000 - if((mpcIdx >= 48) && (mpcIdx < 56)) { - AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[0] &= ~(0xF << ((mpcIdx-48)*4)); - } - //Set regions the ABH controller for ram memory 0x0003_8000 - 0x0004_0000 - if((mpcIdx >= 56) && (mpcIdx < 64)) { - AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[1] &= ~(0xF << ((mpcIdx-56)*4)); - } - //Set regions the ABH controller for ram memory 0x0004_0000 - 0x0004_4000 - if((mpcIdx >= 64) && (mpcIdx < 72)) { - AHB_SECURE_CTRL->SEC_CTRL_RAM4[0].MEM_RULE[0] &= ~(0xF << ((mpcIdx-64)*4)); - } - } - } else { - ERROR_MSG("Failed to set up initial MPC configuration! NS RAM regions are not alligned to 4kB. Halting."); - while (1) { - ; - } - } - - /* Add barriers to assure the MPC configuration is done before continue - * the execution. - */ - __DSB(); - __ISB(); -} - -/*---------------------- PPC configuration functions -------------------------*/ - -void ppc_init_cfg(void) -{ - /* Secure access to Flash controller in the PPC */ - - AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 = - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(0x3U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(0x0U); - - /* Grant non-secure access to peripherals in the PPC */ - - /* APB settings for Bridge 0 */ - AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 = - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE(0x0U); - - AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 = - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(0x0U); - - AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 = - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE(0x0U); - - AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL3 = - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_CAPTOUCH_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_EZH_RULE(0x0U); - - /* APB settings for Bridge 1 */ - AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 = - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PVT_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(0x0U); - - AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 = - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(0x0U); - - AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 = - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_ROMPC_RULE(0x0U); - - /* AHB settings*/ - AHB_SECURE_CTRL->SEC_CTRL_AHB0_0_SLAVE_RULE = - AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE(0x0U); - - AHB_SECURE_CTRL->SEC_CTRL_AHB0_1_SLAVE_RULE = - AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE(0x0U); - - AHB_SECURE_CTRL->SEC_CTRL_AHB1_0_SLAVE_RULE = - AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE(0x0U); - - AHB_SECURE_CTRL->SEC_CTRL_AHB1_1_SLAVE_RULE = - AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE(0x0U); - - AHB_SECURE_CTRL->SEC_CTRL_AHB2[0].SEC_CTRL_AHB2_0_SLAVE_RULE = - AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE(0x0U); - - AHB_SECURE_CTRL->SEC_CTRL_AHB2[0].SEC_CTRL_AHB2_1_SLAVE_RULE = - AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE(0x0U); - - AHB_SECURE_CTRL->SEC_CTRL_AHB2[0].SEC_CTRL_AHB2_0_MEM_RULE[0] = - AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(0x0U); - - AHB_SECURE_CTRL->SEC_CTRL_USB_HS[0].SLAVE_RULE = - AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(0x0U); - - AHB_SECURE_CTRL->SEC_CTRL_USB_HS[0].MEM_RULE[0] = - AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE(0x0U) | - AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE(0x0U); - - /* Enable AHB secure controller check and lock all rule registers */ - AHB_SECURE_CTRL->MISC_CTRL_REG = - (AHB_SECURE_CTRL->MISC_CTRL_REG & ~(AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK | - AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)) | - AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(0x1U) | - AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(0x1U); - - AHB_SECURE_CTRL->MISC_CTRL_DP_REG = - (AHB_SECURE_CTRL->MISC_CTRL_DP_REG & ~(AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK | - AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK | - AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK)) | - AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(0x1U) | - AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(0x1U) | - AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(0x1U); - -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/target_cfg.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/target_cfg.h deleted file mode 100644 index 0cba40c641..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/target_cfg.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __TARGET_CFG_H__ -#define __TARGET_CFG_H__ - -#include "tfm_peripherals_def.h" - -/** - * \brief Store the addresses of memory regions - */ -struct memory_region_limits { - uint32_t non_secure_code_start; - uint32_t non_secure_partition_base; - uint32_t non_secure_partition_limit; - uint32_t veneer_base; - uint32_t veneer_limit; -}; - -/** - * \brief Holds the data necessary to do isolation for a specific peripheral. - */ -struct tfm_spm_partition_platform_data_t -{ - uint32_t periph_start; - uint32_t periph_limit; - int16_t periph_ppc_bank; - int16_t periph_ppc_loc; -}; - -/** - * \brief Configures the Memory Protection Controller. - */ -void mpc_init_cfg(void); - -/** - * \brief Configures the Peripheral Protection Controller. - */ -void ppc_init_cfg(void); - -/** - * \brief Configures SAU and IDAU. - */ -void sau_and_idau_cfg(void); - - -#endif /* __TARGET_CFG_H__ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/tfm_peripherals_def.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/tfm_peripherals_def.h deleted file mode 100644 index ab5f174fdd..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/tfm_peripherals_def.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __TFM_PERIPHERALS_DEF_H__ -#define __TFM_PERIPHERALS_DEF_H__ - -struct tfm_spm_partition_platform_data_t; - -extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart; - -#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart) - -#endif /* __TFM_PERIPHERALS_DEF_H__ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/trng_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/trng_api.c deleted file mode 100644 index 190be09006..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_S/trng_api.c +++ /dev/null @@ -1,48 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "trng_api.h" - -#if defined(DEVICE_TRNG) -#include "fsl_rng.h" - -void trng_init(trng_t *obj) -{ - /* Init RNGA */ - RNG_Init(RNG); -} - -void trng_free(trng_t *obj) -{ - RNG_Deinit(RNG); -} - -int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) -{ - status_t status; - - /* Get Random data*/ - status = RNG_GetRandomData(RNG, output, length); - if (status == kStatus_Success) { - *output_length = length; - return 0; - } else { - return -1; - } -} - -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core0.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core0.h deleted file mode 100644 index d9e6105a4f..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core0.h +++ /dev/null @@ -1,24755 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b190122 -** -** Abstract: -** CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 -** -** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** -** ################################################################### -*/ - -/*! - * @file LPC55S69_cm33_core0.h - * @version 1.0 - * @date 2018-08-22 - * @brief CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 - * - * CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 - */ - -#ifndef _LPC55S69_CM33_CORE0_H_ -#define _LPC55S69_CM33_CORE0_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0000U - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ - - /* Device specific interrupts */ - WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ - DMA0_IRQn = 1, /**< DMA0 controller */ - GINT0_IRQn = 2, /**< GPIO group 0 */ - GINT1_IRQn = 3, /**< GPIO group 1 */ - PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ - PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ - PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ - PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ - UTICK0_IRQn = 8, /**< Micro-tick Timer */ - MRT0_IRQn = 9, /**< Multi-rate timer */ - CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ - CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ - SCT0_IRQn = 12, /**< SCTimer/PWM */ - CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ - FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - ADC0_IRQn = 22, /**< ADC0 */ - Reserved39_IRQn = 23, /**< Reserved interrupt */ - ACMP_IRQn = 24, /**< ACMP interrupts */ - Reserved41_IRQn = 25, /**< Reserved interrupt */ - Reserved42_IRQn = 26, /**< Reserved interrupt */ - USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ - USB0_IRQn = 28, /**< USB device */ - RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ - Reserved46_IRQn = 30, /**< Reserved interrupt */ - MAILBOX_IRQn = 31, /**< WAKEUP,Mailbox interrupt (present on selected devices) */ - PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ - PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ - PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ - PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ - CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ - CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ - OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ - Reserved55_IRQn = 39, /**< Reserved interrupt */ - Reserved56_IRQn = 40, /**< Reserved interrupt */ - Reserved57_IRQn = 41, /**< Reserved interrupt */ - SDIO_IRQn = 42, /**< SD/MMC */ - Reserved59_IRQn = 43, /**< Reserved interrupt */ - Reserved60_IRQn = 44, /**< Reserved interrupt */ - Reserved61_IRQn = 45, /**< Reserved interrupt */ - USB1_UTMI_IRQn = 46, /**< USB1_UTMI */ - USB1_IRQn = 47, /**< USB1 interrupt */ - USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ - SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ - SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */ - SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */ - PLU_IRQn = 52, /**< PLU interrupt */ - SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ - HASHCRYPT_IRQn = 54, /**< HASHCRYPT interrupt */ - CASER_IRQn = 55, /**< CASPER interrupt */ - PUF_IRQn = 56, /**< PUF interrupt */ - PQ_IRQn = 57, /**< PQ interrupt */ - DMA1_IRQn = 58, /**< DMA1 interrupt */ - LSPI_HS_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M33 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ - -#include "core_cm33.h" /* Core Peripheral Access Layer */ -#include "system_LPC55S69_cm33_core0.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -/*! - * @addtogroup dma_request - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Structure for the DMA hardware request - * - * Defines the structure for the DMA hardware request collections. The user can configure the - * hardware request to trigger the DMA transfer accordingly. The index - * of the hardware request varies according to the to SoC. - */ -typedef enum _dma_request_source -{ - kDma0RequestHashCrypt = 0U, /**< HashCrypt */ - kDma1RequestHashCryptInput = 0U, /**< HashCrypt Input */ - kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ - kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ - kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ - kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ - kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ - kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ - kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ - kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ - kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ - kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ - kDma0RequestFlexcomm2Rx = 8U, /**< Flexcomm Interface 2 RX/I2C Slave */ - kDma1RequestFlexcomm2Rx = 8U, /**< Flexcomm Interface 2 RX/I2C Slave */ - kDma0RequestFlexcomm2Tx = 9U, /**< Flexcomm Interface 2 TX/I2C Master */ - kDma1RequestFlexcomm2Tx = 9U, /**< Flexcomm Interface 2 TX/I2C Master */ - kDma0RequestFlexcomm3Rx = 10U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kDma0RequestFlexcomm3Tx = 11U, /**< Flexcomm Interface 3 TX/I2C Master */ - kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ - kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ - kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ - kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ - kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ - kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ - kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ - kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ - kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */ - kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ - kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ -} dma_request_source_t; - -/* @} */ - - -/*! - * @} - */ /* end of group Mapping_Information */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #else - #pragma push - #pragma anon_unions - #endif -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ - __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ - __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ - __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ - __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ - uint8_t RESERVED_1[12]; - __IO uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ - __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ - uint8_t RESERVED_2[4]; - __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ - uint8_t RESERVED_3[92]; - __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ - __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_4[8]; - __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ - __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ - } CMD[15]; - uint8_t RESERVED_5[136]; - __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_6[240]; - __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ - uint8_t RESERVED_7[248]; - __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ - uint8_t RESERVED_8[124]; - __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ - uint8_t RESERVED_9[2680]; - __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define ADC_VERID_RES_MASK (0x1U) -#define ADC_VERID_RES_SHIFT (0U) -/*! RES - Resolution - * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. - * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. - */ -#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) -#define ADC_VERID_DIFFEN_MASK (0x2U) -#define ADC_VERID_DIFFEN_SHIFT (1U) -/*! DIFFEN - Differential Supported - * 0b0..Differential operation not supported. - * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. - */ -#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) -#define ADC_VERID_MVI_MASK (0x8U) -#define ADC_VERID_MVI_SHIFT (3U) -/*! MVI - Multi Vref Implemented - * 0b0..Single voltage reference high (VREFH) input supported. - * 0b1..Multiple voltage reference high (VREFH) inputs supported. - */ -#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) -#define ADC_VERID_CSW_MASK (0x70U) -#define ADC_VERID_CSW_SHIFT (4U) -/*! CSW - Channel Scale Width - * 0b000..Channel scaling not supported. - * 0b001..Channel scaling supported. 1-bit CSCALE control field. - * 0b110..Channel scaling supported. 6-bit CSCALE control field. - */ -#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) -#define ADC_VERID_VR1RNGI_MASK (0x100U) -#define ADC_VERID_VR1RNGI_SHIFT (8U) -/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented - * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. - * 0b1..Range control required. CFG[VREF1RNG] is implemented. - */ -#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) -#define ADC_VERID_IADCKI_MASK (0x200U) -#define ADC_VERID_IADCKI_SHIFT (9U) -/*! IADCKI - Internal ADC Clock implemented - * 0b0..Internal clock source not implemented. - * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. - */ -#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) -#define ADC_VERID_CALOFSI_MASK (0x400U) -#define ADC_VERID_CALOFSI_SHIFT (10U) -/*! CALOFSI - Calibration Function Implemented - * 0b0..Calibration Not Implemented. - * 0b1..Calibration Implemented. - */ -#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) -#define ADC_VERID_NUM_SEC_MASK (0x800U) -#define ADC_VERID_NUM_SEC_SHIFT (11U) -/*! NUM_SEC - Number of Single Ended Outputs Supported - * 0b0..This design supports one single ended conversion at a time. - * 0b1..This design supports two simultanious single ended conversions. - */ -#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) -#define ADC_VERID_NUM_FIFO_MASK (0x7000U) -#define ADC_VERID_NUM_FIFO_SHIFT (12U) -/*! NUM_FIFO - Number of FIFOs - * 0b000..N/A - * 0b001..This design supports one result FIFO. - * 0b010..This design supports two result FIFOs. - * 0b011..This design supports three result FIFOs. - * 0b100..This design supports four result FIFOs. - */ -#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) -#define ADC_VERID_MINOR_MASK (0xFF0000U) -#define ADC_VERID_MINOR_SHIFT (16U) -#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) -#define ADC_VERID_MAJOR_MASK (0xFF000000U) -#define ADC_VERID_MAJOR_SHIFT (24U) -#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) -#define ADC_PARAM_TRIG_NUM_SHIFT (0U) -#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) -#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) -#define ADC_PARAM_FIFOSIZE_SHIFT (8U) -/*! FIFOSIZE - Result FIFO Depth - * 0b00000001..Result FIFO depth = 1 dataword. - * 0b00000100..Result FIFO depth = 4 datawords. - * 0b00001000..Result FIFO depth = 8 datawords. - * 0b00010000..Result FIFO depth = 16 datawords. - * 0b00100000..Result FIFO depth = 32 datawords. - * 0b01000000..Result FIFO depth = 64 datawords. - */ -#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) -#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) -#define ADC_PARAM_CV_NUM_SHIFT (16U) -#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) -#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) -#define ADC_PARAM_CMD_NUM_SHIFT (24U) -#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) -/*! @} */ - -/*! @name CTRL - ADC Control Register */ -/*! @{ */ -#define ADC_CTRL_ADCEN_MASK (0x1U) -#define ADC_CTRL_ADCEN_SHIFT (0U) -/*! ADCEN - ADC Enable - * 0b0..ADC is disabled. - * 0b1..ADC is enabled. - */ -#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) -#define ADC_CTRL_RST_MASK (0x2U) -#define ADC_CTRL_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..ADC logic is not reset. - * 0b1..ADC logic is reset. - */ -#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) -#define ADC_CTRL_DOZEN_MASK (0x4U) -#define ADC_CTRL_DOZEN_SHIFT (2U) -/*! DOZEN - Doze Enable - * 0b0..ADC is enabled in Doze mode. - * 0b1..ADC is disabled in Doze mode. - */ -#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) -#define ADC_CTRL_CAL_REQ_MASK (0x8U) -#define ADC_CTRL_CAL_REQ_SHIFT (3U) -/*! CAL_REQ - Auto-Calibration Request - * 0b0..No request for auto-calibration has been made. - * 0b1..A request for auto-calibration has been made - */ -#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) -#define ADC_CTRL_CALOFS_MASK (0x10U) -#define ADC_CTRL_CALOFS_SHIFT (4U) -/*! CALOFS - Configure for offset calibration function - * 0b0..Calibration function disabled - * 0b1..Request for offset calibration function - */ -#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) -#define ADC_CTRL_RSTFIFO0_MASK (0x100U) -#define ADC_CTRL_RSTFIFO0_SHIFT (8U) -/*! RSTFIFO0 - Reset FIFO 0 - * 0b0..No effect. - * 0b1..FIFO 0 is reset. - */ -#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) -#define ADC_CTRL_RSTFIFO1_MASK (0x200U) -#define ADC_CTRL_RSTFIFO1_SHIFT (9U) -/*! RSTFIFO1 - Reset FIFO 1 - * 0b0..No effect. - * 0b1..FIFO 1 is reset. - */ -#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) -#define ADC_CTRL_CAL_AVGS_MASK (0x70000U) -#define ADC_CTRL_CAL_AVGS_SHIFT (16U) -/*! CAL_AVGS - Auto-Calibration Averages - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) -/*! @} */ - -/*! @name STAT - ADC Status Register */ -/*! @{ */ -#define ADC_STAT_RDY0_MASK (0x1U) -#define ADC_STAT_RDY0_SHIFT (0U) -/*! RDY0 - Result FIFO 0 Ready Flag - * 0b0..Result FIFO 0 data level not above watermark level. - * 0b1..Result FIFO 0 holding data above watermark level. - */ -#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) -#define ADC_STAT_FOF0_MASK (0x2U) -#define ADC_STAT_FOF0_SHIFT (1U) -/*! FOF0 - Result FIFO 0 Overflow Flag - * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) -#define ADC_STAT_RDY1_MASK (0x4U) -#define ADC_STAT_RDY1_SHIFT (2U) -/*! RDY1 - Result FIFO1 Ready Flag - * 0b0..Result FIFO1 data level not above watermark level. - * 0b1..Result FIFO1 holding data above watermark level. - */ -#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) -#define ADC_STAT_FOF1_MASK (0x8U) -#define ADC_STAT_FOF1_SHIFT (3U) -/*! FOF1 - Result FIFO1 Overflow Flag - * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) -#define ADC_STAT_TEXC_INT_MASK (0x100U) -#define ADC_STAT_TEXC_INT_SHIFT (8U) -/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception - * 0b0..No trigger exceptions have occurred. - * 0b1..A trigger exception has occurred and is pending acknowledgement. - */ -#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) -#define ADC_STAT_TCOMP_INT_MASK (0x200U) -#define ADC_STAT_TCOMP_INT_SHIFT (9U) -/*! TCOMP_INT - Interrupt Flag For Trigger Completion - * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. - * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. - */ -#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) -#define ADC_STAT_CAL_RDY_MASK (0x400U) -#define ADC_STAT_CAL_RDY_SHIFT (10U) -/*! CAL_RDY - Calibration Ready - * 0b0..Calibration is incomplete or hasn't been ran. - * 0b1..The ADC is calibrated. - */ -#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) -#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) -#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) -/*! ADC_ACTIVE - ADC Active - * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. - * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. - */ -#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) -#define ADC_STAT_TRGACT_MASK (0xF0000U) -#define ADC_STAT_TRGACT_SHIFT (16U) -/*! TRGACT - Trigger Active - * 0b0000..Command (sequence) associated with Trigger 0 currently being executed. - * 0b0001..Command (sequence) associated with Trigger 1 currently being executed. - * 0b0010..Command (sequence) associated with Trigger 2 currently being executed. - * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. - */ -#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) -#define ADC_STAT_CMDACT_MASK (0xF000000U) -#define ADC_STAT_CMDACT_SHIFT (24U) -/*! CMDACT - Command Active - * 0b0000..No command is currently in progress. - * 0b0001..Command 1 currently being executed. - * 0b0010..Command 2 currently being executed. - * 0b0011-0b1111..Associated command number is currently being executed. - */ -#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) -/*! @} */ - -/*! @name IE - Interrupt Enable Register */ -/*! @{ */ -#define ADC_IE_FWMIE0_MASK (0x1U) -#define ADC_IE_FWMIE0_SHIFT (0U) -/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable - * 0b0..FIFO 0 watermark interrupts are not enabled. - * 0b1..FIFO 0 watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) -#define ADC_IE_FOFIE0_MASK (0x2U) -#define ADC_IE_FOFIE0_SHIFT (1U) -/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable - * 0b0..FIFO 0 overflow interrupts are not enabled. - * 0b1..FIFO 0 overflow interrupts are enabled. - */ -#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) -#define ADC_IE_FWMIE1_MASK (0x4U) -#define ADC_IE_FWMIE1_SHIFT (2U) -/*! FWMIE1 - FIFO1 Watermark Interrupt Enable - * 0b0..FIFO1 watermark interrupts are not enabled. - * 0b1..FIFO1 watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) -#define ADC_IE_FOFIE1_MASK (0x8U) -#define ADC_IE_FOFIE1_SHIFT (3U) -/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable - * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) -#define ADC_IE_TEXC_IE_MASK (0x100U) -#define ADC_IE_TEXC_IE_SHIFT (8U) -/*! TEXC_IE - Trigger Exception Interrupt Enable - * 0b0..Trigger exception interrupts are disabled. - * 0b1..Trigger exception interrupts are enabled. - */ -#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) -#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) -#define ADC_IE_TCOMP_IE_SHIFT (16U) -/*! TCOMP_IE - Trigger Completion Interrupt Enable - * 0b0000000000000000..Trigger completion interrupts are disabled. - * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only. - * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only. - * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled. - * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source. - */ -#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) -/*! @} */ - -/*! @name DE - DMA Enable Register */ -/*! @{ */ -#define ADC_DE_FWMDE0_MASK (0x1U) -#define ADC_DE_FWMDE0_SHIFT (0U) -/*! FWMDE0 - FIFO 0 Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) -#define ADC_DE_FWMDE1_MASK (0x2U) -#define ADC_DE_FWMDE1_SHIFT (1U) -/*! FWMDE1 - FIFO1 Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) -/*! @} */ - -/*! @name CFG - ADC Configuration Register */ -/*! @{ */ -#define ADC_CFG_TPRICTRL_MASK (0x3U) -#define ADC_CFG_TPRICTRL_SHIFT (0U) -/*! TPRICTRL - ADC trigger priority control - * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. - * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. - * 0b10..If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger. - * 0b11..RESERVED - */ -#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) -#define ADC_CFG_PWRSEL_MASK (0x30U) -#define ADC_CFG_PWRSEL_SHIFT (4U) -/*! PWRSEL - Power Configuration Select - * 0b00..Lowest power setting. - * 0b01..Higher power setting than 0b0. - * 0b10..Higher power setting than 0b1. - * 0b11..Highest power setting. - */ -#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) -#define ADC_CFG_REFSEL_MASK (0xC0U) -#define ADC_CFG_REFSEL_SHIFT (6U) -/*! REFSEL - Voltage Reference Selection - * 0b00..(Default) Option 1 setting. - * 0b01..Option 2 setting. - * 0b10..Option 3 setting. - * 0b11..Reserved - */ -#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) -#define ADC_CFG_TRES_MASK (0x100U) -#define ADC_CFG_TRES_SHIFT (8U) -/*! TRES - Trigger Resume Enable - * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. - * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. - */ -#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) -#define ADC_CFG_TCMDRES_MASK (0x200U) -#define ADC_CFG_TCMDRES_SHIFT (9U) -/*! TCMDRES - Trigger Command Resume - * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. - * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. - */ -#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) -#define ADC_CFG_HPT_EXDI_MASK (0x400U) -#define ADC_CFG_HPT_EXDI_SHIFT (10U) -/*! HPT_EXDI - High Priority Trigger Exception Disable - * 0b0..High priority trigger exceptions are enabled. - * 0b1..High priority trigger exceptions are disabled. - */ -#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) -#define ADC_CFG_PUDLY_MASK (0xFF0000U) -#define ADC_CFG_PUDLY_SHIFT (16U) -#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) -#define ADC_CFG_PWREN_MASK (0x10000000U) -#define ADC_CFG_PWREN_SHIFT (28U) -/*! PWREN - ADC Analog Pre-Enable - * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. - * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog will remain pre-enabled, and no additional delays will be executed. - */ -#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) -/*! @} */ - -/*! @name PAUSE - ADC Pause Register */ -/*! @{ */ -#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) -#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) -#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) -#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) -#define ADC_PAUSE_PAUSEEN_SHIFT (31U) -/*! PAUSEEN - PAUSE Option Enable - * 0b0..Pause operation disabled - * 0b1..Pause operation enabled - */ -#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) -/*! @} */ - -/*! @name SWTRIG - Software Trigger Register */ -/*! @{ */ -#define ADC_SWTRIG_SWT0_MASK (0x1U) -#define ADC_SWTRIG_SWT0_SHIFT (0U) -/*! SWT0 - Software trigger 0 event - * 0b0..No trigger 0 event generated. - * 0b1..Trigger 0 event generated. - */ -#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) -#define ADC_SWTRIG_SWT1_MASK (0x2U) -#define ADC_SWTRIG_SWT1_SHIFT (1U) -/*! SWT1 - Software trigger 1 event - * 0b0..No trigger 1 event generated. - * 0b1..Trigger 1 event generated. - */ -#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) -#define ADC_SWTRIG_SWT2_MASK (0x4U) -#define ADC_SWTRIG_SWT2_SHIFT (2U) -/*! SWT2 - Software trigger 2 event - * 0b0..No trigger 2 event generated. - * 0b1..Trigger 2 event generated. - */ -#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) -#define ADC_SWTRIG_SWT3_MASK (0x8U) -#define ADC_SWTRIG_SWT3_SHIFT (3U) -/*! SWT3 - Software trigger 3 event - * 0b0..No trigger 3 event generated. - * 0b1..Trigger 3 event generated. - */ -#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) -#define ADC_SWTRIG_SWT4_MASK (0x10U) -#define ADC_SWTRIG_SWT4_SHIFT (4U) -/*! SWT4 - Software trigger 4 event - * 0b0..No trigger 4 event generated. - * 0b1..Trigger 4 event generated. - */ -#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) -#define ADC_SWTRIG_SWT5_MASK (0x20U) -#define ADC_SWTRIG_SWT5_SHIFT (5U) -/*! SWT5 - Software trigger 5 event - * 0b0..No trigger 5 event generated. - * 0b1..Trigger 5 event generated. - */ -#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) -#define ADC_SWTRIG_SWT6_MASK (0x40U) -#define ADC_SWTRIG_SWT6_SHIFT (6U) -/*! SWT6 - Software trigger 6 event - * 0b0..No trigger 6 event generated. - * 0b1..Trigger 6 event generated. - */ -#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) -#define ADC_SWTRIG_SWT7_MASK (0x80U) -#define ADC_SWTRIG_SWT7_SHIFT (7U) -/*! SWT7 - Software trigger 7 event - * 0b0..No trigger 7 event generated. - * 0b1..Trigger 7 event generated. - */ -#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) -#define ADC_SWTRIG_SWT8_MASK (0x100U) -#define ADC_SWTRIG_SWT8_SHIFT (8U) -/*! SWT8 - Software trigger 8 event - * 0b0..No trigger 8 event generated. - * 0b1..Trigger 8 event generated. - */ -#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) -#define ADC_SWTRIG_SWT9_MASK (0x200U) -#define ADC_SWTRIG_SWT9_SHIFT (9U) -/*! SWT9 - Software trigger 9 event - * 0b0..No trigger 9 event generated. - * 0b1..Trigger 9 event generated. - */ -#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) -#define ADC_SWTRIG_SWT10_MASK (0x400U) -#define ADC_SWTRIG_SWT10_SHIFT (10U) -/*! SWT10 - Software trigger 10 event - * 0b0..No trigger 10 event generated. - * 0b1..Trigger 10 event generated. - */ -#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) -#define ADC_SWTRIG_SWT11_MASK (0x800U) -#define ADC_SWTRIG_SWT11_SHIFT (11U) -/*! SWT11 - Software trigger 11 event - * 0b0..No trigger 11 event generated. - * 0b1..Trigger 11 event generated. - */ -#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) -#define ADC_SWTRIG_SWT12_MASK (0x1000U) -#define ADC_SWTRIG_SWT12_SHIFT (12U) -/*! SWT12 - Software trigger 12 event - * 0b0..No trigger 12 event generated. - * 0b1..Trigger 12 event generated. - */ -#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) -#define ADC_SWTRIG_SWT13_MASK (0x2000U) -#define ADC_SWTRIG_SWT13_SHIFT (13U) -/*! SWT13 - Software trigger 13 event - * 0b0..No trigger 13 event generated. - * 0b1..Trigger 13 event generated. - */ -#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) -#define ADC_SWTRIG_SWT14_MASK (0x4000U) -#define ADC_SWTRIG_SWT14_SHIFT (14U) -/*! SWT14 - Software trigger 14 event - * 0b0..No trigger 14 event generated. - * 0b1..Trigger 14 event generated. - */ -#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) -#define ADC_SWTRIG_SWT15_MASK (0x8000U) -#define ADC_SWTRIG_SWT15_SHIFT (15U) -/*! SWT15 - Software trigger 15 event - * 0b0..No trigger 15 event generated. - * 0b1..Trigger 15 event generated. - */ -#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK) -/*! @} */ - -/*! @name TSTAT - Trigger Status Register */ -/*! @{ */ -#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) -#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) -/*! TEXC_NUM - Trigger Exception Number - * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. - * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception. - * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception. - * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception. - * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. - */ -#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) -#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) -#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) -/*! TCOMP_FLAG - Trigger Completion Flag - * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled. - * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. - * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. - * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts. - * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. - */ -#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) -/*! @} */ - -/*! @name OFSTRIM - ADC Offset Trim Register */ -/*! @{ */ -#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) -#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) -#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) -#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) -#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) -#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) -/*! @} */ - -/*! @name TCTRL - Trigger Control Register */ -/*! @{ */ -#define ADC_TCTRL_HTEN_MASK (0x1U) -#define ADC_TCTRL_HTEN_SHIFT (0U) -/*! HTEN - Trigger enable - * 0b0..Hardware trigger source disabled - * 0b1..Hardware trigger source enabled - */ -#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) -#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) -#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) -/*! FIFO_SEL_A - SAR Result Destination For Channel A - * 0b0..Result written to FIFO 0 - * 0b1..Result written to FIFO 1 - */ -#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) -#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) -#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) -/*! FIFO_SEL_B - SAR Result Destination For Channel B - * 0b0..Result written to FIFO 0 - * 0b1..Result written to FIFO 1 - */ -#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) -#define ADC_TCTRL_TPRI_MASK (0xF00U) -#define ADC_TCTRL_TPRI_SHIFT (8U) -/*! TPRI - Trigger priority setting - * 0b0000..Set to highest priority, Level 1 - * 0b0001-0b1110..Set to corresponding priority level - * 0b1111..Set to lowest priority, Level 16 - */ -#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) -#define ADC_TCTRL_RSYNC_MASK (0x8000U) -#define ADC_TCTRL_RSYNC_SHIFT (15U) -#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) -#define ADC_TCTRL_TDLY_MASK (0xF0000U) -#define ADC_TCTRL_TDLY_SHIFT (16U) -#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) -#define ADC_TCTRL_TCMD_MASK (0xF000000U) -#define ADC_TCTRL_TCMD_SHIFT (24U) -/*! TCMD - Trigger command select - * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. - * 0b0001..CMD1 is executed - * 0b0010-0b1110..Corresponding CMD is executed - * 0b1111..CMD15 is executed - */ -#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) -/*! @} */ - -/* The count of ADC_TCTRL */ -#define ADC_TCTRL_COUNT (16U) - -/*! @name FCTRL - FIFO Control Register */ -/*! @{ */ -#define ADC_FCTRL_FCOUNT_MASK (0x1FU) -#define ADC_FCTRL_FCOUNT_SHIFT (0U) -#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) -#define ADC_FCTRL_FWMARK_MASK (0xF0000U) -#define ADC_FCTRL_FWMARK_SHIFT (16U) -#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) -/*! @} */ - -/* The count of ADC_FCTRL */ -#define ADC_FCTRL_COUNT (2U) - -/*! @name GCC - Gain Calibration Control */ -/*! @{ */ -#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) -#define ADC_GCC_GAIN_CAL_SHIFT (0U) -#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) -#define ADC_GCC_RDY_MASK (0x1000000U) -#define ADC_GCC_RDY_SHIFT (24U) -/*! RDY - Gain Calibration Value Valid - * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. - * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. - */ -#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) -/*! @} */ - -/* The count of ADC_GCC */ -#define ADC_GCC_COUNT (2U) - -/*! @name GCR - Gain Calculation Result */ -/*! @{ */ -#define ADC_GCR_GCALR_MASK (0xFFFFU) -#define ADC_GCR_GCALR_SHIFT (0U) -#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) -#define ADC_GCR_RDY_MASK (0x1000000U) -#define ADC_GCR_RDY_SHIFT (24U) -/*! RDY - Gain Calculation Ready - * 0b0..The gain offset calculation value is invalid. - * 0b1..The gain calibration value is valid. - */ -#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) -/*! @} */ - -/* The count of ADC_GCR */ -#define ADC_GCR_COUNT (2U) - -/*! @name CMDL - ADC Command Low Buffer Register */ -/*! @{ */ -#define ADC_CMDL_ADCH_MASK (0x1FU) -#define ADC_CMDL_ADCH_SHIFT (0U) -/*! ADCH - Input channel select - * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. - * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. - * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. - * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. - * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. - * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. - */ -#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) -#define ADC_CMDL_CTYPE_MASK (0x60U) -#define ADC_CMDL_CTYPE_SHIFT (5U) -/*! CTYPE - Conversion Type - * 0b00..Single-Ended Mode. Only A side channel is converted. - * 0b01..Single-Ended Mode. Only B side channel is converted. - * 0b10..Differential Mode. A-B. - * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - */ -#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) -#define ADC_CMDL_MODE_MASK (0x80U) -#define ADC_CMDL_MODE_SHIFT (7U) -/*! MODE - Select resolution of conversions - * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - */ -#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) -/*! @} */ - -/* The count of ADC_CMDL */ -#define ADC_CMDL_COUNT (15U) - -/*! @name CMDH - ADC Command High Buffer Register */ -/*! @{ */ -#define ADC_CMDH_CMPEN_MASK (0x3U) -#define ADC_CMDH_CMPEN_SHIFT (0U) -/*! CMPEN - Compare Function Enable - * 0b00..Compare disabled. - * 0b01..Reserved - * 0b10..Compare enabled. Store on true. - * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - */ -#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) -#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) -#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) -/*! WAIT_TRIG - Wait for trigger assertion before execution. - * 0b0..This command will be automatically executed. - * 0b1..The active trigger must be asserted again before executing this command. - */ -#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) -#define ADC_CMDH_LWI_MASK (0x80U) -#define ADC_CMDH_LWI_SHIFT (7U) -/*! LWI - Loop with Increment - * 0b0..Auto channel increment disabled - * 0b1..Auto channel increment enabled - */ -#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) -#define ADC_CMDH_STS_MASK (0x700U) -#define ADC_CMDH_STS_SHIFT (8U) -/*! STS - Sample Time Select - * 0b000..Minimum sample time of 3 ADCK cycles. - * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - */ -#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) -#define ADC_CMDH_AVGS_MASK (0x7000U) -#define ADC_CMDH_AVGS_SHIFT (12U) -/*! AVGS - Hardware Average Select - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) -#define ADC_CMDH_LOOP_MASK (0xF0000U) -#define ADC_CMDH_LOOP_SHIFT (16U) -/*! LOOP - Loop Count Select - * 0b0000..Looping not enabled. Command executes 1 time. - * 0b0001..Loop 1 time. Command executes 2 times. - * 0b0010..Loop 2 times. Command executes 3 times. - * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. - * 0b1111..Loop 15 times. Command executes 16 times. - */ -#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) -#define ADC_CMDH_NEXT_MASK (0xF000000U) -#define ADC_CMDH_NEXT_SHIFT (24U) -/*! NEXT - Next Command Select - * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - * 0b0001..Select CMD1 command buffer register as next command. - * 0b0010-0b1110..Select corresponding CMD command buffer register as next command - * 0b1111..Select CMD15 command buffer register as next command. - */ -#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) -/*! @} */ - -/* The count of ADC_CMDH */ -#define ADC_CMDH_COUNT (15U) - -/*! @name CV - Compare Value Register */ -/*! @{ */ -#define ADC_CV_CVL_MASK (0xFFFFU) -#define ADC_CV_CVL_SHIFT (0U) -#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) -#define ADC_CV_CVH_MASK (0xFFFF0000U) -#define ADC_CV_CVH_SHIFT (16U) -#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) -/*! @} */ - -/* The count of ADC_CV */ -#define ADC_CV_COUNT (4U) - -/*! @name RESFIFO - ADC Data Result FIFO Register */ -/*! @{ */ -#define ADC_RESFIFO_D_MASK (0xFFFFU) -#define ADC_RESFIFO_D_SHIFT (0U) -#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) -#define ADC_RESFIFO_TSRC_MASK (0xF0000U) -#define ADC_RESFIFO_TSRC_SHIFT (16U) -/*! TSRC - Trigger Source - * 0b0000..Trigger source 0 initiated this conversion. - * 0b0001..Trigger source 1 initiated this conversion. - * 0b0010-0b1110..Corresponding trigger source initiated this conversion. - * 0b1111..Trigger source 15 initiated this conversion. - */ -#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) -#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) -#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) -/*! LOOPCNT - Loop count value - * 0b0000..Result is from initial conversion in command. - * 0b0001..Result is from second conversion in command. - * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. - * 0b1111..Result is from 16th conversion in command. - */ -#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) -#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) -#define ADC_RESFIFO_CMDSRC_SHIFT (24U) -/*! CMDSRC - Command Buffer Source - * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. - * 0b0001..CMD1 buffer used as control settings for this conversion. - * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. - * 0b1111..CMD15 buffer used as control settings for this conversion. - */ -#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) -#define ADC_RESFIFO_VALID_MASK (0x80000000U) -#define ADC_RESFIFO_VALID_SHIFT (31U) -/*! VALID - FIFO entry is valid - * 0b0..FIFO is empty. Discard any read from RESFIFO. - * 0b1..FIFO record read from RESFIFO is valid. - */ -#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) -/*! @} */ - -/* The count of ADC_RESFIFO */ -#define ADC_RESFIFO_COUNT (2U) - -/*! @name CAL_GAR - Calibration General A-Side Registers */ -/*! @{ */ -#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) -#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) -#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) -/*! @} */ - -/* The count of ADC_CAL_GAR */ -#define ADC_CAL_GAR_COUNT (33U) - -/*! @name CAL_GBR - Calibration General B-Side Registers */ -/*! @{ */ -#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) -#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) -#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) -/*! @} */ - -/* The count of ADC_CAL_GBR */ -#define ADC_CAL_GBR_COUNT (33U) - -/*! @name TST - ADC Test Register */ -/*! @{ */ -#define ADC_TST_CST_LONG_MASK (0x1U) -#define ADC_TST_CST_LONG_SHIFT (0U) -/*! CST_LONG - Calibration Sample Time Long - * 0b0..Normal sample time. Minimum sample time of 3 ADCK cycles. - * 0b1..Increased sample time. 67 ADCK cycles total sample time. - */ -#define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK) -#define ADC_TST_FOFFM_MASK (0x100U) -#define ADC_TST_FOFFM_SHIFT (8U) -/*! FOFFM - Force M-side positive offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced positive offset on MDAC. - */ -#define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK) -#define ADC_TST_FOFFP_MASK (0x200U) -#define ADC_TST_FOFFP_SHIFT (9U) -/*! FOFFP - Force P-side positive offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced positive offset on PDAC. - */ -#define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK) -#define ADC_TST_FOFFM2_MASK (0x400U) -#define ADC_TST_FOFFM2_SHIFT (10U) -/*! FOFFM2 - Force M-side negative offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced negative offset on MDAC. - */ -#define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK) -#define ADC_TST_FOFFP2_MASK (0x800U) -#define ADC_TST_FOFFP2_SHIFT (11U) -/*! FOFFP2 - Force P-side negative offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced negative offset on PDAC. - */ -#define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK) -#define ADC_TST_TESTEN_MASK (0x800000U) -#define ADC_TST_TESTEN_SHIFT (23U) -/*! TESTEN - Enable test configuration - * 0b0..Normal operation. Test configuration not enabled. - * 0b1..Hardware BIST Test in progress. - */ -#define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral ADC0 base address */ - #define ADC0_BASE (0x500A0000u) - /** Peripheral ADC0 base address */ - #define ADC0_BASE_NS (0x400A0000u) - /** Peripheral ADC0 base pointer */ - #define ADC0 ((ADC_Type *)ADC0_BASE) - /** Peripheral ADC0 base pointer */ - #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS { ADC0_BASE } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS { ADC0 } - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS_NS { ADC0_NS } -#else - /** Peripheral ADC0 base address */ - #define ADC0_BASE (0x400A0000u) - /** Peripheral ADC0 base pointer */ - #define ADC0 ((ADC_Type *)ADC0_BASE) - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS { ADC0_BASE } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS { ADC0 } -#endif -/** Interrupt vectors for the ADC peripheral type */ -#define ADC_IRQS { ADC0_IRQn } - -/*! - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- AHB_SECURE_CTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer - * @{ - */ - -/** AHB_SECURE_CTRL - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x30 */ - __IO uint32_t SLAVE_RULE; /**< , array offset: 0x0, array step: 0x30 */ - uint8_t RESERVED_0[12]; - __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */ - } SEC_CTRL_FLASH_ROM[1]; - struct { /* offset: 0x30, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< , array offset: 0x40, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAMX[1]; - uint8_t RESERVED_0[12]; - struct { /* offset: 0x50, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< , array offset: 0x60, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM0[1]; - uint8_t RESERVED_1[8]; - struct { /* offset: 0x70, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< , array offset: 0x80, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM1[1]; - uint8_t RESERVED_2[8]; - struct { /* offset: 0x90, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< , array offset: 0xA0, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM2[1]; - uint8_t RESERVED_3[8]; - struct { /* offset: 0xB0, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< , array offset: 0xC0, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM3[1]; - uint8_t RESERVED_4[8]; - struct { /* offset: 0xD0, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< , array offset: 0xE0, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAM4[1]; - uint8_t RESERVED_5[12]; - struct { /* offset: 0xF0, array step: 0x30 */ - __IO uint32_t SLAVE_RULE; /**< , array offset: 0xF0, array step: 0x30 */ - uint8_t RESERVED_0[12]; - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL3; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x10C, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */ - } SEC_CTRL_APB_BRIDGE[1]; - __IO uint32_t SEC_CTRL_AHB0_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */ - __IO uint32_t SEC_CTRL_AHB0_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */ - uint8_t RESERVED_6[8]; - __IO uint32_t SEC_CTRL_AHB1_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */ - __IO uint32_t SEC_CTRL_AHB1_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */ - uint8_t RESERVED_7[12]; - struct { /* offset: 0x144, array step: 0x14 */ - __IO uint32_t SEC_CTRL_AHB2_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */ - __IO uint32_t SEC_CTRL_AHB2_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., array offset: 0x148, array step: 0x14 */ - uint8_t RESERVED_0[8]; - __IO uint32_t SEC_CTRL_AHB2_0_MEM_RULE[1]; /**< , array offset: 0x154, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_AHB2[1]; - uint8_t RESERVED_8[8]; - struct { /* offset: 0x160, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< , array offset: 0x160, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< , array offset: 0x170, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_USB_HS[1]; - uint8_t RESERVED_9[3212]; - __I uint32_t SEC_VIO_ADDR[18]; /**< most recent security violation address for AHB layer n, array offset: 0xE00, array step: 0x4 */ - uint8_t RESERVED_10[56]; - __I uint32_t SEC_VIO_MISC_INFO[18]; /**< most recent security violation miscellaneous information for AHB layer n, array offset: 0xE80, array step: 0x4 */ - uint8_t RESERVED_11[56]; - __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ - uint8_t RESERVED_12[124]; - __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins. This register is used to block leakage of Secure interface (GPIOs, I2C, UART configured as secure peripherals) pin states to non-secure world., offset: 0xF80 */ - __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */ - __IO uint32_t SEC_GPIO_MASK2; /**< Secure GPIO mask for port 2 pins., offset: 0xF88 */ - __IO uint32_t SEC_GPIO_MASK3; /**< Secure GPIO mask for port 3 pins., offset: 0xF8C */ - __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */ - __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */ - uint8_t RESERVED_13[36]; - __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */ - uint8_t RESERVED_14[16]; - __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ - __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ - uint8_t RESERVED_15[20]; - __IO uint32_t CM33_LOCK_REG; /**< Miscalleneous control signals for in CM33 (CPU0), offset: 0xFEC */ - __IO uint32_t MCM33_LOCK_REG; /**< Miscalleneous control signals for in micro-CM33 (CPU1), offset: 0xFF0 */ - uint8_t RESERVED_16[4]; - __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ - __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ -} AHB_SECURE_CTRL_Type; - -/* ---------------------------------------------------------------------------- - -- AHB_SECURE_CTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks - * @{ - */ - -/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) -/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) -/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U) - -/*! @name SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) - -/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) -/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) -/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_SHIFT (0U) -/*! RAM0_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) -/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U) -/*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U) -/*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) -/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) -/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) -/*! SYSCON_RULE - System Configuration - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) -/*! IOCON_RULE - I/O Configuration - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) -/*! GINT0_RULE - GPIO input Interrupt 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) -/*! GINT1_RULE - GPIO input Interrupt 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) -/*! PINT_RULE - Pin Interrupt and Pattern match - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) -/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_SHIFT (24U) -/*! PMUX_RULE - Peripherals mux - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) -/*! CTIMER0_RULE - Standard counter/Timer 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) -/*! CTIMER1_RULE - Standard counter/Timer 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) -/*! WWDT_RULE - Windiwed wtachdog Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) -/*! MRT_RULE - Multi-rate Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) -/*! UTICK_RULE - Micro-Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) -/*! ANACTRL_RULE - Analog Modules controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_SHIFT (20U) -/*! EFUSE_RULE - eFUSE (One Time Programmable) memory controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_CAPTOUCH_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_CAPTOUCH_RULE_SHIFT (8U) -/*! CAPTOUCH_RULE - Capacitive Touch controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_CAPTOUCH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_CAPTOUCH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_CAPTOUCH_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_EZH_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_EZH_RULE_SHIFT (20U) -/*! EZH_RULE - EZH slave interface - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_EZH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_EZH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_EZH_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) -/*! PMC_RULE - Power Management Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PVT_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PVT_RULE_SHIFT (8U) -/*! PVT_RULE - Process and Voltage Monitoring controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PVT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PVT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PVT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) -/*! SYSCTRL_RULE - System Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) -/*! CTIMER2_RULE - Standard counter/Timer 2 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) -/*! CTIMER3_RULE - Standard counter/Timer 3 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) -/*! CTIMER4_RULE - Standard counter/Timer 4 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) -/*! RTC_RULE - Real Time Counter - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) -/*! OSEVENT_RULE - OS Event Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) -/*! FLASH_CTRL_RULE - Flash Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) -/*! PRINCE_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) -/*! USBHPHY_RULE - USB High Speed Phy controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) -/*! RNG_RULE - True Random Number Generator - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_SHIFT (12U) -/*! PUFF_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) -/*! PLU_RULE - Programmable Look-Up logic - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_ROMPC_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_ROMPC_RULE_SHIFT (24U) -/*! ROMPC_RULE - ROM patch controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_ROMPC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_ROMPC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_ROMPC_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) - -/*! @name SEC_CTRL_AHB0_0_SLAVE_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_SHIFT (8U) -/*! DMA0_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_SHIFT (16U) -/*! FS_USB_DEV_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_SHIFT (20U) -/*! SCT_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_SHIFT (24U) -/*! FLEXCOMM0_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_SHIFT (28U) -/*! FLEXCOMM1_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB0_1_SLAVE_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_SHIFT (0U) -/*! FLEXCOMM2_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_SHIFT (4U) -/*! FLEXCOMM3_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_SHIFT (8U) -/*! FLEXCOMM4_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_SHIFT (12U) -/*! MAILBOX_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_SHIFT (16U) -/*! GPIO0_RULE - High Speed GPIO - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB1_0_SLAVE_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_SHIFT (16U) -/*! USB_HS_DEV_RULE - USB high Speed device registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_SHIFT (20U) -/*! CRC_RULE - CRC engine - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_SHIFT (24U) -/*! FLEXCOMM5_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_SHIFT (28U) -/*! FLEXCOMM6_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB1_1_SLAVE_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_SHIFT (0U) -/*! FLEXCOMM7_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_SHIFT (12U) -/*! SDIO_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_SHIFT (16U) -/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_SHIFT (28U) -/*! HS_LSPI_RULE - High Speed SPI - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_SHIFT (0U) -/*! ADC_RULE - ADC - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_SHIFT (8U) -/*! USB_FS_HOST_RULE - USB Full Speed Host registers. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_SHIFT (12U) -/*! USB_HS_HOST_RULE - USB High speed host registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_SHIFT (16U) -/*! HASH_RULE - SHA-2 crypto registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_SHIFT (20U) -/*! CASPER_RULE - RSA/ECC crypto accelerator - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_SHIFT (24U) -/*! PQ_RULE - Power Quad (CM33 processor hardware accelerator) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_SHIFT (28U) -/*! DMA1_RULE - DMA Controller (Secure) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_SHIFT (0U) -/*! GPIO1_RULE - Secure High Speed GPIO - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) -/*! AHB_SEC_CTRL_RULE - AHB Secure Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) -/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) -/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) -/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) -/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) -/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) -/*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) -/*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) -/*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) -/*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_VIO_ADDR - most recent security violation address for AHB layer n */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (18U) - -/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB layer n */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (18U) - -/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT (12U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT (13U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT (14U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT (15U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT (16U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT (17U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. This register is used to block leakage of Secure interface (GPIOs, I2C, UART configured as secure peripherals) pin states to non-secure world. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK2 - Secure GPIO mask for port 2 pins. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK_SHIFT (1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK_SHIFT (2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK_SHIFT (3U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK_SHIFT (5U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK_SHIFT (6U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK_SHIFT (7U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK_SHIFT (8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK_SHIFT (9U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK_SHIFT (10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK_SHIFT (11U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK_SHIFT (12U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK_SHIFT (13U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK_SHIFT (14U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK_SHIFT (15U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK_SHIFT (16U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK_SHIFT (17U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK_SHIFT (18U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK_SHIFT (19U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK_SHIFT (20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK_SHIFT (21U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK_SHIFT (22U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK_SHIFT (23U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK_SHIFT (24U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK_SHIFT (25U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK_SHIFT (26U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK_SHIFT (27U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK_SHIFT (28U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK_SHIFT (29U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK_SHIFT (30U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK_SHIFT (31U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK3 - Secure GPIO mask for port 3 pins. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_SHIFT (1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_SHIFT (2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_SHIFT (3U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_SHIFT (5U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_SHIFT (24U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_EZH_ARCH_B_IRQ_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_EZH_ARCH_B_IRQ_SHIFT (30U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_EZH_ARCH_B_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_EZH_ARCH_B_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_EZH_ARCH_B_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK) -/*! @} */ - -/*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_SHIFT (14U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_SHIFT (24U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_AMBER_IRQ_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_AMBER_IRQ_SHIFT (28U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_AMBER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_AMBER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_AMBER_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_RED_IRQ_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_RED_IRQ_SHIFT (29U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_RED_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_RED_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_RED_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_AMBER_IRQ_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_AMBER_IRQ_SHIFT (30U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_AMBER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_AMBER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_AMBER_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_RED_IRQ_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_RED_IRQ_SHIFT (31U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_RED_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_RED_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_RED_IRQ_MASK) -/*! @} */ - -/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK_MASK) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK_MASK (0xC0U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK_SHIFT (6U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK_MASK) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK) -/*! @} */ - -/*! @name MASTER_SEC_LEVEL - master secure level register */ -/*! @{ */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_MASK (0x30U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_SHIFT (4U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_MASK (0xC0U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_SHIFT (6U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_D_MASK (0x3000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_D_SHIFT (12U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_D(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_D_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_D_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_I_MASK (0xC000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_I_SHIFT (14U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_I(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_I_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_I_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) -/*! @} */ - -/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ -/*! @{ */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_MASK (0x30U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_SHIFT (4U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_MASK (0xC0U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_SHIFT (6U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_MASK (0x3000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_SHIFT (12U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_D(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_MASK (0xC000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_SHIFT (14U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_I(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) -/*! @} */ - -/*! @name CM33_LOCK_REG - Miscalleneous control signals for in CM33 (CPU0) */ -/*! @{ */ -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT (6U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK (0x300U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT (8U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT (30U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK) -/*! @} */ - -/*! @name MCM33_LOCK_REG - Miscalleneous control signals for in micro-CM33 (CPU1) */ -/*! @{ */ -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_MASK) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_MASK) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_SHIFT (30U) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_MASK) -/*! @} */ - -/*! @name MISC_CTRL_DP_REG - secure control duplicate register */ -/*! @{ */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) -/*! @} */ - -/*! @name MISC_CTRL_REG - secure control register */ -/*! @{ */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group AHB_SECURE_CTRL_Register_Masks */ - - -/* AHB_SECURE_CTRL - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE (0x500AC000u) - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } -#else - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE (0x400AC000u) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } -#endif - -/*! - * @} - */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ANACTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer - * @{ - */ - -/** ANACTRL - Register Layout Typedef */ -typedef struct { - __IO uint32_t ANALOG_CTRL_CFG; /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */ - __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */ - __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */ - __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ - __IO uint32_t ADC_CTRL; /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */ - uint8_t RESERVED_1[4]; - __IO uint32_t XO32M_CTRL; /**< 32 MHz Crystal Oscillator Control register, offset: 0x20 */ - __I uint32_t XO32M_STATUS; /**< 32 MHz Crystal Oscillator Status register, offset: 0x24 */ - uint8_t RESERVED_2[8]; - __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ - __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ - uint8_t RESERVED_3[8]; - __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */ - __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */ - __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */ - uint8_t RESERVED_4[100]; - __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */ - uint8_t RESERVED_5[12]; - __IO uint32_t XO_CAL_CFG; /**< All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register, offset: 0xC0 */ - __IO uint32_t XO_CAL_CMD; /**< All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register., offset: 0xC4 */ - __I uint32_t XO_CAL_STATUS; /**< All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register., offset: 0xC8 */ - uint8_t RESERVED_6[52]; - __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */ - __IO uint32_t USBHS_PHY_TRIM; /**< USB High Speed Phy Trim values, offset: 0x104 */ - __I uint32_t USBHS_PHY_STATUS; /**< USB High Speed Phy Status, offset: 0x108 */ -} ANACTRL_Type; - -/* ---------------------------------------------------------------------------- - -- ANACTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks - * @{ - */ - -/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */ -/*! @{ */ -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U) -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U) -/*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. - * 0b0..FRO192M trimming and 'Enable' comes from eFUSE. - * 0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. - */ -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK) -/*! @} */ - -/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ -/*! @{ */ -#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK (0x3FU) -#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_SHIFT (0U) -#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK) -#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK (0xFC0U) -#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_SHIFT (6U) -#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) -/*! FLASH_PWRDWN - Flash Power Down status. - * 0b0..Flash is not in power down mode. - * 0b1..Flash is in power down mode. - */ -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) -/*! FLASH_INIT_ERROR - Flash initialization error status. - * 0b0..No error. - * 0b1..At least one error occured during flash initialization.. - */ -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) -#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK (0xF0000000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_SHIFT (28U) -#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK) -/*! @} */ - -/*! @name FREQ_ME_CTRL - Frequency Measure function control register */ -/*! @{ */ -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) -#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) -#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) -#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) -/*! @} */ - -/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ -/*! @{ */ -#define ANACTRL_FRO192M_CTRL_BIAS_TRIM_MASK (0x3FU) -#define ANACTRL_FRO192M_CTRL_BIAS_TRIM_SHIFT (0U) -#define ANACTRL_FRO192M_CTRL_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_BIAS_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_BIAS_TRIM_MASK) -#define ANACTRL_FRO192M_CTRL_TEMP_TRIM_MASK (0x3F80U) -#define ANACTRL_FRO192M_CTRL_TEMP_TRIM_SHIFT (7U) -#define ANACTRL_FRO192M_CTRL_TEMP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_TEMP_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_TEMP_TRIM_MASK) -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) -/*! ENA_12MHZCLK - 12 MHz clock control. - * 0b0..12 MHz clock is disabled. - * 0b1..12 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) -#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U) -#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U) -/*! ENA_48MHZCLK - 48 MHz clock control. - * 0b0..48 MHz clock is disabled. - * 0b1..48 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK) -#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) -#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) -#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) -#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) -#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) -#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) -#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) -#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) -#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) -#define ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK (0x30000000U) -#define ANACTRL_FRO192M_CTRL_ATB_CTRL_SHIFT (28U) -#define ANACTRL_FRO192M_CTRL_ATB_CTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ATB_CTRL_SHIFT)) & ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK) -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) -/*! ENA_96MHZCLK - 96 MHz clock control. - * 0b0..96 MHz clock is disabled. - * 0b1..96 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) -#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U) -#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U) -#define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK) -/*! @} */ - -/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ -/*! @{ */ -#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) -#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) -/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. - * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). - * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). - */ -#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) -/*! @} */ - -/*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */ -/*! @{ */ -#define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK (0x1U) -#define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT (0U) -/*! VBATDIVENABLE - Switch On/Off VBAT divider branch. - * 0b0..VBAT divider branch is disabled. - * 0b1..VBAT divider branch is enabled. - */ -#define ANACTRL_ADC_CTRL_VBATDIVENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK) -/*! @} */ - -/*! @name XO32M_CTRL - 32 MHz Crystal Oscillator Control register */ -/*! @{ */ -#define ANACTRL_XO32M_CTRL_GM_MASK (0xEU) -#define ANACTRL_XO32M_CTRL_GM_SHIFT (1U) -#define ANACTRL_XO32M_CTRL_GM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_GM_SHIFT)) & ANACTRL_XO32M_CTRL_GM_MASK) -#define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U) -#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U) -#define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK) -#define ANACTRL_XO32M_CTRL_AMP_MASK (0xE0U) -#define ANACTRL_XO32M_CTRL_AMP_SHIFT (5U) -#define ANACTRL_XO32M_CTRL_AMP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_AMP_SHIFT)) & ANACTRL_XO32M_CTRL_AMP_MASK) -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK) -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK) -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) -/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. - * 0b0..XO AC buffer bypass is disabled. - * 0b1..XO AC buffer bypass is enabled. - */ -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) -/*! ENABLE_PLL_USB_OUT - Enable XO 32 MHz output to USB HS PLL. - * 0b0..XO 32 MHz output to USB HS PLL is disabled. - * 0b1..XO 32 MHz output to USB HS PLL is enabled. - */ -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) -/*! ENABLE_SYSTEM_CLK_OUT - Enable XO 32 MHz output to CPU system. - * 0b0..XO 32 MHz output to CPU system is disabled. - * 0b1..XO 32 MHz output to CPU system is enabled. - */ -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) -#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_MASK (0x2000000U) -#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_SHIFT (25U) -/*! CAPTESTSTARTSRCSEL - Source selection for 'xo32k_captest_start' signal. - * 0b0..Sourced from CAPTESTSTART. - * 0b1..Sourced from calibration. - */ -#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_MASK) -#define ANACTRL_XO32M_CTRL_CAPTESTSTART_MASK (0x4000000U) -#define ANACTRL_XO32M_CTRL_CAPTESTSTART_SHIFT (26U) -#define ANACTRL_XO32M_CTRL_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTSTART_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTSTART_MASK) -#define ANACTRL_XO32M_CTRL_CAPTESTENABLE_MASK (0x8000000U) -#define ANACTRL_XO32M_CTRL_CAPTESTENABLE_SHIFT (27U) -/*! CAPTESTENABLE - Enable signal for captest. - * 0b0..Captest is disabled. - * 0b1..Captest is enabled. - */ -#define ANACTRL_XO32M_CTRL_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTENABLE_MASK) -#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_MASK (0x10000000U) -#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_SHIFT (28U) -/*! CAPTESTOSCINSEL - Select the input for test. - * 0b0..osc_out (oscillator output) pin. - * 0b1..osc_in (oscillator) pin. - */ -#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_MASK) -/*! @} */ - -/*! @name XO32M_STATUS - 32 MHz Crystal Oscillator Status register */ -/*! @{ */ -#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) -#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) -/*! XO_READY - Indicates XO out frequency statibilty. - * 0b0..XO output frequency is not yet stable. - * 0b1..XO output frequency is stable. - */ -#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) -/*! @} */ - -/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ -/*! @{ */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) -/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. - * 0b0..BOD VBAT interrupt is disabled. - * 0b1..BOD VBAT interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) -/*! BODCORE_INT_ENABLE - BOD CORE interrupt control. - * 0b0..BOD CORE interrupt is disabled. - * 0b1..BOD CORE interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) -/*! DCDC_INT_ENABLE - DCDC interrupt control. - * 0b0..DCDC interrupt is disabled. - * 0b1..DCDC interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) -/*! @} */ - -/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ -/*! @{ */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) -/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) -/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) -/*! BODVBAT_VAL - Current value of BOD VBAT power status output. - * 0b0..VBAT voltage level is below the threshold. - * 0b1..VBAT voltage level is above the threshold. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) -/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) -/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) -/*! BODCORE_VAL - Current value of BOD CORE power status output. - * 0b0..CORE voltage level is below the threshold. - * 0b1..CORE voltage level is above the threshold. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) -/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) -/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) -/*! DCDC_VAL - Current value of DCDC power status output. - * 0b0..DCDC output Voltage is below the targeted regulation level. - * 0b1..DCDC output Voltage is above the targeted regulation level. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) -/*! @} */ - -/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */ -/*! @{ */ -#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U) -#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U) -/*! SL - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK) -#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK) -#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU) -#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U) -/*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. - * 0b00..Normal mode. - * 0b01..P-Monitor mode. Measure with weak P transistor. - * 0b10..P-Monitor mode. Measure with weak N transistor. - * 0b11..Don't use. - */ -#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK) -#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U) -#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK) -#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U) -#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U) -/*! E_ND0 - First NAND2-based ringo control. - * 0b0..First NAND2-based ringo is disabled. - * 0b1..First NAND2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK) -#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U) -#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U) -/*! E_ND1 - Second NAND2-based ringo control. - * 0b0..Second NAND2-based ringo is disabled. - * 0b1..Second NAND2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK) -#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U) -#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U) -/*! E_NR0 - First NOR2-based ringo control. - * 0b0..First NOR2-based ringo is disabled. - * 0b1..First NOR2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK) -#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U) -#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U) -/*! E_NR1 - Second NOR2-based ringo control. - * 0b0..Second NORD2-based ringo is disabled. - * 0b1..Second NORD2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK) -#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U) -#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U) -/*! E_IV0 - First Inverter-based ringo control. - * 0b0..First INV-based ringo is disabled. - * 0b1..First INV-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK) -#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U) -#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U) -/*! E_IV1 - Second Inverter-based ringo control. - * 0b0..Second INV-based ringo is disabled. - * 0b1..Second INV-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK) -#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U) -#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U) -/*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. - * 0b0..First PN-based ringo is disabled. - * 0b1..First PN-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK) -#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U) -#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U) -/*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. - * 0b0..Second PN-based ringo is disabled. - * 0b1..Second PN-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK) -#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U) -#define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK) -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */ -/*! @{ */ -#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U) -#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U) -/*! S - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK) -#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK) -#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U) -#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK) -#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U) -#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U) -/*! E_R24 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK) -#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U) -#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U) -/*! E_R35 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK) -#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U) -#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U) -/*! E_M2 - Metal 2 (M2) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK) -#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U) -#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U) -/*! E_M3 - Metal 3 (M3) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK) -#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U) -#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U) -/*! E_M4 - Metal 4 (M4) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK) -#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U) -#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U) -/*! E_M5 - Metal 5 (M5) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK) -#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U) -#define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK) -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */ -/*! @{ */ -#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U) -#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U) -/*! S - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK) -#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK) -#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U) -#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK) -#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U) -#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U) -/*! E_R24 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK) -#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U) -#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U) -/*! E_R35 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK) -#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U) -#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U) -/*! E_M2 - Metal 2 (M2) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK) -#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U) -#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U) -/*! E_M3 - Metal 3 (M3) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK) -#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U) -#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U) -/*! E_M4 - Metal 4 (M4) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK) -#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U) -#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U) -/*! E_M5 - Metal 5 (M5) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK) -#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U) -#define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK) -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */ -/*! @{ */ -#define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U) -#define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U) -/*! BYPASS - Activate LDO bypass. - * 0b0..Disable bypass mode (for normal operations). - * 0b1..Activate LDO bypass. - */ -#define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK) -#define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U) -#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U) -/*! HIGHZ - . - * 0b0..Output in High normal state. - * 0b1..Output in High Impedance state. - */ -#define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK) -#define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U) -#define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U) -/*! VOUT - Sets the LDO output level. - * 0b000..0.750 V. - * 0b001..0.775 V. - * 0b010..0.800 V. - * 0b011..0.825 V. - * 0b100..0.850 V. - * 0b101..0.875 V. - * 0b110..0.900 V. - * 0b111..0.925 V. - */ -#define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK) -#define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U) -#define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U) -#define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK) -#define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U) -#define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U) -#define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK) -/*! @} */ - -/*! @name XO_CAL_CFG - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register */ -/*! @{ */ -#define ANACTRL_XO_CAL_CFG_START_INV_MASK (0x1U) -#define ANACTRL_XO_CAL_CFG_START_INV_SHIFT (0U) -#define ANACTRL_XO_CAL_CFG_START_INV(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_INV_SHIFT)) & ANACTRL_XO_CAL_CFG_START_INV_MASK) -#define ANACTRL_XO_CAL_CFG_START_OVR_MASK (0x2U) -#define ANACTRL_XO_CAL_CFG_START_OVR_SHIFT (1U) -#define ANACTRL_XO_CAL_CFG_START_OVR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_OVR_SHIFT)) & ANACTRL_XO_CAL_CFG_START_OVR_MASK) -#define ANACTRL_XO_CAL_CFG_START_MASK (0x4U) -#define ANACTRL_XO_CAL_CFG_START_SHIFT (2U) -#define ANACTRL_XO_CAL_CFG_START(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_SHIFT)) & ANACTRL_XO_CAL_CFG_START_MASK) -#define ANACTRL_XO_CAL_CFG_STOP_INV_MASK (0x8U) -#define ANACTRL_XO_CAL_CFG_STOP_INV_SHIFT (3U) -#define ANACTRL_XO_CAL_CFG_STOP_INV(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_STOP_INV_SHIFT)) & ANACTRL_XO_CAL_CFG_STOP_INV_MASK) -#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END_MASK (0x10U) -#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END_SHIFT (4U) -#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_STOP_CNTR_END_SHIFT)) & ANACTRL_XO_CAL_CFG_STOP_CNTR_END_MASK) -#define ANACTRL_XO_CAL_CFG_XO32K_MODE_MASK (0x20U) -#define ANACTRL_XO_CAL_CFG_XO32K_MODE_SHIFT (5U) -/*! XO32K_MODE - When 0 : High speed crystal oscillator calibration is used. When 1 : 32 kHz crystal oscillator calibration is used. - * 0b0..High speed crystal oscillator (12 MHz- 32 MHz) is used - * 0b1..32 kHz crystal oscillator calibration is used. - */ -#define ANACTRL_XO_CAL_CFG_XO32K_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_XO32K_MODE_SHIFT)) & ANACTRL_XO_CAL_CFG_XO32K_MODE_MASK) -/*! @} */ - -/*! @name XO_CAL_CMD - All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register. */ -/*! @{ */ -#define ANACTRL_XO_CAL_CMD_START_MASK (0x1U) -#define ANACTRL_XO_CAL_CMD_START_SHIFT (0U) -#define ANACTRL_XO_CAL_CMD_START(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_START_SHIFT)) & ANACTRL_XO_CAL_CMD_START_MASK) -#define ANACTRL_XO_CAL_CMD_STOP_MASK (0x2U) -#define ANACTRL_XO_CAL_CMD_STOP_SHIFT (1U) -#define ANACTRL_XO_CAL_CMD_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_STOP_SHIFT)) & ANACTRL_XO_CAL_CMD_STOP_MASK) -#define ANACTRL_XO_CAL_CMD_OVR_MASK (0x4U) -#define ANACTRL_XO_CAL_CMD_OVR_SHIFT (2U) -#define ANACTRL_XO_CAL_CMD_OVR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_OVR_SHIFT)) & ANACTRL_XO_CAL_CMD_OVR_MASK) -/*! @} */ - -/*! @name XO_CAL_STATUS - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register. */ -/*! @{ */ -#define ANACTRL_XO_CAL_STATUS_CAL_CNTR_MASK (0xFFFFU) -#define ANACTRL_XO_CAL_STATUS_CAL_CNTR_SHIFT (0U) -#define ANACTRL_XO_CAL_STATUS_CAL_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_STATUS_CAL_CNTR_SHIFT)) & ANACTRL_XO_CAL_STATUS_CAL_CNTR_MASK) -#define ANACTRL_XO_CAL_STATUS_DONE_MASK (0x10000U) -#define ANACTRL_XO_CAL_STATUS_DONE_SHIFT (16U) -#define ANACTRL_XO_CAL_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_STATUS_DONE_SHIFT)) & ANACTRL_XO_CAL_STATUS_DONE_MASK) -/*! @} */ - -/*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */ -/*! @{ */ -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U) -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U) -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK) -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U) -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U) -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK) -#define ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK (0x8U) -#define ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT (3U) -#define ANACTRL_USBHS_PHY_CTRL_iso_atx(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK) -/*! @} */ - -/*! @name USBHS_PHY_TRIM - USB High Speed Phy Trim values */ -/*! @{ */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK (0x3U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT (0U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK (0x3CU) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT (2U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK (0x7C0U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT (6U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK (0xF800U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT (11U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK (0x30000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT (16U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK (0x1C0000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT (18U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK) -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK (0xE00000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT (21U) -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK) -/*! @} */ - -/*! @name USBHS_PHY_STATUS - USB High Speed Phy Status */ -/*! @{ */ -#define ANACTRL_USBHS_PHY_STATUS_pfd_stable_MASK (0x1U) -#define ANACTRL_USBHS_PHY_STATUS_pfd_stable_SHIFT (0U) -#define ANACTRL_USBHS_PHY_STATUS_pfd_stable(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_pfd_stable_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_pfd_stable_MASK) -#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_MASK (0x2U) -#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_SHIFT (1U) -#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_MASK (0x4U) -#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_SHIFT (2U) -#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_MASK (0x8U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_SHIFT (3U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_MASK (0x10U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_SHIFT (4U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_MASK (0x20U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_SHIFT (5U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_MASK (0x40U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_SHIFT (6U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ANACTRL_Register_Masks */ - - -/* ANACTRL - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE (0x50013000u) - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE_NS (0x40013000u) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS { ANACTRL } - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } -#else - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE (0x40013000u) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS { ANACTRL } -#endif - -/*! - * @} - */ /* end of group ANACTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CASPER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer - * @{ - */ - -/** CASPER - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */ - __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */ - __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */ - __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */ - __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */ - __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */ - __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */ - uint8_t RESERVED_0[4]; - __IO uint32_t AREG; /**< A register, offset: 0x20 */ - __IO uint32_t BREG; /**< B register, offset: 0x24 */ - __IO uint32_t CREG; /**< C register, offset: 0x28 */ - __IO uint32_t DREG; /**< D register, offset: 0x2C */ - __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */ - __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */ - __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */ - __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */ - uint8_t RESERVED_1[32]; - __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */ - __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */ - uint8_t RESERVED_2[24]; - __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */ -} CASPER_Type; - -/* ---------------------------------------------------------------------------- - -- CASPER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CASPER_Register_Masks CASPER Register Masks - * @{ - */ - -/*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */ -/*! @{ */ -#define CASPER_CTRL0_ABBPAIR_MASK (0x1U) -#define CASPER_CTRL0_ABBPAIR_SHIFT (0U) -/*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK) -#define CASPER_CTRL0_ABOFF_MASK (0x4U) -#define CASPER_CTRL0_ABOFF_SHIFT (2U) -#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK) -#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U) -#define CASPER_CTRL0_CDBPAIR_SHIFT (16U) -/*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK) -#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U) -#define CASPER_CTRL0_CDOFF_SHIFT (18U) -#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK) -/*! @} */ - -/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */ -/*! @{ */ -#define CASPER_CTRL1_ITER_MASK (0xFFU) -#define CASPER_CTRL1_ITER_SHIFT (0U) -#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK) -#define CASPER_CTRL1_MODE_MASK (0xFF00U) -#define CASPER_CTRL1_MODE_SHIFT (8U) -#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK) -#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U) -#define CASPER_CTRL1_RESBPAIR_SHIFT (16U) -/*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally this is not the same bank as ABBPAIR (when 4-up supported) - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK) -#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U) -#define CASPER_CTRL1_RESOFF_SHIFT (18U) -#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK) -#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U) -#define CASPER_CTRL1_CSKIP_SHIFT (30U) -/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: - * 0b00..No Skip - * 0b01..Skip if Carry is 1 - * 0b10..Skip if Carry is 0 - * 0b11..Set CTRLOFF to CDOFF and Skip - */ -#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK) -/*! @} */ - -/*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */ -/*! @{ */ -#define CASPER_LOADER_COUNT_MASK (0xFFU) -#define CASPER_LOADER_COUNT_SHIFT (0U) -#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK) -#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U) -#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U) -/*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not matter which bank is used as this is loaded when not performing an operation. - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK) -#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U) -#define CASPER_LOADER_CTRLOFF_SHIFT (18U) -#define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK) -/*! @} */ - -/*! @name STATUS - Indicates operational status and would contain the carry bit if used. */ -/*! @{ */ -#define CASPER_STATUS_DONE_MASK (0x1U) -#define CASPER_STATUS_DONE_SHIFT (0U) -/*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. - * 0b0..Busy or just cleared - * 0b1..Completed last operation - */ -#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK) -#define CASPER_STATUS_CARRY_MASK (0x10U) -#define CASPER_STATUS_CARRY_SHIFT (4U) -/*! CARRY - Last carry value if operation produced a carry bit - * 0b0..Carry was 0 or no carry - * 0b1..Carry was 1 - */ -#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK) -#define CASPER_STATUS_BUSY_MASK (0x20U) -#define CASPER_STATUS_BUSY_SHIFT (5U) -/*! BUSY - Indicates if the accelerator is busy performing an operation - * 0b0..Not busy - is idle - * 0b1..Is busy - */ -#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK) -/*! @} */ - -/*! @name INTENSET - Sets interrupts */ -/*! @{ */ -#define CASPER_INTENSET_DONE_MASK (0x1U) -#define CASPER_INTENSET_DONE_SHIFT (0U) -/*! DONE - Set if the accelerator should interrupt when done. - * 0b0..Do not interrupt when done - * 0b1..Interrupt when done - */ -#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK) -/*! @} */ - -/*! @name INTENCLR - Clears interrupts */ -/*! @{ */ -#define CASPER_INTENCLR_DONE_MASK (0x1U) -#define CASPER_INTENCLR_DONE_SHIFT (0U) -/*! DONE - Written to clear an interrupt set with INTENSET. - * 0b0..If written 0, ignored - * 0b1..If written 1, do not Interrupt when done - */ -#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */ -/*! @{ */ -#define CASPER_INTSTAT_DONE_MASK (0x1U) -#define CASPER_INTSTAT_DONE_SHIFT (0U) -/*! DONE - If set, interrupt is caused by accelerator being done. - * 0b0..Not caused by accelerator being done - * 0b1..Caused by accelerator being done - */ -#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK) -/*! @} */ - -/*! @name AREG - A register */ -/*! @{ */ -#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_AREG_REG_VALUE_SHIFT (0U) -#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name BREG - B register */ -/*! @{ */ -#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_BREG_REG_VALUE_SHIFT (0U) -#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name CREG - C register */ -/*! @{ */ -#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_CREG_REG_VALUE_SHIFT (0U) -#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name DREG - D register */ -/*! @{ */ -#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_DREG_REG_VALUE_SHIFT (0U) -#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES0 - Result register 0 */ -/*! @{ */ -#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES0_REG_VALUE_SHIFT (0U) -#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES1 - Result register 1 */ -/*! @{ */ -#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES1_REG_VALUE_SHIFT (0U) -#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES2 - Result register 2 */ -/*! @{ */ -#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES2_REG_VALUE_SHIFT (0U) -#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES3 - Result register 3 */ -/*! @{ */ -#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES3_REG_VALUE_SHIFT (0U) -#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK) -/*! @} */ - -/*! @name MASK - Optional mask register */ -/*! @{ */ -#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU) -#define CASPER_MASK_MASK_SHIFT (0U) -#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK) -/*! @} */ - -/*! @name REMASK - Optional re-mask register */ -/*! @{ */ -#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU) -#define CASPER_REMASK_MASK_SHIFT (0U) -#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK) -/*! @} */ - -/*! @name LOCK - Security lock register */ -/*! @{ */ -#define CASPER_LOCK_LOCK_MASK (0x1U) -#define CASPER_LOCK_LOCK_SHIFT (0U) -/*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. - * 0b0..unlock - * 0b1..Lock to current security level - */ -#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK) -#define CASPER_LOCK_KEY_MASK (0x1FFF0U) -#define CASPER_LOCK_KEY_SHIFT (4U) -/*! KEY - Must be written as 0x73D to change the register. - * 0b0011100111101..If set during write, will allow lock or unlock - */ -#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CASPER_Register_Masks */ - - -/* CASPER - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral CASPER base address */ - #define CASPER_BASE (0x500A5000u) - /** Peripheral CASPER base address */ - #define CASPER_BASE_NS (0x400A5000u) - /** Peripheral CASPER base pointer */ - #define CASPER ((CASPER_Type *)CASPER_BASE) - /** Peripheral CASPER base pointer */ - #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS) - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS { CASPER_BASE } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS { CASPER } - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS_NS { CASPER_NS } -#else - /** Peripheral CASPER base address */ - #define CASPER_BASE (0x400A5000u) - /** Peripheral CASPER base pointer */ - #define CASPER ((CASPER_Type *)CASPER_BASE) - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS { CASPER_BASE } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS { CASPER } -#endif - -/*! - * @} - */ /* end of group CASPER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer - * @{ - */ - -/** CRC - Register Layout Typedef */ -typedef struct { - __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ - union { /* offset: 0x8 */ - __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ - __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ - }; -} CRC_Type; - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/*! @name MODE - CRC mode register */ -/*! @{ */ -#define CRC_MODE_CRC_POLY_MASK (0x3U) -#define CRC_MODE_CRC_POLY_SHIFT (0U) -#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) -#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) -#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) -#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) -#define CRC_MODE_CMPL_WR_MASK (0x8U) -#define CRC_MODE_CMPL_WR_SHIFT (3U) -#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) -#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) -#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) -#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) -#define CRC_MODE_CMPL_SUM_MASK (0x20U) -#define CRC_MODE_CMPL_SUM_SHIFT (5U) -#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) -/*! @} */ - -/*! @name SEED - CRC seed register */ -/*! @{ */ -#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) -#define CRC_SEED_CRC_SEED_SHIFT (0U) -#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) -/*! @} */ - -/*! @name SUM - CRC checksum register */ -/*! @{ */ -#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) -#define CRC_SUM_CRC_SUM_SHIFT (0U) -#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) -/*! @} */ - -/*! @name WR_DATA - CRC data register */ -/*! @{ */ -#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) -#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) -#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CRC_Register_Masks */ - - -/* CRC - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE (0x50095000u) - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE_NS (0x40095000u) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS { CRC_ENGINE } - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } -#else - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE (0x40095000u) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS { CRC_ENGINE } -#endif - -/*! - * @} - */ /* end of group CRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer - * @{ - */ - -/** CTIMER - Register Layout Typedef */ -typedef struct { - __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ - __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ - __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ - __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ - __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ - __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ - __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ - __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ - __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ - __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ - uint8_t RESERVED_0[48]; - __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ - __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */ - __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ -} CTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- CTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Register_Masks CTIMER Register Masks - * @{ - */ - -/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ -/*! @{ */ -#define CTIMER_IR_MR0INT_MASK (0x1U) -#define CTIMER_IR_MR0INT_SHIFT (0U) -#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) -#define CTIMER_IR_MR1INT_MASK (0x2U) -#define CTIMER_IR_MR1INT_SHIFT (1U) -#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) -#define CTIMER_IR_MR2INT_MASK (0x4U) -#define CTIMER_IR_MR2INT_SHIFT (2U) -#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) -#define CTIMER_IR_MR3INT_MASK (0x8U) -#define CTIMER_IR_MR3INT_SHIFT (3U) -#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) -#define CTIMER_IR_CR0INT_MASK (0x10U) -#define CTIMER_IR_CR0INT_SHIFT (4U) -#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) -#define CTIMER_IR_CR1INT_MASK (0x20U) -#define CTIMER_IR_CR1INT_SHIFT (5U) -#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) -#define CTIMER_IR_CR2INT_MASK (0x40U) -#define CTIMER_IR_CR2INT_SHIFT (6U) -#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) -#define CTIMER_IR_CR3INT_MASK (0x80U) -#define CTIMER_IR_CR3INT_SHIFT (7U) -#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) -/*! @} */ - -/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ -/*! @{ */ -#define CTIMER_TCR_CEN_MASK (0x1U) -#define CTIMER_TCR_CEN_SHIFT (0U) -/*! CEN - Counter enable. - * 0b0..Disabled.The counters are disabled. - * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. - */ -#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) -#define CTIMER_TCR_CRST_MASK (0x2U) -#define CTIMER_TCR_CRST_SHIFT (1U) -/*! CRST - Counter reset. - * 0b0..Disabled. Do nothing. - * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero. - */ -#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) -/*! @} */ - -/*! @name TC - Timer Counter */ -/*! @{ */ -#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_TC_TCVAL_SHIFT (0U) -#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) -/*! @} */ - -/*! @name PR - Prescale Register */ -/*! @{ */ -#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PR_PRVAL_SHIFT (0U) -#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) -/*! @} */ - -/*! @name PC - Prescale Counter */ -/*! @{ */ -#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PC_PCVAL_SHIFT (0U) -#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) -/*! @} */ - -/*! @name MCR - Match Control Register */ -/*! @{ */ -#define CTIMER_MCR_MR0I_MASK (0x1U) -#define CTIMER_MCR_MR0I_SHIFT (0U) -#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) -#define CTIMER_MCR_MR0R_MASK (0x2U) -#define CTIMER_MCR_MR0R_SHIFT (1U) -#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) -#define CTIMER_MCR_MR0S_MASK (0x4U) -#define CTIMER_MCR_MR0S_SHIFT (2U) -#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) -#define CTIMER_MCR_MR1I_MASK (0x8U) -#define CTIMER_MCR_MR1I_SHIFT (3U) -#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) -#define CTIMER_MCR_MR1R_MASK (0x10U) -#define CTIMER_MCR_MR1R_SHIFT (4U) -#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) -#define CTIMER_MCR_MR1S_MASK (0x20U) -#define CTIMER_MCR_MR1S_SHIFT (5U) -#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) -#define CTIMER_MCR_MR2I_MASK (0x40U) -#define CTIMER_MCR_MR2I_SHIFT (6U) -#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) -#define CTIMER_MCR_MR2R_MASK (0x80U) -#define CTIMER_MCR_MR2R_SHIFT (7U) -#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) -#define CTIMER_MCR_MR2S_MASK (0x100U) -#define CTIMER_MCR_MR2S_SHIFT (8U) -#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) -#define CTIMER_MCR_MR3I_MASK (0x200U) -#define CTIMER_MCR_MR3I_SHIFT (9U) -#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) -#define CTIMER_MCR_MR3R_MASK (0x400U) -#define CTIMER_MCR_MR3R_SHIFT (10U) -#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) -#define CTIMER_MCR_MR3S_MASK (0x800U) -#define CTIMER_MCR_MR3S_SHIFT (11U) -#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) -#define CTIMER_MCR_MR0RL_MASK (0x1000000U) -#define CTIMER_MCR_MR0RL_SHIFT (24U) -#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) -#define CTIMER_MCR_MR1RL_MASK (0x2000000U) -#define CTIMER_MCR_MR1RL_SHIFT (25U) -#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) -#define CTIMER_MCR_MR2RL_MASK (0x4000000U) -#define CTIMER_MCR_MR2RL_SHIFT (26U) -#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) -#define CTIMER_MCR_MR3RL_MASK (0x8000000U) -#define CTIMER_MCR_MR3RL_SHIFT (27U) -#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) -/*! @} */ - -/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ -/*! @{ */ -#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) -#define CTIMER_MR_MATCH_SHIFT (0U) -#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) -/*! @} */ - -/* The count of CTIMER_MR */ -#define CTIMER_MR_COUNT (4U) - -/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ -/*! @{ */ -#define CTIMER_CCR_CAP0RE_MASK (0x1U) -#define CTIMER_CCR_CAP0RE_SHIFT (0U) -#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) -#define CTIMER_CCR_CAP0FE_MASK (0x2U) -#define CTIMER_CCR_CAP0FE_SHIFT (1U) -#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) -#define CTIMER_CCR_CAP0I_MASK (0x4U) -#define CTIMER_CCR_CAP0I_SHIFT (2U) -#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) -#define CTIMER_CCR_CAP1RE_MASK (0x8U) -#define CTIMER_CCR_CAP1RE_SHIFT (3U) -#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) -#define CTIMER_CCR_CAP1FE_MASK (0x10U) -#define CTIMER_CCR_CAP1FE_SHIFT (4U) -#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) -#define CTIMER_CCR_CAP1I_MASK (0x20U) -#define CTIMER_CCR_CAP1I_SHIFT (5U) -#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) -#define CTIMER_CCR_CAP2RE_MASK (0x40U) -#define CTIMER_CCR_CAP2RE_SHIFT (6U) -#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) -#define CTIMER_CCR_CAP2FE_MASK (0x80U) -#define CTIMER_CCR_CAP2FE_SHIFT (7U) -#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) -#define CTIMER_CCR_CAP2I_MASK (0x100U) -#define CTIMER_CCR_CAP2I_SHIFT (8U) -#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) -#define CTIMER_CCR_CAP3RE_MASK (0x200U) -#define CTIMER_CCR_CAP3RE_SHIFT (9U) -#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) -#define CTIMER_CCR_CAP3FE_MASK (0x400U) -#define CTIMER_CCR_CAP3FE_SHIFT (10U) -#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) -#define CTIMER_CCR_CAP3I_MASK (0x800U) -#define CTIMER_CCR_CAP3I_SHIFT (11U) -#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) -/*! @} */ - -/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ -/*! @{ */ -#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) -#define CTIMER_CR_CAP_SHIFT (0U) -#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) -/*! @} */ - -/* The count of CTIMER_CR */ -#define CTIMER_CR_COUNT (4U) - -/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ -/*! @{ */ -#define CTIMER_EMR_EM0_MASK (0x1U) -#define CTIMER_EMR_EM0_SHIFT (0U) -#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) -#define CTIMER_EMR_EM1_MASK (0x2U) -#define CTIMER_EMR_EM1_SHIFT (1U) -#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) -#define CTIMER_EMR_EM2_MASK (0x4U) -#define CTIMER_EMR_EM2_SHIFT (2U) -#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) -#define CTIMER_EMR_EM3_MASK (0x8U) -#define CTIMER_EMR_EM3_SHIFT (3U) -#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) -#define CTIMER_EMR_EMC0_MASK (0x30U) -#define CTIMER_EMR_EMC0_SHIFT (4U) -/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) -#define CTIMER_EMR_EMC1_MASK (0xC0U) -#define CTIMER_EMR_EMC1_SHIFT (6U) -/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) -#define CTIMER_EMR_EMC2_MASK (0x300U) -#define CTIMER_EMR_EMC2_SHIFT (8U) -/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) -#define CTIMER_EMR_EMC3_MASK (0xC00U) -#define CTIMER_EMR_EMC3_SHIFT (10U) -/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) -/*! @} */ - -/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ -/*! @{ */ -#define CTIMER_CTCR_CTMODE_MASK (0x3U) -#define CTIMER_CTCR_CTMODE_SHIFT (0U) -/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - * 0b00..Timer Mode. Incremented every rising APB bus clock edge. - * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. - * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. - * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. - */ -#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) -#define CTIMER_CTCR_CINSEL_MASK (0xCU) -#define CTIMER_CTCR_CINSEL_SHIFT (2U) -/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. - * 0b00..Channel 0. CAPn.0 for CTIMERn - * 0b01..Channel 1. CAPn.1 for CTIMERn - * 0b10..Channel 2. CAPn.2 for CTIMERn - * 0b11..Channel 3. CAPn.3 for CTIMERn - */ -#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) -#define CTIMER_CTCR_ENCC_MASK (0x10U) -#define CTIMER_CTCR_ENCC_SHIFT (4U) -#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) -#define CTIMER_CTCR_SELCC_MASK (0xE0U) -#define CTIMER_CTCR_SELCC_SHIFT (5U) -/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. - * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - */ -#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) -/*! @} */ - -/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ -/*! @{ */ -#define CTIMER_PWMC_PWMEN0_MASK (0x1U) -#define CTIMER_PWMC_PWMEN0_SHIFT (0U) -/*! PWMEN0 - PWM mode enable for channel0. - * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. - */ -#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) -#define CTIMER_PWMC_PWMEN1_MASK (0x2U) -#define CTIMER_PWMC_PWMEN1_SHIFT (1U) -/*! PWMEN1 - PWM mode enable for channel1. - * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. - */ -#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) -#define CTIMER_PWMC_PWMEN2_MASK (0x4U) -#define CTIMER_PWMC_PWMEN2_SHIFT (2U) -/*! PWMEN2 - PWM mode enable for channel2. - * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. - */ -#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) -#define CTIMER_PWMC_PWMEN3_MASK (0x8U) -#define CTIMER_PWMC_PWMEN3_SHIFT (3U) -/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. - * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. - * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. - */ -#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) -/*! @} */ - -/*! @name MSR - Match Shadow Register */ -/*! @{ */ -#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU) -#define CTIMER_MSR_SHADOWW_SHIFT (0U) -#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK) -/*! @} */ - -/* The count of CTIMER_MSR */ -#define CTIMER_MSR_COUNT (4U) - - -/*! - * @} - */ /* end of group CTIMER_Register_Masks */ - - -/* CTIMER - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE (0x50008000u) - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE_NS (0x40008000u) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE (0x50009000u) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE_NS (0x40009000u) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE (0x50028000u) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE_NS (0x40028000u) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE (0x50029000u) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE_NS (0x40029000u) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE (0x5002A000u) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE_NS (0x4002A000u) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } -#else - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE (0x40008000u) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE (0x40009000u) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE (0x40028000u) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE (0x40029000u) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE (0x4002A000u) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } -#endif -/** Interrupt vectors for the CTIMER peripheral type */ -#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } - -/*! - * @} - */ /* end of group CTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DGBMAILBOX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DGBMAILBOX_Peripheral_Access_Layer DGBMAILBOX Peripheral Access Layer - * @{ - */ - -/** DGBMAILBOX - Register Layout Typedef */ -typedef struct { - __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ - __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ - uint8_t RESERVED_0[240]; - __I uint32_t ID; /**< Identification register, offset: 0xFC */ -} DGBMAILBOX_Type; - -/* ---------------------------------------------------------------------------- - -- DGBMAILBOX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DGBMAILBOX_Register_Masks DGBMAILBOX Register Masks - * @{ - */ - -/*! @name CSW - CRC mode register */ -/*! @{ */ -#define DGBMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) -#define DGBMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) -#define DGBMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DGBMAILBOX_CSW_RESYNCH_REQ_MASK) -#define DGBMAILBOX_CSW_REQ_PENDING_MASK (0x2U) -#define DGBMAILBOX_CSW_REQ_PENDING_SHIFT (1U) -#define DGBMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_REQ_PENDING_SHIFT)) & DGBMAILBOX_CSW_REQ_PENDING_MASK) -#define DGBMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) -#define DGBMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) -#define DGBMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DGBMAILBOX_CSW_DBG_OR_ERR_MASK) -#define DGBMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) -#define DGBMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) -#define DGBMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DGBMAILBOX_CSW_AHB_OR_ERR_MASK) -#define DGBMAILBOX_CSW_SOFT_RESET_MASK (0x10U) -#define DGBMAILBOX_CSW_SOFT_RESET_SHIFT (4U) -#define DGBMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_SOFT_RESET_SHIFT)) & DGBMAILBOX_CSW_SOFT_RESET_MASK) -#define DGBMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) -#define DGBMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) -#define DGBMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DGBMAILBOX_CSW_CHIP_RESET_REQ_MASK) -/*! @} */ - -/*! @name REQUEST - CRC seed register */ -/*! @{ */ -#define DGBMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) -#define DGBMAILBOX_REQUEST_REQ_SHIFT (0U) -#define DGBMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_REQUEST_REQ_SHIFT)) & DGBMAILBOX_REQUEST_REQ_MASK) -/*! @} */ - -/*! @name RETURN - Return value from ROM. */ -/*! @{ */ -#define DGBMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) -#define DGBMAILBOX_RETURN_RET_SHIFT (0U) -#define DGBMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_RETURN_RET_SHIFT)) & DGBMAILBOX_RETURN_RET_MASK) -/*! @} */ - -/*! @name ID - Identification register */ -/*! @{ */ -#define DGBMAILBOX_ID_ID_MASK (0xFFFFFFFFU) -#define DGBMAILBOX_ID_ID_SHIFT (0U) -#define DGBMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_ID_ID_SHIFT)) & DGBMAILBOX_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group DGBMAILBOX_Register_Masks */ - - -/* DGBMAILBOX - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral DGBMAILBOX base address */ - #define DGBMAILBOX_BASE (0x5009C000u) - /** Peripheral DGBMAILBOX base address */ - #define DGBMAILBOX_BASE_NS (0x4009C000u) - /** Peripheral DGBMAILBOX base pointer */ - #define DGBMAILBOX ((DGBMAILBOX_Type *)DGBMAILBOX_BASE) - /** Peripheral DGBMAILBOX base pointer */ - #define DGBMAILBOX_NS ((DGBMAILBOX_Type *)DGBMAILBOX_BASE_NS) - /** Array initializer of DGBMAILBOX peripheral base addresses */ - #define DGBMAILBOX_BASE_ADDRS { DGBMAILBOX_BASE } - /** Array initializer of DGBMAILBOX peripheral base pointers */ - #define DGBMAILBOX_BASE_PTRS { DGBMAILBOX } - /** Array initializer of DGBMAILBOX peripheral base addresses */ - #define DGBMAILBOX_BASE_ADDRS_NS { DGBMAILBOX_BASE_NS } - /** Array initializer of DGBMAILBOX peripheral base pointers */ - #define DGBMAILBOX_BASE_PTRS_NS { DGBMAILBOX_NS } -#else - /** Peripheral DGBMAILBOX base address */ - #define DGBMAILBOX_BASE (0x4009C000u) - /** Peripheral DGBMAILBOX base pointer */ - #define DGBMAILBOX ((DGBMAILBOX_Type *)DGBMAILBOX_BASE) - /** Array initializer of DGBMAILBOX peripheral base addresses */ - #define DGBMAILBOX_BASE_ADDRS { DGBMAILBOX_BASE } - /** Array initializer of DGBMAILBOX peripheral base pointers */ - #define DGBMAILBOX_BASE_PTRS { DGBMAILBOX } -#endif - -/*! - * @} - */ /* end of group DGBMAILBOX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ - __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ - __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ - uint8_t RESERVED_0[20]; - struct { /* offset: 0x20, array step: 0x5C */ - __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ - uint8_t RESERVED_0[4]; - __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ - uint8_t RESERVED_1[4]; - __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ - uint8_t RESERVED_2[4]; - __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ - uint8_t RESERVED_4[4]; - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ - uint8_t RESERVED_5[4]; - __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ - uint8_t RESERVED_6[4]; - __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ - uint8_t RESERVED_7[4]; - __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ - uint8_t RESERVED_8[4]; - __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ - uint8_t RESERVED_9[4]; - __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ - uint8_t RESERVED_10[4]; - __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ - } COMMON[1]; - uint8_t RESERVED_1[900]; - struct { /* offset: 0x400, array step: 0x10 */ - __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ - __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ - __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } CHANNEL[30]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/*! @name CTRL - DMA control. */ -/*! @{ */ -#define DMA_CTRL_ENABLE_MASK (0x1U) -#define DMA_CTRL_ENABLE_SHIFT (0U) -/*! ENABLE - DMA controller master enable. - * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled. - * 0b1..Enabled. The DMA controller is enabled. - */ -#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status. */ -/*! @{ */ -#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) -#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) -/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. - * 0b0..Not pending. No enabled interrupts are pending. - * 0b1..Pending. At least one enabled interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) -#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) -#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) -/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. - * 0b0..Not pending. No error interrupts are pending. - * 0b1..Pending. At least one error interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) -/*! @} */ - -/*! @name SRAMBASE - SRAM address of the channel configuration table. */ -/*! @{ */ -#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) -#define DMA_SRAMBASE_OFFSET_SHIFT (9U) -#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) -/*! @} */ - -/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) -#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLESET */ -#define DMA_COMMON_ENABLESET_COUNT (1U) - -/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) -#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLECLR */ -#define DMA_COMMON_ENABLECLR_COUNT (1U) - -/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) -#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ACTIVE */ -#define DMA_COMMON_ACTIVE_COUNT (1U) - -/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) -#define DMA_COMMON_BUSY_BSY_SHIFT (0U) -#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) -/*! @} */ - -/* The count of DMA_COMMON_BUSY */ -#define DMA_COMMON_BUSY_COUNT (1U) - -/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) -#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ERRINT */ -#define DMA_COMMON_ERRINT_COUNT (1U) - -/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) -#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENSET */ -#define DMA_COMMON_INTENSET_COUNT (1U) - -/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) -#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENCLR */ -#define DMA_COMMON_INTENCLR_COUNT (1U) - -/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTA_IA_SHIFT (0U) -#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTA */ -#define DMA_COMMON_INTA_COUNT (1U) - -/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTB_IB_SHIFT (0U) -#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTB */ -#define DMA_COMMON_INTB_COUNT (1U) - -/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETVALID_SV_SHIFT (0U) -#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETVALID */ -#define DMA_COMMON_SETVALID_COUNT (1U) - -/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) -#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETTRIG */ -#define DMA_COMMON_SETTRIG_COUNT (1U) - -/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) -#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ABORT */ -#define DMA_COMMON_ABORT_COUNT (1U) - -/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ -/*! @{ */ -#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) -#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) -/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. - * 0b0..Disabled. Peripheral DMA requests are disabled. - * 0b1..Enabled. Peripheral DMA requests are enabled. - */ -#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) -#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) -#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) -/*! HWTRIGEN - Hardware Triggering Enable for this channel. - * 0b0..Disabled. Hardware triggering is not used. - * 0b1..Enabled. Use hardware triggering. - */ -#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) -#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) -#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) -/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. - * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. - * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. - */ -#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) -#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) -#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) -/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. - * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. - * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. - */ -#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) -#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) -#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) -/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. - * 0b0..Single transfer. Hardware trigger causes a single transfer. - * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. - */ -#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) -#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) -#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) -#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) -/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. - * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. - * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. - */ -#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) -/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. - * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. - * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. - */ -#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) -#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) -#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) -#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CFG */ -#define DMA_CHANNEL_CFG_COUNT (30U) - -/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ -/*! @{ */ -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) -/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. - * 0b0..No effect. No effect on DMA operation. - * 0b1..Valid pending. - */ -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) -#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) -#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) -/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. - * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. - * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. - */ -#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CTLSTAT */ -#define DMA_CHANNEL_CTLSTAT_COUNT (30U) - -/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ -/*! @{ */ -#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) -#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) -/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. - * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. - * 0b1..Valid. The current channel descriptor is considered valid. - */ -#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) -#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) -#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) -/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. - * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. - * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) -#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) -#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) -/*! SWTRIG - Software Trigger. - * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. - * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. - */ -#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) -/*! CLRTRIG - Clear Trigger. - * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. - * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted - */ -#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) -#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) -#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) -/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. - * 0b0..No effect. - * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) -#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) -#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) -/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. - * 0b0..No effect. - * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) -#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) -#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) -/*! WIDTH - Transfer width used for this DMA channel. - * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). - * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). - * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). - * 0b11..Reserved. Reserved setting, do not use. - */ -#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) -#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) -#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) -/*! SRCINC - Determines whether the source address is incremented for each DMA transfer. - * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. - * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. - * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. - * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. - */ -#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) -#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) -#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) -/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. - * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. - * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. - * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. - * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. - */ -#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_XFERCFG */ -#define DMA_CHANNEL_XFERCFG_COUNT (30U) - - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral DMA0 base address */ - #define DMA0_BASE (0x50082000u) - /** Peripheral DMA0 base address */ - #define DMA0_BASE_NS (0x40082000u) - /** Peripheral DMA0 base pointer */ - #define DMA0 ((DMA_Type *)DMA0_BASE) - /** Peripheral DMA0 base pointer */ - #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) - /** Peripheral DMA1 base address */ - #define DMA1_BASE (0x500A7000u) - /** Peripheral DMA1 base address */ - #define DMA1_BASE_NS (0x400A7000u) - /** Peripheral DMA1 base pointer */ - #define DMA1 ((DMA_Type *)DMA1_BASE) - /** Peripheral DMA1 base pointer */ - #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS { DMA0, DMA1 } - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } -#else - /** Peripheral DMA0 base address */ - #define DMA0_BASE (0x40082000u) - /** Peripheral DMA0 base pointer */ - #define DMA0 ((DMA_Type *)DMA0_BASE) - /** Peripheral DMA1 base address */ - #define DMA1_BASE (0x400A7000u) - /** Peripheral DMA1 base pointer */ - #define DMA1 ((DMA_Type *)DMA1_BASE) - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS { DMA0, DMA1 } -#endif -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } - -/*! - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer - * @{ - */ - -/** FLASH - Register Layout Typedef */ -typedef struct { - __O uint32_t CMD; /**< command register, offset: 0x0 */ - __O uint32_t EVENT; /**< event register, offset: 0x4 */ - __IO uint32_t BURST; /**< read burst register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ - __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ - uint8_t RESERVED_1[104]; - __IO uint32_t DATAW[8]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[3896]; - __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ - __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ - __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ - __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ - __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */ - __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */ - uint8_t RESERVED_3[12]; - __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */ -} FLASH_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_Register_Masks FLASH Register Masks - * @{ - */ - -/*! @name CMD - command register */ -/*! @{ */ -#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) -#define FLASH_CMD_CMD_SHIFT (0U) -#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) -/*! @} */ - -/*! @name EVENT - event register */ -/*! @{ */ -#define FLASH_EVENT_RST_MASK (0x1U) -#define FLASH_EVENT_RST_SHIFT (0U) -#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) -#define FLASH_EVENT_WAKEUP_MASK (0x2U) -#define FLASH_EVENT_WAKEUP_SHIFT (1U) -#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) -#define FLASH_EVENT_ABORT_MASK (0x4U) -#define FLASH_EVENT_ABORT_SHIFT (2U) -#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) -/*! @} */ - -/*! @name BURST - read burst register */ -/*! @{ */ -#define FLASH_BURST_XOR_MASK_MASK (0xFFFFFU) -#define FLASH_BURST_XOR_MASK_SHIFT (0U) -#define FLASH_BURST_XOR_MASK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_XOR_MASK_SHIFT)) & FLASH_BURST_XOR_MASK_MASK) -#define FLASH_BURST_DESCR1_MASK (0xF00000U) -#define FLASH_BURST_DESCR1_SHIFT (20U) -#define FLASH_BURST_DESCR1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR1_SHIFT)) & FLASH_BURST_DESCR1_MASK) -#define FLASH_BURST_DESCR2_MASK (0xF000000U) -#define FLASH_BURST_DESCR2_SHIFT (24U) -#define FLASH_BURST_DESCR2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR2_SHIFT)) & FLASH_BURST_DESCR2_MASK) -#define FLASH_BURST_DESCR3_MASK (0xF0000000U) -#define FLASH_BURST_DESCR3_SHIFT (28U) -#define FLASH_BURST_DESCR3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR3_SHIFT)) & FLASH_BURST_DESCR3_MASK) -/*! @} */ - -/*! @name STARTA - start (or only) address for next flash command */ -/*! @{ */ -#define FLASH_STARTA_STARTA_MASK (0x3FFFFU) -#define FLASH_STARTA_STARTA_SHIFT (0U) -#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) -/*! @} */ - -/*! @name STOPA - end address for next flash command, if command operates on address ranges */ -/*! @{ */ -#define FLASH_STOPA_STOPA_MASK (0x3FFFFU) -#define FLASH_STOPA_STOPA_SHIFT (0U) -#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) -/*! @} */ - -/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ -/*! @{ */ -#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) -#define FLASH_DATAW_DATAW_SHIFT (0U) -#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) -/*! @} */ - -/* The count of FLASH_DATAW */ -#define FLASH_DATAW_COUNT (8U) - -/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ -/*! @{ */ -#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) -#define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) -#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) -#define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) -#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) -#define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) -#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) -#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_ENABLE - Set interrupt enable bits */ -/*! @{ */ -#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) -#define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) -#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) -#define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) -#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) -#define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) -#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) -#define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt status bits */ -/*! @{ */ -#define FLASH_INT_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_STATUS_FAIL_SHIFT (0U) -#define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) -#define FLASH_INT_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_STATUS_ERR_SHIFT (1U) -#define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) -#define FLASH_INT_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_STATUS_DONE_SHIFT (2U) -#define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) -#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) -#define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_ENABLE - Interrupt enable bits */ -/*! @{ */ -#define FLASH_INT_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_ENABLE_FAIL_SHIFT (0U) -#define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) -#define FLASH_INT_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_ENABLE_ERR_SHIFT (1U) -#define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) -#define FLASH_INT_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_ENABLE_DONE_SHIFT (2U) -#define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) -#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) -#define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_CLR_STATUS - Clear interrupt status bits */ -/*! @{ */ -#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) -#define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) -#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) -#define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) -#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) -#define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) -#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) -#define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_STATUS - Set interrupt status bits */ -/*! @{ */ -#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) -#define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) -#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) -#define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) -#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) -#define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) -#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) -#define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name MODULE_ID - Controller+Memory module identification */ -/*! @{ */ -#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) -#define FLASH_MODULE_ID_APERTURE_SHIFT (0U) -#define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) -#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) -#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) -#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) -#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) -#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) -#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) -#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) -#define FLASH_MODULE_ID_ID_SHIFT (16U) -#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLASH_Register_Masks */ - - -/* FLASH - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral FLASH base address */ - #define FLASH_BASE (0x50034000u) - /** Peripheral FLASH base address */ - #define FLASH_BASE_NS (0x40034000u) - /** Peripheral FLASH base pointer */ - #define FLASH ((FLASH_Type *)FLASH_BASE) - /** Peripheral FLASH base pointer */ - #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS { FLASH_BASE } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS { FLASH } - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS_NS { FLASH_NS } -#else - /** Peripheral FLASH base address */ - #define FLASH_BASE (0x40034000u) - /** Peripheral FLASH base pointer */ - #define FLASH ((FLASH_Type *)FLASH_BASE) - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS { FLASH_BASE } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS { FLASH } -#endif - -/*! - * @} - */ /* end of group FLASH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_CFPA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer - * @{ - */ - -/** FLASH_CFPA - Register Layout Typedef */ -typedef struct { - __IO uint32_t HEADER; /**< ., offset: 0x0 */ - __IO uint32_t VERSION; /**< ., offset: 0x4 */ - __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ - __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ - __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ROTKH_REVOKE; /**< ., offset: 0x18 */ - __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x1C */ - __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ - __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ - __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ - __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ - union { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< ., array offset: 0x30, array step: 0x4 */ - struct { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< ., offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< ., offset: 0x34 */ - __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< ., array offset: 0x38, array step: 0x4 */ - } PRINCE_REGION0_IV_CODE_CORE; - }; - union { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< ., array offset: 0x68, array step: 0x4 */ - struct { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< ., offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< ., offset: 0x6C */ - __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< ., array offset: 0x70, array step: 0x4 */ - } PRINCE_REGION1_IV_CODE_CORE; - }; - union { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< ., array offset: 0xA0, array step: 0x4 */ - struct { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< ., offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< ., offset: 0xA4 */ - __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< ., array offset: 0xA8, array step: 0x4 */ - } PRINCE_REGION2_IV_CODE_CORE; - }; - uint8_t RESERVED_1[40]; - __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ -} FLASH_CFPA_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_CFPA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks - * @{ - */ - -/*! @name HEADER - . */ -/*! @{ */ -#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) -#define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) -/*! @} */ - -/*! @name VERSION - . */ -/*! @{ */ -#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ -/*! @{ */ -#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ -/*! @{ */ -#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ -/*! @{ */ -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) -/*! @} */ - -/*! @name ROTKH_REVOKE - . */ -/*! @{ */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) -/*! @} */ - -/*! @name VENDOR_USAGE - . */ -/*! @{ */ -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ -/*! @{ */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK (0x20U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT (5U) -/*! MCM33_DBGEN - Micro CM33 invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK (0x200U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT (9U) -/*! MCM33_NIDEN - Micro CM33 non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ -/*! @{ */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK (0x20U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT (5U) -/*! MCM33_DBGEN - Micro CM33 invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK (0x200U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT (9U) -/*! MCM33_NIDEN - Micro CM33 non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ -/*! @{ */ -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) -/*! @} */ - -/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ -/*! @{ */ -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_CODE - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION0_IV_HEADER0 - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_HEADER1 - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_BODY - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) - -/*! @name PRINCE_REGION1_IV_CODE - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION1_IV_HEADER0 - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_IV_HEADER1 - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_IV_BODY - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) - -/*! @name PRINCE_REGION2_IV_CODE - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION2_IV_HEADER0 - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_IV_HEADER1 - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_IV_BODY - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U) - -/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ -/*! @{ */ -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_CUSTOMER_DEFINED */ -#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U) - -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ -/*! @{ */ -#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) -#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_SHA256_DIGEST */ -#define FLASH_CFPA_SHA256_DIGEST_COUNT (8U) - - -/*! - * @} - */ /* end of group FLASH_CFPA_Register_Masks */ - - -/* FLASH_CFPA - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE (0x1009E000u) - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE_NS (0x9E000u) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE (0x1009E200u) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE_NS (0x9E200u) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE (0x1009DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE_NS (0x9DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS) - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS } -#else - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE (0x9E000u) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE (0x9E200u) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE (0x9DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } -#endif - -/*! - * @} - */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_CMPA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer - * @{ - */ - -/** FLASH_CMPA - Register Layout Typedef */ -typedef struct { - __IO uint32_t BOOT_CFG; /**< ., offset: 0x0 */ - __IO uint32_t SPI_FLASH_CFG; /**< ., offset: 0x4 */ - __IO uint32_t USB_ID; /**< ., offset: 0x8 */ - __IO uint32_t SDIO_CFG; /**< ., offset: 0xC */ - __IO uint32_t DCFG_CC_SOCU_PIN; /**< ., offset: 0x10 */ - __IO uint32_t DCFG_CC_SOCU_DFLT; /**< ., offset: 0x14 */ - __IO uint32_t DAP_VENDOR_USAGE_FIXED; /**< ., offset: 0x18 */ - __IO uint32_t SECURE_BOOT_CFG; /**< ., offset: 0x1C */ - __IO uint32_t PRINCE_BASE_ADDR; /**< ., offset: 0x20 */ - __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ - __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ - __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ - uint8_t RESERVED_0[32]; - __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ - uint8_t RESERVED_1[144]; - __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ -} FLASH_CMPA_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_CMPA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks - * @{ - */ - -/*! @name BOOT_CFG - . */ -/*! @{ */ -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) -/*! DEFAULT_ISP_MODE - Default ISP mode: - * 0b000..Auto ISP - * 0b001..USB_HID_MSC - * 0b010..SPI Slave ISP - * 0b011..I2C Slave ISP - * 0b111..Disable ISP fall through - */ -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) -/*! BOOT_SPEED - Core clock: - * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE - * 0b01..48MHz FRO - * 0b10..96MHz FRO - */ -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) -/*! @} */ - -/*! @name SPI_FLASH_CFG - . */ -/*! @{ */ -#define FLASH_CMPA_SPI_FLASH_CFG_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SPI_FLASH_CFG_FIELD_SHIFT (0U) -#define FLASH_CMPA_SPI_FLASH_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_FIELD_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_FIELD_MASK) -/*! @} */ - -/*! @name USB_ID - . */ -/*! @{ */ -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) -/*! @} */ - -/*! @name SDIO_CFG - . */ -/*! @{ */ -#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) -#define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_PIN - . */ -/*! @{ */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK (0x20U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT (5U) -/*! MCM33_DBGEN - Micro CM33 invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK (0x200U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT (9U) -/*! MCM33_NIDEN - Micro CM33 non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_DFLT - . */ -/*! @{ */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK (0x20U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT (5U) -/*! MCM33_DBGEN - Micro CM33 invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK (0x200U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT (9U) -/*! MCM33_NIDEN - Micro CM33 non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DAP_VENDOR_USAGE_FIXED - . */ -/*! @{ */ -#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_MASK (0xFFFF0000U) -#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_SHIFT (16U) -#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_MASK) -/*! @} */ - -/*! @name SECURE_BOOT_CFG - . */ -/*! @{ */ -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK (0xCU) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT (2U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) -/*! @} */ - -/*! @name PRINCE_BASE_ADDR - . */ -/*! @{ */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x30000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0xC0000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x300000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) -/*! @} */ - -/*! @name PRINCE_SR_0 - Region 0, sub-region enable */ -/*! @{ */ -#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_SR_1 - Region 1, sub-region enable */ -/*! @{ */ -#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_SR_2 - Region 2, sub-region enable */ -/*! @{ */ -#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) -/*! @} */ - -/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] */ -/*! @{ */ -#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) -#define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_ROTKH */ -#define FLASH_CMPA_ROTKH_COUNT (8U) - -/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ -/*! @{ */ -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_CUSTOMER_DEFINED */ -#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U) - -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ -/*! @{ */ -#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) -#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_SHA256_DIGEST */ -#define FLASH_CMPA_SHA256_DIGEST_COUNT (8U) - - -/*! - * @} - */ /* end of group FLASH_CMPA_Register_Masks */ - - -/* FLASH_CMPA - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE (0x1009E400u) - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE_NS (0x9E400u) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS) - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS } -#else - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE (0x9E400u) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } -#endif - -/*! - * @} - */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_KEY_STORE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer - * @{ - */ - -/** FLASH_KEY_STORE - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0 */ - __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */ - __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */ - } KEY_STORE_HEADER; - __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */ - union { /* offset: 0x4B0 */ - __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */ - struct { /* offset: 0x4B0 */ - __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */ - __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */ - __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */ - } SBKEY_KEY_CODE_CORE; - }; - union { /* offset: 0x4E8 */ - __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */ - struct { /* offset: 0x4E8 */ - __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */ - __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */ - __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */ - } USER_KEK_KEY_CODE_CORE; - }; - union { /* offset: 0x520 */ - __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */ - struct { /* offset: 0x520 */ - __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */ - __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */ - __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */ - } UDS_KEY_CODE_CORE; - }; - union { /* offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */ - struct { /* offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */ - __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */ - } PRINCE_REGION0_KEY_CODE_CORE; - }; - union { /* offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */ - struct { /* offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */ - __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */ - } PRINCE_REGION1_KEY_CODE_CORE; - }; - union { /* offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */ - struct { /* offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */ - __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */ - } PRINCE_REGION2_KEY_CODE_CORE; - }; -} FLASH_KEY_STORE_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_KEY_STORE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks - * @{ - */ - -/*! @name HEADER - Valid Key Sore Header : 0x95959595 */ -/*! @{ */ -#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) -/*! @} */ - -/*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ -/*! @{ */ -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) -/*! @} */ - -/*! @name ACTIVATION_CODE - . */ -/*! @{ */ -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_ACTIVATION_CODE */ -#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U) - -/*! @name SBKEY_KEY_CODE - . */ -/*! @{ */ -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */ -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U) - -/*! @name SBKEY_HEADER0 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name SBKEY_HEADER1 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name SBKEY_BODY - . */ -/*! @{ */ -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_SBKEY_BODY */ -#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U) - -/*! @name USER_KEK_KEY_CODE - . */ -/*! @{ */ -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */ -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U) - -/*! @name USER_KEK_HEADER0 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name USER_KEK_HEADER1 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name USER_KEK_BODY - . */ -/*! @{ */ -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_USER_KEK_BODY */ -#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U) - -/*! @name UDS_KEY_CODE - . */ -/*! @{ */ -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_UDS_KEY_CODE */ -#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U) - -/*! @name UDS_HEADER0 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name UDS_HEADER1 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name UDS_BODY - . */ -/*! @{ */ -#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_UDS_BODY */ -#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U) - -/*! @name PRINCE_REGION0_KEY_CODE - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION0_HEADER0 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_HEADER1 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_BODY - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U) - -/*! @name PRINCE_REGION1_KEY_CODE - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION1_HEADER0 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_HEADER1 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_BODY - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U) - -/*! @name PRINCE_REGION2_KEY_CODE - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION2_HEADER0 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_HEADER1 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_BODY - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U) - - -/*! - * @} - */ /* end of group FLASH_KEY_STORE_Register_Masks */ - - -/* FLASH_KEY_STORE - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE (0x1009E600u) - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE_NS (0x9E600u) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS) - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS } -#else - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE (0x9E600u) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } -#endif - -/*! - * @} - */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer - * @{ - */ - -/** FLEXCOMM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4088]; - __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ - __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ -} FLEXCOMM_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks - * @{ - */ - -/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ -/*! @{ */ -#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) -#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) -/*! PERSEL - Peripheral Select. This field is writable by software. - * 0b000..No peripheral selected. - * 0b001..USART function selected. - * 0b010..SPI function selected. - * 0b011..I2C function selected. - * 0b100..I2S transmit function selected. - * 0b101..I2S receive function selected. - * 0b110..Reserved - * 0b111..Reserved - */ -#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) -#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) -#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) -/*! LOCK - Lock the peripheral select. This field is writable by software. - * 0b0..Peripheral select can be changed by software. - * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. - */ -#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) -#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) -#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) -/*! USARTPRESENT - USART present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the USART function. - * 0b1..This Flexcomm includes the USART function. - */ -#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) -#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) -#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) -/*! SPIPRESENT - SPI present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the SPI function. - * 0b1..This Flexcomm includes the SPI function. - */ -#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) -#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) -#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) -/*! I2CPRESENT - I2C present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the I2C function. - * 0b1..This Flexcomm includes the I2C function. - */ -#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) -#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) -#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) -/*! I2SPRESENT - I 2S present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the I2S function. - * 0b1..This Flexcomm includes the I2S function. - */ -#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) -#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) -#define FLEXCOMM_PSELID_ID_SHIFT (12U) -#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) -/*! @} */ - -/*! @name PID - Peripheral identification register. */ -/*! @{ */ -#define FLEXCOMM_PID_Aperture_MASK (0xFFU) -#define FLEXCOMM_PID_Aperture_SHIFT (0U) -#define FLEXCOMM_PID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Aperture_SHIFT)) & FLEXCOMM_PID_Aperture_MASK) -#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) -#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) -#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) -#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) -#define FLEXCOMM_PID_Major_Rev_SHIFT (12U) -#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) -#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) -#define FLEXCOMM_PID_ID_SHIFT (16U) -#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLEXCOMM_Register_Masks */ - - -/* FLEXCOMM - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE (0x50086000u) - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE_NS (0x40086000u) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE (0x50087000u) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE_NS (0x40087000u) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE (0x50088000u) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE_NS (0x40088000u) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE (0x50089000u) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE_NS (0x40089000u) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE (0x5008A000u) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE_NS (0x4008A000u) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE (0x50096000u) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE_NS (0x40096000u) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE (0x50097000u) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE_NS (0x40097000u) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE (0x50098000u) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE_NS (0x40098000u) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE (0x5009F000u) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE_NS (0x4009F000u) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } -#else - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE (0x40086000u) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE (0x40087000u) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE (0x40088000u) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE (0x40089000u) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE (0x4008A000u) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE (0x40096000u) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE (0x40097000u) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE (0x40098000u) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE (0x4009F000u) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } -#endif -/** Interrupt vectors for the FLEXCOMM peripheral type */ -#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, LSPI_HS_IRQn } - -/*! - * @} - */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer - * @{ - */ - -/** GINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ - uint8_t RESERVED_0[28]; - __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[24]; - __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ -} GINT_Type; - -/* ---------------------------------------------------------------------------- - -- GINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Register_Masks GINT Register Masks - * @{ - */ - -/*! @name CTRL - GPIO grouped interrupt control register */ -/*! @{ */ -#define GINT_CTRL_INT_MASK (0x1U) -#define GINT_CTRL_INT_SHIFT (0U) -/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. - * 0b0..No request. No interrupt request is pending. - * 0b1..Request active. Interrupt request is active. - */ -#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) -#define GINT_CTRL_COMB_MASK (0x2U) -#define GINT_CTRL_COMB_SHIFT (1U) -/*! COMB - Combine enabled inputs for group interrupt - * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). - * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). - */ -#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) -#define GINT_CTRL_TRIG_MASK (0x4U) -#define GINT_CTRL_TRIG_SHIFT (2U) -/*! TRIG - Group interrupt trigger - * 0b0..Edge-triggered. - * 0b1..Level-triggered. - */ -#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) -/*! @} */ - -/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ -/*! @{ */ -#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) -#define GINT_PORT_POL_POL_SHIFT (0U) -#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) -/*! @} */ - -/* The count of GINT_PORT_POL */ -#define GINT_PORT_POL_COUNT (2U) - -/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ -/*! @{ */ -#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) -#define GINT_PORT_ENA_ENA_SHIFT (0U) -#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) -/*! @} */ - -/* The count of GINT_PORT_ENA */ -#define GINT_PORT_ENA_COUNT (2U) - - -/*! - * @} - */ /* end of group GINT_Register_Masks */ - - -/* GINT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral GINT0 base address */ - #define GINT0_BASE (0x50002000u) - /** Peripheral GINT0 base address */ - #define GINT0_BASE_NS (0x40002000u) - /** Peripheral GINT0 base pointer */ - #define GINT0 ((GINT_Type *)GINT0_BASE) - /** Peripheral GINT0 base pointer */ - #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) - /** Peripheral GINT1 base address */ - #define GINT1_BASE (0x50003000u) - /** Peripheral GINT1 base address */ - #define GINT1_BASE_NS (0x40003000u) - /** Peripheral GINT1 base pointer */ - #define GINT1 ((GINT_Type *)GINT1_BASE) - /** Peripheral GINT1 base pointer */ - #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS { GINT0, GINT1 } - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } -#else - /** Peripheral GINT0 base address */ - #define GINT0_BASE (0x40002000u) - /** Peripheral GINT0 base pointer */ - #define GINT0 ((GINT_Type *)GINT0_BASE) - /** Peripheral GINT1 base address */ - #define GINT1_BASE (0x40003000u) - /** Peripheral GINT1 base pointer */ - #define GINT1 ((GINT_Type *)GINT1_BASE) - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS { GINT0, GINT1 } -#endif -/** Interrupt vectors for the GINT peripheral type */ -#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } - -/*! - * @} - */ /* end of group GINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint8_t B[4][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ - uint8_t RESERVED_0[3968]; - __IO uint32_t W[4][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ - uint8_t RESERVED_1[3584]; - __IO uint32_t DIR[4]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ - uint8_t RESERVED_2[112]; - __IO uint32_t MASK[4]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ - uint8_t RESERVED_3[112]; - __IO uint32_t PIN[4]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ - uint8_t RESERVED_4[112]; - __IO uint32_t MPIN[4]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ - uint8_t RESERVED_5[112]; - __IO uint32_t SET[4]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ - uint8_t RESERVED_6[112]; - __O uint32_t CLR[4]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ - uint8_t RESERVED_7[112]; - __O uint32_t NOT[4]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ - uint8_t RESERVED_8[112]; - __O uint32_t DIRSET[4]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ - uint8_t RESERVED_9[112]; - __O uint32_t DIRCLR[4]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ - uint8_t RESERVED_10[112]; - __O uint32_t DIRNOT[4]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/*! @name B - Byte pin registers for all port GPIO pins */ -/*! @{ */ -#define GPIO_B_PBYTE_MASK (0x1U) -#define GPIO_B_PBYTE_SHIFT (0U) -#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) -/*! @} */ - -/* The count of GPIO_B */ -#define GPIO_B_COUNT (4U) - -/* The count of GPIO_B */ -#define GPIO_B_COUNT2 (32U) - -/*! @name W - Word pin registers for all port GPIO pins */ -/*! @{ */ -#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) -#define GPIO_W_PWORD_SHIFT (0U) -#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) -/*! @} */ - -/* The count of GPIO_W */ -#define GPIO_W_COUNT (4U) - -/* The count of GPIO_W */ -#define GPIO_W_COUNT2 (32U) - -/*! @name DIR - Direction registers for all port GPIO pins */ -/*! @{ */ -#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) -#define GPIO_DIR_DIRP_SHIFT (0U) -#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) -/*! @} */ - -/* The count of GPIO_DIR */ -#define GPIO_DIR_COUNT (4U) - -/*! @name MASK - Mask register for all port GPIO pins */ -/*! @{ */ -#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) -#define GPIO_MASK_MASKP_SHIFT (0U) -#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) -/*! @} */ - -/* The count of GPIO_MASK */ -#define GPIO_MASK_COUNT (4U) - -/*! @name PIN - Port pin register for all port GPIO pins */ -/*! @{ */ -#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) -#define GPIO_PIN_PORT_SHIFT (0U) -#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) -/*! @} */ - -/* The count of GPIO_PIN */ -#define GPIO_PIN_COUNT (4U) - -/*! @name MPIN - Masked port register for all port GPIO pins */ -/*! @{ */ -#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) -#define GPIO_MPIN_MPORTP_SHIFT (0U) -#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) -/*! @} */ - -/* The count of GPIO_MPIN */ -#define GPIO_MPIN_COUNT (4U) - -/*! @name SET - Write: Set register for port. Read: output bits for port */ -/*! @{ */ -#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) -#define GPIO_SET_SETP_SHIFT (0U) -#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) -/*! @} */ - -/* The count of GPIO_SET */ -#define GPIO_SET_COUNT (4U) - -/*! @name CLR - Clear port for all port GPIO pins */ -/*! @{ */ -#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) -#define GPIO_CLR_CLRP_SHIFT (0U) -#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) -/*! @} */ - -/* The count of GPIO_CLR */ -#define GPIO_CLR_COUNT (4U) - -/*! @name NOT - Toggle port for all port GPIO pins */ -/*! @{ */ -#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) -#define GPIO_NOT_NOTP_SHIFT (0U) -#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) -/*! @} */ - -/* The count of GPIO_NOT */ -#define GPIO_NOT_COUNT (4U) - -/*! @name DIRSET - Set pin direction bits for port */ -/*! @{ */ -#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) -#define GPIO_DIRSET_DIRSETP_SHIFT (0U) -#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) -/*! @} */ - -/* The count of GPIO_DIRSET */ -#define GPIO_DIRSET_COUNT (4U) - -/*! @name DIRCLR - Clear pin direction bits for port */ -/*! @{ */ -#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) -#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) -#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) -/*! @} */ - -/* The count of GPIO_DIRCLR */ -#define GPIO_DIRCLR_COUNT (4U) - -/*! @name DIRNOT - Toggle pin direction bits for port */ -/*! @{ */ -#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) -#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) -#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) -/*! @} */ - -/* The count of GPIO_DIRNOT */ -#define GPIO_DIRNOT_COUNT (4U) - - -/*! - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral GPIO base address */ - #define GPIO_BASE (0x5008C000u) - /** Peripheral GPIO base address */ - #define GPIO_BASE_NS (0x4008C000u) - /** Peripheral GPIO base pointer */ - #define GPIO ((GPIO_Type *)GPIO_BASE) - /** Peripheral GPIO base pointer */ - #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE (0x500A8000u) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE_NS (0x400A8000u) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO, SECGPIO } - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } -#else - /** Peripheral GPIO base address */ - #define GPIO_BASE (0x4008C000u) - /** Peripheral GPIO base pointer */ - #define GPIO ((GPIO_Type *)GPIO_BASE) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE (0x400A8000u) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO, SECGPIO } -#endif - -/*! - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- HASHCRYPT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer - * @{ - */ - -/** HASHCRYPT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Is control register to enable and operate Hash and Crypto, offset: 0x0 */ - __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */ - __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */ - __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */ - __IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available), offset: 0x10 */ - __IO uint32_t MEMADDR; /**< Address to start memory access from (if available)., offset: 0x14 */ - uint8_t RESERVED_0[8]; - __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */ - __O uint32_t ALIAS[7]; /**< , array offset: 0x24, array step: 0x4 */ - __I uint32_t OUTDATA0[8]; /**< , array offset: 0x40, array step: 0x4 */ - __I uint32_t OUTDATA1[8]; /**< , array offset: 0x60, array step: 0x4 */ - __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */ - __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */ - uint8_t RESERVED_1[4]; - __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */ - __O uint32_t MASK[4]; /**< , array offset: 0x90, array step: 0x4 */ -} HASHCRYPT_Type; - -/* ---------------------------------------------------------------------------- - -- HASHCRYPT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks - * @{ - */ - -/*! @name CTRL - Is control register to enable and operate Hash and Crypto */ -/*! @{ */ -#define HASHCRYPT_CTRL_MODE_MASK (0x7U) -#define HASHCRYPT_CTRL_MODE_SHIFT (0U) -/*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available. - * 0b000..Disabled - * 0b001..SHA1 is enabled - * 0b010..SHA2-256 is enabled - * 0b011..SHA2-512 is enabled (if available) - * 0b100..AES if available (see also CRYPTCFG register for more controls) - * 0b101..ICB-AES if available (see also CRYPTCFG register for more controls) - * 0b110..Salsa20/20 if available (including XSalsa - see also CRYPTCFG register) - * 0b111..ChaCha20 if available (see also CRYPTCFG register for more controls) - */ -#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK) -#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U) -#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U) -/*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1. - * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result. - */ -#define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK) -#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U) -#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U) -/*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed). - * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. - * 0b1..DMA will push in the data. - */ -#define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK) -#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U) -#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U) -/*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses. - * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. - */ -#define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK) -#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U) -#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U) -#define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK) -/*! @} */ - -/*! @name STATUS - Indicates status of Hash peripheral. */ -/*! @{ */ -#define HASHCRYPT_STATUS_WAITING_MASK (0x1U) -#define HASHCRYPT_STATUS_WAITING_SHIFT (0U) -/*! WAITING - If 1, the block is waiting for more data to process. - * 0b0..Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set if IsLast is set nor will it set until at least 1 word is read of the output. - * 0b1..Waiting for data to be written in (16 words) - */ -#define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK) -#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK (0x2U) -#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_SHIFT (1U) -/*! DIGEST_aka_OUTDATA - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block already started. For Cryptographic uses, this will be set for each block processed, indicating OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared when any data is written, when New is written, for Cryptographic uses when the last word is read out, or when the block is disabled. - * 0b0..No Digest is ready - * 0b1..Digest is ready. Application may read it or may write more data - */ -#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_SHIFT)) & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK) -#define HASHCRYPT_STATUS_ERROR_MASK (0x4U) -#define HASHCRYPT_STATUS_ERROR_SHIFT (2U) -/*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT field will indicate which block it was on. - * 0b0..No error. - * 0b1..An error occurred since last cleared (written 1 to clear). - */ -#define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK) -#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U) -#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U) -/*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) - * 0b0..No Key is needed and writes will not be treated as Key - * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. - */ -#define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK) -#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U) -#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U) -/*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) - * 0b0..No IV/Nonce is needed, either because written already or because not needed. - * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. - */ -#define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK) -#define HASHCRYPT_STATUS_ICBIDX_MASK (0x3F0000U) -#define HASHCRYPT_STATUS_ICBIDX_SHIFT (16U) -#define HASHCRYPT_STATUS_ICBIDX(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK) -/*! @} */ - -/*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */ -/*! @{ */ -#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U) -#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U) -/*! WAITING - Indicates if should interrupt when waiting for data input. - * 0b0..Will not interrupt when waiting. - * 0b1..Will interrupt when waiting - */ -#define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK) -#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U) -#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U) -/*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). - * 0b0..Will not interrupt when Digest is ready - * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). - */ -#define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK) -#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U) -#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U) -/*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status) - * 0b0..Will not interrupt on Error. - * 0b1..Will interrupt on Error (until cleared). - */ -#define HASHCRYPT_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK) -/*! @} */ - -/*! @name INTENCLR - Write 1 to clear interrupts. */ -/*! @{ */ -#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U) -#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U) -#define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK) -#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U) -#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U) -#define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK) -#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U) -#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U) -#define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK) -/*! @} */ - -/*! @name MEMCTRL - Setup Master to access memory (if available) */ -/*! @{ */ -#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U) -#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U) -/*! MASTER - * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. - * 0b1..Mastering is enabled and DMA and INDATA should not be used. - */ -#define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK) -#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U) -#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U) -#define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK) -/*! @} */ - -/*! @name MEMADDR - Address to start memory access from (if available). */ -/*! @{ */ -#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU) -#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U) -#define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK) -/*! @} */ - -/*! @name INDATA - Input of 16 words at a time to load up buffer. */ -/*! @{ */ -#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU) -#define HASHCRYPT_INDATA_DATA_SHIFT (0U) -#define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK) -/*! @} */ - -/*! @name ALIAS - */ -/*! @{ */ -#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU) -#define HASHCRYPT_ALIAS_DATA_SHIFT (0U) -#define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK) -/*! @} */ - -/* The count of HASHCRYPT_ALIAS */ -#define HASHCRYPT_ALIAS_COUNT (7U) - -/*! @name OUTDATA0 - */ -/*! @{ */ -#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_MASK (0xFFFFFFFFU) -#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_SHIFT (0U) -#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_SHIFT)) & HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_MASK) -/*! @} */ - -/* The count of HASHCRYPT_OUTDATA0 */ -#define HASHCRYPT_OUTDATA0_COUNT (8U) - -/*! @name OUTDATA1 - */ -/*! @{ */ -#define HASHCRYPT_OUTDATA1_OUTPUT_MASK (0xFFFFFFFFU) -#define HASHCRYPT_OUTDATA1_OUTPUT_SHIFT (0U) -#define HASHCRYPT_OUTDATA1_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_OUTDATA1_OUTPUT_SHIFT)) & HASHCRYPT_OUTDATA1_OUTPUT_MASK) -/*! @} */ - -/* The count of HASHCRYPT_OUTDATA1 */ -#define HASHCRYPT_OUTDATA1_COUNT (8U) - -/*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */ -/*! @{ */ -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U) -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U) -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK) -#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U) -#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U) -#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK) -#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U) -#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U) -#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK) -#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U) -#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U) -#define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK) -#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U) -#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U) -/*! AESMODE - AES Cipher mode to use if plain AES - * 0b00..ECB - used as is - * 0b01..CBC mode (see details on IV/nonce) - * 0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS. - * 0b11..reserved - */ -#define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK) -#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U) -#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U) -/*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB - * 0b0..Encrypt - * 0b1..Decrypt - */ -#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK) -#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U) -#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U) -/*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are used, only the highest level is permitted to select this. - * 0b0..User key provided in normal way - * 0b1..Secret key provided in hidden way by HW - */ -#define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK) -#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U) -#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U) -/*! AESKEYSZ - Sets the AES key size - * 0b00..128 bit key - * 0b01..192 bit key - * 0b10..256 bit key - * 0b11..reserved - */ -#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK) -#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U) -#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U) -#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK) -#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U) -#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U) -#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK) -#define HASHCRYPT_CRYPTCFG_XSALSA_MASK (0x20000U) -#define HASHCRYPT_CRYPTCFG_XSALSA_SHIFT (17U) -#define HASHCRYPT_CRYPTCFG_XSALSA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_XSALSA_SHIFT)) & HASHCRYPT_CRYPTCFG_XSALSA_MASK) -#define HASHCRYPT_CRYPTCFG_ICBSZ_MASK (0x300000U) -#define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT (20U) -/*! ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the counter is assumed to occupy the low order bits of the IV. - * 0b00..32 bits of the IV/ctr are used (from 127:96) - * 0b01..64 bits of the IV/ctr are used (from 127:64) - * 0b10..96 bits of the IV/ctr are used (from 127:32) - * 0b11..All 128 bits of the IV/ctr are used - */ -#define HASHCRYPT_CRYPTCFG_ICBSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK) -#define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK (0xC00000U) -#define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT (22U) -/*! ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st. - * 0b00..8 blocks - * 0b01..16 blocks - * 0b10..32 blocks - * 0b11..64 blocks - */ -#define HASHCRYPT_CRYPTCFG_ICBSTRM(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSTRM_MASK) -/*! @} */ - -/*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */ -/*! @{ */ -#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U) -#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U) -#define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK) -#define HASHCRYPT_CONFIG_DMA_MASK (0x2U) -#define HASHCRYPT_CONFIG_DMA_SHIFT (1U) -#define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK) -#define HASHCRYPT_CONFIG_AHB_MASK (0x8U) -#define HASHCRYPT_CONFIG_AHB_SHIFT (3U) -#define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK) -#define HASHCRYPT_CONFIG_SHA512_MASK (0x20U) -#define HASHCRYPT_CONFIG_SHA512_SHIFT (5U) -#define HASHCRYPT_CONFIG_SHA512(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SHA512_SHIFT)) & HASHCRYPT_CONFIG_SHA512_MASK) -#define HASHCRYPT_CONFIG_AES_MASK (0x40U) -#define HASHCRYPT_CONFIG_AES_SHIFT (6U) -#define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK) -#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U) -#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U) -#define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK) -#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U) -#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U) -#define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK) -#define HASHCRYPT_CONFIG_SALSA_MASK (0x200U) -#define HASHCRYPT_CONFIG_SALSA_SHIFT (9U) -#define HASHCRYPT_CONFIG_SALSA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SALSA_SHIFT)) & HASHCRYPT_CONFIG_SALSA_MASK) -#define HASHCRYPT_CONFIG_CHACHA_MASK (0x400U) -#define HASHCRYPT_CONFIG_CHACHA_SHIFT (10U) -#define HASHCRYPT_CONFIG_CHACHA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_CHACHA_SHIFT)) & HASHCRYPT_CONFIG_CHACHA_MASK) -#define HASHCRYPT_CONFIG_ICB_MASK (0x800U) -#define HASHCRYPT_CONFIG_ICB_SHIFT (11U) -#define HASHCRYPT_CONFIG_ICB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK) -/*! @} */ - -/*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */ -/*! @{ */ -#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U) -#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U) -/*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. If locked already, may only write if at same or higher security level as lock. Reads as: 0 if unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the only readable registers if locked and current state is lower than lock level. - * 0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. - * 0b01..Locks to the current security level. AHB Master will issue requests at this level. - */ -#define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK) -#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U) -#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U) -#define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK) -/*! @} */ - -/*! @name MASK - */ -/*! @{ */ -#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU) -#define HASHCRYPT_MASK_MASK_SHIFT (0U) -#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK) -/*! @} */ - -/* The count of HASHCRYPT_MASK */ -#define HASHCRYPT_MASK_COUNT (4U) - - -/*! - * @} - */ /* end of group HASHCRYPT_Register_Masks */ - - -/* HASHCRYPT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE (0x500A4000u) - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE_NS (0x400A4000u) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS) - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS { HASHCRYPT } - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS } -#else - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE (0x400A4000u) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS { HASHCRYPT } -#endif - -/*! - * @} - */ /* end of group HASHCRYPT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer - * @{ - */ - -/** I2C - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[2048]; - __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ - __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ - __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ - __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ - __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ - __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ - uint8_t RESERVED_1[4]; - __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ - __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ - __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ - uint8_t RESERVED_2[20]; - __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ - __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ - __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ - __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ - uint8_t RESERVED_3[36]; - __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ - uint8_t RESERVED_4[1912]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} I2C_Type; - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/*! @name CFG - Configuration for shared functions. */ -/*! @{ */ -#define I2C_CFG_MSTEN_MASK (0x1U) -#define I2C_CFG_MSTEN_SHIFT (0U) -/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. - * 0b0..Disabled. The I2C Master function is disabled. - * 0b1..Enabled. The I2C Master function is enabled. - */ -#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) -#define I2C_CFG_SLVEN_MASK (0x2U) -#define I2C_CFG_SLVEN_SHIFT (1U) -/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. - * 0b0..Disabled. The I2C slave function is disabled. - * 0b1..Enabled. The I2C slave function is enabled. - */ -#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) -#define I2C_CFG_MONEN_MASK (0x4U) -#define I2C_CFG_MONEN_SHIFT (2U) -/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. - * 0b0..Disabled. The I2C Monitor function is disabled. - * 0b1..Enabled. The I2C Monitor function is enabled. - */ -#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) -#define I2C_CFG_TIMEOUTEN_MASK (0x8U) -#define I2C_CFG_TIMEOUTEN_SHIFT (3U) -/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. - * 0b0..Disabled. Time-out function is disabled. - * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. - */ -#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) -#define I2C_CFG_MONCLKSTR_MASK (0x10U) -#define I2C_CFG_MONCLKSTR_SHIFT (4U) -/*! MONCLKSTR - Monitor function Clock Stretching. - * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. - * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function. - */ -#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) -#define I2C_CFG_HSCAPABLE_MASK (0x20U) -#define I2C_CFG_HSCAPABLE_SHIFT (5U) -/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor. - * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin, - * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information. - */ -#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) -/*! @} */ - -/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ -#define I2C_STAT_MSTPENDING_MASK (0x1U) -#define I2C_STAT_MSTPENDING_SHIFT (0U) -/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. - * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. - * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. - */ -#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) -#define I2C_STAT_MSTSTATE_MASK (0xEU) -#define I2C_STAT_MSTSTATE_SHIFT (1U) -/*! MSTSTATE - Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. - * 0b000..Idle. The Master function is available to be used for a new transaction. - * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. - * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. - * 0b011..NACK Address. Slave NACKed address. - * 0b100..NACK Data. Slave NACKed transmitted data. - */ -#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) -#define I2C_STAT_MSTARBLOSS_MASK (0x10U) -#define I2C_STAT_MSTARBLOSS_SHIFT (4U) -/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - * 0b0..No Arbitration Loss has occurred. - * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. - */ -#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) -#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) -/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - * 0b0..No Start/Stop Error has occurred. - * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. - */ -#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) -#define I2C_STAT_SLVPENDING_MASK (0x100U) -#define I2C_STAT_SLVPENDING_SHIFT (8U) -/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. - * 0b0..In progress. The Slave function does not currently need service. - * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. - */ -#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) -#define I2C_STAT_SLVSTATE_MASK (0x600U) -#define I2C_STAT_SLVSTATE_SHIFT (9U) -/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. - * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. - * 0b01..Slave receive. Received data is available (Slave Receiver mode). - * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). - */ -#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) -#define I2C_STAT_SLVNOTSTR_MASK (0x800U) -#define I2C_STAT_SLVNOTSTR_SHIFT (11U) -/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. - * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. - * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. - */ -#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) -#define I2C_STAT_SLVIDX_MASK (0x3000U) -#define I2C_STAT_SLVIDX_SHIFT (12U) -/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. - * 0b00..Address 0. Slave address 0 was matched. - * 0b01..Address 1. Slave address 1 was matched. - * 0b10..Address 2. Slave address 2 was matched. - * 0b11..Address 3. Slave address 3 was matched. - */ -#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) -#define I2C_STAT_SLVSEL_MASK (0x4000U) -#define I2C_STAT_SLVSEL_SHIFT (14U) -/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. - * 0b0..Not selected. The Slave function is not currently selected. - * 0b1..Selected. The Slave function is currently selected. - */ -#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) -#define I2C_STAT_SLVDESEL_MASK (0x8000U) -#define I2C_STAT_SLVDESEL_SHIFT (15U) -/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. - * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. - * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. - */ -#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) -#define I2C_STAT_MONRDY_MASK (0x10000U) -#define I2C_STAT_MONRDY_SHIFT (16U) -/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. - * 0b0..No data. The Monitor function does not currently have data available. - * 0b1..Data waiting. The Monitor function has data waiting to be read. - */ -#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) -#define I2C_STAT_MONOV_MASK (0x20000U) -#define I2C_STAT_MONOV_SHIFT (17U) -/*! MONOV - Monitor Overflow flag. - * 0b0..No overrun. Monitor data has not overrun. - * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. - */ -#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) -#define I2C_STAT_MONACTIVE_MASK (0x40000U) -#define I2C_STAT_MONACTIVE_SHIFT (18U) -/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. - * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. - * 0b1..Active. The Monitor function considers the I2C bus to be active. - */ -#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) -#define I2C_STAT_MONIDLE_MASK (0x80000U) -#define I2C_STAT_MONIDLE_SHIFT (19U) -/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. - * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. - * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. - */ -#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) -#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) -/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. - * 0b0..No time-out. I2C bus events have not caused a time-out. - * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. - */ -#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) -#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) -/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. - * 0b0..No time-out. SCL low time has not caused a time-out. - * 0b1..Time-out. SCL low time has caused a time-out. - */ -#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable Set and read register. */ -/*! @{ */ -#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) -#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) -/*! MSTPENDINGEN - Master Pending interrupt Enable. - * 0b0..Disabled. The MstPending interrupt is disabled. - * 0b1..Enabled. The MstPending interrupt is enabled. - */ -#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) -#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) -#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) -/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. - * 0b0..Disabled. The MstArbLoss interrupt is disabled. - * 0b1..Enabled. The MstArbLoss interrupt is enabled. - */ -#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) -#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) -#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) -/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. - * 0b0..Disabled. The MstStStpErr interrupt is disabled. - * 0b1..Enabled. The MstStStpErr interrupt is enabled. - */ -#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) -#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) -#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) -/*! SLVPENDINGEN - Slave Pending interrupt Enable. - * 0b0..Disabled. The SlvPending interrupt is disabled. - * 0b1..Enabled. The SlvPending interrupt is enabled. - */ -#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) -#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) -#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) -/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. - * 0b0..Disabled. The SlvNotStr interrupt is disabled. - * 0b1..Enabled. The SlvNotStr interrupt is enabled. - */ -#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) -#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) -#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) -/*! SLVDESELEN - Slave Deselect interrupt Enable. - * 0b0..Disabled. The SlvDeSel interrupt is disabled. - * 0b1..Enabled. The SlvDeSel interrupt is enabled. - */ -#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) -#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) -#define I2C_INTENSET_MONRDYEN_SHIFT (16U) -/*! MONRDYEN - Monitor data Ready interrupt Enable. - * 0b0..Disabled. The MonRdy interrupt is disabled. - * 0b1..Enabled. The MonRdy interrupt is enabled. - */ -#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) -#define I2C_INTENSET_MONOVEN_MASK (0x20000U) -#define I2C_INTENSET_MONOVEN_SHIFT (17U) -/*! MONOVEN - Monitor Overrun interrupt Enable. - * 0b0..Disabled. The MonOv interrupt is disabled. - * 0b1..Enabled. The MonOv interrupt is enabled. - */ -#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) -#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) -#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) -/*! MONIDLEEN - Monitor Idle interrupt Enable. - * 0b0..Disabled. The MonIdle interrupt is disabled. - * 0b1..Enabled. The MonIdle interrupt is enabled. - */ -#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) -#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) -#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) -/*! EVENTTIMEOUTEN - Event time-out interrupt Enable. - * 0b0..Disabled. The Event time-out interrupt is disabled. - * 0b1..Enabled. The Event time-out interrupt is enabled. - */ -#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) -#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) -#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) -/*! SCLTIMEOUTEN - SCL time-out interrupt Enable. - * 0b0..Disabled. The SCL time-out interrupt is disabled. - * 0b1..Enabled. The SCL time-out interrupt is enabled. - */ -#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. */ -/*! @{ */ -#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) -#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) -#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) -#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) -#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) -#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) -#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) -#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) -#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) -#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) -#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) -#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) -#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) -#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) -#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) -#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) -#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) -#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) -#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) -#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) -#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) -#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) -#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) -#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) -#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) -#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) -#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) -#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) -#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) -#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) -/*! @} */ - -/*! @name TIMEOUT - Time-out value register. */ -/*! @{ */ -#define I2C_TIMEOUT_TOMIN_MASK (0xFU) -#define I2C_TIMEOUT_TOMIN_SHIFT (0U) -#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) -#define I2C_TIMEOUT_TO_MASK (0xFFF0U) -#define I2C_TIMEOUT_TO_SHIFT (4U) -#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) -/*! @} */ - -/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ -/*! @{ */ -#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) -#define I2C_CLKDIV_DIVVAL_SHIFT (0U) -#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ -#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) -#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) -#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) -#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) -#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) -#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) -#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) -#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) -#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) -#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) -#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) -#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) -#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) -#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) -#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) -#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) -#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) -#define I2C_INTSTAT_MONRDY_MASK (0x10000U) -#define I2C_INTSTAT_MONRDY_SHIFT (16U) -#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) -#define I2C_INTSTAT_MONOV_MASK (0x20000U) -#define I2C_INTSTAT_MONOV_SHIFT (17U) -#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) -#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) -#define I2C_INTSTAT_MONIDLE_SHIFT (19U) -#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) -#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) -#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) -#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) -#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name MSTCTL - Master control register. */ -/*! @{ */ -#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) -#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) -/*! MSTCONTINUE - Master Continue. This bit is write-only. - * 0b0..No effect. - * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. - */ -#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) -#define I2C_MSTCTL_MSTSTART_MASK (0x2U) -#define I2C_MSTCTL_MSTSTART_SHIFT (1U) -/*! MSTSTART - Master Start control. This bit is write-only. - * 0b0..No effect. - * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. - */ -#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) -#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) -#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) -/*! MSTSTOP - Master Stop control. This bit is write-only. - * 0b0..No effect. - * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). - */ -#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) -#define I2C_MSTCTL_MSTDMA_MASK (0x8U) -#define I2C_MSTCTL_MSTDMA_SHIFT (3U) -/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. - * 0b0..Disable. No DMA requests are generated for master operation. - * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. - */ -#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) -/*! @} */ - -/*! @name MSTTIME - Master timing configuration. */ -/*! @{ */ -#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) -#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) -/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. - * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. - * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) -#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) -#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) -/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. - * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . - * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) -/*! @} */ - -/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ -/*! @{ */ -#define I2C_MSTDAT_DATA_MASK (0xFFU) -#define I2C_MSTDAT_DATA_SHIFT (0U) -#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVCTL - Slave control register. */ -/*! @{ */ -#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) -#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) -/*! SLVCONTINUE - Slave Continue. - * 0b0..No effect. - * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1. - */ -#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) -#define I2C_SLVCTL_SLVNACK_MASK (0x2U) -#define I2C_SLVCTL_SLVNACK_SHIFT (1U) -/*! SLVNACK - Slave NACK. - * 0b0..No effect. - * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). - */ -#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) -#define I2C_SLVCTL_SLVDMA_MASK (0x8U) -#define I2C_SLVCTL_SLVDMA_SHIFT (3U) -/*! SLVDMA - Slave DMA enable. - * 0b0..Disabled. No DMA requests are issued for Slave mode operation. - * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. - */ -#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) -#define I2C_SLVCTL_AUTOACK_MASK (0x100U) -#define I2C_SLVCTL_AUTOACK_SHIFT (8U) -/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt. - * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored). - * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. - */ -#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) -#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) -#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) -/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation. - * 0b0..The expected next operation in Automatic Mode is an I2C write. - * 0b1..The expected next operation in Automatic Mode is an I2C read. - */ -#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) -/*! @} */ - -/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ -/*! @{ */ -#define I2C_SLVDAT_DATA_MASK (0xFFU) -#define I2C_SLVDAT_DATA_SHIFT (0U) -#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVADR - Slave address register. */ -/*! @{ */ -#define I2C_SLVADR_SADISABLE_MASK (0x1U) -#define I2C_SLVADR_SADISABLE_SHIFT (0U) -/*! SADISABLE - Slave Address n Disable. - * 0b0..Enabled. Slave Address n is enabled. - * 0b1..Ignored Slave Address n is ignored. - */ -#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) -#define I2C_SLVADR_SLVADR_MASK (0xFEU) -#define I2C_SLVADR_SLVADR_SHIFT (1U) -#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) -#define I2C_SLVADR_AUTONACK_MASK (0x8000U) -#define I2C_SLVADR_AUTONACK_SHIFT (15U) -/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations. - * 0b0..Normal operation, matching I2C addresses are not ignored. - * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction. - */ -#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) -/*! @} */ - -/* The count of I2C_SLVADR */ -#define I2C_SLVADR_COUNT (4U) - -/*! @name SLVQUAL0 - Slave Qualification for address 0. */ -/*! @{ */ -#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) -#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) -/*! QUALMODE0 - Qualify mode for slave address 0. - * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. - * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. - */ -#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) -#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) -#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) -#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) -/*! @} */ - -/*! @name MONRXDAT - Monitor receiver data register. */ -/*! @{ */ -#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) -#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) -#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) -#define I2C_MONRXDAT_MONSTART_MASK (0x100U) -#define I2C_MONRXDAT_MONSTART_SHIFT (8U) -/*! MONSTART - Monitor Received Start. - * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. - * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) -#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) -#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) -/*! MONRESTART - Monitor Received Repeated Start. - * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. - * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) -#define I2C_MONRXDAT_MONNACK_MASK (0x400U) -#define I2C_MONRXDAT_MONNACK_SHIFT (10U) -/*! MONNACK - Monitor Received NACK. - * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. - * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. - */ -#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ -#define I2C_ID_APERTURE_MASK (0xFFU) -#define I2C_ID_APERTURE_SHIFT (0U) -#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) -#define I2C_ID_MINOR_REV_MASK (0xF00U) -#define I2C_ID_MINOR_REV_SHIFT (8U) -#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) -#define I2C_ID_MAJOR_REV_MASK (0xF000U) -#define I2C_ID_MAJOR_REV_SHIFT (12U) -#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) -#define I2C_ID_ID_MASK (0xFFFF0000U) -#define I2C_ID_ID_SHIFT (16U) -#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2C_Register_Masks */ - - -/* I2C - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral I2C0 base address */ - #define I2C0_BASE (0x50086000u) - /** Peripheral I2C0 base address */ - #define I2C0_BASE_NS (0x40086000u) - /** Peripheral I2C0 base pointer */ - #define I2C0 ((I2C_Type *)I2C0_BASE) - /** Peripheral I2C0 base pointer */ - #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) - /** Peripheral I2C1 base address */ - #define I2C1_BASE (0x50087000u) - /** Peripheral I2C1 base address */ - #define I2C1_BASE_NS (0x40087000u) - /** Peripheral I2C1 base pointer */ - #define I2C1 ((I2C_Type *)I2C1_BASE) - /** Peripheral I2C1 base pointer */ - #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) - /** Peripheral I2C2 base address */ - #define I2C2_BASE (0x50088000u) - /** Peripheral I2C2 base address */ - #define I2C2_BASE_NS (0x40088000u) - /** Peripheral I2C2 base pointer */ - #define I2C2 ((I2C_Type *)I2C2_BASE) - /** Peripheral I2C2 base pointer */ - #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) - /** Peripheral I2C3 base address */ - #define I2C3_BASE (0x50089000u) - /** Peripheral I2C3 base address */ - #define I2C3_BASE_NS (0x40089000u) - /** Peripheral I2C3 base pointer */ - #define I2C3 ((I2C_Type *)I2C3_BASE) - /** Peripheral I2C3 base pointer */ - #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) - /** Peripheral I2C4 base address */ - #define I2C4_BASE (0x5008A000u) - /** Peripheral I2C4 base address */ - #define I2C4_BASE_NS (0x4008A000u) - /** Peripheral I2C4 base pointer */ - #define I2C4 ((I2C_Type *)I2C4_BASE) - /** Peripheral I2C4 base pointer */ - #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) - /** Peripheral I2C5 base address */ - #define I2C5_BASE (0x50096000u) - /** Peripheral I2C5 base address */ - #define I2C5_BASE_NS (0x40096000u) - /** Peripheral I2C5 base pointer */ - #define I2C5 ((I2C_Type *)I2C5_BASE) - /** Peripheral I2C5 base pointer */ - #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) - /** Peripheral I2C6 base address */ - #define I2C6_BASE (0x50097000u) - /** Peripheral I2C6 base address */ - #define I2C6_BASE_NS (0x40097000u) - /** Peripheral I2C6 base pointer */ - #define I2C6 ((I2C_Type *)I2C6_BASE) - /** Peripheral I2C6 base pointer */ - #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) - /** Peripheral I2C7 base address */ - #define I2C7_BASE (0x50098000u) - /** Peripheral I2C7 base address */ - #define I2C7_BASE_NS (0x40098000u) - /** Peripheral I2C7 base pointer */ - #define I2C7 ((I2C_Type *)I2C7_BASE) - /** Peripheral I2C7 base pointer */ - #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } -#else - /** Peripheral I2C0 base address */ - #define I2C0_BASE (0x40086000u) - /** Peripheral I2C0 base pointer */ - #define I2C0 ((I2C_Type *)I2C0_BASE) - /** Peripheral I2C1 base address */ - #define I2C1_BASE (0x40087000u) - /** Peripheral I2C1 base pointer */ - #define I2C1 ((I2C_Type *)I2C1_BASE) - /** Peripheral I2C2 base address */ - #define I2C2_BASE (0x40088000u) - /** Peripheral I2C2 base pointer */ - #define I2C2 ((I2C_Type *)I2C2_BASE) - /** Peripheral I2C3 base address */ - #define I2C3_BASE (0x40089000u) - /** Peripheral I2C3 base pointer */ - #define I2C3 ((I2C_Type *)I2C3_BASE) - /** Peripheral I2C4 base address */ - #define I2C4_BASE (0x4008A000u) - /** Peripheral I2C4 base pointer */ - #define I2C4 ((I2C_Type *)I2C4_BASE) - /** Peripheral I2C5 base address */ - #define I2C5_BASE (0x40096000u) - /** Peripheral I2C5 base pointer */ - #define I2C5 ((I2C_Type *)I2C5_BASE) - /** Peripheral I2C6 base address */ - #define I2C6_BASE (0x40097000u) - /** Peripheral I2C6 base pointer */ - #define I2C6 ((I2C_Type *)I2C6_BASE) - /** Peripheral I2C7 base address */ - #define I2C7_BASE (0x40098000u) - /** Peripheral I2C7 base pointer */ - #define I2C7 ((I2C_Type *)I2C7_BASE) - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } -#endif -/** Interrupt vectors for the I2C peripheral type */ -#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2S Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer - * @{ - */ - -/** I2S - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[3072]; - __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ - __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ - __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ - struct { /* offset: 0xC20, array step: 0x20 */ - __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0xC20, array step: 0x20 */ - __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0xC24, array step: 0x20 */ - __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0xC28, array step: 0x20 */ - uint8_t RESERVED_0[20]; - } SECCHANNEL[3]; - uint8_t RESERVED_2[384]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ - uint8_t RESERVED_5[8]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ - uint8_t RESERVED_6[8]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ - uint8_t RESERVED_7[436]; - __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ -} I2S_Type; - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ -/*! @{ */ -#define I2S_CFG1_MAINENABLE_MASK (0x1U) -#define I2S_CFG1_MAINENABLE_SHIFT (0U) -/*! MAINENABLE - Main enable for I 2S function in this Flexcomm - * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled. - * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. - */ -#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) -#define I2S_CFG1_DATAPAUSE_MASK (0x2U) -#define I2S_CFG1_DATAPAUSE_SHIFT (1U) -/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame. - * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. - * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. - */ -#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) -#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) -#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) -/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. - * 0b00..1 I2S channel pairs in this flexcomm - * 0b01..2 I2S channel pairs in this flexcomm - * 0b10..3 I2S channel pairs in this flexcomm - * 0b11..4 I2S channel pairs in this flexcomm - */ -#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) -#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) -#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) -/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. - * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. - * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock. - * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. - * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. - */ -#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) -#define I2S_CFG1_MODE_MASK (0xC0U) -#define I2S_CFG1_MODE_SHIFT (6U) -/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples. - * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. - * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. - * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. - * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. - */ -#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) -#define I2S_CFG1_RIGHTLOW_MASK (0x100U) -#define I2S_CFG1_RIGHTLOW_SHIFT (8U) -/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. - * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel. - * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel. - */ -#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) -#define I2S_CFG1_LEFTJUST_MASK (0x200U) -#define I2S_CFG1_LEFTJUST_SHIFT (9U) -/*! LEFTJUST - Left Justify data. - * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus. - * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus. - */ -#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) -#define I2S_CFG1_ONECHANNEL_MASK (0x400U) -#define I2S_CFG1_ONECHANNEL_SHIFT (10U) -/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers. - * 0b0..I2S data for this channel pair is treated as left and right channels. - * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION. - */ -#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) -#define I2S_CFG1_PDMDATA_MASK (0x800U) -#define I2S_CFG1_PDMDATA_SHIFT (11U) -/*! PDMDATA - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC55xx, this bit applies only to Flexcomm 6,7. - * 0b0..Normal operation, data is transferred to or from the Flexcomm FIFO. - * 0b1..The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun. - */ -#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK) -#define I2S_CFG1_SCK_POL_MASK (0x1000U) -#define I2S_CFG1_SCK_POL_SHIFT (12U) -/*! SCK_POL - SCK polarity. - * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). - * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. - */ -#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) -#define I2S_CFG1_WS_POL_MASK (0x2000U) -#define I2S_CFG1_WS_POL_SHIFT (13U) -/*! WS_POL - WS polarity. - * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). - * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). - */ -#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) -#define I2S_CFG1_DATALEN_MASK (0x1F0000U) -#define I2S_CFG1_DATALEN_SHIFT (16U) -#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) -/*! @} */ - -/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ -/*! @{ */ -#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) -#define I2S_CFG2_FRAMELEN_SHIFT (0U) -#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) -#define I2S_CFG2_POSITION_MASK (0x1FF0000U) -#define I2S_CFG2_POSITION_SHIFT (16U) -#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) -/*! @} */ - -/*! @name STAT - Status register for the primary channel pair. */ -/*! @{ */ -#define I2S_STAT_BUSY_MASK (0x1U) -#define I2S_STAT_BUSY_SHIFT (0U) -/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. - * 0b0..The transmitter/receiver for channel pair is currently idle. - * 0b1..The transmitter/receiver for channel pair is currently processing data. - */ -#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) -#define I2S_STAT_SLVFRMERR_MASK (0x2U) -#define I2S_STAT_SLVFRMERR_SHIFT (1U) -/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream. - * 0b0..No error has been recorded. - * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. - */ -#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) -#define I2S_STAT_LR_MASK (0x4U) -#define I2S_STAT_LR_SHIFT (2U) -/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair. - * 0b0..Left channel. - * 0b1..Right channel. - */ -#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) -#define I2S_STAT_DATAPAUSED_MASK (0x8U) -#define I2S_STAT_DATAPAUSED_SHIFT (3U) -/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels - * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. - * 0b1..A data pause has been requested and is now in force. - */ -#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) -/*! @} */ - -/*! @name DIV - Clock divider, used by all channel pairs. */ -/*! @{ */ -#define I2S_DIV_DIV_MASK (0xFFFU) -#define I2S_DIV_DIV_SHIFT (0U) -#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) -/*! @} */ - -/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */ -/*! @{ */ -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U) -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U) -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PCFG1 */ -#define I2S_SECCHANNEL_PCFG1_COUNT (3U) - -/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */ -/*! @{ */ -#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U) -#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U) -#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PCFG2 */ -#define I2S_SECCHANNEL_PCFG2_COUNT (3U) - -/*! @name SECCHANNEL_PSTAT - Status register for channel pair */ -/*! @{ */ -#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U) -#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U) -#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK) -#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U) -#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U) -#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PSTAT */ -#define I2S_SECCHANNEL_PSTAT_COUNT (3U) - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ -#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) -#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) -#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) -#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused. - * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 bits or less, or when MONO = 1 for this channel pair. - * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. - */ -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. - * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. - * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. - */ -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) -#define I2S_FIFOCFG_SIZE_MASK (0x30U) -#define I2S_FIFOCFG_SIZE_SHIFT (4U) -#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) -#define I2S_FIFOCFG_DMATX_MASK (0x1000U) -#define I2S_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) -#define I2S_FIFOCFG_DMARX_MASK (0x2000U) -#define I2S_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) -#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) -#define I2S_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) -#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) -#define I2S_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) -#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) -#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) -#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) -#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) -#define I2S_FIFOCFG_POPDBG_MASK (0x40000U) -#define I2S_FIFOCFG_POPDBG_SHIFT (18U) -/*! POPDBG - Pop FIFO for debug reads. - * 0b0..Debug reads of the FIFO do not pop the FIFO. - * 0b1..A debug read will cause the FIFO to pop. - */ -#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ -#define I2S_FIFOSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOSTAT_TXERR_SHIFT (0U) -#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) -#define I2S_FIFOSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOSTAT_RXERR_SHIFT (1U) -#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) -#define I2S_FIFOSTAT_PERINT_MASK (0x8U) -#define I2S_FIFOSTAT_PERINT_SHIFT (3U) -#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) -#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) -#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) -#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) -#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) -#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) -#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) -#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) -#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) -#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) -#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ -#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) -#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) -#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) -#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) -#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) -#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) -#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ -#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) -#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) -#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) -#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) -#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - */ -#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) -#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ -#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) -#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) -#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) -#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) -#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) -#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) -#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) -#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ -#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) -#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) -#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) -#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) -#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) -#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) -#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) -#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) -#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ -#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFOWR_TXDATA_SHIFT (0U) -#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ -#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) -#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) -#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ -#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORD_RXDATA_SHIFT (0U) -#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ -#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48H_RXDATA_SHIFT (0U) -#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ -#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ -#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) -#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name ID - I2S Module identification */ -/*! @{ */ -#define I2S_ID_Aperture_MASK (0xFFU) -#define I2S_ID_Aperture_SHIFT (0U) -#define I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK) -#define I2S_ID_Minor_Rev_MASK (0xF00U) -#define I2S_ID_Minor_Rev_SHIFT (8U) -#define I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK) -#define I2S_ID_Major_Rev_MASK (0xF000U) -#define I2S_ID_Major_Rev_SHIFT (12U) -#define I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK) -#define I2S_ID_ID_MASK (0xFFFF0000U) -#define I2S_ID_ID_SHIFT (16U) -#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2S_Register_Masks */ - - -/* I2S - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral I2S0 base address */ - #define I2S0_BASE (0x50086000u) - /** Peripheral I2S0 base address */ - #define I2S0_BASE_NS (0x40086000u) - /** Peripheral I2S0 base pointer */ - #define I2S0 ((I2S_Type *)I2S0_BASE) - /** Peripheral I2S0 base pointer */ - #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) - /** Peripheral I2S1 base address */ - #define I2S1_BASE (0x50087000u) - /** Peripheral I2S1 base address */ - #define I2S1_BASE_NS (0x40087000u) - /** Peripheral I2S1 base pointer */ - #define I2S1 ((I2S_Type *)I2S1_BASE) - /** Peripheral I2S1 base pointer */ - #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) - /** Peripheral I2S2 base address */ - #define I2S2_BASE (0x50088000u) - /** Peripheral I2S2 base address */ - #define I2S2_BASE_NS (0x40088000u) - /** Peripheral I2S2 base pointer */ - #define I2S2 ((I2S_Type *)I2S2_BASE) - /** Peripheral I2S2 base pointer */ - #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) - /** Peripheral I2S3 base address */ - #define I2S3_BASE (0x50089000u) - /** Peripheral I2S3 base address */ - #define I2S3_BASE_NS (0x40089000u) - /** Peripheral I2S3 base pointer */ - #define I2S3 ((I2S_Type *)I2S3_BASE) - /** Peripheral I2S3 base pointer */ - #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) - /** Peripheral I2S4 base address */ - #define I2S4_BASE (0x5008A000u) - /** Peripheral I2S4 base address */ - #define I2S4_BASE_NS (0x4008A000u) - /** Peripheral I2S4 base pointer */ - #define I2S4 ((I2S_Type *)I2S4_BASE) - /** Peripheral I2S4 base pointer */ - #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) - /** Peripheral I2S5 base address */ - #define I2S5_BASE (0x50096000u) - /** Peripheral I2S5 base address */ - #define I2S5_BASE_NS (0x40096000u) - /** Peripheral I2S5 base pointer */ - #define I2S5 ((I2S_Type *)I2S5_BASE) - /** Peripheral I2S5 base pointer */ - #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) - /** Peripheral I2S6 base address */ - #define I2S6_BASE (0x50097000u) - /** Peripheral I2S6 base address */ - #define I2S6_BASE_NS (0x40097000u) - /** Peripheral I2S6 base pointer */ - #define I2S6 ((I2S_Type *)I2S6_BASE) - /** Peripheral I2S6 base pointer */ - #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) - /** Peripheral I2S7 base address */ - #define I2S7_BASE (0x50098000u) - /** Peripheral I2S7 base address */ - #define I2S7_BASE_NS (0x40098000u) - /** Peripheral I2S7 base pointer */ - #define I2S7 ((I2S_Type *)I2S7_BASE) - /** Peripheral I2S7 base pointer */ - #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } -#else - /** Peripheral I2S0 base address */ - #define I2S0_BASE (0x40086000u) - /** Peripheral I2S0 base pointer */ - #define I2S0 ((I2S_Type *)I2S0_BASE) - /** Peripheral I2S1 base address */ - #define I2S1_BASE (0x40087000u) - /** Peripheral I2S1 base pointer */ - #define I2S1 ((I2S_Type *)I2S1_BASE) - /** Peripheral I2S2 base address */ - #define I2S2_BASE (0x40088000u) - /** Peripheral I2S2 base pointer */ - #define I2S2 ((I2S_Type *)I2S2_BASE) - /** Peripheral I2S3 base address */ - #define I2S3_BASE (0x40089000u) - /** Peripheral I2S3 base pointer */ - #define I2S3 ((I2S_Type *)I2S3_BASE) - /** Peripheral I2S4 base address */ - #define I2S4_BASE (0x4008A000u) - /** Peripheral I2S4 base pointer */ - #define I2S4 ((I2S_Type *)I2S4_BASE) - /** Peripheral I2S5 base address */ - #define I2S5_BASE (0x40096000u) - /** Peripheral I2S5 base pointer */ - #define I2S5 ((I2S_Type *)I2S5_BASE) - /** Peripheral I2S6 base address */ - #define I2S6_BASE (0x40097000u) - /** Peripheral I2S6 base pointer */ - #define I2S6 ((I2S_Type *)I2S6_BASE) - /** Peripheral I2S7 base address */ - #define I2S7_BASE (0x40098000u) - /** Peripheral I2S7 base pointer */ - #define I2S7 ((I2S_Type *)I2S7_BASE) - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } -#endif -/** Interrupt vectors for the I2S peripheral type */ -#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2S_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer - * @{ - */ - -/** INPUTMUX - Register Layout Typedef */ -typedef struct { - __IO uint32_t SCT0_INMUX[7]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t TIMER0CAPTSEL[4]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[16]; - __IO uint32_t TIMER1CAPTSEL[4]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_2[16]; - __IO uint32_t TIMER2CAPTSEL[4]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */ - uint8_t RESERVED_3[80]; - __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ - __IO uint32_t DMA0_ITRIG_INMUX[23]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_4[36]; - __IO uint32_t DMA0_OTRIG_INMUX[4]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */ - uint8_t RESERVED_5[16]; - __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ - __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ - uint8_t RESERVED_6[24]; - __IO uint32_t TIMER3CAPTSEL[4]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */ - uint8_t RESERVED_7[16]; - __IO uint32_t TIMER4CAPTSEL[4]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */ - uint8_t RESERVED_8[16]; - __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */ - uint8_t RESERVED_9[24]; - __IO uint32_t DMA1_ITRIG_INMUX[10]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_10[24]; - __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_11[1264]; - __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */ - uint8_t RESERVED_12[4]; - __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */ - uint8_t RESERVED_13[4]; - __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */ - uint8_t RESERVED_14[12]; - __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */ - uint8_t RESERVED_15[4]; - __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */ - uint8_t RESERVED_16[4]; - __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */ - uint8_t RESERVED_17[12]; - __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */ - uint8_t RESERVED_18[4]; - __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */ - uint8_t RESERVED_19[4]; - __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */ - uint8_t RESERVED_20[12]; - __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */ - uint8_t RESERVED_21[4]; - __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */ - uint8_t RESERVED_22[4]; - __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */ -} INPUTMUX_Type; - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks - * @{ - */ - -/*! @name SCT0_INMUX - Input mux register for SCT0 input */ -/*! @{ */ -#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) -#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) -/*! INP_N - Input number to SCT0 inputs 0 to 6.. - * 0b00000..SCT_GPI0 function selected from IOCON register - * 0b00001..SCT_GPI1 function selected from IOCON register - * 0b00010..SCT_GPI2 function selected from IOCON register - * 0b00011..SCT_GPI3 function selected from IOCON register - * 0b00100..SCT_GPI4 function selected from IOCON register - * 0b00101..SCT_GPI5 function selected from IOCON register - * 0b00110..SCT_GPI6 function selected from IOCON register - * 0b00111..SCT_GPI7 function selected from IOCON register - * 0b01000..T0_OUT0 ctimer 0 match[0] output - * 0b01001..T1_OUT0 ctimer 1 match[0] output - * 0b01010..T2_OUT0 ctimer 2 match[0] output - * 0b01011..T3_OUT0 ctimer 3 match[0] output - * 0b01100..T4_OUT0 ctimer 4 match[0] output - * 0b01101..ADC_IRQ interrupt request from ADC - * 0b01110..GPIOINT_BMATCH - * 0b01111..USB0_FRAME_TOGGLE - * 0b10000..USB1_FRAME_TOGGLE - * 0b10001..COMP_OUTPUT output from analog comparator - * 0b10010..I2S_SHARED_SCK[0] output from I2S pin sharing - * 0b10011..I2S_SHARED_SCK[1] output from I2S pin sharing - * 0b10100..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b10101..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b10110..ARM_TXEV interrupt event from cpu0 or cpu1 - * 0b10111..DEBUG_HALTED from cpu0 or cpu1 - * 0b11000-0b11111..None - */ -#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) -/*! @} */ - -/* The count of INPUTMUX_SCT0_INMUX */ -#define INPUTMUX_SCT0_INMUX_COUNT (7U) - -/*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */ -/*! @{ */ -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER0CAPTSEL */ -#define INPUTMUX_TIMER0CAPTSEL_COUNT (4U) - -/*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */ -/*! @{ */ -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER1CAPTSEL */ -#define INPUTMUX_TIMER1CAPTSEL_COUNT (4U) - -/*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */ -/*! @{ */ -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER2CAPTSEL */ -#define INPUTMUX_TIMER2CAPTSEL_COUNT (4U) - -/*! @name PINTSEL - Pin interrupt select register */ -/*! @{ */ -#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) -#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) -#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSEL */ -#define INPUTMUX_PINTSEL_COUNT (8U) - -/*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */ -/*! @{ */ -#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) -/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). - * 0b00000..Pin interrupt 0 - * 0b00001..Pin interrupt 1 - * 0b00010..Pin interrupt 2 - * 0b00011..Pin interrupt 3 - * 0b00100..Timer CTIMER0 Match 0 - * 0b00101..Timer CTIMER0 Match 1 - * 0b00110..Timer CTIMER1 Match 0 - * 0b00111..Timer CTIMER1 Match 1 - * 0b01000..Timer CTIMER2 Match 0 - * 0b01001..Timer CTIMER2 Match 1 - * 0b01010..Timer CTIMER3 Match 0 - * 0b01011..Timer CTIMER3 Match 1 - * 0b01100..Timer CTIMER4 Match 0 - * 0b01101..Timer CTIMER4 Match 1 - * 0b01110..COMP_OUTPUT - * 0b01111..DMA0 output trigger mux 0 - * 0b10000..DMA0 output trigger mux 1 - * 0b10001..DMA0 output trigger mux 1 - * 0b10010..DMA0 output trigger mux 3 - * 0b10011..SCT0 DMA request 0 - * 0b10100..SCT0 DMA request 1 - * 0b10101..HASH DMA RX trigger - * 0b10110-0b11111..None - */ -#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA0_ITRIG_INMUX */ -#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (23U) - -/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */ -/*! @{ */ -#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) -#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA0_OTRIG_INMUX */ -#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (4U) - -/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ -/*! @{ */ -#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) -#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) -/*! @} */ - -/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ -/*! @{ */ -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) -#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) -/*! @} */ - -/*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */ -/*! @{ */ -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER3CAPTSEL */ -#define INPUTMUX_TIMER3CAPTSEL_COUNT (4U) - -/*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */ -/*! @{ */ -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER4CAPTSEL */ -#define INPUTMUX_TIMER4CAPTSEL_COUNT (4U) - -/*! @name PINTSECSEL - Pin interrupt secure select register */ -/*! @{ */ -#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) -#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) -#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSECSEL */ -#define INPUTMUX_PINTSECSEL_COUNT (2U) - -/*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */ -/*! @{ */ -#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU) -#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) -/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). - * 0b0000..Pin interrupt 0 - * 0b0001..Pin interrupt 1 - * 0b0010..Pin interrupt 2 - * 0b0011..Pin interrupt 3 - * 0b0100..Timer CTIMER0 Match 0 - * 0b0101..Timer CTIMER0 Match 1 - * 0b0110..Timer CTIMER2 Match 0 - * 0b0111..Timer CTIMER4 Match 0 - * 0b1000..DMA1 output trigger mux 0 - * 0b1001..DMA1 output trigger mux 1 - * 0b1010..DMA1 output trigger mux 2 - * 0b1011..DMA1 output trigger mux 3 - * 0b1100..SCT0 DMA request 0 - * 0b1101..SCT0 DMA request 1 - * 0b1110..HASH DMA RX trigger - * 0b1111..None - */ -#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA1_ITRIG_INMUX */ -#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (10U) - -/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */ -/*! @{ */ -#define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU) -#define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U) -#define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA1_OTRIG_INMUX */ -#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U) - -/*! @name DMA0_REQ_ENA - Enable DMA0 requests */ -/*! @{ */ -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U) -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK) -/*! @} */ - -/*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */ -/*! @{ */ -#define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U) -#define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */ -/*! @{ */ -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U) -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA - Enable DMA1 requests */ -/*! @{ */ -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U) -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */ -/*! @{ */ -#define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U) -#define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */ -/*! @{ */ -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U) -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */ -/*! @{ */ -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */ -/*! @{ */ -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U) -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */ -/*! @{ */ -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U) -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */ -/*! @{ */ -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */ -/*! @{ */ -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U) -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */ -/*! @{ */ -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U) -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group INPUTMUX_Register_Masks */ - - -/* INPUTMUX - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE (0x50006000u) - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE_NS (0x40006000u) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS { INPUTMUX } - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } -#else - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE (0x40006000u) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS { INPUTMUX } -#endif - -/*! - * @} - */ /* end of group INPUTMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- IOCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer - * @{ - */ - -/** IOCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ -} IOCON_Type; - -/* ---------------------------------------------------------------------------- - -- IOCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Register_Masks IOCON Register Masks - * @{ - */ - -/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ -/*! @{ */ -#define IOCON_PIO_FUNC_MASK (0xFU) -#define IOCON_PIO_FUNC_SHIFT (0U) -/*! FUNC - Selects pin function. - * 0b0000..Alternative connection 0. - * 0b0001..Alternative connection 1. - * 0b0010..Alternative connection 2. - * 0b0011..Alternative connection 3. - * 0b0100..Alternative connection 4. - * 0b0101..Alternative connection 5. - * 0b0110..Alternative connection 6. - * 0b0111..Alternative connection 7. - */ -#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) -#define IOCON_PIO_MODE_MASK (0x30U) -#define IOCON_PIO_MODE_SHIFT (4U) -/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) -#define IOCON_PIO_SLEW_MASK (0x40U) -#define IOCON_PIO_SLEW_SHIFT (6U) -/*! SLEW - Driver slew rate. - * 0b0..Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. - * 0b1..Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. - */ -#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) -#define IOCON_PIO_INVERT_MASK (0x80U) -#define IOCON_PIO_INVERT_SHIFT (7U) -/*! INVERT - Input polarity. - * 0b0..Disabled. Input function is not inverted. - * 0b1..Enabled. Input is function inverted. - */ -#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) -#define IOCON_PIO_DIGIMODE_MASK (0x100U) -#define IOCON_PIO_DIGIMODE_SHIFT (8U) -/*! DIGIMODE - Select Digital mode. - * 0b0..Analog mode, digital input is disabled. - * 0b1..Digital mode, digital input is enabled. - */ -#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) -#define IOCON_PIO_OD_MASK (0x200U) -#define IOCON_PIO_OD_SHIFT (9U) -/*! OD - Controls open-drain mode. - * 0b0..Normal. Normal push-pull output - * 0b1..Open-drain. Simulated open-drain output (high drive disabled). - */ -#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) -#define IOCON_PIO_ASW_MASK (0x400U) -#define IOCON_PIO_ASW_SHIFT (10U) -/*! ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 - * 0b0..Analog switch is open. - * 0b1..Analog switch is closed. - */ -#define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK) -#define IOCON_PIO_SSEL_MASK (0x800U) -#define IOCON_PIO_SSEL_SHIFT (11U) -/*! SSEL - Supply Selection bit. - * 0b0..3V3 Signaling in I2C Mode. - * 0b1..1V8 Signaling in I2C Mode. - */ -#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) -#define IOCON_PIO_FILTEROFF_MASK (0x1000U) -#define IOCON_PIO_FILTEROFF_SHIFT (12U) -/*! FILTEROFF - Controls input glitch filter. - * 0b0..Filter enabled. Noise pulses below approximately 10 ns are filtered out. - * 0b1..Filter disabled. No input filtering is done. - */ -#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) -#define IOCON_PIO_ECS_MASK (0x2000U) -#define IOCON_PIO_ECS_SHIFT (13U) -/*! ECS - Pull-up current source enable in IIC mode. - * 0b1..Enabled. Pull resistor is conencted. - * 0b0..Disabled. IO is in open drain. - */ -#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) -#define IOCON_PIO_EGP_MASK (0x4000U) -#define IOCON_PIO_EGP_SHIFT (14U) -/*! EGP - Controls slew rate of I2C pad. - * 0b0..I2C mode. - * 0b1..GPIO mode. - */ -#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) -#define IOCON_PIO_I2CFILTER_MASK (0x8000U) -#define IOCON_PIO_I2CFILTER_SHIFT (15U) -/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. - * 0b0..I2C 50 ns glitch filter enabled. Typically used for Fast-mode and Fast-mode Plus I2C. - * 0b1..I2C 10 ns glitch filter enabled. Typically used for Standard-mode I2C. - */ -#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) -/*! @} */ - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT (2U) - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT2 (32U) - - -/*! - * @} - */ /* end of group IOCON_Register_Masks */ - - -/* IOCON - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral IOCON base address */ - #define IOCON_BASE (0x50001000u) - /** Peripheral IOCON base address */ - #define IOCON_BASE_NS (0x40001000u) - /** Peripheral IOCON base pointer */ - #define IOCON ((IOCON_Type *)IOCON_BASE) - /** Peripheral IOCON base pointer */ - #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS { IOCON_BASE } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS { IOCON } - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS_NS { IOCON_NS } -#else - /** Peripheral IOCON base address */ - #define IOCON_BASE (0x40001000u) - /** Peripheral IOCON base pointer */ - #define IOCON ((IOCON_Type *)IOCON_BASE) - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS { IOCON_BASE } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS { IOCON } -#endif - -/*! - * @} - */ /* end of group IOCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MAILBOX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer - * @{ - */ - -/** MAILBOX - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */ - __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */ - __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } MBOXIRQ[2]; - uint8_t RESERVED_0[216]; - __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */ -} MAILBOX_Type; - -/* ---------------------------------------------------------------------------- - -- MAILBOX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks - * @{ - */ - -/*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ -/*! @{ */ -#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) -#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQ */ -#define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) - -/*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ -/*! @{ */ -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQSET */ -#define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) - -/*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ -/*! @{ */ -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQCLR */ -#define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) - -/*! @name MUTEX - Mutual exclusion register[1] */ -/*! @{ */ -#define MAILBOX_MUTEX_EX_MASK (0x1U) -#define MAILBOX_MUTEX_EX_SHIFT (0U) -#define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MAILBOX_Register_Masks */ - - -/* MAILBOX - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral MAILBOX base address */ - #define MAILBOX_BASE (0x5008B000u) - /** Peripheral MAILBOX base address */ - #define MAILBOX_BASE_NS (0x4008B000u) - /** Peripheral MAILBOX base pointer */ - #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) - /** Peripheral MAILBOX base pointer */ - #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) - /** Array initializer of MAILBOX peripheral base addresses */ - #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } - /** Array initializer of MAILBOX peripheral base pointers */ - #define MAILBOX_BASE_PTRS { MAILBOX } - /** Array initializer of MAILBOX peripheral base addresses */ - #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } - /** Array initializer of MAILBOX peripheral base pointers */ - #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } -#else - /** Peripheral MAILBOX base address */ - #define MAILBOX_BASE (0x4008B000u) - /** Peripheral MAILBOX base pointer */ - #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) - /** Array initializer of MAILBOX peripheral base addresses */ - #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } - /** Array initializer of MAILBOX peripheral base pointers */ - #define MAILBOX_BASE_PTRS { MAILBOX } -#endif -/** Interrupt vectors for the MAILBOX peripheral type */ -#define MAILBOX_IRQS { MAILBOX_IRQn } - -/*! - * @} - */ /* end of group MAILBOX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MRT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer - * @{ - */ - -/** MRT - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ - __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ - __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ - __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ - } CHANNEL[4]; - uint8_t RESERVED_0[176]; - __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ - __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ - __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ -} MRT_Type; - -/* ---------------------------------------------------------------------------- - -- MRT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Register_Masks MRT Register Masks - * @{ - */ - -/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ -/*! @{ */ -#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) -#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) -#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) -#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) -/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. - * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. - * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. - */ -#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_INTVAL */ -#define MRT_CHANNEL_INTVAL_COUNT (4U) - -/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ -/*! @{ */ -#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) -#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_TIMER */ -#define MRT_CHANNEL_TIMER_COUNT (4U) - -/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ -/*! @{ */ -#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) -#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) -/*! INTEN - Enable the TIMERn interrupt. - * 0b0..Disabled. TIMERn interrupt is disabled. - * 0b1..Enabled. TIMERn interrupt is enabled. - */ -#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) -#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) -#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) -/*! MODE - Selects timer mode. - * 0b00..Repeat interrupt mode. - * 0b01..One-shot interrupt mode. - * 0b10..One-shot stall mode. - * 0b11..Reserved. - */ -#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_CTRL */ -#define MRT_CHANNEL_CTRL_COUNT (4U) - -/*! @name CHANNEL_STAT - MRT Status register. */ -/*! @{ */ -#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) -#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) -/*! INTFLAG - Monitors the interrupt flag. - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. - */ -#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) -#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) -#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) -/*! RUN - Indicates the state of TIMERn. This bit is read-only. - * 0b0..Idle state. TIMERn is stopped. - * 0b1..Running. TIMERn is running. - */ -#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) -#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) -#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) -/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes. - * 0b0..This channel is not in use. - * 0b1..This channel is in use. - */ -#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_STAT */ -#define MRT_CHANNEL_STAT_COUNT (4U) - -/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ -/*! @{ */ -#define MRT_MODCFG_NOC_MASK (0xFU) -#define MRT_MODCFG_NOC_SHIFT (0U) -#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) -#define MRT_MODCFG_NOB_MASK (0x1F0U) -#define MRT_MODCFG_NOB_SHIFT (4U) -#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) -#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) -#define MRT_MODCFG_MULTITASK_SHIFT (31U) -/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. - * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. - * 0b1..Multi-task mode. - */ -#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) -/*! @} */ - -/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ -/*! @{ */ -#define MRT_IDLE_CH_CHAN_MASK (0xF0U) -#define MRT_IDLE_CH_CHAN_SHIFT (4U) -#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) -/*! @} */ - -/*! @name IRQ_FLAG - Global interrupt flag register */ -/*! @{ */ -#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) -#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) -/*! GFLAG0 - Monitors the interrupt flag of TIMER0. - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. - */ -#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) -#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) -#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) -#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) -#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) -#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) -#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) -#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) -#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) -#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MRT_Register_Masks */ - - -/* MRT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral MRT0 base address */ - #define MRT0_BASE (0x5000D000u) - /** Peripheral MRT0 base address */ - #define MRT0_BASE_NS (0x4000D000u) - /** Peripheral MRT0 base pointer */ - #define MRT0 ((MRT_Type *)MRT0_BASE) - /** Peripheral MRT0 base pointer */ - #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS { MRT0_BASE } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS { MRT0 } - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS_NS { MRT0_NS } -#else - /** Peripheral MRT0 base address */ - #define MRT0_BASE (0x4000D000u) - /** Peripheral MRT0 base pointer */ - #define MRT0 ((MRT_Type *)MRT0_BASE) - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS { MRT0_BASE } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS { MRT0 } -#endif -/** Interrupt vectors for the MRT peripheral type */ -#define MRT_IRQS { MRT0_IRQn } - -/*! - * @} - */ /* end of group MRT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- OSTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer - * @{ - */ - -/** OSTIMER - Register Layout Typedef */ -typedef struct { - __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ - __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ - __I uint32_t CAPTUREN_L; /**< Local Capture Low Register for CPUn, offset: 0x8 */ - __I uint32_t CAPTUREN_H; /**< Local Capture High Register for CPUn, offset: 0xC */ - __IO uint32_t MATCHN_L; /**< Local Match Low Register for CPUn, offset: 0x10 */ - __IO uint32_t MATCHN_H; /**< Match High Register for CPUn, offset: 0x14 */ - uint8_t RESERVED_0[4]; - __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register for CPUn, offset: 0x1C */ -} OSTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- OSTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks - * @{ - */ - -/*! @name EVTIMERL - EVTIMER Low Register */ -/*! @{ */ -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) -/*! @} */ - -/*! @name EVTIMERH - EVTIMER High Register */ -/*! @{ */ -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) -/*! @} */ - -/*! @name CAPTUREN_L - Local Capture Low Register for CPUn */ -/*! @{ */ -#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT (0U) -#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK) -/*! @} */ - -/*! @name CAPTUREN_H - Local Capture High Register for CPUn */ -/*! @{ */ -#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT (0U) -#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK) -/*! @} */ - -/*! @name MATCHN_L - Local Match Low Register for CPUn */ -/*! @{ */ -#define OSTIMER_MATCHN_L_MATCHn_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT (0U) -#define OSTIMER_MATCHN_L_MATCHn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_L_MATCHn_VALUE_MASK) -/*! @} */ - -/*! @name MATCHN_H - Match High Register for CPUn */ -/*! @{ */ -#define OSTIMER_MATCHN_H_MATCHn_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT (0U) -#define OSTIMER_MATCHN_H_MATCHn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_H_MATCHn_VALUE_MASK) -/*! @} */ - -/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register for CPUn */ -/*! @{ */ -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group OSTIMER_Register_Masks */ - - -/* OSTIMER - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE (0x5002D000u) - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE_NS (0x4002D000u) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS) - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS { OSTIMER } - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS } -#else - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE (0x4002D000u) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS { OSTIMER } -#endif -/** Interrupt vectors for the OSTIMER peripheral type */ -#define OSTIMER_IRQS { OS_EVENT_IRQn } - -/*! - * @} - */ /* end of group OSTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer - * @{ - */ - -/** PINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ - __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ - __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ - __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ - __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ - __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ - __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ - __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ - __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ - __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ - __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ - __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ - __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ -} PINT_Type; - -/* ---------------------------------------------------------------------------- - -- PINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Register_Masks PINT Register Masks - * @{ - */ - -/*! @name ISEL - Pin Interrupt Mode register */ -/*! @{ */ -#define PINT_ISEL_PMODE_MASK (0xFFU) -#define PINT_ISEL_PMODE_SHIFT (0U) -#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) -/*! @} */ - -/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ -/*! @{ */ -#define PINT_IENR_ENRL_MASK (0xFFU) -#define PINT_IENR_ENRL_SHIFT (0U) -#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) -/*! @} */ - -/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ -/*! @{ */ -#define PINT_SIENR_SETENRL_MASK (0xFFU) -#define PINT_SIENR_SETENRL_SHIFT (0U) -#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) -/*! @} */ - -/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ -/*! @{ */ -#define PINT_CIENR_CENRL_MASK (0xFFU) -#define PINT_CIENR_CENRL_SHIFT (0U) -#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) -/*! @} */ - -/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ -/*! @{ */ -#define PINT_IENF_ENAF_MASK (0xFFU) -#define PINT_IENF_ENAF_SHIFT (0U) -#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) -/*! @} */ - -/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ -/*! @{ */ -#define PINT_SIENF_SETENAF_MASK (0xFFU) -#define PINT_SIENF_SETENAF_SHIFT (0U) -#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) -/*! @} */ - -/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ -/*! @{ */ -#define PINT_CIENF_CENAF_MASK (0xFFU) -#define PINT_CIENF_CENAF_SHIFT (0U) -#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) -/*! @} */ - -/*! @name RISE - Pin interrupt rising edge register */ -/*! @{ */ -#define PINT_RISE_RDET_MASK (0xFFU) -#define PINT_RISE_RDET_SHIFT (0U) -#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) -/*! @} */ - -/*! @name FALL - Pin interrupt falling edge register */ -/*! @{ */ -#define PINT_FALL_FDET_MASK (0xFFU) -#define PINT_FALL_FDET_SHIFT (0U) -#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) -/*! @} */ - -/*! @name IST - Pin interrupt status register */ -/*! @{ */ -#define PINT_IST_PSTAT_MASK (0xFFU) -#define PINT_IST_PSTAT_SHIFT (0U) -#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) -/*! @} */ - -/*! @name PMCTRL - Pattern match interrupt control register */ -/*! @{ */ -#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) -#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) -/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. - * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. - * 0b1..Pattern match. Interrupts are driven in response to pattern matches. - */ -#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) -#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) -#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) -/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. - * 0b0..Disabled. RXEV output to the CPU is disabled. - * 0b1..Enabled. RXEV output to the CPU is enabled. - */ -#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) -#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) -#define PINT_PMCTRL_PMAT_SHIFT (24U) -#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) -/*! @} */ - -/*! @name PMSRC - Pattern match interrupt bit-slice source register */ -/*! @{ */ -#define PINT_PMSRC_SRC0_MASK (0x700U) -#define PINT_PMSRC_SRC0_SHIFT (8U) -/*! SRC0 - Selects the input source for bit slice 0 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. - */ -#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) -#define PINT_PMSRC_SRC1_MASK (0x3800U) -#define PINT_PMSRC_SRC1_SHIFT (11U) -/*! SRC1 - Selects the input source for bit slice 1 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. - */ -#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) -#define PINT_PMSRC_SRC2_MASK (0x1C000U) -#define PINT_PMSRC_SRC2_SHIFT (14U) -/*! SRC2 - Selects the input source for bit slice 2 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. - */ -#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) -#define PINT_PMSRC_SRC3_MASK (0xE0000U) -#define PINT_PMSRC_SRC3_SHIFT (17U) -/*! SRC3 - Selects the input source for bit slice 3 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. - */ -#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) -#define PINT_PMSRC_SRC4_MASK (0x700000U) -#define PINT_PMSRC_SRC4_SHIFT (20U) -/*! SRC4 - Selects the input source for bit slice 4 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. - */ -#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) -#define PINT_PMSRC_SRC5_MASK (0x3800000U) -#define PINT_PMSRC_SRC5_SHIFT (23U) -/*! SRC5 - Selects the input source for bit slice 5 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. - */ -#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) -#define PINT_PMSRC_SRC6_MASK (0x1C000000U) -#define PINT_PMSRC_SRC6_SHIFT (26U) -/*! SRC6 - Selects the input source for bit slice 6 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. - */ -#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) -#define PINT_PMSRC_SRC7_MASK (0xE0000000U) -#define PINT_PMSRC_SRC7_SHIFT (29U) -/*! SRC7 - Selects the input source for bit slice 7 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. - */ -#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) -/*! @} */ - -/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ -/*! @{ */ -#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) -#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) -/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. - * 0b0..No effect. Slice 0 is not an endpoint. - * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) -#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) -#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) -/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. - * 0b0..No effect. Slice 1 is not an endpoint. - * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) -#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) -#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) -/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. - * 0b0..No effect. Slice 2 is not an endpoint. - * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) -#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) -#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) -/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. - * 0b0..No effect. Slice 3 is not an endpoint. - * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) -#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) -#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) -/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. - * 0b0..No effect. Slice 4 is not an endpoint. - * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) -#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) -#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) -/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. - * 0b0..No effect. Slice 5 is not an endpoint. - * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) -#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) -#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) -/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. - * 0b0..No effect. Slice 6 is not an endpoint. - * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) -#define PINT_PMCFG_CFG0_MASK (0x700U) -#define PINT_PMCFG_CFG0_SHIFT (8U) -/*! CFG0 - Specifies the match contribution condition for bit slice 0. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) -#define PINT_PMCFG_CFG1_MASK (0x3800U) -#define PINT_PMCFG_CFG1_SHIFT (11U) -/*! CFG1 - Specifies the match contribution condition for bit slice 1. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) -#define PINT_PMCFG_CFG2_MASK (0x1C000U) -#define PINT_PMCFG_CFG2_SHIFT (14U) -/*! CFG2 - Specifies the match contribution condition for bit slice 2. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) -#define PINT_PMCFG_CFG3_MASK (0xE0000U) -#define PINT_PMCFG_CFG3_SHIFT (17U) -/*! CFG3 - Specifies the match contribution condition for bit slice 3. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) -#define PINT_PMCFG_CFG4_MASK (0x700000U) -#define PINT_PMCFG_CFG4_SHIFT (20U) -/*! CFG4 - Specifies the match contribution condition for bit slice 4. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) -#define PINT_PMCFG_CFG5_MASK (0x3800000U) -#define PINT_PMCFG_CFG5_SHIFT (23U) -/*! CFG5 - Specifies the match contribution condition for bit slice 5. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) -#define PINT_PMCFG_CFG6_MASK (0x1C000000U) -#define PINT_PMCFG_CFG6_SHIFT (26U) -/*! CFG6 - Specifies the match contribution condition for bit slice 6. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) -#define PINT_PMCFG_CFG7_MASK (0xE0000000U) -#define PINT_PMCFG_CFG7_SHIFT (29U) -/*! CFG7 - Specifies the match contribution condition for bit slice 7. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PINT_Register_Masks */ - - -/* PINT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral PINT base address */ - #define PINT_BASE (0x50004000u) - /** Peripheral PINT base address */ - #define PINT_BASE_NS (0x40004000u) - /** Peripheral PINT base pointer */ - #define PINT ((PINT_Type *)PINT_BASE) - /** Peripheral PINT base pointer */ - #define PINT_NS ((PINT_Type *)PINT_BASE_NS) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE (0x50005000u) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE_NS (0x40005000u) - /** Peripheral SECPINT base pointer */ - #define SECPINT ((PINT_Type *)SECPINT_BASE) - /** Peripheral SECPINT base pointer */ - #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS { PINT, SECPINT } - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } -#else - /** Peripheral PINT base address */ - #define PINT_BASE (0x40004000u) - /** Peripheral PINT base pointer */ - #define PINT ((PINT_Type *)PINT_BASE) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE (0x40005000u) - /** Peripheral SECPINT base pointer */ - #define SECPINT ((PINT_Type *)SECPINT_BASE) - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS { PINT, SECPINT } -#endif -/** Interrupt vectors for the PINT peripheral type */ -#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } - -/*! - * @} - */ /* end of group PINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PLU Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer - * @{ - */ - -/** PLU - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x20 */ - __IO uint32_t INP[5]; /**< LUT0 input 0 MUX..LUT25 input 4 MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ - uint8_t RESERVED_0[12]; - } LUT[26]; - uint8_t RESERVED_0[1216]; - __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ - uint8_t RESERVED_1[152]; - __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ - __IO uint32_t WAKEINT; /**< Wakeup interrupt control for PLU, offset: 0x904 */ - uint8_t RESERVED_2[760]; - __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ -} PLU_Type; - -/* ---------------------------------------------------------------------------- - -- PLU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PLU_Register_Masks PLU Register Masks - * @{ - */ - -/*! @name LUT_INP - LUT0 input 0 MUX..LUT25 input 4 MUX */ -/*! @{ */ -#define PLU_LUT_INP_LUT_INP_MASK (0x3FU) -#define PLU_LUT_INP_LUT_INP_SHIFT (0U) -/*! LUT_INP - Selects the input source to be connected to LUT25 input4. - * 0b000000..The PLU primary inputs 0. - * 0b000001..The PLU primary inputs 1. - * 0b000010..The PLU primary inputs 2. - * 0b000011..The PLU primary inputs 3. - * 0b000100..The PLU primary inputs 4. - * 0b000101..The PLU primary inputs 5. - * 0b000110..Tie low. - * 0b000111..The output of LUT1. - * 0b001000..The output of LUT2. - * 0b001001..The output of LUT3. - * 0b001010..The output of LUT4. - * 0b001011..The output of LUT5. - * 0b001100..The output of LUT6. - * 0b001101..The output of LUT7. - * 0b001110..The output of LUT8. - * 0b001111..The output of LUT9. - * 0b010000..The output of LUT10. - * 0b010001..The output of LUT11. - * 0b010010..The output of LUT12. - * 0b010011..The output of LUT13. - * 0b010100..The output of LUT14. - * 0b010101..The output of LUT15. - * 0b010110..The output of LUT16. - * 0b010111..The output of LUT17. - * 0b011000..The output of LUT18. - * 0b011001..The output of LUT19. - * 0b011010..The output of LUT20. - * 0b011011..The output of LUT21. - * 0b011100..The output of LUT22. - * 0b011101..The output of LUT23. - * 0b011110..The output of LUT24. - * 0b011111..The output of LUT25. - * 0b100000..state(0). - * 0b100001..state(1). - * 0b100010..state(2). - * 0b100011..state(3). - */ -#define PLU_LUT_INP_LUT_INP(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_LUT_INP_SHIFT)) & PLU_LUT_INP_LUT_INP_MASK) -/*! @} */ - -/* The count of PLU_LUT_INP */ -#define PLU_LUT_INP_COUNT (26U) - -/* The count of PLU_LUT_INP */ -#define PLU_LUT_INP_COUNT2 (5U) - -/*! @name LUT_T_LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ -/*! @{ */ -#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_MASK (0xFFFFFFFFU) -#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_SHIFT (0U) -#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_SHIFT)) & PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_MASK) -/*! @} */ - -/* The count of PLU_LUT_T_LUT_TRUTH */ -#define PLU_LUT_T_LUT_TRUTH_COUNT (26U) - -/*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ -/*! @{ */ -#define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) -#define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) -#define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) -/*! @} */ - -/*! @name WAKEINT - Wakeup interrupt control for PLU */ -/*! @{ */ -#define PLU_WAKEINT_MASK_MASK (0xFFU) -#define PLU_WAKEINT_MASK_SHIFT (0U) -#define PLU_WAKEINT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_MASK_SHIFT)) & PLU_WAKEINT_MASK_MASK) -#define PLU_WAKEINT_FILTER_MODE_MASK (0x300U) -#define PLU_WAKEINT_FILTER_MODE_SHIFT (8U) -/*! FILTER_MODE - control input of the PLU, add filtering for glitch - * 0b00..Bypass mode. - * 0b01..Filter 1 clock period. - * 0b10..Filter 2 clock period. - * 0b11..Filter 3 clock period. - */ -#define PLU_WAKEINT_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_FILTER_MODE_SHIFT)) & PLU_WAKEINT_FILTER_MODE_MASK) -#define PLU_WAKEINT_FILTER_CLKSEL_MASK (0xC00U) -#define PLU_WAKEINT_FILTER_CLKSEL_SHIFT (10U) -#define PLU_WAKEINT_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_FILTER_CLKSEL_MASK) -#define PLU_WAKEINT_LATCH_ENABLE_MASK (0x1000U) -#define PLU_WAKEINT_LATCH_ENABLE_SHIFT (12U) -#define PLU_WAKEINT_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_LATCH_ENABLE_MASK) -#define PLU_WAKEINT_INTR_CLEAR_MASK (0x2000U) -#define PLU_WAKEINT_INTR_CLEAR_SHIFT (13U) -#define PLU_WAKEINT_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_INTR_CLEAR_MASK) -/*! @} */ - -/*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ -/*! @{ */ -#define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) -#define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) -/*! OUTPUTn - Selects the source to be connected to PLU Output 7. - * 0b00000..The PLU output 0. - * 0b00001..The PLU output 1. - * 0b00010..The PLU output 2. - * 0b00011..The PLU output 3. - * 0b00100..The PLU output 4. - * 0b00101..The PLU output 5. - * 0b00110..The PLU output 6. - * 0b00111..The PLU output 7. - * 0b01000..The PLU output 8. - * 0b01001..The PLU output 9. - * 0b01010..The PLU output 10. - * 0b01011..The PLU output 11. - * 0b01100..The PLU output 12. - * 0b01101..The PLU output 13. - * 0b01110..The PLU output 14. - * 0b01111..The PLU output 15. - * 0b10000..The PLU output 16. - * 0b10001..The PLU output 17. - * 0b10010..The PLU output 18. - * 0b10011..The PLU output 19. - * 0b10100..The PLU output 20. - * 0b10101..The PLU output 21. - * 0b10110..The PLU output 22. - * 0b10111..The PLU output 23. - * 0b11000..The PLU output 24. - * 0b11001..The PLU output 25. - * 0b11010..state(0). - * 0b11011..state(1). - * 0b11100..state(2). - * 0b11101..state(3). - */ -#define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK) -/*! @} */ - -/* The count of PLU_OUTPUT_MUX */ -#define PLU_OUTPUT_MUX_COUNT (8U) - - -/*! - * @} - */ /* end of group PLU_Register_Masks */ - - -/* PLU - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral PLU base address */ - #define PLU_BASE (0x5003D000u) - /** Peripheral PLU base address */ - #define PLU_BASE_NS (0x4003D000u) - /** Peripheral PLU base pointer */ - #define PLU ((PLU_Type *)PLU_BASE) - /** Peripheral PLU base pointer */ - #define PLU_NS ((PLU_Type *)PLU_BASE_NS) - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS { PLU_BASE } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS { PLU } - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS_NS { PLU_BASE_NS } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS_NS { PLU_NS } -#else - /** Peripheral PLU base address */ - #define PLU_BASE (0x4003D000u) - /** Peripheral PLU base pointer */ - #define PLU ((PLU_Type *)PLU_BASE) - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS { PLU_BASE } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS { PLU } -#endif - -/*! - * @} - */ /* end of group PLU_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer - * @{ - */ - -/** PMC - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[8]; - __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */ - __IO uint32_t RESETCAUSE; /**< Reset Cause register [Reset by: PoR], offset: 0xC */ - uint8_t RESERVED_1[32]; - __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ - uint8_t RESERVED_2[4]; - __IO uint32_t BODCORE; /**< Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x38 */ - uint8_t RESERVED_3[8]; - __IO uint32_t FRO1M; /**< 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x44 */ - __IO uint32_t FRO32K; /**< 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x48 */ - __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */ - __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */ - uint8_t RESERVED_4[20]; - __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */ - uint8_t RESERVED_5[8]; - __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */ - uint8_t RESERVED_6[12]; - __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */ - uint8_t RESERVED_7[16]; - __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */ - __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */ - uint8_t RESERVED_8[16]; - __IO uint32_t PDSLEEPCFG0; /**< Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xB0 */ - uint8_t RESERVED_9[4]; - __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */ - uint8_t RESERVED_10[4]; - __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */ - uint8_t RESERVED_11[4]; - __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */ -} PMC_Type; - -/* ---------------------------------------------------------------------------- - -- PMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Register_Masks PMC Register Masks - * @{ - */ - -/*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) -/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). - * 0b0..Reset event from DEEP POWER DOWN mode is disable. - * 0b1..Reset event from DEEP POWER DOWN mode is enable. - */ -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) -#define PMC_RESETCTRL_BODVBATRESETENABLE_MASK (0x2U) -#define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT (1U) -/*! BODVBATRESETENABLE - BOD VBAT reset enable. - * 0b0..BOD VBAT reset is disable. - * 0b1..BOD VBAT reset is enable. - */ -#define PMC_RESETCTRL_BODVBATRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK) -#define PMC_RESETCTRL_BODCORERESETENABLE_MASK (0x4U) -#define PMC_RESETCTRL_BODCORERESETENABLE_SHIFT (2U) -/*! BODCORERESETENABLE - BOD CORE reset enable. - * 0b0..BOD CORE reset is disable. - * 0b1..BOD CORE reset is enable. - */ -#define PMC_RESETCTRL_BODCORERESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENABLE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENABLE_MASK) -#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) -#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) -/*! SWRRESETENABLE - Software reset enable. - * 0b0..Software reset is disable. - * 0b1..Software reset is enable. - */ -#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) -/*! @} */ - -/*! @name RESETCAUSE - Reset Cause register [Reset by: PoR] */ -/*! @{ */ -#define PMC_RESETCAUSE_POR_MASK (0x1U) -#define PMC_RESETCAUSE_POR_SHIFT (0U) -#define PMC_RESETCAUSE_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_POR_SHIFT)) & PMC_RESETCAUSE_POR_MASK) -#define PMC_RESETCAUSE_PADRESET_MASK (0x2U) -#define PMC_RESETCAUSE_PADRESET_SHIFT (1U) -#define PMC_RESETCAUSE_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_PADRESET_SHIFT)) & PMC_RESETCAUSE_PADRESET_MASK) -#define PMC_RESETCAUSE_BODRESET_MASK (0x4U) -#define PMC_RESETCAUSE_BODRESET_SHIFT (2U) -#define PMC_RESETCAUSE_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_BODRESET_SHIFT)) & PMC_RESETCAUSE_BODRESET_MASK) -#define PMC_RESETCAUSE_SYSTEMRESET_MASK (0x8U) -#define PMC_RESETCAUSE_SYSTEMRESET_SHIFT (3U) -#define PMC_RESETCAUSE_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SYSTEMRESET_SHIFT)) & PMC_RESETCAUSE_SYSTEMRESET_MASK) -#define PMC_RESETCAUSE_WDTRESET_MASK (0x10U) -#define PMC_RESETCAUSE_WDTRESET_SHIFT (4U) -#define PMC_RESETCAUSE_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_WDTRESET_SHIFT)) & PMC_RESETCAUSE_WDTRESET_MASK) -#define PMC_RESETCAUSE_SWRRESET_MASK (0x20U) -#define PMC_RESETCAUSE_SWRRESET_SHIFT (5U) -#define PMC_RESETCAUSE_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SWRRESET_SHIFT)) & PMC_RESETCAUSE_SWRRESET_MASK) -#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK (0x40U) -#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT (6U) -#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT)) & PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK) -#define PMC_RESETCAUSE_DPDRESET_RTC_MASK (0x80U) -#define PMC_RESETCAUSE_DPDRESET_RTC_SHIFT (7U) -#define PMC_RESETCAUSE_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_RTC_SHIFT)) & PMC_RESETCAUSE_DPDRESET_RTC_MASK) -#define PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK (0x100U) -#define PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT (8U) -#define PMC_RESETCAUSE_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT)) & PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK) -/*! @} */ - -/*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */ -/*! @{ */ -#define PMC_BODVBAT_TRIGLVL_MASK (0x1FU) -#define PMC_BODVBAT_TRIGLVL_SHIFT (0U) -/*! TRIGLVL - BoD trigger level. - * 0b00000..1.00 V. - * 0b00001..1.10 V. - * 0b00010..1.20 V. - * 0b00011..1.30 V. - * 0b00100..1.40 V. - * 0b00101..1.50 V. - * 0b00110..1.60 V. - * 0b00111..1.65 V. - * 0b01000..1.70 V. - * 0b01001..1.75 V. - * 0b01010..1.80 V. - * 0b01011..1.90 V. - * 0b01100..2.00 V. - * 0b01101..2.10 V. - * 0b01110..2.20 V. - * 0b01111..2.30 V. - * 0b10000..2.40 V. - * 0b10001..2.50 V. - * 0b10010..2.60 V. - * 0b10011..2.70 V. - * 0b10100..2.806 V. - * 0b10101..2.90 V. - * 0b10110..3.00 V. - * 0b10111..3.10 V. - * 0b11000..3.20 V. - * 0b11001..3.30 V. - * 0b11010..3.30 V. - * 0b11011..3.30 V. - * 0b11100..3.30 V. - * 0b11101..3.30 V. - * 0b11110..3.30 V. - * 0b11111..3.30 V. - */ -#define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK) -#define PMC_BODVBAT_HYST_MASK (0x60U) -#define PMC_BODVBAT_HYST_SHIFT (5U) -/*! HYST - BoD Hysteresis control. - * 0b00..25 mV. - * 0b01..50 mV. - * 0b10..75 mV. - * 0b11..100 mV. - */ -#define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK) -/*! @} */ - -/*! @name BODCORE - Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ -#define PMC_BODCORE_TRIGLVL_MASK (0x7U) -#define PMC_BODCORE_TRIGLVL_SHIFT (0U) -/*! TRIGLVL - BoD trigger level. - * 0b000..0.60 V. - * 0b001..0.65 V. - * 0b010..0.70 V. - * 0b011..0.75 V. - * 0b100..0.80 V. - * 0b101..0.85 V. - * 0b110..0.90 V. - * 0b111..0.95 V. - */ -#define PMC_BODCORE_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_TRIGLVL_SHIFT)) & PMC_BODCORE_TRIGLVL_MASK) -#define PMC_BODCORE_HYST_MASK (0x30U) -#define PMC_BODCORE_HYST_SHIFT (4U) -/*! HYST - BoD Core Hysteresis control. - * 0b00..25 mV. - * 0b01..50 mV. - * 0b10..75 mV. - * 0b11..100 mV. - */ -#define PMC_BODCORE_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_HYST_SHIFT)) & PMC_BODCORE_HYST_MASK) -/*! @} */ - -/*! @name FRO1M - 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ -#define PMC_FRO1M_FREQSEL_MASK (0x7FU) -#define PMC_FRO1M_FREQSEL_SHIFT (0U) -#define PMC_FRO1M_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_FREQSEL_SHIFT)) & PMC_FRO1M_FREQSEL_MASK) -#define PMC_FRO1M_ATBCTRL_MASK (0x180U) -#define PMC_FRO1M_ATBCTRL_SHIFT (7U) -#define PMC_FRO1M_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_ATBCTRL_SHIFT)) & PMC_FRO1M_ATBCTRL_MASK) -#define PMC_FRO1M_DIVSEL_MASK (0x3E00U) -#define PMC_FRO1M_DIVSEL_SHIFT (9U) -/*! DIVSEL - Divider selection bits. - * 0b00000..2.0. - * 0b00001..4.0. - * 0b00010..6.0. - * 0b00011..8.0. - * 0b00100..10.0. - * 0b00101..12.0. - * 0b00110..14.0. - * 0b00111..16.0. - * 0b01000..18.0. - * 0b01001..20.0. - * 0b01010..22.0. - * 0b01011..24.0. - * 0b01100..26.0. - * 0b01101..28.0. - * 0b01110..30.0. - * 0b01111..32.0. - * 0b10000..34.0. - * 0b10001..36.0. - * 0b10010..38.0. - * 0b10011..40.0. - * 0b10100..42.0. - * 0b10101..44.0. - * 0b10110..46.0. - * 0b10111..48.0. - * 0b11000..50.0. - * 0b11001..52.0. - * 0b11010..54.0. - * 0b11011..56.0. - * 0b11100..58.0. - * 0b11101..60.0. - * 0b11110..62.0. - * 0b11111..1.0. - */ -#define PMC_FRO1M_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_DIVSEL_SHIFT)) & PMC_FRO1M_DIVSEL_MASK) -/*! @} */ - -/*! @name FRO32K - 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ -#define PMC_FRO32K_NTAT_MASK (0xEU) -#define PMC_FRO32K_NTAT_SHIFT (1U) -#define PMC_FRO32K_NTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_NTAT_SHIFT)) & PMC_FRO32K_NTAT_MASK) -#define PMC_FRO32K_PTAT_MASK (0x70U) -#define PMC_FRO32K_PTAT_SHIFT (4U) -#define PMC_FRO32K_PTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_PTAT_SHIFT)) & PMC_FRO32K_PTAT_MASK) -#define PMC_FRO32K_CAPCAL_MASK (0xFF80U) -#define PMC_FRO32K_CAPCAL_SHIFT (7U) -#define PMC_FRO32K_CAPCAL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_CAPCAL_SHIFT)) & PMC_FRO32K_CAPCAL_MASK) -#define PMC_FRO32K_ATBCTRL_MASK (0x30000U) -#define PMC_FRO32K_ATBCTRL_SHIFT (16U) -#define PMC_FRO32K_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_ATBCTRL_SHIFT)) & PMC_FRO32K_ATBCTRL_MASK) -/*! @} */ - -/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ -#define PMC_XTAL32K_IREF_MASK (0x6U) -#define PMC_XTAL32K_IREF_SHIFT (1U) -#define PMC_XTAL32K_IREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK) -#define PMC_XTAL32K_TEST_MASK (0x8U) -#define PMC_XTAL32K_TEST_SHIFT (3U) -#define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK) -#define PMC_XTAL32K_IBIAS_MASK (0x30U) -#define PMC_XTAL32K_IBIAS_SHIFT (4U) -#define PMC_XTAL32K_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK) -#define PMC_XTAL32K_AMPL_MASK (0xC0U) -#define PMC_XTAL32K_AMPL_SHIFT (6U) -#define PMC_XTAL32K_AMPL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK) -#define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U) -#define PMC_XTAL32K_CAPBANKIN_SHIFT (8U) -#define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK) -#define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U) -#define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U) -#define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK) -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK (0x400000U) -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT (22U) -/*! CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set. - * 0b0..Sourced from CAPTESTSTART. - * 0b1..Sourced from calibration. - */ -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT)) & PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK) -#define PMC_XTAL32K_CAPTESTSTART_MASK (0x800000U) -#define PMC_XTAL32K_CAPTESTSTART_SHIFT (23U) -#define PMC_XTAL32K_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTART_SHIFT)) & PMC_XTAL32K_CAPTESTSTART_MASK) -#define PMC_XTAL32K_CAPTESTENABLE_MASK (0x1000000U) -#define PMC_XTAL32K_CAPTESTENABLE_SHIFT (24U) -#define PMC_XTAL32K_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTENABLE_SHIFT)) & PMC_XTAL32K_CAPTESTENABLE_MASK) -#define PMC_XTAL32K_CAPTESTOSCINSEL_MASK (0x2000000U) -#define PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT (25U) -/*! CAPTESTOSCINSEL - Select the input for test. - * 0b0..Oscillator output pin (osc_out). - * 0b1..Oscillator input pin (osc_in). - */ -#define PMC_XTAL32K_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT)) & PMC_XTAL32K_CAPTESTOSCINSEL_MASK) -/*! @} */ - -/*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ -#define PMC_COMP_HYST_MASK (0x2U) -#define PMC_COMP_HYST_SHIFT (1U) -/*! HYST - Hysteris when hyst = '1'. - * 0b0..Hysteresis is disable. - * 0b1..Hysteresis is enable. - */ -#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) -#define PMC_COMP_VREFINPUT_MASK (0x4U) -#define PMC_COMP_VREFINPUT_SHIFT (2U) -/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). - * 0b0..Select internal VREF. - * 0b1..Select VDDA. - */ -#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) -#define PMC_COMP_LOWPOWER_MASK (0x8U) -#define PMC_COMP_LOWPOWER_SHIFT (3U) -/*! LOWPOWER - Low power mode. - * 0b0..High speed mode. - * 0b1..Low power mode (Low speed). - */ -#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) -#define PMC_COMP_PMUX_MASK (0x70U) -#define PMC_COMP_PMUX_SHIFT (4U) -/*! PMUX - Control word for P multiplexer:. - * 0b000..VREF (See fiedl VREFINPUT). - * 0b001..Pin P0_0. - * 0b010..Pin P0_9. - * 0b011..Pin P0_18. - * 0b100..Pin P1_14. - * 0b101..Pin P2_23. - */ -#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) -#define PMC_COMP_NMUX_MASK (0x380U) -#define PMC_COMP_NMUX_SHIFT (7U) -/*! NMUX - Control word for N multiplexer:. - * 0b000..VREF (See field VREFINPUT). - * 0b001..Pin P0_0. - * 0b010..Pin P0_9. - * 0b011..Pin P0_18. - * 0b100..Pin P1_14. - * 0b101..Pin P2_23. - */ -#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) -#define PMC_COMP_VREF_MASK (0x7C00U) -#define PMC_COMP_VREF_SHIFT (10U) -#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) -#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) -#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) -#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) -#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) -#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) -#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) -#define PMC_COMP_PMUXCAPT_MASK (0xE00000U) -#define PMC_COMP_PMUXCAPT_SHIFT (21U) -#define PMC_COMP_PMUXCAPT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUXCAPT_SHIFT)) & PMC_COMP_PMUXCAPT_MASK) -/*! @} */ - -/*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */ -/*! @{ */ -#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) -#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) -/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. - */ -#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) -#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) -#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) -/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. - */ -#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) -#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) -#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) -/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. - */ -#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) -#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) -#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) -/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3. - */ -#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK) -/*! @} */ - -/*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ -#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) -#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) -#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) -#define PMC_STATUSCLK_FRO1MCLKVALID_MASK (0x2U) -#define PMC_STATUSCLK_FRO1MCLKVALID_SHIFT (1U) -#define PMC_STATUSCLK_FRO1MCLKVALID(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_FRO1MCLKVALID_SHIFT)) & PMC_STATUSCLK_FRO1MCLKVALID_MASK) -#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) -#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) -/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. - * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared.. - * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared.. - */ -#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) -/*! @} */ - -/*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ -#define PMC_AOREG1_DATA31_0_MASK (0xFFFFFFFFU) -#define PMC_AOREG1_DATA31_0_SHIFT (0U) -#define PMC_AOREG1_DATA31_0(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DATA31_0_SHIFT)) & PMC_AOREG1_DATA31_0_MASK) -/*! @} */ - -/*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ -#define PMC_RTCOSC32K_SEL_MASK (0x1U) -#define PMC_RTCOSC32K_SEL_SHIFT (0U) -/*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . - * 0b0..FRO 32 KHz. - * 0b1..XTAL 32KHz. - */ -#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) -#define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU) -#define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U) -#define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK) -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U) -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U) -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK) -#define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U) -#define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U) -#define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK) -#define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U) -#define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U) -#define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK) -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U) -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U) -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK) -/*! @} */ - -/*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ -#define PMC_OSTIMER_SOFTRESET_MASK (0x1U) -#define PMC_OSTIMER_SOFTRESET_SHIFT (0U) -#define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK) -#define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U) -#define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U) -#define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK) -#define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U) -#define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U) -#define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK) -#define PMC_OSTIMER_OSC32KPD_MASK (0x8U) -#define PMC_OSTIMER_OSC32KPD_SHIFT (3U) -#define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK) -/*! @} */ - -/*! @name PDSLEEPCFG0 - Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ -/*! @{ */ -#define PMC_PDSLEEPCFG0_PDEN_DCDC_MASK (0x1U) -#define PMC_PDSLEEPCFG0_PDEN_DCDC_SHIFT (0U) -/*! PDEN_DCDC - Controls DCDC power during DEEP SLEEP (DCDC is always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..DCDC is powered on during low power mode.. - * 0b1..DCDC is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_DCDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_DCDC_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_DCDC_MASK) -#define PMC_PDSLEEPCFG0_PDEN_BIAS_MASK (0x2U) -#define PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT (1U) -/*! PDEN_BIAS - Controls Analog Bias power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..Analog Bias is powered on during low power mode.. - * 0b1..Analog Bias is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BIAS_MASK) -#define PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK (0x4U) -#define PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT (2U) -/*! PDEN_BODCORE - Controls Core Logic BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..BOD CORE is powered on during low power mode.. - * 0b1..BOD CORE is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK) -#define PMC_PDSLEEPCFG0_PDEN_BODVBAT_MASK (0x8U) -#define PMC_PDSLEEPCFG0_PDEN_BODVBAT_SHIFT (3U) -/*! PDEN_BODVBAT - Controls VBAT BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..BOD VBAT is powered on during low power mode.. - * 0b1..BOD VBAT is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODVBAT_MASK) -#define PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK (0x10U) -#define PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT (4U) -/*! PDEN_FRO1M - Controls 1 MHz Free Running Oscillator power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - * 0b0..FRO 1MHz is powered on during low power mode.. - * 0b1..FRO 1MHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_FRO1M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK) -#define PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK (0x20U) -#define PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT (5U) -/*! PDEN_FRO192M - Controls 192MHz Free Running Oscillator power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..FRO 192 MHz is powered on during low power mode.. - * 0b1..FRO 192 MHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK) -#define PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK (0x40U) -#define PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT (6U) -/*! PDEN_FRO32K - Controls power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - * 0b0..FRO 32 KHz is powered on during low power mode.. - * 0b1..FRO 32 KHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK) -#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK (0x80U) -#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT (7U) -/*! PDEN_XTAL32K - Controls crystal 32 KHz power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - * 0b0..crystal 32 KHz is powered on during low power mode.. - * 0b1..crystal 32 KHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK) -#define PMC_PDSLEEPCFG0_PDEN_XTAL32M_MASK (0x100U) -#define PMC_PDSLEEPCFG0_PDEN_XTAL32M_SHIFT (8U) -/*! PDEN_XTAL32M - Controls crystal 32 MHz power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..crystal 32 MHz is powered on during low power mode.. - * 0b1..crystal 32 MHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTAL32M_MASK) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_MASK (0x200U) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT (9U) -/*! PDEN_PLL0 - Controls System PLL (also refered as PLL0) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..System PLL (also refered as PLL0) is powered on during low power mode.. - * 0b1..System PLL (also refered as PLL0) is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_MASK) -#define PMC_PDSLEEPCFG0_PDEN_PLL1_MASK (0x400U) -#define PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT (10U) -/*! PDEN_PLL1 - Controls USB PLL (also refered as PLL1) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..USB PLL (also refered as PLL1) is powered on during low power mode.. - * 0b1..USB PLL (also refered as PLL1) is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL1_MASK) -#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK (0x800U) -#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT (11U) -/*! PDEN_USBFSPHY - Controls USB Full Speed phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..USB Full Speed phy is powered on during low power mode.. - * 0b1..USB Full Speed phy is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK) -#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY_MASK (0x1000U) -#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY_SHIFT (12U) -/*! PDEN_USBHSPHY - Controls USB High Speed Phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..USB High Speed Phy is powered on during low power mode.. - * 0b1..USB High Speed Phy is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_USBHSPHY_MASK) -#define PMC_PDSLEEPCFG0_PDEN_COMP_MASK (0x2000U) -#define PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT (13U) -/*! PDEN_COMP - Controls Analog Comparator power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..Analog Comparator is powered on during low power mode.. - * 0b1..Analog Comparator is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_COMP_MASK) -#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS_MASK (0x4000U) -#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS_SHIFT (14U) -/*! PDEN_TEMPSENS - Controls Temperature Sensor power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..Temperature Sensor is powered on during low power mode.. - * 0b1..Temperature Sensor is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_TEMPSENS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_TEMPSENS_MASK) -#define PMC_PDSLEEPCFG0_PDEN_GPADC_MASK (0x8000U) -#define PMC_PDSLEEPCFG0_PDEN_GPADC_SHIFT (15U) -/*! PDEN_GPADC - Controls General Purpose ADC (GPADC) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..General Purpose ADC (GPADC) is powered on during low power mode.. - * 0b1..General Purpose ADC (GPADC) is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_GPADC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_GPADC_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_GPADC_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK (0x10000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT (16U) -/*! PDEN_LDOMEM - Controls Memories LDO power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - * 0b0..Memories LDO is powered on during low power mode.. - * 0b1..Memories LDO is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_MASK (0x20000U) -#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_SHIFT (17U) -/*! PDEN_LDODEEPSLEEP - Controls Deep Sleep LDO power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..Deep Sleep LDO is powered on during low power mode.. - * 0b1..Deep Sleep LDO is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_MASK (0x40000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_SHIFT (18U) -/*! PDEN_LDOUSBHS - Controls USB high speed LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..USB high speed LDO is powered on during low power mode.. - * 0b1..USB high speed LDO is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_MASK) -#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS_MASK (0x80000U) -#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS_SHIFT (19U) -/*! PDEN_AUXBIAS - during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..is powered on during low power mode.. - * 0b1..is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_AUXBIAS_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M_MASK (0x100000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M_SHIFT (20U) -/*! PDEN_LDOXO32M - Controls crystal 32 MHz LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..crystal 32 MHz LDO is powered on during low power mode.. - * 0b1..crystal 32 MHz LDO is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOXO32M_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK (0x200000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT (21U) -/*! PDEN_LDOFLASHNV - Controls Flash NV (high voltage) LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..Flash NV (high voltage) is powered on during low power mode.. - * 0b1..Flash NV (high voltage) is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK) -#define PMC_PDSLEEPCFG0_PDEN_RNG_MASK (0x400000U) -#define PMC_PDSLEEPCFG0_PDEN_RNG_SHIFT (22U) -/*! PDEN_RNG - Controls True Random Number Genetaor (TRNG) clock sources power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..True Random Number Genetaor (TRNG) clock sources are powered on during low power mode.. - * 0b1..True Random Number Genetaor (TRNG) clock sources are powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_RNG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_RNG_MASK) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT (23U) -/*! PDEN_PLL0_SSCG - Controls PLL0 Spread Sprectrum module power during DEEP SLEEP (PLL0 Spread Spectrum is always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..PLL0 Spread Sprectrum module is powered on during low power mode.. - * 0b1..PLL0 Spread Sprectrum module is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK) -#define PMC_PDSLEEPCFG0_PDEN_ROM_MASK (0x1000000U) -#define PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT (24U) -/*! PDEN_ROM - Controls ROM power during DEEP SLEEP (ROM is always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..ROM is powered on during low power mode.. - * 0b1..ROM is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_ROM_MASK) -/*! @} */ - -/*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ -#define PMC_PDRUNCFG0_PDEN_DCDC_MASK (0x1U) -#define PMC_PDRUNCFG0_PDEN_DCDC_SHIFT (0U) -/*! PDEN_DCDC - Controls power to Bulk DCDC Converter. - * 0b0..DCDC is powered. - * 0b1..DCDC is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_DCDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_DCDC_SHIFT)) & PMC_PDRUNCFG0_PDEN_DCDC_MASK) -#define PMC_PDRUNCFG0_PDEN_BIAS_MASK (0x2U) -#define PMC_PDRUNCFG0_PDEN_BIAS_SHIFT (1U) -/*! PDEN_BIAS - Controls power to . - * 0b0..Analog Bias is powered. - * 0b1..Analog Bias is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_BIAS_MASK) -#define PMC_PDRUNCFG0_PDEN_BODCORE_MASK (0x4U) -#define PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT (2U) -/*! PDEN_BODCORE - Controls power to Core Brown Out Detector (BOD). - * 0b0..BOD CORE is powered. - * 0b1..BOD CORE is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODCORE_MASK) -#define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U) -#define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U) -/*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). - * 0b0..BOD VBAT is powered. - * 0b1..BOD VBAT is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK) -#define PMC_PDRUNCFG0_PDEN_FRO192M_MASK (0x20U) -#define PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT (5U) -/*! PDEN_FRO192M - Controls power to the Free Running Oscillator (FRO) 192 MHz; The 12MHz, 48 MHz and 96 MHz clocks are derived from this FRO. - * 0b0..FRO 192MHz is powered. - * 0b1..FRO 192MHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) -#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) -#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) -/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. - * 0b0..FRO32KHz is powered. - * 0b1..FRO32KHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) -#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) -#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) -/*! PDEN_XTAL32K - Controls power to crystal 32 KHz. - * 0b0..Crystal 32KHz is powered. - * 0b1..Crystal 32KHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) -#define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U) -#define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U) -/*! PDEN_XTAL32M - Controls power to crystal 32 MHz. - * 0b0..Crystal 32MHz is powered. - * 0b1..Crystal 32MHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK) -#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) -#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) -/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). - * 0b0..PLL0 is powered. - * 0b1..PLL0 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) -#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) -#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) -/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). - * 0b0..PLL1 is powered. - * 0b1..PLL1 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) -#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) -#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) -/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. - * 0b0..USB Full Speed phy is powered. - * 0b1..USB Full Speed phy is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) -#define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U) -#define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U) -/*! PDEN_USBHSPHY - Controls power to USB High Speed Phy. - * 0b0..USB HS phy is powered. - * 0b1..USB HS phy is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK) -#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) -#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) -/*! PDEN_COMP - Controls power to Analog Comparator. - * 0b0..Analog Comparator is powered. - * 0b1..Analog Comparator is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) -#define PMC_PDRUNCFG0_PDEN_TEMPSENS_MASK (0x4000U) -#define PMC_PDRUNCFG0_PDEN_TEMPSENS_SHIFT (14U) -/*! PDEN_TEMPSENS - Controls power to Temperature Sensor. - * 0b0..Temperature Sensor is powered. - * 0b1..Temperature Sensor is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_TEMPSENS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_TEMPSENS_SHIFT)) & PMC_PDRUNCFG0_PDEN_TEMPSENS_MASK) -#define PMC_PDRUNCFG0_PDEN_GPADC_MASK (0x8000U) -#define PMC_PDRUNCFG0_PDEN_GPADC_SHIFT (15U) -/*! PDEN_GPADC - Controls power to General Purpose ADC (GPADC). - * 0b0..GPADC is powered. - * 0b1..GPADC is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_GPADC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_GPADC_SHIFT)) & PMC_PDRUNCFG0_PDEN_GPADC_MASK) -#define PMC_PDRUNCFG0_PDEN_LDOMEM_MASK (0x10000U) -#define PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT (16U) -/*! PDEN_LDOMEM - Controls power to Memories LDO. - * 0b0..Memories LDO is powered. - * 0b1..Memories LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOMEM_MASK) -#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_MASK (0x20000U) -#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_SHIFT (17U) -/*! PDEN_LDODEEPSLEEP - Controls power to Deep Sleep LDO. - * 0b0..Deep Sleep LDO is powered. - * 0b1..Deep Sleep LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_MASK) -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U) -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U) -/*! PDEN_LDOUSBHS - Controls power to USB high speed LDO. - * 0b0..USB high speed LDO is powered. - * 0b1..USB high speed LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK) -#define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U) -#define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U) -/*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) - * 0b0..auxiliary biasing is powered. - * 0b1..auxiliary biasing is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK) -#define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U) -#define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U) -/*! PDEN_LDOXO32M - Controls power to crystal 32 MHz LDO. - * 0b0..crystal 32 MHz LDO is powered. - * 0b1..crystal 32 MHz LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK) -#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK (0x200000U) -#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT (21U) -/*! PDEN_LDOFLASHNV - Controls power to Flasn NV (high voltage) LDO. - * 0b0..Flash NV LDO is powered. - * 0b1..Flash NV LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK) -#define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U) -#define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U) -/*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. - * 0b0..TRNG clocks are powered. - * 0b1..TRNG clocks are powered down. - */ -#define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK) -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) -/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. - * 0b0..PLL0 Sread spectrum module is powered. - * 0b1..PLL0 Sread spectrum module is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) -/*! @} */ - -/*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) -/*! @} */ - -/*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PMC_Register_Masks */ - - -/* PMC - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral PMC base address */ - #define PMC_BASE (0x50020000u) - /** Peripheral PMC base address */ - #define PMC_BASE_NS (0x40020000u) - /** Peripheral PMC base pointer */ - #define PMC ((PMC_Type *)PMC_BASE) - /** Peripheral PMC base pointer */ - #define PMC_NS ((PMC_Type *)PMC_BASE_NS) - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS { PMC_BASE } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS { PMC } - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS_NS { PMC_NS } -#else - /** Peripheral PMC base address */ - #define PMC_BASE (0x40020000u) - /** Peripheral PMC base pointer */ - #define PMC ((PMC_Type *)PMC_BASE) - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS { PMC_BASE } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS { PMC } -#endif - -/*! - * @} - */ /* end of group PMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- POWERQUAD Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer - * @{ - */ - -/** POWERQUAD - Register Layout Typedef */ -typedef struct { - __IO uint32_t OUTBASE; /**< Base address register for output region, offset: 0x0 */ - __IO uint32_t OUTFORMAT; /**< Output format, offset: 0x4 */ - __IO uint32_t TMPBASE; /**< Base address register for temp region, offset: 0x8 */ - __IO uint32_t TMPFORMAT; /**< Temp format, offset: 0xC */ - __IO uint32_t INABASE; /**< Base address register for input A region, offset: 0x10 */ - __IO uint32_t INAFORMAT; /**< Input A format, offset: 0x14 */ - __IO uint32_t INBBASE; /**< Base address register for input B region, offset: 0x18 */ - __IO uint32_t INBFORMAT; /**< Input B format, offset: 0x1C */ - uint8_t RESERVED_0[224]; - __IO uint32_t CONTROL; /**< PowerQuad Control register, offset: 0x100 */ - __IO uint32_t LENGTH; /**< Length register, offset: 0x104 */ - __IO uint32_t CPPRE; /**< Pre-scale register, offset: 0x108 */ - __IO uint32_t MISC; /**< Misc register, offset: 0x10C */ - __IO uint32_t CURSORY; /**< Cursory register, offset: 0x110 */ - uint8_t RESERVED_1[108]; - __IO uint32_t CORDIC_X; /**< Cordic input X register, offset: 0x180 */ - __IO uint32_t CORDIC_Y; /**< Cordic input Y register, offset: 0x184 */ - __IO uint32_t CORDIC_Z; /**< Cordic input Z register, offset: 0x188 */ - __IO uint32_t ERRSTAT; /**< Read/Write register where error statuses are captured (sticky), offset: 0x18C */ - __IO uint32_t INTREN; /**< INTERRUPT enable register, offset: 0x190 */ - __IO uint32_t EVENTEN; /**< Event Enable register, offset: 0x194 */ - __IO uint32_t INTRSTAT; /**< INTERRUPT STATUS register, offset: 0x198 */ - uint8_t RESERVED_2[100]; - __IO uint32_t GPREG[16]; /**< General purpose register bank N., array offset: 0x200, array step: 0x4 */ - __IO uint32_t COMPREG[8]; /**< Compute register bank, array offset: 0x240, array step: 0x4 */ -} POWERQUAD_Type; - -/* ---------------------------------------------------------------------------- - -- POWERQUAD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks - * @{ - */ - -/*! @name OUTBASE - Base address register for output region */ -/*! @{ */ -#define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U) -#define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK) -/*! @} */ - -/*! @name OUTFORMAT - Output format */ -/*! @{ */ -#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U) -#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U) -#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK) -#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U) -#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U) -#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK) -#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U) -#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U) -#define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK) -/*! @} */ - -/*! @name TMPBASE - Base address register for temp region */ -/*! @{ */ -#define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U) -#define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK) -/*! @} */ - -/*! @name TMPFORMAT - Temp format */ -/*! @{ */ -#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U) -#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U) -#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK) -#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U) -#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U) -#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK) -#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U) -#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U) -#define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK) -/*! @} */ - -/*! @name INABASE - Base address register for input A region */ -/*! @{ */ -#define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_INABASE_INABASE_SHIFT (0U) -#define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK) -/*! @} */ - -/*! @name INAFORMAT - Input A format */ -/*! @{ */ -#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U) -#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U) -#define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK) -#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U) -#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U) -#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK) -#define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U) -#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U) -#define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK) -/*! @} */ - -/*! @name INBBASE - Base address register for input B region */ -/*! @{ */ -#define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_INBBASE_INBBASE_SHIFT (0U) -#define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK) -/*! @} */ - -/*! @name INBFORMAT - Input B format */ -/*! @{ */ -#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U) -#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U) -#define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK) -#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U) -#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U) -#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK) -#define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U) -#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U) -#define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK) -/*! @} */ - -/*! @name CONTROL - PowerQuad Control register */ -/*! @{ */ -#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU) -#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U) -#define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK) -#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U) -#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U) -#define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK) -#define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U) -#define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U) -#define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK) -/*! @} */ - -/*! @name LENGTH - Length register */ -/*! @{ */ -#define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU) -#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U) -#define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK) -/*! @} */ - -/*! @name CPPRE - Pre-scale register */ -/*! @{ */ -#define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU) -#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U) -#define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK) -#define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U) -#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U) -#define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK) -#define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U) -#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U) -#define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK) -#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U) -#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U) -#define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK) -/*! @} */ - -/*! @name MISC - Misc register */ -/*! @{ */ -#define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU) -#define POWERQUAD_MISC_INST_MISC_SHIFT (0U) -#define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK) -/*! @} */ - -/*! @name CURSORY - Cursory register */ -/*! @{ */ -#define POWERQUAD_CURSORY_CURSORY_MASK (0x1U) -#define POWERQUAD_CURSORY_CURSORY_SHIFT (0U) -#define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK) -/*! @} */ - -/*! @name CORDIC_X - Cordic input X register */ -/*! @{ */ -#define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU) -#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U) -#define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK) -/*! @} */ - -/*! @name CORDIC_Y - Cordic input Y register */ -/*! @{ */ -#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU) -#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U) -#define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK) -/*! @} */ - -/*! @name CORDIC_Z - Cordic input Z register */ -/*! @{ */ -#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU) -#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U) -#define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK) -/*! @} */ - -/*! @name ERRSTAT - Read/Write register where error statuses are captured (sticky) */ -/*! @{ */ -#define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U) -#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U) -#define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK) -#define POWERQUAD_ERRSTAT_NAN_MASK (0x2U) -#define POWERQUAD_ERRSTAT_NAN_SHIFT (1U) -#define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK) -#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U) -#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U) -#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK) -#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U) -#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U) -#define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK) -#define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U) -#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U) -#define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK) -/*! @} */ - -/*! @name INTREN - INTERRUPT enable register */ -/*! @{ */ -#define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U) -#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U) -#define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK) -#define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U) -#define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U) -#define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK) -#define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U) -#define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U) -#define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK) -#define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U) -#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U) -#define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK) -#define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U) -#define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U) -#define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK) -#define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U) -#define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U) -#define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK) -/*! @} */ - -/*! @name EVENTEN - Event Enable register */ -/*! @{ */ -#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U) -#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U) -#define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK) -#define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U) -#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U) -#define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK) -#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U) -#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U) -#define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK) -#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U) -#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U) -#define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK) -#define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U) -#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U) -#define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK) -#define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U) -#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U) -#define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK) -/*! @} */ - -/*! @name INTRSTAT - INTERRUPT STATUS register */ -/*! @{ */ -#define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U) -#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U) -#define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK) -/*! @} */ - -/*! @name GPREG - General purpose register bank N. */ -/*! @{ */ -#define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU) -#define POWERQUAD_GPREG_GPREG_SHIFT (0U) -#define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK) -/*! @} */ - -/* The count of POWERQUAD_GPREG */ -#define POWERQUAD_GPREG_COUNT (16U) - -/*! @name COMPREGS_COMPREG - Compute register bank */ -/*! @{ */ -#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU) -#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U) -#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK) -/*! @} */ - -/* The count of POWERQUAD_COMPREGS_COMPREG */ -#define POWERQUAD_COMPREGS_COMPREG_COUNT (8U) - - -/*! - * @} - */ /* end of group POWERQUAD_Register_Masks */ - - -/* POWERQUAD - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral POWERQUAD base address */ - #define POWERQUAD_BASE (0x500A6000u) - /** Peripheral POWERQUAD base address */ - #define POWERQUAD_BASE_NS (0x400A6000u) - /** Peripheral POWERQUAD base pointer */ - #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) - /** Peripheral POWERQUAD base pointer */ - #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) - /** Array initializer of POWERQUAD peripheral base addresses */ - #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } - /** Array initializer of POWERQUAD peripheral base pointers */ - #define POWERQUAD_BASE_PTRS { POWERQUAD } - /** Array initializer of POWERQUAD peripheral base addresses */ - #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } - /** Array initializer of POWERQUAD peripheral base pointers */ - #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } -#else - /** Peripheral POWERQUAD base address */ - #define POWERQUAD_BASE (0x400A6000u) - /** Peripheral POWERQUAD base pointer */ - #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) - /** Array initializer of POWERQUAD peripheral base addresses */ - #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } - /** Array initializer of POWERQUAD peripheral base pointers */ - #define POWERQUAD_BASE_PTRS { POWERQUAD } -#endif - -/*! - * @} - */ /* end of group POWERQUAD_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PRINCE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer - * @{ - */ - -/** PRINCE - Register Layout Typedef */ -typedef struct { - __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */ - __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */ - __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */ - __IO uint32_t LOCK; /**< Lock register, offset: 0xC */ - __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */ - __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */ - __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */ - __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */ - __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */ - __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */ - __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */ - __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */ - __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */ - __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */ - __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */ - __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */ -} PRINCE_Type; - -/* ---------------------------------------------------------------------------- - -- PRINCE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PRINCE_Register_Masks PRINCE Register Masks - * @{ - */ - -/*! @name ENC_ENABLE - Encryption Enable register */ -/*! @{ */ -#define PRINCE_ENC_ENABLE_EN_MASK (0x1U) -#define PRINCE_ENC_ENABLE_EN_SHIFT (0U) -/*! EN - Encryption Enable. - * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled.. - * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled.. - */ -#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) -/*! @} */ - -/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ -/*! @{ */ -#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) -#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) -#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) -/*! @} */ - -/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ -/*! @{ */ -#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) -#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) -#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) -/*! @} */ - -/*! @name LOCK - Lock register */ -/*! @{ */ -#define PRINCE_LOCK_LOCKREG0_MASK (0x1U) -#define PRINCE_LOCK_LOCKREG0_SHIFT (0U) -/*! LOCKREG0 - Lock Region 0 registers. - * 0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. - * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) -#define PRINCE_LOCK_LOCKREG1_MASK (0x2U) -#define PRINCE_LOCK_LOCKREG1_SHIFT (1U) -/*! LOCKREG1 - Lock Region 1 registers. - * 0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. - * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) -#define PRINCE_LOCK_LOCKREG2_MASK (0x4U) -#define PRINCE_LOCK_LOCKREG2_SHIFT (2U) -/*! LOCKREG2 - Lock Region 2 registers. - * 0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. - * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) -#define PRINCE_LOCK_LOCKMASK_MASK (0x100U) -#define PRINCE_LOCK_LOCKMASK_SHIFT (8U) -/*! LOCKMASK - Lock the Mask registers. - * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable.. - * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable.. - */ -#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK) -/*! @} */ - -/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ -/*! @{ */ -#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) -#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ -/*! @{ */ -#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) -#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR0 - Base Address for region 0 register */ -/*! @{ */ -#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) -#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) -#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) -#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ -/*! @{ */ -#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE0_EN_SHIFT (0U) -#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) -/*! @} */ - -/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ -/*! @{ */ -#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) -#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ -/*! @{ */ -#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) -#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR1 - Base Address for region 1 register */ -/*! @{ */ -#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) -#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) -#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) -#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ -/*! @{ */ -#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE1_EN_SHIFT (0U) -#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) -/*! @} */ - -/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ -/*! @{ */ -#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) -#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ -/*! @{ */ -#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) -#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR2 - Base Address for region 2 register */ -/*! @{ */ -#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) -#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) -#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) -#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ -/*! @{ */ -#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE2_EN_SHIFT (0U) -#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PRINCE_Register_Masks */ - - -/* PRINCE - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral PRINCE base address */ - #define PRINCE_BASE (0x50035000u) - /** Peripheral PRINCE base address */ - #define PRINCE_BASE_NS (0x40035000u) - /** Peripheral PRINCE base pointer */ - #define PRINCE ((PRINCE_Type *)PRINCE_BASE) - /** Peripheral PRINCE base pointer */ - #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS) - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS { PRINCE_BASE } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS { PRINCE } - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS_NS { PRINCE_NS } -#else - /** Peripheral PRINCE base address */ - #define PRINCE_BASE (0x40035000u) - /** Peripheral PRINCE base pointer */ - #define PRINCE ((PRINCE_Type *)PRINCE_BASE) - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS { PRINCE_BASE } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS { PRINCE } -#endif - -/*! - * @} - */ /* end of group PRINCE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PUF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer - * @{ - */ - -/** PUF - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */ - __IO uint32_t KEYINDEX; /**< PUF Key Index register, offset: 0x4 */ - __IO uint32_t KEYSIZE; /**< PUF Key Size register, offset: 0x8 */ - uint8_t RESERVED_0[20]; - __I uint32_t STAT; /**< PUF Status register, offset: 0x20 */ - uint8_t RESERVED_1[4]; - __I uint32_t ALLOW; /**< PUF Allow register, offset: 0x28 */ - uint8_t RESERVED_2[20]; - __O uint32_t KEYINPUT; /**< PUF Key Input register, offset: 0x40 */ - __O uint32_t CODEINPUT; /**< PUF Code Input register, offset: 0x44 */ - __I uint32_t CODEOUTPUT; /**< PUF Code Output register, offset: 0x48 */ - uint8_t RESERVED_3[20]; - __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index register, offset: 0x60 */ - __I uint32_t KEYOUTPUT; /**< PUF Key Output register, offset: 0x64 */ - uint8_t RESERVED_4[116]; - __IO uint32_t IFSTAT; /**< PUF Interface Status and clear register, offset: 0xDC */ - uint8_t RESERVED_5[28]; - __I uint32_t VERSION; /**< PUF version register., offset: 0xFC */ - __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */ - __IO uint32_t INTSTAT; /**< PUF interrupt status, offset: 0x104 */ - __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ - __IO uint32_t CFG; /**< PUF config register for block bits, offset: 0x10C */ - uint8_t RESERVED_6[240]; - __IO uint32_t KEYLOCK; /**< Only reset in case of full IC reset, offset: 0x200 */ - __IO uint32_t KEYENABLE; /**< , offset: 0x204 */ - __O uint32_t KEYRESET; /**< Reinitialize Keys shift registers counters, offset: 0x208 */ - __IO uint32_t IDXBLK_L; /**< , offset: 0x20C */ - __IO uint32_t IDXBLK_H_DP; /**< , offset: 0x210 */ - __O uint32_t KEYMASK[4]; /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */ - uint8_t RESERVED_7[48]; - __IO uint32_t IDXBLK_H; /**< , offset: 0x254 */ - __IO uint32_t IDXBLK_L_DP; /**< , offset: 0x258 */ - __I uint32_t SHIFT_STATUS; /**< , offset: 0x25C */ -} PUF_Type; - -/* ---------------------------------------------------------------------------- - -- PUF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_Register_Masks PUF Register Masks - * @{ - */ - -/*! @name CTRL - PUF Control register */ -/*! @{ */ -#define PUF_CTRL_ZEROIZE_MASK (0x1U) -#define PUF_CTRL_ZEROIZE_SHIFT (0U) -#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) -#define PUF_CTRL_ENROLL_MASK (0x2U) -#define PUF_CTRL_ENROLL_SHIFT (1U) -#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) -#define PUF_CTRL_START_MASK (0x4U) -#define PUF_CTRL_START_SHIFT (2U) -#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) -#define PUF_CTRL_GENERATEKEY_MASK (0x8U) -#define PUF_CTRL_GENERATEKEY_SHIFT (3U) -#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) -#define PUF_CTRL_SETKEY_MASK (0x10U) -#define PUF_CTRL_SETKEY_SHIFT (4U) -#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) -#define PUF_CTRL_GETKEY_MASK (0x40U) -#define PUF_CTRL_GETKEY_SHIFT (6U) -#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) -/*! @} */ - -/*! @name KEYINDEX - PUF Key Index register */ -/*! @{ */ -#define PUF_KEYINDEX_KEYIDX_MASK (0xFU) -#define PUF_KEYINDEX_KEYIDX_SHIFT (0U) -#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) -/*! @} */ - -/*! @name KEYSIZE - PUF Key Size register */ -/*! @{ */ -#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) -#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U) -#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) -/*! @} */ - -/*! @name STAT - PUF Status register */ -/*! @{ */ -#define PUF_STAT_BUSY_MASK (0x1U) -#define PUF_STAT_BUSY_SHIFT (0U) -#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) -#define PUF_STAT_SUCCESS_MASK (0x2U) -#define PUF_STAT_SUCCESS_SHIFT (1U) -#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) -#define PUF_STAT_ERROR_MASK (0x4U) -#define PUF_STAT_ERROR_SHIFT (2U) -#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) -#define PUF_STAT_KEYINREQ_MASK (0x10U) -#define PUF_STAT_KEYINREQ_SHIFT (4U) -#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) -#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U) -#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U) -#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) -#define PUF_STAT_CODEINREQ_MASK (0x40U) -#define PUF_STAT_CODEINREQ_SHIFT (6U) -#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) -#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U) -#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U) -#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) -/*! @} */ - -/*! @name ALLOW - PUF Allow register */ -/*! @{ */ -#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U) -#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U) -#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) -#define PUF_ALLOW_ALLOWSTART_MASK (0x2U) -#define PUF_ALLOW_ALLOWSTART_SHIFT (1U) -#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) -#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) -#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) -#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) -#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) -#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) -#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) -/*! @} */ - -/*! @name KEYINPUT - PUF Key Input register */ -/*! @{ */ -#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) -#define PUF_KEYINPUT_KEYIN_SHIFT (0U) -#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) -/*! @} */ - -/*! @name CODEINPUT - PUF Code Input register */ -/*! @{ */ -#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) -#define PUF_CODEINPUT_CODEIN_SHIFT (0U) -#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) -/*! @} */ - -/*! @name CODEOUTPUT - PUF Code Output register */ -/*! @{ */ -#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) -#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) -#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) -/*! @} */ - -/*! @name KEYOUTINDEX - PUF Key Output Index register */ -/*! @{ */ -#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU) -#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) -#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) -/*! @} */ - -/*! @name KEYOUTPUT - PUF Key Output register */ -/*! @{ */ -#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) -#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) -#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) -/*! @} */ - -/*! @name IFSTAT - PUF Interface Status and clear register */ -/*! @{ */ -#define PUF_IFSTAT_ERROR_MASK (0x1U) -#define PUF_IFSTAT_ERROR_SHIFT (0U) -#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) -/*! @} */ - -/*! @name VERSION - PUF version register. */ -/*! @{ */ -#define PUF_VERSION_KEYOUT_MASK (0xFFFFFFFFU) -#define PUF_VERSION_KEYOUT_SHIFT (0U) -#define PUF_VERSION_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_KEYOUT_SHIFT)) & PUF_VERSION_KEYOUT_MASK) -/*! @} */ - -/*! @name INTEN - PUF Interrupt Enable */ -/*! @{ */ -#define PUF_INTEN_READYEN_MASK (0x1U) -#define PUF_INTEN_READYEN_SHIFT (0U) -#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) -#define PUF_INTEN_SUCCESEN_MASK (0x2U) -#define PUF_INTEN_SUCCESEN_SHIFT (1U) -#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK) -#define PUF_INTEN_ERROREN_MASK (0x4U) -#define PUF_INTEN_ERROREN_SHIFT (2U) -#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) -#define PUF_INTEN_KEYINREQEN_MASK (0x10U) -#define PUF_INTEN_KEYINREQEN_SHIFT (4U) -#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) -#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) -#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) -#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) -#define PUF_INTEN_CODEINREQEN_MASK (0x40U) -#define PUF_INTEN_CODEINREQEN_SHIFT (6U) -#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) -#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) -#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) -#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) -/*! @} */ - -/*! @name INTSTAT - PUF interrupt status */ -/*! @{ */ -#define PUF_INTSTAT_READY_MASK (0x1U) -#define PUF_INTSTAT_READY_SHIFT (0U) -#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) -#define PUF_INTSTAT_SUCCESS_MASK (0x2U) -#define PUF_INTSTAT_SUCCESS_SHIFT (1U) -#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) -#define PUF_INTSTAT_ERROR_MASK (0x4U) -#define PUF_INTSTAT_ERROR_SHIFT (2U) -#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) -#define PUF_INTSTAT_KEYINREQ_MASK (0x10U) -#define PUF_INTSTAT_KEYINREQ_SHIFT (4U) -#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) -#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) -#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) -#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) -#define PUF_INTSTAT_CODEINREQ_MASK (0x40U) -#define PUF_INTSTAT_CODEINREQ_SHIFT (6U) -#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) -#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) -#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) -#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) -/*! @} */ - -/*! @name PWRCTRL - PUF RAM Power Control */ -/*! @{ */ -#define PUF_PWRCTRL_RAMON_MASK (0x1U) -#define PUF_PWRCTRL_RAMON_SHIFT (0U) -#define PUF_PWRCTRL_RAMON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK) -#define PUF_PWRCTRL_RAMSTAT_MASK (0x2U) -#define PUF_PWRCTRL_RAMSTAT_SHIFT (1U) -#define PUF_PWRCTRL_RAMSTAT(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK) -/*! @} */ - -/*! @name CFG - PUF config register for block bits */ -/*! @{ */ -#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U) -#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U) -#define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK) -#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U) -#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U) -#define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK) -/*! @} */ - -/*! @name KEYLOCK - Only reset in case of full IC reset */ -/*! @{ */ -#define PUF_KEYLOCK_KEY0_MASK (0x3U) -#define PUF_KEYLOCK_KEY0_SHIFT (0U) -#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK) -#define PUF_KEYLOCK_KEY1_MASK (0xCU) -#define PUF_KEYLOCK_KEY1_SHIFT (2U) -#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK) -#define PUF_KEYLOCK_KEY2_MASK (0x30U) -#define PUF_KEYLOCK_KEY2_SHIFT (4U) -#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK) -#define PUF_KEYLOCK_KEY3_MASK (0xC0U) -#define PUF_KEYLOCK_KEY3_SHIFT (6U) -#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK) -/*! @} */ - -/*! @name KEYENABLE - */ -/*! @{ */ -#define PUF_KEYENABLE_KEY0_MASK (0x3U) -#define PUF_KEYENABLE_KEY0_SHIFT (0U) -#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK) -#define PUF_KEYENABLE_KEY1_MASK (0xCU) -#define PUF_KEYENABLE_KEY1_SHIFT (2U) -#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK) -#define PUF_KEYENABLE_KEY2_MASK (0x30U) -#define PUF_KEYENABLE_KEY2_SHIFT (4U) -#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK) -#define PUF_KEYENABLE_KEY3_MASK (0xC0U) -#define PUF_KEYENABLE_KEY3_SHIFT (6U) -#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK) -/*! @} */ - -/*! @name KEYRESET - Reinitialize Keys shift registers counters */ -/*! @{ */ -#define PUF_KEYRESET_KEY0_MASK (0x3U) -#define PUF_KEYRESET_KEY0_SHIFT (0U) -#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK) -#define PUF_KEYRESET_KEY1_MASK (0xCU) -#define PUF_KEYRESET_KEY1_SHIFT (2U) -#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK) -#define PUF_KEYRESET_KEY2_MASK (0x30U) -#define PUF_KEYRESET_KEY2_SHIFT (4U) -#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK) -#define PUF_KEYRESET_KEY3_MASK (0xC0U) -#define PUF_KEYRESET_KEY3_SHIFT (6U) -#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK) -/*! @} */ - -/*! @name IDXBLK_L - */ -/*! @{ */ -#define PUF_IDXBLK_L_IDX0_MASK (0x3U) -#define PUF_IDXBLK_L_IDX0_SHIFT (0U) -#define PUF_IDXBLK_L_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX0_SHIFT)) & PUF_IDXBLK_L_IDX0_MASK) -#define PUF_IDXBLK_L_IDX1_MASK (0xCU) -#define PUF_IDXBLK_L_IDX1_SHIFT (2U) -#define PUF_IDXBLK_L_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK) -#define PUF_IDXBLK_L_IDX2_MASK (0x30U) -#define PUF_IDXBLK_L_IDX2_SHIFT (4U) -#define PUF_IDXBLK_L_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK) -#define PUF_IDXBLK_L_IDX3_MASK (0xC0U) -#define PUF_IDXBLK_L_IDX3_SHIFT (6U) -#define PUF_IDXBLK_L_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK) -#define PUF_IDXBLK_L_IDX4_MASK (0x300U) -#define PUF_IDXBLK_L_IDX4_SHIFT (8U) -#define PUF_IDXBLK_L_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK) -#define PUF_IDXBLK_L_IDX5_MASK (0xC00U) -#define PUF_IDXBLK_L_IDX5_SHIFT (10U) -#define PUF_IDXBLK_L_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK) -#define PUF_IDXBLK_L_IDX6_MASK (0x3000U) -#define PUF_IDXBLK_L_IDX6_SHIFT (12U) -#define PUF_IDXBLK_L_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK) -#define PUF_IDXBLK_L_IDX7_MASK (0xC000U) -#define PUF_IDXBLK_L_IDX7_SHIFT (14U) -#define PUF_IDXBLK_L_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK) -#define PUF_IDXBLK_L_LOCK_IDX_MASK (0xC0000000U) -#define PUF_IDXBLK_L_LOCK_IDX_SHIFT (30U) -#define PUF_IDXBLK_L_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK) -/*! @} */ - -/*! @name IDXBLK_H_DP - */ -/*! @{ */ -#define PUF_IDXBLK_H_DP_IDX8_MASK (0x3U) -#define PUF_IDXBLK_H_DP_IDX8_SHIFT (0U) -#define PUF_IDXBLK_H_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK) -#define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) -#define PUF_IDXBLK_H_DP_IDX9_SHIFT (2U) -#define PUF_IDXBLK_H_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK) -#define PUF_IDXBLK_H_DP_IDX10_MASK (0x30U) -#define PUF_IDXBLK_H_DP_IDX10_SHIFT (4U) -#define PUF_IDXBLK_H_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK) -#define PUF_IDXBLK_H_DP_IDX11_MASK (0xC0U) -#define PUF_IDXBLK_H_DP_IDX11_SHIFT (6U) -#define PUF_IDXBLK_H_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK) -#define PUF_IDXBLK_H_DP_IDX12_MASK (0x300U) -#define PUF_IDXBLK_H_DP_IDX12_SHIFT (8U) -#define PUF_IDXBLK_H_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK) -#define PUF_IDXBLK_H_DP_IDX13_MASK (0xC00U) -#define PUF_IDXBLK_H_DP_IDX13_SHIFT (10U) -#define PUF_IDXBLK_H_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK) -#define PUF_IDXBLK_H_DP_IDX14_MASK (0x3000U) -#define PUF_IDXBLK_H_DP_IDX14_SHIFT (12U) -#define PUF_IDXBLK_H_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK) -#define PUF_IDXBLK_H_DP_IDX15_MASK (0xC000U) -#define PUF_IDXBLK_H_DP_IDX15_SHIFT (14U) -#define PUF_IDXBLK_H_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK) -/*! @} */ - -/*! @name KEYMASK - Only reset in case of full IC reset */ -/*! @{ */ -#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) -#define PUF_KEYMASK_KEYMASK_SHIFT (0U) -#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK) -/*! @} */ - -/* The count of PUF_KEYMASK */ -#define PUF_KEYMASK_COUNT (4U) - -/*! @name IDXBLK_H - */ -/*! @{ */ -#define PUF_IDXBLK_H_IDX8_MASK (0x3U) -#define PUF_IDXBLK_H_IDX8_SHIFT (0U) -#define PUF_IDXBLK_H_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK) -#define PUF_IDXBLK_H_IDX9_MASK (0xCU) -#define PUF_IDXBLK_H_IDX9_SHIFT (2U) -#define PUF_IDXBLK_H_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK) -#define PUF_IDXBLK_H_IDX10_MASK (0x30U) -#define PUF_IDXBLK_H_IDX10_SHIFT (4U) -#define PUF_IDXBLK_H_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK) -#define PUF_IDXBLK_H_IDX11_MASK (0xC0U) -#define PUF_IDXBLK_H_IDX11_SHIFT (6U) -#define PUF_IDXBLK_H_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK) -#define PUF_IDXBLK_H_IDX12_MASK (0x300U) -#define PUF_IDXBLK_H_IDX12_SHIFT (8U) -#define PUF_IDXBLK_H_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK) -#define PUF_IDXBLK_H_IDX13_MASK (0xC00U) -#define PUF_IDXBLK_H_IDX13_SHIFT (10U) -#define PUF_IDXBLK_H_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK) -#define PUF_IDXBLK_H_IDX14_MASK (0x3000U) -#define PUF_IDXBLK_H_IDX14_SHIFT (12U) -#define PUF_IDXBLK_H_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK) -#define PUF_IDXBLK_H_IDX15_MASK (0xC000U) -#define PUF_IDXBLK_H_IDX15_SHIFT (14U) -#define PUF_IDXBLK_H_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK) -#define PUF_IDXBLK_H_LOCK_IDX_MASK (0xC0000000U) -#define PUF_IDXBLK_H_LOCK_IDX_SHIFT (30U) -#define PUF_IDXBLK_H_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK) -/*! @} */ - -/*! @name IDXBLK_L_DP - */ -/*! @{ */ -#define PUF_IDXBLK_L_DP_IDX0_MASK (0x3U) -#define PUF_IDXBLK_L_DP_IDX0_SHIFT (0U) -#define PUF_IDXBLK_L_DP_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX0_SHIFT)) & PUF_IDXBLK_L_DP_IDX0_MASK) -#define PUF_IDXBLK_L_DP_IDX1_MASK (0xCU) -#define PUF_IDXBLK_L_DP_IDX1_SHIFT (2U) -#define PUF_IDXBLK_L_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK) -#define PUF_IDXBLK_L_DP_IDX2_MASK (0x30U) -#define PUF_IDXBLK_L_DP_IDX2_SHIFT (4U) -#define PUF_IDXBLK_L_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK) -#define PUF_IDXBLK_L_DP_IDX3_MASK (0xC0U) -#define PUF_IDXBLK_L_DP_IDX3_SHIFT (6U) -#define PUF_IDXBLK_L_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK) -#define PUF_IDXBLK_L_DP_IDX4_MASK (0x300U) -#define PUF_IDXBLK_L_DP_IDX4_SHIFT (8U) -#define PUF_IDXBLK_L_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK) -#define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) -#define PUF_IDXBLK_L_DP_IDX5_SHIFT (10U) -#define PUF_IDXBLK_L_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK) -#define PUF_IDXBLK_L_DP_IDX6_MASK (0x3000U) -#define PUF_IDXBLK_L_DP_IDX6_SHIFT (12U) -#define PUF_IDXBLK_L_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK) -#define PUF_IDXBLK_L_DP_IDX7_MASK (0xC000U) -#define PUF_IDXBLK_L_DP_IDX7_SHIFT (14U) -#define PUF_IDXBLK_L_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK) -/*! @} */ - -/*! @name SHIFT_STATUS - */ -/*! @{ */ -#define PUF_SHIFT_STATUS_KEY0_MASK (0xFU) -#define PUF_SHIFT_STATUS_KEY0_SHIFT (0U) -#define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK) -#define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U) -#define PUF_SHIFT_STATUS_KEY1_SHIFT (4U) -#define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK) -#define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U) -#define PUF_SHIFT_STATUS_KEY2_SHIFT (8U) -#define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK) -#define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U) -#define PUF_SHIFT_STATUS_KEY3_SHIFT (12U) -#define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PUF_Register_Masks */ - - -/* PUF - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral PUF base address */ - #define PUF_BASE (0x5003B000u) - /** Peripheral PUF base address */ - #define PUF_BASE_NS (0x4003B000u) - /** Peripheral PUF base pointer */ - #define PUF ((PUF_Type *)PUF_BASE) - /** Peripheral PUF base pointer */ - #define PUF_NS ((PUF_Type *)PUF_BASE_NS) - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS { PUF_BASE } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS { PUF } - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_NS { PUF_BASE_NS } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_NS { PUF_NS } -#else - /** Peripheral PUF base address */ - #define PUF_BASE (0x4003B000u) - /** Peripheral PUF base pointer */ - #define PUF ((PUF_Type *)PUF_BASE) - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS { PUF_BASE } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS { PUF } -#endif -/** Interrupt vectors for the PUF peripheral type */ -#define PUF_IRQS { PUF_IRQn } - -/*! - * @} - */ /* end of group PUF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RNG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer - * @{ - */ - -/** RNG - Register Layout Typedef */ -typedef struct { - __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */ - __I uint32_t ENCRYPTED_NUMBER; /**< This register contains a random 32 bit number which is pre-computed, offset: 0x4 */ - __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */ - __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */ - __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */ - __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */ - __IO uint32_t MISC_CFG; /**< , offset: 0x18 */ - uint8_t RESERVED_0[4056]; - __IO uint32_t POWERDOWN; /**< Powerdown mode (standard but certainly useless here), offset: 0xFF4 */ - uint8_t RESERVED_1[4]; - __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */ -} RNG_Type; - -/* ---------------------------------------------------------------------------- - -- RNG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Register_Masks RNG Register Masks - * @{ - */ - -/*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */ -/*! @{ */ -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU) -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U) -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK) -/*! @} */ - -/*! @name ENCRYPTED_NUMBER - This register contains a random 32 bit number which is pre-computed */ -/*! @{ */ -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK (0xFFFFFFFFU) -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT (0U) -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT)) & RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK) -/*! @} */ - -/*! @name COUNTER_VAL - */ -/*! @{ */ -#define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU) -#define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U) -#define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK) -#define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x1F00U) -#define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U) -#define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK) -/*! @} */ - -/*! @name COUNTER_CFG - */ -/*! @{ */ -#define RNG_COUNTER_CFG_MODE_MASK (0x3U) -#define RNG_COUNTER_CFG_MODE_SHIFT (0U) -#define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK) -#define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU) -#define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U) -#define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK) -#define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U) -#define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U) -#define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK) -#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_MASK (0x100U) -#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_SHIFT (8U) -#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_SHIFT)) & RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_MASK) -#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_MASK (0x200U) -#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_SHIFT (9U) -#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_SHIFT)) & RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_MASK) -/*! @} */ - -/*! @name ONLINE_TEST_CFG - */ -/*! @{ */ -#define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U) -#define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U) -#define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK) -#define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U) -#define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U) -#define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK) -/*! @} */ - -/*! @name ONLINE_TEST_VAL - */ -/*! @{ */ -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU) -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U) -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK) -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U) -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U) -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U) -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U) -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) -/*! @} */ - -/*! @name MISC_CFG - */ -/*! @{ */ -#define RNG_MISC_CFG_AES_RESEED_MASK (0x1U) -#define RNG_MISC_CFG_AES_RESEED_SHIFT (0U) -#define RNG_MISC_CFG_AES_RESEED(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_RESEED_SHIFT)) & RNG_MISC_CFG_AES_RESEED_MASK) -#define RNG_MISC_CFG_AES_DT_CFG_MASK (0x2U) -#define RNG_MISC_CFG_AES_DT_CFG_SHIFT (1U) -#define RNG_MISC_CFG_AES_DT_CFG(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_DT_CFG_SHIFT)) & RNG_MISC_CFG_AES_DT_CFG_MASK) -/*! @} */ - -/*! @name POWERDOWN - Powerdown mode (standard but certainly useless here) */ -/*! @{ */ -#define RNG_POWERDOWN_SOFT_RESET_MASK (0x1U) -#define RNG_POWERDOWN_SOFT_RESET_SHIFT (0U) -#define RNG_POWERDOWN_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_SOFT_RESET_MASK) -#define RNG_POWERDOWN_FORCE_SOFT_RESET_MASK (0x2U) -#define RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT (1U) -#define RNG_POWERDOWN_FORCE_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_FORCE_SOFT_RESET_MASK) -#define RNG_POWERDOWN_POWERDOWN_MASK (0x80000000U) -#define RNG_POWERDOWN_POWERDOWN_SHIFT (31U) -#define RNG_POWERDOWN_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_POWERDOWN_SHIFT)) & RNG_POWERDOWN_POWERDOWN_MASK) -/*! @} */ - -/*! @name MODULEID - IP identifier */ -/*! @{ */ -#define RNG_MODULEID_APERTURE_MASK (0xFFU) -#define RNG_MODULEID_APERTURE_SHIFT (0U) -#define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK) -#define RNG_MODULEID_MIN_REV_MASK (0xF00U) -#define RNG_MODULEID_MIN_REV_SHIFT (8U) -#define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK) -#define RNG_MODULEID_MAJ_REV_MASK (0xF000U) -#define RNG_MODULEID_MAJ_REV_SHIFT (12U) -#define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK) -#define RNG_MODULEID_ID_MASK (0xFFFF0000U) -#define RNG_MODULEID_ID_SHIFT (16U) -#define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group RNG_Register_Masks */ - - -/* RNG - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral RNG base address */ - #define RNG_BASE (0x5003A000u) - /** Peripheral RNG base address */ - #define RNG_BASE_NS (0x4003A000u) - /** Peripheral RNG base pointer */ - #define RNG ((RNG_Type *)RNG_BASE) - /** Peripheral RNG base pointer */ - #define RNG_NS ((RNG_Type *)RNG_BASE_NS) - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS { RNG_BASE } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS { RNG } - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS_NS { RNG_BASE_NS } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS_NS { RNG_NS } -#else - /** Peripheral RNG base address */ - #define RNG_BASE (0x4003A000u) - /** Peripheral RNG base pointer */ - #define RNG ((RNG_Type *)RNG_BASE) - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS { RNG_BASE } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS { RNG } -#endif - -/*! - * @} - */ /* end of group RNG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer - * @{ - */ - -/** RTC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ - __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ - __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ - __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ - __I uint32_t SUBSEC; /**< RTC Sub-second Counter register, offset: 0x10 */ - uint8_t RESERVED_0[44]; - __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ -} RTC_Type; - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/*! @name CTRL - RTC control register */ -/*! @{ */ -#define RTC_CTRL_SWRESET_MASK (0x1U) -#define RTC_CTRL_SWRESET_SHIFT (0U) -/*! SWRESET - Software reset control - * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. - * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. - */ -#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) -#define RTC_CTRL_ALARM1HZ_MASK (0x4U) -#define RTC_CTRL_ALARM1HZ_SHIFT (2U) -/*! ALARM1HZ - RTC 1 Hz timer alarm flag status. - * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. - * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. - */ -#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) -#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) -#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) -/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. - * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. - * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. - */ -#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) -#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) -#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) -/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. - * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. - */ -#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) -#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) -#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) -/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. - * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. - */ -#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) -#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) -#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) -/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). - * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. The 1 kHz RTC timer is enabled. - */ -#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) -#define RTC_CTRL_RTC_EN_MASK (0x80U) -#define RTC_CTRL_RTC_EN_SHIFT (7U) -/*! RTC_EN - RTC enable. - * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register. - * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register. - */ -#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) -#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) -#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) -/*! RTC_OSC_PD - RTC oscillator power-down control. - * 0b0..See RTC_OSC_BYPASS - * 0b1..RTC oscillator is powered-down. - */ -#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) -#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) -#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) -/*! RTC_OSC_BYPASS - RTC oscillator bypass control. - * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. - * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. - */ -#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) -#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U) -#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U) -/*! RTC_SUBSEC_ENA - RTC Sub-second counter control. - * 0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second counter, this bit will always read-back as a '0'. - * 0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip exits deep power-down mode. - */ -#define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK) -/*! @} */ - -/*! @name MATCH - RTC match register */ -/*! @{ */ -#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) -#define RTC_MATCH_MATVAL_SHIFT (0U) -#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) -/*! @} */ - -/*! @name COUNT - RTC counter register */ -/*! @{ */ -#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) -#define RTC_COUNT_VAL_SHIFT (0U) -#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) -/*! @} */ - -/*! @name WAKE - High-resolution/wake-up timer control register */ -/*! @{ */ -#define RTC_WAKE_VAL_MASK (0xFFFFU) -#define RTC_WAKE_VAL_SHIFT (0U) -#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) -/*! @} */ - -/*! @name SUBSEC - RTC Sub-second Counter register */ -/*! @{ */ -#define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU) -#define RTC_SUBSEC_SUBSEC_SHIFT (0U) -#define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK) -/*! @} */ - -/*! @name GPREG - General Purpose register */ -/*! @{ */ -#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) -#define RTC_GPREG_GPDATA_SHIFT (0U) -#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) -/*! @} */ - -/* The count of RTC_GPREG */ -#define RTC_GPREG_COUNT (8U) - - -/*! - * @} - */ /* end of group RTC_Register_Masks */ - - -/* RTC - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral RTC base address */ - #define RTC_BASE (0x5002C000u) - /** Peripheral RTC base address */ - #define RTC_BASE_NS (0x4002C000u) - /** Peripheral RTC base pointer */ - #define RTC ((RTC_Type *)RTC_BASE) - /** Peripheral RTC base pointer */ - #define RTC_NS ((RTC_Type *)RTC_BASE_NS) - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS { RTC_BASE } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS { RTC } - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS_NS { RTC_NS } -#else - /** Peripheral RTC base address */ - #define RTC_BASE (0x4002C000u) - /** Peripheral RTC base pointer */ - #define RTC ((RTC_Type *)RTC_BASE) - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS { RTC_BASE } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS { RTC } -#endif -/** Interrupt vectors for the RTC peripheral type */ -#define RTC_IRQS { RTC_IRQn } - -/*! - * @} - */ /* end of group RTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SCT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer - * @{ - */ - -/** SCT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ - __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ - __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ - __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ - __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ - __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ - uint8_t RESERVED_0[40]; - __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ - __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ - __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ - __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ - __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ - __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ - __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ - __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */ - __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */ - uint8_t RESERVED_1[140]; - __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ - __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ - __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ - __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ - union { /* offset: 0x100 */ - __IO uint32_t SCTCAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ - __IO uint32_t SCTMATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ - }; - uint8_t RESERVED_2[216]; - union { /* offset: 0x200 */ - __IO uint32_t SCTCAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ - __IO uint32_t SCTMATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ - }; - uint8_t RESERVED_3[216]; - struct { /* offset: 0x300, array step: 0x8 */ - __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ - __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ - } EVENT[10]; - uint8_t RESERVED_4[432]; - struct { /* offset: 0x500, array step: 0x8 */ - __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ - __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ - } OUT[10]; -} SCT_Type; - -/* ---------------------------------------------------------------------------- - -- SCT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Register_Masks SCT Register Masks - * @{ - */ - -/*! @name CONFIG - SCT configuration register */ -/*! @{ */ -#define SCT_CONFIG_UNIFY_MASK (0x1U) -#define SCT_CONFIG_UNIFY_SHIFT (0U) -/*! UNIFY - SCT operation - * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. - * 0b1..The SCT operates as a unified 32-bit counter. - */ -#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) -#define SCT_CONFIG_CLKMODE_MASK (0x6U) -#define SCT_CONFIG_CLKMODE_SHIFT (1U) -/*! CLKMODE - SCT clock mode - * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. - * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode. - * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. - * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock. - */ -#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) -#define SCT_CONFIG_CKSEL_MASK (0x78U) -#define SCT_CONFIG_CKSEL_SHIFT (3U) -/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register. - * 0b0000..Rising edges on input 0. - * 0b0001..Falling edges on input 0. - * 0b0010..Rising edges on input 1. - * 0b0011..Falling edges on input 1. - * 0b0100..Rising edges on input 2. - * 0b0101..Falling edges on input 2. - * 0b0110..Rising edges on input 3. - * 0b0111..Falling edges on input 3. - */ -#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) -#define SCT_CONFIG_NORELAOD_L_MASK (0x80U) -#define SCT_CONFIG_NORELAOD_L_SHIFT (7U) -#define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK) -#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) -#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) -#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) -#define SCT_CONFIG_INSYNC_MASK (0x1E00U) -#define SCT_CONFIG_INSYNC_SHIFT (9U) -#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) -#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) -#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) -#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) -#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) -#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) -#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) -/*! @} */ - -/*! @name CTRL - SCT control register */ -/*! @{ */ -#define SCT_CTRL_DOWN_L_MASK (0x1U) -#define SCT_CTRL_DOWN_L_SHIFT (0U) -#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) -#define SCT_CTRL_STOP_L_MASK (0x2U) -#define SCT_CTRL_STOP_L_SHIFT (1U) -#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) -#define SCT_CTRL_HALT_L_MASK (0x4U) -#define SCT_CTRL_HALT_L_SHIFT (2U) -#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) -#define SCT_CTRL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRL_CLRCTR_L_SHIFT (3U) -#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) -#define SCT_CTRL_BIDIR_L_MASK (0x10U) -#define SCT_CTRL_BIDIR_L_SHIFT (4U) -/*! BIDIR_L - L or unified counter direction select - * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. - * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) -#define SCT_CTRL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRL_PRE_L_SHIFT (5U) -#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) -#define SCT_CTRL_DOWN_H_MASK (0x10000U) -#define SCT_CTRL_DOWN_H_SHIFT (16U) -#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) -#define SCT_CTRL_STOP_H_MASK (0x20000U) -#define SCT_CTRL_STOP_H_SHIFT (17U) -#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) -#define SCT_CTRL_HALT_H_MASK (0x40000U) -#define SCT_CTRL_HALT_H_SHIFT (18U) -#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) -#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) -#define SCT_CTRL_CLRCTR_H_SHIFT (19U) -#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) -#define SCT_CTRL_BIDIR_H_MASK (0x100000U) -#define SCT_CTRL_BIDIR_H_SHIFT (20U) -/*! BIDIR_H - Direction select - * 0b0..The H counter counts up to its limit condition, then is cleared to zero. - * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) -#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) -#define SCT_CTRL_PRE_H_SHIFT (21U) -#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) -/*! @} */ - -/*! @name LIMIT - SCT limit event select register */ -/*! @{ */ -#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) -#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) -#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) -#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) -#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) -#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) -/*! @} */ - -/*! @name HALT - SCT halt event select register */ -/*! @{ */ -#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) -#define SCT_HALT_HALTMSK_L_SHIFT (0U) -#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) -#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) -#define SCT_HALT_HALTMSK_H_SHIFT (16U) -#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) -/*! @} */ - -/*! @name STOP - SCT stop event select register */ -/*! @{ */ -#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) -#define SCT_STOP_STOPMSK_L_SHIFT (0U) -#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) -#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) -#define SCT_STOP_STOPMSK_H_SHIFT (16U) -#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) -/*! @} */ - -/*! @name START - SCT start event select register */ -/*! @{ */ -#define SCT_START_STARTMSK_L_MASK (0xFFFFU) -#define SCT_START_STARTMSK_L_SHIFT (0U) -#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) -#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) -#define SCT_START_STARTMSK_H_SHIFT (16U) -#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) -/*! @} */ - -/*! @name COUNT - SCT counter register */ -/*! @{ */ -#define SCT_COUNT_CTR_L_MASK (0xFFFFU) -#define SCT_COUNT_CTR_L_SHIFT (0U) -#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) -#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) -#define SCT_COUNT_CTR_H_SHIFT (16U) -#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) -/*! @} */ - -/*! @name STATE - SCT state register */ -/*! @{ */ -#define SCT_STATE_STATE_L_MASK (0x1FU) -#define SCT_STATE_STATE_L_SHIFT (0U) -#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) -#define SCT_STATE_STATE_H_MASK (0x1F0000U) -#define SCT_STATE_STATE_H_SHIFT (16U) -#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) -/*! @} */ - -/*! @name INPUT - SCT input register */ -/*! @{ */ -#define SCT_INPUT_AIN0_MASK (0x1U) -#define SCT_INPUT_AIN0_SHIFT (0U) -#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) -#define SCT_INPUT_AIN1_MASK (0x2U) -#define SCT_INPUT_AIN1_SHIFT (1U) -#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) -#define SCT_INPUT_AIN2_MASK (0x4U) -#define SCT_INPUT_AIN2_SHIFT (2U) -#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) -#define SCT_INPUT_AIN3_MASK (0x8U) -#define SCT_INPUT_AIN3_SHIFT (3U) -#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) -#define SCT_INPUT_AIN4_MASK (0x10U) -#define SCT_INPUT_AIN4_SHIFT (4U) -#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) -#define SCT_INPUT_AIN5_MASK (0x20U) -#define SCT_INPUT_AIN5_SHIFT (5U) -#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) -#define SCT_INPUT_AIN6_MASK (0x40U) -#define SCT_INPUT_AIN6_SHIFT (6U) -#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) -#define SCT_INPUT_AIN7_MASK (0x80U) -#define SCT_INPUT_AIN7_SHIFT (7U) -#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) -#define SCT_INPUT_AIN8_MASK (0x100U) -#define SCT_INPUT_AIN8_SHIFT (8U) -#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) -#define SCT_INPUT_AIN9_MASK (0x200U) -#define SCT_INPUT_AIN9_SHIFT (9U) -#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) -#define SCT_INPUT_AIN10_MASK (0x400U) -#define SCT_INPUT_AIN10_SHIFT (10U) -#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) -#define SCT_INPUT_AIN11_MASK (0x800U) -#define SCT_INPUT_AIN11_SHIFT (11U) -#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) -#define SCT_INPUT_AIN12_MASK (0x1000U) -#define SCT_INPUT_AIN12_SHIFT (12U) -#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) -#define SCT_INPUT_AIN13_MASK (0x2000U) -#define SCT_INPUT_AIN13_SHIFT (13U) -#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) -#define SCT_INPUT_AIN14_MASK (0x4000U) -#define SCT_INPUT_AIN14_SHIFT (14U) -#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) -#define SCT_INPUT_AIN15_MASK (0x8000U) -#define SCT_INPUT_AIN15_SHIFT (15U) -#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) -#define SCT_INPUT_SIN0_MASK (0x10000U) -#define SCT_INPUT_SIN0_SHIFT (16U) -#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) -#define SCT_INPUT_SIN1_MASK (0x20000U) -#define SCT_INPUT_SIN1_SHIFT (17U) -#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) -#define SCT_INPUT_SIN2_MASK (0x40000U) -#define SCT_INPUT_SIN2_SHIFT (18U) -#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) -#define SCT_INPUT_SIN3_MASK (0x80000U) -#define SCT_INPUT_SIN3_SHIFT (19U) -#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) -#define SCT_INPUT_SIN4_MASK (0x100000U) -#define SCT_INPUT_SIN4_SHIFT (20U) -#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) -#define SCT_INPUT_SIN5_MASK (0x200000U) -#define SCT_INPUT_SIN5_SHIFT (21U) -#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) -#define SCT_INPUT_SIN6_MASK (0x400000U) -#define SCT_INPUT_SIN6_SHIFT (22U) -#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) -#define SCT_INPUT_SIN7_MASK (0x800000U) -#define SCT_INPUT_SIN7_SHIFT (23U) -#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) -#define SCT_INPUT_SIN8_MASK (0x1000000U) -#define SCT_INPUT_SIN8_SHIFT (24U) -#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) -#define SCT_INPUT_SIN9_MASK (0x2000000U) -#define SCT_INPUT_SIN9_SHIFT (25U) -#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) -#define SCT_INPUT_SIN10_MASK (0x4000000U) -#define SCT_INPUT_SIN10_SHIFT (26U) -#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) -#define SCT_INPUT_SIN11_MASK (0x8000000U) -#define SCT_INPUT_SIN11_SHIFT (27U) -#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) -#define SCT_INPUT_SIN12_MASK (0x10000000U) -#define SCT_INPUT_SIN12_SHIFT (28U) -#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) -#define SCT_INPUT_SIN13_MASK (0x20000000U) -#define SCT_INPUT_SIN13_SHIFT (29U) -#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) -#define SCT_INPUT_SIN14_MASK (0x40000000U) -#define SCT_INPUT_SIN14_SHIFT (30U) -#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) -#define SCT_INPUT_SIN15_MASK (0x80000000U) -#define SCT_INPUT_SIN15_SHIFT (31U) -#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) -/*! @} */ - -/*! @name REGMODE - SCT match/capture mode register */ -/*! @{ */ -#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) -#define SCT_REGMODE_REGMOD_L_SHIFT (0U) -#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) -#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) -#define SCT_REGMODE_REGMOD_H_SHIFT (16U) -#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) -/*! @} */ - -/*! @name OUTPUT - SCT output register */ -/*! @{ */ -#define SCT_OUTPUT_OUT_MASK (0xFFFFU) -#define SCT_OUTPUT_OUT_SHIFT (0U) -#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) -/*! @} */ - -/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ -/*! @{ */ -#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) -#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) -/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) -#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) -/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) -#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) -/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) -#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) -/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) -#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) -/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) -#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) -/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) -#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) -/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) -#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) -/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) -#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) -/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) -#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) -/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) -#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) -/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) -#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) -/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) -/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) -/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) -/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) -/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) -/*! @} */ - -/*! @name RES - SCT conflict resolution register */ -/*! @{ */ -#define SCT_RES_O0RES_MASK (0x3U) -#define SCT_RES_O0RES_SHIFT (0U) -/*! O0RES - Effect of simultaneous set and clear on output 0. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR0 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) -#define SCT_RES_O1RES_MASK (0xCU) -#define SCT_RES_O1RES_SHIFT (2U) -/*! O1RES - Effect of simultaneous set and clear on output 1. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR1 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) -#define SCT_RES_O2RES_MASK (0x30U) -#define SCT_RES_O2RES_SHIFT (4U) -/*! O2RES - Effect of simultaneous set and clear on output 2. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output n (or set based on the SETCLR2 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) -#define SCT_RES_O3RES_MASK (0xC0U) -#define SCT_RES_O3RES_SHIFT (6U) -/*! O3RES - Effect of simultaneous set and clear on output 3. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR3 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) -#define SCT_RES_O4RES_MASK (0x300U) -#define SCT_RES_O4RES_SHIFT (8U) -/*! O4RES - Effect of simultaneous set and clear on output 4. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR4 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) -#define SCT_RES_O5RES_MASK (0xC00U) -#define SCT_RES_O5RES_SHIFT (10U) -/*! O5RES - Effect of simultaneous set and clear on output 5. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR5 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) -#define SCT_RES_O6RES_MASK (0x3000U) -#define SCT_RES_O6RES_SHIFT (12U) -/*! O6RES - Effect of simultaneous set and clear on output 6. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR6 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) -#define SCT_RES_O7RES_MASK (0xC000U) -#define SCT_RES_O7RES_SHIFT (14U) -/*! O7RES - Effect of simultaneous set and clear on output 7. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output n (or set based on the SETCLR7 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) -#define SCT_RES_O8RES_MASK (0x30000U) -#define SCT_RES_O8RES_SHIFT (16U) -/*! O8RES - Effect of simultaneous set and clear on output 8. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR8 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) -#define SCT_RES_O9RES_MASK (0xC0000U) -#define SCT_RES_O9RES_SHIFT (18U) -/*! O9RES - Effect of simultaneous set and clear on output 9. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR9 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) -#define SCT_RES_O10RES_MASK (0x300000U) -#define SCT_RES_O10RES_SHIFT (20U) -/*! O10RES - Effect of simultaneous set and clear on output 10. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR10 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) -#define SCT_RES_O11RES_MASK (0xC00000U) -#define SCT_RES_O11RES_SHIFT (22U) -/*! O11RES - Effect of simultaneous set and clear on output 11. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR11 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) -#define SCT_RES_O12RES_MASK (0x3000000U) -#define SCT_RES_O12RES_SHIFT (24U) -/*! O12RES - Effect of simultaneous set and clear on output 12. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR12 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) -#define SCT_RES_O13RES_MASK (0xC000000U) -#define SCT_RES_O13RES_SHIFT (26U) -/*! O13RES - Effect of simultaneous set and clear on output 13. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR13 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) -#define SCT_RES_O14RES_MASK (0x30000000U) -#define SCT_RES_O14RES_SHIFT (28U) -/*! O14RES - Effect of simultaneous set and clear on output 14. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR14 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) -#define SCT_RES_O15RES_MASK (0xC0000000U) -#define SCT_RES_O15RES_SHIFT (30U) -/*! O15RES - Effect of simultaneous set and clear on output 15. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR15 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) -/*! @} */ - -/*! @name DMA0REQUEST - SCT DMA request 0 register */ -/*! @{ */ -#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU) -#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U) -#define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK) -#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U) -#define SCT_DMA0REQUEST_DRL0_SHIFT (30U) -#define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK) -#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U) -#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U) -#define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK) -/*! @} */ - -/*! @name DMA1REQUEST - SCT DMA request 1 register */ -/*! @{ */ -#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU) -#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U) -#define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK) -#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U) -#define SCT_DMA1REQUEST_DRL1_SHIFT (30U) -#define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK) -#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U) -#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U) -#define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK) -/*! @} */ - -/*! @name EVEN - SCT event interrupt enable register */ -/*! @{ */ -#define SCT_EVEN_IEN_MASK (0xFFFFU) -#define SCT_EVEN_IEN_SHIFT (0U) -#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) -/*! @} */ - -/*! @name EVFLAG - SCT event flag register */ -/*! @{ */ -#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) -#define SCT_EVFLAG_FLAG_SHIFT (0U) -#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) -/*! @} */ - -/*! @name CONEN - SCT conflict interrupt enable register */ -/*! @{ */ -#define SCT_CONEN_NCEN_MASK (0xFFFFU) -#define SCT_CONEN_NCEN_SHIFT (0U) -#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) -/*! @} */ - -/*! @name CONFLAG - SCT conflict flag register */ -/*! @{ */ -#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) -#define SCT_CONFLAG_NCFLAG_SHIFT (0U) -#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) -#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) -#define SCT_CONFLAG_BUSERRL_SHIFT (30U) -#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) -#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) -#define SCT_CONFLAG_BUSERRH_SHIFT (31U) -#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) -/*! @} */ - -/*! @name SCTCAP - SCT capture register of capture channel */ -/*! @{ */ -#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU) -#define SCT_SCTCAP_CAPn_L_SHIFT (0U) -#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK) -#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U) -#define SCT_SCTCAP_CAPn_H_SHIFT (16U) -#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTCAP */ -#define SCT_SCTCAP_COUNT (10U) - -/*! @name SCTMATCH - SCT match value register of match channels */ -/*! @{ */ -#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU) -#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U) -#define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK) -#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U) -#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U) -#define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTMATCH */ -#define SCT_SCTMATCH_COUNT (10U) - -/*! @name SCTCAPCTRL - SCT capture control register */ -/*! @{ */ -#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU) -#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U) -#define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK) -#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) -#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U) -#define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTCAPCTRL */ -#define SCT_SCTCAPCTRL_COUNT (10U) - -/*! @name SCTMATCHREL - SCT match reload value register */ -/*! @{ */ -#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU) -#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U) -#define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK) -#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U) -#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U) -#define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTMATCHREL */ -#define SCT_SCTMATCHREL_COUNT (10U) - -/*! @name EVENT_STATE - SCT event state register 0 */ -/*! @{ */ -#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU) -#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U) -#define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK) -/*! @} */ - -/* The count of SCT_EVENT_STATE */ -#define SCT_EVENT_STATE_COUNT (10U) - -/*! @name EVENT_CTRL - SCT event control register 0 */ -/*! @{ */ -#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU) -#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U) -#define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK) -#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U) -#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U) -/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. - * 0b0..Selects the L state and the L match register selected by MATCHSEL. - * 0b1..Selects the H state and the H match register selected by MATCHSEL. - */ -#define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK) -#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U) -#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U) -/*! OUTSEL - Input/output select - * 0b0..Selects the inputs selected by IOSEL. - * 0b1..Selects the outputs selected by IOSEL. - */ -#define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK) -#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U) -#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U) -#define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK) -#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U) -#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U) -/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . - * 0b00..LOW - * 0b01..Rise - * 0b10..Fall - * 0b11..HIGH - */ -#define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK) -#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U) -#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U) -/*! COMBMODE - Selects how the specified match and I/O condition are used and combined. - * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. - * 0b01..MATCH. Uses the specified match only. - * 0b10..IO. Uses the specified I/O condition only. - * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. - */ -#define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK) -#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U) -#define SCT_EVENT_CTRL_STATELD_SHIFT (14U) -/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. - * 0b0..STATEV value is added into STATE (the carry-out is ignored). - * 0b1..STATEV value is loaded into STATE. - */ -#define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK) -#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U) -#define SCT_EVENT_CTRL_STATEV_SHIFT (15U) -#define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK) -#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U) -#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U) -#define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK) -#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U) -#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U) -/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. - * 0b00..Direction independent. This event is triggered regardless of the count direction. - * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. - * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. - */ -#define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK) -/*! @} */ - -/* The count of SCT_EVENT_CTRL */ -#define SCT_EVENT_CTRL_COUNT (10U) - -/*! @name OUT_SET - SCT output 0 set register */ -/*! @{ */ -#define SCT_OUT_SET_SET_MASK (0xFFFFU) -#define SCT_OUT_SET_SET_SHIFT (0U) -#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) -/*! @} */ - -/* The count of SCT_OUT_SET */ -#define SCT_OUT_SET_COUNT (10U) - -/*! @name OUT_CLR - SCT output 0 clear register */ -/*! @{ */ -#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) -#define SCT_OUT_CLR_CLR_SHIFT (0U) -#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) -/*! @} */ - -/* The count of SCT_OUT_CLR */ -#define SCT_OUT_CLR_COUNT (10U) - - -/*! - * @} - */ /* end of group SCT_Register_Masks */ - - -/* SCT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral SCT0 base address */ - #define SCT0_BASE (0x50085000u) - /** Peripheral SCT0 base address */ - #define SCT0_BASE_NS (0x40085000u) - /** Peripheral SCT0 base pointer */ - #define SCT0 ((SCT_Type *)SCT0_BASE) - /** Peripheral SCT0 base pointer */ - #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS { SCT0_BASE } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS { SCT0 } - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS_NS { SCT0_NS } -#else - /** Peripheral SCT0 base address */ - #define SCT0_BASE (0x40085000u) - /** Peripheral SCT0 base pointer */ - #define SCT0 ((SCT_Type *)SCT0_BASE) - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS { SCT0_BASE } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS { SCT0 } -#endif -/** Interrupt vectors for the SCT peripheral type */ -#define SCT_IRQS { SCT0_IRQn } - -/*! - * @} - */ /* end of group SCT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SDIF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer - * @{ - */ - -/** SDIF - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ - __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */ - __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */ - __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */ - __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */ - __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */ - __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */ - __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */ - __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */ - __IO uint32_t CMD; /**< Command register, offset: 0x2C */ - __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */ - __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */ - __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */ - __IO uint32_t STATUS; /**< Status register, offset: 0x48 */ - __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */ - __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */ - __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */ - uint8_t RESERVED_1[4]; - __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */ - __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */ - __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */ - uint8_t RESERVED_2[16]; - __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */ - uint8_t RESERVED_3[4]; - __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */ - __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */ - __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */ - __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */ - __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */ - __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */ - __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */ - uint8_t RESERVED_4[100]; - __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */ - __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */ - uint8_t RESERVED_5[248]; - __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */ -} SDIF_Type; - -/* ---------------------------------------------------------------------------- - -- SDIF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDIF_Register_Masks SDIF Register Masks - * @{ - */ - -/*! @name CTRL - Control register */ -/*! @{ */ -#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U) -#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U) -#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK) -#define SDIF_CTRL_FIFO_RESET_MASK (0x2U) -#define SDIF_CTRL_FIFO_RESET_SHIFT (1U) -#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK) -#define SDIF_CTRL_DMA_RESET_MASK (0x4U) -#define SDIF_CTRL_DMA_RESET_SHIFT (2U) -#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK) -#define SDIF_CTRL_INT_ENABLE_MASK (0x10U) -#define SDIF_CTRL_INT_ENABLE_SHIFT (4U) -#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK) -#define SDIF_CTRL_READ_WAIT_MASK (0x40U) -#define SDIF_CTRL_READ_WAIT_SHIFT (6U) -#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK) -#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U) -#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) -#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK) -#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U) -#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U) -#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK) -#define SDIF_CTRL_SEND_CCSD_MASK (0x200U) -#define SDIF_CTRL_SEND_CCSD_SHIFT (9U) -#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK) -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U) -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK) -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U) -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK) -#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U) -#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U) -#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK) -#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U) -#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U) -#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK) -#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U) -#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U) -#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK) -#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U) -#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) -#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) -/*! @} */ - -/*! @name PWREN - Power Enable register */ -/*! @{ */ -#define SDIF_PWREN_POWER_ENABLE0_MASK (0x1U) -#define SDIF_PWREN_POWER_ENABLE0_SHIFT (0U) -#define SDIF_PWREN_POWER_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK) -#define SDIF_PWREN_POWER_ENABLE1_MASK (0x2U) -#define SDIF_PWREN_POWER_ENABLE1_SHIFT (1U) -#define SDIF_PWREN_POWER_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK) -/*! @} */ - -/*! @name CLKDIV - Clock Divider register */ -/*! @{ */ -#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU) -#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U) -#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK) -/*! @} */ - -/*! @name CLKENA - Clock Enable register */ -/*! @{ */ -#define SDIF_CLKENA_CCLK0_ENABLE_MASK (0x1U) -#define SDIF_CLKENA_CCLK0_ENABLE_SHIFT (0U) -#define SDIF_CLKENA_CCLK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK) -#define SDIF_CLKENA_CCLK1_ENABLE_MASK (0x2U) -#define SDIF_CLKENA_CCLK1_ENABLE_SHIFT (1U) -#define SDIF_CLKENA_CCLK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK) -#define SDIF_CLKENA_CCLK0_LOW_POWER_MASK (0x10000U) -#define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT (16U) -#define SDIF_CLKENA_CCLK0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK) -#define SDIF_CLKENA_CCLK1_LOW_POWER_MASK (0x20000U) -#define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT (17U) -#define SDIF_CLKENA_CCLK1_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK) -/*! @} */ - -/*! @name TMOUT - Time-out register */ -/*! @{ */ -#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU) -#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) -#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK) -#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U) -#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U) -#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK) -/*! @} */ - -/*! @name CTYPE - Card Type register */ -/*! @{ */ -#define SDIF_CTYPE_CARD0_WIDTH0_MASK (0x1U) -#define SDIF_CTYPE_CARD0_WIDTH0_SHIFT (0U) -#define SDIF_CTYPE_CARD0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK) -#define SDIF_CTYPE_CARD1_WIDTH0_MASK (0x2U) -#define SDIF_CTYPE_CARD1_WIDTH0_SHIFT (1U) -#define SDIF_CTYPE_CARD1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK) -#define SDIF_CTYPE_CARD0_WIDTH1_MASK (0x10000U) -#define SDIF_CTYPE_CARD0_WIDTH1_SHIFT (16U) -#define SDIF_CTYPE_CARD0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK) -#define SDIF_CTYPE_CARD1_WIDTH1_MASK (0x20000U) -#define SDIF_CTYPE_CARD1_WIDTH1_SHIFT (17U) -#define SDIF_CTYPE_CARD1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK) -/*! @} */ - -/*! @name BLKSIZ - Block Size register */ -/*! @{ */ -#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU) -#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U) -#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK) -/*! @} */ - -/*! @name BYTCNT - Byte Count register */ -/*! @{ */ -#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U) -#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK) -/*! @} */ - -/*! @name INTMASK - Interrupt Mask register */ -/*! @{ */ -#define SDIF_INTMASK_CDET_MASK (0x1U) -#define SDIF_INTMASK_CDET_SHIFT (0U) -#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK) -#define SDIF_INTMASK_RE_MASK (0x2U) -#define SDIF_INTMASK_RE_SHIFT (1U) -#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK) -#define SDIF_INTMASK_CDONE_MASK (0x4U) -#define SDIF_INTMASK_CDONE_SHIFT (2U) -#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK) -#define SDIF_INTMASK_DTO_MASK (0x8U) -#define SDIF_INTMASK_DTO_SHIFT (3U) -#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK) -#define SDIF_INTMASK_TXDR_MASK (0x10U) -#define SDIF_INTMASK_TXDR_SHIFT (4U) -#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK) -#define SDIF_INTMASK_RXDR_MASK (0x20U) -#define SDIF_INTMASK_RXDR_SHIFT (5U) -#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK) -#define SDIF_INTMASK_RCRC_MASK (0x40U) -#define SDIF_INTMASK_RCRC_SHIFT (6U) -#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK) -#define SDIF_INTMASK_DCRC_MASK (0x80U) -#define SDIF_INTMASK_DCRC_SHIFT (7U) -#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK) -#define SDIF_INTMASK_RTO_MASK (0x100U) -#define SDIF_INTMASK_RTO_SHIFT (8U) -#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK) -#define SDIF_INTMASK_DRTO_MASK (0x200U) -#define SDIF_INTMASK_DRTO_SHIFT (9U) -#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK) -#define SDIF_INTMASK_HTO_MASK (0x400U) -#define SDIF_INTMASK_HTO_SHIFT (10U) -#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK) -#define SDIF_INTMASK_FRUN_MASK (0x800U) -#define SDIF_INTMASK_FRUN_SHIFT (11U) -#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK) -#define SDIF_INTMASK_HLE_MASK (0x1000U) -#define SDIF_INTMASK_HLE_SHIFT (12U) -#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK) -#define SDIF_INTMASK_SBE_MASK (0x2000U) -#define SDIF_INTMASK_SBE_SHIFT (13U) -#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK) -#define SDIF_INTMASK_ACD_MASK (0x4000U) -#define SDIF_INTMASK_ACD_SHIFT (14U) -#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK) -#define SDIF_INTMASK_EBE_MASK (0x8000U) -#define SDIF_INTMASK_EBE_SHIFT (15U) -#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK) -#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U) -#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U) -#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK) -/*! @} */ - -/*! @name CMDARG - Command Argument register */ -/*! @{ */ -#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU) -#define SDIF_CMDARG_CMD_ARG_SHIFT (0U) -#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK) -/*! @} */ - -/*! @name CMD - Command register */ -/*! @{ */ -#define SDIF_CMD_CMD_INDEX_MASK (0x3FU) -#define SDIF_CMD_CMD_INDEX_SHIFT (0U) -#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK) -#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U) -#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U) -#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK) -#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U) -#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U) -#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK) -#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U) -#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) -#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK) -#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U) -#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U) -#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK) -#define SDIF_CMD_READ_WRITE_MASK (0x400U) -#define SDIF_CMD_READ_WRITE_SHIFT (10U) -#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK) -#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U) -#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U) -#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK) -#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U) -#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U) -#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK) -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U) -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK) -#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U) -#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U) -#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK) -#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U) -#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U) -#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK) -#define SDIF_CMD_CARD_NUMBER_MASK (0x1F0000U) -#define SDIF_CMD_CARD_NUMBER_SHIFT (16U) -/*! CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed - * 0b00000..Command will be execute on SDCARD 0 - * 0b00001..Command will be execute on SDCARD 1 - */ -#define SDIF_CMD_CARD_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK) -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U) -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U) -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK) -#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U) -#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U) -#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK) -#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U) -#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U) -#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK) -#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U) -#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U) -#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK) -#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U) -#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U) -#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK) -#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U) -#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U) -#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK) -#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U) -#define SDIF_CMD_BOOT_MODE_SHIFT (27U) -#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK) -#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U) -#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U) -#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK) -#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U) -#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U) -#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK) -#define SDIF_CMD_START_CMD_MASK (0x80000000U) -#define SDIF_CMD_START_CMD_SHIFT (31U) -#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK) -/*! @} */ - -/*! @name RESP - Response register */ -/*! @{ */ -#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU) -#define SDIF_RESP_RESPONSE_SHIFT (0U) -#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK) -/*! @} */ - -/* The count of SDIF_RESP */ -#define SDIF_RESP_COUNT (4U) - -/*! @name MINTSTS - Masked Interrupt Status register */ -/*! @{ */ -#define SDIF_MINTSTS_CDET_MASK (0x1U) -#define SDIF_MINTSTS_CDET_SHIFT (0U) -#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK) -#define SDIF_MINTSTS_RE_MASK (0x2U) -#define SDIF_MINTSTS_RE_SHIFT (1U) -#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK) -#define SDIF_MINTSTS_CDONE_MASK (0x4U) -#define SDIF_MINTSTS_CDONE_SHIFT (2U) -#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK) -#define SDIF_MINTSTS_DTO_MASK (0x8U) -#define SDIF_MINTSTS_DTO_SHIFT (3U) -#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK) -#define SDIF_MINTSTS_TXDR_MASK (0x10U) -#define SDIF_MINTSTS_TXDR_SHIFT (4U) -#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK) -#define SDIF_MINTSTS_RXDR_MASK (0x20U) -#define SDIF_MINTSTS_RXDR_SHIFT (5U) -#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK) -#define SDIF_MINTSTS_RCRC_MASK (0x40U) -#define SDIF_MINTSTS_RCRC_SHIFT (6U) -#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK) -#define SDIF_MINTSTS_DCRC_MASK (0x80U) -#define SDIF_MINTSTS_DCRC_SHIFT (7U) -#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK) -#define SDIF_MINTSTS_RTO_MASK (0x100U) -#define SDIF_MINTSTS_RTO_SHIFT (8U) -#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK) -#define SDIF_MINTSTS_DRTO_MASK (0x200U) -#define SDIF_MINTSTS_DRTO_SHIFT (9U) -#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK) -#define SDIF_MINTSTS_HTO_MASK (0x400U) -#define SDIF_MINTSTS_HTO_SHIFT (10U) -#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK) -#define SDIF_MINTSTS_FRUN_MASK (0x800U) -#define SDIF_MINTSTS_FRUN_SHIFT (11U) -#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK) -#define SDIF_MINTSTS_HLE_MASK (0x1000U) -#define SDIF_MINTSTS_HLE_SHIFT (12U) -#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK) -#define SDIF_MINTSTS_SBE_MASK (0x2000U) -#define SDIF_MINTSTS_SBE_SHIFT (13U) -#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK) -#define SDIF_MINTSTS_ACD_MASK (0x4000U) -#define SDIF_MINTSTS_ACD_SHIFT (14U) -#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK) -#define SDIF_MINTSTS_EBE_MASK (0x8000U) -#define SDIF_MINTSTS_EBE_SHIFT (15U) -#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK) -#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U) -#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U) -#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK) -/*! @} */ - -/*! @name RINTSTS - Raw Interrupt Status register */ -/*! @{ */ -#define SDIF_RINTSTS_CDET_MASK (0x1U) -#define SDIF_RINTSTS_CDET_SHIFT (0U) -#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK) -#define SDIF_RINTSTS_RE_MASK (0x2U) -#define SDIF_RINTSTS_RE_SHIFT (1U) -#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK) -#define SDIF_RINTSTS_CDONE_MASK (0x4U) -#define SDIF_RINTSTS_CDONE_SHIFT (2U) -#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK) -#define SDIF_RINTSTS_DTO_MASK (0x8U) -#define SDIF_RINTSTS_DTO_SHIFT (3U) -#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK) -#define SDIF_RINTSTS_TXDR_MASK (0x10U) -#define SDIF_RINTSTS_TXDR_SHIFT (4U) -#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK) -#define SDIF_RINTSTS_RXDR_MASK (0x20U) -#define SDIF_RINTSTS_RXDR_SHIFT (5U) -#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK) -#define SDIF_RINTSTS_RCRC_MASK (0x40U) -#define SDIF_RINTSTS_RCRC_SHIFT (6U) -#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK) -#define SDIF_RINTSTS_DCRC_MASK (0x80U) -#define SDIF_RINTSTS_DCRC_SHIFT (7U) -#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK) -#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U) -#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U) -#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK) -#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U) -#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U) -#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK) -#define SDIF_RINTSTS_HTO_MASK (0x400U) -#define SDIF_RINTSTS_HTO_SHIFT (10U) -#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK) -#define SDIF_RINTSTS_FRUN_MASK (0x800U) -#define SDIF_RINTSTS_FRUN_SHIFT (11U) -#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK) -#define SDIF_RINTSTS_HLE_MASK (0x1000U) -#define SDIF_RINTSTS_HLE_SHIFT (12U) -#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK) -#define SDIF_RINTSTS_SBE_MASK (0x2000U) -#define SDIF_RINTSTS_SBE_SHIFT (13U) -#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK) -#define SDIF_RINTSTS_ACD_MASK (0x4000U) -#define SDIF_RINTSTS_ACD_SHIFT (14U) -#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK) -#define SDIF_RINTSTS_EBE_MASK (0x8000U) -#define SDIF_RINTSTS_EBE_SHIFT (15U) -#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK) -#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U) -#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U) -#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK) -/*! @} */ - -/*! @name STATUS - Status register */ -/*! @{ */ -#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U) -#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) -#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK) -#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U) -#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) -#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK) -#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U) -#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U) -#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK) -#define SDIF_STATUS_FIFO_FULL_MASK (0x8U) -#define SDIF_STATUS_FIFO_FULL_SHIFT (3U) -#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK) -#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U) -#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U) -#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK) -#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U) -#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U) -#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK) -#define SDIF_STATUS_DATA_BUSY_MASK (0x200U) -#define SDIF_STATUS_DATA_BUSY_SHIFT (9U) -#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK) -#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U) -#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) -#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK) -#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) -#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U) -#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK) -#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U) -#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U) -#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK) -#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U) -#define SDIF_STATUS_DMA_ACK_SHIFT (30U) -#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK) -#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U) -#define SDIF_STATUS_DMA_REQ_SHIFT (31U) -#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK) -/*! @} */ - -/*! @name FIFOTH - FIFO Threshold Watermark register */ -/*! @{ */ -#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU) -#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U) -#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK) -#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U) -#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U) -#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK) -#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U) -#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U) -#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK) -/*! @} */ - -/*! @name CDETECT - Card Detect register */ -/*! @{ */ -#define SDIF_CDETECT_CARD0_DETECT_MASK (0x1U) -#define SDIF_CDETECT_CARD0_DETECT_SHIFT (0U) -#define SDIF_CDETECT_CARD0_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK) -#define SDIF_CDETECT_CARD1_DETECT_MASK (0x2U) -#define SDIF_CDETECT_CARD1_DETECT_SHIFT (1U) -#define SDIF_CDETECT_CARD1_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK) -/*! @} */ - -/*! @name WRTPRT - Write Protect register */ -/*! @{ */ -#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U) -#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U) -#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK) -/*! @} */ - -/*! @name TCBCNT - Transferred CIU Card Byte Count register */ -/*! @{ */ -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK) -/*! @} */ - -/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */ -/*! @{ */ -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK) -/*! @} */ - -/*! @name DEBNCE - Debounce Count register */ -/*! @{ */ -#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU) -#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) -#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK) -/*! @} */ - -/*! @name RST_N - Hardware Reset */ -/*! @{ */ -#define SDIF_RST_N_CARD_RESET_MASK (0x1U) -#define SDIF_RST_N_CARD_RESET_SHIFT (0U) -#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK) -/*! @} */ - -/*! @name BMOD - Bus Mode register */ -/*! @{ */ -#define SDIF_BMOD_SWR_MASK (0x1U) -#define SDIF_BMOD_SWR_SHIFT (0U) -#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK) -#define SDIF_BMOD_FB_MASK (0x2U) -#define SDIF_BMOD_FB_SHIFT (1U) -#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK) -#define SDIF_BMOD_DSL_MASK (0x7CU) -#define SDIF_BMOD_DSL_SHIFT (2U) -#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK) -#define SDIF_BMOD_DE_MASK (0x80U) -#define SDIF_BMOD_DE_SHIFT (7U) -#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK) -#define SDIF_BMOD_PBL_MASK (0x700U) -#define SDIF_BMOD_PBL_SHIFT (8U) -#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK) -/*! @} */ - -/*! @name PLDMND - Poll Demand register */ -/*! @{ */ -#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU) -#define SDIF_PLDMND_PD_SHIFT (0U) -#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK) -/*! @} */ - -/*! @name DBADDR - Descriptor List Base Address register */ -/*! @{ */ -#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU) -#define SDIF_DBADDR_SDL_SHIFT (0U) -#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK) -/*! @} */ - -/*! @name IDSTS - Internal DMAC Status register */ -/*! @{ */ -#define SDIF_IDSTS_TI_MASK (0x1U) -#define SDIF_IDSTS_TI_SHIFT (0U) -#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK) -#define SDIF_IDSTS_RI_MASK (0x2U) -#define SDIF_IDSTS_RI_SHIFT (1U) -#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK) -#define SDIF_IDSTS_FBE_MASK (0x4U) -#define SDIF_IDSTS_FBE_SHIFT (2U) -#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK) -#define SDIF_IDSTS_DU_MASK (0x10U) -#define SDIF_IDSTS_DU_SHIFT (4U) -#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK) -#define SDIF_IDSTS_CES_MASK (0x20U) -#define SDIF_IDSTS_CES_SHIFT (5U) -#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK) -#define SDIF_IDSTS_NIS_MASK (0x100U) -#define SDIF_IDSTS_NIS_SHIFT (8U) -#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK) -#define SDIF_IDSTS_AIS_MASK (0x200U) -#define SDIF_IDSTS_AIS_SHIFT (9U) -#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK) -#define SDIF_IDSTS_EB_MASK (0x1C00U) -#define SDIF_IDSTS_EB_SHIFT (10U) -#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK) -#define SDIF_IDSTS_FSM_MASK (0x1E000U) -#define SDIF_IDSTS_FSM_SHIFT (13U) -#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK) -/*! @} */ - -/*! @name IDINTEN - Internal DMAC Interrupt Enable register */ -/*! @{ */ -#define SDIF_IDINTEN_TI_MASK (0x1U) -#define SDIF_IDINTEN_TI_SHIFT (0U) -#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK) -#define SDIF_IDINTEN_RI_MASK (0x2U) -#define SDIF_IDINTEN_RI_SHIFT (1U) -#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK) -#define SDIF_IDINTEN_FBE_MASK (0x4U) -#define SDIF_IDINTEN_FBE_SHIFT (2U) -#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK) -#define SDIF_IDINTEN_DU_MASK (0x10U) -#define SDIF_IDINTEN_DU_SHIFT (4U) -#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK) -#define SDIF_IDINTEN_CES_MASK (0x20U) -#define SDIF_IDINTEN_CES_SHIFT (5U) -#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK) -#define SDIF_IDINTEN_NIS_MASK (0x100U) -#define SDIF_IDINTEN_NIS_SHIFT (8U) -#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK) -#define SDIF_IDINTEN_AIS_MASK (0x200U) -#define SDIF_IDINTEN_AIS_SHIFT (9U) -#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK) -/*! @} */ - -/*! @name DSCADDR - Current Host Descriptor Address register */ -/*! @{ */ -#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU) -#define SDIF_DSCADDR_HDA_SHIFT (0U) -#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK) -/*! @} */ - -/*! @name BUFADDR - Current Buffer Descriptor Address register */ -/*! @{ */ -#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU) -#define SDIF_BUFADDR_HBA_SHIFT (0U) -#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK) -/*! @} */ - -/*! @name CARDTHRCTL - Card Threshold Control */ -/*! @{ */ -#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U) -#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U) -#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK) -#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U) -#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U) -#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK) -#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U) -#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U) -#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK) -/*! @} */ - -/*! @name BACKENDPWR - Power control */ -/*! @{ */ -#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U) -#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U) -#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK) -/*! @} */ - -/*! @name FIFO - SDIF FIFO */ -/*! @{ */ -#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU) -#define SDIF_FIFO_DATA_SHIFT (0U) -#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK) -/*! @} */ - -/* The count of SDIF_FIFO */ -#define SDIF_FIFO_COUNT (64U) - - -/*! - * @} - */ /* end of group SDIF_Register_Masks */ - - -/* SDIF - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral SDIF base address */ - #define SDIF_BASE (0x5009B000u) - /** Peripheral SDIF base address */ - #define SDIF_BASE_NS (0x4009B000u) - /** Peripheral SDIF base pointer */ - #define SDIF ((SDIF_Type *)SDIF_BASE) - /** Peripheral SDIF base pointer */ - #define SDIF_NS ((SDIF_Type *)SDIF_BASE_NS) - /** Array initializer of SDIF peripheral base addresses */ - #define SDIF_BASE_ADDRS { SDIF_BASE } - /** Array initializer of SDIF peripheral base pointers */ - #define SDIF_BASE_PTRS { SDIF } - /** Array initializer of SDIF peripheral base addresses */ - #define SDIF_BASE_ADDRS_NS { SDIF_BASE_NS } - /** Array initializer of SDIF peripheral base pointers */ - #define SDIF_BASE_PTRS_NS { SDIF_NS } -#else - /** Peripheral SDIF base address */ - #define SDIF_BASE (0x4009B000u) - /** Peripheral SDIF base pointer */ - #define SDIF ((SDIF_Type *)SDIF_BASE) - /** Array initializer of SDIF peripheral base addresses */ - #define SDIF_BASE_ADDRS { SDIF_BASE } - /** Array initializer of SDIF peripheral base pointers */ - #define SDIF_BASE_PTRS { SDIF } -#endif -/** Interrupt vectors for the SDIF peripheral type */ -#define SDIF_IRQS { SDIO_IRQn } - -/*! - * @} - */ /* end of group SDIF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer - * @{ - */ - -/** SPI - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[1024]; - __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ - __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ - __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ - __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ - __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ - __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ - uint8_t RESERVED_2[2516]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_6[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_7[440]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} SPI_Type; - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/*! @name CFG - SPI Configuration register */ -/*! @{ */ -#define SPI_CFG_ENABLE_MASK (0x1U) -#define SPI_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - SPI enable. - * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. - * 0b1..Enabled. The SPI is enabled for operation. - */ -#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) -#define SPI_CFG_MASTER_MASK (0x4U) -#define SPI_CFG_MASTER_SHIFT (2U) -/*! MASTER - Master mode select. - * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. - * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. - */ -#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) -#define SPI_CFG_LSBF_MASK (0x8U) -#define SPI_CFG_LSBF_SHIFT (3U) -/*! LSBF - LSB First mode enable. - * 0b0..Standard. Data is transmitted and received in standard MSB first order. - * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). - */ -#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) -#define SPI_CFG_CPHA_MASK (0x10U) -#define SPI_CFG_CPHA_SHIFT (4U) -/*! CPHA - Clock Phase select. - * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge. - * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge. - */ -#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) -#define SPI_CFG_CPOL_MASK (0x20U) -#define SPI_CFG_CPOL_SHIFT (5U) -/*! CPOL - Clock Polarity select. - * 0b0..Low. The rest state of the clock (between transfers) is low. - * 0b1..High. The rest state of the clock (between transfers) is high. - */ -#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) -#define SPI_CFG_LOOP_MASK (0x80U) -#define SPI_CFG_LOOP_SHIFT (7U) -/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. - * 0b0..Disabled. - * 0b1..Enabled. - */ -#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) -#define SPI_CFG_SPOL0_MASK (0x100U) -#define SPI_CFG_SPOL0_SHIFT (8U) -/*! SPOL0 - SSEL0 Polarity select. - * 0b0..Low. The SSEL0 pin is active low. - * 0b1..High. The SSEL0 pin is active high. - */ -#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) -#define SPI_CFG_SPOL1_MASK (0x200U) -#define SPI_CFG_SPOL1_SHIFT (9U) -/*! SPOL1 - SSEL1 Polarity select. - * 0b0..Low. The SSEL1 pin is active low. - * 0b1..High. The SSEL1 pin is active high. - */ -#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) -#define SPI_CFG_SPOL2_MASK (0x400U) -#define SPI_CFG_SPOL2_SHIFT (10U) -/*! SPOL2 - SSEL2 Polarity select. - * 0b0..Low. The SSEL2 pin is active low. - * 0b1..High. The SSEL2 pin is active high. - */ -#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) -#define SPI_CFG_SPOL3_MASK (0x800U) -#define SPI_CFG_SPOL3_SHIFT (11U) -/*! SPOL3 - SSEL3 Polarity select. - * 0b0..Low. The SSEL3 pin is active low. - * 0b1..High. The SSEL3 pin is active high. - */ -#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) -/*! @} */ - -/*! @name DLY - SPI Delay register */ -/*! @{ */ -#define SPI_DLY_PRE_DELAY_MASK (0xFU) -#define SPI_DLY_PRE_DELAY_SHIFT (0U) -#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) -#define SPI_DLY_POST_DELAY_MASK (0xF0U) -#define SPI_DLY_POST_DELAY_SHIFT (4U) -#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) -#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) -#define SPI_DLY_FRAME_DELAY_SHIFT (8U) -#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) -#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) -#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) -#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) -/*! @} */ - -/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ -/*! @{ */ -#define SPI_STAT_SSA_MASK (0x10U) -#define SPI_STAT_SSA_SHIFT (4U) -#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) -#define SPI_STAT_SSD_MASK (0x20U) -#define SPI_STAT_SSD_SHIFT (5U) -#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) -#define SPI_STAT_STALLED_MASK (0x40U) -#define SPI_STAT_STALLED_SHIFT (6U) -#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) -#define SPI_STAT_ENDTRANSFER_MASK (0x80U) -#define SPI_STAT_ENDTRANSFER_SHIFT (7U) -#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) -#define SPI_STAT_MSTIDLE_MASK (0x100U) -#define SPI_STAT_MSTIDLE_SHIFT (8U) -#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ -#define SPI_INTENSET_SSAEN_MASK (0x10U) -#define SPI_INTENSET_SSAEN_SHIFT (4U) -/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. - * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. - * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. - */ -#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) -#define SPI_INTENSET_SSDEN_MASK (0x20U) -#define SPI_INTENSET_SSDEN_SHIFT (5U) -/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. - * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. - * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. - */ -#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) -#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) -#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) -/*! MSTIDLEEN - Master idle interrupt enable. - * 0b0..No interrupt will be generated when the SPI master function is idle. - * 0b1..An interrupt will be generated when the SPI master function is fully idle. - */ -#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) -/*! @} */ - -/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ -/*! @{ */ -#define SPI_INTENCLR_SSAEN_MASK (0x10U) -#define SPI_INTENCLR_SSAEN_SHIFT (4U) -#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) -#define SPI_INTENCLR_SSDEN_MASK (0x20U) -#define SPI_INTENCLR_SSDEN_SHIFT (5U) -#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) -#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) -#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) -#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) -/*! @} */ - -/*! @name DIV - SPI clock Divider */ -/*! @{ */ -#define SPI_DIV_DIVVAL_MASK (0xFFFFU) -#define SPI_DIV_DIVVAL_SHIFT (0U) -#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - SPI Interrupt Status */ -/*! @{ */ -#define SPI_INTSTAT_SSA_MASK (0x10U) -#define SPI_INTSTAT_SSA_SHIFT (4U) -#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) -#define SPI_INTSTAT_SSD_MASK (0x20U) -#define SPI_INTSTAT_SSD_SHIFT (5U) -#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) -#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) -#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) -#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ -#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) -#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) -#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) -#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) -#define SPI_FIFOCFG_SIZE_MASK (0x30U) -#define SPI_FIFOCFG_SIZE_SHIFT (4U) -#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) -#define SPI_FIFOCFG_DMATX_MASK (0x1000U) -#define SPI_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) -#define SPI_FIFOCFG_DMARX_MASK (0x2000U) -#define SPI_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) -#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) -#define SPI_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) -#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) -#define SPI_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) -#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) -#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) -#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) -#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) -#define SPI_FIFOCFG_POPDBG_MASK (0x40000U) -#define SPI_FIFOCFG_POPDBG_SHIFT (18U) -/*! POPDBG - Pop FIFO for debug reads. - * 0b0..Debug reads of the FIFO do not pop the FIFO. - * 0b1..A debug read will cause the FIFO to pop. - */ -#define SPI_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ -#define SPI_FIFOSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOSTAT_TXERR_SHIFT (0U) -#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) -#define SPI_FIFOSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOSTAT_RXERR_SHIFT (1U) -#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) -#define SPI_FIFOSTAT_PERINT_MASK (0x8U) -#define SPI_FIFOSTAT_PERINT_SHIFT (3U) -#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) -#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) -#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) -#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) -#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) -#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) -#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) -#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) -#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) -#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) -#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ -#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) -#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) -#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) -#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) -#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) -#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) -#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ -#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) -#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) -#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) -#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) -#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - */ -#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) -#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ -#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) -#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) -#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) -#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) -#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) -#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) -#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) -#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ -#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) -#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) -#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) -#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) -#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) -#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) -#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) -#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) -#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ -#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) -#define SPI_FIFOWR_TXDATA_SHIFT (0U) -#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) -#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) -#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) -/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL0 asserted. - * 0b1..SSEL0 not asserted. - */ -#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) -#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) -#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) -/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL1 asserted. - * 0b1..SSEL1 not asserted. - */ -#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) -#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) -#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) -/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL2 asserted. - * 0b1..SSEL2 not asserted. - */ -#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) -#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) -#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) -/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL3 asserted. - * 0b1..SSEL3 not asserted. - */ -#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) -#define SPI_FIFOWR_EOT_MASK (0x100000U) -#define SPI_FIFOWR_EOT_SHIFT (20U) -/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register. - * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. - * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. - */ -#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) -#define SPI_FIFOWR_EOF_MASK (0x200000U) -#define SPI_FIFOWR_EOF_SHIFT (21U) -/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. - * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. - * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted. - */ -#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) -#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) -#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) -/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA. - * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received. - * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. - */ -#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) -#define SPI_FIFOWR_LEN_MASK (0xF000000U) -#define SPI_FIFOWR_LEN_SHIFT (24U) -#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ -#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORD_RXDATA_SHIFT (0U) -#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) -#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) -#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) -#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) -#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) -#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) -#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) -#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) -#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) -#define SPI_FIFORD_SOT_MASK (0x100000U) -#define SPI_FIFORD_SOT_SHIFT (20U) -#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ -#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) -#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) -#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) -#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) -#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) -#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) -#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) -#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) -#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ -#define SPI_ID_APERTURE_MASK (0xFFU) -#define SPI_ID_APERTURE_SHIFT (0U) -#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) -#define SPI_ID_MINOR_REV_MASK (0xF00U) -#define SPI_ID_MINOR_REV_SHIFT (8U) -#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) -#define SPI_ID_MAJOR_REV_MASK (0xF000U) -#define SPI_ID_MAJOR_REV_SHIFT (12U) -#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) -#define SPI_ID_ID_MASK (0xFFFF0000U) -#define SPI_ID_ID_SHIFT (16U) -#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SPI_Register_Masks */ - - -/* SPI - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral SPI0 base address */ - #define SPI0_BASE (0x50086000u) - /** Peripheral SPI0 base address */ - #define SPI0_BASE_NS (0x40086000u) - /** Peripheral SPI0 base pointer */ - #define SPI0 ((SPI_Type *)SPI0_BASE) - /** Peripheral SPI0 base pointer */ - #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) - /** Peripheral SPI1 base address */ - #define SPI1_BASE (0x50087000u) - /** Peripheral SPI1 base address */ - #define SPI1_BASE_NS (0x40087000u) - /** Peripheral SPI1 base pointer */ - #define SPI1 ((SPI_Type *)SPI1_BASE) - /** Peripheral SPI1 base pointer */ - #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) - /** Peripheral SPI2 base address */ - #define SPI2_BASE (0x50088000u) - /** Peripheral SPI2 base address */ - #define SPI2_BASE_NS (0x40088000u) - /** Peripheral SPI2 base pointer */ - #define SPI2 ((SPI_Type *)SPI2_BASE) - /** Peripheral SPI2 base pointer */ - #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS) - /** Peripheral SPI3 base address */ - #define SPI3_BASE (0x50089000u) - /** Peripheral SPI3 base address */ - #define SPI3_BASE_NS (0x40089000u) - /** Peripheral SPI3 base pointer */ - #define SPI3 ((SPI_Type *)SPI3_BASE) - /** Peripheral SPI3 base pointer */ - #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) - /** Peripheral SPI4 base address */ - #define SPI4_BASE (0x5008A000u) - /** Peripheral SPI4 base address */ - #define SPI4_BASE_NS (0x4008A000u) - /** Peripheral SPI4 base pointer */ - #define SPI4 ((SPI_Type *)SPI4_BASE) - /** Peripheral SPI4 base pointer */ - #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) - /** Peripheral SPI5 base address */ - #define SPI5_BASE (0x50096000u) - /** Peripheral SPI5 base address */ - #define SPI5_BASE_NS (0x40096000u) - /** Peripheral SPI5 base pointer */ - #define SPI5 ((SPI_Type *)SPI5_BASE) - /** Peripheral SPI5 base pointer */ - #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS) - /** Peripheral SPI6 base address */ - #define SPI6_BASE (0x50097000u) - /** Peripheral SPI6 base address */ - #define SPI6_BASE_NS (0x40097000u) - /** Peripheral SPI6 base pointer */ - #define SPI6 ((SPI_Type *)SPI6_BASE) - /** Peripheral SPI6 base pointer */ - #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) - /** Peripheral SPI7 base address */ - #define SPI7_BASE (0x50098000u) - /** Peripheral SPI7 base address */ - #define SPI7_BASE_NS (0x40098000u) - /** Peripheral SPI7 base pointer */ - #define SPI7 ((SPI_Type *)SPI7_BASE) - /** Peripheral SPI7 base pointer */ - #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) - /** Peripheral SPI8 base address */ - #define SPI8_BASE (0x5009F000u) - /** Peripheral SPI8 base address */ - #define SPI8_BASE_NS (0x4009F000u) - /** Peripheral SPI8 base pointer */ - #define SPI8 ((SPI_Type *)SPI8_BASE) - /** Peripheral SPI8 base pointer */ - #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS } -#else - /** Peripheral SPI0 base address */ - #define SPI0_BASE (0x40086000u) - /** Peripheral SPI0 base pointer */ - #define SPI0 ((SPI_Type *)SPI0_BASE) - /** Peripheral SPI1 base address */ - #define SPI1_BASE (0x40087000u) - /** Peripheral SPI1 base pointer */ - #define SPI1 ((SPI_Type *)SPI1_BASE) - /** Peripheral SPI2 base address */ - #define SPI2_BASE (0x40088000u) - /** Peripheral SPI2 base pointer */ - #define SPI2 ((SPI_Type *)SPI2_BASE) - /** Peripheral SPI3 base address */ - #define SPI3_BASE (0x40089000u) - /** Peripheral SPI3 base pointer */ - #define SPI3 ((SPI_Type *)SPI3_BASE) - /** Peripheral SPI4 base address */ - #define SPI4_BASE (0x4008A000u) - /** Peripheral SPI4 base pointer */ - #define SPI4 ((SPI_Type *)SPI4_BASE) - /** Peripheral SPI5 base address */ - #define SPI5_BASE (0x40096000u) - /** Peripheral SPI5 base pointer */ - #define SPI5 ((SPI_Type *)SPI5_BASE) - /** Peripheral SPI6 base address */ - #define SPI6_BASE (0x40097000u) - /** Peripheral SPI6 base pointer */ - #define SPI6 ((SPI_Type *)SPI6_BASE) - /** Peripheral SPI7 base address */ - #define SPI7_BASE (0x40098000u) - /** Peripheral SPI7 base pointer */ - #define SPI7 ((SPI_Type *)SPI7_BASE) - /** Peripheral SPI8 base address */ - #define SPI8_BASE (0x4009F000u) - /** Peripheral SPI8 base pointer */ - #define SPI8 ((SPI_Type *)SPI8_BASE) - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } -#endif -/** Interrupt vectors for the SPI peripheral type */ -#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, LSPI_HS_IRQn } - -/*! - * @} - */ /* end of group SPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer - * @{ - */ - -/** SYSCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */ - uint8_t RESERVED_1[36]; - __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ - __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ - __IO uint32_t CPU1TCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */ - uint8_t RESERVED_2[4]; - __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ - uint8_t RESERVED_3[180]; - union { /* offset: 0x100 */ - struct { /* offset: 0x100 */ - __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */ - __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */ - __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */ - } PRESETCTRL; - __IO uint32_t PRESETCTRLX[3]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */ - }; - uint8_t RESERVED_4[20]; - __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */ - uint8_t RESERVED_5[20]; - __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset contro clearl register, array offset: 0x140, array step: 0x4 */ - uint8_t RESERVED_6[20]; - __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */ - uint8_t RESERVED_7[156]; - union { /* offset: 0x200 */ - struct { /* offset: 0x200 */ - __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */ - __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */ - __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */ - } AHBCLKCTRL; - __IO uint32_t AHBCLKCTRLX[3]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */ - }; - uint8_t RESERVED_8[20]; - __IO uint32_t AHBCLKCTRLSET[3]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */ - uint8_t RESERVED_9[20]; - __IO uint32_t AHBCLKCTRLCLR[3]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_10[20]; - union { /* offset: 0x260 */ - struct { /* offset: 0x260 */ - __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */ - __IO uint32_t SYSTICKCLKSEL1; /**< System Tick Timer for CPU1 source select, offset: 0x264 */ - } SYSTICKCLKSEL; - __IO uint32_t SYSTICKCLKSELX[2]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */ - }; - __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */ - union { /* offset: 0x26C */ - struct { /* offset: 0x26C */ - __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */ - __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */ - __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */ - __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */ - __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */ - } CTIMERCLKSEL; - __IO uint32_t CTIMERCLKSELX[5]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */ - }; - __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */ - __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */ - __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */ - uint8_t RESERVED_11[4]; - __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */ - __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */ - uint8_t RESERVED_12[12]; - __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ - __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ - __IO uint32_t USB1CLKSEL; /**< HS USB clock source select - NOT USED, offset: 0x2AC */ - union { /* offset: 0x2B0 */ - struct { /* offset: 0x2B0 */ - __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */ - __IO uint32_t FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */ - __IO uint32_t FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */ - __IO uint32_t FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */ - __IO uint32_t FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */ - __IO uint32_t FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */ - __IO uint32_t FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */ - __IO uint32_t FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */ - } FCCLKSEL; - __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */ - }; - __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */ - uint8_t RESERVED_13[12]; - __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ - uint8_t RESERVED_14[12]; - __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ - uint8_t RESERVED_15[4]; - __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ - uint8_t RESERVED_16[4]; - __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */ - __IO uint32_t SYSTICKCLKDIV1; /**< System Tick Timer divider for CPU1, offset: 0x304 */ - __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ - uint8_t RESERVED_17[20]; - union { /* offset: 0x320 */ - struct { /* offset: 0x320 */ - __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */ - __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */ - __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */ - __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */ - __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */ - __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */ - __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */ - __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */ - } FLEXFRGCTRL; - __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */ - }; - uint8_t RESERVED_18[64]; - __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ - __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ - __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ - __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ - uint8_t RESERVED_19[4]; - __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ - __IO uint32_t USB0CLKDIV; /**< USB0 Clock divider, offset: 0x398 */ - uint8_t RESERVED_20[16]; - __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ - uint8_t RESERVED_21[4]; - __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ - uint8_t RESERVED_22[4]; - __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ - uint8_t RESERVED_23[4]; - __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */ - uint8_t RESERVED_24[52]; - __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */ - __IO uint32_t FMCCR; /**< FMC configuration register - INTERNAL USE ONLY, offset: 0x400 */ - uint8_t RESERVED_25[8]; - __IO uint32_t USB0CLKCTRL; /**< USB0 clock control, offset: 0x40C */ - __I uint32_t USB0CLKSTAT; /**< USB0 clock status, offset: 0x410 */ - uint8_t RESERVED_26[8]; - __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */ - __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ - __IO uint32_t USB1CLKCTRL; /**< USB1 clock control, offset: 0x424 */ - __I uint32_t USB1CLKSTAT; /**< USB1 clock status, offset: 0x428 */ - uint8_t RESERVED_27[36]; - __IO uint32_t FLASHBANKENABLE; /**< Flash Banks control, offset: 0x450 */ - uint8_t RESERVED_28[12]; - __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */ - uint8_t RESERVED_29[252]; - __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ - __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */ - __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */ - __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */ - __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */ - uint8_t RESERVED_30[12]; - __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */ - __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */ - __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */ - __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ - __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */ - __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */ - uint8_t RESERVED_31[52]; - __IO uint32_t EFUSECLKCTRL; /**< eFUSE controller clock enable, offset: 0x5CC */ - uint8_t RESERVED_32[176]; - __IO uint32_t STARTER[2]; /**< Start logic wake-up enable register, array offset: 0x680, array step: 0x4 */ - uint8_t RESERVED_33[24]; - __O uint32_t STARTERSET[2]; /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */ - uint8_t RESERVED_34[24]; - __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTER, array offset: 0x6C0, array step: 0x4 */ - uint8_t RESERVED_35[184]; - __IO uint32_t HARDWARESLEEP; /**< Hardware Sleep control, offset: 0x780 */ - uint8_t RESERVED_36[124]; - __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ - __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ - __IO uint32_t CPSTACK; /**< Coprocessor Stack Address, offset: 0x808 */ - __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */ - uint8_t RESERVED_37[240]; - __IO uint32_t DICE_REG0; /**< Composite Device Identifier, offset: 0x900 */ - __IO uint32_t DICE_REG1; /**< Composite Device Identifier, offset: 0x904 */ - __IO uint32_t DICE_REG2; /**< Composite Device Identifier, offset: 0x908 */ - __IO uint32_t DICE_REG3; /**< Composite Device Identifier, offset: 0x90C */ - __IO uint32_t DICE_REG4; /**< Composite Device Identifier, offset: 0x910 */ - __IO uint32_t DICE_REG5; /**< Composite Device Identifier, offset: 0x914 */ - __IO uint32_t DICE_REG6; /**< Composite Device Identifier, offset: 0x918 */ - __IO uint32_t DICE_REG7; /**< Composite Device Identifier, offset: 0x91C */ - uint8_t RESERVED_38[248]; - __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */ - uint8_t RESERVED_39[244]; - __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ - __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ - uint8_t RESERVED_40[748]; - __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ - __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */ - uint8_t RESERVED_41[404]; - __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers -- FOR INTERNAl USE ONLY, offset: 0xFA0 */ - __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY, offset: 0xFA4 */ - __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY, offset: 0xFA8 */ - uint8_t RESERVED_42[4]; - __O uint32_t CODESECURITYPROTTEST; /**< Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY, offset: 0xFB0 */ - __O uint32_t CODESECURITYPROTCPU0; /**< Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY, offset: 0xFB4 */ - __O uint32_t CODESECURITYPROTCPU1; /**< Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY, offset: 0xFB8 */ - __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY, offset: 0xFBC */ - __IO uint32_t DEBUG_AUTH_SCRATCH; /**< Debug authentication scratch registers -- FOR INTERNAL USE ONLY, offset: 0xFC0 */ - uint8_t RESERVED_43[16]; - __IO uint32_t CPUCFG; /**< CPUs configuration register, offset: 0xFD4 */ - uint8_t RESERVED_44[20]; - __IO uint32_t PERIPHENCFG; /**< peripheral enable configuration -- FOR INTERNAL USE ONLY, offset: 0xFEC */ - uint8_t RESERVED_45[8]; - __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ - __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ -} SYSCON_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Register_Masks SYSCON Register Masks - * @{ - */ - -/*! @name MEMORYREMAP - Memory Remap control register */ -/*! @{ */ -#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) -#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) -/*! MAP - Select the location of the vector table :. - * 0b00..Vector Table in ROM. - * 0b01..Vector Table in RAM. - * 0b10..Vector Table in Flash. - * 0b11..Vector Table in Flash. - */ -#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK) -/*! @} */ - -/*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */ -/*! @{ */ -#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_MASK (0x3U) -#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_SHIFT (0U) -#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_MASK) -#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_MASK (0xCU) -#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_SHIFT (2U) -#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_MASK) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_MASK (0x30U) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_SHIFT (4U) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_MASK) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_MASK (0xC0U) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_SHIFT (6U) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_MASK) -#define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0x300U) -#define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (8U) -#define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK) -#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U) -#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U) -#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK (0x3000U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT (12U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK (0xC000U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT (14U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK) -#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U) -#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U) -#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK) -#define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U) -#define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U) -#define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK) -#define SYSCON_AHBMATPRIO_PRI_SHA2_MASK (0x300000U) -#define SYSCON_AHBMATPRIO_PRI_SHA2_SHIFT (20U) -#define SYSCON_AHBMATPRIO_PRI_SHA2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SHA2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SHA2_MASK) -#define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC00000U) -#define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (22U) -#define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) -#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U) -#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U) -#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) -/*! @} */ - -/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ -/*! @{ */ -#define SYSCON_CPU0STCKCAL_CAL_MASK (0xFFFFFFU) -#define SYSCON_CPU0STCKCAL_CAL_SHIFT (0U) -#define SYSCON_CPU0STCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_CAL_SHIFT)) & SYSCON_CPU0STCKCAL_CAL_MASK) -#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) -#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) -#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) -#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ -/*! @{ */ -#define SYSCON_CPU0NSTCKCAL_CAL_MASK (0xFFFFFFU) -#define SYSCON_CPU0NSTCKCAL_CAL_SHIFT (0U) -#define SYSCON_CPU0NSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_CAL_SHIFT)) & SYSCON_CPU0NSTCKCAL_CAL_MASK) -#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) -#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) -#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) -#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name CPU1TCKCAL - System tick calibration for CPU1 */ -/*! @{ */ -#define SYSCON_CPU1TCKCAL_CAL_MASK (0xFFFFFFU) -#define SYSCON_CPU1TCKCAL_CAL_SHIFT (0U) -#define SYSCON_CPU1TCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_CAL_SHIFT)) & SYSCON_CPU1TCKCAL_CAL_MASK) -#define SYSCON_CPU1TCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU1TCKCAL_SKEW_SHIFT (24U) -#define SYSCON_CPU1TCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_SKEW_SHIFT)) & SYSCON_CPU1TCKCAL_SKEW_MASK) -#define SYSCON_CPU1TCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU1TCKCAL_NOREF_SHIFT (25U) -#define SYSCON_CPU1TCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_NOREF_SHIFT)) & SYSCON_CPU1TCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name NMISRC - NMI Source Select */ -/*! @{ */ -#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) -#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) -#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) -#define SYSCON_NMISRC_IRQCPU1_MASK (0x3F00U) -#define SYSCON_NMISRC_IRQCPU1_SHIFT (8U) -#define SYSCON_NMISRC_IRQCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK) -#define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U) -#define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U) -#define SYSCON_NMISRC_NMIENCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK) -#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) -#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) -#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) -/*! @} */ - -/*! @name PRESETCTRL0 - Peripheral reset control 0 */ -/*! @{ */ -#define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U) -/*! ROM_RST - ROM reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK) -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) -/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) -/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U) -/*! SRAM_CTRL3_RST - SRAM Controller 3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK) -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U) -/*! SRAM_CTRL4_RST - SRAM Controller 4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK) -#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) -/*! FLASH_RST - Flash controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) -#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) -/*! FMC_RST - FMC controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) -#define SYSCON_PRESETCTRL0_MUX0_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL0_MUX0_RST_SHIFT (11U) -/*! MUX0_RST - Input Mux 0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_MUX0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX0_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX0_RST_MASK) -#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) -/*! IOCON_RST - I/O controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) -#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) -/*! GPIO0_RST - GPIO0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) -#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) -/*! GPIO1_RST - GPIO1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) -#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U) -/*! GPIO2_RST - GPIO2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) -#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U) -/*! GPIO3_RST - GPIO3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) -#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) -/*! PINT_RST - Pin interrupt (PINT) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) -#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) -/*! GINT_RST - Group interrupt (GINT) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) -#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) -/*! DMA0_RST - DMA0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) -#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) -/*! CRCGEN_RST - CRCGEN reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) -#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) -/*! WWDT_RST - Watchdog Timer reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) -#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) -#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) -/*! RTC_RST - Real Time Clock (RTC) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) -#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) -/*! MAILBOX_RST - Inter CPU communication Mailbox reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) -#define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U) -/*! ADC_RST - ADC reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRL1 - Peripheral reset control 1 */ -/*! @{ */ -#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) -#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) -/*! MRT_RST - MRT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) -#define SYSCON_PRESETCTRL1_OSTIMER0_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL1_OSTIMER0_RST_SHIFT (1U) -/*! OSTIMER0_RST - OS Timer 0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_OSTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER0_RST_MASK) -#define SYSCON_PRESETCTRL1_SCT0_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL1_SCT0_RST_SHIFT (2U) -/*! SCT0_RST - SCT0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT0_RST_MASK) -#define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT (6U) -/*! SCTIPU_RST - SCTIPU reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_SCTIPU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK) -#define SYSCON_PRESETCTRL1_UTICK0_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL1_UTICK0_RST_SHIFT (10U) -/*! UTICK0_RST - UTICK0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK0_RST_MASK) -#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) -/*! FC0_RST - FC0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) -#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) -/*! FC1_RST - FC1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) -#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) -/*! FC2_RST - FC2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) -#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) -/*! FC3_RST - FC3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) -#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) -/*! FC4_RST - FC4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) -#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) -/*! FC5_RST - FC5 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) -#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) -/*! FC6_RST - FC6 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) -#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) -/*! FC7_RST - FC7 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) -#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) -/*! TIMER2_RST - Timer 2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) -#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) -#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) -/*! USB0_DEV_RST - USB0 DEV reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) -#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) -/*! TIMER0_RST - Timer 0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) -#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) -/*! TIMER1_RST - Timer 1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) -#define SYSCON_PRESETCTRL1_PVT_RST_MASK (0x10000000U) -#define SYSCON_PRESETCTRL1_PVT_RST_SHIFT (28U) -/*! PVT_RST - PVT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_PVT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_PVT_RST_SHIFT)) & SYSCON_PRESETCTRL1_PVT_RST_MASK) -#define SYSCON_PRESETCTRL1_EZHA_RST_MASK (0x40000000U) -#define SYSCON_PRESETCTRL1_EZHA_RST_SHIFT (30U) -/*! EZHA_RST - EZH a reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_EZHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHA_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHA_RST_MASK) -#define SYSCON_PRESETCTRL1_EZHB_RST_MASK (0x80000000U) -#define SYSCON_PRESETCTRL1_EZHB_RST_SHIFT (31U) -/*! EZHB_RST - EZH b reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_EZHB_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHB_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHB_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRL2 - Peripheral reset control 2 */ -/*! @{ */ -#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) -/*! DMA1_RST - DMA1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) -#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) -/*! COMP_RST - Comparator reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) -#define SYSCON_PRESETCTRL2_SDIO_RST_MASK (0x8U) -#define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT (3U) -/*! SDIO_RST - SDIO reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK) -#define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U) -/*! USB1_HOST_RST - USB1 Host reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK) -#define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U) -#define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U) -/*! USB1_DEV_RST - USB1 dev reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK) -#define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U) -/*! USB1_RAM_RST - USB1 RAM reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK) -#define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U) -/*! USB1_PHY_RST - USB1 PHY reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK) -#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) -/*! FREQME_RST - Frequency meter reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) -#define SYSCON_PRESETCTRL2_GPIO4_RST_MASK (0x200U) -#define SYSCON_PRESETCTRL2_GPIO4_RST_SHIFT (9U) -/*! GPIO4_RST - GPIO4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO4_RST_MASK) -#define SYSCON_PRESETCTRL2_GPIO5_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL2_GPIO5_RST_SHIFT (10U) -/*! GPIO5_RST - GPIO5 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO5_RST_MASK) -#define SYSCON_PRESETCTRL2_OTP_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL2_OTP_RST_SHIFT (12U) -/*! OTP_RST - OTP reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_OTP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL2_OTP_RST_MASK) -#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) -/*! RNG_RST - RNG reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) -#define SYSCON_PRESETCTRL2_MUX1_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL2_MUX1_RST_SHIFT (14U) -/*! MUX1_RST - Peripheral Input Mux 1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_MUX1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_MUX1_RST_SHIFT)) & SYSCON_PRESETCTRL2_MUX1_RST_MASK) -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) -/*! USB0_HOSTM_RST - USB0 Host Master reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) -/*! USB0_HOSTS_RST - USB0 Host Slave reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) -#define SYSCON_PRESETCTRL2_HASH0_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL2_HASH0_RST_SHIFT (18U) -/*! HASH0_RST - HASH0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_HASH0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH0_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH0_RST_MASK) -#define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U) -/*! PQ_RST - Power Quad reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK) -#define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U) -/*! PLULUT_RST - PLU LUT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK) -#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) -/*! TIMER3_RST - Timer 3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) -#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) -/*! TIMER4_RST - Timer 4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) -#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) -#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) -/*! PUF_RST - PUF reset control reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) -#define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U) -#define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U) -/*! CASPER_RST - Casper reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK) -#define SYSCON_PRESETCTRL2_CAPT0_RST_MASK (0x2000000U) -#define SYSCON_PRESETCTRL2_CAPT0_RST_SHIFT (25U) -/*! CAPT0_RST - CAPT0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_CAPT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CAPT0_RST_SHIFT)) & SYSCON_PRESETCTRL2_CAPT0_RST_MASK) -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U) -/*! ANALOG_CTRL_RST - analog control reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK) -#define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U) -#define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U) -/*! HS_LSPI_RST - HS LSPI reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK) -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) -/*! GPIO_SEC_RST - GPIO secure reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) -/*! GPIO_SEC_INT_RST - GPIO secure int reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRLX - Peripheral reset control register */ -/*! @{ */ -#define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLX_DATA_SHIFT (0U) -#define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLX */ -#define SYSCON_PRESETCTRLX_COUNT (3U) - -/*! @name PRESETCTRLSET - Peripheral reset control set register */ -/*! @{ */ -#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) -#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLSET */ -#define SYSCON_PRESETCTRLSET_COUNT (3U) - -/*! @name PRESETCTRLCLR - Peripheral reset contro clearl register */ -/*! @{ */ -#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) -#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLCLR */ -#define SYSCON_PRESETCTRLCLR_COUNT (3U) - -/*! @name SWR_RESET - generate a software_reset */ -/*! @{ */ -#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) -#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) -/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. - * 0b01011010000000000000000000000001..Generate a software reset. - * 0b00000000000000000000000000000000..Bloc is not reset. - */ -#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL0 - AHB Clock control 0 */ -/*! @{ */ -#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) -#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) -/*! ROM - Enables the clock for the ROM. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) -/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) -/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U) -/*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U) -/*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK) -#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) -#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) -/*! FLASH - Enables the clock for the Flash controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) -#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) -#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) -/*! FMC - Enables the clock for the FMC controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) -#define SYSCON_AHBCLKCTRL0_MUX0_MASK (0x800U) -#define SYSCON_AHBCLKCTRL0_MUX0_SHIFT (11U) -/*! MUX0 - Enables the clock for the Input Mux 0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX0_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX0_MASK) -#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) -/*! IOCON - Enables the clock for the I/O controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) -#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) -/*! GPIO0 - Enables the clock for the GPIO0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) -#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) -/*! GPIO1 - Enables the clock for the GPIO1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) -#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U) -/*! GPIO2 - Enables the clock for the GPIO2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) -#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U) -/*! GPIO3 - Enables the clock for the GPIO3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) -#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) -/*! PINT - Enables the clock for the Pin interrupt (PINT). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) -#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) -/*! GINT - Enables the clock for the Group interrupt (GINT). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) -#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) -/*! DMA0 - Enables the clock for the DMA0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) -#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) -/*! CRCGEN - Enables the clock for the CRCGEN. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) -#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) -/*! WWDT - Enables the clock for the Watchdog Timer. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) -#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) -/*! RTC - Enables the clock for the Real Time Clock (RTC). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) -#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) -/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) -#define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U) -/*! ADC - Enables the clock for the ADC. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL1 - AHB Clock control 1 */ -/*! @{ */ -#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) -#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) -/*! MRT - Enables the clock for the MRT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) -#define SYSCON_AHBCLKCTRL1_OSTIMER0_MASK (0x2U) -#define SYSCON_AHBCLKCTRL1_OSTIMER0_SHIFT (1U) -/*! OSTIMER0 - Enables the clock for the OS Timer 0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER0_MASK) -#define SYSCON_AHBCLKCTRL1_SCT0_MASK (0x4U) -#define SYSCON_AHBCLKCTRL1_SCT0_SHIFT (2U) -/*! SCT0 - Enables the clock for the SCT0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT0_MASK) -#define SYSCON_AHBCLKCTRL1_SCTIPU_MASK (0x40U) -#define SYSCON_AHBCLKCTRL1_SCTIPU_SHIFT (6U) -/*! SCTIPU - Enables the clock for the SCTIPU. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_SCTIPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCTIPU_SHIFT)) & SYSCON_AHBCLKCTRL1_SCTIPU_MASK) -#define SYSCON_AHBCLKCTRL1_UTICK0_MASK (0x400U) -#define SYSCON_AHBCLKCTRL1_UTICK0_SHIFT (10U) -/*! UTICK0 - Enables the clock for the UTICK0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK0_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK0_MASK) -#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) -#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) -/*! FC0 - Enables the clock for the FC0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) -#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) -/*! FC1 - Enables the clock for the FC1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) -#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) -/*! FC2 - Enables the clock for the FC2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) -#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) -/*! FC3 - Enables the clock for the FC3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) -#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) -/*! FC4 - Enables the clock for the FC4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) -#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) -/*! FC5 - Enables the clock for the FC5. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) -#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) -/*! FC6 - Enables the clock for the FC6. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) -#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) -/*! FC7 - Enables the clock for the FC7. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) -#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) -/*! TIMER2 - Enables the clock for the Timer 2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) -#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) -#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) -/*! USB0_DEV - Enables the clock for the USB0 DEV. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) -#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) -/*! TIMER0 - Enables the clock for the Timer 0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) -#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) -/*! TIMER1 - Enables the clock for the Timer 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) -#define SYSCON_AHBCLKCTRL1_PVT_MASK (0x10000000U) -#define SYSCON_AHBCLKCTRL1_PVT_SHIFT (28U) -/*! PVT - Enables the clock for the PVT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_PVT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_PVT_SHIFT)) & SYSCON_AHBCLKCTRL1_PVT_MASK) -#define SYSCON_AHBCLKCTRL1_EZHA_MASK (0x40000000U) -#define SYSCON_AHBCLKCTRL1_EZHA_SHIFT (30U) -/*! EZHA - Enables the clock for the EZH a. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_EZHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHA_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHA_MASK) -#define SYSCON_AHBCLKCTRL1_EZHB_MASK (0x80000000U) -#define SYSCON_AHBCLKCTRL1_EZHB_SHIFT (31U) -/*! EZHB - Enables the clock for the EZH b. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_EZHB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHB_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHB_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL2 - AHB Clock control 2 */ -/*! @{ */ -#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) -#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) -/*! DMA1 - Enables the clock for the DMA1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) -#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) -#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) -/*! COMP - Enables the clock for the Comparator. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) -#define SYSCON_AHBCLKCTRL2_SDIO_MASK (0x8U) -#define SYSCON_AHBCLKCTRL2_SDIO_SHIFT (3U) -/*! SDIO - Enables the clock for the SDIO. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK) -#define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U) -#define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U) -/*! USB1_HOST - Enables the clock for the USB1 Host. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK) -#define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U) -#define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U) -/*! USB1_DEV - Enables the clock for the USB1 dev. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK) -#define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U) -#define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U) -/*! USB1_RAM - Enables the clock for the USB1 RAM. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK) -#define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U) -#define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U) -/*! USB1_PHY - Enables the clock for the USB1 PHY. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK) -#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) -#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) -/*! FREQME - Enables the clock for the Frequency meter. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) -#define SYSCON_AHBCLKCTRL2_GPIO4_MASK (0x200U) -#define SYSCON_AHBCLKCTRL2_GPIO4_SHIFT (9U) -/*! GPIO4 - Enables the clock for the GPIO4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO4_MASK) -#define SYSCON_AHBCLKCTRL2_GPIO5_MASK (0x400U) -#define SYSCON_AHBCLKCTRL2_GPIO5_SHIFT (10U) -/*! GPIO5 - Enables the clock for the GPIO5. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO5_MASK) -#define SYSCON_AHBCLKCTRL2_OTP_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL2_OTP_SHIFT (12U) -/*! OTP - Enables the clock for the OTP. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_OTP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_OTP_SHIFT)) & SYSCON_AHBCLKCTRL2_OTP_MASK) -#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) -/*! RNG - Enables the clock for the RNG. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) -#define SYSCON_AHBCLKCTRL2_MUX1_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL2_MUX1_SHIFT (14U) -/*! MUX1 - Enables the clock for the Peripheral Input Mux 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_MUX1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_MUX1_SHIFT)) & SYSCON_AHBCLKCTRL2_MUX1_MASK) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) -/*! USB0_HOSTM - Enables the clock for the USB0 Host Master. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) -/*! USB0_HOSTS - Enables the clock for the USB0 Host Slave. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) -#define SYSCON_AHBCLKCTRL2_HASH0_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL2_HASH0_SHIFT (18U) -/*! HASH0 - Enables the clock for the HASH0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_HASH0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH0_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH0_MASK) -#define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U) -/*! PQ - Enables the clock for the Power Quad. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK) -#define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U) -/*! PLULUT - Enables the clock for the PLU LUT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK) -#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) -/*! TIMER3 - Enables the clock for the Timer 3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) -#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) -/*! TIMER4 - Enables the clock for the Timer 4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) -#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) -/*! PUF - Enables the clock for the PUF reset control. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) -#define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U) -#define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U) -/*! CASPER - Enables the clock for the Casper. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK) -#define SYSCON_AHBCLKCTRL2_CAPT0_MASK (0x2000000U) -#define SYSCON_AHBCLKCTRL2_CAPT0_SHIFT (25U) -/*! CAPT0 - Enables the clock for the CAPT0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_CAPT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CAPT0_SHIFT)) & SYSCON_AHBCLKCTRL2_CAPT0_MASK) -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) -/*! ANALOG_CTRL - Enables the clock for the analog control. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) -#define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U) -#define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U) -/*! HS_LSPI - Enables the clock for the HS LSPI. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) -/*! GPIO_SEC - Enables the clock for the GPIO secure. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) -/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK) -/*! @} */ - -/*! @name AHBCLKCTRLX - Peripheral reset control register */ -/*! @{ */ -#define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U) -#define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLX */ -#define SYSCON_AHBCLKCTRLX_COUNT (3U) - -/*! @name AHBCLKCTRLSET - Peripheral reset control register */ -/*! @{ */ -#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) -#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLSET */ -#define SYSCON_AHBCLKCTRLSET_COUNT (3U) - -/*! @name AHBCLKCTRLCLR - Peripheral reset control register */ -/*! @{ */ -#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) -#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLCLR */ -#define SYSCON_AHBCLKCTRLCLR_COUNT (3U) - -/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ -/*! @{ */ -#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) -/*! SEL - System Tick Timer for CPU0 source select. - * 0b000..System Tick 0 divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKSEL1 - System Tick Timer for CPU1 source select */ -/*! @{ */ -#define SYSCON_SYSTICKCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT (0U) -/*! SEL - System Tick Timer for CPU1 source select. - * 0b000..System Tick 1 divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SYSTICKCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL1_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKSELX - Peripheral reset control register */ -/*! @{ */ -#define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U) -#define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_SYSTICKCLKSELX */ -#define SYSCON_SYSTICKCLKSELX_COUNT (2U) - -/*! @name TRACECLKSEL - Trace clock source select */ -/*! @{ */ -#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) -#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) -/*! SEL - Trace clock source select. - * 0b000..Trace divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */ -/*! @{ */ -#define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U) -/*! SEL - CTimer 0 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */ -/*! @{ */ -#define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U) -/*! SEL - CTimer 1 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */ -/*! @{ */ -#define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U) -/*! SEL - CTimer 2 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */ -/*! @{ */ -#define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U) -/*! SEL - CTimer 3 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */ -/*! @{ */ -#define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U) -/*! SEL - CTimer 4 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSELX - Peripheral reset control register */ -/*! @{ */ -#define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U) -#define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_CTIMERCLKSELX */ -#define SYSCON_CTIMERCLKSELX_COUNT (5U) - -/*! @name MAINCLKSELA - Main clock A source select */ -/*! @{ */ -#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) -#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) -/*! SEL - Main clock A source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) -/*! @} */ - -/*! @name MAINCLKSELB - Main clock source select */ -/*! @{ */ -#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) -#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) -/*! SEL - Main clock source select. - * 0b000..Main Clock A. - * 0b001..PLL0 clock. - * 0b010..PLL1 clock. - * 0b011..Oscillator 32 kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) -/*! @} */ - -/*! @name CLKOUTSEL - CLKOUT clock source select */ -/*! @{ */ -#define SYSCON_CLKOUTSEL_SEL_MASK (0x7U) -#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) -/*! SEL - CLKOUT clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..CLKIN clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..PLL1 clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) -/*! @} */ - -/*! @name PLL0CLKSEL - PLL0 clock source select */ -/*! @{ */ -#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) -#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) -/*! SEL - PLL0 clock source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..Oscillator 32kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name PLL1CLKSEL - PLL1 clock source select */ -/*! @{ */ -#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) -#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) -/*! SEL - PLL1 clock source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..Oscillator 32kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name ADCCLKSEL - ADC clock source select */ -/*! @{ */ -#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) -#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) -/*! SEL - ADC clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..FRO 96 MHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name USB0CLKSEL - FS USB clock source select */ -/*! @{ */ -#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) -#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) -/*! SEL - FS USB clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..PLL1 clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name USB1CLKSEL - HS USB clock source select - NOT USED */ -/*! @{ */ -#define SYSCON_USB1CLKSEL_SEL_MASK (0x7U) -#define SYSCON_USB1CLKSEL_SEL_SHIFT (0U) -/*! SEL - HS USB clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..CLKIN clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..PLL1 clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_USB1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */ -/*! @{ */ -#define SYSCON_FCCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL0_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */ -/*! @{ */ -#define SYSCON_FCCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL1_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */ -/*! @{ */ -#define SYSCON_FCCLKSEL2_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL2_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */ -/*! @{ */ -#define SYSCON_FCCLKSEL3_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL3_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */ -/*! @{ */ -#define SYSCON_FCCLKSEL4_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL4_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */ -/*! @{ */ -#define SYSCON_FCCLKSEL5_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL5_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL5_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */ -/*! @{ */ -#define SYSCON_FCCLKSEL6_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL6_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL6_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */ -/*! @{ */ -#define SYSCON_FCCLKSEL7_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL7_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL7_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSELX - Peripheral reset control register */ -/*! @{ */ -#define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_FCCLKSELX_DATA_SHIFT (0U) -#define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_FCCLKSELX */ -#define SYSCON_FCCLKSELX_COUNT (8U) - -/*! @name HSLSPICLKSEL - HS LSPI clock source select */ -/*! @{ */ -#define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U) -#define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U) -/*! SEL - HS LSPI clock source select. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..No clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_HSLSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK) -/*! @} */ - -/*! @name MCLKCLKSEL - MCLK clock source select */ -/*! @{ */ -#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) -#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) -/*! SEL - MCLK clock source select. - * 0b000..FRO 96 MHz clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ -/*! @{ */ -#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) -/*! SEL - SCTimer/PWM clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..CLKIN clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..MCLK clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SDIOCLKSEL - SDIO clock source select */ -/*! @{ */ -#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U) -/*! SEL - SDIO clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..PLL1 clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */ -/*! @{ */ -#define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU) -#define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U) -#define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK) -#define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U) -#define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK) -#define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U) -#define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK) -#define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U) -#define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK) -/*! @} */ - -/*! @name SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 */ -/*! @{ */ -#define SYSCON_SYSTICKCLKDIV1_DIV_MASK (0xFFU) -#define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT (0U) -#define SYSCON_SYSTICKCLKDIV1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK) -#define SYSCON_SYSTICKCLKDIV1_RESET_MASK (0x20000000U) -#define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SYSTICKCLKDIV1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK) -#define SYSCON_SYSTICKCLKDIV1_HALT_MASK (0x40000000U) -#define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SYSTICKCLKDIV1_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK) -#define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK (0x80000000U) -#define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SYSTICKCLKDIV1_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK) -/*! @} */ - -/*! @name TRACECLKDIV - TRACE clock divider */ -/*! @{ */ -#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) -#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) -#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) -#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) -#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) -#define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_TRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */ -/*! @{ */ -#define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U) -#define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK) -#define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U) -#define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */ -/*! @{ */ -#define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U) -#define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK) -#define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U) -#define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */ -/*! @{ */ -#define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U) -#define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK) -#define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U) -#define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */ -/*! @{ */ -#define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U) -#define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK) -#define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U) -#define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */ -/*! @{ */ -#define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U) -#define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK) -#define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U) -#define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */ -/*! @{ */ -#define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U) -#define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK) -#define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U) -#define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */ -/*! @{ */ -#define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U) -#define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK) -#define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U) -#define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */ -/*! @{ */ -#define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U) -#define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK) -#define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U) -#define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRGXCTRL - Peripheral reset control register */ -/*! @{ */ -#define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U) -#define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_FLEXFRGXCTRL */ -#define SYSCON_FLEXFRGXCTRL_COUNT (8U) - -/*! @name AHBCLKDIV - System clock divider */ -/*! @{ */ -#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) -#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) -#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) -#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) -#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name CLKOUTDIV - CLKOUT clock divider */ -/*! @{ */ -#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) -#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) -#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) -#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) -#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) -#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) -#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) -#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ -/*! @{ */ -#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) -#define SYSCON_FROHFDIV_DIV_SHIFT (0U) -#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) -#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) -#define SYSCON_FROHFDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) -#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) -#define SYSCON_FROHFDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) -#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name WDTCLKDIV - WDT clock divider */ -/*! @{ */ -#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) -#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) -#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) -#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) -#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) -#define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_WDTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name ADCCLKDIV - ADC clock divider */ -/*! @{ */ -#define SYSCON_ADCCLKDIV_DIV_MASK (0x7U) -#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) -#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) -#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) -#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) -#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name USB0CLKDIV - USB0 Clock divider */ -/*! @{ */ -#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) -#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) -#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) -#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) -#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name MCLKDIV - I2S MCLK clock divider */ -/*! @{ */ -#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_MCLKDIV_DIV_SHIFT (0U) -#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) -#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_MCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) -#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_MCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) -#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name SCTCLKDIV - SCT/PWM clock divider */ -/*! @{ */ -#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) -#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) -#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) -#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) -#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name SDIOCLKDIV - SDIO clock divider */ -/*! @{ */ -#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U) -#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK) -#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK) -#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK) -#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name PLL0CLKDIV - PLL0 clock divider */ -/*! @{ */ -#define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U) -#define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK) -#define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK) -#define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK) -#define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_PLL0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */ -/*! @{ */ -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU) -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U) -/*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL). - * 0b00000000000000000000000000000001..update all clock configuration. - * 0b00000000000000000000000000000000..all hardware clock configruration are freeze. - */ -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK) -/*! @} */ - -/*! @name FMCCR - FMC configuration register - INTERNAL USE ONLY */ -/*! @{ */ -#define SYSCON_FMCCR_FETCHCTL_MASK (0x3U) -#define SYSCON_FMCCR_FETCHCTL_SHIFT (0U) -/*! FETCHCTL - Fetch control - * 0b00..No buffering (bypass always used) for Fetch cycles - * 0b01..One buffer is used for all Fetch cycles - * 0b10..All buffers can be used for Fetch cycles - */ -#define SYSCON_FMCCR_FETCHCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCTL_SHIFT)) & SYSCON_FMCCR_FETCHCTL_MASK) -#define SYSCON_FMCCR_DATACTL_MASK (0xCU) -#define SYSCON_FMCCR_DATACTL_SHIFT (2U) -/*! DATACTL - Data control - * 0b00..No buffering (bypass always used) for Data cycles - * 0b01..One buffer is used for all Data cycles - * 0b10..All buffers can be used for Data cycles - */ -#define SYSCON_FMCCR_DATACTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACTL_SHIFT)) & SYSCON_FMCCR_DATACTL_MASK) -#define SYSCON_FMCCR_ACCEL_MASK (0x10U) -#define SYSCON_FMCCR_ACCEL_SHIFT (4U) -#define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) -#define SYSCON_FMCCR_PREFEN_MASK (0x20U) -#define SYSCON_FMCCR_PREFEN_SHIFT (5U) -#define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) -#define SYSCON_FMCCR_PREFOVR_MASK (0x40U) -#define SYSCON_FMCCR_PREFOVR_SHIFT (6U) -#define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) -#define SYSCON_FMCCR_PREFCRI_MASK (0x700U) -#define SYSCON_FMCCR_PREFCRI_SHIFT (8U) -#define SYSCON_FMCCR_PREFCRI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFCRI_SHIFT)) & SYSCON_FMCCR_PREFCRI_MASK) -#define SYSCON_FMCCR_FMCTIM_MASK (0x1F000U) -#define SYSCON_FMCCR_FMCTIM_SHIFT (12U) -#define SYSCON_FMCCR_FMCTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FMCTIM_SHIFT)) & SYSCON_FMCCR_FMCTIM_MASK) -#define SYSCON_FMCCR_PFISLRU_MASK (0x20000U) -#define SYSCON_FMCCR_PFISLRU_SHIFT (17U) -#define SYSCON_FMCCR_PFISLRU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PFISLRU_SHIFT)) & SYSCON_FMCCR_PFISLRU_MASK) -#define SYSCON_FMCCR_PFADAP_MASK (0x40000U) -#define SYSCON_FMCCR_PFADAP_SHIFT (18U) -#define SYSCON_FMCCR_PFADAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PFADAP_SHIFT)) & SYSCON_FMCCR_PFADAP_MASK) -/*! @} */ - -/*! @name USB0CLKCTRL - USB0 clock control */ -/*! @{ */ -#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U) -#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U) -/*! AP_FS_DEV_CLK - USB0 Device USB0_NEEDCLK signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK) -#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U) -#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U) -/*! POL_FS_DEV_CLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. - * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. - * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK) -#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U) -#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U) -/*! AP_FS_HOST_CLK - USB0 Host USB0_NEEDCLK signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK) -#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U) -#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U) -/*! POL_FS_HOST_CLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. - * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. - * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK) -#define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK (0x10U) -#define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT (4U) -/*! PU_DISABLE - Internal pull-up disable control. - * 0b1..Internal pull-up disable. - * 0b0..Internal pull-up enable. - */ -#define SYSCON_USB0CLKCTRL_PU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK) -/*! @} */ - -/*! @name USB0CLKSTAT - USB0 clock status */ -/*! @{ */ -#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) -#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) -/*! DEV_NEED_CLKST - USB0 Device USB0_NEEDCLK signal status:. - * 0b1..USB0 Device clock is high. - * 0b0..USB0 Device clock is low. - */ -#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK) -#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) -#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) -/*! HOST_NEED_CLKST - USB0 Host USB0_NEEDCLK signal status:. - * 0b1..USB0 Host clock is high. - * 0b0..USB0 Host clock is low. - */ -#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK) -/*! @} */ - -/*! @name FMCFLUSH - FMCflush control */ -/*! @{ */ -#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) -#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) -#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) -/*! @} */ - -/*! @name MCLKIO - MCLK control */ -/*! @{ */ -#define SYSCON_MCLKIO_MCLKIO_MASK (0xFFFFFFFFU) -#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) -/*! MCLKIO - MCLK control. - * 0b00000000000000000000000000000000..input mode. - * 0b00000000000000000000000000000001..output mode. - */ -#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) -/*! @} */ - -/*! @name USB1CLKCTRL - USB1 clock control */ -/*! @{ */ -#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_MASK (0x1U) -#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_SHIFT (0U) -/*! AP_HS_DEV_CLK - USB1 Device need_clock signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_MASK) -#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_MASK (0x2U) -#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_SHIFT (1U) -/*! POL_HS_DEV_CLK - USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt:. - * 0b0..Falling edge of device need_clock triggers wake-up. - * 0b1..Rising edge of device need_clock triggers wake-up. - */ -#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_MASK) -#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_MASK (0x4U) -#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_SHIFT (2U) -/*! AP_HS_HOST_CLK - USB1 Host need_clock signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_MASK) -#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_MASK (0x8U) -#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_SHIFT (3U) -/*! POL_HS_HOST_CLK - USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt: 0 Falling edge of device need_clock triggers wake-up. - * 0b0..Falling edge of device need_clock triggers wake-up. - * 0b1..Rising edge of device need_clock triggers wake-up. - */ -#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_MASK) -#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) -#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) -/*! HS_DEV_WAKEUP_N - External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to synchronous control logic:. - * 0b0..Forces USB1 PHY to wake-up. - * 0b1..Normal USB1 PHY behavior. - */ -#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK) -/*! @} */ - -/*! @name USB1CLKSTAT - USB1 clock status */ -/*! @{ */ -#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) -#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) -/*! DEV_NEED_CLKST - USB1 Device need_clock signal status:. - * 0b1..USB1 Device clock is high. - * 0b0..USB1 Device clock is low. - */ -#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK) -#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) -#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) -/*! HOST_NEED_CLKST - USB1 Host need_clock signal status:. - * 0b1..USB1 Host clock is high. - * 0b0..USB1 Host clock is low. - */ -#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK) -/*! @} */ - -/*! @name FLASHBANKENABLE - Flash Banks control */ -/*! @{ */ -#define SYSCON_FLASHBANKENABLE_BANK0_MASK (0xFU) -#define SYSCON_FLASHBANKENABLE_BANK0_SHIFT (0U) -/*! BANK0 - Flash Bank0 control. - * 0b0000..Flash BANK0 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - * 0b1010..1010: Flash BANK0 checker is disabled (all Flash pages inside this bank can be erased and programmed). - */ -#define SYSCON_FLASHBANKENABLE_BANK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK0_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK0_MASK) -#define SYSCON_FLASHBANKENABLE_BANK1_MASK (0xF0U) -#define SYSCON_FLASHBANKENABLE_BANK1_SHIFT (4U) -/*! BANK1 - Flash Bank1 control. - * 0b0000..Flash BANK1 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - * 0b1010..1010: Flash BANK1 checker is disabled (all Flash pages inside this bank can be erased and programmed). - */ -#define SYSCON_FLASHBANKENABLE_BANK1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK1_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK1_MASK) -#define SYSCON_FLASHBANKENABLE_BANK2_MASK (0xF00U) -#define SYSCON_FLASHBANKENABLE_BANK2_SHIFT (8U) -/*! BANK2 - Flash Bank2 control. - * 0b0000..Flash BANK2 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - * 0b1010..1010: Flash BANK2 checker is disabled (all Flash pages inside this bank can be erased and programmed). - */ -#define SYSCON_FLASHBANKENABLE_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK2_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK2_MASK) -/*! @} */ - -/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */ -/*! @{ */ -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U) -/*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. - * 0b00..0 degree shift. - * 0b01..90 degree shift. - * 0b10..180 degree shift. - * 0b11..270 degree shift. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U) -/*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. - * 0b00..0 degree shift. - * 0b01..90 degree shift. - * 0b10..180 degree shift. - * 0b11..270 degree shift. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK) -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U) -/*! PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. - * 0b0..Bypassed. - * 0b1..Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. - */ -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U) -/*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field. - * 0b1..Enable drive delay. - * 0b0..Disable drive delay. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U) -/*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. - * 0b1..Enables sample delay. - * 0b0..Disables sample delay. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK) -/*! @} */ - -/*! @name PLL1CTRL - PLL1 550m control */ -/*! @{ */ -#define SYSCON_PLL1CTRL_SELR_MASK (0xFU) -#define SYSCON_PLL1CTRL_SELR_SHIFT (0U) -#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) -#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) -#define SYSCON_PLL1CTRL_SELI_SHIFT (4U) -#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) -#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) -#define SYSCON_PLL1CTRL_SELP_SHIFT (10U) -#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) -#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) -#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) -/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - * 0b1..PLL input clock is sent directly to the PLL output. - * 0b0..use PLL. - */ -#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) -/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - * 0b1..bypass of the divide-by-2 divider in the post-divider. - * 0b0..use the divide-by-2 divider in the post-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) -#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) -#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) -#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) -#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) -#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) -/*! BWDIRECT - control of the bandwidth of the PLL. - * 0b1..modify the bandwidth of the PLL directly. - * 0b0..the bandwidth is changed synchronously with the feedback-divider. - */ -#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) -#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) -#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) -/*! BYPASSPREDIV - bypass of the pre-divider. - * 0b1..bypass of the pre-divider. - * 0b0..use the pre-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) -/*! BYPASSPOSTDIV - bypass of the post-divider. - * 0b1..bypass of the post-divider. - * 0b0..use the post-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) -#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) -#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) -/*! CLKEN - enable the output clock. - * 0b1..Enable the output clock. - * 0b0..Disable the output clock. - */ -#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) -#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) -#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) -#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) -#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) -#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) -#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) -#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) -#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) -/*! SKEWEN - Skew mode. - * 0b1..skewmode is enable. - * 0b0..skewmode is disable. - */ -#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK) -/*! @} */ - -/*! @name PLL1STAT - PLL1 550m status */ -/*! @{ */ -#define SYSCON_PLL1STAT_LOCK_MASK (0x1U) -#define SYSCON_PLL1STAT_LOCK_SHIFT (0U) -#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) -#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) -#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) -#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) -#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) -#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) -#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) -#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) -#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) -#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) -#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) -#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) -#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) -/*! @} */ - -/*! @name PLL1NDEC - PLL1 550m N divider */ -/*! @{ */ -#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) -#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) -#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) -#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) -#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) -#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) -/*! @} */ - -/*! @name PLL1MDEC - PLL1 550m M divider */ -/*! @{ */ -#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) -#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) -#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) -#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) -#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) -#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) -/*! @} */ - -/*! @name PLL1PDEC - PLL1 550m P divider */ -/*! @{ */ -#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) -#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) -#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) -#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) -#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) -#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) -/*! @} */ - -/*! @name PLL0CTRL - PLL0 550m control */ -/*! @{ */ -#define SYSCON_PLL0CTRL_SELR_MASK (0xFU) -#define SYSCON_PLL0CTRL_SELR_SHIFT (0U) -#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) -#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) -#define SYSCON_PLL0CTRL_SELI_SHIFT (4U) -#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) -#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) -#define SYSCON_PLL0CTRL_SELP_SHIFT (10U) -#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) -#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) -#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) -/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - * 0b1..Bypass PLL input clock is sent directly to the PLL output. - * 0b0..use PLL. - */ -#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) -/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - * 0b1..bypass of the divide-by-2 divider in the post-divider. - * 0b0..use the divide-by-2 divider in the post-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) -#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) -#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) -#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) -#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) -#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) -/*! BWDIRECT - Control of the bandwidth of the PLL. - * 0b1..modify the bandwidth of the PLL directly. - * 0b0..the bandwidth is changed synchronously with the feedback-divider. - */ -#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) -#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) -#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) -/*! BYPASSPREDIV - bypass of the pre-divider. - * 0b1..bypass of the pre-divider. - * 0b0..use the pre-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) -/*! BYPASSPOSTDIV - bypass of the post-divider. - * 0b1..bypass of the post-divider. - * 0b0..use the post-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) -#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) -#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) -/*! CLKEN - enable the output clock. - * 0b1..enable the output clock. - * 0b0..disable the output clock. - */ -#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) -#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) -#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) -/*! FRMEN - free running mode. - * 0b1..free running mode is enable. - * 0b0..free running mode is disable. - */ -#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) -#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) -#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) -#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) -#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) -#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) -/*! SKEWEN - skew mode. - * 0b1..skew mode is enable. - * 0b0..skew mode is disable. - */ -#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK) -/*! @} */ - -/*! @name PLL0STAT - PLL0 550m status */ -/*! @{ */ -#define SYSCON_PLL0STAT_LOCK_MASK (0x1U) -#define SYSCON_PLL0STAT_LOCK_SHIFT (0U) -#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) -#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) -#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) -#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) -#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) -#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) -#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) -#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) -#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) -#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) -#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) -#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) -#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) -/*! @} */ - -/*! @name PLL0NDEC - PLL0 550m N divider */ -/*! @{ */ -#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) -#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) -#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) -#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) -#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) -#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) -/*! @} */ - -/*! @name PLL0PDEC - PLL0 550m P divider */ -/*! @{ */ -#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) -#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) -#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) -#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) -#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) -#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) -/*! @} */ - -/*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */ -/*! @{ */ -#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) -#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) -#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) -/*! @} */ - -/*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */ -/*! @{ */ -#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) -#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) -#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) -#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) -#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) -#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) -#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) -#define SYSCON_PLL0SSCG1_MF_SHIFT (2U) -#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) -#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) -#define SYSCON_PLL0SSCG1_MR_SHIFT (5U) -#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) -#define SYSCON_PLL0SSCG1_MC_MASK (0x300U) -#define SYSCON_PLL0SSCG1_MC_SHIFT (8U) -#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) -#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) -#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) -#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) -#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) -#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) -#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) -#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) -#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) -#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) -#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) -#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) -#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) -/*! @} */ - -/*! @name EFUSECLKCTRL - eFUSE controller clock enable */ -/*! @{ */ -#define SYSCON_EFUSECLKCTRL_EFUSECLKENA_MASK (0x1U) -#define SYSCON_EFUSECLKCTRL_EFUSECLKENA_SHIFT (0U) -#define SYSCON_EFUSECLKCTRL_EFUSECLKENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EFUSECLKCTRL_EFUSECLKENA_SHIFT)) & SYSCON_EFUSECLKCTRL_EFUSECLKENA_MASK) -/*! @} */ - -/*! @name STARTER - Start logic wake-up enable register */ -/*! @{ */ -#define SYSCON_STARTER_GPIO_INT04_MASK (0x1U) -#define SYSCON_STARTER_GPIO_INT04_SHIFT (0U) -/*! GPIO_INT04 - GPIO_INT04 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT04(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT04_SHIFT)) & SYSCON_STARTER_GPIO_INT04_MASK) -#define SYSCON_STARTER_SYS_MASK (0x1U) -#define SYSCON_STARTER_SYS_SHIFT (0U) -/*! SYS - SYS interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SYS_SHIFT)) & SYSCON_STARTER_SYS_MASK) -#define SYSCON_STARTER_GPIO_INT05_MASK (0x2U) -#define SYSCON_STARTER_GPIO_INT05_SHIFT (1U) -/*! GPIO_INT05 - GPIO_INT05 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT05(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT05_SHIFT)) & SYSCON_STARTER_GPIO_INT05_MASK) -#define SYSCON_STARTER_SDMA0_MASK (0x2U) -#define SYSCON_STARTER_SDMA0_SHIFT (1U) -/*! SDMA0 - SDMA0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA0_SHIFT)) & SYSCON_STARTER_SDMA0_MASK) -#define SYSCON_STARTER_GINT0_MASK (0x4U) -#define SYSCON_STARTER_GINT0_SHIFT (2U) -/*! GINT0 - GINT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK) -#define SYSCON_STARTER_GPIO_INT06_MASK (0x4U) -#define SYSCON_STARTER_GPIO_INT06_SHIFT (2U) -/*! GPIO_INT06 - GPIO_INT06 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT06(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT06_SHIFT)) & SYSCON_STARTER_GPIO_INT06_MASK) -#define SYSCON_STARTER_GINT1_MASK (0x8U) -#define SYSCON_STARTER_GINT1_SHIFT (3U) -/*! GINT1 - GINT1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK) -#define SYSCON_STARTER_GPIO_INT07_MASK (0x8U) -#define SYSCON_STARTER_GPIO_INT07_SHIFT (3U) -/*! GPIO_INT07 - GPIO_INT07 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT07(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT07_SHIFT)) & SYSCON_STARTER_GPIO_INT07_MASK) -#define SYSCON_STARTER_CTIMER2_MASK (0x10U) -#define SYSCON_STARTER_CTIMER2_SHIFT (4U) -/*! CTIMER2 - CTIMER2 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK) -#define SYSCON_STARTER_PIO_INT0_MASK (0x10U) -#define SYSCON_STARTER_PIO_INT0_SHIFT (4U) -/*! PIO_INT0 - PIO_INT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT0_SHIFT)) & SYSCON_STARTER_PIO_INT0_MASK) -#define SYSCON_STARTER_CTIMER4_MASK (0x20U) -#define SYSCON_STARTER_CTIMER4_SHIFT (5U) -/*! CTIMER4 - CTIMER4 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK) -#define SYSCON_STARTER_PIO_INT1_MASK (0x20U) -#define SYSCON_STARTER_PIO_INT1_SHIFT (5U) -/*! PIO_INT1 - PIO_INT1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT1_SHIFT)) & SYSCON_STARTER_PIO_INT1_MASK) -#define SYSCON_STARTER_OS_EVENT_MASK (0x40U) -#define SYSCON_STARTER_OS_EVENT_SHIFT (6U) -/*! OS_EVENT - OS_EVENT interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_OS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_OS_EVENT_SHIFT)) & SYSCON_STARTER_OS_EVENT_MASK) -#define SYSCON_STARTER_PIO_INT2_MASK (0x40U) -#define SYSCON_STARTER_PIO_INT2_SHIFT (6U) -/*! PIO_INT2 - PIO_INT2 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT2_SHIFT)) & SYSCON_STARTER_PIO_INT2_MASK) -#define SYSCON_STARTER_PIO_INT3_MASK (0x80U) -#define SYSCON_STARTER_PIO_INT3_SHIFT (7U) -/*! PIO_INT3 - PIO_INT3 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT3_SHIFT)) & SYSCON_STARTER_PIO_INT3_MASK) -#define SYSCON_STARTER_UTICK0_MASK (0x100U) -#define SYSCON_STARTER_UTICK0_SHIFT (8U) -/*! UTICK0 - UTICK0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK0_SHIFT)) & SYSCON_STARTER_UTICK0_MASK) -#define SYSCON_STARTER_MRT0_MASK (0x200U) -#define SYSCON_STARTER_MRT0_SHIFT (9U) -/*! MRT0 - MRT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT0_SHIFT)) & SYSCON_STARTER_MRT0_MASK) -#define SYSCON_STARTER_CTIMER0_MASK (0x400U) -#define SYSCON_STARTER_CTIMER0_SHIFT (10U) -/*! CTIMER0 - CTIMER0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK) -#define SYSCON_STARTER_SDIO_MASK (0x400U) -#define SYSCON_STARTER_SDIO_SHIFT (10U) -/*! SDIO - SDIO interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDIO_SHIFT)) & SYSCON_STARTER_SDIO_MASK) -#define SYSCON_STARTER_CTIMER1_MASK (0x800U) -#define SYSCON_STARTER_CTIMER1_SHIFT (11U) -/*! CTIMER1 - CTIMER1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK) -#define SYSCON_STARTER_SCT0_MASK (0x1000U) -#define SYSCON_STARTER_SCT0_SHIFT (12U) -/*! SCT0 - SCT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK) -#define SYSCON_STARTER_CTIMER3_MASK (0x2000U) -#define SYSCON_STARTER_CTIMER3_SHIFT (13U) -/*! CTIMER3 - CTIMER3 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK) -#define SYSCON_STARTER_FLEXINT0_MASK (0x4000U) -#define SYSCON_STARTER_FLEXINT0_SHIFT (14U) -/*! FLEXINT0 - FLEXINT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT0_SHIFT)) & SYSCON_STARTER_FLEXINT0_MASK) -#define SYSCON_STARTER_FLEXINT1_MASK (0x8000U) -#define SYSCON_STARTER_FLEXINT1_SHIFT (15U) -/*! FLEXINT1 - FLEXINT1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT1_SHIFT)) & SYSCON_STARTER_FLEXINT1_MASK) -#define SYSCON_STARTER_USB1_MASK (0x8000U) -#define SYSCON_STARTER_USB1_SHIFT (15U) -/*! USB1 - USB1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK) -#define SYSCON_STARTER_FLEXINT2_MASK (0x10000U) -#define SYSCON_STARTER_FLEXINT2_SHIFT (16U) -/*! FLEXINT2 - FLEXINT2 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT2_SHIFT)) & SYSCON_STARTER_FLEXINT2_MASK) -#define SYSCON_STARTER_USB1_NEEDCLK_MASK (0x10000U) -#define SYSCON_STARTER_USB1_NEEDCLK_SHIFT (16U) -/*! USB1_NEEDCLK - USB1_NEEDCLK interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB1_NEEDCLK_MASK) -#define SYSCON_STARTER_FLEXINT3_MASK (0x20000U) -#define SYSCON_STARTER_FLEXINT3_SHIFT (17U) -/*! FLEXINT3 - FLEXINT3 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT3_SHIFT)) & SYSCON_STARTER_FLEXINT3_MASK) -#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK (0x20000U) -#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT (17U) -/*! SEC_HYPERVISOR_CALL - SEC_HYPERVISOR_CALL interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_HYPERVISOR_CALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT)) & SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK) -#define SYSCON_STARTER_FLEXINT4_MASK (0x40000U) -#define SYSCON_STARTER_FLEXINT4_SHIFT (18U) -/*! FLEXINT4 - FLEXINT4 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT4_SHIFT)) & SYSCON_STARTER_FLEXINT4_MASK) -#define SYSCON_STARTER_SEC_GPIO_INT00_MASK (0x40000U) -#define SYSCON_STARTER_SEC_GPIO_INT00_SHIFT (18U) -/*! SEC_GPIO_INT00 - SEC_GPIO_INT00 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_GPIO_INT00(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT00_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT00_MASK) -#define SYSCON_STARTER_FLEXINT5_MASK (0x80000U) -#define SYSCON_STARTER_FLEXINT5_SHIFT (19U) -/*! FLEXINT5 - FLEXINT5 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT5_SHIFT)) & SYSCON_STARTER_FLEXINT5_MASK) -#define SYSCON_STARTER_SEC_GPIO_INT01_MASK (0x80000U) -#define SYSCON_STARTER_SEC_GPIO_INT01_SHIFT (19U) -/*! SEC_GPIO_INT01 - SEC_GPIO_INT01 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_GPIO_INT01(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT01_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT01_MASK) -#define SYSCON_STARTER_FLEXINT6_MASK (0x100000U) -#define SYSCON_STARTER_FLEXINT6_SHIFT (20U) -/*! FLEXINT6 - FLEXINT6 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT6_SHIFT)) & SYSCON_STARTER_FLEXINT6_MASK) -#define SYSCON_STARTER_PLU_MASK (0x100000U) -#define SYSCON_STARTER_PLU_SHIFT (20U) -/*! PLU - PLU interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PLU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PLU_SHIFT)) & SYSCON_STARTER_PLU_MASK) -#define SYSCON_STARTER_FLEXINT7_MASK (0x200000U) -#define SYSCON_STARTER_FLEXINT7_SHIFT (21U) -/*! FLEXINT7 - FLEXINT7 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT7_SHIFT)) & SYSCON_STARTER_FLEXINT7_MASK) -#define SYSCON_STARTER_SEC_VIO_MASK (0x200000U) -#define SYSCON_STARTER_SEC_VIO_SHIFT (21U) -/*! SEC_VIO - SEC_VIO interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_VIO_SHIFT)) & SYSCON_STARTER_SEC_VIO_MASK) -#define SYSCON_STARTER_ADC0_MASK (0x400000U) -#define SYSCON_STARTER_ADC0_SHIFT (22U) -/*! ADC0 - ADC0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SHIFT)) & SYSCON_STARTER_ADC0_MASK) -#define SYSCON_STARTER_SHA_MASK (0x400000U) -#define SYSCON_STARTER_SHA_SHIFT (22U) -/*! SHA - SHA interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SHA_SHIFT)) & SYSCON_STARTER_SHA_MASK) -#define SYSCON_STARTER_CASER_MASK (0x800000U) -#define SYSCON_STARTER_CASER_SHIFT (23U) -/*! CASER - CASER interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CASER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CASER_SHIFT)) & SYSCON_STARTER_CASER_MASK) -#define SYSCON_STARTER_ADC0_THCMP_OVR_MASK (0x1000000U) -#define SYSCON_STARTER_ADC0_THCMP_OVR_SHIFT (24U) -/*! ADC0_THCMP_OVR - ADC0_THCMP_OVR interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ADC0_THCMP_OVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_THCMP_OVR_SHIFT)) & SYSCON_STARTER_ADC0_THCMP_OVR_MASK) -#define SYSCON_STARTER_QDDKEY_MASK (0x1000000U) -#define SYSCON_STARTER_QDDKEY_SHIFT (24U) -/*! QDDKEY - QDDKEY interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_QDDKEY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_QDDKEY_SHIFT)) & SYSCON_STARTER_QDDKEY_MASK) -#define SYSCON_STARTER_PQ_MASK (0x2000000U) -#define SYSCON_STARTER_PQ_SHIFT (25U) -/*! PQ - PQ interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PQ_SHIFT)) & SYSCON_STARTER_PQ_MASK) -#define SYSCON_STARTER_SDMA1_MASK (0x4000000U) -#define SYSCON_STARTER_SDMA1_SHIFT (26U) -/*! SDMA1 - SDMA1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA1_SHIFT)) & SYSCON_STARTER_SDMA1_MASK) -#define SYSCON_STARTER_LSPI_HS_MASK (0x8000000U) -#define SYSCON_STARTER_LSPI_HS_SHIFT (27U) -/*! LSPI_HS - LSPI_HS interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_LSPI_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_LSPI_HS_SHIFT)) & SYSCON_STARTER_LSPI_HS_MASK) -#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U) -#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U) -/*! USB0_NEEDCLK - USB0_NEEDCLK interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK) -#define SYSCON_STARTER_USB0_MASK (0x10000000U) -#define SYSCON_STARTER_USB0_SHIFT (28U) -/*! USB0 - USB0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK) -#define SYSCON_STARTER_RTC_LITE0_MASK (0x20000000U) -#define SYSCON_STARTER_RTC_LITE0_SHIFT (29U) -/*! RTC_LITE0 - RTC_LITE0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_RTC_LITE0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_LITE0_SHIFT)) & SYSCON_STARTER_RTC_LITE0_MASK) -#define SYSCON_STARTER_EZH_ARCH_B0_MASK (0x40000000U) -#define SYSCON_STARTER_EZH_ARCH_B0_SHIFT (30U) -/*! EZH_ARCH_B0 - EZH_ARCH_B0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_EZH_ARCH_B0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_EZH_ARCH_B0_SHIFT)) & SYSCON_STARTER_EZH_ARCH_B0_MASK) -#define SYSCON_STARTER_WAKEUPPADS_MASK (0x80000000U) -#define SYSCON_STARTER_WAKEUPPADS_SHIFT (31U) -#define SYSCON_STARTER_WAKEUPPADS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUPPADS_SHIFT)) & SYSCON_STARTER_WAKEUPPADS_MASK) -#define SYSCON_STARTER_WAKEUP_MAILBOX0_MASK (0x80000000U) -#define SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT (31U) -/*! WAKEUP_MAILBOX0 - WAKEUP_MAILBOX0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_WAKEUP_MAILBOX0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT)) & SYSCON_STARTER_WAKEUP_MAILBOX0_MASK) -/*! @} */ - -/* The count of SYSCON_STARTER */ -#define SYSCON_STARTER_COUNT (2U) - -/*! @name STARTERSET - Set bits in STARTER */ -/*! @{ */ -#define SYSCON_STARTERSET_GPIO_INT04_SET_MASK (0x1U) -#define SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT (0U) -#define SYSCON_STARTERSET_GPIO_INT04_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT04_SET_MASK) -#define SYSCON_STARTERSET_SYS_SET_MASK (0x1U) -#define SYSCON_STARTERSET_SYS_SET_SHIFT (0U) -#define SYSCON_STARTERSET_SYS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SYS_SET_SHIFT)) & SYSCON_STARTERSET_SYS_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT05_SET_MASK (0x2U) -#define SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT (1U) -#define SYSCON_STARTERSET_GPIO_INT05_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT05_SET_MASK) -#define SYSCON_STARTERSET_SDMA0_SET_MASK (0x2U) -#define SYSCON_STARTERSET_SDMA0_SET_SHIFT (1U) -#define SYSCON_STARTERSET_SDMA0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA0_SET_SHIFT)) & SYSCON_STARTERSET_SDMA0_SET_MASK) -#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK (0x4U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT (2U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT06_SET_MASK (0x4U) -#define SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT (2U) -#define SYSCON_STARTERSET_GPIO_INT06_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT06_SET_MASK) -#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK (0x8U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT (3U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT07_SET_MASK (0x8U) -#define SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT (3U) -#define SYSCON_STARTERSET_GPIO_INT07_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT07_SET_MASK) -#define SYSCON_STARTERSET_CTIMER2_SET_MASK (0x10U) -#define SYSCON_STARTERSET_CTIMER2_SET_SHIFT (4U) -#define SYSCON_STARTERSET_CTIMER2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER2_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER2_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT00_SET_MASK (0x10U) -#define SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT (4U) -#define SYSCON_STARTERSET_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT00_SET_MASK) -#define SYSCON_STARTERSET_CTIMER4_SET_MASK (0x20U) -#define SYSCON_STARTERSET_CTIMER4_SET_SHIFT (5U) -#define SYSCON_STARTERSET_CTIMER4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER4_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER4_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT01_SET_MASK (0x20U) -#define SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT (5U) -#define SYSCON_STARTERSET_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT01_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT02_SET_MASK (0x40U) -#define SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT (6U) -#define SYSCON_STARTERSET_GPIO_INT02_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT02_SET_MASK) -#define SYSCON_STARTERSET_OS_EVENT_SET_MASK (0x40U) -#define SYSCON_STARTERSET_OS_EVENT_SET_SHIFT (6U) -#define SYSCON_STARTERSET_OS_EVENT_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_OS_EVENT_SET_SHIFT)) & SYSCON_STARTERSET_OS_EVENT_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT03_SET_MASK (0x80U) -#define SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT (7U) -#define SYSCON_STARTERSET_GPIO_INT03_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT03_SET_MASK) -#define SYSCON_STARTERSET_UTICK0_SET_MASK (0x100U) -#define SYSCON_STARTERSET_UTICK0_SET_SHIFT (8U) -#define SYSCON_STARTERSET_UTICK0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_UTICK0_SET_SHIFT)) & SYSCON_STARTERSET_UTICK0_SET_MASK) -#define SYSCON_STARTERSET_MRT0_SET_MASK (0x200U) -#define SYSCON_STARTERSET_MRT0_SET_SHIFT (9U) -#define SYSCON_STARTERSET_MRT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_MRT0_SET_SHIFT)) & SYSCON_STARTERSET_MRT0_SET_MASK) -#define SYSCON_STARTERSET_CTIMER0_SET_MASK (0x400U) -#define SYSCON_STARTERSET_CTIMER0_SET_SHIFT (10U) -#define SYSCON_STARTERSET_CTIMER0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER0_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER0_SET_MASK) -#define SYSCON_STARTERSET_SDIO_SET_MASK (0x400U) -#define SYSCON_STARTERSET_SDIO_SET_SHIFT (10U) -#define SYSCON_STARTERSET_SDIO_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDIO_SET_SHIFT)) & SYSCON_STARTERSET_SDIO_SET_MASK) -#define SYSCON_STARTERSET_CTIMER1_SET_MASK (0x800U) -#define SYSCON_STARTERSET_CTIMER1_SET_SHIFT (11U) -#define SYSCON_STARTERSET_CTIMER1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER1_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER1_SET_MASK) -#define SYSCON_STARTERSET_SCT0_SET_MASK (0x1000U) -#define SYSCON_STARTERSET_SCT0_SET_SHIFT (12U) -#define SYSCON_STARTERSET_SCT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SCT0_SET_SHIFT)) & SYSCON_STARTERSET_SCT0_SET_MASK) -#define SYSCON_STARTERSET_CTIMER3_SET_MASK (0x2000U) -#define SYSCON_STARTERSET_CTIMER3_SET_SHIFT (13U) -#define SYSCON_STARTERSET_CTIMER3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER3_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER3_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT0_SET_MASK (0x4000U) -#define SYSCON_STARTERSET_FLEXINT0_SET_SHIFT (14U) -#define SYSCON_STARTERSET_FLEXINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT0_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT1_SET_MASK (0x8000U) -#define SYSCON_STARTERSET_FLEXINT1_SET_SHIFT (15U) -#define SYSCON_STARTERSET_FLEXINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT1_SET_MASK) -#define SYSCON_STARTERSET_USB1_SET_MASK (0x8000U) -#define SYSCON_STARTERSET_USB1_SET_SHIFT (15U) -#define SYSCON_STARTERSET_USB1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB1_SET_SHIFT)) & SYSCON_STARTERSET_USB1_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT2_SET_MASK (0x10000U) -#define SYSCON_STARTERSET_FLEXINT2_SET_SHIFT (16U) -#define SYSCON_STARTERSET_FLEXINT2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT2_SET_MASK) -#define SYSCON_STARTERSET_USB1_NEEDCLK_SET_MASK (0x10000U) -#define SYSCON_STARTERSET_USB1_NEEDCLK_SET_SHIFT (16U) -#define SYSCON_STARTERSET_USB1_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB1_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB1_NEEDCLK_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT3_SET_MASK (0x20000U) -#define SYSCON_STARTERSET_FLEXINT3_SET_SHIFT (17U) -#define SYSCON_STARTERSET_FLEXINT3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT3_SET_MASK) -#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK (0x20000U) -#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT (17U) -#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT)) & SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT4_SET_MASK (0x40000U) -#define SYSCON_STARTERSET_FLEXINT4_SET_SHIFT (18U) -#define SYSCON_STARTERSET_FLEXINT4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT4_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT4_SET_MASK) -#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK (0x40000U) -#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT (18U) -#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT5_SET_MASK (0x80000U) -#define SYSCON_STARTERSET_FLEXINT5_SET_SHIFT (19U) -#define SYSCON_STARTERSET_FLEXINT5_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT5_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT5_SET_MASK) -#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK (0x80000U) -#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT (19U) -#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT6_SET_MASK (0x100000U) -#define SYSCON_STARTERSET_FLEXINT6_SET_SHIFT (20U) -#define SYSCON_STARTERSET_FLEXINT6_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT6_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT6_SET_MASK) -#define SYSCON_STARTERSET_PLU_SET_MASK (0x100000U) -#define SYSCON_STARTERSET_PLU_SET_SHIFT (20U) -#define SYSCON_STARTERSET_PLU_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PLU_SET_SHIFT)) & SYSCON_STARTERSET_PLU_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT7_SET_MASK (0x200000U) -#define SYSCON_STARTERSET_FLEXINT7_SET_SHIFT (21U) -#define SYSCON_STARTERSET_FLEXINT7_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT7_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT7_SET_MASK) -#define SYSCON_STARTERSET_SEC_VIO_SET_MASK (0x200000U) -#define SYSCON_STARTERSET_SEC_VIO_SET_SHIFT (21U) -#define SYSCON_STARTERSET_SEC_VIO_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_VIO_SET_SHIFT)) & SYSCON_STARTERSET_SEC_VIO_SET_MASK) -#define SYSCON_STARTERSET_ADC0_SET_MASK (0x400000U) -#define SYSCON_STARTERSET_ADC0_SET_SHIFT (22U) -#define SYSCON_STARTERSET_ADC0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_SET_MASK) -#define SYSCON_STARTERSET_SHA_SET_MASK (0x400000U) -#define SYSCON_STARTERSET_SHA_SET_SHIFT (22U) -#define SYSCON_STARTERSET_SHA_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SHA_SET_SHIFT)) & SYSCON_STARTERSET_SHA_SET_MASK) -#define SYSCON_STARTERSET_CASER_SET_MASK (0x800000U) -#define SYSCON_STARTERSET_CASER_SET_SHIFT (23U) -#define SYSCON_STARTERSET_CASER_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CASER_SET_SHIFT)) & SYSCON_STARTERSET_CASER_SET_MASK) -#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK (0x1000000U) -#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT (24U) -#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK) -#define SYSCON_STARTERSET_QDDKEY_SET_MASK (0x1000000U) -#define SYSCON_STARTERSET_QDDKEY_SET_SHIFT (24U) -#define SYSCON_STARTERSET_QDDKEY_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_QDDKEY_SET_SHIFT)) & SYSCON_STARTERSET_QDDKEY_SET_MASK) -#define SYSCON_STARTERSET_PQ_SET_MASK (0x2000000U) -#define SYSCON_STARTERSET_PQ_SET_SHIFT (25U) -#define SYSCON_STARTERSET_PQ_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PQ_SET_SHIFT)) & SYSCON_STARTERSET_PQ_SET_MASK) -#define SYSCON_STARTERSET_SDMA1_SET_MASK (0x4000000U) -#define SYSCON_STARTERSET_SDMA1_SET_SHIFT (26U) -#define SYSCON_STARTERSET_SDMA1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA1_SET_SHIFT)) & SYSCON_STARTERSET_SDMA1_SET_MASK) -#define SYSCON_STARTERSET_LSPI_HS_SET_MASK (0x8000000U) -#define SYSCON_STARTERSET_LSPI_HS_SET_SHIFT (27U) -#define SYSCON_STARTERSET_LSPI_HS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_LSPI_HS_SET_SHIFT)) & SYSCON_STARTERSET_LSPI_HS_SET_MASK) -#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK (0x8000000U) -#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT (27U) -#define SYSCON_STARTERSET_USB0_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK) -#define SYSCON_STARTERSET_USB0_SET_MASK (0x10000000U) -#define SYSCON_STARTERSET_USB0_SET_SHIFT (28U) -#define SYSCON_STARTERSET_USB0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_SET_SHIFT)) & SYSCON_STARTERSET_USB0_SET_MASK) -#define SYSCON_STARTERSET_RTC_LITE0_SET_MASK (0x20000000U) -#define SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT (29U) -#define SYSCON_STARTERSET_RTC_LITE0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT)) & SYSCON_STARTERSET_RTC_LITE0_SET_MASK) -#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK (0x40000000U) -#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT (30U) -#define SYSCON_STARTERSET_EZH_ARCH_B0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT)) & SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK) -#define SYSCON_STARTERSET_WAKEUPPADS_SET_MASK (0x80000000U) -#define SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT (31U) -#define SYSCON_STARTERSET_WAKEUPPADS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUPPADS_SET_MASK) -#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK (0x80000000U) -#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT (31U) -#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERSET */ -#define SYSCON_STARTERSET_COUNT (2U) - -/*! @name STARTERCLR - Clear bits in STARTER */ -/*! @{ */ -#define SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK (0x1U) -#define SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT (0U) -#define SYSCON_STARTERCLR_GPIO_INT04_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK) -#define SYSCON_STARTERCLR_SYS_CLR_MASK (0x1U) -#define SYSCON_STARTERCLR_SYS_CLR_SHIFT (0U) -#define SYSCON_STARTERCLR_SYS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SYS_CLR_SHIFT)) & SYSCON_STARTERCLR_SYS_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK (0x2U) -#define SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT (1U) -#define SYSCON_STARTERCLR_GPIO_INT05_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK) -#define SYSCON_STARTERCLR_SDMA0_CLR_MASK (0x2U) -#define SYSCON_STARTERCLR_SDMA0_CLR_SHIFT (1U) -#define SYSCON_STARTERCLR_SDMA0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA0_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA0_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK (0x4U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT (2U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK (0x4U) -#define SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT (2U) -#define SYSCON_STARTERCLR_GPIO_INT06_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK (0x8U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT (3U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK (0x8U) -#define SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT (3U) -#define SYSCON_STARTERCLR_GPIO_INT07_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER2_CLR_MASK (0x10U) -#define SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT (4U) -#define SYSCON_STARTERCLR_CTIMER2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER2_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK (0x10U) -#define SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT (4U) -#define SYSCON_STARTERCLR_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER4_CLR_MASK (0x20U) -#define SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT (5U) -#define SYSCON_STARTERCLR_CTIMER4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER4_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK (0x20U) -#define SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT (5U) -#define SYSCON_STARTERCLR_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK (0x40U) -#define SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT (6U) -#define SYSCON_STARTERCLR_GPIO_INT02_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK) -#define SYSCON_STARTERCLR_OS_EVENT_CLR_MASK (0x40U) -#define SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT (6U) -#define SYSCON_STARTERCLR_OS_EVENT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT)) & SYSCON_STARTERCLR_OS_EVENT_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK (0x80U) -#define SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT (7U) -#define SYSCON_STARTERCLR_GPIO_INT03_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK) -#define SYSCON_STARTERCLR_UTICK0_CLR_MASK (0x100U) -#define SYSCON_STARTERCLR_UTICK0_CLR_SHIFT (8U) -#define SYSCON_STARTERCLR_UTICK0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_UTICK0_CLR_SHIFT)) & SYSCON_STARTERCLR_UTICK0_CLR_MASK) -#define SYSCON_STARTERCLR_MRT0_CLR_MASK (0x200U) -#define SYSCON_STARTERCLR_MRT0_CLR_SHIFT (9U) -#define SYSCON_STARTERCLR_MRT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_MRT0_CLR_SHIFT)) & SYSCON_STARTERCLR_MRT0_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER0_CLR_MASK (0x400U) -#define SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT (10U) -#define SYSCON_STARTERCLR_CTIMER0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER0_CLR_MASK) -#define SYSCON_STARTERCLR_SDIO_CLR_MASK (0x400U) -#define SYSCON_STARTERCLR_SDIO_CLR_SHIFT (10U) -#define SYSCON_STARTERCLR_SDIO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDIO_CLR_SHIFT)) & SYSCON_STARTERCLR_SDIO_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER1_CLR_MASK (0x800U) -#define SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT (11U) -#define SYSCON_STARTERCLR_CTIMER1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER1_CLR_MASK) -#define SYSCON_STARTERCLR_SCT0_CLR_MASK (0x1000U) -#define SYSCON_STARTERCLR_SCT0_CLR_SHIFT (12U) -#define SYSCON_STARTERCLR_SCT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SCT0_CLR_SHIFT)) & SYSCON_STARTERCLR_SCT0_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER3_CLR_MASK (0x2000U) -#define SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT (13U) -#define SYSCON_STARTERCLR_CTIMER3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER3_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT0_CLR_MASK (0x4000U) -#define SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT (14U) -#define SYSCON_STARTERCLR_FLEXINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT0_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT1_CLR_MASK (0x8000U) -#define SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT (15U) -#define SYSCON_STARTERCLR_FLEXINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT1_CLR_MASK) -#define SYSCON_STARTERCLR_USB1_CLR_MASK (0x8000U) -#define SYSCON_STARTERCLR_USB1_CLR_SHIFT (15U) -#define SYSCON_STARTERCLR_USB1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB1_CLR_SHIFT)) & SYSCON_STARTERCLR_USB1_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT2_CLR_MASK (0x10000U) -#define SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT (16U) -#define SYSCON_STARTERCLR_FLEXINT2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT2_CLR_MASK) -#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_MASK (0x10000U) -#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_SHIFT (16U) -#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT3_CLR_MASK (0x20000U) -#define SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT (17U) -#define SYSCON_STARTERCLR_FLEXINT3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT3_CLR_MASK) -#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK (0x20000U) -#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT (17U) -#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT4_CLR_MASK (0x40000U) -#define SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT (18U) -#define SYSCON_STARTERCLR_FLEXINT4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT4_CLR_MASK) -#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK (0x40000U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT (18U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT5_CLR_MASK (0x80000U) -#define SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT (19U) -#define SYSCON_STARTERCLR_FLEXINT5_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT5_CLR_MASK) -#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK (0x80000U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT (19U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT6_CLR_MASK (0x100000U) -#define SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT (20U) -#define SYSCON_STARTERCLR_FLEXINT6_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT6_CLR_MASK) -#define SYSCON_STARTERCLR_PLU_CLR_MASK (0x100000U) -#define SYSCON_STARTERCLR_PLU_CLR_SHIFT (20U) -#define SYSCON_STARTERCLR_PLU_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PLU_CLR_SHIFT)) & SYSCON_STARTERCLR_PLU_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT7_CLR_MASK (0x200000U) -#define SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT (21U) -#define SYSCON_STARTERCLR_FLEXINT7_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT7_CLR_MASK) -#define SYSCON_STARTERCLR_SEC_VIO_CLR_MASK (0x200000U) -#define SYSCON_STARTERCLR_SEC_VIO_CLR_SHIFT (21U) -#define SYSCON_STARTERCLR_SEC_VIO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_VIO_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_VIO_CLR_MASK) -#define SYSCON_STARTERCLR_ADC0_CLR_MASK (0x400000U) -#define SYSCON_STARTERCLR_ADC0_CLR_SHIFT (22U) -#define SYSCON_STARTERCLR_ADC0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_CLR_MASK) -#define SYSCON_STARTERCLR_SHA_CLR_MASK (0x400000U) -#define SYSCON_STARTERCLR_SHA_CLR_SHIFT (22U) -#define SYSCON_STARTERCLR_SHA_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SHA_CLR_SHIFT)) & SYSCON_STARTERCLR_SHA_CLR_MASK) -#define SYSCON_STARTERCLR_CASER_CLR_MASK (0x800000U) -#define SYSCON_STARTERCLR_CASER_CLR_SHIFT (23U) -#define SYSCON_STARTERCLR_CASER_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CASER_CLR_SHIFT)) & SYSCON_STARTERCLR_CASER_CLR_MASK) -#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK (0x1000000U) -#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT (24U) -#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK) -#define SYSCON_STARTERCLR_QDDKEY_CLR_MASK (0x1000000U) -#define SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT (24U) -#define SYSCON_STARTERCLR_QDDKEY_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT)) & SYSCON_STARTERCLR_QDDKEY_CLR_MASK) -#define SYSCON_STARTERCLR_PQ_CLR_MASK (0x2000000U) -#define SYSCON_STARTERCLR_PQ_CLR_SHIFT (25U) -#define SYSCON_STARTERCLR_PQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PQ_CLR_SHIFT)) & SYSCON_STARTERCLR_PQ_CLR_MASK) -#define SYSCON_STARTERCLR_SDMA1_CLR_MASK (0x4000000U) -#define SYSCON_STARTERCLR_SDMA1_CLR_SHIFT (26U) -#define SYSCON_STARTERCLR_SDMA1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA1_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA1_CLR_MASK) -#define SYSCON_STARTERCLR_LSPI_HS_CLR_MASK (0x8000000U) -#define SYSCON_STARTERCLR_LSPI_HS_CLR_SHIFT (27U) -#define SYSCON_STARTERCLR_LSPI_HS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_LSPI_HS_CLR_SHIFT)) & SYSCON_STARTERCLR_LSPI_HS_CLR_MASK) -#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK (0x8000000U) -#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT (27U) -#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK) -#define SYSCON_STARTERCLR_USB0_CLR_MASK (0x10000000U) -#define SYSCON_STARTERCLR_USB0_CLR_SHIFT (28U) -#define SYSCON_STARTERCLR_USB0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_CLR_MASK) -#define SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK (0x20000000U) -#define SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT (29U) -#define SYSCON_STARTERCLR_RTC_LITE0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT)) & SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK) -#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK (0x40000000U) -#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT (30U) -#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT)) & SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK) -#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK (0x80000000U) -#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT (31U) -#define SYSCON_STARTERCLR_WAKEUPPADS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK) -#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK (0x80000000U) -#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT (31U) -#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERCLR */ -#define SYSCON_STARTERCLR_COUNT (2U) - -/*! @name HARDWARESLEEP - Hardware Sleep control */ -/*! @{ */ -#define SYSCON_HARDWARESLEEP_FORCED_MASK (0x1U) -#define SYSCON_HARDWARESLEEP_FORCED_SHIFT (0U) -#define SYSCON_HARDWARESLEEP_FORCED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_FORCED_SHIFT)) & SYSCON_HARDWARESLEEP_FORCED_MASK) -#define SYSCON_HARDWARESLEEP_PERIPHERALS_MASK (0x2U) -#define SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT (1U) -#define SYSCON_HARDWARESLEEP_PERIPHERALS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT)) & SYSCON_HARDWARESLEEP_PERIPHERALS_MASK) -#define SYSCON_HARDWARESLEEP_SDMA0_MASK (0x8U) -#define SYSCON_HARDWARESLEEP_SDMA0_SHIFT (3U) -#define SYSCON_HARDWARESLEEP_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA0_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA0_MASK) -#define SYSCON_HARDWARESLEEP_SDMA1_MASK (0x20U) -#define SYSCON_HARDWARESLEEP_SDMA1_SHIFT (5U) -#define SYSCON_HARDWARESLEEP_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA1_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA1_MASK) -/*! @} */ - -/*! @name CPUCTRL - CPU Control for multiple processors */ -/*! @{ */ -#define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U) -#define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U) -/*! CPU1CLKEN - CPU1 clock enable. - * 0b1..The CPU1 clock is enabled. - * 0b0..The CPU1 clock is not enabled. - */ -#define SYSCON_CPUCTRL_CPU1CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK) -#define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U) -#define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U) -/*! CPU1RSTEN - CPU1 reset. - * 0b1..The CPU1 is being reset. - * 0b0..The CPU1 is not being reset. - */ -#define SYSCON_CPUCTRL_CPU1RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK) -/*! @} */ - -/*! @name CPBOOT - Coprocessor Boot Address */ -/*! @{ */ -#define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFFFFU) -#define SYSCON_CPBOOT_CPBOOT_SHIFT (0U) -#define SYSCON_CPBOOT_CPBOOT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK) -/*! @} */ - -/*! @name CPSTACK - Coprocessor Stack Address */ -/*! @{ */ -#define SYSCON_CPSTACK_CPSTACK_MASK (0xFFFFFFFFU) -#define SYSCON_CPSTACK_CPSTACK_SHIFT (0U) -#define SYSCON_CPSTACK_CPSTACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTACK_CPSTACK_SHIFT)) & SYSCON_CPSTACK_CPSTACK_MASK) -/*! @} */ - -/*! @name CPSTAT - CPU Status */ -/*! @{ */ -#define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U) -#define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U) -/*! CPU0SLEEPING - The CPU0 sleeping state. - * 0b1..the CPU is sleeping. - * 0b0..the CPU is not sleeping. - */ -#define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK) -#define SYSCON_CPSTAT_CPU1SLEEPING_MASK (0x2U) -#define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT (1U) -/*! CPU1SLEEPING - The CPU1 sleeping state. - * 0b1..the CPU is sleeping. - * 0b0..the CPU is not sleeping. - */ -#define SYSCON_CPSTAT_CPU1SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK) -#define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U) -#define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U) -/*! CPU0LOCKUP - The CPU0 lockup state. - * 0b1..the CPU is in lockup. - * 0b0..the CPU is not in lockup. - */ -#define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK) -#define SYSCON_CPSTAT_CPU1LOCKUP_MASK (0x8U) -#define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT (3U) -/*! CPU1LOCKUP - The CPU1 lockup state. - * 0b1..the CPU is in lockup. - * 0b0..the CPU is not in lockup. - */ -#define SYSCON_CPSTAT_CPU1LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK) -/*! @} */ - -/*! @name DICE_REG0 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG0_DICE_REG0_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG0_DICE_REG0_SHIFT (0U) -#define SYSCON_DICE_REG0_DICE_REG0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG0_DICE_REG0_SHIFT)) & SYSCON_DICE_REG0_DICE_REG0_MASK) -/*! @} */ - -/*! @name DICE_REG1 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG1_DICE_REG1_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG1_DICE_REG1_SHIFT (0U) -#define SYSCON_DICE_REG1_DICE_REG1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG1_DICE_REG1_SHIFT)) & SYSCON_DICE_REG1_DICE_REG1_MASK) -/*! @} */ - -/*! @name DICE_REG2 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG2_DICE_REG2_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG2_DICE_REG2_SHIFT (0U) -#define SYSCON_DICE_REG2_DICE_REG2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG2_DICE_REG2_SHIFT)) & SYSCON_DICE_REG2_DICE_REG2_MASK) -/*! @} */ - -/*! @name DICE_REG3 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG3_DICE_REG3_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG3_DICE_REG3_SHIFT (0U) -#define SYSCON_DICE_REG3_DICE_REG3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG3_DICE_REG3_SHIFT)) & SYSCON_DICE_REG3_DICE_REG3_MASK) -/*! @} */ - -/*! @name DICE_REG4 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG4_DICE_REG4_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG4_DICE_REG4_SHIFT (0U) -#define SYSCON_DICE_REG4_DICE_REG4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG4_DICE_REG4_SHIFT)) & SYSCON_DICE_REG4_DICE_REG4_MASK) -/*! @} */ - -/*! @name DICE_REG5 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG5_DICE_REG5_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG5_DICE_REG5_SHIFT (0U) -#define SYSCON_DICE_REG5_DICE_REG5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG5_DICE_REG5_SHIFT)) & SYSCON_DICE_REG5_DICE_REG5_MASK) -/*! @} */ - -/*! @name DICE_REG6 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG6_DICE_REG6_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG6_DICE_REG6_SHIFT (0U) -#define SYSCON_DICE_REG6_DICE_REG6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG6_DICE_REG6_SHIFT)) & SYSCON_DICE_REG6_DICE_REG6_MASK) -/*! @} */ - -/*! @name DICE_REG7 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG7_DICE_REG7_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG7_DICE_REG7_SHIFT (0U) -#define SYSCON_DICE_REG7_DICE_REG7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG7_DICE_REG7_SHIFT)) & SYSCON_DICE_REG7_DICE_REG7_MASK) -/*! @} */ - -/*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */ -/*! @{ */ -#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_MASK (0x1U) -#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_SHIFT (0U) -/*! FLASH48MHZ_ENA - Enable Flash 48 MHz clock. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_MASK) -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) -/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) -/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) -/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) -/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) -#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) -#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) -/*! CLKIN_ENA - Enable clock_in clock for clock module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) -/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) -/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) -/*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) -/*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK) -/*! @} */ - -/*! @name COMP_INT_CTRL - Comparator Interrupt control */ -/*! @{ */ -#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) -#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) -/*! INT_ENABLE - Analog Comparator interrupt enable control:. - * 0b1..interrupt enable. - * 0b0..interrupt disable. - */ -#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) -#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) -#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) -/*! INT_CLEAR - Analog Comparator interrupt clear. - * 0b0..No effect. - * 0b1..Clear the interrupt. Self-cleared bit. - */ -#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) -#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) -#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) -/*! INT_CTRL - Comparator interrupt type selector:. - * 0b000..The analog comparator interrupt edge sensitive is disabled. - * 0b010..analog comparator interrupt is rising edge sensitive. - * 0b100..analog comparator interrupt is falling edge sensitive. - * 0b110..analog comparator interrupt is rising and falling edge sensitive. - * 0b001..The analog comparator interrupt level sensitive is disabled. - * 0b011..Analog Comparator interrupt is high level sensitive. - * 0b101..Analog Comparator interrupt is low level sensitive. - * 0b111..The analog comparator interrupt level sensitive is disabled. - */ -#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) -#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) -#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) -/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. - * 0b0..Select Analog Comparator filtered output as input for interrupt detection. - * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when Analog comparator is used as wake up source in Power down mode. - */ -#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK) -/*! @} */ - -/*! @name COMP_INT_STATUS - Comparator Interrupt status */ -/*! @{ */ -#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) -#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) -/*! STATUS - Interrupt status BEFORE Interrupt Enable. - * 0b0..no interrupt pending. - * 0b1..interrupt pending. - */ -#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) -#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) -#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) -/*! INT_STATUS - Interrupt status AFTER Interrupt Enable. - * 0b0..no interrupt pending. - * 0b1..interrupt pending. - */ -#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) -#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) -#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) -/*! VAL - comparator analog output. - * 0b1..P+ is greater than P-. - * 0b0..P+ is smaller than P-. - */ -#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK) -/*! @} */ - -/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ -/*! @{ */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) -/*! ROM - Control automatic clock gating of ROM controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U) -/*! RAMX_CTRL - Control automatic clock gating of RAMX controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U) -/*! RAM0_CTRL - Control automatic clock gating of RAM0 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U) -/*! RAM1_CTRL - Control automatic clock gating of RAM1 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U) -/*! RAM2_CTRL - Control automatic clock gating of RAM2 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK (0x20U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT (5U) -/*! RAM3_CTRL - Control automatic clock gating of RAM3 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK (0x40U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT (6U) -/*! RAM4_CTRL - Control automatic clock gating of RAM4 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) -/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) -/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH_MASK (0x200U) -#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH_SHIFT (9U) -/*! FLASH - Control automatic clock gating of FLASH controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_FLASH_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_FLASH_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_FMC_MASK (0x400U) -#define SYSCON_AUTOCLKGATEOVERRIDE_FMC_SHIFT (10U) -/*! FMC - Control automatic clock gating of FMC controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_FMC_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_FMC_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) -/*! CRCGEN - Control automatic clock gating of CRCGEN controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) -/*! SDMA0 - Control automatic clock gating of DMA0 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) -/*! SDMA1 - Control automatic clock gating of DMA1 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_USB_MASK (0x4000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_USB_SHIFT (14U) -/*! USB - Control automatic clock gating of USB controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_USB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) -/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) -/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. - * 0b1100000011011110..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0000000000000000..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) -/*! @} */ - -/*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */ -/*! @{ */ -#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) -#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) -/*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. - * 0b1..bypass of the first stage of synchonization inside GPIO_INT module. - * 0b0..use the first stage of synchonization inside GPIO_INT module. - */ -#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) -/*! @} */ - -/*! @name DEBUG_LOCK_EN - Control write access to security registers -- FOR INTERNAl USE ONLY */ -/*! @{ */ -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) -/*! LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, CODESECURITYPROTCPU1, CM33_DEBUG_FEATURES, MCM33_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. - * 0b1010..1010: Enable write access to all 6 registers. - * 0b0000..Any other value than b1010: disable write access to all 6 registers. - */ -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) -/*! @} */ - -/*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY */ -/*! @{ */ -#define SYSCON_DEBUG_FEATURES_CM33_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_CM33_DBGEN_SHIFT (0U) -/*! CM33_DBGEN - CM33 (CPU0) Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_DBGEN_MASK) -#define SYSCON_DEBUG_FEATURES_CM33_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_CM33_NIDEN_SHIFT (2U) -/*! CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_NIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN_SHIFT (4U) -/*! CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_SPIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_SHIFT (6U) -/*! CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN_MASK (0x300U) -#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN_SHIFT (8U) -/*! MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_MCM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_MCM33_DBGEN_MASK) -#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN_MASK (0xC00U) -#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN_SHIFT (10U) -/*! MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_MCM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_MCM33_NIDEN_MASK) -/*! @} */ - -/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY */ -/*! @{ */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_SHIFT (0U) -/*! CM33_DBGEN - CM33 (CPU0) Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_SHIFT (2U) -/*! CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_SHIFT (4U) -/*! CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_SHIFT (6U) -/*! CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_MASK (0x300U) -#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_SHIFT (8U) -/*! MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_MASK (0xC00U) -#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_SHIFT (10U) -/*! MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_MASK) -/*! @} */ - -/*! @name CODESECURITYPROTTEST - Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY */ -/*! @{ */ -#define SYSCON_CODESECURITYPROTTEST_SEC_CODE_MASK (0xFFFFFFFFU) -#define SYSCON_CODESECURITYPROTTEST_SEC_CODE_SHIFT (0U) -/*! SEC_CODE - Security code to allow test access : 0x12345678. - * 0b00010010001101000101011001111000..Security code to allow test access. - * 0b00000000000000000000000000000000..test access is not allowed. - */ -#define SYSCON_CODESECURITYPROTTEST_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTTEST_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTTEST_SEC_CODE_MASK) -/*! @} */ - -/*! @name CODESECURITYPROTCPU0 - Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY */ -/*! @{ */ -#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE_MASK (0xFFFFFFFFU) -#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE_SHIFT (0U) -/*! SEC_CODE - Security code to allow CPU0 DAP: 0x12345678. - * 0b00010010001101000101011001111000..Security code to allow CPU0 DAP. - * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. - */ -#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTCPU0_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTCPU0_SEC_CODE_MASK) -/*! @} */ - -/*! @name CODESECURITYPROTCPU1 - Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY */ -/*! @{ */ -#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE_MASK (0xFFFFFFFFU) -#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE_SHIFT (0U) -/*! SEC_CODE - Security code to allow CPU1 DAP: 0x12345678. - * 0b00010010001101000101011001111000..Security code to allow CPU1 DAP. - * 0b00000000000000000000000000000000..CPU1 DAP is not allowed. - */ -#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTCPU1_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTCPU1_SEC_CODE_MASK) -/*! @} */ - -/*! @name KEY_BLOCK - block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY */ -/*! @{ */ -#define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU) -#define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U) -#define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK) -/*! @} */ - -/*! @name DEBUG_AUTH_SCRATCH - Debug authentication scratch registers -- FOR INTERNAL USE ONLY */ -/*! @{ */ -#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_MASK (0xFFFFFFFFU) -#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_SHIFT (0U) -#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_SHIFT)) & SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_MASK) -/*! @} */ - -/*! @name CPUCFG - CPUs configuration register */ -/*! @{ */ -#define SYSCON_CPUCFG_CPU1ENABLE_MASK (0x4U) -#define SYSCON_CPUCFG_CPU1ENABLE_SHIFT (2U) -/*! CPU1ENABLE - Enable CPU1. - * 0b0..CPU1 is disable (Processor in reset). - * 0b1..CPU1 is enable. - */ -#define SYSCON_CPUCFG_CPU1ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCFG_CPU1ENABLE_SHIFT)) & SYSCON_CPUCFG_CPU1ENABLE_MASK) -/*! @} */ - -/*! @name PERIPHENCFG - peripheral enable configuration -- FOR INTERNAL USE ONLY */ -/*! @{ */ -#define SYSCON_PERIPHENCFG_SCTEN_MASK (0x1U) -#define SYSCON_PERIPHENCFG_SCTEN_SHIFT (0U) -/*! SCTEN - SCT enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_SCTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_SCTEN_SHIFT)) & SYSCON_PERIPHENCFG_SCTEN_MASK) -#define SYSCON_PERIPHENCFG_ADCEN_MASK (0x2U) -#define SYSCON_PERIPHENCFG_ADCEN_SHIFT (1U) -/*! ADCEN - ADC enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_ADCEN_SHIFT)) & SYSCON_PERIPHENCFG_ADCEN_MASK) -#define SYSCON_PERIPHENCFG_USB0EN_MASK (0x4U) -#define SYSCON_PERIPHENCFG_USB0EN_SHIFT (2U) -/*! USB0EN - USB0 enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_USB0EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_USB0EN_SHIFT)) & SYSCON_PERIPHENCFG_USB0EN_MASK) -#define SYSCON_PERIPHENCFG_PUFFEN_MASK (0x40U) -#define SYSCON_PERIPHENCFG_PUFFEN_SHIFT (6U) -/*! PUFFEN - Puff enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_PUFFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_PUFFEN_SHIFT)) & SYSCON_PERIPHENCFG_PUFFEN_MASK) -#define SYSCON_PERIPHENCFG_USB1EN_MASK (0x400U) -#define SYSCON_PERIPHENCFG_USB1EN_SHIFT (10U) -/*! USB1EN - USB1 enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_USB1EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_USB1EN_SHIFT)) & SYSCON_PERIPHENCFG_USB1EN_MASK) -#define SYSCON_PERIPHENCFG_SDIOEN_MASK (0x800U) -#define SYSCON_PERIPHENCFG_SDIOEN_SHIFT (11U) -/*! SDIOEN - SDIO enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_SDIOEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_SDIOEN_SHIFT)) & SYSCON_PERIPHENCFG_SDIOEN_MASK) -#define SYSCON_PERIPHENCFG_HASHEN_MASK (0x1000U) -#define SYSCON_PERIPHENCFG_HASHEN_SHIFT (12U) -/*! HASHEN - HASH enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_HASHEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_HASHEN_SHIFT)) & SYSCON_PERIPHENCFG_HASHEN_MASK) -#define SYSCON_PERIPHENCFG_PRINCEEN_MASK (0x4000U) -#define SYSCON_PERIPHENCFG_PRINCEEN_SHIFT (14U) -/*! PRINCEEN - PRINCE enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_PRINCEEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_PRINCEEN_SHIFT)) & SYSCON_PERIPHENCFG_PRINCEEN_MASK) -/*! @} */ - -/*! @name DEVICE_ID0 - Device ID */ -/*! @{ */ -#define SYSCON_DEVICE_ID0_PARTCONFIG_MASK (0xFFU) -#define SYSCON_DEVICE_ID0_PARTCONFIG_SHIFT (0U) -#define SYSCON_DEVICE_ID0_PARTCONFIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTCONFIG_SHIFT)) & SYSCON_DEVICE_ID0_PARTCONFIG_MASK) -#define SYSCON_DEVICE_ID0_SRAM_SIZE_MASK (0xF00U) -#define SYSCON_DEVICE_ID0_SRAM_SIZE_SHIFT (8U) -#define SYSCON_DEVICE_ID0_SRAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_SRAM_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_SRAM_SIZE_MASK) -#define SYSCON_DEVICE_ID0_FLASH_SIZE_MASK (0x7000U) -#define SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT (12U) -#define SYSCON_DEVICE_ID0_FLASH_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_FLASH_SIZE_MASK) -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) -#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_MASK (0x7000000U) -#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_SHIFT (24U) -#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_SHIFT)) & SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_MASK) -/*! @} */ - -/*! @name DIEID - Chip revision ID and Number */ -/*! @{ */ -#define SYSCON_DIEID_REV_ID_MASK (0xFU) -#define SYSCON_DIEID_REV_ID_SHIFT (0U) -#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCON_Register_Masks */ - - -/* SYSCON - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral SYSCON base address */ - #define SYSCON_BASE (0x50000000u) - /** Peripheral SYSCON base address */ - #define SYSCON_BASE_NS (0x40000000u) - /** Peripheral SYSCON base pointer */ - #define SYSCON ((SYSCON_Type *)SYSCON_BASE) - /** Peripheral SYSCON base pointer */ - #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS { SYSCON_BASE } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS { SYSCON } - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS_NS { SYSCON_NS } -#else - /** Peripheral SYSCON base address */ - #define SYSCON_BASE (0x40000000u) - /** Peripheral SYSCON base pointer */ - #define SYSCON ((SYSCON_Type *)SYSCON_BASE) - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS { SYSCON_BASE } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS { SYSCON } -#endif - -/*! - * @} - */ /* end of group SYSCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCTL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer - * @{ - */ - -/** SYSCTL - Register Layout Typedef */ -typedef struct { - __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */ - uint8_t RESERVED_0[60]; - __IO uint32_t FCCTRLSEL[8]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_1[32]; - __IO uint32_t SHAREDCTRLSET[2]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[120]; - __I uint32_t USB_HS_STATUS; /**< Status register for USB HS, offset: 0x100 */ -} SYSCTL_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCTL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks - * @{ - */ - -/*! @name UPDATELCKOUT - update lock out control */ -/*! @{ */ -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) -/*! UPDATELCKOUT - All Registers - * 0b0..Normal Mode. Can be written to. - * 0b1..Protected Mode. Cannot be written to. - */ -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK) -/*! @} */ - -/*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */ -/*! @{ */ -#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) -#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) -/*! SCKINSEL - Selects the source for SCK going into this Flexcomm. - * 0b00..Selects the dedicated FCn_SCK function for this Flexcomm. - * 0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) -#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) -#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) -/*! WSINSEL - Selects the source for WS going into this Flexcomm. - * 0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. - * 0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) -#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) -#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) -/*! DATAINSEL - Selects the source for DATA input to this Flexcomm. - * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. - * 0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) -#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) -#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) -/*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm. - * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. - * 0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK) -/*! @} */ - -/* The count of SYSCTL_FCCTRLSEL */ -#define SYSCTL_FCCTRLSEL_COUNT (8U) - -/*! @name SHARECTRLSET_SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ -/*! @{ */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) -/*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set. - * 0b000..SCK for this shared signal set comes from Flexcomm 0. - * 0b001..SCK for this shared signal set comes from Flexcomm 1. - * 0b010..SCK for this shared signal set comes from Flexcomm 2. - * 0b011..SCK for this shared signal set comes from Flexcomm 3. - * 0b100..SCK for this shared signal set comes from Flexcomm 4. - * 0b101..SCK for this shared signal set comes from Flexcomm 5. - * 0b110..SCK for this shared signal set comes from Flexcomm 6. - * 0b111..SCK for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) -/*! SHAREDWSSEL - Selects the source for WS of this shared signal set. - * 0b000..WS for this shared signal set comes from Flexcomm 0. - * 0b001..WS for this shared signal set comes from Flexcomm 1. - * 0b010..WS for this shared signal set comes from Flexcomm 2. - * 0b011..WS for this shared signal set comes from Flexcomm 3. - * 0b100..WS for this shared signal set comes from Flexcomm 4. - * 0b101..WS for this shared signal set comes from Flexcomm 5. - * 0b110..WS for this shared signal set comes from Flexcomm 6. - * 0b111..WS for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) -/*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set. - * 0b000..DATA input for this shared signal set comes from Flexcomm 0. - * 0b001..DATA input for this shared signal set comes from Flexcomm 1. - * 0b010..DATA input for this shared signal set comes from Flexcomm 2. - * 0b011..DATA input for this shared signal set comes from Flexcomm 3. - * 0b100..DATA input for this shared signal set comes from Flexcomm 4. - * 0b101..DATA input for this shared signal set comes from Flexcomm 5. - * 0b110..DATA input for this shared signal set comes from Flexcomm 6. - * 0b111..DATA input for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) -/*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC0 does not contribute to this shared set. - * 0b1..Data output from FC0 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) -/*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC1 does not contribute to this shared set. - * 0b1..Data output from FC1 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK (0x40000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_SHIFT (18U) -/*! F20DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC2 does not contribute to this shared set. - * 0b1..Data output from FC2 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_MASK (0x80000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT (19U) -/*! FC3DATAOUTEN - Controls FC3 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC3 does not contribute to this shared set. - * 0b1..Data output from FC3 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) -/*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC4 does not contribute to this shared set. - * 0b1..Data output from FC4 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) -/*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC5 does not contribute to this shared set. - * 0b1..Data output from FC5 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) -/*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC6 does not contribute to this shared set. - * 0b1..Data output from FC6 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) -/*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC7 does not contribute to this shared set. - * 0b1..Data output from FC7 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK) -/*! @} */ - -/* The count of SYSCTL_SHARECTRLSET_SHAREDCTRLSET */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_COUNT (2U) - -/*! @name USB_HS_STATUS - Status register for USB HS */ -/*! @{ */ -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U) -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U) -/*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. - * 0b0..3v3 supply is good. - * 0b1..3v3 supply is too low. - */ -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCTL_Register_Masks */ - - -/* SYSCTL - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE (0x50023000u) - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE_NS (0x40023000u) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS { SYSCTL } - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } -#else - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE (0x40023000u) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS { SYSCTL } -#endif - -/*! - * @} - */ /* end of group SYSCTL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer - * @{ - */ - -/** USART - Register Layout Typedef */ -typedef struct { - __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ - __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ - __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ - uint8_t RESERVED_0[12]; - __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ - __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ - __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ - __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ - uint8_t RESERVED_1[3536]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_2[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_3[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_4[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_6[440]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} USART_Type; - -/* ---------------------------------------------------------------------------- - -- USART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Register_Masks USART Register Masks - * @{ - */ - -/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ -/*! @{ */ -#define USART_CFG_ENABLE_MASK (0x1U) -#define USART_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - USART Enable. - * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. - * 0b1..Enabled. The USART is enabled for operation. - */ -#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) -#define USART_CFG_DATALEN_MASK (0xCU) -#define USART_CFG_DATALEN_SHIFT (2U) -/*! DATALEN - Selects the data size for the USART. - * 0b00..7 bit Data length. - * 0b01..8 bit Data length. - * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. - * 0b11..Reserved. - */ -#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) -#define USART_CFG_PARITYSEL_MASK (0x30U) -#define USART_CFG_PARITYSEL_SHIFT (4U) -/*! PARITYSEL - Selects what type of parity is used by the USART. - * 0b00..No parity. - * 0b01..Reserved. - * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. - * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. - */ -#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) -#define USART_CFG_STOPLEN_MASK (0x40U) -#define USART_CFG_STOPLEN_SHIFT (6U) -/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. - * 0b0..1 stop bit. - * 0b1..2 stop bits. This setting should only be used for asynchronous communication. - */ -#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) -#define USART_CFG_MODE32K_MASK (0x80U) -#define USART_CFG_MODE32K_SHIFT (7U) -/*! MODE32K - Selects standard or 32 kHz clocking mode. - * 0b0..Disabled. USART uses standard clocking. - * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. - */ -#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) -#define USART_CFG_LINMODE_MASK (0x100U) -#define USART_CFG_LINMODE_SHIFT (8U) -/*! LINMODE - LIN break mode enable. - * 0b0..Disabled. Break detect and generate is configured for normal operation. - * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. - */ -#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) -#define USART_CFG_CTSEN_MASK (0x200U) -#define USART_CFG_CTSEN_SHIFT (9U) -/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. - * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. - * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. - */ -#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) -#define USART_CFG_SYNCEN_MASK (0x800U) -#define USART_CFG_SYNCEN_SHIFT (11U) -/*! SYNCEN - Selects synchronous or asynchronous operation. - * 0b0..Asynchronous mode. - * 0b1..Synchronous mode. - */ -#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) -#define USART_CFG_CLKPOL_MASK (0x1000U) -#define USART_CFG_CLKPOL_SHIFT (12U) -/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. - * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. - * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. - */ -#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) -#define USART_CFG_SYNCMST_MASK (0x4000U) -#define USART_CFG_SYNCMST_SHIFT (14U) -/*! SYNCMST - Synchronous mode Master select. - * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. - * 0b1..Master. When synchronous mode is enabled, the USART is a master. - */ -#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) -#define USART_CFG_LOOP_MASK (0x8000U) -#define USART_CFG_LOOP_SHIFT (15U) -/*! LOOP - Selects data loopback mode. - * 0b0..Normal operation. - * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. - */ -#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) -#define USART_CFG_OETA_MASK (0x40000U) -#define USART_CFG_OETA_SHIFT (18U) -/*! OETA - Output Enable Turnaround time enable for RS-485 operation. - * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. - * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. - */ -#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) -#define USART_CFG_AUTOADDR_MASK (0x80000U) -#define USART_CFG_AUTOADDR_SHIFT (19U) -/*! AUTOADDR - Automatic Address matching enable. - * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). - * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. - */ -#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) -#define USART_CFG_OESEL_MASK (0x100000U) -#define USART_CFG_OESEL_SHIFT (20U) -/*! OESEL - Output Enable Select. - * 0b0..Standard. The RTS signal is used as the standard flow control function. - * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. - */ -#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) -#define USART_CFG_OEPOL_MASK (0x200000U) -#define USART_CFG_OEPOL_SHIFT (21U) -/*! OEPOL - Output Enable Polarity. - * 0b0..Low. If selected by OESEL, the output enable is active low. - * 0b1..High. If selected by OESEL, the output enable is active high. - */ -#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) -#define USART_CFG_RXPOL_MASK (0x400000U) -#define USART_CFG_RXPOL_SHIFT (22U) -/*! RXPOL - Receive data polarity. - * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. - * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. - */ -#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) -#define USART_CFG_TXPOL_MASK (0x800000U) -#define USART_CFG_TXPOL_SHIFT (23U) -/*! TXPOL - Transmit data polarity. - * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. - * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. - */ -#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) -/*! @} */ - -/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ -/*! @{ */ -#define USART_CTL_TXBRKEN_MASK (0x2U) -#define USART_CTL_TXBRKEN_SHIFT (1U) -/*! TXBRKEN - Break Enable. - * 0b0..Normal operation. - * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. - */ -#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) -#define USART_CTL_ADDRDET_MASK (0x4U) -#define USART_CTL_ADDRDET_SHIFT (2U) -/*! ADDRDET - Enable address detect mode. - * 0b0..Disabled. The USART presents all incoming data. - * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. - */ -#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) -#define USART_CTL_TXDIS_MASK (0x40U) -#define USART_CTL_TXDIS_SHIFT (6U) -/*! TXDIS - Transmit Disable. - * 0b0..Not disabled. USART transmitter is not disabled. - * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. - */ -#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) -#define USART_CTL_CC_MASK (0x100U) -#define USART_CTL_CC_SHIFT (8U) -/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. - * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. - * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). - */ -#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) -#define USART_CTL_CLRCCONRX_MASK (0x200U) -#define USART_CTL_CLRCCONRX_SHIFT (9U) -/*! CLRCCONRX - Clear Continuous Clock. - * 0b0..No effect. No effect on the CC bit. - * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. - */ -#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) -#define USART_CTL_AUTOBAUD_MASK (0x10000U) -#define USART_CTL_AUTOBAUD_SHIFT (16U) -/*! AUTOBAUD - Autobaud enable. - * 0b0..Disabled. USART is in normal operating mode. - * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. - */ -#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) -/*! @} */ - -/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ -/*! @{ */ -#define USART_STAT_RXIDLE_MASK (0x2U) -#define USART_STAT_RXIDLE_SHIFT (1U) -#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) -#define USART_STAT_TXIDLE_MASK (0x8U) -#define USART_STAT_TXIDLE_SHIFT (3U) -#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) -#define USART_STAT_CTS_MASK (0x10U) -#define USART_STAT_CTS_SHIFT (4U) -#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) -#define USART_STAT_DELTACTS_MASK (0x20U) -#define USART_STAT_DELTACTS_SHIFT (5U) -#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) -#define USART_STAT_TXDISSTAT_MASK (0x40U) -#define USART_STAT_TXDISSTAT_SHIFT (6U) -#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) -#define USART_STAT_RXBRK_MASK (0x400U) -#define USART_STAT_RXBRK_SHIFT (10U) -#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) -#define USART_STAT_DELTARXBRK_MASK (0x800U) -#define USART_STAT_DELTARXBRK_SHIFT (11U) -#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) -#define USART_STAT_START_MASK (0x1000U) -#define USART_STAT_START_SHIFT (12U) -#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) -#define USART_STAT_FRAMERRINT_MASK (0x2000U) -#define USART_STAT_FRAMERRINT_SHIFT (13U) -#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) -#define USART_STAT_PARITYERRINT_MASK (0x4000U) -#define USART_STAT_PARITYERRINT_SHIFT (14U) -#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) -#define USART_STAT_RXNOISEINT_MASK (0x8000U) -#define USART_STAT_RXNOISEINT_SHIFT (15U) -#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) -#define USART_STAT_ABERR_MASK (0x10000U) -#define USART_STAT_ABERR_SHIFT (16U) -#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ -#define USART_INTENSET_TXIDLEEN_MASK (0x8U) -#define USART_INTENSET_TXIDLEEN_SHIFT (3U) -#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) -#define USART_INTENSET_DELTACTSEN_MASK (0x20U) -#define USART_INTENSET_DELTACTSEN_SHIFT (5U) -#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) -#define USART_INTENSET_TXDISEN_MASK (0x40U) -#define USART_INTENSET_TXDISEN_SHIFT (6U) -#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) -#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) -#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) -#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) -#define USART_INTENSET_STARTEN_MASK (0x1000U) -#define USART_INTENSET_STARTEN_SHIFT (12U) -#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) -#define USART_INTENSET_FRAMERREN_MASK (0x2000U) -#define USART_INTENSET_FRAMERREN_SHIFT (13U) -#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) -#define USART_INTENSET_PARITYERREN_MASK (0x4000U) -#define USART_INTENSET_PARITYERREN_SHIFT (14U) -#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) -#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) -#define USART_INTENSET_RXNOISEEN_SHIFT (15U) -#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) -#define USART_INTENSET_ABERREN_MASK (0x10000U) -#define USART_INTENSET_ABERREN_SHIFT (16U) -#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ -/*! @{ */ -#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) -#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) -#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) -#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) -#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) -#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) -#define USART_INTENCLR_TXDISCLR_MASK (0x40U) -#define USART_INTENCLR_TXDISCLR_SHIFT (6U) -#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) -#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) -#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) -#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) -#define USART_INTENCLR_STARTCLR_MASK (0x1000U) -#define USART_INTENCLR_STARTCLR_SHIFT (12U) -#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) -#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) -#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) -#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) -#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) -#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) -#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) -#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) -#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) -#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) -#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) -#define USART_INTENCLR_ABERRCLR_SHIFT (16U) -#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) -/*! @} */ - -/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ -/*! @{ */ -#define USART_BRG_BRGVAL_MASK (0xFFFFU) -#define USART_BRG_BRGVAL_SHIFT (0U) -#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ -/*! @{ */ -#define USART_INTSTAT_TXIDLE_MASK (0x8U) -#define USART_INTSTAT_TXIDLE_SHIFT (3U) -#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) -#define USART_INTSTAT_DELTACTS_MASK (0x20U) -#define USART_INTSTAT_DELTACTS_SHIFT (5U) -#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) -#define USART_INTSTAT_TXDISINT_MASK (0x40U) -#define USART_INTSTAT_TXDISINT_SHIFT (6U) -#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) -#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) -#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) -#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) -#define USART_INTSTAT_START_MASK (0x1000U) -#define USART_INTSTAT_START_SHIFT (12U) -#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) -#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) -#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) -#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) -#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) -#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) -#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) -#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) -#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) -#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) -#define USART_INTSTAT_ABERRINT_MASK (0x10000U) -#define USART_INTSTAT_ABERRINT_SHIFT (16U) -#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) -/*! @} */ - -/*! @name OSR - Oversample selection register for asynchronous communication. */ -/*! @{ */ -#define USART_OSR_OSRVAL_MASK (0xFU) -#define USART_OSR_OSRVAL_SHIFT (0U) -#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) -/*! @} */ - -/*! @name ADDR - Address register for automatic address matching. */ -/*! @{ */ -#define USART_ADDR_ADDRESS_MASK (0xFFU) -#define USART_ADDR_ADDRESS_SHIFT (0U) -#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ -#define USART_FIFOCFG_ENABLETX_MASK (0x1U) -#define USART_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) -#define USART_FIFOCFG_ENABLERX_MASK (0x2U) -#define USART_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) -#define USART_FIFOCFG_SIZE_MASK (0x30U) -#define USART_FIFOCFG_SIZE_SHIFT (4U) -#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) -#define USART_FIFOCFG_DMATX_MASK (0x1000U) -#define USART_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) -#define USART_FIFOCFG_DMARX_MASK (0x2000U) -#define USART_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) -#define USART_FIFOCFG_WAKETX_MASK (0x4000U) -#define USART_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) -#define USART_FIFOCFG_WAKERX_MASK (0x8000U) -#define USART_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) -#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) -#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) -#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) -#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) -#define USART_FIFOCFG_POPDBG_MASK (0x40000U) -#define USART_FIFOCFG_POPDBG_SHIFT (18U) -/*! POPDBG - Pop FIFO for debug reads. - * 0b0..Debug reads of the FIFO do not pop the FIFO. - * 0b1..A debug read will cause the FIFO to pop. - */ -#define USART_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ -#define USART_FIFOSTAT_TXERR_MASK (0x1U) -#define USART_FIFOSTAT_TXERR_SHIFT (0U) -#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) -#define USART_FIFOSTAT_RXERR_MASK (0x2U) -#define USART_FIFOSTAT_RXERR_SHIFT (1U) -#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) -#define USART_FIFOSTAT_PERINT_MASK (0x8U) -#define USART_FIFOSTAT_PERINT_SHIFT (3U) -#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) -#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) -#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) -#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) -#define USART_FIFOSTAT_RXFULL_MASK (0x80U) -#define USART_FIFOSTAT_RXFULL_SHIFT (7U) -#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) -#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define USART_FIFOSTAT_TXLVL_SHIFT (8U) -#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) -#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define USART_FIFOSTAT_RXLVL_SHIFT (16U) -#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ -#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) -#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) -#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) -#define USART_FIFOTRIG_TXLVL_SHIFT (8U) -#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) -#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define USART_FIFOTRIG_RXLVL_SHIFT (16U) -#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ -#define USART_FIFOINTENSET_TXERR_MASK (0x1U) -#define USART_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) -#define USART_FIFOINTENSET_RXERR_MASK (0x2U) -#define USART_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) -#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) -#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - */ -#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) -#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) -#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ -#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) -#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) -#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) -#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) -#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) -#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) -#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) -#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ -#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) -#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) -#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) -#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) -#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) -#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) -#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) -#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) -#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) -#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) -#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ -#define USART_FIFOWR_TXDATA_MASK (0x1FFU) -#define USART_FIFOWR_TXDATA_SHIFT (0U) -#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ -#define USART_FIFORD_RXDATA_MASK (0x1FFU) -#define USART_FIFORD_RXDATA_SHIFT (0U) -#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) -#define USART_FIFORD_FRAMERR_MASK (0x2000U) -#define USART_FIFORD_FRAMERR_SHIFT (13U) -#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) -#define USART_FIFORD_PARITYERR_MASK (0x4000U) -#define USART_FIFORD_PARITYERR_SHIFT (14U) -#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) -#define USART_FIFORD_RXNOISE_MASK (0x8000U) -#define USART_FIFORD_RXNOISE_SHIFT (15U) -#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ -#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) -#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) -#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) -#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) -#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) -#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) -#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) -#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) -#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) -#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) -#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ -#define USART_ID_APERTURE_MASK (0xFFU) -#define USART_ID_APERTURE_SHIFT (0U) -#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) -#define USART_ID_MINOR_REV_MASK (0xF00U) -#define USART_ID_MINOR_REV_SHIFT (8U) -#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) -#define USART_ID_MAJOR_REV_MASK (0xF000U) -#define USART_ID_MAJOR_REV_SHIFT (12U) -#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) -#define USART_ID_ID_MASK (0xFFFF0000U) -#define USART_ID_ID_SHIFT (16U) -#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USART_Register_Masks */ - - -/* USART - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral USART0 base address */ - #define USART0_BASE (0x50086000u) - /** Peripheral USART0 base address */ - #define USART0_BASE_NS (0x40086000u) - /** Peripheral USART0 base pointer */ - #define USART0 ((USART_Type *)USART0_BASE) - /** Peripheral USART0 base pointer */ - #define USART0_NS ((USART_Type *)USART0_BASE_NS) - /** Peripheral USART1 base address */ - #define USART1_BASE (0x50087000u) - /** Peripheral USART1 base address */ - #define USART1_BASE_NS (0x40087000u) - /** Peripheral USART1 base pointer */ - #define USART1 ((USART_Type *)USART1_BASE) - /** Peripheral USART1 base pointer */ - #define USART1_NS ((USART_Type *)USART1_BASE_NS) - /** Peripheral USART2 base address */ - #define USART2_BASE (0x50088000u) - /** Peripheral USART2 base address */ - #define USART2_BASE_NS (0x40088000u) - /** Peripheral USART2 base pointer */ - #define USART2 ((USART_Type *)USART2_BASE) - /** Peripheral USART2 base pointer */ - #define USART2_NS ((USART_Type *)USART2_BASE_NS) - /** Peripheral USART3 base address */ - #define USART3_BASE (0x50089000u) - /** Peripheral USART3 base address */ - #define USART3_BASE_NS (0x40089000u) - /** Peripheral USART3 base pointer */ - #define USART3 ((USART_Type *)USART3_BASE) - /** Peripheral USART3 base pointer */ - #define USART3_NS ((USART_Type *)USART3_BASE_NS) - /** Peripheral USART4 base address */ - #define USART4_BASE (0x5008A000u) - /** Peripheral USART4 base address */ - #define USART4_BASE_NS (0x4008A000u) - /** Peripheral USART4 base pointer */ - #define USART4 ((USART_Type *)USART4_BASE) - /** Peripheral USART4 base pointer */ - #define USART4_NS ((USART_Type *)USART4_BASE_NS) - /** Peripheral USART5 base address */ - #define USART5_BASE (0x50096000u) - /** Peripheral USART5 base address */ - #define USART5_BASE_NS (0x40096000u) - /** Peripheral USART5 base pointer */ - #define USART5 ((USART_Type *)USART5_BASE) - /** Peripheral USART5 base pointer */ - #define USART5_NS ((USART_Type *)USART5_BASE_NS) - /** Peripheral USART6 base address */ - #define USART6_BASE (0x50097000u) - /** Peripheral USART6 base address */ - #define USART6_BASE_NS (0x40097000u) - /** Peripheral USART6 base pointer */ - #define USART6 ((USART_Type *)USART6_BASE) - /** Peripheral USART6 base pointer */ - #define USART6_NS ((USART_Type *)USART6_BASE_NS) - /** Peripheral USART7 base address */ - #define USART7_BASE (0x50098000u) - /** Peripheral USART7 base address */ - #define USART7_BASE_NS (0x40098000u) - /** Peripheral USART7 base pointer */ - #define USART7 ((USART_Type *)USART7_BASE) - /** Peripheral USART7 base pointer */ - #define USART7_NS ((USART_Type *)USART7_BASE_NS) - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } -#else - /** Peripheral USART0 base address */ - #define USART0_BASE (0x40086000u) - /** Peripheral USART0 base pointer */ - #define USART0 ((USART_Type *)USART0_BASE) - /** Peripheral USART1 base address */ - #define USART1_BASE (0x40087000u) - /** Peripheral USART1 base pointer */ - #define USART1 ((USART_Type *)USART1_BASE) - /** Peripheral USART2 base address */ - #define USART2_BASE (0x40088000u) - /** Peripheral USART2 base pointer */ - #define USART2 ((USART_Type *)USART2_BASE) - /** Peripheral USART3 base address */ - #define USART3_BASE (0x40089000u) - /** Peripheral USART3 base pointer */ - #define USART3 ((USART_Type *)USART3_BASE) - /** Peripheral USART4 base address */ - #define USART4_BASE (0x4008A000u) - /** Peripheral USART4 base pointer */ - #define USART4 ((USART_Type *)USART4_BASE) - /** Peripheral USART5 base address */ - #define USART5_BASE (0x40096000u) - /** Peripheral USART5 base pointer */ - #define USART5 ((USART_Type *)USART5_BASE) - /** Peripheral USART6 base address */ - #define USART6_BASE (0x40097000u) - /** Peripheral USART6 base pointer */ - #define USART6 ((USART_Type *)USART6_BASE) - /** Peripheral USART7 base address */ - #define USART7_BASE (0x40098000u) - /** Peripheral USART7 base pointer */ - #define USART7 ((USART_Type *)USART7_BASE) - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } -#endif -/** Interrupt vectors for the USART peripheral type */ -#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group USART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer - * @{ - */ - -/** USB - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ - __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ -} USB_Type; - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status register */ -/*! @{ */ -#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) -#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) -#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) -#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) -#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: - * 0b0..USB_NEEDCLK has normal function. - * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. - */ -#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) -#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -/*! LPM_SUP - LPM Supported: - * 0b0..LPM not supported. - * 0b1..LPM supported. - */ -#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) -#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) -#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) -#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -/*! INTONNAK_CO - Interrupt on NAK for control OUT EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) -#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -/*! INTONNAK_CI - Interrupt on NAK for control IN EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) -#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USB_DEVCMDSTAT_DCON_SHIFT (16U) -#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) -#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) -#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) -#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) -#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) -#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) -#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) -#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) -#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) -#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) -#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) -/*! @} */ - -/*! @name INFO - USB Info register */ -/*! @{ */ -#define USB_INFO_FRAME_NR_MASK (0x7FFU) -#define USB_INFO_FRAME_NR_SHIFT (0U) -#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) -#define USB_INFO_ERR_CODE_MASK (0x7800U) -#define USB_INFO_ERR_CODE_SHIFT (11U) -/*! ERR_CODE - The error code which last occurred: - * 0b0000..No error - * 0b0001..PID encoding error - * 0b0010..PID unknown - * 0b0011..Packet unexpected - * 0b0100..Token CRC error - * 0b0101..Data CRC error - * 0b0110..Time out - * 0b0111..Babble - * 0b1000..Truncated EOP - * 0b1001..Sent/Received NAK - * 0b1010..Sent Stall - * 0b1011..Overrun - * 0b1100..Sent empty packet - * 0b1101..Bitstuff error - * 0b1110..Sync error - * 0b1111..Wrong data toggle - */ -#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) -#define USB_INFO_MINREV_MASK (0xFF0000U) -#define USB_INFO_MINREV_SHIFT (16U) -#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) -#define USB_INFO_MAJREV_MASK (0xFF000000U) -#define USB_INFO_MAJREV_SHIFT (24U) -#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) -/*! @} */ - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -/*! @{ */ -#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) -#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) -#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) -/*! @} */ - -/*! @name DATABUFSTART - USB Data buffer start address */ -/*! @{ */ -#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) -#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) -#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) -/*! @} */ - -/*! @name LPM - USB Link Power Management register */ -/*! @{ */ -#define USB_LPM_HIRD_HW_MASK (0xFU) -#define USB_LPM_HIRD_HW_SHIFT (0U) -#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) -#define USB_LPM_HIRD_SW_MASK (0xF0U) -#define USB_LPM_HIRD_SW_SHIFT (4U) -#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) -#define USB_LPM_DATA_PENDING_MASK (0x100U) -#define USB_LPM_DATA_PENDING_SHIFT (8U) -#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) -/*! @} */ - -/*! @name EPSKIP - USB Endpoint skip */ -/*! @{ */ -#define USB_EPSKIP_SKIP_MASK (0x3FFU) -#define USB_EPSKIP_SKIP_SHIFT (0U) -#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) -/*! @} */ - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -/*! @{ */ -#define USB_EPINUSE_BUF_MASK (0x3FCU) -#define USB_EPINUSE_BUF_SHIFT (2U) -#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) -/*! @} */ - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ -/*! @{ */ -#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) -#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) -#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) -/*! @} */ - -/*! @name INTSTAT - USB interrupt status register */ -/*! @{ */ -#define USB_INTSTAT_EP0OUT_MASK (0x1U) -#define USB_INTSTAT_EP0OUT_SHIFT (0U) -#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) -#define USB_INTSTAT_EP0IN_MASK (0x2U) -#define USB_INTSTAT_EP0IN_SHIFT (1U) -#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) -#define USB_INTSTAT_EP1OUT_MASK (0x4U) -#define USB_INTSTAT_EP1OUT_SHIFT (2U) -#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) -#define USB_INTSTAT_EP1IN_MASK (0x8U) -#define USB_INTSTAT_EP1IN_SHIFT (3U) -#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) -#define USB_INTSTAT_EP2OUT_MASK (0x10U) -#define USB_INTSTAT_EP2OUT_SHIFT (4U) -#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) -#define USB_INTSTAT_EP2IN_MASK (0x20U) -#define USB_INTSTAT_EP2IN_SHIFT (5U) -#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) -#define USB_INTSTAT_EP3OUT_MASK (0x40U) -#define USB_INTSTAT_EP3OUT_SHIFT (6U) -#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) -#define USB_INTSTAT_EP3IN_MASK (0x80U) -#define USB_INTSTAT_EP3IN_SHIFT (7U) -#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) -#define USB_INTSTAT_EP4OUT_MASK (0x100U) -#define USB_INTSTAT_EP4OUT_SHIFT (8U) -#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) -#define USB_INTSTAT_EP4IN_MASK (0x200U) -#define USB_INTSTAT_EP4IN_SHIFT (9U) -#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) -#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USB_INTSTAT_FRAME_INT_SHIFT (30U) -#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) -#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USB_INTSTAT_DEV_INT_SHIFT (31U) -#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) -/*! @} */ - -/*! @name INTEN - USB interrupt enable register */ -/*! @{ */ -#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) -#define USB_INTEN_EP_INT_EN_SHIFT (0U) -#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) -#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) -#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) -#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USB_INTEN_DEV_INT_EN_SHIFT (31U) -#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) -/*! @} */ - -/*! @name INTSETSTAT - USB set interrupt status register */ -/*! @{ */ -#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) -#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) -#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) -#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) -#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) -/*! @} */ - -/*! @name EPTOGGLE - USB Endpoint toggle register */ -/*! @{ */ -#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) -#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) -#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USB_Register_Masks */ - - -/* USB - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral USB0 base address */ - #define USB0_BASE (0x50084000u) - /** Peripheral USB0 base address */ - #define USB0_BASE_NS (0x40084000u) - /** Peripheral USB0 base pointer */ - #define USB0 ((USB_Type *)USB0_BASE) - /** Peripheral USB0 base pointer */ - #define USB0_NS ((USB_Type *)USB0_BASE_NS) - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS { USB0_BASE } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS { USB0 } - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS_NS { USB0_BASE_NS } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS_NS { USB0_NS } -#else - /** Peripheral USB0 base address */ - #define USB0_BASE (0x40084000u) - /** Peripheral USB0 base pointer */ - #define USB0 ((USB_Type *)USB0_BASE) - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS { USB0_BASE } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS { USB0 } -#endif -/** Interrupt vectors for the USB peripheral type */ -#define USB_IRQS { USB0_IRQn } -#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBFSH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer - * @{ - */ - -/** USBFSH - Register Layout Typedef */ -typedef struct { - __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */ - __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */ - __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */ - __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */ - __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ - __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ - __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ - __IO uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ - __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ - __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ - __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ - __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ - __IO uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ - __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ - __IO uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ - __IO uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ - __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ - __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ - __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ - __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */ - __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */ - __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */ - uint8_t RESERVED_0[4]; - __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */ -} USBFSH_Type; - -/* ---------------------------------------------------------------------------- - -- USBFSH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBFSH_Register_Masks USBFSH Register Masks - * @{ - */ - -/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ -/*! @{ */ -#define USBFSH_HCREVISION_REV_MASK (0xFFU) -#define USBFSH_HCREVISION_REV_SHIFT (0U) -#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) -/*! @} */ - -/*! @name HCCONTROL - Defines the operating modes of the HC */ -/*! @{ */ -#define USBFSH_HCCONTROL_CBSR_MASK (0x3U) -#define USBFSH_HCCONTROL_CBSR_SHIFT (0U) -#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) -#define USBFSH_HCCONTROL_PLE_MASK (0x4U) -#define USBFSH_HCCONTROL_PLE_SHIFT (2U) -#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) -#define USBFSH_HCCONTROL_IE_MASK (0x8U) -#define USBFSH_HCCONTROL_IE_SHIFT (3U) -#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) -#define USBFSH_HCCONTROL_CLE_MASK (0x10U) -#define USBFSH_HCCONTROL_CLE_SHIFT (4U) -#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) -#define USBFSH_HCCONTROL_BLE_MASK (0x20U) -#define USBFSH_HCCONTROL_BLE_SHIFT (5U) -#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) -#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) -#define USBFSH_HCCONTROL_HCFS_SHIFT (6U) -#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) -#define USBFSH_HCCONTROL_IR_MASK (0x100U) -#define USBFSH_HCCONTROL_IR_SHIFT (8U) -#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) -#define USBFSH_HCCONTROL_RWC_MASK (0x200U) -#define USBFSH_HCCONTROL_RWC_SHIFT (9U) -#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) -#define USBFSH_HCCONTROL_RWE_MASK (0x400U) -#define USBFSH_HCCONTROL_RWE_SHIFT (10U) -#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) -/*! @} */ - -/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ -/*! @{ */ -#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) -#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) -#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) -#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) -#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) -#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) -#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) -#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) -#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) -#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) -#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) -#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) -#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) -#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) -#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) -/*! @} */ - -/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ -/*! @{ */ -#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) -#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) -#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) -#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) -#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) -#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) -#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) -#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) -#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) -#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) -#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) -#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) -#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) -#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) -#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) -#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) -#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) -/*! @} */ - -/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ -/*! @{ */ -#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) -#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) -#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) -#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) -#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) -#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) -#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) -#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) -#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) -#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) -#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) -#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) -#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) -#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) -#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) -#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) -#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) -#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) -#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) -#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) -/*! @} */ - -/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ -/*! @{ */ -#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) -#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) -#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) -#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) -#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) -#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) -#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) -#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) -#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) -#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) -#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) -#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) -#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) -#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) -#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) -#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) -#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) -#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) -#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) -#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) -/*! @} */ - -/*! @name HCHCCA - Contains the physical address of the host controller communication area */ -/*! @{ */ -#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) -#define USBFSH_HCHCCA_HCCA_SHIFT (8U) -#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) -/*! @} */ - -/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ -/*! @{ */ -#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) -#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) -/*! @} */ - -/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ -/*! @{ */ -#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) -#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) -#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) -/*! @} */ - -/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ -/*! @{ */ -#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) -#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) -/*! @} */ - -/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ -/*! @{ */ -#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) -#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) -#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) -/*! @} */ - -/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ -/*! @{ */ -#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) -#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) -/*! @} */ - -/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ -/*! @{ */ -#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) -#define USBFSH_HCDONEHEAD_DH_SHIFT (4U) -#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) -/*! @} */ - -/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ -/*! @{ */ -#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) -#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) -#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) -#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) -#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) -#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) -#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) -#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) -#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) -/*! @} */ - -/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ -/*! @{ */ -#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) -#define USBFSH_HCFMREMAINING_FR_SHIFT (0U) -#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) -#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) -#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) -#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) -/*! @} */ - -/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ -/*! @{ */ -#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) -#define USBFSH_HCFMNUMBER_FN_SHIFT (0U) -#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) -/*! @} */ - -/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ -/*! @{ */ -#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) -#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) -#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) -/*! @} */ - -/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ -/*! @{ */ -#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) -#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) -#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) -/*! @} */ - -/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ -/*! @{ */ -#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) -#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) -#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) -#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) -#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) -#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) -#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) -#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) -#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) -#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) -#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) -#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) -#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) -#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) -#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) -#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) -#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) -#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) -#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) -#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) -#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) -/*! @} */ - -/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ -/*! @{ */ -#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) -#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) -#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) -#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) -#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) -#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) -/*! @} */ - -/*! @name HCRHSTATUS - This register is divided into two parts */ -/*! @{ */ -#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) -#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) -#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) -#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) -#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) -#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) -#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) -#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) -#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) -#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) -#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) -#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) -#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) -#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) -#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) -#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) -#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) -#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) -/*! @} */ - -/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ -/*! @{ */ -#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) -#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) -#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) -#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) -#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) -#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) -#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) -#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) -#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) -#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) -#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) -#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) -#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) -#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) -#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) -#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) -#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) -#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) -#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) -#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) -#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) -#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) -#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) -#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) -#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) -#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) -#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) -#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) -#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) -#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) -#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) -#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) -#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) -#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) -#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) -#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) -/*! @} */ - -/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ -/*! @{ */ -#define USBFSH_PORTMODE_ID_MASK (0x1U) -#define USBFSH_PORTMODE_ID_SHIFT (0U) -#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) -#define USBFSH_PORTMODE_ID_EN_MASK (0x100U) -#define USBFSH_PORTMODE_ID_EN_SHIFT (8U) -#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) -#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) -#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) -#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBFSH_Register_Masks */ - - -/* USBFSH - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral USBFSH base address */ - #define USBFSH_BASE (0x500A2000u) - /** Peripheral USBFSH base address */ - #define USBFSH_BASE_NS (0x400A2000u) - /** Peripheral USBFSH base pointer */ - #define USBFSH ((USBFSH_Type *)USBFSH_BASE) - /** Peripheral USBFSH base pointer */ - #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS) - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS { USBFSH_BASE } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS { USBFSH } - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS_NS { USBFSH_NS } -#else - /** Peripheral USBFSH base address */ - #define USBFSH_BASE (0x400A2000u) - /** Peripheral USBFSH base pointer */ - #define USBFSH ((USBFSH_Type *)USBFSH_BASE) - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS { USBFSH_BASE } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS { USBFSH } -#endif -/** Interrupt vectors for the USBFSH peripheral type */ -#define USBFSH_IRQS { USB0_IRQn } -#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBFSH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBHSD Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer - * @{ - */ - -/** USBHSD - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ - __I uint32_t INFO; /**< USB Info register, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ - uint8_t RESERVED_1[4]; - __IO uint32_t ULPIDEBUG; /**< UTMI/ULPI debug register, offset: 0x3C */ -} USBHSD_Type; - -/* ---------------------------------------------------------------------------- - -- USBHSD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSD_Register_Masks USBHSD Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status register */ -/*! @{ */ -#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) -#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) -#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) -#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) -#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) -#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK (0x400U) -#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT (10U) -#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK) -#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) -#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) -#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) -#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) -#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) -#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) -#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) -#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) -#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) -#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) -#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) -#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) -#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) -#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) -#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) -#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) -#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) -#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) -#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) -#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) -/*! @} */ - -/*! @name INFO - USB Info register */ -/*! @{ */ -#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) -#define USBHSD_INFO_FRAME_NR_SHIFT (0U) -#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) -#define USBHSD_INFO_ERR_CODE_MASK (0x7800U) -#define USBHSD_INFO_ERR_CODE_SHIFT (11U) -#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) -#define USBHSD_INFO_Minrev_MASK (0xFF0000U) -#define USBHSD_INFO_Minrev_SHIFT (16U) -#define USBHSD_INFO_Minrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK) -#define USBHSD_INFO_Majrev_MASK (0xFF000000U) -#define USBHSD_INFO_Majrev_SHIFT (24U) -#define USBHSD_INFO_Majrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK) -/*! @} */ - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -/*! @{ */ -#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) -#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) -#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) -#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) -#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) -#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) -/*! @} */ - -/*! @name DATABUFSTART - USB Data buffer start address */ -/*! @{ */ -#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) -#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) -#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) -/*! @} */ - -/*! @name LPM - USB Link Power Management register */ -/*! @{ */ -#define USBHSD_LPM_HIRD_HW_MASK (0xFU) -#define USBHSD_LPM_HIRD_HW_SHIFT (0U) -#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) -#define USBHSD_LPM_HIRD_SW_MASK (0xF0U) -#define USBHSD_LPM_HIRD_SW_SHIFT (4U) -#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) -#define USBHSD_LPM_DATA_PENDING_MASK (0x100U) -#define USBHSD_LPM_DATA_PENDING_SHIFT (8U) -#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) -/*! @} */ - -/*! @name EPSKIP - USB Endpoint skip */ -/*! @{ */ -#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) -#define USBHSD_EPSKIP_SKIP_SHIFT (0U) -#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) -/*! @} */ - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -/*! @{ */ -#define USBHSD_EPINUSE_BUF_MASK (0xFFCU) -#define USBHSD_EPINUSE_BUF_SHIFT (2U) -#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) -/*! @} */ - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ -/*! @{ */ -#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) -#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) -#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) -/*! @} */ - -/*! @name INTSTAT - USB interrupt status register */ -/*! @{ */ -#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) -#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) -#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) -#define USBHSD_INTSTAT_EP0IN_MASK (0x2U) -#define USBHSD_INTSTAT_EP0IN_SHIFT (1U) -#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) -#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) -#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) -#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) -#define USBHSD_INTSTAT_EP1IN_MASK (0x8U) -#define USBHSD_INTSTAT_EP1IN_SHIFT (3U) -#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) -#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) -#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) -#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) -#define USBHSD_INTSTAT_EP2IN_MASK (0x20U) -#define USBHSD_INTSTAT_EP2IN_SHIFT (5U) -#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) -#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) -#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) -#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) -#define USBHSD_INTSTAT_EP3IN_MASK (0x80U) -#define USBHSD_INTSTAT_EP3IN_SHIFT (7U) -#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) -#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) -#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) -#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) -#define USBHSD_INTSTAT_EP4IN_MASK (0x200U) -#define USBHSD_INTSTAT_EP4IN_SHIFT (9U) -#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) -#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) -#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) -#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) -#define USBHSD_INTSTAT_EP5IN_MASK (0x800U) -#define USBHSD_INTSTAT_EP5IN_SHIFT (11U) -#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) -#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) -#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) -#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) -#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) -/*! @} */ - -/*! @name INTEN - USB interrupt enable register */ -/*! @{ */ -#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) -#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) -#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) -#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) -#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) -#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) -#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) -/*! @} */ - -/*! @name INTSETSTAT - USB set interrupt status register */ -/*! @{ */ -#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) -#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) -#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) -#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) -#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) -/*! @} */ - -/*! @name EPTOGGLE - USB Endpoint toggle register */ -/*! @{ */ -#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) -#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) -#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) -/*! @} */ - -/*! @name ULPIDEBUG - UTMI/ULPI debug register */ -/*! @{ */ -#define USBHSD_ULPIDEBUG_PHY_ADDR_MASK (0xFFU) -#define USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT (0U) -#define USBHSD_ULPIDEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ADDR_MASK) -#define USBHSD_ULPIDEBUG_PHY_WDATA_MASK (0xFF00U) -#define USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT (8U) -#define USBHSD_ULPIDEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_WDATA_MASK) -#define USBHSD_ULPIDEBUG_PHY_RDATA_MASK (0xFF0000U) -#define USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT (16U) -#define USBHSD_ULPIDEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RDATA_MASK) -#define USBHSD_ULPIDEBUG_PHY_RW_MASK (0x1000000U) -#define USBHSD_ULPIDEBUG_PHY_RW_SHIFT (24U) -#define USBHSD_ULPIDEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RW_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RW_MASK) -#define USBHSD_ULPIDEBUG_PHY_ACCESS_MASK (0x2000000U) -#define USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT (25U) -#define USBHSD_ULPIDEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ACCESS_MASK) -#define USBHSD_ULPIDEBUG_PHY_MODE_MASK (0x80000000U) -#define USBHSD_ULPIDEBUG_PHY_MODE_SHIFT (31U) -#define USBHSD_ULPIDEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_MODE_SHIFT)) & USBHSD_ULPIDEBUG_PHY_MODE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBHSD_Register_Masks */ - - -/* USBHSD - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral USBHSD base address */ - #define USBHSD_BASE (0x50094000u) - /** Peripheral USBHSD base address */ - #define USBHSD_BASE_NS (0x40094000u) - /** Peripheral USBHSD base pointer */ - #define USBHSD ((USBHSD_Type *)USBHSD_BASE) - /** Peripheral USBHSD base pointer */ - #define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS) - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS { USBHSD_BASE } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS { USBHSD } - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS_NS { USBHSD_BASE_NS } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS_NS { USBHSD_NS } -#else - /** Peripheral USBHSD base address */ - #define USBHSD_BASE (0x40094000u) - /** Peripheral USBHSD base pointer */ - #define USBHSD ((USBHSD_Type *)USBHSD_BASE) - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS { USBHSD_BASE } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS { USBHSD } -#endif -/** Interrupt vectors for the USBHSD peripheral type */ -#define USBHSD_IRQS { USB1_IRQn } -#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBHSD_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBHSH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer - * @{ - */ - -/** USBHSH - Register Layout Typedef */ -typedef struct { - __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ - __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ - __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x8 */ - __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ - __IO uint32_t ATL_PTD_BASE_ADDR; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ - __IO uint32_t ISO_PTD_BASE_ADDR; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ - __IO uint32_t INT_PTD_BASE_ADDR; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ - __IO uint32_t DATA_PAYLOAD_BASE_ADDR; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ - __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ - __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ - __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ - __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ - __IO uint32_t ATL_PTD_DONE_MAP; /**< Done map for each ATL PTD, offset: 0x30 */ - __IO uint32_t ATL_PTD_SKIP_MAP; /**< Skip map for each ATL PTD, offset: 0x34 */ - __IO uint32_t ISO_PTD_DONE_MAP; /**< Done map for each ISO PTD, offset: 0x38 */ - __IO uint32_t ISO_PTD_SKIP_MAP; /**< Skip map for each ISO PTD, offset: 0x3C */ - __IO uint32_t INT_PTD_DONE_MAP; /**< Done map for each INT PTD, offset: 0x40 */ - __IO uint32_t INT_PTD_SKIP_MAP; /**< Skip map for each INT PTD, offset: 0x44 */ - __IO uint32_t LAST_PTD_INUSE; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ - __IO uint32_t UTMIPLUS_ULPI_DEBUG; /**< Register to read/write registers in the attached USB PHY, offset: 0x4C */ - __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ -} USBHSH_Type; - -/* ---------------------------------------------------------------------------- - -- USBHSH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSH_Register_Masks USBHSH Register Masks - * @{ - */ - -/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ -/*! @{ */ -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) -#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) -#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) -#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) -/*! @} */ - -/*! @name HCSPARAMS - Host Controller Structural Parameters */ -/*! @{ */ -#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) -#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) -#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) -#define USBHSH_HCSPARAMS_PPC_MASK (0x10U) -#define USBHSH_HCSPARAMS_PPC_SHIFT (4U) -#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) -#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) -#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) -#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) -/*! @} */ - -/*! @name HCCPARAMS - Host Controller Capability Parameters */ -/*! @{ */ -#define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U) -#define USBHSH_HCCPARAMS_LPMC_SHIFT (17U) -#define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK) -/*! @} */ - -/*! @name FLADJ_FRINDEX - Frame Length Adjustment */ -/*! @{ */ -#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) -#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) -#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) -#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) -#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) -#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) -/*! @} */ - -/*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */ -/*! @{ */ -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK (0x1F0U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT (4U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK (0xFFFFFE00U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT (9U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK) -/*! @} */ - -/*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */ -/*! @{ */ -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK (0x3E0U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK (0xFFFFFC00U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT (10U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK) -/*! @} */ - -/*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */ -/*! @{ */ -#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK (0x3E0U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK) -#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK (0xFFFFFC00U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT (10U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK) -/*! @} */ - -/*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */ -/*! @{ */ -#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U) -#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U) -#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK) -/*! @} */ - -/*! @name USBCMD - USB Command register */ -/*! @{ */ -#define USBHSH_USBCMD_RS_MASK (0x1U) -#define USBHSH_USBCMD_RS_SHIFT (0U) -#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) -#define USBHSH_USBCMD_HCRESET_MASK (0x2U) -#define USBHSH_USBCMD_HCRESET_SHIFT (1U) -#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) -#define USBHSH_USBCMD_FLS_MASK (0xCU) -#define USBHSH_USBCMD_FLS_SHIFT (2U) -#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) -#define USBHSH_USBCMD_LHCR_MASK (0x80U) -#define USBHSH_USBCMD_LHCR_SHIFT (7U) -#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) -#define USBHSH_USBCMD_ATL_EN_MASK (0x100U) -#define USBHSH_USBCMD_ATL_EN_SHIFT (8U) -#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) -#define USBHSH_USBCMD_ISO_EN_MASK (0x200U) -#define USBHSH_USBCMD_ISO_EN_SHIFT (9U) -#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) -#define USBHSH_USBCMD_INT_EN_MASK (0x400U) -#define USBHSH_USBCMD_INT_EN_SHIFT (10U) -#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) -#define USBHSH_USBCMD_HIRD_MASK (0xF000000U) -#define USBHSH_USBCMD_HIRD_SHIFT (24U) -#define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK) -#define USBHSH_USBCMD_LPM_RWU_MASK (0x10000000U) -#define USBHSH_USBCMD_LPM_RWU_SHIFT (28U) -#define USBHSH_USBCMD_LPM_RWU(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK) -/*! @} */ - -/*! @name USBSTS - USB Interrupt Status register */ -/*! @{ */ -#define USBHSH_USBSTS_PCD_MASK (0x4U) -#define USBHSH_USBSTS_PCD_SHIFT (2U) -#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) -#define USBHSH_USBSTS_FLR_MASK (0x8U) -#define USBHSH_USBSTS_FLR_SHIFT (3U) -#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) -#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) -#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) -#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) -#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) -#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) -#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) -#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) -#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) -#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) -#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) -#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) -#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) -/*! @} */ - -/*! @name USBINTR - USB Interrupt Enable register */ -/*! @{ */ -#define USBHSH_USBINTR_PCDE_MASK (0x4U) -#define USBHSH_USBINTR_PCDE_SHIFT (2U) -#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) -#define USBHSH_USBINTR_FLRE_MASK (0x8U) -#define USBHSH_USBINTR_FLRE_SHIFT (3U) -#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) -#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) -#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) -#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) -#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) -#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) -#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) -#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) -#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) -#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) -#define USBHSH_USBINTR_SOF_E_MASK (0x80000U) -#define USBHSH_USBINTR_SOF_E_SHIFT (19U) -#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) -/*! @} */ - -/*! @name PORTSC1 - Port Status and Control register */ -/*! @{ */ -#define USBHSH_PORTSC1_CCS_MASK (0x1U) -#define USBHSH_PORTSC1_CCS_SHIFT (0U) -#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) -#define USBHSH_PORTSC1_CSC_MASK (0x2U) -#define USBHSH_PORTSC1_CSC_SHIFT (1U) -#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) -#define USBHSH_PORTSC1_PED_MASK (0x4U) -#define USBHSH_PORTSC1_PED_SHIFT (2U) -#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) -#define USBHSH_PORTSC1_PEDC_MASK (0x8U) -#define USBHSH_PORTSC1_PEDC_SHIFT (3U) -#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) -#define USBHSH_PORTSC1_OCA_MASK (0x10U) -#define USBHSH_PORTSC1_OCA_SHIFT (4U) -#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) -#define USBHSH_PORTSC1_OCC_MASK (0x20U) -#define USBHSH_PORTSC1_OCC_SHIFT (5U) -#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) -#define USBHSH_PORTSC1_FPR_MASK (0x40U) -#define USBHSH_PORTSC1_FPR_SHIFT (6U) -#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) -#define USBHSH_PORTSC1_SUSP_MASK (0x80U) -#define USBHSH_PORTSC1_SUSP_SHIFT (7U) -#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) -#define USBHSH_PORTSC1_PR_MASK (0x100U) -#define USBHSH_PORTSC1_PR_SHIFT (8U) -#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) -#define USBHSH_PORTSC1_SUS_L1_MASK (0x200U) -#define USBHSH_PORTSC1_SUS_L1_SHIFT (9U) -#define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK) -#define USBHSH_PORTSC1_LS_MASK (0xC00U) -#define USBHSH_PORTSC1_LS_SHIFT (10U) -#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) -#define USBHSH_PORTSC1_PP_MASK (0x1000U) -#define USBHSH_PORTSC1_PP_SHIFT (12U) -#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) -#define USBHSH_PORTSC1_PIC_MASK (0xC000U) -#define USBHSH_PORTSC1_PIC_SHIFT (14U) -#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) -#define USBHSH_PORTSC1_PTC_MASK (0xF0000U) -#define USBHSH_PORTSC1_PTC_SHIFT (16U) -#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) -#define USBHSH_PORTSC1_PSPD_MASK (0x300000U) -#define USBHSH_PORTSC1_PSPD_SHIFT (20U) -#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) -#define USBHSH_PORTSC1_WOO_MASK (0x400000U) -#define USBHSH_PORTSC1_WOO_SHIFT (22U) -#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) -#define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U) -#define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U) -#define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK) -#define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U) -#define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U) -#define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK) -/*! @} */ - -/*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */ -/*! @{ */ -#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT (0U) -#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK) -/*! @} */ - -/*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */ -/*! @{ */ -#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT (0U) -#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK) -/*! @} */ - -/*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */ -/*! @{ */ -#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT (0U) -#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK) -/*! @} */ - -/*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */ -/*! @{ */ -#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT (0U) -#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK) -/*! @} */ - -/*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */ -/*! @{ */ -#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT (0U) -#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK) -/*! @} */ - -/*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */ -/*! @{ */ -#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT (0U) -#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK) -/*! @} */ - -/*! @name LAST_PTD_INUSE - Marks the last PTD in the list for ISO, INT and ATL */ -/*! @{ */ -#define USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK (0x1FU) -#define USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT (0U) -#define USBHSH_LAST_PTD_INUSE_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK) -#define USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK (0x1F00U) -#define USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT (8U) -#define USBHSH_LAST_PTD_INUSE_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK) -#define USBHSH_LAST_PTD_INUSE_INT_LAST_MASK (0x1F0000U) -#define USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT (16U) -#define USBHSH_LAST_PTD_INUSE_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_INT_LAST_MASK) -/*! @} */ - -/*! @name UTMIPLUS_ULPI_DEBUG - Register to read/write registers in the attached USB PHY */ -/*! @{ */ -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK (0xFFU) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT (0U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK (0xFF00U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT (8U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK (0xFF0000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT (16U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK (0x1000000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT (24U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK (0x2000000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT (25U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK (0x80000000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT (31U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK) -/*! @} */ - -/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ -/*! @{ */ -#define USBHSH_PORTMODE_ID0_MASK (0x1U) -#define USBHSH_PORTMODE_ID0_SHIFT (0U) -#define USBHSH_PORTMODE_ID0(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK) -#define USBHSH_PORTMODE_ID0_EN_MASK (0x100U) -#define USBHSH_PORTMODE_ID0_EN_SHIFT (8U) -#define USBHSH_PORTMODE_ID0_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK) -#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) -#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) -#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) -#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) -#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) -#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) -#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) -#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) -#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBHSH_Register_Masks */ - - -/* USBHSH - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral USBHSH base address */ - #define USBHSH_BASE (0x500A3000u) - /** Peripheral USBHSH base address */ - #define USBHSH_BASE_NS (0x400A3000u) - /** Peripheral USBHSH base pointer */ - #define USBHSH ((USBHSH_Type *)USBHSH_BASE) - /** Peripheral USBHSH base pointer */ - #define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS) - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS { USBHSH_BASE } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS { USBHSH } - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS_NS { USBHSH_BASE_NS } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS_NS { USBHSH_NS } -#else - /** Peripheral USBHSH base address */ - #define USBHSH_BASE (0x400A3000u) - /** Peripheral USBHSH base pointer */ - #define USBHSH ((USBHSH_Type *)USBHSH_BASE) - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS { USBHSH_BASE } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS { USBHSH } -#endif -/** Interrupt vectors for the USBHSH peripheral type */ -#define USBHSH_IRQS { USB1_IRQn } -#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBHSH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBPHY Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer - * @{ - */ - -/** USBPHY - Register Layout Typedef */ -typedef struct { - __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ - __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ - __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ - __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ - __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ - __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ - __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ - __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ - __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ - __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ - __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ - __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ - __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ - __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ - __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ - __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ - __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ - uint8_t RESERVED_0[12]; - __IO uint32_t DEBUG0; /**< USB PHY Debug Register 0, offset: 0x50 */ - __IO uint32_t DEBUG0_SET; /**< USB PHY Debug Register 0, offset: 0x54 */ - __IO uint32_t DEBUG0_CLR; /**< USB PHY Debug Register 0, offset: 0x58 */ - __IO uint32_t DEBUG0_TOG; /**< USB PHY Debug Register 0, offset: 0x5C */ - uint8_t RESERVED_1[16]; - __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ - __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ - __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ - __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ - __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ - uint8_t RESERVED_2[28]; - __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */ - __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */ - __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */ - __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */ - uint8_t RESERVED_3[16]; - __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */ - __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */ - __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */ - __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */ - __I uint32_t USB1_VBUS_DET_STAT; /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */ - uint8_t RESERVED_4[12]; - __IO uint32_t USB1_CHRG_DETECT; /**< USB PHY Charger Detect Control Register, offset: 0xE0 */ - __IO uint32_t USB1_CHRG_DETECT_SET; /**< USB PHY Charger Detect Control Register, offset: 0xE4 */ - __IO uint32_t USB1_CHRG_DETECT_CLR; /**< USB PHY Charger Detect Control Register, offset: 0xE8 */ - __IO uint32_t USB1_CHRG_DETECT_TOG; /**< USB PHY Charger Detect Control Register, offset: 0xEC */ - __I uint32_t USB1_CHRG_DET_STAT; /**< USB PHY Charger Detect Status Register, offset: 0xF0 */ - uint8_t RESERVED_5[12]; - __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100 */ - __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */ - __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */ - __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */ -} USBPHY_Type; - -/* ---------------------------------------------------------------------------- - -- USBPHY Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Register_Masks USBPHY Register Masks - * @{ - */ - -/*! @name PWD - USB PHY Power-Down Register */ -/*! @{ */ -#define USBPHY_PWD_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) -#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) -#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) -#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) -#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) -#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) -#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_SET - USB PHY Power-Down Register */ -/*! @{ */ -#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) -#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) -#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) -#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) -#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) -#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) -#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_CLR - USB PHY Power-Down Register */ -/*! @{ */ -#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) -#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) -#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) -#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) -#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) -#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) -#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_TOG - USB PHY Power-Down Register */ -/*! @{ */ -#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) -#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) -#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) -#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) -#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) -#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) -#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) -/*! @} */ - -/*! @name TX - USB PHY Transmitter Control Register */ -/*! @{ */ -#define USBPHY_TX_D_CAL_MASK (0xFU) -#define USBPHY_TX_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) -#define USBPHY_TX_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) -#define USBPHY_TX_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK) -#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) -#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_SET - USB PHY Transmitter Control Register */ -/*! @{ */ -#define USBPHY_TX_SET_D_CAL_MASK (0xFU) -#define USBPHY_TX_SET_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) -#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) -#define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK) -#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) -#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_CLR - USB PHY Transmitter Control Register */ -/*! @{ */ -#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) -#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) -#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) -#define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK) -#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) -#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_TOG - USB PHY Transmitter Control Register */ -/*! @{ */ -#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) -#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) -#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) -#define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK) -#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) -#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name RX - USB PHY Receiver Control Register */ -/*! @{ */ -#define USBPHY_RX_ENVADJ_MASK (0x7U) -#define USBPHY_RX_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) -#define USBPHY_RX_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) -#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_SET - USB PHY Receiver Control Register */ -/*! @{ */ -#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) -#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) -#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) -#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_CLR - USB PHY Receiver Control Register */ -/*! @{ */ -#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) -#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) -#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) -#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_TOG - USB PHY Receiver Control Register */ -/*! @{ */ -#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) -#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) -#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) -#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) -/*! @} */ - -/*! @name CTRL - USB PHY General Control Register */ -/*! @{ */ -#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) -#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) -#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) -#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) -#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) -#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) -#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) -#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) -#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) -#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) -#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) -#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_SET - USB PHY General Control Register */ -/*! @{ */ -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) -#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) -#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) -#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) -#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) -#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) -#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) -#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_CLR - USB PHY General Control Register */ -/*! @{ */ -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) -#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) -#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) -#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) -#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) -#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_TOG - USB PHY General Control Register */ -/*! @{ */ -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) -#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) -#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) -#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) -#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) -#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) -/*! @} */ - -/*! @name STATUS - USB PHY Status Register */ -/*! @{ */ -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) -/*! HOSTDISCONDETECT_STATUS - * 0b0..USB cable disconnect has not been detected at the local host - * 0b1..USB cable disconnect has been detected at the local host - */ -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) -#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) -#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) -/*! DEVPLUGIN_STATUS - * 0b0..No attachment to a USB host is detected - * 0b1..Cable attachment to a USB host is detected - */ -#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) -#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) -#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) -#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) -#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) -#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) -#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) -/*! @} */ - -/*! @name DEBUG0 - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG0_SET - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_SET_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_SET_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG0_SET_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG0_CLR - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_CLR_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_CLR_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLR_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG0_TOG - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_TOG_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_TOG_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG0_TOG_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG1 - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% - */ -#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) -#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT (18U) -#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK) -#define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK (0x600000U) -#define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT (21U) -#define USBPHY_DEBUG1_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK) -/*! @} */ - -/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% - */ -#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK (0x600000U) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK) -/*! @} */ - -/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% - */ -#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK (0x600000U) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK) -/*! @} */ - -/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% - */ -#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK (0x600000U) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK) -/*! @} */ - -/*! @name VERSION - UTMI RTL Version */ -/*! @{ */ -#define USBPHY_VERSION_STEP_MASK (0xFFFFU) -#define USBPHY_VERSION_STEP_SHIFT (0U) -#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) -#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) -#define USBPHY_VERSION_MINOR_SHIFT (16U) -#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) -#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) -#define USBPHY_VERSION_MAJOR_SHIFT (24U) -#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) -/*! @} */ - -/*! @name PLL_SIC - USB PHY PLL Control/Status Register */ -/*! @{ */ -#define USBPHY_PLL_SIC_MISC2_CONTROL0_MASK (0x20U) -#define USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT (5U) -#define USBPHY_PLL_SIC_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_MISC2_CONTROL0_MASK) -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) -#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) -#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) -#define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U) -#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U) -#define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK) -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) -#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) -#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) -#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) -#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ -/*! @{ */ -#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK (0x20U) -#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT (5U) -#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK) -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) -#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) -#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) -#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U) -#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U) -#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) -#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ -/*! @{ */ -#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK (0x20U) -#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT (5U) -#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK) -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) -#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) -#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U) -#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U) -#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) -#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ -/*! @{ */ -#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK (0x20U) -#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT (5U) -#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK) -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) -#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) -#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U) -#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U) -#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) -#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x100000U) -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) -#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U) -#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U) -/*! EN_CHARGER_RESISTOR - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP - */ -#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U) -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U) -#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U) -/*! EN_CHARGER_RESISTOR - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP - */ -#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U) -/*! EN_CHARGER_RESISTOR - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U) -/*! EN_CHARGER_RESISTOR - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */ -/*! @{ */ -#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) -#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) -/*! SESSEND - * 0b0..The VBUS voltage is above the Session Valid threshold - * 0b1..The VBUS voltage is below the Session Valid threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) -#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) -#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) -/*! BVALID - * 0b0..The VBUS voltage is below the Session Valid threshold - * 0b1..The VBUS voltage is above the Session Valid threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) -#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) -#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) -/*! AVALID - * 0b0..The VBUS voltage is below the Session Valid threshold - * 0b1..The VBUS voltage is above the Session Valid threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) -/*! VBUS_VALID - * 0b0..VBUS is below the comparator threshold - * 0b1..VBUS is above the comparator threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) -/*! VBUS_VALID_3V - * 0b0..VBUS voltage is below VBUS_VALID_3V threshold - * 0b1..VBUS voltage is above VBUS_VALID_3V threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DETECT - USB PHY Charger Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U) -#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U) -#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. - */ -#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U) -#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U) -#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. - */ -#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U) -#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U) -#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. - */ -#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U) -#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U) -#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. - */ -#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U) -#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U) -/*! PLUG_CONTACT - * 0b0..No USB cable attachment has been detected - * 0b1..A USB cable attachment between the device and host has been detected - */ -#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK) -#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U) -#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U) -/*! CHRG_DETECTED - * 0b0..Standard Downstream Port (SDP) has been detected - * 0b1..Charging Port has been detected - */ -#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK) -#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U) -#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U) -/*! DM_STATE - * 0b0..USB_DM pin voltage is < 0.8V - * 0b1..USB_DM pin voltage is > 2.0V - */ -#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK) -#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U) -#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U) -/*! DP_STATE - * 0b0..USB_DP pin voltage is < 0.8V - * 0b1..USB_DP pin voltage is > 2.0V - */ -#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK) -#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U) -#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U) -/*! SECDET_DCP - * 0b0..Charging Downstream Port (CDP) has been detected - * 0b1..Downstream Charging Port (DCP) has been detected - */ -#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK) -/*! @} */ - -/*! @name ANACTRL - USB PHY Analog Control Register */ -/*! @{ */ -#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_SET - USB PHY Analog Control Register */ -/*! @{ */ -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_CLR - USB PHY Analog Control Register */ -/*! @{ */ -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_TOG - USB PHY Analog Control Register */ -/*! @{ */ -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBPHY_Register_Masks */ - - -/* USBPHY - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral USBPHY base address */ - #define USBPHY_BASE (0x50038000u) - /** Peripheral USBPHY base address */ - #define USBPHY_BASE_NS (0x40038000u) - /** Peripheral USBPHY base pointer */ - #define USBPHY ((USBPHY_Type *)USBPHY_BASE) - /** Peripheral USBPHY base pointer */ - #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS { USBPHY_BASE } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS { USBPHY } - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS_NS { USBPHY_NS } -#else - /** Peripheral USBPHY base address */ - #define USBPHY_BASE (0x40038000u) - /** Peripheral USBPHY base pointer */ - #define USBPHY ((USBPHY_Type *)USBPHY_BASE) - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS { USBPHY_BASE } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS { USBPHY } -#endif - -/*! - * @} - */ /* end of group USBPHY_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- UTICK Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer - * @{ - */ - -/** UTICK - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ - __IO uint32_t STAT; /**< Status register., offset: 0x4 */ - __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ - __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ - __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ -} UTICK_Type; - -/* ---------------------------------------------------------------------------- - -- UTICK Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Register_Masks UTICK Register Masks - * @{ - */ - -/*! @name CTRL - Control register. */ -/*! @{ */ -#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) -#define UTICK_CTRL_DELAYVAL_SHIFT (0U) -#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) -#define UTICK_CTRL_REPEAT_MASK (0x80000000U) -#define UTICK_CTRL_REPEAT_SHIFT (31U) -#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) -/*! @} */ - -/*! @name STAT - Status register. */ -/*! @{ */ -#define UTICK_STAT_INTR_MASK (0x1U) -#define UTICK_STAT_INTR_SHIFT (0U) -#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) -#define UTICK_STAT_ACTIVE_MASK (0x2U) -#define UTICK_STAT_ACTIVE_SHIFT (1U) -#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) -/*! @} */ - -/*! @name CFG - Capture configuration register. */ -/*! @{ */ -#define UTICK_CFG_CAPEN0_MASK (0x1U) -#define UTICK_CFG_CAPEN0_SHIFT (0U) -#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) -#define UTICK_CFG_CAPEN1_MASK (0x2U) -#define UTICK_CFG_CAPEN1_SHIFT (1U) -#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) -#define UTICK_CFG_CAPEN2_MASK (0x4U) -#define UTICK_CFG_CAPEN2_SHIFT (2U) -#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) -#define UTICK_CFG_CAPEN3_MASK (0x8U) -#define UTICK_CFG_CAPEN3_SHIFT (3U) -#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) -#define UTICK_CFG_CAPPOL0_MASK (0x100U) -#define UTICK_CFG_CAPPOL0_SHIFT (8U) -#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) -#define UTICK_CFG_CAPPOL1_MASK (0x200U) -#define UTICK_CFG_CAPPOL1_SHIFT (9U) -#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) -#define UTICK_CFG_CAPPOL2_MASK (0x400U) -#define UTICK_CFG_CAPPOL2_SHIFT (10U) -#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) -#define UTICK_CFG_CAPPOL3_MASK (0x800U) -#define UTICK_CFG_CAPPOL3_SHIFT (11U) -#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) -/*! @} */ - -/*! @name CAPCLR - Capture clear register. */ -/*! @{ */ -#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) -#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) -#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) -#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) -#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) -#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) -#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) -#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) -#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) -#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) -#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) -#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) -/*! @} */ - -/*! @name CAP - Capture register . */ -/*! @{ */ -#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) -#define UTICK_CAP_CAP_VALUE_SHIFT (0U) -#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) -#define UTICK_CAP_VALID_MASK (0x80000000U) -#define UTICK_CAP_VALID_SHIFT (31U) -#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) -/*! @} */ - -/* The count of UTICK_CAP */ -#define UTICK_CAP_COUNT (4U) - - -/*! - * @} - */ /* end of group UTICK_Register_Masks */ - - -/* UTICK - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE (0x5000E000u) - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE_NS (0x4000E000u) - /** Peripheral UTICK0 base pointer */ - #define UTICK0 ((UTICK_Type *)UTICK0_BASE) - /** Peripheral UTICK0 base pointer */ - #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS { UTICK0_BASE } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS { UTICK0 } - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS_NS { UTICK0_NS } -#else - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE (0x4000E000u) - /** Peripheral UTICK0 base pointer */ - #define UTICK0 ((UTICK_Type *)UTICK0_BASE) - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS { UTICK0_BASE } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS { UTICK0 } -#endif -/** Interrupt vectors for the UTICK peripheral type */ -#define UTICK_IRQS { UTICK0_IRQn } - -/*! - * @} - */ /* end of group UTICK_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- WWDT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer - * @{ - */ - -/** WWDT - Register Layout Typedef */ -typedef struct { - __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ - __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ - __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ - __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ - uint8_t RESERVED_0[4]; - __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ - __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ -} WWDT_Type; - -/* ---------------------------------------------------------------------------- - -- WWDT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Register_Masks WWDT Register Masks - * @{ - */ - -/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ -/*! @{ */ -#define WWDT_MOD_WDEN_MASK (0x1U) -#define WWDT_MOD_WDEN_SHIFT (0U) -/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently. - * 0b0..Stop. The watchdog timer is stopped. - * 0b1..Run. The watchdog timer is running. - */ -#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) -#define WWDT_MOD_WDRESET_MASK (0x2U) -#define WWDT_MOD_WDRESET_SHIFT (1U) -/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. - * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. - * 0b1..Reset. A watchdog time-out will cause a chip reset. - */ -#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) -#define WWDT_MOD_WDTOF_MASK (0x4U) -#define WWDT_MOD_WDTOF_SHIFT (2U) -#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) -#define WWDT_MOD_WDINT_MASK (0x8U) -#define WWDT_MOD_WDINT_SHIFT (3U) -#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) -#define WWDT_MOD_WDPROTECT_MASK (0x10U) -#define WWDT_MOD_WDPROTECT_SHIFT (4U) -/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. - * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. - * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. - */ -#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) -/*! @} */ - -/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ -/*! @{ */ -#define WWDT_TC_COUNT_MASK (0xFFFFFFU) -#define WWDT_TC_COUNT_SHIFT (0U) -#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) -/*! @} */ - -/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ -/*! @{ */ -#define WWDT_FEED_FEED_MASK (0xFFU) -#define WWDT_FEED_FEED_SHIFT (0U) -#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) -/*! @} */ - -/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ -/*! @{ */ -#define WWDT_TV_COUNT_MASK (0xFFFFFFU) -#define WWDT_TV_COUNT_SHIFT (0U) -#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) -/*! @} */ - -/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ -/*! @{ */ -#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) -#define WWDT_WARNINT_WARNINT_SHIFT (0U) -#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) -/*! @} */ - -/*! @name WINDOW - Watchdog Window compare value. */ -/*! @{ */ -#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) -#define WWDT_WINDOW_WINDOW_SHIFT (0U) -#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group WWDT_Register_Masks */ - - -/* WWDT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral WWDT base address */ - #define WWDT_BASE (0x5000C000u) - /** Peripheral WWDT base address */ - #define WWDT_BASE_NS (0x4000C000u) - /** Peripheral WWDT base pointer */ - #define WWDT ((WWDT_Type *)WWDT_BASE) - /** Peripheral WWDT base pointer */ - #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS) - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS { WWDT_BASE } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS { WWDT } - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS_NS { WWDT_NS } -#else - /** Peripheral WWDT base address */ - #define WWDT_BASE (0x4000C000u) - /** Peripheral WWDT base pointer */ - #define WWDT ((WWDT_Type *)WWDT_BASE) - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS { WWDT_BASE } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS { WWDT } -#endif -/** Interrupt vectors for the WWDT peripheral type */ -#define WWDT_IRQS { WDT_BOD_IRQn } - -/*! - * @} - */ /* end of group WWDT_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #else - #pragma pop - #endif -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/*! - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - * @{ - */ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang system_header - #endif -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma system_include -#endif - -/** - * @brief Mask and left-shift a bit field value for use in a register bit range. - * @param field Name of the register bit field. - * @param value Value of the bit field. - * @return Masked and shifted value. - */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) -/** - * @brief Mask and right-shift a register value to extract a bit field value. - * @param field Name of the register bit field. - * @param value Value of the register. - * @return Masked and shifted bit field value. - */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) - -/*! - * @} - */ /* end of group Bit_Field_Generic_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDK Compatibility - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDK_Compatibility_Symbols SDK Compatibility - * @{ - */ - -/** EMC CS base address */ -#define EMC_CS0_BASE (0x80000000u) -#define EMC_CS1_BASE (0x90000000u) -#define EMC_CS2_BASE (0x98000000u) -#define EMC_CS3_BASE (0x9C000000u) -#define EMC_DYCS0_BASE (0xA0000000u) -#define EMC_DYCS1_BASE (0xB0000000u) -#define EMC_DYCS2_BASE (0xC0000000u) -#define EMC_DYCS3_BASE (0xD0000000u) -#define EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE} -#define EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE} - -/** OTP API */ -typedef struct { - uint32_t (*otpInit)(void); /** Initializes OTP controller */ - uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask); /** Unlock one or more OTP banks for write access */ - uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask); /** Lock one or more OTP banks for write access */ - uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, - uint32_t lockWrite); /** Locks or unlocks write access to a register of an OTP bank and the write lock */ - uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, - uint32_t lockWrite); /** Locks or unlocks read access to a register of an OTP bank and the write lock */ - uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value); /** Program a single register in an OTP bank */ - uint32_t RESERVED_0[5]; - uint32_t (*rngRead)(void); /** Returns 32-bit number from hardware random number generator */ - uint32_t (*otpGetDriverVersion)(void); /** Returns the version of the OTP driver in ROM */ -} OTP_API_Type; - -/** ROM API */ -typedef struct { - __I uint32_t usbdApiBase; /** USB API Base */ - uint32_t RESERVED_0[13]; - __I OTP_API_Type *otpApiBase; /** OTP API Base */ - __I uint32_t aesApiBase; /** AES API Base */ - __I uint32_t secureApiBase; /** Secure API Base */ -} ROM_API_Type; - -/** ROM API base address */ -#define ROM_API_BASE (0x03000200u) -/** ROM API base pointer */ -#define ROM_API (*(ROM_API_Type**) ROM_API_BASE) -/** OTP API base pointer */ -#define OTP_API (ROM_API->otpApiBase) - -/*! - * @} - */ /* end of group SDK_Compatibility_Symbols */ - - -#endif /* _LPC55S69_CM33_CORE0_H_ */ - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core0_features.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core0_features.h deleted file mode 100644 index 4959b85bb5..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core0_features.h +++ /dev/null @@ -1,292 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2018-08-22 -** Build: b190122 -** -** Abstract: -** Chip specific module features. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** -** ################################################################### -*/ - -#ifndef _LPC55S69_cm33_core0_FEATURES_H_ -#define _LPC55S69_cm33_core0_FEATURES_H_ - -/* SOC module features */ - -/* @brief CASPER availability on the SoC. */ -#define FSL_FEATURE_SOC_CASPER_COUNT (1) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (1) -/* @brief CTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_CTIMER_COUNT (5) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (2) -/* @brief FLASH availability on the SoC. */ -#define FSL_FEATURE_SOC_FLASH_COUNT (1) -/* @brief FLEXCOMM availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) -/* @brief GINT availability on the SoC. */ -#define FSL_FEATURE_SOC_GINT_COUNT (2) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (1) -/* @brief SECGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_SECGPIO_COUNT (1) -/* @brief HASHCRYPT availability on the SoC. */ -#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (8) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (8) -/* @brief INPUTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) -/* @brief IOCON availability on the SoC. */ -#define FSL_FEATURE_SOC_IOCON_COUNT (1) -/* @brief LPADC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPADC_COUNT (1) -/* @brief MAILBOX availability on the SoC. */ -#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) -/* @brief MRT availability on the SoC. */ -#define FSL_FEATURE_SOC_MRT_COUNT (1) -/* @brief OSTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) -/* @brief PINT availability on the SoC. */ -#define FSL_FEATURE_SOC_PINT_COUNT (1) -/* @brief SECPINT availability on the SoC. */ -#define FSL_FEATURE_SOC_SECPINT_COUNT (1) -/* @brief PMC availability on the SoC. */ -#define FSL_FEATURE_SOC_PMC_COUNT (1) -/* @brief POWERQUAD availability on the SoC. */ -#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) -/* @brief PUF availability on the SoC. */ -#define FSL_FEATURE_SOC_PUF_COUNT (1) -/* @brief RNG1 availability on the SoC. */ -#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCT availability on the SoC. */ -#define FSL_FEATURE_SOC_SCT_COUNT (1) -/* @brief SDIF availability on the SoC. */ -#define FSL_FEATURE_SOC_SDIF_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (9) -/* @brief SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCON_COUNT (1) -/* @brief SYSCTL1 availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) -/* @brief USART availability on the SoC. */ -#define FSL_FEATURE_SOC_USART_COUNT (8) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (1) -/* @brief USBFSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBFSH_COUNT (1) -/* @brief USBHSD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSD_COUNT (1) -/* @brief USBHSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSH_COUNT (1) -/* @brief USBPHY availability on the SoC. */ -#define FSL_FEATURE_SOC_USBPHY_COUNT (1) -/* @brief UTICK availability on the SoC. */ -#define FSL_FEATURE_SOC_UTICK_COUNT (1) -/* @brief WWDT availability on the SoC. */ -#define FSL_FEATURE_SOC_WWDT_COUNT (1) - -/* LPADC module features */ - -/* @brief FIFO availability on the SoC. */ -#define FSL_FEATURE_LPADC_FIFO_COUNT (2) -/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) -/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) -/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) -/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) -/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) -/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) -/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) -/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) -/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) -/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) -/* @brief Has calibration (bitfield CFG[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) -/* @brief Has offset trim (register OFSTRIM). */ -#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) - -/* CASPER module features */ - -/* @brief Base address of the CASPER dedicated RAM */ -#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) -/* @brief Interleaving of the CASPER dedicated RAM */ -#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1) - -/* DMA module features */ - -/* @brief Number of channels */ -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30) - -/* HASHCRYPT module features */ - -/* @brief the address of alias offset */ -#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) - -/* I2S module features */ - -/* @brief I2S support dual channel transfer. */ -#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) - -/* IOCON module features */ - -/* @brief Func bit field width */ -#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) - -/* MAILBOX module features */ - -/* @brief Mailbox side for current core */ -#define FSL_FEATURE_MAILBOX_SIDE_A (1) - -/* MRT module features */ - -/* @brief number of channels. */ -#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) - -/* PINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (10) - -/* POWERLIB module features */ - -/* @brief Niobe4's Powerlib API is different with other LPC series devices. */ -#define FSL_FEATURE_POWERLIB_NIOBE4_EXTEND (1) - -/* POWERQUAD module features */ - -/* @brief Sine and Cossine fix errata */ -#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1) - -/* PUF module features */ - -/* @brief Number of PUF key slots available on device. */ -#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) -/* @brief the shift status value */ -#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) - -/* SCT module features */ - -/* @brief Number of events */ -#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) -/* @brief Number of states */ -#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) -/* @brief Number of match capture */ -#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) -/* @brief Number of outputs */ -#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) - -/* SDIF module features */ - -/* @brief FIFO depth, every location is a WORD */ -#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) -/* @brief Max DMA buffer size */ -#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) -/* @brief Max source clock in HZ */ -#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) -/* @brief support 2 cards */ -#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) - -/* SECPINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) - -/* SYSCON module features */ - -/* @brief Pointer to ROM IAP entry functions */ -#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) -/* @brief Flash page size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) -/* @brief Flash sector size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) -/* @brief Flash size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592) -/* @brief Has Power Down mode */ -#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) -/* @brief CCM_ANALOG availability on the SoC. */ -#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) - -/* USB module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USB_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USB version */ -#define FSL_FEATURE_USB_VERSION (200) -/* @brief Number of the endpoint in USB FS */ -#define FSL_FEATURE_USB_EP_NUM (5) - -/* USBFSH module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBFSH version */ -#define FSL_FEATURE_USBFSH_VERSION (200) - -/* USBHSD module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBHSD version */ -#define FSL_FEATURE_USBHSD_VERSION (300) -/* @brief Number of the endpoint in USB HS */ -#define FSL_FEATURE_USBHSD_EP_NUM (6) - -/* USBHSH module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBHSH version */ -#define FSL_FEATURE_USBHSH_VERSION (300) - -/* UTICK module features */ - -/* @brief UTICK does not support PD configure. */ -#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) - -/* WWDT module features */ - -/* @brief WWDT does not support oscillator lock. */ -#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) -/* @brief WWDT does not support power down configure */ -#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) - -#endif /* _LPC55S69_cm33_core0_FEATURES_H_ */ - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core1.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core1.h deleted file mode 100644 index 8a4b751223..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core1.h +++ /dev/null @@ -1,24757 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JET98_cm33_core1 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b190122 -** -** Abstract: -** CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 -** -** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** -** ################################################################### -*/ - -/*! - * @file LPC55S69_cm33_core1.h - * @version 1.0 - * @date 2018-08-22 - * @brief CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 - * - * CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 - */ - -#ifndef _LPC55S69_CM33_CORE1_H_ -#define _LPC55S69_CM33_CORE1_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0000U - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ - SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ - - /* Device specific interrupts */ - WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ - DMA0_IRQn = 1, /**< DMA0 controller */ - GINT0_IRQn = 2, /**< GPIO group 0 */ - GINT1_IRQn = 3, /**< GPIO group 1 */ - PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ - PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ - PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ - PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ - UTICK0_IRQn = 8, /**< Micro-tick Timer */ - MRT0_IRQn = 9, /**< Multi-rate timer */ - CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ - CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ - SCT0_IRQn = 12, /**< SCTimer/PWM */ - CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ - FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ - FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ - ADC0_IRQn = 22, /**< ADC0 */ - Reserved39_IRQn = 23, /**< Reserved interrupt */ - ACMP_IRQn = 24, /**< ACMP interrupts */ - Reserved41_IRQn = 25, /**< Reserved interrupt */ - Reserved42_IRQn = 26, /**< Reserved interrupt */ - USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ - USB0_IRQn = 28, /**< USB device */ - RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ - Reserved46_IRQn = 30, /**< Reserved interrupt */ - MAILBOX_IRQn = 31, /**< WAKEUP,Mailbox interrupt (present on selected devices) */ - PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ - PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ - PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ - PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ - CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ - CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ - OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ - Reserved55_IRQn = 39, /**< Reserved interrupt */ - Reserved56_IRQn = 40, /**< Reserved interrupt */ - Reserved57_IRQn = 41, /**< Reserved interrupt */ - SDIO_IRQn = 42, /**< SD/MMC */ - Reserved59_IRQn = 43, /**< Reserved interrupt */ - Reserved60_IRQn = 44, /**< Reserved interrupt */ - Reserved61_IRQn = 45, /**< Reserved interrupt */ - USB1_UTMI_IRQn = 46, /**< USB1_UTMI */ - USB1_IRQn = 47, /**< USB1 interrupt */ - USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ - SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ - SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */ - SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */ - PLU_IRQn = 52, /**< PLU interrupt */ - SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ - HASHCRYPT_IRQn = 54, /**< HASHCRYPT interrupt */ - CASER_IRQn = 55, /**< CASPER interrupt */ - PUF_IRQn = 56, /**< PUF interrupt */ - PQ_IRQn = 57, /**< PQ interrupt */ - DMA1_IRQn = 58, /**< DMA1 interrupt */ - LSPI_HS_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M33 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */ -#define __DSP_PRESENT 0 /**< Defines if Armv8-M Mainline core supports DSP instructions */ -#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ - -#include "core_cm33.h" /* Core Peripheral Access Layer */ -#include "system_LPC55S69_cm33_core1.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -/*! - * @addtogroup dma_request - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Structure for the DMA hardware request - * - * Defines the structure for the DMA hardware request collections. The user can configure the - * hardware request to trigger the DMA transfer accordingly. The index - * of the hardware request varies according to the to SoC. - */ -typedef enum _dma_request_source -{ - kDma0RequestHashCrypt = 0U, /**< HashCrypt */ - kDma1RequestHashCryptInput = 0U, /**< HashCrypt Input */ - kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ - kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ - kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ - kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ - kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ - kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ - kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ - kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ - kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ - kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ - kDma0RequestFlexcomm2Rx = 8U, /**< Flexcomm Interface 2 RX/I2C Slave */ - kDma1RequestFlexcomm2Rx = 8U, /**< Flexcomm Interface 2 RX/I2C Slave */ - kDma0RequestFlexcomm2Tx = 9U, /**< Flexcomm Interface 2 TX/I2C Master */ - kDma1RequestFlexcomm2Tx = 9U, /**< Flexcomm Interface 2 TX/I2C Master */ - kDma0RequestFlexcomm3Rx = 10U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kDma0RequestFlexcomm3Tx = 11U, /**< Flexcomm Interface 3 TX/I2C Master */ - kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ - kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ - kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ - kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ - kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ - kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ - kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ - kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ - kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */ - kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ - kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ -} dma_request_source_t; - -/* @} */ - - -/*! - * @} - */ /* end of group Mapping_Information */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #else - #pragma push - #pragma anon_unions - #endif -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ - __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ - __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ - __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ - __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ - uint8_t RESERVED_1[12]; - __IO uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ - __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ - uint8_t RESERVED_2[4]; - __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ - uint8_t RESERVED_3[92]; - __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ - __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_4[8]; - __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ - __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ - struct { /* offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ - } CMD[15]; - uint8_t RESERVED_5[136]; - __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_6[240]; - __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ - uint8_t RESERVED_7[248]; - __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ - uint8_t RESERVED_8[124]; - __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ - uint8_t RESERVED_9[2680]; - __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define ADC_VERID_RES_MASK (0x1U) -#define ADC_VERID_RES_SHIFT (0U) -/*! RES - Resolution - * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. - * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. - */ -#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) -#define ADC_VERID_DIFFEN_MASK (0x2U) -#define ADC_VERID_DIFFEN_SHIFT (1U) -/*! DIFFEN - Differential Supported - * 0b0..Differential operation not supported. - * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. - */ -#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) -#define ADC_VERID_MVI_MASK (0x8U) -#define ADC_VERID_MVI_SHIFT (3U) -/*! MVI - Multi Vref Implemented - * 0b0..Single voltage reference high (VREFH) input supported. - * 0b1..Multiple voltage reference high (VREFH) inputs supported. - */ -#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) -#define ADC_VERID_CSW_MASK (0x70U) -#define ADC_VERID_CSW_SHIFT (4U) -/*! CSW - Channel Scale Width - * 0b000..Channel scaling not supported. - * 0b001..Channel scaling supported. 1-bit CSCALE control field. - * 0b110..Channel scaling supported. 6-bit CSCALE control field. - */ -#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) -#define ADC_VERID_VR1RNGI_MASK (0x100U) -#define ADC_VERID_VR1RNGI_SHIFT (8U) -/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented - * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. - * 0b1..Range control required. CFG[VREF1RNG] is implemented. - */ -#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) -#define ADC_VERID_IADCKI_MASK (0x200U) -#define ADC_VERID_IADCKI_SHIFT (9U) -/*! IADCKI - Internal ADC Clock implemented - * 0b0..Internal clock source not implemented. - * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. - */ -#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) -#define ADC_VERID_CALOFSI_MASK (0x400U) -#define ADC_VERID_CALOFSI_SHIFT (10U) -/*! CALOFSI - Calibration Function Implemented - * 0b0..Calibration Not Implemented. - * 0b1..Calibration Implemented. - */ -#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) -#define ADC_VERID_NUM_SEC_MASK (0x800U) -#define ADC_VERID_NUM_SEC_SHIFT (11U) -/*! NUM_SEC - Number of Single Ended Outputs Supported - * 0b0..This design supports one single ended conversion at a time. - * 0b1..This design supports two simultanious single ended conversions. - */ -#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) -#define ADC_VERID_NUM_FIFO_MASK (0x7000U) -#define ADC_VERID_NUM_FIFO_SHIFT (12U) -/*! NUM_FIFO - Number of FIFOs - * 0b000..N/A - * 0b001..This design supports one result FIFO. - * 0b010..This design supports two result FIFOs. - * 0b011..This design supports three result FIFOs. - * 0b100..This design supports four result FIFOs. - */ -#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) -#define ADC_VERID_MINOR_MASK (0xFF0000U) -#define ADC_VERID_MINOR_SHIFT (16U) -#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) -#define ADC_VERID_MAJOR_MASK (0xFF000000U) -#define ADC_VERID_MAJOR_SHIFT (24U) -#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) -#define ADC_PARAM_TRIG_NUM_SHIFT (0U) -#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) -#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) -#define ADC_PARAM_FIFOSIZE_SHIFT (8U) -/*! FIFOSIZE - Result FIFO Depth - * 0b00000001..Result FIFO depth = 1 dataword. - * 0b00000100..Result FIFO depth = 4 datawords. - * 0b00001000..Result FIFO depth = 8 datawords. - * 0b00010000..Result FIFO depth = 16 datawords. - * 0b00100000..Result FIFO depth = 32 datawords. - * 0b01000000..Result FIFO depth = 64 datawords. - */ -#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) -#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) -#define ADC_PARAM_CV_NUM_SHIFT (16U) -#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) -#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) -#define ADC_PARAM_CMD_NUM_SHIFT (24U) -#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) -/*! @} */ - -/*! @name CTRL - ADC Control Register */ -/*! @{ */ -#define ADC_CTRL_ADCEN_MASK (0x1U) -#define ADC_CTRL_ADCEN_SHIFT (0U) -/*! ADCEN - ADC Enable - * 0b0..ADC is disabled. - * 0b1..ADC is enabled. - */ -#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) -#define ADC_CTRL_RST_MASK (0x2U) -#define ADC_CTRL_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..ADC logic is not reset. - * 0b1..ADC logic is reset. - */ -#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) -#define ADC_CTRL_DOZEN_MASK (0x4U) -#define ADC_CTRL_DOZEN_SHIFT (2U) -/*! DOZEN - Doze Enable - * 0b0..ADC is enabled in Doze mode. - * 0b1..ADC is disabled in Doze mode. - */ -#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) -#define ADC_CTRL_CAL_REQ_MASK (0x8U) -#define ADC_CTRL_CAL_REQ_SHIFT (3U) -/*! CAL_REQ - Auto-Calibration Request - * 0b0..No request for auto-calibration has been made. - * 0b1..A request for auto-calibration has been made - */ -#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) -#define ADC_CTRL_CALOFS_MASK (0x10U) -#define ADC_CTRL_CALOFS_SHIFT (4U) -/*! CALOFS - Configure for offset calibration function - * 0b0..Calibration function disabled - * 0b1..Request for offset calibration function - */ -#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) -#define ADC_CTRL_RSTFIFO0_MASK (0x100U) -#define ADC_CTRL_RSTFIFO0_SHIFT (8U) -/*! RSTFIFO0 - Reset FIFO 0 - * 0b0..No effect. - * 0b1..FIFO 0 is reset. - */ -#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) -#define ADC_CTRL_RSTFIFO1_MASK (0x200U) -#define ADC_CTRL_RSTFIFO1_SHIFT (9U) -/*! RSTFIFO1 - Reset FIFO 1 - * 0b0..No effect. - * 0b1..FIFO 1 is reset. - */ -#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) -#define ADC_CTRL_CAL_AVGS_MASK (0x70000U) -#define ADC_CTRL_CAL_AVGS_SHIFT (16U) -/*! CAL_AVGS - Auto-Calibration Averages - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) -/*! @} */ - -/*! @name STAT - ADC Status Register */ -/*! @{ */ -#define ADC_STAT_RDY0_MASK (0x1U) -#define ADC_STAT_RDY0_SHIFT (0U) -/*! RDY0 - Result FIFO 0 Ready Flag - * 0b0..Result FIFO 0 data level not above watermark level. - * 0b1..Result FIFO 0 holding data above watermark level. - */ -#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) -#define ADC_STAT_FOF0_MASK (0x2U) -#define ADC_STAT_FOF0_SHIFT (1U) -/*! FOF0 - Result FIFO 0 Overflow Flag - * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) -#define ADC_STAT_RDY1_MASK (0x4U) -#define ADC_STAT_RDY1_SHIFT (2U) -/*! RDY1 - Result FIFO1 Ready Flag - * 0b0..Result FIFO1 data level not above watermark level. - * 0b1..Result FIFO1 holding data above watermark level. - */ -#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) -#define ADC_STAT_FOF1_MASK (0x8U) -#define ADC_STAT_FOF1_SHIFT (3U) -/*! FOF1 - Result FIFO1 Overflow Flag - * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) -#define ADC_STAT_TEXC_INT_MASK (0x100U) -#define ADC_STAT_TEXC_INT_SHIFT (8U) -/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception - * 0b0..No trigger exceptions have occurred. - * 0b1..A trigger exception has occurred and is pending acknowledgement. - */ -#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) -#define ADC_STAT_TCOMP_INT_MASK (0x200U) -#define ADC_STAT_TCOMP_INT_SHIFT (9U) -/*! TCOMP_INT - Interrupt Flag For Trigger Completion - * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. - * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. - */ -#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) -#define ADC_STAT_CAL_RDY_MASK (0x400U) -#define ADC_STAT_CAL_RDY_SHIFT (10U) -/*! CAL_RDY - Calibration Ready - * 0b0..Calibration is incomplete or hasn't been ran. - * 0b1..The ADC is calibrated. - */ -#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) -#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) -#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) -/*! ADC_ACTIVE - ADC Active - * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. - * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. - */ -#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) -#define ADC_STAT_TRGACT_MASK (0xF0000U) -#define ADC_STAT_TRGACT_SHIFT (16U) -/*! TRGACT - Trigger Active - * 0b0000..Command (sequence) associated with Trigger 0 currently being executed. - * 0b0001..Command (sequence) associated with Trigger 1 currently being executed. - * 0b0010..Command (sequence) associated with Trigger 2 currently being executed. - * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. - */ -#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) -#define ADC_STAT_CMDACT_MASK (0xF000000U) -#define ADC_STAT_CMDACT_SHIFT (24U) -/*! CMDACT - Command Active - * 0b0000..No command is currently in progress. - * 0b0001..Command 1 currently being executed. - * 0b0010..Command 2 currently being executed. - * 0b0011-0b1111..Associated command number is currently being executed. - */ -#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) -/*! @} */ - -/*! @name IE - Interrupt Enable Register */ -/*! @{ */ -#define ADC_IE_FWMIE0_MASK (0x1U) -#define ADC_IE_FWMIE0_SHIFT (0U) -/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable - * 0b0..FIFO 0 watermark interrupts are not enabled. - * 0b1..FIFO 0 watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) -#define ADC_IE_FOFIE0_MASK (0x2U) -#define ADC_IE_FOFIE0_SHIFT (1U) -/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable - * 0b0..FIFO 0 overflow interrupts are not enabled. - * 0b1..FIFO 0 overflow interrupts are enabled. - */ -#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) -#define ADC_IE_FWMIE1_MASK (0x4U) -#define ADC_IE_FWMIE1_SHIFT (2U) -/*! FWMIE1 - FIFO1 Watermark Interrupt Enable - * 0b0..FIFO1 watermark interrupts are not enabled. - * 0b1..FIFO1 watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) -#define ADC_IE_FOFIE1_MASK (0x8U) -#define ADC_IE_FOFIE1_SHIFT (3U) -/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable - * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. - */ -#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) -#define ADC_IE_TEXC_IE_MASK (0x100U) -#define ADC_IE_TEXC_IE_SHIFT (8U) -/*! TEXC_IE - Trigger Exception Interrupt Enable - * 0b0..Trigger exception interrupts are disabled. - * 0b1..Trigger exception interrupts are enabled. - */ -#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) -#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) -#define ADC_IE_TCOMP_IE_SHIFT (16U) -/*! TCOMP_IE - Trigger Completion Interrupt Enable - * 0b0000000000000000..Trigger completion interrupts are disabled. - * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only. - * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only. - * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled. - * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source. - */ -#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) -/*! @} */ - -/*! @name DE - DMA Enable Register */ -/*! @{ */ -#define ADC_DE_FWMDE0_MASK (0x1U) -#define ADC_DE_FWMDE0_SHIFT (0U) -/*! FWMDE0 - FIFO 0 Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) -#define ADC_DE_FWMDE1_MASK (0x2U) -#define ADC_DE_FWMDE1_SHIFT (1U) -/*! FWMDE1 - FIFO1 Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) -/*! @} */ - -/*! @name CFG - ADC Configuration Register */ -/*! @{ */ -#define ADC_CFG_TPRICTRL_MASK (0x3U) -#define ADC_CFG_TPRICTRL_SHIFT (0U) -/*! TPRICTRL - ADC trigger priority control - * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. - * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. - * 0b10..If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger. - * 0b11..RESERVED - */ -#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) -#define ADC_CFG_PWRSEL_MASK (0x30U) -#define ADC_CFG_PWRSEL_SHIFT (4U) -/*! PWRSEL - Power Configuration Select - * 0b00..Lowest power setting. - * 0b01..Higher power setting than 0b0. - * 0b10..Higher power setting than 0b1. - * 0b11..Highest power setting. - */ -#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) -#define ADC_CFG_REFSEL_MASK (0xC0U) -#define ADC_CFG_REFSEL_SHIFT (6U) -/*! REFSEL - Voltage Reference Selection - * 0b00..(Default) Option 1 setting. - * 0b01..Option 2 setting. - * 0b10..Option 3 setting. - * 0b11..Reserved - */ -#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) -#define ADC_CFG_TRES_MASK (0x100U) -#define ADC_CFG_TRES_SHIFT (8U) -/*! TRES - Trigger Resume Enable - * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. - * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. - */ -#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) -#define ADC_CFG_TCMDRES_MASK (0x200U) -#define ADC_CFG_TCMDRES_SHIFT (9U) -/*! TCMDRES - Trigger Command Resume - * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. - * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. - */ -#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) -#define ADC_CFG_HPT_EXDI_MASK (0x400U) -#define ADC_CFG_HPT_EXDI_SHIFT (10U) -/*! HPT_EXDI - High Priority Trigger Exception Disable - * 0b0..High priority trigger exceptions are enabled. - * 0b1..High priority trigger exceptions are disabled. - */ -#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) -#define ADC_CFG_PUDLY_MASK (0xFF0000U) -#define ADC_CFG_PUDLY_SHIFT (16U) -#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) -#define ADC_CFG_PWREN_MASK (0x10000000U) -#define ADC_CFG_PWREN_SHIFT (28U) -/*! PWREN - ADC Analog Pre-Enable - * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. - * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog will remain pre-enabled, and no additional delays will be executed. - */ -#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) -/*! @} */ - -/*! @name PAUSE - ADC Pause Register */ -/*! @{ */ -#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) -#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) -#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) -#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) -#define ADC_PAUSE_PAUSEEN_SHIFT (31U) -/*! PAUSEEN - PAUSE Option Enable - * 0b0..Pause operation disabled - * 0b1..Pause operation enabled - */ -#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) -/*! @} */ - -/*! @name SWTRIG - Software Trigger Register */ -/*! @{ */ -#define ADC_SWTRIG_SWT0_MASK (0x1U) -#define ADC_SWTRIG_SWT0_SHIFT (0U) -/*! SWT0 - Software trigger 0 event - * 0b0..No trigger 0 event generated. - * 0b1..Trigger 0 event generated. - */ -#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) -#define ADC_SWTRIG_SWT1_MASK (0x2U) -#define ADC_SWTRIG_SWT1_SHIFT (1U) -/*! SWT1 - Software trigger 1 event - * 0b0..No trigger 1 event generated. - * 0b1..Trigger 1 event generated. - */ -#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) -#define ADC_SWTRIG_SWT2_MASK (0x4U) -#define ADC_SWTRIG_SWT2_SHIFT (2U) -/*! SWT2 - Software trigger 2 event - * 0b0..No trigger 2 event generated. - * 0b1..Trigger 2 event generated. - */ -#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) -#define ADC_SWTRIG_SWT3_MASK (0x8U) -#define ADC_SWTRIG_SWT3_SHIFT (3U) -/*! SWT3 - Software trigger 3 event - * 0b0..No trigger 3 event generated. - * 0b1..Trigger 3 event generated. - */ -#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) -#define ADC_SWTRIG_SWT4_MASK (0x10U) -#define ADC_SWTRIG_SWT4_SHIFT (4U) -/*! SWT4 - Software trigger 4 event - * 0b0..No trigger 4 event generated. - * 0b1..Trigger 4 event generated. - */ -#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) -#define ADC_SWTRIG_SWT5_MASK (0x20U) -#define ADC_SWTRIG_SWT5_SHIFT (5U) -/*! SWT5 - Software trigger 5 event - * 0b0..No trigger 5 event generated. - * 0b1..Trigger 5 event generated. - */ -#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) -#define ADC_SWTRIG_SWT6_MASK (0x40U) -#define ADC_SWTRIG_SWT6_SHIFT (6U) -/*! SWT6 - Software trigger 6 event - * 0b0..No trigger 6 event generated. - * 0b1..Trigger 6 event generated. - */ -#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) -#define ADC_SWTRIG_SWT7_MASK (0x80U) -#define ADC_SWTRIG_SWT7_SHIFT (7U) -/*! SWT7 - Software trigger 7 event - * 0b0..No trigger 7 event generated. - * 0b1..Trigger 7 event generated. - */ -#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) -#define ADC_SWTRIG_SWT8_MASK (0x100U) -#define ADC_SWTRIG_SWT8_SHIFT (8U) -/*! SWT8 - Software trigger 8 event - * 0b0..No trigger 8 event generated. - * 0b1..Trigger 8 event generated. - */ -#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) -#define ADC_SWTRIG_SWT9_MASK (0x200U) -#define ADC_SWTRIG_SWT9_SHIFT (9U) -/*! SWT9 - Software trigger 9 event - * 0b0..No trigger 9 event generated. - * 0b1..Trigger 9 event generated. - */ -#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) -#define ADC_SWTRIG_SWT10_MASK (0x400U) -#define ADC_SWTRIG_SWT10_SHIFT (10U) -/*! SWT10 - Software trigger 10 event - * 0b0..No trigger 10 event generated. - * 0b1..Trigger 10 event generated. - */ -#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) -#define ADC_SWTRIG_SWT11_MASK (0x800U) -#define ADC_SWTRIG_SWT11_SHIFT (11U) -/*! SWT11 - Software trigger 11 event - * 0b0..No trigger 11 event generated. - * 0b1..Trigger 11 event generated. - */ -#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) -#define ADC_SWTRIG_SWT12_MASK (0x1000U) -#define ADC_SWTRIG_SWT12_SHIFT (12U) -/*! SWT12 - Software trigger 12 event - * 0b0..No trigger 12 event generated. - * 0b1..Trigger 12 event generated. - */ -#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) -#define ADC_SWTRIG_SWT13_MASK (0x2000U) -#define ADC_SWTRIG_SWT13_SHIFT (13U) -/*! SWT13 - Software trigger 13 event - * 0b0..No trigger 13 event generated. - * 0b1..Trigger 13 event generated. - */ -#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) -#define ADC_SWTRIG_SWT14_MASK (0x4000U) -#define ADC_SWTRIG_SWT14_SHIFT (14U) -/*! SWT14 - Software trigger 14 event - * 0b0..No trigger 14 event generated. - * 0b1..Trigger 14 event generated. - */ -#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) -#define ADC_SWTRIG_SWT15_MASK (0x8000U) -#define ADC_SWTRIG_SWT15_SHIFT (15U) -/*! SWT15 - Software trigger 15 event - * 0b0..No trigger 15 event generated. - * 0b1..Trigger 15 event generated. - */ -#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK) -/*! @} */ - -/*! @name TSTAT - Trigger Status Register */ -/*! @{ */ -#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) -#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) -/*! TEXC_NUM - Trigger Exception Number - * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. - * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception. - * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception. - * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception. - * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. - */ -#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) -#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) -#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) -/*! TCOMP_FLAG - Trigger Completion Flag - * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled. - * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. - * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. - * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts. - * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. - */ -#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) -/*! @} */ - -/*! @name OFSTRIM - ADC Offset Trim Register */ -/*! @{ */ -#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) -#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) -#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) -#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) -#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) -#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) -/*! @} */ - -/*! @name TCTRL - Trigger Control Register */ -/*! @{ */ -#define ADC_TCTRL_HTEN_MASK (0x1U) -#define ADC_TCTRL_HTEN_SHIFT (0U) -/*! HTEN - Trigger enable - * 0b0..Hardware trigger source disabled - * 0b1..Hardware trigger source enabled - */ -#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) -#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) -#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) -/*! FIFO_SEL_A - SAR Result Destination For Channel A - * 0b0..Result written to FIFO 0 - * 0b1..Result written to FIFO 1 - */ -#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) -#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) -#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) -/*! FIFO_SEL_B - SAR Result Destination For Channel B - * 0b0..Result written to FIFO 0 - * 0b1..Result written to FIFO 1 - */ -#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) -#define ADC_TCTRL_TPRI_MASK (0xF00U) -#define ADC_TCTRL_TPRI_SHIFT (8U) -/*! TPRI - Trigger priority setting - * 0b0000..Set to highest priority, Level 1 - * 0b0001-0b1110..Set to corresponding priority level - * 0b1111..Set to lowest priority, Level 16 - */ -#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) -#define ADC_TCTRL_RSYNC_MASK (0x8000U) -#define ADC_TCTRL_RSYNC_SHIFT (15U) -#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) -#define ADC_TCTRL_TDLY_MASK (0xF0000U) -#define ADC_TCTRL_TDLY_SHIFT (16U) -#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) -#define ADC_TCTRL_TCMD_MASK (0xF000000U) -#define ADC_TCTRL_TCMD_SHIFT (24U) -/*! TCMD - Trigger command select - * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. - * 0b0001..CMD1 is executed - * 0b0010-0b1110..Corresponding CMD is executed - * 0b1111..CMD15 is executed - */ -#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) -/*! @} */ - -/* The count of ADC_TCTRL */ -#define ADC_TCTRL_COUNT (16U) - -/*! @name FCTRL - FIFO Control Register */ -/*! @{ */ -#define ADC_FCTRL_FCOUNT_MASK (0x1FU) -#define ADC_FCTRL_FCOUNT_SHIFT (0U) -#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) -#define ADC_FCTRL_FWMARK_MASK (0xF0000U) -#define ADC_FCTRL_FWMARK_SHIFT (16U) -#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) -/*! @} */ - -/* The count of ADC_FCTRL */ -#define ADC_FCTRL_COUNT (2U) - -/*! @name GCC - Gain Calibration Control */ -/*! @{ */ -#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) -#define ADC_GCC_GAIN_CAL_SHIFT (0U) -#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) -#define ADC_GCC_RDY_MASK (0x1000000U) -#define ADC_GCC_RDY_SHIFT (24U) -/*! RDY - Gain Calibration Value Valid - * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. - * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. - */ -#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) -/*! @} */ - -/* The count of ADC_GCC */ -#define ADC_GCC_COUNT (2U) - -/*! @name GCR - Gain Calculation Result */ -/*! @{ */ -#define ADC_GCR_GCALR_MASK (0xFFFFU) -#define ADC_GCR_GCALR_SHIFT (0U) -#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) -#define ADC_GCR_RDY_MASK (0x1000000U) -#define ADC_GCR_RDY_SHIFT (24U) -/*! RDY - Gain Calculation Ready - * 0b0..The gain offset calculation value is invalid. - * 0b1..The gain calibration value is valid. - */ -#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) -/*! @} */ - -/* The count of ADC_GCR */ -#define ADC_GCR_COUNT (2U) - -/*! @name CMDL - ADC Command Low Buffer Register */ -/*! @{ */ -#define ADC_CMDL_ADCH_MASK (0x1FU) -#define ADC_CMDL_ADCH_SHIFT (0U) -/*! ADCH - Input channel select - * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. - * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. - * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. - * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. - * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. - * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. - * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. - */ -#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) -#define ADC_CMDL_CTYPE_MASK (0x60U) -#define ADC_CMDL_CTYPE_SHIFT (5U) -/*! CTYPE - Conversion Type - * 0b00..Single-Ended Mode. Only A side channel is converted. - * 0b01..Single-Ended Mode. Only B side channel is converted. - * 0b10..Differential Mode. A-B. - * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. - */ -#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) -#define ADC_CMDL_MODE_MASK (0x80U) -#define ADC_CMDL_MODE_SHIFT (7U) -/*! MODE - Select resolution of conversions - * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. - * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. - */ -#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) -/*! @} */ - -/* The count of ADC_CMDL */ -#define ADC_CMDL_COUNT (15U) - -/*! @name CMDH - ADC Command High Buffer Register */ -/*! @{ */ -#define ADC_CMDH_CMPEN_MASK (0x3U) -#define ADC_CMDH_CMPEN_SHIFT (0U) -/*! CMPEN - Compare Function Enable - * 0b00..Compare disabled. - * 0b01..Reserved - * 0b10..Compare enabled. Store on true. - * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - */ -#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) -#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) -#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) -/*! WAIT_TRIG - Wait for trigger assertion before execution. - * 0b0..This command will be automatically executed. - * 0b1..The active trigger must be asserted again before executing this command. - */ -#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) -#define ADC_CMDH_LWI_MASK (0x80U) -#define ADC_CMDH_LWI_SHIFT (7U) -/*! LWI - Loop with Increment - * 0b0..Auto channel increment disabled - * 0b1..Auto channel increment enabled - */ -#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) -#define ADC_CMDH_STS_MASK (0x700U) -#define ADC_CMDH_STS_SHIFT (8U) -/*! STS - Sample Time Select - * 0b000..Minimum sample time of 3 ADCK cycles. - * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - */ -#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) -#define ADC_CMDH_AVGS_MASK (0x7000U) -#define ADC_CMDH_AVGS_SHIFT (12U) -/*! AVGS - Hardware Average Select - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) -#define ADC_CMDH_LOOP_MASK (0xF0000U) -#define ADC_CMDH_LOOP_SHIFT (16U) -/*! LOOP - Loop Count Select - * 0b0000..Looping not enabled. Command executes 1 time. - * 0b0001..Loop 1 time. Command executes 2 times. - * 0b0010..Loop 2 times. Command executes 3 times. - * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. - * 0b1111..Loop 15 times. Command executes 16 times. - */ -#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) -#define ADC_CMDH_NEXT_MASK (0xF000000U) -#define ADC_CMDH_NEXT_SHIFT (24U) -/*! NEXT - Next Command Select - * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - * 0b0001..Select CMD1 command buffer register as next command. - * 0b0010-0b1110..Select corresponding CMD command buffer register as next command - * 0b1111..Select CMD15 command buffer register as next command. - */ -#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) -/*! @} */ - -/* The count of ADC_CMDH */ -#define ADC_CMDH_COUNT (15U) - -/*! @name CV - Compare Value Register */ -/*! @{ */ -#define ADC_CV_CVL_MASK (0xFFFFU) -#define ADC_CV_CVL_SHIFT (0U) -#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) -#define ADC_CV_CVH_MASK (0xFFFF0000U) -#define ADC_CV_CVH_SHIFT (16U) -#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) -/*! @} */ - -/* The count of ADC_CV */ -#define ADC_CV_COUNT (4U) - -/*! @name RESFIFO - ADC Data Result FIFO Register */ -/*! @{ */ -#define ADC_RESFIFO_D_MASK (0xFFFFU) -#define ADC_RESFIFO_D_SHIFT (0U) -#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) -#define ADC_RESFIFO_TSRC_MASK (0xF0000U) -#define ADC_RESFIFO_TSRC_SHIFT (16U) -/*! TSRC - Trigger Source - * 0b0000..Trigger source 0 initiated this conversion. - * 0b0001..Trigger source 1 initiated this conversion. - * 0b0010-0b1110..Corresponding trigger source initiated this conversion. - * 0b1111..Trigger source 15 initiated this conversion. - */ -#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) -#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) -#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) -/*! LOOPCNT - Loop count value - * 0b0000..Result is from initial conversion in command. - * 0b0001..Result is from second conversion in command. - * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. - * 0b1111..Result is from 16th conversion in command. - */ -#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) -#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) -#define ADC_RESFIFO_CMDSRC_SHIFT (24U) -/*! CMDSRC - Command Buffer Source - * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. - * 0b0001..CMD1 buffer used as control settings for this conversion. - * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. - * 0b1111..CMD15 buffer used as control settings for this conversion. - */ -#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) -#define ADC_RESFIFO_VALID_MASK (0x80000000U) -#define ADC_RESFIFO_VALID_SHIFT (31U) -/*! VALID - FIFO entry is valid - * 0b0..FIFO is empty. Discard any read from RESFIFO. - * 0b1..FIFO record read from RESFIFO is valid. - */ -#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) -/*! @} */ - -/* The count of ADC_RESFIFO */ -#define ADC_RESFIFO_COUNT (2U) - -/*! @name CAL_GAR - Calibration General A-Side Registers */ -/*! @{ */ -#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) -#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) -#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) -/*! @} */ - -/* The count of ADC_CAL_GAR */ -#define ADC_CAL_GAR_COUNT (33U) - -/*! @name CAL_GBR - Calibration General B-Side Registers */ -/*! @{ */ -#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) -#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) -#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) -/*! @} */ - -/* The count of ADC_CAL_GBR */ -#define ADC_CAL_GBR_COUNT (33U) - -/*! @name TST - ADC Test Register */ -/*! @{ */ -#define ADC_TST_CST_LONG_MASK (0x1U) -#define ADC_TST_CST_LONG_SHIFT (0U) -/*! CST_LONG - Calibration Sample Time Long - * 0b0..Normal sample time. Minimum sample time of 3 ADCK cycles. - * 0b1..Increased sample time. 67 ADCK cycles total sample time. - */ -#define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK) -#define ADC_TST_FOFFM_MASK (0x100U) -#define ADC_TST_FOFFM_SHIFT (8U) -/*! FOFFM - Force M-side positive offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced positive offset on MDAC. - */ -#define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK) -#define ADC_TST_FOFFP_MASK (0x200U) -#define ADC_TST_FOFFP_SHIFT (9U) -/*! FOFFP - Force P-side positive offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced positive offset on PDAC. - */ -#define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK) -#define ADC_TST_FOFFM2_MASK (0x400U) -#define ADC_TST_FOFFM2_SHIFT (10U) -/*! FOFFM2 - Force M-side negative offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced negative offset on MDAC. - */ -#define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK) -#define ADC_TST_FOFFP2_MASK (0x800U) -#define ADC_TST_FOFFP2_SHIFT (11U) -/*! FOFFP2 - Force P-side negative offset - * 0b0..Normal operation. No forced offset. - * 0b1..Test configuration. Forced negative offset on PDAC. - */ -#define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK) -#define ADC_TST_TESTEN_MASK (0x800000U) -#define ADC_TST_TESTEN_SHIFT (23U) -/*! TESTEN - Enable test configuration - * 0b0..Normal operation. Test configuration not enabled. - * 0b1..Hardware BIST Test in progress. - */ -#define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral ADC0 base address */ - #define ADC0_BASE (0x500A0000u) - /** Peripheral ADC0 base address */ - #define ADC0_BASE_NS (0x400A0000u) - /** Peripheral ADC0 base pointer */ - #define ADC0 ((ADC_Type *)ADC0_BASE) - /** Peripheral ADC0 base pointer */ - #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS { ADC0_BASE } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS { ADC0 } - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS_NS { ADC0_NS } -#else - /** Peripheral ADC0 base address */ - #define ADC0_BASE (0x400A0000u) - /** Peripheral ADC0 base pointer */ - #define ADC0 ((ADC_Type *)ADC0_BASE) - /** Array initializer of ADC peripheral base addresses */ - #define ADC_BASE_ADDRS { ADC0_BASE } - /** Array initializer of ADC peripheral base pointers */ - #define ADC_BASE_PTRS { ADC0 } -#endif -/** Interrupt vectors for the ADC peripheral type */ -#define ADC_IRQS { ADC0_IRQn } - -/*! - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- AHB_SECURE_CTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer - * @{ - */ - -/** AHB_SECURE_CTRL - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x30 */ - __IO uint32_t SLAVE_RULE; /**< , array offset: 0x0, array step: 0x30 */ - uint8_t RESERVED_0[12]; - __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */ - } SEC_CTRL_FLASH_ROM[1]; - struct { /* offset: 0x30, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< , array offset: 0x40, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAMX[1]; - uint8_t RESERVED_0[12]; - struct { /* offset: 0x50, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< , array offset: 0x60, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM0[1]; - uint8_t RESERVED_1[8]; - struct { /* offset: 0x70, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< , array offset: 0x80, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM1[1]; - uint8_t RESERVED_2[8]; - struct { /* offset: 0x90, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< , array offset: 0xA0, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM2[1]; - uint8_t RESERVED_3[8]; - struct { /* offset: 0xB0, array step: 0x18 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[2]; /**< , array offset: 0xC0, array step: index*0x18, index2*0x4 */ - } SEC_CTRL_RAM3[1]; - uint8_t RESERVED_4[8]; - struct { /* offset: 0xD0, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< , array offset: 0xE0, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_RAM4[1]; - uint8_t RESERVED_5[12]; - struct { /* offset: 0xF0, array step: 0x30 */ - __IO uint32_t SLAVE_RULE; /**< , array offset: 0xF0, array step: 0x30 */ - uint8_t RESERVED_0[12]; - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL3; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x10C, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */ - __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */ - } SEC_CTRL_APB_BRIDGE[1]; - __IO uint32_t SEC_CTRL_AHB0_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */ - __IO uint32_t SEC_CTRL_AHB0_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */ - uint8_t RESERVED_6[8]; - __IO uint32_t SEC_CTRL_AHB1_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */ - __IO uint32_t SEC_CTRL_AHB1_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */ - uint8_t RESERVED_7[12]; - struct { /* offset: 0x144, array step: 0x14 */ - __IO uint32_t SEC_CTRL_AHB2_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */ - __IO uint32_t SEC_CTRL_AHB2_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., array offset: 0x148, array step: 0x14 */ - uint8_t RESERVED_0[8]; - __IO uint32_t SEC_CTRL_AHB2_0_MEM_RULE[1]; /**< , array offset: 0x154, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_AHB2[1]; - uint8_t RESERVED_8[8]; - struct { /* offset: 0x160, array step: 0x14 */ - __IO uint32_t SLAVE_RULE; /**< , array offset: 0x160, array step: 0x14 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MEM_RULE[1]; /**< , array offset: 0x170, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_USB_HS[1]; - uint8_t RESERVED_9[3212]; - __I uint32_t SEC_VIO_ADDR[18]; /**< most recent security violation address for AHB layer n, array offset: 0xE00, array step: 0x4 */ - uint8_t RESERVED_10[56]; - __I uint32_t SEC_VIO_MISC_INFO[18]; /**< most recent security violation miscellaneous information for AHB layer n, array offset: 0xE80, array step: 0x4 */ - uint8_t RESERVED_11[56]; - __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ - uint8_t RESERVED_12[124]; - __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins. This register is used to block leakage of Secure interface (GPIOs, I2C, UART configured as secure peripherals) pin states to non-secure world., offset: 0xF80 */ - __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */ - __IO uint32_t SEC_GPIO_MASK2; /**< Secure GPIO mask for port 2 pins., offset: 0xF88 */ - __IO uint32_t SEC_GPIO_MASK3; /**< Secure GPIO mask for port 3 pins., offset: 0xF8C */ - __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */ - __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */ - uint8_t RESERVED_13[36]; - __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */ - uint8_t RESERVED_14[16]; - __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ - __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ - uint8_t RESERVED_15[20]; - __IO uint32_t CM33_LOCK_REG; /**< Miscalleneous control signals for in CM33 (CPU0), offset: 0xFEC */ - __IO uint32_t MCM33_LOCK_REG; /**< Miscalleneous control signals for in micro-CM33 (CPU1), offset: 0xFF0 */ - uint8_t RESERVED_16[4]; - __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ - __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ -} AHB_SECURE_CTRL_Type; - -/* ---------------------------------------------------------------------------- - -- AHB_SECURE_CTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks - * @{ - */ - -/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) -/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) -/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U) - -/*! @name SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) - -/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) -/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) -/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_SHIFT (0U) -/*! RAM0_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) -/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U) -/*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) -/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) -/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) -/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) -/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_COUNT2 (2U) - -/*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U) -/*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) -/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) -/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) -/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) -/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) -/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) -/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) -/*! SYSCON_RULE - System Configuration - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) -/*! IOCON_RULE - I/O Configuration - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) -/*! GINT0_RULE - GPIO input Interrupt 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) -/*! GINT1_RULE - GPIO input Interrupt 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) -/*! PINT_RULE - Pin Interrupt and Pattern match - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) -/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_SHIFT (24U) -/*! PMUX_RULE - Peripherals mux - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) -/*! CTIMER0_RULE - Standard counter/Timer 0 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) -/*! CTIMER1_RULE - Standard counter/Timer 1 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) -/*! WWDT_RULE - Windiwed wtachdog Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) -/*! MRT_RULE - Multi-rate Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) -/*! UTICK_RULE - Micro-Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) -/*! ANACTRL_RULE - Analog Modules controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_SHIFT (20U) -/*! EFUSE_RULE - eFUSE (One Time Programmable) memory controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_CAPTOUCH_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_CAPTOUCH_RULE_SHIFT (8U) -/*! CAPTOUCH_RULE - Capacitive Touch controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_CAPTOUCH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_CAPTOUCH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_CAPTOUCH_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_EZH_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_EZH_RULE_SHIFT (20U) -/*! EZH_RULE - EZH slave interface - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_EZH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_EZH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_EZH_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) -/*! PMC_RULE - Power Management Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PVT_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PVT_RULE_SHIFT (8U) -/*! PVT_RULE - Process and Voltage Monitoring controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PVT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PVT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PVT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) -/*! SYSCTRL_RULE - System Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) -/*! CTIMER2_RULE - Standard counter/Timer 2 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) -/*! CTIMER3_RULE - Standard counter/Timer 3 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) -/*! CTIMER4_RULE - Standard counter/Timer 4 - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) -/*! RTC_RULE - Real Time Counter - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) -/*! OSEVENT_RULE - OS Event Timer - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) -/*! FLASH_CTRL_RULE - Flash Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) -/*! PRINCE_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) -/*! USBHPHY_RULE - USB High Speed Phy controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) -/*! RNG_RULE - True Random Number Generator - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_SHIFT (12U) -/*! PUFF_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) -/*! PLU_RULE - Programmable Look-Up logic - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_ROMPC_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_ROMPC_RULE_SHIFT (24U) -/*! ROMPC_RULE - ROM patch controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_ROMPC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_ROMPC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_ROMPC_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) - -/*! @name SEC_CTRL_AHB0_0_SLAVE_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_SHIFT (8U) -/*! DMA0_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_SHIFT (16U) -/*! FS_USB_DEV_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_SHIFT (20U) -/*! SCT_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_SHIFT (24U) -/*! FLEXCOMM0_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_SHIFT (28U) -/*! FLEXCOMM1_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB0_1_SLAVE_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_SHIFT (0U) -/*! FLEXCOMM2_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_SHIFT (4U) -/*! FLEXCOMM3_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_SHIFT (8U) -/*! FLEXCOMM4_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_SHIFT (12U) -/*! MAILBOX_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_SHIFT (16U) -/*! GPIO0_RULE - High Speed GPIO - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB1_0_SLAVE_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_SHIFT (16U) -/*! USB_HS_DEV_RULE - USB high Speed device registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_SHIFT (20U) -/*! CRC_RULE - CRC engine - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_SHIFT (24U) -/*! FLEXCOMM5_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_SHIFT (28U) -/*! FLEXCOMM6_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB1_1_SLAVE_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_SHIFT (0U) -/*! FLEXCOMM7_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_SHIFT (12U) -/*! SDIO_RULE - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_SHIFT (16U) -/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_SHIFT (28U) -/*! HS_LSPI_RULE - High Speed SPI - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_MASK) -/*! @} */ - -/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_SHIFT (0U) -/*! ADC_RULE - ADC - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_SHIFT (8U) -/*! USB_FS_HOST_RULE - USB Full Speed Host registers. - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_SHIFT (12U) -/*! USB_HS_HOST_RULE - USB High speed host registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_SHIFT (16U) -/*! HASH_RULE - SHA-2 crypto registers - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_SHIFT (20U) -/*! CASPER_RULE - RSA/ECC crypto accelerator - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_SHIFT (24U) -/*! PQ_RULE - Power Quad (CM33 processor hardware accelerator) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_SHIFT (28U) -/*! DMA1_RULE - DMA Controller (Secure) - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE - Security access rules for AHB peripherals. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_SHIFT (0U) -/*! GPIO1_RULE - Secure High Speed GPIO - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) -/*! AHB_SEC_CTRL_RULE - AHB Secure Controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) -/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) -/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) -/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) -/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) -/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) - -/*! @name SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE - */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) -/*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) -/*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) -/*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) -/*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_COUNT (1U) - -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_COUNT2 (1U) - -/*! @name SEC_VIO_ADDR - most recent security violation address for AHB layer n */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ -#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (18U) - -/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB layer n */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) -/*! @} */ - -/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */ -#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (18U) - -/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT (12U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT (13U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT (14U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT (15U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT (16U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT (17U) -#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. This register is used to block leakage of Secure interface (GPIOs, I2C, UART configured as secure peripherals) pin states to non-secure world. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK2 - Secure GPIO mask for port 2 pins. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK_SHIFT (1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK_SHIFT (2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK_SHIFT (3U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK_SHIFT (5U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK_SHIFT (6U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK_SHIFT (7U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK_SHIFT (8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK_SHIFT (9U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK_SHIFT (10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK_SHIFT (11U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK_SHIFT (12U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK_SHIFT (13U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK_SHIFT (14U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK_SHIFT (15U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK_SHIFT (16U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK_SHIFT (17U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK_SHIFT (18U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK_SHIFT (19U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK_SHIFT (20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK_SHIFT (21U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK_SHIFT (22U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK_SHIFT (23U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK_SHIFT (24U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK_SHIFT (25U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK_SHIFT (26U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK_SHIFT (27U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK_SHIFT (28U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK_SHIFT (29U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK_SHIFT (30U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK_SHIFT (31U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_GPIO_MASK3 - Secure GPIO mask for port 3 pins. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_SHIFT (1U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_SHIFT (2U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_SHIFT (3U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_MASK) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_SHIFT (5U) -#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_MASK) -/*! @} */ - -/*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_SHIFT (24U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_EZH_ARCH_B_IRQ_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_EZH_ARCH_B_IRQ_SHIFT (30U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_EZH_ARCH_B_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_EZH_ARCH_B_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_EZH_ARCH_B_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK) -/*! @} */ - -/*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_SHIFT (14U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_SHIFT (24U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_AMBER_IRQ_MASK (0x10000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_AMBER_IRQ_SHIFT (28U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_AMBER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_AMBER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_AMBER_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_RED_IRQ_MASK (0x20000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_RED_IRQ_SHIFT (29U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_RED_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_RED_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_RED_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_AMBER_IRQ_MASK (0x40000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_AMBER_IRQ_SHIFT (30U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_AMBER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_AMBER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_AMBER_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_RED_IRQ_MASK (0x80000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_RED_IRQ_SHIFT (31U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_RED_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_RED_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_RED_IRQ_MASK) -/*! @} */ - -/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ -/*! @{ */ -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK_SHIFT (4U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK_MASK) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK_MASK (0xC0U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK_SHIFT (6U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK_MASK) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U) -#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK) -/*! @} */ - -/*! @name MASTER_SEC_LEVEL - master secure level register */ -/*! @{ */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_MASK (0x30U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_SHIFT (4U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_MASK (0xC0U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_SHIFT (6U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_D_MASK (0x3000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_D_SHIFT (12U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_D(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_D_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_D_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_I_MASK (0xC000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_I_SHIFT (14U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_I(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_I_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_I_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) -/*! @} */ - -/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ -/*! @{ */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_MASK (0x30U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_SHIFT (4U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_MASK (0xC0U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_SHIFT (6U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_MASK (0x3000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_SHIFT (12U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_D(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_MASK (0xC000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_SHIFT (14U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_I(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) -/*! @} */ - -/*! @name CM33_LOCK_REG - Miscalleneous control signals for in CM33 (CPU0) */ -/*! @{ */ -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT (6U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK (0x300U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT (8U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT (30U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK) -/*! @} */ - -/*! @name MCM33_LOCK_REG - Miscalleneous control signals for in micro-CM33 (CPU1) */ -/*! @{ */ -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_MASK) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_MASK) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_SHIFT (30U) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_MASK) -/*! @} */ - -/*! @name MISC_CTRL_DP_REG - secure control duplicate register */ -/*! @{ */ -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) -#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) -/*! @} */ - -/*! @name MISC_CTRL_REG - secure control register */ -/*! @{ */ -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) -#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group AHB_SECURE_CTRL_Register_Masks */ - - -/* AHB_SECURE_CTRL - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE (0x500AC000u) - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } -#else - /** Peripheral AHB_SECURE_CTRL base address */ - #define AHB_SECURE_CTRL_BASE (0x400AC000u) - /** Peripheral AHB_SECURE_CTRL base pointer */ - #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) - /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ - #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } - /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ - #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } -#endif - -/*! - * @} - */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ANACTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer - * @{ - */ - -/** ANACTRL - Register Layout Typedef */ -typedef struct { - __IO uint32_t ANALOG_CTRL_CFG; /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */ - __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */ - __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */ - __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ - __IO uint32_t ADC_CTRL; /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */ - uint8_t RESERVED_1[4]; - __IO uint32_t XO32M_CTRL; /**< 32 MHz Crystal Oscillator Control register, offset: 0x20 */ - __I uint32_t XO32M_STATUS; /**< 32 MHz Crystal Oscillator Status register, offset: 0x24 */ - uint8_t RESERVED_2[8]; - __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ - __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ - uint8_t RESERVED_3[8]; - __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */ - __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */ - __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */ - uint8_t RESERVED_4[100]; - __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */ - uint8_t RESERVED_5[12]; - __IO uint32_t XO_CAL_CFG; /**< All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register, offset: 0xC0 */ - __IO uint32_t XO_CAL_CMD; /**< All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register., offset: 0xC4 */ - __I uint32_t XO_CAL_STATUS; /**< All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register., offset: 0xC8 */ - uint8_t RESERVED_6[52]; - __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */ - __IO uint32_t USBHS_PHY_TRIM; /**< USB High Speed Phy Trim values, offset: 0x104 */ - __I uint32_t USBHS_PHY_STATUS; /**< USB High Speed Phy Status, offset: 0x108 */ -} ANACTRL_Type; - -/* ---------------------------------------------------------------------------- - -- ANACTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks - * @{ - */ - -/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */ -/*! @{ */ -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U) -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U) -/*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. - * 0b0..FRO192M trimming and 'Enable' comes from eFUSE. - * 0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. - */ -#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK) -/*! @} */ - -/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ -/*! @{ */ -#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK (0x3FU) -#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_SHIFT (0U) -#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK) -#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK (0xFC0U) -#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_SHIFT (6U) -#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) -/*! FLASH_PWRDWN - Flash Power Down status. - * 0b0..Flash is not in power down mode. - * 0b1..Flash is in power down mode. - */ -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) -/*! FLASH_INIT_ERROR - Flash initialization error status. - * 0b0..No error. - * 0b1..At least one error occured during flash initialization.. - */ -#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) -#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK (0xF0000000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_SHIFT (28U) -#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK) -/*! @} */ - -/*! @name FREQ_ME_CTRL - Frequency Measure function control register */ -/*! @{ */ -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) -#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) -#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) -#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) -#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) -/*! @} */ - -/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ -/*! @{ */ -#define ANACTRL_FRO192M_CTRL_BIAS_TRIM_MASK (0x3FU) -#define ANACTRL_FRO192M_CTRL_BIAS_TRIM_SHIFT (0U) -#define ANACTRL_FRO192M_CTRL_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_BIAS_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_BIAS_TRIM_MASK) -#define ANACTRL_FRO192M_CTRL_TEMP_TRIM_MASK (0x3F80U) -#define ANACTRL_FRO192M_CTRL_TEMP_TRIM_SHIFT (7U) -#define ANACTRL_FRO192M_CTRL_TEMP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_TEMP_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_TEMP_TRIM_MASK) -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) -/*! ENA_12MHZCLK - 12 MHz clock control. - * 0b0..12 MHz clock is disabled. - * 0b1..12 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) -#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U) -#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U) -/*! ENA_48MHZCLK - 48 MHz clock control. - * 0b0..48 MHz clock is disabled. - * 0b1..48 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK) -#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) -#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) -#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) -#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) -#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) -#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) -#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) -#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) -#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) -#define ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK (0x30000000U) -#define ANACTRL_FRO192M_CTRL_ATB_CTRL_SHIFT (28U) -#define ANACTRL_FRO192M_CTRL_ATB_CTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ATB_CTRL_SHIFT)) & ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK) -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) -/*! ENA_96MHZCLK - 96 MHz clock control. - * 0b0..96 MHz clock is disabled. - * 0b1..96 MHz clock is enabled. - */ -#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) -#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U) -#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U) -#define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK) -/*! @} */ - -/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ -/*! @{ */ -#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) -#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) -/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. - * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). - * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). - */ -#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) -#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) -/*! @} */ - -/*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */ -/*! @{ */ -#define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK (0x1U) -#define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT (0U) -/*! VBATDIVENABLE - Switch On/Off VBAT divider branch. - * 0b0..VBAT divider branch is disabled. - * 0b1..VBAT divider branch is enabled. - */ -#define ANACTRL_ADC_CTRL_VBATDIVENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK) -/*! @} */ - -/*! @name XO32M_CTRL - 32 MHz Crystal Oscillator Control register */ -/*! @{ */ -#define ANACTRL_XO32M_CTRL_GM_MASK (0xEU) -#define ANACTRL_XO32M_CTRL_GM_SHIFT (1U) -#define ANACTRL_XO32M_CTRL_GM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_GM_SHIFT)) & ANACTRL_XO32M_CTRL_GM_MASK) -#define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U) -#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U) -#define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK) -#define ANACTRL_XO32M_CTRL_AMP_MASK (0xE0U) -#define ANACTRL_XO32M_CTRL_AMP_SHIFT (5U) -#define ANACTRL_XO32M_CTRL_AMP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_AMP_SHIFT)) & ANACTRL_XO32M_CTRL_AMP_MASK) -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK) -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U) -#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK) -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) -/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. - * 0b0..XO AC buffer bypass is disabled. - * 0b1..XO AC buffer bypass is enabled. - */ -#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) -/*! ENABLE_PLL_USB_OUT - Enable XO 32 MHz output to USB HS PLL. - * 0b0..XO 32 MHz output to USB HS PLL is disabled. - * 0b1..XO 32 MHz output to USB HS PLL is enabled. - */ -#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) -/*! ENABLE_SYSTEM_CLK_OUT - Enable XO 32 MHz output to CPU system. - * 0b0..XO 32 MHz output to CPU system is disabled. - * 0b1..XO 32 MHz output to CPU system is enabled. - */ -#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) -#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_MASK (0x2000000U) -#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_SHIFT (25U) -/*! CAPTESTSTARTSRCSEL - Source selection for 'xo32k_captest_start' signal. - * 0b0..Sourced from CAPTESTSTART. - * 0b1..Sourced from calibration. - */ -#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_MASK) -#define ANACTRL_XO32M_CTRL_CAPTESTSTART_MASK (0x4000000U) -#define ANACTRL_XO32M_CTRL_CAPTESTSTART_SHIFT (26U) -#define ANACTRL_XO32M_CTRL_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTSTART_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTSTART_MASK) -#define ANACTRL_XO32M_CTRL_CAPTESTENABLE_MASK (0x8000000U) -#define ANACTRL_XO32M_CTRL_CAPTESTENABLE_SHIFT (27U) -/*! CAPTESTENABLE - Enable signal for captest. - * 0b0..Captest is disabled. - * 0b1..Captest is enabled. - */ -#define ANACTRL_XO32M_CTRL_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTENABLE_MASK) -#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_MASK (0x10000000U) -#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_SHIFT (28U) -/*! CAPTESTOSCINSEL - Select the input for test. - * 0b0..osc_out (oscillator output) pin. - * 0b1..osc_in (oscillator) pin. - */ -#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_MASK) -/*! @} */ - -/*! @name XO32M_STATUS - 32 MHz Crystal Oscillator Status register */ -/*! @{ */ -#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) -#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) -/*! XO_READY - Indicates XO out frequency statibilty. - * 0b0..XO output frequency is not yet stable. - * 0b1..XO output frequency is stable. - */ -#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) -/*! @} */ - -/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ -/*! @{ */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) -/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. - * 0b0..BOD VBAT interrupt is disabled. - * 0b1..BOD VBAT interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) -/*! BODCORE_INT_ENABLE - BOD CORE interrupt control. - * 0b0..BOD CORE interrupt is disabled. - * 0b1..BOD CORE interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) -#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) -/*! DCDC_INT_ENABLE - DCDC interrupt control. - * 0b0..DCDC interrupt is disabled. - * 0b1..DCDC interrupt is enabled. - */ -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) -#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) -/*! @} */ - -/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ -/*! @{ */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) -/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) -/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) -/*! BODVBAT_VAL - Current value of BOD VBAT power status output. - * 0b0..VBAT voltage level is below the threshold. - * 0b1..VBAT voltage level is above the threshold. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) -/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) -/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) -/*! BODCORE_VAL - Current value of BOD CORE power status output. - * 0b0..CORE voltage level is below the threshold. - * 0b1..CORE voltage level is above the threshold. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) -/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) -/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. - * 0b0..No interrupt pending.. - * 0b1..Interrupt pending.. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) -/*! DCDC_VAL - Current value of DCDC power status output. - * 0b0..DCDC output Voltage is below the targeted regulation level. - * 0b1..DCDC output Voltage is above the targeted regulation level. - */ -#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) -/*! @} */ - -/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */ -/*! @{ */ -#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U) -#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U) -/*! SL - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK) -#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK) -#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU) -#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U) -/*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. - * 0b00..Normal mode. - * 0b01..P-Monitor mode. Measure with weak P transistor. - * 0b10..P-Monitor mode. Measure with weak N transistor. - * 0b11..Don't use. - */ -#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK) -#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U) -#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK) -#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U) -#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U) -/*! E_ND0 - First NAND2-based ringo control. - * 0b0..First NAND2-based ringo is disabled. - * 0b1..First NAND2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK) -#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U) -#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U) -/*! E_ND1 - Second NAND2-based ringo control. - * 0b0..Second NAND2-based ringo is disabled. - * 0b1..Second NAND2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK) -#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U) -#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U) -/*! E_NR0 - First NOR2-based ringo control. - * 0b0..First NOR2-based ringo is disabled. - * 0b1..First NOR2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK) -#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U) -#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U) -/*! E_NR1 - Second NOR2-based ringo control. - * 0b0..Second NORD2-based ringo is disabled. - * 0b1..Second NORD2-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK) -#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U) -#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U) -/*! E_IV0 - First Inverter-based ringo control. - * 0b0..First INV-based ringo is disabled. - * 0b1..First INV-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK) -#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U) -#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U) -/*! E_IV1 - Second Inverter-based ringo control. - * 0b0..Second INV-based ringo is disabled. - * 0b1..Second INV-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK) -#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U) -#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U) -/*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. - * 0b0..First PN-based ringo is disabled. - * 0b1..First PN-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK) -#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U) -#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U) -/*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. - * 0b0..Second PN-based ringo is disabled. - * 0b1..Second PN-based ringo is enabled. - */ -#define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK) -#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U) -#define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK) -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */ -/*! @{ */ -#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U) -#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U) -/*! S - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK) -#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK) -#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U) -#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK) -#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U) -#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U) -/*! E_R24 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK) -#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U) -#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U) -/*! E_R35 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK) -#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U) -#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U) -/*! E_M2 - Metal 2 (M2) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK) -#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U) -#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U) -/*! E_M3 - Metal 3 (M3) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK) -#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U) -#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U) -/*! E_M4 - Metal 4 (M4) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK) -#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U) -#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U) -/*! E_M5 - Metal 5 (M5) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK) -#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U) -#define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK) -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */ -/*! @{ */ -#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U) -#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U) -/*! S - Select short or long ringo (for all ringos types). - * 0b0..Select short ringo (few elements). - * 0b1..Select long ringo (many elements). - */ -#define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK) -#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U) -#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U) -/*! FS - Ringo frequency output divider. - * 0b0..High frequency output (frequency lower than 100 MHz). - * 0b1..Low frequency output (frequency lower than 10 MHz). - */ -#define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK) -#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U) -#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U) -/*! PD - Ringo module Power control. - * 0b0..The Ringo module is enabled. - * 0b1..The Ringo module is disabled. - */ -#define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK) -#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U) -#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U) -/*! E_R24 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK) -#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U) -#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U) -/*! E_R35 - . - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK) -#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U) -#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U) -/*! E_M2 - Metal 2 (M2) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK) -#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U) -#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U) -/*! E_M3 - Metal 3 (M3) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK) -#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U) -#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U) -/*! E_M4 - Metal 4 (M4) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK) -#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U) -#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U) -/*! E_M5 - Metal 5 (M5) monitor control. - * 0b0..Ringo is disabled. - * 0b1..Ringo is enabled. - */ -#define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK) -#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U) -#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U) -#define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK) -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U) -#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK) -/*! @} */ - -/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */ -/*! @{ */ -#define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U) -#define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U) -/*! BYPASS - Activate LDO bypass. - * 0b0..Disable bypass mode (for normal operations). - * 0b1..Activate LDO bypass. - */ -#define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK) -#define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U) -#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U) -/*! HIGHZ - . - * 0b0..Output in High normal state. - * 0b1..Output in High Impedance state. - */ -#define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK) -#define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U) -#define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U) -/*! VOUT - Sets the LDO output level. - * 0b000..0.750 V. - * 0b001..0.775 V. - * 0b010..0.800 V. - * 0b011..0.825 V. - * 0b100..0.850 V. - * 0b101..0.875 V. - * 0b110..0.900 V. - * 0b111..0.925 V. - */ -#define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK) -#define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U) -#define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U) -#define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK) -#define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U) -#define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U) -#define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK) -/*! @} */ - -/*! @name XO_CAL_CFG - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register */ -/*! @{ */ -#define ANACTRL_XO_CAL_CFG_START_INV_MASK (0x1U) -#define ANACTRL_XO_CAL_CFG_START_INV_SHIFT (0U) -#define ANACTRL_XO_CAL_CFG_START_INV(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_INV_SHIFT)) & ANACTRL_XO_CAL_CFG_START_INV_MASK) -#define ANACTRL_XO_CAL_CFG_START_OVR_MASK (0x2U) -#define ANACTRL_XO_CAL_CFG_START_OVR_SHIFT (1U) -#define ANACTRL_XO_CAL_CFG_START_OVR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_OVR_SHIFT)) & ANACTRL_XO_CAL_CFG_START_OVR_MASK) -#define ANACTRL_XO_CAL_CFG_START_MASK (0x4U) -#define ANACTRL_XO_CAL_CFG_START_SHIFT (2U) -#define ANACTRL_XO_CAL_CFG_START(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_SHIFT)) & ANACTRL_XO_CAL_CFG_START_MASK) -#define ANACTRL_XO_CAL_CFG_STOP_INV_MASK (0x8U) -#define ANACTRL_XO_CAL_CFG_STOP_INV_SHIFT (3U) -#define ANACTRL_XO_CAL_CFG_STOP_INV(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_STOP_INV_SHIFT)) & ANACTRL_XO_CAL_CFG_STOP_INV_MASK) -#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END_MASK (0x10U) -#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END_SHIFT (4U) -#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_STOP_CNTR_END_SHIFT)) & ANACTRL_XO_CAL_CFG_STOP_CNTR_END_MASK) -#define ANACTRL_XO_CAL_CFG_XO32K_MODE_MASK (0x20U) -#define ANACTRL_XO_CAL_CFG_XO32K_MODE_SHIFT (5U) -/*! XO32K_MODE - When 0 : High speed crystal oscillator calibration is used. When 1 : 32 kHz crystal oscillator calibration is used. - * 0b0..High speed crystal oscillator (12 MHz- 32 MHz) is used - * 0b1..32 kHz crystal oscillator calibration is used. - */ -#define ANACTRL_XO_CAL_CFG_XO32K_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_XO32K_MODE_SHIFT)) & ANACTRL_XO_CAL_CFG_XO32K_MODE_MASK) -/*! @} */ - -/*! @name XO_CAL_CMD - All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register. */ -/*! @{ */ -#define ANACTRL_XO_CAL_CMD_START_MASK (0x1U) -#define ANACTRL_XO_CAL_CMD_START_SHIFT (0U) -#define ANACTRL_XO_CAL_CMD_START(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_START_SHIFT)) & ANACTRL_XO_CAL_CMD_START_MASK) -#define ANACTRL_XO_CAL_CMD_STOP_MASK (0x2U) -#define ANACTRL_XO_CAL_CMD_STOP_SHIFT (1U) -#define ANACTRL_XO_CAL_CMD_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_STOP_SHIFT)) & ANACTRL_XO_CAL_CMD_STOP_MASK) -#define ANACTRL_XO_CAL_CMD_OVR_MASK (0x4U) -#define ANACTRL_XO_CAL_CMD_OVR_SHIFT (2U) -#define ANACTRL_XO_CAL_CMD_OVR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_OVR_SHIFT)) & ANACTRL_XO_CAL_CMD_OVR_MASK) -/*! @} */ - -/*! @name XO_CAL_STATUS - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register. */ -/*! @{ */ -#define ANACTRL_XO_CAL_STATUS_CAL_CNTR_MASK (0xFFFFU) -#define ANACTRL_XO_CAL_STATUS_CAL_CNTR_SHIFT (0U) -#define ANACTRL_XO_CAL_STATUS_CAL_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_STATUS_CAL_CNTR_SHIFT)) & ANACTRL_XO_CAL_STATUS_CAL_CNTR_MASK) -#define ANACTRL_XO_CAL_STATUS_DONE_MASK (0x10000U) -#define ANACTRL_XO_CAL_STATUS_DONE_SHIFT (16U) -#define ANACTRL_XO_CAL_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_STATUS_DONE_SHIFT)) & ANACTRL_XO_CAL_STATUS_DONE_MASK) -/*! @} */ - -/*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */ -/*! @{ */ -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U) -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U) -#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK) -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U) -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U) -#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK) -#define ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK (0x8U) -#define ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT (3U) -#define ANACTRL_USBHS_PHY_CTRL_iso_atx(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK) -/*! @} */ - -/*! @name USBHS_PHY_TRIM - USB High Speed Phy Trim values */ -/*! @{ */ -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK (0x3U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT (0U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK (0x3CU) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT (2U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK (0x7C0U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT (6U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK (0xF800U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT (11U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK (0x30000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT (16U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK (0x1C0000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT (18U) -#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK) -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK (0xE00000U) -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT (21U) -#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK) -/*! @} */ - -/*! @name USBHS_PHY_STATUS - USB High Speed Phy Status */ -/*! @{ */ -#define ANACTRL_USBHS_PHY_STATUS_pfd_stable_MASK (0x1U) -#define ANACTRL_USBHS_PHY_STATUS_pfd_stable_SHIFT (0U) -#define ANACTRL_USBHS_PHY_STATUS_pfd_stable(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_pfd_stable_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_pfd_stable_MASK) -#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_MASK (0x2U) -#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_SHIFT (1U) -#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_MASK (0x4U) -#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_SHIFT (2U) -#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_MASK (0x8U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_SHIFT (3U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_MASK (0x10U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_SHIFT (4U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_MASK (0x20U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_SHIFT (5U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_MASK (0x40U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_SHIFT (6U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ANACTRL_Register_Masks */ - - -/* ANACTRL - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE (0x50013000u) - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE_NS (0x40013000u) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS { ANACTRL } - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } -#else - /** Peripheral ANACTRL base address */ - #define ANACTRL_BASE (0x40013000u) - /** Peripheral ANACTRL base pointer */ - #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) - /** Array initializer of ANACTRL peripheral base addresses */ - #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } - /** Array initializer of ANACTRL peripheral base pointers */ - #define ANACTRL_BASE_PTRS { ANACTRL } -#endif - -/*! - * @} - */ /* end of group ANACTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CASPER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer - * @{ - */ - -/** CASPER - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */ - __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */ - __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */ - __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */ - __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */ - __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */ - __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */ - uint8_t RESERVED_0[4]; - __IO uint32_t AREG; /**< A register, offset: 0x20 */ - __IO uint32_t BREG; /**< B register, offset: 0x24 */ - __IO uint32_t CREG; /**< C register, offset: 0x28 */ - __IO uint32_t DREG; /**< D register, offset: 0x2C */ - __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */ - __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */ - __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */ - __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */ - uint8_t RESERVED_1[32]; - __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */ - __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */ - uint8_t RESERVED_2[24]; - __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */ -} CASPER_Type; - -/* ---------------------------------------------------------------------------- - -- CASPER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CASPER_Register_Masks CASPER Register Masks - * @{ - */ - -/*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */ -/*! @{ */ -#define CASPER_CTRL0_ABBPAIR_MASK (0x1U) -#define CASPER_CTRL0_ABBPAIR_SHIFT (0U) -/*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK) -#define CASPER_CTRL0_ABOFF_MASK (0x4U) -#define CASPER_CTRL0_ABOFF_SHIFT (2U) -#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK) -#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U) -#define CASPER_CTRL0_CDBPAIR_SHIFT (16U) -/*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK) -#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U) -#define CASPER_CTRL0_CDOFF_SHIFT (18U) -#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK) -/*! @} */ - -/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */ -/*! @{ */ -#define CASPER_CTRL1_ITER_MASK (0xFFU) -#define CASPER_CTRL1_ITER_SHIFT (0U) -#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK) -#define CASPER_CTRL1_MODE_MASK (0xFF00U) -#define CASPER_CTRL1_MODE_SHIFT (8U) -#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK) -#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U) -#define CASPER_CTRL1_RESBPAIR_SHIFT (16U) -/*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally this is not the same bank as ABBPAIR (when 4-up supported) - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK) -#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U) -#define CASPER_CTRL1_RESOFF_SHIFT (18U) -#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK) -#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U) -#define CASPER_CTRL1_CSKIP_SHIFT (30U) -/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: - * 0b00..No Skip - * 0b01..Skip if Carry is 1 - * 0b10..Skip if Carry is 0 - * 0b11..Set CTRLOFF to CDOFF and Skip - */ -#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK) -/*! @} */ - -/*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */ -/*! @{ */ -#define CASPER_LOADER_COUNT_MASK (0xFFU) -#define CASPER_LOADER_COUNT_SHIFT (0U) -#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK) -#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U) -#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U) -/*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not matter which bank is used as this is loaded when not performing an operation. - * 0b0..Bank-pair 0 (1st) - * 0b1..Bank-pair 1 (2nd) - */ -#define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK) -#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U) -#define CASPER_LOADER_CTRLOFF_SHIFT (18U) -#define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK) -/*! @} */ - -/*! @name STATUS - Indicates operational status and would contain the carry bit if used. */ -/*! @{ */ -#define CASPER_STATUS_DONE_MASK (0x1U) -#define CASPER_STATUS_DONE_SHIFT (0U) -/*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. - * 0b0..Busy or just cleared - * 0b1..Completed last operation - */ -#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK) -#define CASPER_STATUS_CARRY_MASK (0x10U) -#define CASPER_STATUS_CARRY_SHIFT (4U) -/*! CARRY - Last carry value if operation produced a carry bit - * 0b0..Carry was 0 or no carry - * 0b1..Carry was 1 - */ -#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK) -#define CASPER_STATUS_BUSY_MASK (0x20U) -#define CASPER_STATUS_BUSY_SHIFT (5U) -/*! BUSY - Indicates if the accelerator is busy performing an operation - * 0b0..Not busy - is idle - * 0b1..Is busy - */ -#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK) -/*! @} */ - -/*! @name INTENSET - Sets interrupts */ -/*! @{ */ -#define CASPER_INTENSET_DONE_MASK (0x1U) -#define CASPER_INTENSET_DONE_SHIFT (0U) -/*! DONE - Set if the accelerator should interrupt when done. - * 0b0..Do not interrupt when done - * 0b1..Interrupt when done - */ -#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK) -/*! @} */ - -/*! @name INTENCLR - Clears interrupts */ -/*! @{ */ -#define CASPER_INTENCLR_DONE_MASK (0x1U) -#define CASPER_INTENCLR_DONE_SHIFT (0U) -/*! DONE - Written to clear an interrupt set with INTENSET. - * 0b0..If written 0, ignored - * 0b1..If written 1, do not Interrupt when done - */ -#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */ -/*! @{ */ -#define CASPER_INTSTAT_DONE_MASK (0x1U) -#define CASPER_INTSTAT_DONE_SHIFT (0U) -/*! DONE - If set, interrupt is caused by accelerator being done. - * 0b0..Not caused by accelerator being done - * 0b1..Caused by accelerator being done - */ -#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK) -/*! @} */ - -/*! @name AREG - A register */ -/*! @{ */ -#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_AREG_REG_VALUE_SHIFT (0U) -#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name BREG - B register */ -/*! @{ */ -#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_BREG_REG_VALUE_SHIFT (0U) -#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name CREG - C register */ -/*! @{ */ -#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_CREG_REG_VALUE_SHIFT (0U) -#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name DREG - D register */ -/*! @{ */ -#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_DREG_REG_VALUE_SHIFT (0U) -#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES0 - Result register 0 */ -/*! @{ */ -#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES0_REG_VALUE_SHIFT (0U) -#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES1 - Result register 1 */ -/*! @{ */ -#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES1_REG_VALUE_SHIFT (0U) -#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES2 - Result register 2 */ -/*! @{ */ -#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES2_REG_VALUE_SHIFT (0U) -#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK) -/*! @} */ - -/*! @name RES3 - Result register 3 */ -/*! @{ */ -#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU) -#define CASPER_RES3_REG_VALUE_SHIFT (0U) -#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK) -/*! @} */ - -/*! @name MASK - Optional mask register */ -/*! @{ */ -#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU) -#define CASPER_MASK_MASK_SHIFT (0U) -#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK) -/*! @} */ - -/*! @name REMASK - Optional re-mask register */ -/*! @{ */ -#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU) -#define CASPER_REMASK_MASK_SHIFT (0U) -#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK) -/*! @} */ - -/*! @name LOCK - Security lock register */ -/*! @{ */ -#define CASPER_LOCK_LOCK_MASK (0x1U) -#define CASPER_LOCK_LOCK_SHIFT (0U) -/*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. - * 0b0..unlock - * 0b1..Lock to current security level - */ -#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK) -#define CASPER_LOCK_KEY_MASK (0x1FFF0U) -#define CASPER_LOCK_KEY_SHIFT (4U) -/*! KEY - Must be written as 0x73D to change the register. - * 0b0011100111101..If set during write, will allow lock or unlock - */ -#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CASPER_Register_Masks */ - - -/* CASPER - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral CASPER base address */ - #define CASPER_BASE (0x500A5000u) - /** Peripheral CASPER base address */ - #define CASPER_BASE_NS (0x400A5000u) - /** Peripheral CASPER base pointer */ - #define CASPER ((CASPER_Type *)CASPER_BASE) - /** Peripheral CASPER base pointer */ - #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS) - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS { CASPER_BASE } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS { CASPER } - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS_NS { CASPER_NS } -#else - /** Peripheral CASPER base address */ - #define CASPER_BASE (0x400A5000u) - /** Peripheral CASPER base pointer */ - #define CASPER ((CASPER_Type *)CASPER_BASE) - /** Array initializer of CASPER peripheral base addresses */ - #define CASPER_BASE_ADDRS { CASPER_BASE } - /** Array initializer of CASPER peripheral base pointers */ - #define CASPER_BASE_PTRS { CASPER } -#endif - -/*! - * @} - */ /* end of group CASPER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer - * @{ - */ - -/** CRC - Register Layout Typedef */ -typedef struct { - __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ - union { /* offset: 0x8 */ - __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ - __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ - }; -} CRC_Type; - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/*! @name MODE - CRC mode register */ -/*! @{ */ -#define CRC_MODE_CRC_POLY_MASK (0x3U) -#define CRC_MODE_CRC_POLY_SHIFT (0U) -#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) -#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) -#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) -#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) -#define CRC_MODE_CMPL_WR_MASK (0x8U) -#define CRC_MODE_CMPL_WR_SHIFT (3U) -#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) -#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) -#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) -#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) -#define CRC_MODE_CMPL_SUM_MASK (0x20U) -#define CRC_MODE_CMPL_SUM_SHIFT (5U) -#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) -/*! @} */ - -/*! @name SEED - CRC seed register */ -/*! @{ */ -#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) -#define CRC_SEED_CRC_SEED_SHIFT (0U) -#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) -/*! @} */ - -/*! @name SUM - CRC checksum register */ -/*! @{ */ -#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) -#define CRC_SUM_CRC_SUM_SHIFT (0U) -#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) -/*! @} */ - -/*! @name WR_DATA - CRC data register */ -/*! @{ */ -#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) -#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) -#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CRC_Register_Masks */ - - -/* CRC - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE (0x50095000u) - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE_NS (0x40095000u) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS { CRC_ENGINE } - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } -#else - /** Peripheral CRC_ENGINE base address */ - #define CRC_ENGINE_BASE (0x40095000u) - /** Peripheral CRC_ENGINE base pointer */ - #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) - /** Array initializer of CRC peripheral base addresses */ - #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } - /** Array initializer of CRC peripheral base pointers */ - #define CRC_BASE_PTRS { CRC_ENGINE } -#endif - -/*! - * @} - */ /* end of group CRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer - * @{ - */ - -/** CTIMER - Register Layout Typedef */ -typedef struct { - __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ - __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ - __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ - __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ - __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ - __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ - __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ - __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ - __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ - __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ - uint8_t RESERVED_0[48]; - __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ - __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */ - __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ -} CTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- CTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Register_Masks CTIMER Register Masks - * @{ - */ - -/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ -/*! @{ */ -#define CTIMER_IR_MR0INT_MASK (0x1U) -#define CTIMER_IR_MR0INT_SHIFT (0U) -#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) -#define CTIMER_IR_MR1INT_MASK (0x2U) -#define CTIMER_IR_MR1INT_SHIFT (1U) -#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) -#define CTIMER_IR_MR2INT_MASK (0x4U) -#define CTIMER_IR_MR2INT_SHIFT (2U) -#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) -#define CTIMER_IR_MR3INT_MASK (0x8U) -#define CTIMER_IR_MR3INT_SHIFT (3U) -#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) -#define CTIMER_IR_CR0INT_MASK (0x10U) -#define CTIMER_IR_CR0INT_SHIFT (4U) -#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) -#define CTIMER_IR_CR1INT_MASK (0x20U) -#define CTIMER_IR_CR1INT_SHIFT (5U) -#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) -#define CTIMER_IR_CR2INT_MASK (0x40U) -#define CTIMER_IR_CR2INT_SHIFT (6U) -#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) -#define CTIMER_IR_CR3INT_MASK (0x80U) -#define CTIMER_IR_CR3INT_SHIFT (7U) -#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) -/*! @} */ - -/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ -/*! @{ */ -#define CTIMER_TCR_CEN_MASK (0x1U) -#define CTIMER_TCR_CEN_SHIFT (0U) -/*! CEN - Counter enable. - * 0b0..Disabled.The counters are disabled. - * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. - */ -#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) -#define CTIMER_TCR_CRST_MASK (0x2U) -#define CTIMER_TCR_CRST_SHIFT (1U) -/*! CRST - Counter reset. - * 0b0..Disabled. Do nothing. - * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero. - */ -#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) -/*! @} */ - -/*! @name TC - Timer Counter */ -/*! @{ */ -#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_TC_TCVAL_SHIFT (0U) -#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) -/*! @} */ - -/*! @name PR - Prescale Register */ -/*! @{ */ -#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PR_PRVAL_SHIFT (0U) -#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) -/*! @} */ - -/*! @name PC - Prescale Counter */ -/*! @{ */ -#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PC_PCVAL_SHIFT (0U) -#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) -/*! @} */ - -/*! @name MCR - Match Control Register */ -/*! @{ */ -#define CTIMER_MCR_MR0I_MASK (0x1U) -#define CTIMER_MCR_MR0I_SHIFT (0U) -#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) -#define CTIMER_MCR_MR0R_MASK (0x2U) -#define CTIMER_MCR_MR0R_SHIFT (1U) -#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) -#define CTIMER_MCR_MR0S_MASK (0x4U) -#define CTIMER_MCR_MR0S_SHIFT (2U) -#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) -#define CTIMER_MCR_MR1I_MASK (0x8U) -#define CTIMER_MCR_MR1I_SHIFT (3U) -#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) -#define CTIMER_MCR_MR1R_MASK (0x10U) -#define CTIMER_MCR_MR1R_SHIFT (4U) -#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) -#define CTIMER_MCR_MR1S_MASK (0x20U) -#define CTIMER_MCR_MR1S_SHIFT (5U) -#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) -#define CTIMER_MCR_MR2I_MASK (0x40U) -#define CTIMER_MCR_MR2I_SHIFT (6U) -#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) -#define CTIMER_MCR_MR2R_MASK (0x80U) -#define CTIMER_MCR_MR2R_SHIFT (7U) -#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) -#define CTIMER_MCR_MR2S_MASK (0x100U) -#define CTIMER_MCR_MR2S_SHIFT (8U) -#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) -#define CTIMER_MCR_MR3I_MASK (0x200U) -#define CTIMER_MCR_MR3I_SHIFT (9U) -#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) -#define CTIMER_MCR_MR3R_MASK (0x400U) -#define CTIMER_MCR_MR3R_SHIFT (10U) -#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) -#define CTIMER_MCR_MR3S_MASK (0x800U) -#define CTIMER_MCR_MR3S_SHIFT (11U) -#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) -#define CTIMER_MCR_MR0RL_MASK (0x1000000U) -#define CTIMER_MCR_MR0RL_SHIFT (24U) -#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) -#define CTIMER_MCR_MR1RL_MASK (0x2000000U) -#define CTIMER_MCR_MR1RL_SHIFT (25U) -#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) -#define CTIMER_MCR_MR2RL_MASK (0x4000000U) -#define CTIMER_MCR_MR2RL_SHIFT (26U) -#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) -#define CTIMER_MCR_MR3RL_MASK (0x8000000U) -#define CTIMER_MCR_MR3RL_SHIFT (27U) -#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) -/*! @} */ - -/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ -/*! @{ */ -#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) -#define CTIMER_MR_MATCH_SHIFT (0U) -#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) -/*! @} */ - -/* The count of CTIMER_MR */ -#define CTIMER_MR_COUNT (4U) - -/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ -/*! @{ */ -#define CTIMER_CCR_CAP0RE_MASK (0x1U) -#define CTIMER_CCR_CAP0RE_SHIFT (0U) -#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) -#define CTIMER_CCR_CAP0FE_MASK (0x2U) -#define CTIMER_CCR_CAP0FE_SHIFT (1U) -#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) -#define CTIMER_CCR_CAP0I_MASK (0x4U) -#define CTIMER_CCR_CAP0I_SHIFT (2U) -#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) -#define CTIMER_CCR_CAP1RE_MASK (0x8U) -#define CTIMER_CCR_CAP1RE_SHIFT (3U) -#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) -#define CTIMER_CCR_CAP1FE_MASK (0x10U) -#define CTIMER_CCR_CAP1FE_SHIFT (4U) -#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) -#define CTIMER_CCR_CAP1I_MASK (0x20U) -#define CTIMER_CCR_CAP1I_SHIFT (5U) -#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) -#define CTIMER_CCR_CAP2RE_MASK (0x40U) -#define CTIMER_CCR_CAP2RE_SHIFT (6U) -#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) -#define CTIMER_CCR_CAP2FE_MASK (0x80U) -#define CTIMER_CCR_CAP2FE_SHIFT (7U) -#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) -#define CTIMER_CCR_CAP2I_MASK (0x100U) -#define CTIMER_CCR_CAP2I_SHIFT (8U) -#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) -#define CTIMER_CCR_CAP3RE_MASK (0x200U) -#define CTIMER_CCR_CAP3RE_SHIFT (9U) -#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) -#define CTIMER_CCR_CAP3FE_MASK (0x400U) -#define CTIMER_CCR_CAP3FE_SHIFT (10U) -#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) -#define CTIMER_CCR_CAP3I_MASK (0x800U) -#define CTIMER_CCR_CAP3I_SHIFT (11U) -#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) -/*! @} */ - -/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ -/*! @{ */ -#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) -#define CTIMER_CR_CAP_SHIFT (0U) -#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) -/*! @} */ - -/* The count of CTIMER_CR */ -#define CTIMER_CR_COUNT (4U) - -/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ -/*! @{ */ -#define CTIMER_EMR_EM0_MASK (0x1U) -#define CTIMER_EMR_EM0_SHIFT (0U) -#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) -#define CTIMER_EMR_EM1_MASK (0x2U) -#define CTIMER_EMR_EM1_SHIFT (1U) -#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) -#define CTIMER_EMR_EM2_MASK (0x4U) -#define CTIMER_EMR_EM2_SHIFT (2U) -#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) -#define CTIMER_EMR_EM3_MASK (0x8U) -#define CTIMER_EMR_EM3_SHIFT (3U) -#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) -#define CTIMER_EMR_EMC0_MASK (0x30U) -#define CTIMER_EMR_EMC0_SHIFT (4U) -/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) -#define CTIMER_EMR_EMC1_MASK (0xC0U) -#define CTIMER_EMR_EMC1_SHIFT (6U) -/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) -#define CTIMER_EMR_EMC2_MASK (0x300U) -#define CTIMER_EMR_EMC2_SHIFT (8U) -/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) -#define CTIMER_EMR_EMC3_MASK (0xC00U) -#define CTIMER_EMR_EMC3_SHIFT (10U) -/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) -/*! @} */ - -/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ -/*! @{ */ -#define CTIMER_CTCR_CTMODE_MASK (0x3U) -#define CTIMER_CTCR_CTMODE_SHIFT (0U) -/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - * 0b00..Timer Mode. Incremented every rising APB bus clock edge. - * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. - * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. - * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. - */ -#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) -#define CTIMER_CTCR_CINSEL_MASK (0xCU) -#define CTIMER_CTCR_CINSEL_SHIFT (2U) -/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. - * 0b00..Channel 0. CAPn.0 for CTIMERn - * 0b01..Channel 1. CAPn.1 for CTIMERn - * 0b10..Channel 2. CAPn.2 for CTIMERn - * 0b11..Channel 3. CAPn.3 for CTIMERn - */ -#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) -#define CTIMER_CTCR_ENCC_MASK (0x10U) -#define CTIMER_CTCR_ENCC_SHIFT (4U) -#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) -#define CTIMER_CTCR_SELCC_MASK (0xE0U) -#define CTIMER_CTCR_SELCC_SHIFT (5U) -/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. - * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - */ -#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) -/*! @} */ - -/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ -/*! @{ */ -#define CTIMER_PWMC_PWMEN0_MASK (0x1U) -#define CTIMER_PWMC_PWMEN0_SHIFT (0U) -/*! PWMEN0 - PWM mode enable for channel0. - * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. - */ -#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) -#define CTIMER_PWMC_PWMEN1_MASK (0x2U) -#define CTIMER_PWMC_PWMEN1_SHIFT (1U) -/*! PWMEN1 - PWM mode enable for channel1. - * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. - */ -#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) -#define CTIMER_PWMC_PWMEN2_MASK (0x4U) -#define CTIMER_PWMC_PWMEN2_SHIFT (2U) -/*! PWMEN2 - PWM mode enable for channel2. - * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. - */ -#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) -#define CTIMER_PWMC_PWMEN3_MASK (0x8U) -#define CTIMER_PWMC_PWMEN3_SHIFT (3U) -/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. - * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. - * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. - */ -#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) -/*! @} */ - -/*! @name MSR - Match Shadow Register */ -/*! @{ */ -#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU) -#define CTIMER_MSR_SHADOWW_SHIFT (0U) -#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK) -/*! @} */ - -/* The count of CTIMER_MSR */ -#define CTIMER_MSR_COUNT (4U) - - -/*! - * @} - */ /* end of group CTIMER_Register_Masks */ - - -/* CTIMER - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE (0x50008000u) - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE_NS (0x40008000u) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE (0x50009000u) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE_NS (0x40009000u) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE (0x50028000u) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE_NS (0x40028000u) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE (0x50029000u) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE_NS (0x40029000u) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE (0x5002A000u) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE_NS (0x4002A000u) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } -#else - /** Peripheral CTIMER0 base address */ - #define CTIMER0_BASE (0x40008000u) - /** Peripheral CTIMER0 base pointer */ - #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) - /** Peripheral CTIMER1 base address */ - #define CTIMER1_BASE (0x40009000u) - /** Peripheral CTIMER1 base pointer */ - #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) - /** Peripheral CTIMER2 base address */ - #define CTIMER2_BASE (0x40028000u) - /** Peripheral CTIMER2 base pointer */ - #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) - /** Peripheral CTIMER3 base address */ - #define CTIMER3_BASE (0x40029000u) - /** Peripheral CTIMER3 base pointer */ - #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) - /** Peripheral CTIMER4 base address */ - #define CTIMER4_BASE (0x4002A000u) - /** Peripheral CTIMER4 base pointer */ - #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) - /** Array initializer of CTIMER peripheral base addresses */ - #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } - /** Array initializer of CTIMER peripheral base pointers */ - #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } -#endif -/** Interrupt vectors for the CTIMER peripheral type */ -#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } - -/*! - * @} - */ /* end of group CTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DGBMAILBOX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DGBMAILBOX_Peripheral_Access_Layer DGBMAILBOX Peripheral Access Layer - * @{ - */ - -/** DGBMAILBOX - Register Layout Typedef */ -typedef struct { - __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ - __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ - uint8_t RESERVED_0[240]; - __I uint32_t ID; /**< Identification register, offset: 0xFC */ -} DGBMAILBOX_Type; - -/* ---------------------------------------------------------------------------- - -- DGBMAILBOX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DGBMAILBOX_Register_Masks DGBMAILBOX Register Masks - * @{ - */ - -/*! @name CSW - CRC mode register */ -/*! @{ */ -#define DGBMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) -#define DGBMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) -#define DGBMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DGBMAILBOX_CSW_RESYNCH_REQ_MASK) -#define DGBMAILBOX_CSW_REQ_PENDING_MASK (0x2U) -#define DGBMAILBOX_CSW_REQ_PENDING_SHIFT (1U) -#define DGBMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_REQ_PENDING_SHIFT)) & DGBMAILBOX_CSW_REQ_PENDING_MASK) -#define DGBMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) -#define DGBMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) -#define DGBMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DGBMAILBOX_CSW_DBG_OR_ERR_MASK) -#define DGBMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) -#define DGBMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) -#define DGBMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DGBMAILBOX_CSW_AHB_OR_ERR_MASK) -#define DGBMAILBOX_CSW_SOFT_RESET_MASK (0x10U) -#define DGBMAILBOX_CSW_SOFT_RESET_SHIFT (4U) -#define DGBMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_SOFT_RESET_SHIFT)) & DGBMAILBOX_CSW_SOFT_RESET_MASK) -#define DGBMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) -#define DGBMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) -#define DGBMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DGBMAILBOX_CSW_CHIP_RESET_REQ_MASK) -/*! @} */ - -/*! @name REQUEST - CRC seed register */ -/*! @{ */ -#define DGBMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) -#define DGBMAILBOX_REQUEST_REQ_SHIFT (0U) -#define DGBMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_REQUEST_REQ_SHIFT)) & DGBMAILBOX_REQUEST_REQ_MASK) -/*! @} */ - -/*! @name RETURN - Return value from ROM. */ -/*! @{ */ -#define DGBMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) -#define DGBMAILBOX_RETURN_RET_SHIFT (0U) -#define DGBMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_RETURN_RET_SHIFT)) & DGBMAILBOX_RETURN_RET_MASK) -/*! @} */ - -/*! @name ID - Identification register */ -/*! @{ */ -#define DGBMAILBOX_ID_ID_MASK (0xFFFFFFFFU) -#define DGBMAILBOX_ID_ID_SHIFT (0U) -#define DGBMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_ID_ID_SHIFT)) & DGBMAILBOX_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group DGBMAILBOX_Register_Masks */ - - -/* DGBMAILBOX - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral DGBMAILBOX base address */ - #define DGBMAILBOX_BASE (0x5009C000u) - /** Peripheral DGBMAILBOX base address */ - #define DGBMAILBOX_BASE_NS (0x4009C000u) - /** Peripheral DGBMAILBOX base pointer */ - #define DGBMAILBOX ((DGBMAILBOX_Type *)DGBMAILBOX_BASE) - /** Peripheral DGBMAILBOX base pointer */ - #define DGBMAILBOX_NS ((DGBMAILBOX_Type *)DGBMAILBOX_BASE_NS) - /** Array initializer of DGBMAILBOX peripheral base addresses */ - #define DGBMAILBOX_BASE_ADDRS { DGBMAILBOX_BASE } - /** Array initializer of DGBMAILBOX peripheral base pointers */ - #define DGBMAILBOX_BASE_PTRS { DGBMAILBOX } - /** Array initializer of DGBMAILBOX peripheral base addresses */ - #define DGBMAILBOX_BASE_ADDRS_NS { DGBMAILBOX_BASE_NS } - /** Array initializer of DGBMAILBOX peripheral base pointers */ - #define DGBMAILBOX_BASE_PTRS_NS { DGBMAILBOX_NS } -#else - /** Peripheral DGBMAILBOX base address */ - #define DGBMAILBOX_BASE (0x4009C000u) - /** Peripheral DGBMAILBOX base pointer */ - #define DGBMAILBOX ((DGBMAILBOX_Type *)DGBMAILBOX_BASE) - /** Array initializer of DGBMAILBOX peripheral base addresses */ - #define DGBMAILBOX_BASE_ADDRS { DGBMAILBOX_BASE } - /** Array initializer of DGBMAILBOX peripheral base pointers */ - #define DGBMAILBOX_BASE_PTRS { DGBMAILBOX } -#endif - -/*! - * @} - */ /* end of group DGBMAILBOX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ - __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ - __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ - uint8_t RESERVED_0[20]; - struct { /* offset: 0x20, array step: 0x5C */ - __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ - uint8_t RESERVED_0[4]; - __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ - uint8_t RESERVED_1[4]; - __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ - uint8_t RESERVED_2[4]; - __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ - uint8_t RESERVED_4[4]; - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ - uint8_t RESERVED_5[4]; - __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ - uint8_t RESERVED_6[4]; - __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ - uint8_t RESERVED_7[4]; - __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ - uint8_t RESERVED_8[4]; - __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ - uint8_t RESERVED_9[4]; - __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ - uint8_t RESERVED_10[4]; - __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ - } COMMON[1]; - uint8_t RESERVED_1[900]; - struct { /* offset: 0x400, array step: 0x10 */ - __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ - __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ - __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } CHANNEL[30]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/*! @name CTRL - DMA control. */ -/*! @{ */ -#define DMA_CTRL_ENABLE_MASK (0x1U) -#define DMA_CTRL_ENABLE_SHIFT (0U) -/*! ENABLE - DMA controller master enable. - * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled. - * 0b1..Enabled. The DMA controller is enabled. - */ -#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status. */ -/*! @{ */ -#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) -#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) -/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. - * 0b0..Not pending. No enabled interrupts are pending. - * 0b1..Pending. At least one enabled interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) -#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) -#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) -/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. - * 0b0..Not pending. No error interrupts are pending. - * 0b1..Pending. At least one error interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) -/*! @} */ - -/*! @name SRAMBASE - SRAM address of the channel configuration table. */ -/*! @{ */ -#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) -#define DMA_SRAMBASE_OFFSET_SHIFT (9U) -#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) -/*! @} */ - -/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) -#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLESET */ -#define DMA_COMMON_ENABLESET_COUNT (1U) - -/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) -#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLECLR */ -#define DMA_COMMON_ENABLECLR_COUNT (1U) - -/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) -#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ACTIVE */ -#define DMA_COMMON_ACTIVE_COUNT (1U) - -/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) -#define DMA_COMMON_BUSY_BSY_SHIFT (0U) -#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) -/*! @} */ - -/* The count of DMA_COMMON_BUSY */ -#define DMA_COMMON_BUSY_COUNT (1U) - -/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) -#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ERRINT */ -#define DMA_COMMON_ERRINT_COUNT (1U) - -/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) -#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENSET */ -#define DMA_COMMON_INTENSET_COUNT (1U) - -/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) -#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENCLR */ -#define DMA_COMMON_INTENCLR_COUNT (1U) - -/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTA_IA_SHIFT (0U) -#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTA */ -#define DMA_COMMON_INTA_COUNT (1U) - -/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTB_IB_SHIFT (0U) -#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTB */ -#define DMA_COMMON_INTB_COUNT (1U) - -/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETVALID_SV_SHIFT (0U) -#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETVALID */ -#define DMA_COMMON_SETVALID_COUNT (1U) - -/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) -#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETTRIG */ -#define DMA_COMMON_SETTRIG_COUNT (1U) - -/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) -#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ABORT */ -#define DMA_COMMON_ABORT_COUNT (1U) - -/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ -/*! @{ */ -#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) -#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) -/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. - * 0b0..Disabled. Peripheral DMA requests are disabled. - * 0b1..Enabled. Peripheral DMA requests are enabled. - */ -#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) -#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) -#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) -/*! HWTRIGEN - Hardware Triggering Enable for this channel. - * 0b0..Disabled. Hardware triggering is not used. - * 0b1..Enabled. Use hardware triggering. - */ -#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) -#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) -#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) -/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. - * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. - * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. - */ -#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) -#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) -#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) -/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. - * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. - * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. - */ -#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) -#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) -#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) -/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. - * 0b0..Single transfer. Hardware trigger causes a single transfer. - * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. - */ -#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) -#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) -#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) -#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) -/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. - * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. - * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. - */ -#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) -/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. - * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. - * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. - */ -#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) -#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) -#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) -#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CFG */ -#define DMA_CHANNEL_CFG_COUNT (30U) - -/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ -/*! @{ */ -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) -/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. - * 0b0..No effect. No effect on DMA operation. - * 0b1..Valid pending. - */ -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) -#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) -#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) -/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. - * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. - * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. - */ -#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CTLSTAT */ -#define DMA_CHANNEL_CTLSTAT_COUNT (30U) - -/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ -/*! @{ */ -#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) -#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) -/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. - * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. - * 0b1..Valid. The current channel descriptor is considered valid. - */ -#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) -#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) -#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) -/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. - * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. - * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) -#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) -#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) -/*! SWTRIG - Software Trigger. - * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. - * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. - */ -#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) -/*! CLRTRIG - Clear Trigger. - * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. - * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted - */ -#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) -#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) -#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) -/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. - * 0b0..No effect. - * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) -#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) -#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) -/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. - * 0b0..No effect. - * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) -#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) -#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) -/*! WIDTH - Transfer width used for this DMA channel. - * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). - * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). - * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). - * 0b11..Reserved. Reserved setting, do not use. - */ -#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) -#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) -#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) -/*! SRCINC - Determines whether the source address is incremented for each DMA transfer. - * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. - * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. - * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. - * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. - */ -#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) -#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) -#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) -/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. - * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. - * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. - * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. - * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. - */ -#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_XFERCFG */ -#define DMA_CHANNEL_XFERCFG_COUNT (30U) - - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral DMA0 base address */ - #define DMA0_BASE (0x50082000u) - /** Peripheral DMA0 base address */ - #define DMA0_BASE_NS (0x40082000u) - /** Peripheral DMA0 base pointer */ - #define DMA0 ((DMA_Type *)DMA0_BASE) - /** Peripheral DMA0 base pointer */ - #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) - /** Peripheral DMA1 base address */ - #define DMA1_BASE (0x500A7000u) - /** Peripheral DMA1 base address */ - #define DMA1_BASE_NS (0x400A7000u) - /** Peripheral DMA1 base pointer */ - #define DMA1 ((DMA_Type *)DMA1_BASE) - /** Peripheral DMA1 base pointer */ - #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS { DMA0, DMA1 } - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } -#else - /** Peripheral DMA0 base address */ - #define DMA0_BASE (0x40082000u) - /** Peripheral DMA0 base pointer */ - #define DMA0 ((DMA_Type *)DMA0_BASE) - /** Peripheral DMA1 base address */ - #define DMA1_BASE (0x400A7000u) - /** Peripheral DMA1 base pointer */ - #define DMA1 ((DMA_Type *)DMA1_BASE) - /** Array initializer of DMA peripheral base addresses */ - #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } - /** Array initializer of DMA peripheral base pointers */ - #define DMA_BASE_PTRS { DMA0, DMA1 } -#endif -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } - -/*! - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer - * @{ - */ - -/** FLASH - Register Layout Typedef */ -typedef struct { - __O uint32_t CMD; /**< command register, offset: 0x0 */ - __O uint32_t EVENT; /**< event register, offset: 0x4 */ - __IO uint32_t BURST; /**< read burst register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ - __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ - uint8_t RESERVED_1[104]; - __IO uint32_t DATAW[8]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[3896]; - __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ - __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ - __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ - __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ - __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */ - __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */ - uint8_t RESERVED_3[12]; - __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */ -} FLASH_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_Register_Masks FLASH Register Masks - * @{ - */ - -/*! @name CMD - command register */ -/*! @{ */ -#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) -#define FLASH_CMD_CMD_SHIFT (0U) -#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) -/*! @} */ - -/*! @name EVENT - event register */ -/*! @{ */ -#define FLASH_EVENT_RST_MASK (0x1U) -#define FLASH_EVENT_RST_SHIFT (0U) -#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) -#define FLASH_EVENT_WAKEUP_MASK (0x2U) -#define FLASH_EVENT_WAKEUP_SHIFT (1U) -#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) -#define FLASH_EVENT_ABORT_MASK (0x4U) -#define FLASH_EVENT_ABORT_SHIFT (2U) -#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) -/*! @} */ - -/*! @name BURST - read burst register */ -/*! @{ */ -#define FLASH_BURST_XOR_MASK_MASK (0xFFFFFU) -#define FLASH_BURST_XOR_MASK_SHIFT (0U) -#define FLASH_BURST_XOR_MASK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_XOR_MASK_SHIFT)) & FLASH_BURST_XOR_MASK_MASK) -#define FLASH_BURST_DESCR1_MASK (0xF00000U) -#define FLASH_BURST_DESCR1_SHIFT (20U) -#define FLASH_BURST_DESCR1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR1_SHIFT)) & FLASH_BURST_DESCR1_MASK) -#define FLASH_BURST_DESCR2_MASK (0xF000000U) -#define FLASH_BURST_DESCR2_SHIFT (24U) -#define FLASH_BURST_DESCR2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR2_SHIFT)) & FLASH_BURST_DESCR2_MASK) -#define FLASH_BURST_DESCR3_MASK (0xF0000000U) -#define FLASH_BURST_DESCR3_SHIFT (28U) -#define FLASH_BURST_DESCR3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR3_SHIFT)) & FLASH_BURST_DESCR3_MASK) -/*! @} */ - -/*! @name STARTA - start (or only) address for next flash command */ -/*! @{ */ -#define FLASH_STARTA_STARTA_MASK (0x3FFFFU) -#define FLASH_STARTA_STARTA_SHIFT (0U) -#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) -/*! @} */ - -/*! @name STOPA - end address for next flash command, if command operates on address ranges */ -/*! @{ */ -#define FLASH_STOPA_STOPA_MASK (0x3FFFFU) -#define FLASH_STOPA_STOPA_SHIFT (0U) -#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) -/*! @} */ - -/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ -/*! @{ */ -#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) -#define FLASH_DATAW_DATAW_SHIFT (0U) -#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) -/*! @} */ - -/* The count of FLASH_DATAW */ -#define FLASH_DATAW_COUNT (8U) - -/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ -/*! @{ */ -#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) -#define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) -#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) -#define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) -#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) -#define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) -#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) -#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_ENABLE - Set interrupt enable bits */ -/*! @{ */ -#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) -#define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) -#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) -#define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) -#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) -#define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) -#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) -#define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt status bits */ -/*! @{ */ -#define FLASH_INT_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_STATUS_FAIL_SHIFT (0U) -#define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) -#define FLASH_INT_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_STATUS_ERR_SHIFT (1U) -#define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) -#define FLASH_INT_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_STATUS_DONE_SHIFT (2U) -#define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) -#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) -#define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_ENABLE - Interrupt enable bits */ -/*! @{ */ -#define FLASH_INT_ENABLE_FAIL_MASK (0x1U) -#define FLASH_INT_ENABLE_FAIL_SHIFT (0U) -#define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) -#define FLASH_INT_ENABLE_ERR_MASK (0x2U) -#define FLASH_INT_ENABLE_ERR_SHIFT (1U) -#define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) -#define FLASH_INT_ENABLE_DONE_MASK (0x4U) -#define FLASH_INT_ENABLE_DONE_SHIFT (2U) -#define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) -#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) -#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) -#define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_CLR_STATUS - Clear interrupt status bits */ -/*! @{ */ -#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) -#define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) -#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) -#define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) -#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) -#define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) -#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) -#define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name INT_SET_STATUS - Set interrupt status bits */ -/*! @{ */ -#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) -#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) -#define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) -#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) -#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) -#define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) -#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) -#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) -#define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) -#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) -#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) -#define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) -/*! @} */ - -/*! @name MODULE_ID - Controller+Memory module identification */ -/*! @{ */ -#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) -#define FLASH_MODULE_ID_APERTURE_SHIFT (0U) -#define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) -#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) -#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) -#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) -#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) -#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) -#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) -#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) -#define FLASH_MODULE_ID_ID_SHIFT (16U) -#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLASH_Register_Masks */ - - -/* FLASH - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral FLASH base address */ - #define FLASH_BASE (0x50034000u) - /** Peripheral FLASH base address */ - #define FLASH_BASE_NS (0x40034000u) - /** Peripheral FLASH base pointer */ - #define FLASH ((FLASH_Type *)FLASH_BASE) - /** Peripheral FLASH base pointer */ - #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS { FLASH_BASE } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS { FLASH } - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS_NS { FLASH_NS } -#else - /** Peripheral FLASH base address */ - #define FLASH_BASE (0x40034000u) - /** Peripheral FLASH base pointer */ - #define FLASH ((FLASH_Type *)FLASH_BASE) - /** Array initializer of FLASH peripheral base addresses */ - #define FLASH_BASE_ADDRS { FLASH_BASE } - /** Array initializer of FLASH peripheral base pointers */ - #define FLASH_BASE_PTRS { FLASH } -#endif - -/*! - * @} - */ /* end of group FLASH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_CFPA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer - * @{ - */ - -/** FLASH_CFPA - Register Layout Typedef */ -typedef struct { - __IO uint32_t HEADER; /**< ., offset: 0x0 */ - __IO uint32_t VERSION; /**< ., offset: 0x4 */ - __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ - __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ - __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ROTKH_REVOKE; /**< ., offset: 0x18 */ - __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x1C */ - __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ - __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ - __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ - __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ - union { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< ., array offset: 0x30, array step: 0x4 */ - struct { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< ., offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< ., offset: 0x34 */ - __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< ., array offset: 0x38, array step: 0x4 */ - } PRINCE_REGION0_IV_CODE_CORE; - }; - union { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< ., array offset: 0x68, array step: 0x4 */ - struct { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< ., offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< ., offset: 0x6C */ - __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< ., array offset: 0x70, array step: 0x4 */ - } PRINCE_REGION1_IV_CODE_CORE; - }; - union { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< ., array offset: 0xA0, array step: 0x4 */ - struct { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< ., offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< ., offset: 0xA4 */ - __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< ., array offset: 0xA8, array step: 0x4 */ - } PRINCE_REGION2_IV_CODE_CORE; - }; - uint8_t RESERVED_1[40]; - __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ -} FLASH_CFPA_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_CFPA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks - * @{ - */ - -/*! @name HEADER - . */ -/*! @{ */ -#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) -#define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) -/*! @} */ - -/*! @name VERSION - . */ -/*! @{ */ -#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ -/*! @{ */ -#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ -/*! @{ */ -#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) -#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) -/*! @} */ - -/*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ -/*! @{ */ -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) -#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) -/*! @} */ - -/*! @name ROTKH_REVOKE - . */ -/*! @{ */ -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) -#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) -/*! @} */ - -/*! @name VENDOR_USAGE - . */ -/*! @{ */ -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) -#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) -#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ -/*! @{ */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK (0x20U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT (5U) -/*! MCM33_DBGEN - Micro CM33 invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK (0x200U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT (9U) -/*! MCM33_NIDEN - Micro CM33 non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ -/*! @{ */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK (0x20U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT (5U) -/*! MCM33_DBGEN - Micro CM33 invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK (0x200U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT (9U) -/*! MCM33_NIDEN - Micro CM33 non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ -/*! @{ */ -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) -/*! @} */ - -/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ -/*! @{ */ -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) -#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_CODE - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION0_IV_HEADER0 - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_HEADER1 - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_IV_BODY - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) - -/*! @name PRINCE_REGION1_IV_CODE - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION1_IV_HEADER0 - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_IV_HEADER1 - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_IV_BODY - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) - -/*! @name PRINCE_REGION2_IV_CODE - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ -#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) - -/*! @name PRINCE_REGION2_IV_HEADER0 - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_IV_HEADER1 - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) -#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_IV_BODY - . */ -/*! @{ */ -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */ -#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U) - -/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ -/*! @{ */ -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) -#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_CUSTOMER_DEFINED */ -#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U) - -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ -/*! @{ */ -#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) -#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CFPA_SHA256_DIGEST */ -#define FLASH_CFPA_SHA256_DIGEST_COUNT (8U) - - -/*! - * @} - */ /* end of group FLASH_CFPA_Register_Masks */ - - -/* FLASH_CFPA - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE (0x1009E000u) - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE_NS (0x9E000u) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE (0x1009E200u) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE_NS (0x9E200u) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE (0x1009DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE_NS (0x9DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS) - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS } -#else - /** Peripheral FLASH_CFPA0 base address */ - #define FLASH_CFPA0_BASE (0x9E000u) - /** Peripheral FLASH_CFPA0 base pointer */ - #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) - /** Peripheral FLASH_CFPA1 base address */ - #define FLASH_CFPA1_BASE (0x9E200u) - /** Peripheral FLASH_CFPA1 base pointer */ - #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) - /** Peripheral FLASH_CFPA_SCRATCH base address */ - #define FLASH_CFPA_SCRATCH_BASE (0x9DE00u) - /** Peripheral FLASH_CFPA_SCRATCH base pointer */ - #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) - /** Array initializer of FLASH_CFPA peripheral base addresses */ - #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } - /** Array initializer of FLASH_CFPA peripheral base pointers */ - #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } -#endif - -/*! - * @} - */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_CMPA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer - * @{ - */ - -/** FLASH_CMPA - Register Layout Typedef */ -typedef struct { - __IO uint32_t BOOT_CFG; /**< ., offset: 0x0 */ - __IO uint32_t SPI_FLASH_CFG; /**< ., offset: 0x4 */ - __IO uint32_t USB_ID; /**< ., offset: 0x8 */ - __IO uint32_t SDIO_CFG; /**< ., offset: 0xC */ - __IO uint32_t DCFG_CC_SOCU_PIN; /**< ., offset: 0x10 */ - __IO uint32_t DCFG_CC_SOCU_DFLT; /**< ., offset: 0x14 */ - __IO uint32_t DAP_VENDOR_USAGE_FIXED; /**< ., offset: 0x18 */ - __IO uint32_t SECURE_BOOT_CFG; /**< ., offset: 0x1C */ - __IO uint32_t PRINCE_BASE_ADDR; /**< ., offset: 0x20 */ - __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ - __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ - __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ - uint8_t RESERVED_0[32]; - __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ - uint8_t RESERVED_1[144]; - __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ -} FLASH_CMPA_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_CMPA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks - * @{ - */ - -/*! @name BOOT_CFG - . */ -/*! @{ */ -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) -/*! DEFAULT_ISP_MODE - Default ISP mode: - * 0b000..Auto ISP - * 0b001..USB_HID_MSC - * 0b010..SPI Slave ISP - * 0b011..I2C Slave ISP - * 0b111..Disable ISP fall through - */ -#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) -/*! BOOT_SPEED - Core clock: - * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE - * 0b01..48MHz FRO - * 0b10..96MHz FRO - */ -#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) -#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) -/*! @} */ - -/*! @name SPI_FLASH_CFG - . */ -/*! @{ */ -#define FLASH_CMPA_SPI_FLASH_CFG_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SPI_FLASH_CFG_FIELD_SHIFT (0U) -#define FLASH_CMPA_SPI_FLASH_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_FIELD_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_FIELD_MASK) -/*! @} */ - -/*! @name USB_ID - . */ -/*! @{ */ -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) -#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) -#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) -/*! @} */ - -/*! @name SDIO_CFG - . */ -/*! @{ */ -#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) -#define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_PIN - . */ -/*! @{ */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK (0x20U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT (5U) -/*! MCM33_DBGEN - Micro CM33 invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK (0x200U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT (9U) -/*! MCM33_NIDEN - Micro CM33 non-invasive debug enable - * 0b0..Use DAP to enable - * 0b1..Fixed state - */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DCFG_CC_SOCU_DFLT - . */ -/*! @{ */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) -/*! NIDEN - Non Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) -/*! DBGEN - Non Secure debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) -/*! SPNIDEN - Secure non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) -/*! SPIDEN - Secure invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) -/*! TAPEN - JTAG TAP fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK (0x20U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT (5U) -/*! MCM33_DBGEN - Micro CM33 invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) -/*! ISP_CMD_EN - ISP Boot Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) -/*! FA_CMD_EN - FA Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) -/*! ME_CMD_EN - Flash Mass Erase Command fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK (0x200U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT (9U) -/*! MCM33_NIDEN - Micro CM33 non-invasive debug fixed state - * 0b0..Disable - * 0b1..Enable - */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) -/*! @} */ - -/*! @name DAP_VENDOR_USAGE_FIXED - . */ -/*! @{ */ -#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_MASK (0xFFFF0000U) -#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_SHIFT (16U) -#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_MASK) -/*! @} */ - -/*! @name SECURE_BOOT_CFG - . */ -/*! @{ */ -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) -#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK (0xCU) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT (2U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) -#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) -#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) -#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) -/*! @} */ - -/*! @name PRINCE_BASE_ADDR - . */ -/*! @{ */ -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x30000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0xC0000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x300000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) -/*! @} */ - -/*! @name PRINCE_SR_0 - Region 0, sub-region enable */ -/*! @{ */ -#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_SR_1 - Region 1, sub-region enable */ -/*! @{ */ -#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_SR_2 - Region 2, sub-region enable */ -/*! @{ */ -#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) -#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) -/*! @} */ - -/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] */ -/*! @{ */ -#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) -#define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_ROTKH */ -#define FLASH_CMPA_ROTKH_COUNT (8U) - -/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ -/*! @{ */ -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) -#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_CUSTOMER_DEFINED */ -#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U) - -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ -/*! @{ */ -#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) -#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_CMPA_SHA256_DIGEST */ -#define FLASH_CMPA_SHA256_DIGEST_COUNT (8U) - - -/*! - * @} - */ /* end of group FLASH_CMPA_Register_Masks */ - - -/* FLASH_CMPA - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE (0x1009E400u) - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE_NS (0x9E400u) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS) - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS } -#else - /** Peripheral FLASH_CMPA base address */ - #define FLASH_CMPA_BASE (0x9E400u) - /** Peripheral FLASH_CMPA base pointer */ - #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) - /** Array initializer of FLASH_CMPA peripheral base addresses */ - #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } - /** Array initializer of FLASH_CMPA peripheral base pointers */ - #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } -#endif - -/*! - * @} - */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLASH_KEY_STORE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer - * @{ - */ - -/** FLASH_KEY_STORE - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0 */ - __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */ - __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */ - } KEY_STORE_HEADER; - __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */ - union { /* offset: 0x4B0 */ - __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */ - struct { /* offset: 0x4B0 */ - __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */ - __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */ - __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */ - } SBKEY_KEY_CODE_CORE; - }; - union { /* offset: 0x4E8 */ - __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */ - struct { /* offset: 0x4E8 */ - __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */ - __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */ - __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */ - } USER_KEK_KEY_CODE_CORE; - }; - union { /* offset: 0x520 */ - __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */ - struct { /* offset: 0x520 */ - __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */ - __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */ - __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */ - } UDS_KEY_CODE_CORE; - }; - union { /* offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */ - struct { /* offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */ - __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */ - __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */ - } PRINCE_REGION0_KEY_CODE_CORE; - }; - union { /* offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */ - struct { /* offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */ - __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */ - __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */ - } PRINCE_REGION1_KEY_CODE_CORE; - }; - union { /* offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */ - struct { /* offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */ - __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */ - __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */ - } PRINCE_REGION2_KEY_CODE_CORE; - }; -} FLASH_KEY_STORE_Type; - -/* ---------------------------------------------------------------------------- - -- FLASH_KEY_STORE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks - * @{ - */ - -/*! @name HEADER - Valid Key Sore Header : 0x95959595 */ -/*! @{ */ -#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) -/*! @} */ - -/*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ -/*! @{ */ -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) -/*! @} */ - -/*! @name ACTIVATION_CODE - . */ -/*! @{ */ -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_ACTIVATION_CODE */ -#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U) - -/*! @name SBKEY_KEY_CODE - . */ -/*! @{ */ -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */ -#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U) - -/*! @name SBKEY_HEADER0 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name SBKEY_HEADER1 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) -#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name SBKEY_BODY - . */ -/*! @{ */ -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_SBKEY_BODY */ -#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U) - -/*! @name USER_KEK_KEY_CODE - . */ -/*! @{ */ -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */ -#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U) - -/*! @name USER_KEK_HEADER0 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name USER_KEK_HEADER1 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) -#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name USER_KEK_BODY - . */ -/*! @{ */ -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_USER_KEK_BODY */ -#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U) - -/*! @name UDS_KEY_CODE - . */ -/*! @{ */ -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_UDS_KEY_CODE */ -#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U) - -/*! @name UDS_HEADER0 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name UDS_HEADER1 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) -#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) -#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) -#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name UDS_BODY - . */ -/*! @{ */ -#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_UDS_BODY */ -#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U) - -/*! @name PRINCE_REGION0_KEY_CODE - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION0_HEADER0 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_HEADER1 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) -#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION0_BODY - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U) - -/*! @name PRINCE_REGION1_KEY_CODE - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION1_HEADER0 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_HEADER1 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) -#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION1_BODY - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U) - -/*! @name PRINCE_REGION2_KEY_CODE - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */ -#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U) - -/*! @name PRINCE_REGION2_HEADER0 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_HEADER1 - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) -#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) -/*! @} */ - -/*! @name PRINCE_REGION2_BODY - . */ -/*! @{ */ -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) -/*! @} */ - -/* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */ -#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U) - - -/*! - * @} - */ /* end of group FLASH_KEY_STORE_Register_Masks */ - - -/* FLASH_KEY_STORE - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE (0x1009E600u) - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE_NS (0x9E600u) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS) - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS } -#else - /** Peripheral FLASH_KEY_STORE base address */ - #define FLASH_KEY_STORE_BASE (0x9E600u) - /** Peripheral FLASH_KEY_STORE base pointer */ - #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) - /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ - #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } - /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ - #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } -#endif - -/*! - * @} - */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer - * @{ - */ - -/** FLEXCOMM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4088]; - __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ - __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ -} FLEXCOMM_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks - * @{ - */ - -/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ -/*! @{ */ -#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) -#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) -/*! PERSEL - Peripheral Select. This field is writable by software. - * 0b000..No peripheral selected. - * 0b001..USART function selected. - * 0b010..SPI function selected. - * 0b011..I2C function selected. - * 0b100..I2S transmit function selected. - * 0b101..I2S receive function selected. - * 0b110..Reserved - * 0b111..Reserved - */ -#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) -#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) -#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) -/*! LOCK - Lock the peripheral select. This field is writable by software. - * 0b0..Peripheral select can be changed by software. - * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. - */ -#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) -#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) -#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) -/*! USARTPRESENT - USART present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the USART function. - * 0b1..This Flexcomm includes the USART function. - */ -#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) -#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) -#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) -/*! SPIPRESENT - SPI present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the SPI function. - * 0b1..This Flexcomm includes the SPI function. - */ -#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) -#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) -#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) -/*! I2CPRESENT - I2C present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the I2C function. - * 0b1..This Flexcomm includes the I2C function. - */ -#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) -#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) -#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) -/*! I2SPRESENT - I 2S present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the I2S function. - * 0b1..This Flexcomm includes the I2S function. - */ -#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) -#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) -#define FLEXCOMM_PSELID_ID_SHIFT (12U) -#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) -/*! @} */ - -/*! @name PID - Peripheral identification register. */ -/*! @{ */ -#define FLEXCOMM_PID_Aperture_MASK (0xFFU) -#define FLEXCOMM_PID_Aperture_SHIFT (0U) -#define FLEXCOMM_PID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Aperture_SHIFT)) & FLEXCOMM_PID_Aperture_MASK) -#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) -#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) -#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) -#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) -#define FLEXCOMM_PID_Major_Rev_SHIFT (12U) -#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) -#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) -#define FLEXCOMM_PID_ID_SHIFT (16U) -#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLEXCOMM_Register_Masks */ - - -/* FLEXCOMM - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE (0x50086000u) - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE_NS (0x40086000u) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE (0x50087000u) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE_NS (0x40087000u) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE (0x50088000u) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE_NS (0x40088000u) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE (0x50089000u) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE_NS (0x40089000u) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE (0x5008A000u) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE_NS (0x4008A000u) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE (0x50096000u) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE_NS (0x40096000u) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE (0x50097000u) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE_NS (0x40097000u) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE (0x50098000u) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE_NS (0x40098000u) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE (0x5009F000u) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE_NS (0x4009F000u) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } -#else - /** Peripheral FLEXCOMM0 base address */ - #define FLEXCOMM0_BASE (0x40086000u) - /** Peripheral FLEXCOMM0 base pointer */ - #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) - /** Peripheral FLEXCOMM1 base address */ - #define FLEXCOMM1_BASE (0x40087000u) - /** Peripheral FLEXCOMM1 base pointer */ - #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) - /** Peripheral FLEXCOMM2 base address */ - #define FLEXCOMM2_BASE (0x40088000u) - /** Peripheral FLEXCOMM2 base pointer */ - #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) - /** Peripheral FLEXCOMM3 base address */ - #define FLEXCOMM3_BASE (0x40089000u) - /** Peripheral FLEXCOMM3 base pointer */ - #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) - /** Peripheral FLEXCOMM4 base address */ - #define FLEXCOMM4_BASE (0x4008A000u) - /** Peripheral FLEXCOMM4 base pointer */ - #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) - /** Peripheral FLEXCOMM5 base address */ - #define FLEXCOMM5_BASE (0x40096000u) - /** Peripheral FLEXCOMM5 base pointer */ - #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) - /** Peripheral FLEXCOMM6 base address */ - #define FLEXCOMM6_BASE (0x40097000u) - /** Peripheral FLEXCOMM6 base pointer */ - #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) - /** Peripheral FLEXCOMM7 base address */ - #define FLEXCOMM7_BASE (0x40098000u) - /** Peripheral FLEXCOMM7 base pointer */ - #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) - /** Peripheral FLEXCOMM8 base address */ - #define FLEXCOMM8_BASE (0x4009F000u) - /** Peripheral FLEXCOMM8 base pointer */ - #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) - /** Array initializer of FLEXCOMM peripheral base addresses */ - #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } - /** Array initializer of FLEXCOMM peripheral base pointers */ - #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } -#endif -/** Interrupt vectors for the FLEXCOMM peripheral type */ -#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, LSPI_HS_IRQn } - -/*! - * @} - */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer - * @{ - */ - -/** GINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ - uint8_t RESERVED_0[28]; - __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[24]; - __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ -} GINT_Type; - -/* ---------------------------------------------------------------------------- - -- GINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Register_Masks GINT Register Masks - * @{ - */ - -/*! @name CTRL - GPIO grouped interrupt control register */ -/*! @{ */ -#define GINT_CTRL_INT_MASK (0x1U) -#define GINT_CTRL_INT_SHIFT (0U) -/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. - * 0b0..No request. No interrupt request is pending. - * 0b1..Request active. Interrupt request is active. - */ -#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) -#define GINT_CTRL_COMB_MASK (0x2U) -#define GINT_CTRL_COMB_SHIFT (1U) -/*! COMB - Combine enabled inputs for group interrupt - * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). - * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). - */ -#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) -#define GINT_CTRL_TRIG_MASK (0x4U) -#define GINT_CTRL_TRIG_SHIFT (2U) -/*! TRIG - Group interrupt trigger - * 0b0..Edge-triggered. - * 0b1..Level-triggered. - */ -#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) -/*! @} */ - -/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ -/*! @{ */ -#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) -#define GINT_PORT_POL_POL_SHIFT (0U) -#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) -/*! @} */ - -/* The count of GINT_PORT_POL */ -#define GINT_PORT_POL_COUNT (2U) - -/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ -/*! @{ */ -#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) -#define GINT_PORT_ENA_ENA_SHIFT (0U) -#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) -/*! @} */ - -/* The count of GINT_PORT_ENA */ -#define GINT_PORT_ENA_COUNT (2U) - - -/*! - * @} - */ /* end of group GINT_Register_Masks */ - - -/* GINT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral GINT0 base address */ - #define GINT0_BASE (0x50002000u) - /** Peripheral GINT0 base address */ - #define GINT0_BASE_NS (0x40002000u) - /** Peripheral GINT0 base pointer */ - #define GINT0 ((GINT_Type *)GINT0_BASE) - /** Peripheral GINT0 base pointer */ - #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) - /** Peripheral GINT1 base address */ - #define GINT1_BASE (0x50003000u) - /** Peripheral GINT1 base address */ - #define GINT1_BASE_NS (0x40003000u) - /** Peripheral GINT1 base pointer */ - #define GINT1 ((GINT_Type *)GINT1_BASE) - /** Peripheral GINT1 base pointer */ - #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS { GINT0, GINT1 } - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } -#else - /** Peripheral GINT0 base address */ - #define GINT0_BASE (0x40002000u) - /** Peripheral GINT0 base pointer */ - #define GINT0 ((GINT_Type *)GINT0_BASE) - /** Peripheral GINT1 base address */ - #define GINT1_BASE (0x40003000u) - /** Peripheral GINT1 base pointer */ - #define GINT1 ((GINT_Type *)GINT1_BASE) - /** Array initializer of GINT peripheral base addresses */ - #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } - /** Array initializer of GINT peripheral base pointers */ - #define GINT_BASE_PTRS { GINT0, GINT1 } -#endif -/** Interrupt vectors for the GINT peripheral type */ -#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } - -/*! - * @} - */ /* end of group GINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint8_t B[4][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ - uint8_t RESERVED_0[3968]; - __IO uint32_t W[4][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ - uint8_t RESERVED_1[3584]; - __IO uint32_t DIR[4]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ - uint8_t RESERVED_2[112]; - __IO uint32_t MASK[4]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ - uint8_t RESERVED_3[112]; - __IO uint32_t PIN[4]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ - uint8_t RESERVED_4[112]; - __IO uint32_t MPIN[4]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ - uint8_t RESERVED_5[112]; - __IO uint32_t SET[4]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ - uint8_t RESERVED_6[112]; - __O uint32_t CLR[4]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ - uint8_t RESERVED_7[112]; - __O uint32_t NOT[4]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ - uint8_t RESERVED_8[112]; - __O uint32_t DIRSET[4]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ - uint8_t RESERVED_9[112]; - __O uint32_t DIRCLR[4]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ - uint8_t RESERVED_10[112]; - __O uint32_t DIRNOT[4]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/*! @name B - Byte pin registers for all port GPIO pins */ -/*! @{ */ -#define GPIO_B_PBYTE_MASK (0x1U) -#define GPIO_B_PBYTE_SHIFT (0U) -#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) -/*! @} */ - -/* The count of GPIO_B */ -#define GPIO_B_COUNT (4U) - -/* The count of GPIO_B */ -#define GPIO_B_COUNT2 (32U) - -/*! @name W - Word pin registers for all port GPIO pins */ -/*! @{ */ -#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) -#define GPIO_W_PWORD_SHIFT (0U) -#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) -/*! @} */ - -/* The count of GPIO_W */ -#define GPIO_W_COUNT (4U) - -/* The count of GPIO_W */ -#define GPIO_W_COUNT2 (32U) - -/*! @name DIR - Direction registers for all port GPIO pins */ -/*! @{ */ -#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) -#define GPIO_DIR_DIRP_SHIFT (0U) -#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) -/*! @} */ - -/* The count of GPIO_DIR */ -#define GPIO_DIR_COUNT (4U) - -/*! @name MASK - Mask register for all port GPIO pins */ -/*! @{ */ -#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) -#define GPIO_MASK_MASKP_SHIFT (0U) -#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) -/*! @} */ - -/* The count of GPIO_MASK */ -#define GPIO_MASK_COUNT (4U) - -/*! @name PIN - Port pin register for all port GPIO pins */ -/*! @{ */ -#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) -#define GPIO_PIN_PORT_SHIFT (0U) -#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) -/*! @} */ - -/* The count of GPIO_PIN */ -#define GPIO_PIN_COUNT (4U) - -/*! @name MPIN - Masked port register for all port GPIO pins */ -/*! @{ */ -#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) -#define GPIO_MPIN_MPORTP_SHIFT (0U) -#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) -/*! @} */ - -/* The count of GPIO_MPIN */ -#define GPIO_MPIN_COUNT (4U) - -/*! @name SET - Write: Set register for port. Read: output bits for port */ -/*! @{ */ -#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) -#define GPIO_SET_SETP_SHIFT (0U) -#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) -/*! @} */ - -/* The count of GPIO_SET */ -#define GPIO_SET_COUNT (4U) - -/*! @name CLR - Clear port for all port GPIO pins */ -/*! @{ */ -#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) -#define GPIO_CLR_CLRP_SHIFT (0U) -#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) -/*! @} */ - -/* The count of GPIO_CLR */ -#define GPIO_CLR_COUNT (4U) - -/*! @name NOT - Toggle port for all port GPIO pins */ -/*! @{ */ -#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) -#define GPIO_NOT_NOTP_SHIFT (0U) -#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) -/*! @} */ - -/* The count of GPIO_NOT */ -#define GPIO_NOT_COUNT (4U) - -/*! @name DIRSET - Set pin direction bits for port */ -/*! @{ */ -#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) -#define GPIO_DIRSET_DIRSETP_SHIFT (0U) -#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) -/*! @} */ - -/* The count of GPIO_DIRSET */ -#define GPIO_DIRSET_COUNT (4U) - -/*! @name DIRCLR - Clear pin direction bits for port */ -/*! @{ */ -#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) -#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) -#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) -/*! @} */ - -/* The count of GPIO_DIRCLR */ -#define GPIO_DIRCLR_COUNT (4U) - -/*! @name DIRNOT - Toggle pin direction bits for port */ -/*! @{ */ -#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) -#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) -#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) -/*! @} */ - -/* The count of GPIO_DIRNOT */ -#define GPIO_DIRNOT_COUNT (4U) - - -/*! - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral GPIO base address */ - #define GPIO_BASE (0x5008C000u) - /** Peripheral GPIO base address */ - #define GPIO_BASE_NS (0x4008C000u) - /** Peripheral GPIO base pointer */ - #define GPIO ((GPIO_Type *)GPIO_BASE) - /** Peripheral GPIO base pointer */ - #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE (0x500A8000u) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE_NS (0x400A8000u) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO, SECGPIO } - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } -#else - /** Peripheral GPIO base address */ - #define GPIO_BASE (0x4008C000u) - /** Peripheral GPIO base pointer */ - #define GPIO ((GPIO_Type *)GPIO_BASE) - /** Peripheral SECGPIO base address */ - #define SECGPIO_BASE (0x400A8000u) - /** Peripheral SECGPIO base pointer */ - #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) - /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } - /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO, SECGPIO } -#endif - -/*! - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- HASHCRYPT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer - * @{ - */ - -/** HASHCRYPT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Is control register to enable and operate Hash and Crypto, offset: 0x0 */ - __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */ - __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */ - __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */ - __IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available), offset: 0x10 */ - __IO uint32_t MEMADDR; /**< Address to start memory access from (if available)., offset: 0x14 */ - uint8_t RESERVED_0[8]; - __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */ - __O uint32_t ALIAS[7]; /**< , array offset: 0x24, array step: 0x4 */ - __I uint32_t OUTDATA0[8]; /**< , array offset: 0x40, array step: 0x4 */ - __I uint32_t OUTDATA1[8]; /**< , array offset: 0x60, array step: 0x4 */ - __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */ - __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */ - uint8_t RESERVED_1[4]; - __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */ - __O uint32_t MASK[4]; /**< , array offset: 0x90, array step: 0x4 */ -} HASHCRYPT_Type; - -/* ---------------------------------------------------------------------------- - -- HASHCRYPT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks - * @{ - */ - -/*! @name CTRL - Is control register to enable and operate Hash and Crypto */ -/*! @{ */ -#define HASHCRYPT_CTRL_MODE_MASK (0x7U) -#define HASHCRYPT_CTRL_MODE_SHIFT (0U) -/*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available. - * 0b000..Disabled - * 0b001..SHA1 is enabled - * 0b010..SHA2-256 is enabled - * 0b011..SHA2-512 is enabled (if available) - * 0b100..AES if available (see also CRYPTCFG register for more controls) - * 0b101..ICB-AES if available (see also CRYPTCFG register for more controls) - * 0b110..Salsa20/20 if available (including XSalsa - see also CRYPTCFG register) - * 0b111..ChaCha20 if available (see also CRYPTCFG register for more controls) - */ -#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK) -#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U) -#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U) -/*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1. - * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result. - */ -#define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK) -#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U) -#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U) -/*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed). - * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. - * 0b1..DMA will push in the data. - */ -#define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK) -#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U) -#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U) -/*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses. - * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. - */ -#define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK) -#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U) -#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U) -#define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK) -/*! @} */ - -/*! @name STATUS - Indicates status of Hash peripheral. */ -/*! @{ */ -#define HASHCRYPT_STATUS_WAITING_MASK (0x1U) -#define HASHCRYPT_STATUS_WAITING_SHIFT (0U) -/*! WAITING - If 1, the block is waiting for more data to process. - * 0b0..Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set if IsLast is set nor will it set until at least 1 word is read of the output. - * 0b1..Waiting for data to be written in (16 words) - */ -#define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK) -#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK (0x2U) -#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_SHIFT (1U) -/*! DIGEST_aka_OUTDATA - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block already started. For Cryptographic uses, this will be set for each block processed, indicating OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared when any data is written, when New is written, for Cryptographic uses when the last word is read out, or when the block is disabled. - * 0b0..No Digest is ready - * 0b1..Digest is ready. Application may read it or may write more data - */ -#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_SHIFT)) & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK) -#define HASHCRYPT_STATUS_ERROR_MASK (0x4U) -#define HASHCRYPT_STATUS_ERROR_SHIFT (2U) -/*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT field will indicate which block it was on. - * 0b0..No error. - * 0b1..An error occurred since last cleared (written 1 to clear). - */ -#define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK) -#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U) -#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U) -/*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) - * 0b0..No Key is needed and writes will not be treated as Key - * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. - */ -#define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK) -#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U) -#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U) -/*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) - * 0b0..No IV/Nonce is needed, either because written already or because not needed. - * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. - */ -#define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK) -#define HASHCRYPT_STATUS_ICBIDX_MASK (0x3F0000U) -#define HASHCRYPT_STATUS_ICBIDX_SHIFT (16U) -#define HASHCRYPT_STATUS_ICBIDX(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK) -/*! @} */ - -/*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */ -/*! @{ */ -#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U) -#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U) -/*! WAITING - Indicates if should interrupt when waiting for data input. - * 0b0..Will not interrupt when waiting. - * 0b1..Will interrupt when waiting - */ -#define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK) -#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U) -#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U) -/*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). - * 0b0..Will not interrupt when Digest is ready - * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). - */ -#define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK) -#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U) -#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U) -/*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status) - * 0b0..Will not interrupt on Error. - * 0b1..Will interrupt on Error (until cleared). - */ -#define HASHCRYPT_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK) -/*! @} */ - -/*! @name INTENCLR - Write 1 to clear interrupts. */ -/*! @{ */ -#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U) -#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U) -#define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK) -#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U) -#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U) -#define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK) -#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U) -#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U) -#define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK) -/*! @} */ - -/*! @name MEMCTRL - Setup Master to access memory (if available) */ -/*! @{ */ -#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U) -#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U) -/*! MASTER - * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. - * 0b1..Mastering is enabled and DMA and INDATA should not be used. - */ -#define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK) -#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U) -#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U) -#define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK) -/*! @} */ - -/*! @name MEMADDR - Address to start memory access from (if available). */ -/*! @{ */ -#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU) -#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U) -#define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK) -/*! @} */ - -/*! @name INDATA - Input of 16 words at a time to load up buffer. */ -/*! @{ */ -#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU) -#define HASHCRYPT_INDATA_DATA_SHIFT (0U) -#define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK) -/*! @} */ - -/*! @name ALIAS - */ -/*! @{ */ -#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU) -#define HASHCRYPT_ALIAS_DATA_SHIFT (0U) -#define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK) -/*! @} */ - -/* The count of HASHCRYPT_ALIAS */ -#define HASHCRYPT_ALIAS_COUNT (7U) - -/*! @name OUTDATA0 - */ -/*! @{ */ -#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_MASK (0xFFFFFFFFU) -#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_SHIFT (0U) -#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_SHIFT)) & HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_MASK) -/*! @} */ - -/* The count of HASHCRYPT_OUTDATA0 */ -#define HASHCRYPT_OUTDATA0_COUNT (8U) - -/*! @name OUTDATA1 - */ -/*! @{ */ -#define HASHCRYPT_OUTDATA1_OUTPUT_MASK (0xFFFFFFFFU) -#define HASHCRYPT_OUTDATA1_OUTPUT_SHIFT (0U) -#define HASHCRYPT_OUTDATA1_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_OUTDATA1_OUTPUT_SHIFT)) & HASHCRYPT_OUTDATA1_OUTPUT_MASK) -/*! @} */ - -/* The count of HASHCRYPT_OUTDATA1 */ -#define HASHCRYPT_OUTDATA1_COUNT (8U) - -/*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */ -/*! @{ */ -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U) -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U) -#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK) -#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U) -#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U) -#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK) -#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U) -#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U) -#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK) -#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U) -#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U) -#define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK) -#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U) -#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U) -/*! AESMODE - AES Cipher mode to use if plain AES - * 0b00..ECB - used as is - * 0b01..CBC mode (see details on IV/nonce) - * 0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS. - * 0b11..reserved - */ -#define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK) -#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U) -#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U) -/*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB - * 0b0..Encrypt - * 0b1..Decrypt - */ -#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK) -#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U) -#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U) -/*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are used, only the highest level is permitted to select this. - * 0b0..User key provided in normal way - * 0b1..Secret key provided in hidden way by HW - */ -#define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK) -#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U) -#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U) -/*! AESKEYSZ - Sets the AES key size - * 0b00..128 bit key - * 0b01..192 bit key - * 0b10..256 bit key - * 0b11..reserved - */ -#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK) -#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U) -#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U) -#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK) -#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U) -#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U) -#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK) -#define HASHCRYPT_CRYPTCFG_XSALSA_MASK (0x20000U) -#define HASHCRYPT_CRYPTCFG_XSALSA_SHIFT (17U) -#define HASHCRYPT_CRYPTCFG_XSALSA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_XSALSA_SHIFT)) & HASHCRYPT_CRYPTCFG_XSALSA_MASK) -#define HASHCRYPT_CRYPTCFG_ICBSZ_MASK (0x300000U) -#define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT (20U) -/*! ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the counter is assumed to occupy the low order bits of the IV. - * 0b00..32 bits of the IV/ctr are used (from 127:96) - * 0b01..64 bits of the IV/ctr are used (from 127:64) - * 0b10..96 bits of the IV/ctr are used (from 127:32) - * 0b11..All 128 bits of the IV/ctr are used - */ -#define HASHCRYPT_CRYPTCFG_ICBSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK) -#define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK (0xC00000U) -#define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT (22U) -/*! ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st. - * 0b00..8 blocks - * 0b01..16 blocks - * 0b10..32 blocks - * 0b11..64 blocks - */ -#define HASHCRYPT_CRYPTCFG_ICBSTRM(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSTRM_MASK) -/*! @} */ - -/*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */ -/*! @{ */ -#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U) -#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U) -#define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK) -#define HASHCRYPT_CONFIG_DMA_MASK (0x2U) -#define HASHCRYPT_CONFIG_DMA_SHIFT (1U) -#define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK) -#define HASHCRYPT_CONFIG_AHB_MASK (0x8U) -#define HASHCRYPT_CONFIG_AHB_SHIFT (3U) -#define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK) -#define HASHCRYPT_CONFIG_SHA512_MASK (0x20U) -#define HASHCRYPT_CONFIG_SHA512_SHIFT (5U) -#define HASHCRYPT_CONFIG_SHA512(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SHA512_SHIFT)) & HASHCRYPT_CONFIG_SHA512_MASK) -#define HASHCRYPT_CONFIG_AES_MASK (0x40U) -#define HASHCRYPT_CONFIG_AES_SHIFT (6U) -#define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK) -#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U) -#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U) -#define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK) -#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U) -#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U) -#define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK) -#define HASHCRYPT_CONFIG_SALSA_MASK (0x200U) -#define HASHCRYPT_CONFIG_SALSA_SHIFT (9U) -#define HASHCRYPT_CONFIG_SALSA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SALSA_SHIFT)) & HASHCRYPT_CONFIG_SALSA_MASK) -#define HASHCRYPT_CONFIG_CHACHA_MASK (0x400U) -#define HASHCRYPT_CONFIG_CHACHA_SHIFT (10U) -#define HASHCRYPT_CONFIG_CHACHA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_CHACHA_SHIFT)) & HASHCRYPT_CONFIG_CHACHA_MASK) -#define HASHCRYPT_CONFIG_ICB_MASK (0x800U) -#define HASHCRYPT_CONFIG_ICB_SHIFT (11U) -#define HASHCRYPT_CONFIG_ICB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK) -/*! @} */ - -/*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */ -/*! @{ */ -#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U) -#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U) -/*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. If locked already, may only write if at same or higher security level as lock. Reads as: 0 if unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the only readable registers if locked and current state is lower than lock level. - * 0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. - * 0b01..Locks to the current security level. AHB Master will issue requests at this level. - */ -#define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK) -#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U) -#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U) -#define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK) -/*! @} */ - -/*! @name MASK - */ -/*! @{ */ -#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU) -#define HASHCRYPT_MASK_MASK_SHIFT (0U) -#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK) -/*! @} */ - -/* The count of HASHCRYPT_MASK */ -#define HASHCRYPT_MASK_COUNT (4U) - - -/*! - * @} - */ /* end of group HASHCRYPT_Register_Masks */ - - -/* HASHCRYPT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE (0x500A4000u) - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE_NS (0x400A4000u) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS) - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS { HASHCRYPT } - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS } -#else - /** Peripheral HASHCRYPT base address */ - #define HASHCRYPT_BASE (0x400A4000u) - /** Peripheral HASHCRYPT base pointer */ - #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) - /** Array initializer of HASHCRYPT peripheral base addresses */ - #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } - /** Array initializer of HASHCRYPT peripheral base pointers */ - #define HASHCRYPT_BASE_PTRS { HASHCRYPT } -#endif - -/*! - * @} - */ /* end of group HASHCRYPT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer - * @{ - */ - -/** I2C - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[2048]; - __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ - __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ - __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ - __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ - __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ - __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ - uint8_t RESERVED_1[4]; - __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ - __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ - __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ - uint8_t RESERVED_2[20]; - __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ - __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ - __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ - __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ - uint8_t RESERVED_3[36]; - __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ - uint8_t RESERVED_4[1912]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} I2C_Type; - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/*! @name CFG - Configuration for shared functions. */ -/*! @{ */ -#define I2C_CFG_MSTEN_MASK (0x1U) -#define I2C_CFG_MSTEN_SHIFT (0U) -/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. - * 0b0..Disabled. The I2C Master function is disabled. - * 0b1..Enabled. The I2C Master function is enabled. - */ -#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) -#define I2C_CFG_SLVEN_MASK (0x2U) -#define I2C_CFG_SLVEN_SHIFT (1U) -/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. - * 0b0..Disabled. The I2C slave function is disabled. - * 0b1..Enabled. The I2C slave function is enabled. - */ -#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) -#define I2C_CFG_MONEN_MASK (0x4U) -#define I2C_CFG_MONEN_SHIFT (2U) -/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. - * 0b0..Disabled. The I2C Monitor function is disabled. - * 0b1..Enabled. The I2C Monitor function is enabled. - */ -#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) -#define I2C_CFG_TIMEOUTEN_MASK (0x8U) -#define I2C_CFG_TIMEOUTEN_SHIFT (3U) -/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. - * 0b0..Disabled. Time-out function is disabled. - * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. - */ -#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) -#define I2C_CFG_MONCLKSTR_MASK (0x10U) -#define I2C_CFG_MONCLKSTR_SHIFT (4U) -/*! MONCLKSTR - Monitor function Clock Stretching. - * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. - * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function. - */ -#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) -#define I2C_CFG_HSCAPABLE_MASK (0x20U) -#define I2C_CFG_HSCAPABLE_SHIFT (5U) -/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor. - * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin, - * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information. - */ -#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) -/*! @} */ - -/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ -#define I2C_STAT_MSTPENDING_MASK (0x1U) -#define I2C_STAT_MSTPENDING_SHIFT (0U) -/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. - * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. - * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. - */ -#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) -#define I2C_STAT_MSTSTATE_MASK (0xEU) -#define I2C_STAT_MSTSTATE_SHIFT (1U) -/*! MSTSTATE - Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. - * 0b000..Idle. The Master function is available to be used for a new transaction. - * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. - * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. - * 0b011..NACK Address. Slave NACKed address. - * 0b100..NACK Data. Slave NACKed transmitted data. - */ -#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) -#define I2C_STAT_MSTARBLOSS_MASK (0x10U) -#define I2C_STAT_MSTARBLOSS_SHIFT (4U) -/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - * 0b0..No Arbitration Loss has occurred. - * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. - */ -#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) -#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) -/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - * 0b0..No Start/Stop Error has occurred. - * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. - */ -#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) -#define I2C_STAT_SLVPENDING_MASK (0x100U) -#define I2C_STAT_SLVPENDING_SHIFT (8U) -/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. - * 0b0..In progress. The Slave function does not currently need service. - * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. - */ -#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) -#define I2C_STAT_SLVSTATE_MASK (0x600U) -#define I2C_STAT_SLVSTATE_SHIFT (9U) -/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. - * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. - * 0b01..Slave receive. Received data is available (Slave Receiver mode). - * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). - */ -#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) -#define I2C_STAT_SLVNOTSTR_MASK (0x800U) -#define I2C_STAT_SLVNOTSTR_SHIFT (11U) -/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. - * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. - * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. - */ -#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) -#define I2C_STAT_SLVIDX_MASK (0x3000U) -#define I2C_STAT_SLVIDX_SHIFT (12U) -/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. - * 0b00..Address 0. Slave address 0 was matched. - * 0b01..Address 1. Slave address 1 was matched. - * 0b10..Address 2. Slave address 2 was matched. - * 0b11..Address 3. Slave address 3 was matched. - */ -#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) -#define I2C_STAT_SLVSEL_MASK (0x4000U) -#define I2C_STAT_SLVSEL_SHIFT (14U) -/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. - * 0b0..Not selected. The Slave function is not currently selected. - * 0b1..Selected. The Slave function is currently selected. - */ -#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) -#define I2C_STAT_SLVDESEL_MASK (0x8000U) -#define I2C_STAT_SLVDESEL_SHIFT (15U) -/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. - * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. - * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. - */ -#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) -#define I2C_STAT_MONRDY_MASK (0x10000U) -#define I2C_STAT_MONRDY_SHIFT (16U) -/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. - * 0b0..No data. The Monitor function does not currently have data available. - * 0b1..Data waiting. The Monitor function has data waiting to be read. - */ -#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) -#define I2C_STAT_MONOV_MASK (0x20000U) -#define I2C_STAT_MONOV_SHIFT (17U) -/*! MONOV - Monitor Overflow flag. - * 0b0..No overrun. Monitor data has not overrun. - * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. - */ -#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) -#define I2C_STAT_MONACTIVE_MASK (0x40000U) -#define I2C_STAT_MONACTIVE_SHIFT (18U) -/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. - * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. - * 0b1..Active. The Monitor function considers the I2C bus to be active. - */ -#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) -#define I2C_STAT_MONIDLE_MASK (0x80000U) -#define I2C_STAT_MONIDLE_SHIFT (19U) -/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. - * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. - * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. - */ -#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) -#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) -/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. - * 0b0..No time-out. I2C bus events have not caused a time-out. - * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. - */ -#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) -#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) -/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. - * 0b0..No time-out. SCL low time has not caused a time-out. - * 0b1..Time-out. SCL low time has caused a time-out. - */ -#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable Set and read register. */ -/*! @{ */ -#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) -#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) -/*! MSTPENDINGEN - Master Pending interrupt Enable. - * 0b0..Disabled. The MstPending interrupt is disabled. - * 0b1..Enabled. The MstPending interrupt is enabled. - */ -#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) -#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) -#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) -/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. - * 0b0..Disabled. The MstArbLoss interrupt is disabled. - * 0b1..Enabled. The MstArbLoss interrupt is enabled. - */ -#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) -#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) -#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) -/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. - * 0b0..Disabled. The MstStStpErr interrupt is disabled. - * 0b1..Enabled. The MstStStpErr interrupt is enabled. - */ -#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) -#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) -#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) -/*! SLVPENDINGEN - Slave Pending interrupt Enable. - * 0b0..Disabled. The SlvPending interrupt is disabled. - * 0b1..Enabled. The SlvPending interrupt is enabled. - */ -#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) -#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) -#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) -/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. - * 0b0..Disabled. The SlvNotStr interrupt is disabled. - * 0b1..Enabled. The SlvNotStr interrupt is enabled. - */ -#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) -#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) -#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) -/*! SLVDESELEN - Slave Deselect interrupt Enable. - * 0b0..Disabled. The SlvDeSel interrupt is disabled. - * 0b1..Enabled. The SlvDeSel interrupt is enabled. - */ -#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) -#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) -#define I2C_INTENSET_MONRDYEN_SHIFT (16U) -/*! MONRDYEN - Monitor data Ready interrupt Enable. - * 0b0..Disabled. The MonRdy interrupt is disabled. - * 0b1..Enabled. The MonRdy interrupt is enabled. - */ -#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) -#define I2C_INTENSET_MONOVEN_MASK (0x20000U) -#define I2C_INTENSET_MONOVEN_SHIFT (17U) -/*! MONOVEN - Monitor Overrun interrupt Enable. - * 0b0..Disabled. The MonOv interrupt is disabled. - * 0b1..Enabled. The MonOv interrupt is enabled. - */ -#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) -#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) -#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) -/*! MONIDLEEN - Monitor Idle interrupt Enable. - * 0b0..Disabled. The MonIdle interrupt is disabled. - * 0b1..Enabled. The MonIdle interrupt is enabled. - */ -#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) -#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) -#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) -/*! EVENTTIMEOUTEN - Event time-out interrupt Enable. - * 0b0..Disabled. The Event time-out interrupt is disabled. - * 0b1..Enabled. The Event time-out interrupt is enabled. - */ -#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) -#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) -#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) -/*! SCLTIMEOUTEN - SCL time-out interrupt Enable. - * 0b0..Disabled. The SCL time-out interrupt is disabled. - * 0b1..Enabled. The SCL time-out interrupt is enabled. - */ -#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. */ -/*! @{ */ -#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) -#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) -#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) -#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) -#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) -#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) -#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) -#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) -#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) -#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) -#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) -#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) -#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) -#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) -#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) -#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) -#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) -#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) -#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) -#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) -#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) -#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) -#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) -#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) -#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) -#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) -#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) -#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) -#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) -#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) -/*! @} */ - -/*! @name TIMEOUT - Time-out value register. */ -/*! @{ */ -#define I2C_TIMEOUT_TOMIN_MASK (0xFU) -#define I2C_TIMEOUT_TOMIN_SHIFT (0U) -#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) -#define I2C_TIMEOUT_TO_MASK (0xFFF0U) -#define I2C_TIMEOUT_TO_SHIFT (4U) -#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) -/*! @} */ - -/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ -/*! @{ */ -#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) -#define I2C_CLKDIV_DIVVAL_SHIFT (0U) -#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ -#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) -#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) -#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) -#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) -#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) -#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) -#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) -#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) -#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) -#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) -#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) -#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) -#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) -#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) -#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) -#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) -#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) -#define I2C_INTSTAT_MONRDY_MASK (0x10000U) -#define I2C_INTSTAT_MONRDY_SHIFT (16U) -#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) -#define I2C_INTSTAT_MONOV_MASK (0x20000U) -#define I2C_INTSTAT_MONOV_SHIFT (17U) -#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) -#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) -#define I2C_INTSTAT_MONIDLE_SHIFT (19U) -#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) -#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) -#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) -#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) -#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name MSTCTL - Master control register. */ -/*! @{ */ -#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) -#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) -/*! MSTCONTINUE - Master Continue. This bit is write-only. - * 0b0..No effect. - * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. - */ -#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) -#define I2C_MSTCTL_MSTSTART_MASK (0x2U) -#define I2C_MSTCTL_MSTSTART_SHIFT (1U) -/*! MSTSTART - Master Start control. This bit is write-only. - * 0b0..No effect. - * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. - */ -#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) -#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) -#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) -/*! MSTSTOP - Master Stop control. This bit is write-only. - * 0b0..No effect. - * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). - */ -#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) -#define I2C_MSTCTL_MSTDMA_MASK (0x8U) -#define I2C_MSTCTL_MSTDMA_SHIFT (3U) -/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. - * 0b0..Disable. No DMA requests are generated for master operation. - * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. - */ -#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) -/*! @} */ - -/*! @name MSTTIME - Master timing configuration. */ -/*! @{ */ -#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) -#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) -/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. - * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. - * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) -#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) -#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) -/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. - * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . - * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) -/*! @} */ - -/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ -/*! @{ */ -#define I2C_MSTDAT_DATA_MASK (0xFFU) -#define I2C_MSTDAT_DATA_SHIFT (0U) -#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVCTL - Slave control register. */ -/*! @{ */ -#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) -#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) -/*! SLVCONTINUE - Slave Continue. - * 0b0..No effect. - * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1. - */ -#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) -#define I2C_SLVCTL_SLVNACK_MASK (0x2U) -#define I2C_SLVCTL_SLVNACK_SHIFT (1U) -/*! SLVNACK - Slave NACK. - * 0b0..No effect. - * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). - */ -#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) -#define I2C_SLVCTL_SLVDMA_MASK (0x8U) -#define I2C_SLVCTL_SLVDMA_SHIFT (3U) -/*! SLVDMA - Slave DMA enable. - * 0b0..Disabled. No DMA requests are issued for Slave mode operation. - * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. - */ -#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) -#define I2C_SLVCTL_AUTOACK_MASK (0x100U) -#define I2C_SLVCTL_AUTOACK_SHIFT (8U) -/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt. - * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored). - * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. - */ -#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) -#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) -#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) -/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation. - * 0b0..The expected next operation in Automatic Mode is an I2C write. - * 0b1..The expected next operation in Automatic Mode is an I2C read. - */ -#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) -/*! @} */ - -/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ -/*! @{ */ -#define I2C_SLVDAT_DATA_MASK (0xFFU) -#define I2C_SLVDAT_DATA_SHIFT (0U) -#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVADR - Slave address register. */ -/*! @{ */ -#define I2C_SLVADR_SADISABLE_MASK (0x1U) -#define I2C_SLVADR_SADISABLE_SHIFT (0U) -/*! SADISABLE - Slave Address n Disable. - * 0b0..Enabled. Slave Address n is enabled. - * 0b1..Ignored Slave Address n is ignored. - */ -#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) -#define I2C_SLVADR_SLVADR_MASK (0xFEU) -#define I2C_SLVADR_SLVADR_SHIFT (1U) -#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) -#define I2C_SLVADR_AUTONACK_MASK (0x8000U) -#define I2C_SLVADR_AUTONACK_SHIFT (15U) -/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations. - * 0b0..Normal operation, matching I2C addresses are not ignored. - * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction. - */ -#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) -/*! @} */ - -/* The count of I2C_SLVADR */ -#define I2C_SLVADR_COUNT (4U) - -/*! @name SLVQUAL0 - Slave Qualification for address 0. */ -/*! @{ */ -#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) -#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) -/*! QUALMODE0 - Qualify mode for slave address 0. - * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. - * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. - */ -#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) -#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) -#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) -#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) -/*! @} */ - -/*! @name MONRXDAT - Monitor receiver data register. */ -/*! @{ */ -#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) -#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) -#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) -#define I2C_MONRXDAT_MONSTART_MASK (0x100U) -#define I2C_MONRXDAT_MONSTART_SHIFT (8U) -/*! MONSTART - Monitor Received Start. - * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. - * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) -#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) -#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) -/*! MONRESTART - Monitor Received Repeated Start. - * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. - * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) -#define I2C_MONRXDAT_MONNACK_MASK (0x400U) -#define I2C_MONRXDAT_MONNACK_SHIFT (10U) -/*! MONNACK - Monitor Received NACK. - * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. - * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. - */ -#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ -#define I2C_ID_APERTURE_MASK (0xFFU) -#define I2C_ID_APERTURE_SHIFT (0U) -#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) -#define I2C_ID_MINOR_REV_MASK (0xF00U) -#define I2C_ID_MINOR_REV_SHIFT (8U) -#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) -#define I2C_ID_MAJOR_REV_MASK (0xF000U) -#define I2C_ID_MAJOR_REV_SHIFT (12U) -#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) -#define I2C_ID_ID_MASK (0xFFFF0000U) -#define I2C_ID_ID_SHIFT (16U) -#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2C_Register_Masks */ - - -/* I2C - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral I2C0 base address */ - #define I2C0_BASE (0x50086000u) - /** Peripheral I2C0 base address */ - #define I2C0_BASE_NS (0x40086000u) - /** Peripheral I2C0 base pointer */ - #define I2C0 ((I2C_Type *)I2C0_BASE) - /** Peripheral I2C0 base pointer */ - #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) - /** Peripheral I2C1 base address */ - #define I2C1_BASE (0x50087000u) - /** Peripheral I2C1 base address */ - #define I2C1_BASE_NS (0x40087000u) - /** Peripheral I2C1 base pointer */ - #define I2C1 ((I2C_Type *)I2C1_BASE) - /** Peripheral I2C1 base pointer */ - #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) - /** Peripheral I2C2 base address */ - #define I2C2_BASE (0x50088000u) - /** Peripheral I2C2 base address */ - #define I2C2_BASE_NS (0x40088000u) - /** Peripheral I2C2 base pointer */ - #define I2C2 ((I2C_Type *)I2C2_BASE) - /** Peripheral I2C2 base pointer */ - #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) - /** Peripheral I2C3 base address */ - #define I2C3_BASE (0x50089000u) - /** Peripheral I2C3 base address */ - #define I2C3_BASE_NS (0x40089000u) - /** Peripheral I2C3 base pointer */ - #define I2C3 ((I2C_Type *)I2C3_BASE) - /** Peripheral I2C3 base pointer */ - #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) - /** Peripheral I2C4 base address */ - #define I2C4_BASE (0x5008A000u) - /** Peripheral I2C4 base address */ - #define I2C4_BASE_NS (0x4008A000u) - /** Peripheral I2C4 base pointer */ - #define I2C4 ((I2C_Type *)I2C4_BASE) - /** Peripheral I2C4 base pointer */ - #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) - /** Peripheral I2C5 base address */ - #define I2C5_BASE (0x50096000u) - /** Peripheral I2C5 base address */ - #define I2C5_BASE_NS (0x40096000u) - /** Peripheral I2C5 base pointer */ - #define I2C5 ((I2C_Type *)I2C5_BASE) - /** Peripheral I2C5 base pointer */ - #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) - /** Peripheral I2C6 base address */ - #define I2C6_BASE (0x50097000u) - /** Peripheral I2C6 base address */ - #define I2C6_BASE_NS (0x40097000u) - /** Peripheral I2C6 base pointer */ - #define I2C6 ((I2C_Type *)I2C6_BASE) - /** Peripheral I2C6 base pointer */ - #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) - /** Peripheral I2C7 base address */ - #define I2C7_BASE (0x50098000u) - /** Peripheral I2C7 base address */ - #define I2C7_BASE_NS (0x40098000u) - /** Peripheral I2C7 base pointer */ - #define I2C7 ((I2C_Type *)I2C7_BASE) - /** Peripheral I2C7 base pointer */ - #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } -#else - /** Peripheral I2C0 base address */ - #define I2C0_BASE (0x40086000u) - /** Peripheral I2C0 base pointer */ - #define I2C0 ((I2C_Type *)I2C0_BASE) - /** Peripheral I2C1 base address */ - #define I2C1_BASE (0x40087000u) - /** Peripheral I2C1 base pointer */ - #define I2C1 ((I2C_Type *)I2C1_BASE) - /** Peripheral I2C2 base address */ - #define I2C2_BASE (0x40088000u) - /** Peripheral I2C2 base pointer */ - #define I2C2 ((I2C_Type *)I2C2_BASE) - /** Peripheral I2C3 base address */ - #define I2C3_BASE (0x40089000u) - /** Peripheral I2C3 base pointer */ - #define I2C3 ((I2C_Type *)I2C3_BASE) - /** Peripheral I2C4 base address */ - #define I2C4_BASE (0x4008A000u) - /** Peripheral I2C4 base pointer */ - #define I2C4 ((I2C_Type *)I2C4_BASE) - /** Peripheral I2C5 base address */ - #define I2C5_BASE (0x40096000u) - /** Peripheral I2C5 base pointer */ - #define I2C5 ((I2C_Type *)I2C5_BASE) - /** Peripheral I2C6 base address */ - #define I2C6_BASE (0x40097000u) - /** Peripheral I2C6 base pointer */ - #define I2C6 ((I2C_Type *)I2C6_BASE) - /** Peripheral I2C7 base address */ - #define I2C7_BASE (0x40098000u) - /** Peripheral I2C7 base pointer */ - #define I2C7 ((I2C_Type *)I2C7_BASE) - /** Array initializer of I2C peripheral base addresses */ - #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } - /** Array initializer of I2C peripheral base pointers */ - #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } -#endif -/** Interrupt vectors for the I2C peripheral type */ -#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2S Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer - * @{ - */ - -/** I2S - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[3072]; - __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ - __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ - __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ - struct { /* offset: 0xC20, array step: 0x20 */ - __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0xC20, array step: 0x20 */ - __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0xC24, array step: 0x20 */ - __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0xC28, array step: 0x20 */ - uint8_t RESERVED_0[20]; - } SECCHANNEL[3]; - uint8_t RESERVED_2[384]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ - uint8_t RESERVED_5[8]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ - uint8_t RESERVED_6[8]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ - uint8_t RESERVED_7[436]; - __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ -} I2S_Type; - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ -/*! @{ */ -#define I2S_CFG1_MAINENABLE_MASK (0x1U) -#define I2S_CFG1_MAINENABLE_SHIFT (0U) -/*! MAINENABLE - Main enable for I 2S function in this Flexcomm - * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled. - * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. - */ -#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) -#define I2S_CFG1_DATAPAUSE_MASK (0x2U) -#define I2S_CFG1_DATAPAUSE_SHIFT (1U) -/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame. - * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. - * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. - */ -#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) -#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) -#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) -/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. - * 0b00..1 I2S channel pairs in this flexcomm - * 0b01..2 I2S channel pairs in this flexcomm - * 0b10..3 I2S channel pairs in this flexcomm - * 0b11..4 I2S channel pairs in this flexcomm - */ -#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) -#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) -#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) -/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. - * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. - * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock. - * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. - * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. - */ -#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) -#define I2S_CFG1_MODE_MASK (0xC0U) -#define I2S_CFG1_MODE_SHIFT (6U) -/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples. - * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. - * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. - * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. - * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. - */ -#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) -#define I2S_CFG1_RIGHTLOW_MASK (0x100U) -#define I2S_CFG1_RIGHTLOW_SHIFT (8U) -/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. - * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel. - * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel. - */ -#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) -#define I2S_CFG1_LEFTJUST_MASK (0x200U) -#define I2S_CFG1_LEFTJUST_SHIFT (9U) -/*! LEFTJUST - Left Justify data. - * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus. - * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus. - */ -#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) -#define I2S_CFG1_ONECHANNEL_MASK (0x400U) -#define I2S_CFG1_ONECHANNEL_SHIFT (10U) -/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers. - * 0b0..I2S data for this channel pair is treated as left and right channels. - * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION. - */ -#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) -#define I2S_CFG1_PDMDATA_MASK (0x800U) -#define I2S_CFG1_PDMDATA_SHIFT (11U) -/*! PDMDATA - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC55xx, this bit applies only to Flexcomm 6,7. - * 0b0..Normal operation, data is transferred to or from the Flexcomm FIFO. - * 0b1..The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun. - */ -#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK) -#define I2S_CFG1_SCK_POL_MASK (0x1000U) -#define I2S_CFG1_SCK_POL_SHIFT (12U) -/*! SCK_POL - SCK polarity. - * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). - * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. - */ -#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) -#define I2S_CFG1_WS_POL_MASK (0x2000U) -#define I2S_CFG1_WS_POL_SHIFT (13U) -/*! WS_POL - WS polarity. - * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). - * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). - */ -#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) -#define I2S_CFG1_DATALEN_MASK (0x1F0000U) -#define I2S_CFG1_DATALEN_SHIFT (16U) -#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) -/*! @} */ - -/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ -/*! @{ */ -#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) -#define I2S_CFG2_FRAMELEN_SHIFT (0U) -#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) -#define I2S_CFG2_POSITION_MASK (0x1FF0000U) -#define I2S_CFG2_POSITION_SHIFT (16U) -#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) -/*! @} */ - -/*! @name STAT - Status register for the primary channel pair. */ -/*! @{ */ -#define I2S_STAT_BUSY_MASK (0x1U) -#define I2S_STAT_BUSY_SHIFT (0U) -/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. - * 0b0..The transmitter/receiver for channel pair is currently idle. - * 0b1..The transmitter/receiver for channel pair is currently processing data. - */ -#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) -#define I2S_STAT_SLVFRMERR_MASK (0x2U) -#define I2S_STAT_SLVFRMERR_SHIFT (1U) -/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream. - * 0b0..No error has been recorded. - * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. - */ -#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) -#define I2S_STAT_LR_MASK (0x4U) -#define I2S_STAT_LR_SHIFT (2U) -/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair. - * 0b0..Left channel. - * 0b1..Right channel. - */ -#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) -#define I2S_STAT_DATAPAUSED_MASK (0x8U) -#define I2S_STAT_DATAPAUSED_SHIFT (3U) -/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels - * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. - * 0b1..A data pause has been requested and is now in force. - */ -#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) -/*! @} */ - -/*! @name DIV - Clock divider, used by all channel pairs. */ -/*! @{ */ -#define I2S_DIV_DIV_MASK (0xFFFU) -#define I2S_DIV_DIV_SHIFT (0U) -#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) -/*! @} */ - -/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */ -/*! @{ */ -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U) -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U) -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PCFG1 */ -#define I2S_SECCHANNEL_PCFG1_COUNT (3U) - -/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */ -/*! @{ */ -#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U) -#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U) -#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PCFG2 */ -#define I2S_SECCHANNEL_PCFG2_COUNT (3U) - -/*! @name SECCHANNEL_PSTAT - Status register for channel pair */ -/*! @{ */ -#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U) -#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U) -#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK) -#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U) -#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U) -#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PSTAT */ -#define I2S_SECCHANNEL_PSTAT_COUNT (3U) - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ -#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) -#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) -#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) -#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused. - * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 bits or less, or when MONO = 1 for this channel pair. - * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. - */ -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. - * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. - * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. - */ -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) -#define I2S_FIFOCFG_SIZE_MASK (0x30U) -#define I2S_FIFOCFG_SIZE_SHIFT (4U) -#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) -#define I2S_FIFOCFG_DMATX_MASK (0x1000U) -#define I2S_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) -#define I2S_FIFOCFG_DMARX_MASK (0x2000U) -#define I2S_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) -#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) -#define I2S_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) -#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) -#define I2S_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) -#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) -#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) -#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) -#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) -#define I2S_FIFOCFG_POPDBG_MASK (0x40000U) -#define I2S_FIFOCFG_POPDBG_SHIFT (18U) -/*! POPDBG - Pop FIFO for debug reads. - * 0b0..Debug reads of the FIFO do not pop the FIFO. - * 0b1..A debug read will cause the FIFO to pop. - */ -#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ -#define I2S_FIFOSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOSTAT_TXERR_SHIFT (0U) -#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) -#define I2S_FIFOSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOSTAT_RXERR_SHIFT (1U) -#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) -#define I2S_FIFOSTAT_PERINT_MASK (0x8U) -#define I2S_FIFOSTAT_PERINT_SHIFT (3U) -#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) -#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) -#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) -#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) -#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) -#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) -#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) -#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) -#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) -#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) -#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ -#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) -#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) -#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) -#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) -#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) -#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) -#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ -#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) -#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) -#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) -#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) -#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - */ -#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) -#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ -#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) -#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) -#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) -#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) -#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) -#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) -#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) -#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ -#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) -#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) -#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) -#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) -#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) -#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) -#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) -#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) -#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ -#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFOWR_TXDATA_SHIFT (0U) -#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ -#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) -#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) -#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ -#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORD_RXDATA_SHIFT (0U) -#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ -#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48H_RXDATA_SHIFT (0U) -#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ -#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ -#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) -#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name ID - I2S Module identification */ -/*! @{ */ -#define I2S_ID_Aperture_MASK (0xFFU) -#define I2S_ID_Aperture_SHIFT (0U) -#define I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK) -#define I2S_ID_Minor_Rev_MASK (0xF00U) -#define I2S_ID_Minor_Rev_SHIFT (8U) -#define I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK) -#define I2S_ID_Major_Rev_MASK (0xF000U) -#define I2S_ID_Major_Rev_SHIFT (12U) -#define I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK) -#define I2S_ID_ID_MASK (0xFFFF0000U) -#define I2S_ID_ID_SHIFT (16U) -#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2S_Register_Masks */ - - -/* I2S - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral I2S0 base address */ - #define I2S0_BASE (0x50086000u) - /** Peripheral I2S0 base address */ - #define I2S0_BASE_NS (0x40086000u) - /** Peripheral I2S0 base pointer */ - #define I2S0 ((I2S_Type *)I2S0_BASE) - /** Peripheral I2S0 base pointer */ - #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) - /** Peripheral I2S1 base address */ - #define I2S1_BASE (0x50087000u) - /** Peripheral I2S1 base address */ - #define I2S1_BASE_NS (0x40087000u) - /** Peripheral I2S1 base pointer */ - #define I2S1 ((I2S_Type *)I2S1_BASE) - /** Peripheral I2S1 base pointer */ - #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) - /** Peripheral I2S2 base address */ - #define I2S2_BASE (0x50088000u) - /** Peripheral I2S2 base address */ - #define I2S2_BASE_NS (0x40088000u) - /** Peripheral I2S2 base pointer */ - #define I2S2 ((I2S_Type *)I2S2_BASE) - /** Peripheral I2S2 base pointer */ - #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) - /** Peripheral I2S3 base address */ - #define I2S3_BASE (0x50089000u) - /** Peripheral I2S3 base address */ - #define I2S3_BASE_NS (0x40089000u) - /** Peripheral I2S3 base pointer */ - #define I2S3 ((I2S_Type *)I2S3_BASE) - /** Peripheral I2S3 base pointer */ - #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) - /** Peripheral I2S4 base address */ - #define I2S4_BASE (0x5008A000u) - /** Peripheral I2S4 base address */ - #define I2S4_BASE_NS (0x4008A000u) - /** Peripheral I2S4 base pointer */ - #define I2S4 ((I2S_Type *)I2S4_BASE) - /** Peripheral I2S4 base pointer */ - #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) - /** Peripheral I2S5 base address */ - #define I2S5_BASE (0x50096000u) - /** Peripheral I2S5 base address */ - #define I2S5_BASE_NS (0x40096000u) - /** Peripheral I2S5 base pointer */ - #define I2S5 ((I2S_Type *)I2S5_BASE) - /** Peripheral I2S5 base pointer */ - #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) - /** Peripheral I2S6 base address */ - #define I2S6_BASE (0x50097000u) - /** Peripheral I2S6 base address */ - #define I2S6_BASE_NS (0x40097000u) - /** Peripheral I2S6 base pointer */ - #define I2S6 ((I2S_Type *)I2S6_BASE) - /** Peripheral I2S6 base pointer */ - #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) - /** Peripheral I2S7 base address */ - #define I2S7_BASE (0x50098000u) - /** Peripheral I2S7 base address */ - #define I2S7_BASE_NS (0x40098000u) - /** Peripheral I2S7 base pointer */ - #define I2S7 ((I2S_Type *)I2S7_BASE) - /** Peripheral I2S7 base pointer */ - #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } -#else - /** Peripheral I2S0 base address */ - #define I2S0_BASE (0x40086000u) - /** Peripheral I2S0 base pointer */ - #define I2S0 ((I2S_Type *)I2S0_BASE) - /** Peripheral I2S1 base address */ - #define I2S1_BASE (0x40087000u) - /** Peripheral I2S1 base pointer */ - #define I2S1 ((I2S_Type *)I2S1_BASE) - /** Peripheral I2S2 base address */ - #define I2S2_BASE (0x40088000u) - /** Peripheral I2S2 base pointer */ - #define I2S2 ((I2S_Type *)I2S2_BASE) - /** Peripheral I2S3 base address */ - #define I2S3_BASE (0x40089000u) - /** Peripheral I2S3 base pointer */ - #define I2S3 ((I2S_Type *)I2S3_BASE) - /** Peripheral I2S4 base address */ - #define I2S4_BASE (0x4008A000u) - /** Peripheral I2S4 base pointer */ - #define I2S4 ((I2S_Type *)I2S4_BASE) - /** Peripheral I2S5 base address */ - #define I2S5_BASE (0x40096000u) - /** Peripheral I2S5 base pointer */ - #define I2S5 ((I2S_Type *)I2S5_BASE) - /** Peripheral I2S6 base address */ - #define I2S6_BASE (0x40097000u) - /** Peripheral I2S6 base pointer */ - #define I2S6 ((I2S_Type *)I2S6_BASE) - /** Peripheral I2S7 base address */ - #define I2S7_BASE (0x40098000u) - /** Peripheral I2S7 base pointer */ - #define I2S7 ((I2S_Type *)I2S7_BASE) - /** Array initializer of I2S peripheral base addresses */ - #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } - /** Array initializer of I2S peripheral base pointers */ - #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } -#endif -/** Interrupt vectors for the I2S peripheral type */ -#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2S_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer - * @{ - */ - -/** INPUTMUX - Register Layout Typedef */ -typedef struct { - __IO uint32_t SCT0_INMUX[7]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t TIMER0CAPTSEL[4]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[16]; - __IO uint32_t TIMER1CAPTSEL[4]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_2[16]; - __IO uint32_t TIMER2CAPTSEL[4]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */ - uint8_t RESERVED_3[80]; - __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ - __IO uint32_t DMA0_ITRIG_INMUX[23]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_4[36]; - __IO uint32_t DMA0_OTRIG_INMUX[4]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */ - uint8_t RESERVED_5[16]; - __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ - __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ - uint8_t RESERVED_6[24]; - __IO uint32_t TIMER3CAPTSEL[4]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */ - uint8_t RESERVED_7[16]; - __IO uint32_t TIMER4CAPTSEL[4]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */ - uint8_t RESERVED_8[16]; - __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */ - uint8_t RESERVED_9[24]; - __IO uint32_t DMA1_ITRIG_INMUX[10]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_10[24]; - __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_11[1264]; - __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */ - uint8_t RESERVED_12[4]; - __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */ - uint8_t RESERVED_13[4]; - __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */ - uint8_t RESERVED_14[12]; - __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */ - uint8_t RESERVED_15[4]; - __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */ - uint8_t RESERVED_16[4]; - __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */ - uint8_t RESERVED_17[12]; - __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */ - uint8_t RESERVED_18[4]; - __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */ - uint8_t RESERVED_19[4]; - __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */ - uint8_t RESERVED_20[12]; - __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */ - uint8_t RESERVED_21[4]; - __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */ - uint8_t RESERVED_22[4]; - __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */ -} INPUTMUX_Type; - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks - * @{ - */ - -/*! @name SCT0_INMUX - Input mux register for SCT0 input */ -/*! @{ */ -#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) -#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) -/*! INP_N - Input number to SCT0 inputs 0 to 6.. - * 0b00000..SCT_GPI0 function selected from IOCON register - * 0b00001..SCT_GPI1 function selected from IOCON register - * 0b00010..SCT_GPI2 function selected from IOCON register - * 0b00011..SCT_GPI3 function selected from IOCON register - * 0b00100..SCT_GPI4 function selected from IOCON register - * 0b00101..SCT_GPI5 function selected from IOCON register - * 0b00110..SCT_GPI6 function selected from IOCON register - * 0b00111..SCT_GPI7 function selected from IOCON register - * 0b01000..T0_OUT0 ctimer 0 match[0] output - * 0b01001..T1_OUT0 ctimer 1 match[0] output - * 0b01010..T2_OUT0 ctimer 2 match[0] output - * 0b01011..T3_OUT0 ctimer 3 match[0] output - * 0b01100..T4_OUT0 ctimer 4 match[0] output - * 0b01101..ADC_IRQ interrupt request from ADC - * 0b01110..GPIOINT_BMATCH - * 0b01111..USB0_FRAME_TOGGLE - * 0b10000..USB1_FRAME_TOGGLE - * 0b10001..COMP_OUTPUT output from analog comparator - * 0b10010..I2S_SHARED_SCK[0] output from I2S pin sharing - * 0b10011..I2S_SHARED_SCK[1] output from I2S pin sharing - * 0b10100..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b10101..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b10110..ARM_TXEV interrupt event from cpu0 or cpu1 - * 0b10111..DEBUG_HALTED from cpu0 or cpu1 - * 0b11000-0b11111..None - */ -#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) -/*! @} */ - -/* The count of INPUTMUX_SCT0_INMUX */ -#define INPUTMUX_SCT0_INMUX_COUNT (7U) - -/*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */ -/*! @{ */ -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER0CAPTSEL */ -#define INPUTMUX_TIMER0CAPTSEL_COUNT (4U) - -/*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */ -/*! @{ */ -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER1CAPTSEL */ -#define INPUTMUX_TIMER1CAPTSEL_COUNT (4U) - -/*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */ -/*! @{ */ -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER2CAPTSEL */ -#define INPUTMUX_TIMER2CAPTSEL_COUNT (4U) - -/*! @name PINTSEL - Pin interrupt select register */ -/*! @{ */ -#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) -#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) -#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSEL */ -#define INPUTMUX_PINTSEL_COUNT (8U) - -/*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */ -/*! @{ */ -#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) -/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). - * 0b00000..Pin interrupt 0 - * 0b00001..Pin interrupt 1 - * 0b00010..Pin interrupt 2 - * 0b00011..Pin interrupt 3 - * 0b00100..Timer CTIMER0 Match 0 - * 0b00101..Timer CTIMER0 Match 1 - * 0b00110..Timer CTIMER1 Match 0 - * 0b00111..Timer CTIMER1 Match 1 - * 0b01000..Timer CTIMER2 Match 0 - * 0b01001..Timer CTIMER2 Match 1 - * 0b01010..Timer CTIMER3 Match 0 - * 0b01011..Timer CTIMER3 Match 1 - * 0b01100..Timer CTIMER4 Match 0 - * 0b01101..Timer CTIMER4 Match 1 - * 0b01110..COMP_OUTPUT - * 0b01111..DMA0 output trigger mux 0 - * 0b10000..DMA0 output trigger mux 1 - * 0b10001..DMA0 output trigger mux 1 - * 0b10010..DMA0 output trigger mux 3 - * 0b10011..SCT0 DMA request 0 - * 0b10100..SCT0 DMA request 1 - * 0b10101..HASH DMA RX trigger - * 0b10110-0b11111..None - */ -#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA0_ITRIG_INMUX */ -#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (23U) - -/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */ -/*! @{ */ -#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) -#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA0_OTRIG_INMUX */ -#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (4U) - -/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ -/*! @{ */ -#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) -#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) -/*! @} */ - -/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ -/*! @{ */ -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) -#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) -/*! @} */ - -/*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */ -/*! @{ */ -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER3CAPTSEL */ -#define INPUTMUX_TIMER3CAPTSEL_COUNT (4U) - -/*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */ -/*! @{ */ -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU) -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U) -/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 - * 0b00000..CT_INP0 function selected from IOCON register - * 0b00001..CT_INP1 function selected from IOCON register - * 0b00010..CT_INP2 function selected from IOCON register - * 0b00011..CT_INP3 function selected from IOCON register - * 0b00100..CT_INP4 function selected from IOCON register - * 0b00101..CT_INP5 function selected from IOCON register - * 0b00110..CT_INP6 function selected from IOCON register - * 0b00111..CT_INP7 function selected from IOCON register - * 0b01000..CT_INP8 function selected from IOCON register - * 0b01001..CT_INP9 function selected from IOCON register - * 0b01010..CT_INP10 function selected from IOCON register - * 0b01011..CT_INP11 function selected from IOCON register - * 0b01100..CT_INP12 function selected from IOCON register - * 0b01101..CT_INP13 function selected from IOCON register - * 0b01110..CT_INP14 function selected from IOCON register - * 0b01111..CT_INP15 function selected from IOCON register - * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register - * 0b10100..USB0_FRAME_TOGGLE - * 0b10101..USB1_FRAME_TOGGLE - * 0b10110..COMP_OUTPUT output from analog comparator - * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing - * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing - * 0b11001-0b11111..None - */ -#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK) -/*! @} */ - -/* The count of INPUTMUX_TIMER4CAPTSEL */ -#define INPUTMUX_TIMER4CAPTSEL_COUNT (4U) - -/*! @name PINTSECSEL - Pin interrupt secure select register */ -/*! @{ */ -#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) -#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) -#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSECSEL */ -#define INPUTMUX_PINTSECSEL_COUNT (2U) - -/*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */ -/*! @{ */ -#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU) -#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) -/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). - * 0b0000..Pin interrupt 0 - * 0b0001..Pin interrupt 1 - * 0b0010..Pin interrupt 2 - * 0b0011..Pin interrupt 3 - * 0b0100..Timer CTIMER0 Match 0 - * 0b0101..Timer CTIMER0 Match 1 - * 0b0110..Timer CTIMER2 Match 0 - * 0b0111..Timer CTIMER4 Match 0 - * 0b1000..DMA1 output trigger mux 0 - * 0b1001..DMA1 output trigger mux 1 - * 0b1010..DMA1 output trigger mux 2 - * 0b1011..DMA1 output trigger mux 3 - * 0b1100..SCT0 DMA request 0 - * 0b1101..SCT0 DMA request 1 - * 0b1110..HASH DMA RX trigger - * 0b1111..None - */ -#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA1_ITRIG_INMUX */ -#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (10U) - -/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */ -/*! @{ */ -#define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU) -#define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U) -#define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA1_OTRIG_INMUX */ -#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U) - -/*! @name DMA0_REQ_ENA - Enable DMA0 requests */ -/*! @{ */ -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U) -#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK) -/*! @} */ - -/*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */ -/*! @{ */ -#define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U) -#define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */ -/*! @{ */ -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU) -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U) -#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA - Enable DMA1 requests */ -/*! @{ */ -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U) -#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */ -/*! @{ */ -#define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U) -#define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */ -/*! @{ */ -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU) -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U) -#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */ -/*! @{ */ -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) -#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */ -/*! @{ */ -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U) -#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */ -/*! @{ */ -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU) -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U) -#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */ -/*! @{ */ -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) -#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */ -/*! @{ */ -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U) -#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK) -/*! @} */ - -/*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */ -/*! @{ */ -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU) -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U) -#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group INPUTMUX_Register_Masks */ - - -/* INPUTMUX - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE (0x50006000u) - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE_NS (0x40006000u) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS { INPUTMUX } - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } -#else - /** Peripheral INPUTMUX base address */ - #define INPUTMUX_BASE (0x40006000u) - /** Peripheral INPUTMUX base pointer */ - #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) - /** Array initializer of INPUTMUX peripheral base addresses */ - #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } - /** Array initializer of INPUTMUX peripheral base pointers */ - #define INPUTMUX_BASE_PTRS { INPUTMUX } -#endif - -/*! - * @} - */ /* end of group INPUTMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- IOCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer - * @{ - */ - -/** IOCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ -} IOCON_Type; - -/* ---------------------------------------------------------------------------- - -- IOCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Register_Masks IOCON Register Masks - * @{ - */ - -/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ -/*! @{ */ -#define IOCON_PIO_FUNC_MASK (0xFU) -#define IOCON_PIO_FUNC_SHIFT (0U) -/*! FUNC - Selects pin function. - * 0b0000..Alternative connection 0. - * 0b0001..Alternative connection 1. - * 0b0010..Alternative connection 2. - * 0b0011..Alternative connection 3. - * 0b0100..Alternative connection 4. - * 0b0101..Alternative connection 5. - * 0b0110..Alternative connection 6. - * 0b0111..Alternative connection 7. - */ -#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) -#define IOCON_PIO_MODE_MASK (0x30U) -#define IOCON_PIO_MODE_SHIFT (4U) -/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) -#define IOCON_PIO_SLEW_MASK (0x40U) -#define IOCON_PIO_SLEW_SHIFT (6U) -/*! SLEW - Driver slew rate. - * 0b0..Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. - * 0b1..Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. - */ -#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) -#define IOCON_PIO_INVERT_MASK (0x80U) -#define IOCON_PIO_INVERT_SHIFT (7U) -/*! INVERT - Input polarity. - * 0b0..Disabled. Input function is not inverted. - * 0b1..Enabled. Input is function inverted. - */ -#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) -#define IOCON_PIO_DIGIMODE_MASK (0x100U) -#define IOCON_PIO_DIGIMODE_SHIFT (8U) -/*! DIGIMODE - Select Digital mode. - * 0b0..Analog mode, digital input is disabled. - * 0b1..Digital mode, digital input is enabled. - */ -#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) -#define IOCON_PIO_OD_MASK (0x200U) -#define IOCON_PIO_OD_SHIFT (9U) -/*! OD - Controls open-drain mode. - * 0b0..Normal. Normal push-pull output - * 0b1..Open-drain. Simulated open-drain output (high drive disabled). - */ -#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) -#define IOCON_PIO_ASW_MASK (0x400U) -#define IOCON_PIO_ASW_SHIFT (10U) -/*! ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 - * 0b0..Analog switch is open. - * 0b1..Analog switch is closed. - */ -#define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK) -#define IOCON_PIO_SSEL_MASK (0x800U) -#define IOCON_PIO_SSEL_SHIFT (11U) -/*! SSEL - Supply Selection bit. - * 0b0..3V3 Signaling in I2C Mode. - * 0b1..1V8 Signaling in I2C Mode. - */ -#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) -#define IOCON_PIO_FILTEROFF_MASK (0x1000U) -#define IOCON_PIO_FILTEROFF_SHIFT (12U) -/*! FILTEROFF - Controls input glitch filter. - * 0b0..Filter enabled. Noise pulses below approximately 10 ns are filtered out. - * 0b1..Filter disabled. No input filtering is done. - */ -#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) -#define IOCON_PIO_ECS_MASK (0x2000U) -#define IOCON_PIO_ECS_SHIFT (13U) -/*! ECS - Pull-up current source enable in IIC mode. - * 0b1..Enabled. Pull resistor is conencted. - * 0b0..Disabled. IO is in open drain. - */ -#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) -#define IOCON_PIO_EGP_MASK (0x4000U) -#define IOCON_PIO_EGP_SHIFT (14U) -/*! EGP - Controls slew rate of I2C pad. - * 0b0..I2C mode. - * 0b1..GPIO mode. - */ -#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) -#define IOCON_PIO_I2CFILTER_MASK (0x8000U) -#define IOCON_PIO_I2CFILTER_SHIFT (15U) -/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. - * 0b0..I2C 50 ns glitch filter enabled. Typically used for Fast-mode and Fast-mode Plus I2C. - * 0b1..I2C 10 ns glitch filter enabled. Typically used for Standard-mode I2C. - */ -#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) -/*! @} */ - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT (2U) - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT2 (32U) - - -/*! - * @} - */ /* end of group IOCON_Register_Masks */ - - -/* IOCON - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral IOCON base address */ - #define IOCON_BASE (0x50001000u) - /** Peripheral IOCON base address */ - #define IOCON_BASE_NS (0x40001000u) - /** Peripheral IOCON base pointer */ - #define IOCON ((IOCON_Type *)IOCON_BASE) - /** Peripheral IOCON base pointer */ - #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS { IOCON_BASE } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS { IOCON } - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS_NS { IOCON_NS } -#else - /** Peripheral IOCON base address */ - #define IOCON_BASE (0x40001000u) - /** Peripheral IOCON base pointer */ - #define IOCON ((IOCON_Type *)IOCON_BASE) - /** Array initializer of IOCON peripheral base addresses */ - #define IOCON_BASE_ADDRS { IOCON_BASE } - /** Array initializer of IOCON peripheral base pointers */ - #define IOCON_BASE_PTRS { IOCON } -#endif - -/*! - * @} - */ /* end of group IOCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MAILBOX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer - * @{ - */ - -/** MAILBOX - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */ - __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */ - __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } MBOXIRQ[2]; - uint8_t RESERVED_0[216]; - __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */ -} MAILBOX_Type; - -/* ---------------------------------------------------------------------------- - -- MAILBOX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks - * @{ - */ - -/*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ -/*! @{ */ -#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) -#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQ */ -#define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) - -/*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ -/*! @{ */ -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) -#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQSET */ -#define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) - -/*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ -/*! @{ */ -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) -#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) -/*! @} */ - -/* The count of MAILBOX_MBOXIRQ_IRQCLR */ -#define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) - -/*! @name MUTEX - Mutual exclusion register[1] */ -/*! @{ */ -#define MAILBOX_MUTEX_EX_MASK (0x1U) -#define MAILBOX_MUTEX_EX_SHIFT (0U) -#define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MAILBOX_Register_Masks */ - - -/* MAILBOX - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral MAILBOX base address */ - #define MAILBOX_BASE (0x5008B000u) - /** Peripheral MAILBOX base address */ - #define MAILBOX_BASE_NS (0x4008B000u) - /** Peripheral MAILBOX base pointer */ - #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) - /** Peripheral MAILBOX base pointer */ - #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) - /** Array initializer of MAILBOX peripheral base addresses */ - #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } - /** Array initializer of MAILBOX peripheral base pointers */ - #define MAILBOX_BASE_PTRS { MAILBOX } - /** Array initializer of MAILBOX peripheral base addresses */ - #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } - /** Array initializer of MAILBOX peripheral base pointers */ - #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } -#else - /** Peripheral MAILBOX base address */ - #define MAILBOX_BASE (0x4008B000u) - /** Peripheral MAILBOX base pointer */ - #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) - /** Array initializer of MAILBOX peripheral base addresses */ - #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } - /** Array initializer of MAILBOX peripheral base pointers */ - #define MAILBOX_BASE_PTRS { MAILBOX } -#endif -/** Interrupt vectors for the MAILBOX peripheral type */ -#define MAILBOX_IRQS { MAILBOX_IRQn } - -/*! - * @} - */ /* end of group MAILBOX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MRT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer - * @{ - */ - -/** MRT - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ - __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ - __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ - __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ - } CHANNEL[4]; - uint8_t RESERVED_0[176]; - __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ - __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ - __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ -} MRT_Type; - -/* ---------------------------------------------------------------------------- - -- MRT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Register_Masks MRT Register Masks - * @{ - */ - -/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ -/*! @{ */ -#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) -#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) -#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) -#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) -/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. - * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. - * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. - */ -#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_INTVAL */ -#define MRT_CHANNEL_INTVAL_COUNT (4U) - -/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ -/*! @{ */ -#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) -#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_TIMER */ -#define MRT_CHANNEL_TIMER_COUNT (4U) - -/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ -/*! @{ */ -#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) -#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) -/*! INTEN - Enable the TIMERn interrupt. - * 0b0..Disabled. TIMERn interrupt is disabled. - * 0b1..Enabled. TIMERn interrupt is enabled. - */ -#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) -#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) -#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) -/*! MODE - Selects timer mode. - * 0b00..Repeat interrupt mode. - * 0b01..One-shot interrupt mode. - * 0b10..One-shot stall mode. - * 0b11..Reserved. - */ -#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_CTRL */ -#define MRT_CHANNEL_CTRL_COUNT (4U) - -/*! @name CHANNEL_STAT - MRT Status register. */ -/*! @{ */ -#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) -#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) -/*! INTFLAG - Monitors the interrupt flag. - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. - */ -#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) -#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) -#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) -/*! RUN - Indicates the state of TIMERn. This bit is read-only. - * 0b0..Idle state. TIMERn is stopped. - * 0b1..Running. TIMERn is running. - */ -#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) -#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) -#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) -/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes. - * 0b0..This channel is not in use. - * 0b1..This channel is in use. - */ -#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_STAT */ -#define MRT_CHANNEL_STAT_COUNT (4U) - -/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ -/*! @{ */ -#define MRT_MODCFG_NOC_MASK (0xFU) -#define MRT_MODCFG_NOC_SHIFT (0U) -#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) -#define MRT_MODCFG_NOB_MASK (0x1F0U) -#define MRT_MODCFG_NOB_SHIFT (4U) -#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) -#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) -#define MRT_MODCFG_MULTITASK_SHIFT (31U) -/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. - * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. - * 0b1..Multi-task mode. - */ -#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) -/*! @} */ - -/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ -/*! @{ */ -#define MRT_IDLE_CH_CHAN_MASK (0xF0U) -#define MRT_IDLE_CH_CHAN_SHIFT (4U) -#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) -/*! @} */ - -/*! @name IRQ_FLAG - Global interrupt flag register */ -/*! @{ */ -#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) -#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) -/*! GFLAG0 - Monitors the interrupt flag of TIMER0. - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. - */ -#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) -#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) -#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) -#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) -#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) -#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) -#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) -#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) -#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) -#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MRT_Register_Masks */ - - -/* MRT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral MRT0 base address */ - #define MRT0_BASE (0x5000D000u) - /** Peripheral MRT0 base address */ - #define MRT0_BASE_NS (0x4000D000u) - /** Peripheral MRT0 base pointer */ - #define MRT0 ((MRT_Type *)MRT0_BASE) - /** Peripheral MRT0 base pointer */ - #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS { MRT0_BASE } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS { MRT0 } - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS_NS { MRT0_NS } -#else - /** Peripheral MRT0 base address */ - #define MRT0_BASE (0x4000D000u) - /** Peripheral MRT0 base pointer */ - #define MRT0 ((MRT_Type *)MRT0_BASE) - /** Array initializer of MRT peripheral base addresses */ - #define MRT_BASE_ADDRS { MRT0_BASE } - /** Array initializer of MRT peripheral base pointers */ - #define MRT_BASE_PTRS { MRT0 } -#endif -/** Interrupt vectors for the MRT peripheral type */ -#define MRT_IRQS { MRT0_IRQn } - -/*! - * @} - */ /* end of group MRT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- OSTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer - * @{ - */ - -/** OSTIMER - Register Layout Typedef */ -typedef struct { - __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ - __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ - __I uint32_t CAPTUREN_L; /**< Local Capture Low Register for CPUn, offset: 0x8 */ - __I uint32_t CAPTUREN_H; /**< Local Capture High Register for CPUn, offset: 0xC */ - __IO uint32_t MATCHN_L; /**< Local Match Low Register for CPUn, offset: 0x10 */ - __IO uint32_t MATCHN_H; /**< Match High Register for CPUn, offset: 0x14 */ - uint8_t RESERVED_0[4]; - __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register for CPUn, offset: 0x1C */ -} OSTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- OSTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks - * @{ - */ - -/*! @name EVTIMERL - EVTIMER Low Register */ -/*! @{ */ -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) -#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) -/*! @} */ - -/*! @name EVTIMERH - EVTIMER High Register */ -/*! @{ */ -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) -/*! @} */ - -/*! @name CAPTUREN_L - Local Capture Low Register for CPUn */ -/*! @{ */ -#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT (0U) -#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK) -/*! @} */ - -/*! @name CAPTUREN_H - Local Capture High Register for CPUn */ -/*! @{ */ -#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT (0U) -#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK) -/*! @} */ - -/*! @name MATCHN_L - Local Match Low Register for CPUn */ -/*! @{ */ -#define OSTIMER_MATCHN_L_MATCHn_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT (0U) -#define OSTIMER_MATCHN_L_MATCHn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_L_MATCHn_VALUE_MASK) -/*! @} */ - -/*! @name MATCHN_H - Match High Register for CPUn */ -/*! @{ */ -#define OSTIMER_MATCHN_H_MATCHn_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT (0U) -#define OSTIMER_MATCHN_H_MATCHn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_H_MATCHn_VALUE_MASK) -/*! @} */ - -/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register for CPUn */ -/*! @{ */ -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) -#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group OSTIMER_Register_Masks */ - - -/* OSTIMER - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE (0x5002D000u) - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE_NS (0x4002D000u) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS) - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS { OSTIMER } - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS } -#else - /** Peripheral OSTIMER base address */ - #define OSTIMER_BASE (0x4002D000u) - /** Peripheral OSTIMER base pointer */ - #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) - /** Array initializer of OSTIMER peripheral base addresses */ - #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } - /** Array initializer of OSTIMER peripheral base pointers */ - #define OSTIMER_BASE_PTRS { OSTIMER } -#endif -/** Interrupt vectors for the OSTIMER peripheral type */ -#define OSTIMER_IRQS { OS_EVENT_IRQn } - -/*! - * @} - */ /* end of group OSTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer - * @{ - */ - -/** PINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ - __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ - __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ - __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ - __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ - __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ - __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ - __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ - __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ - __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ - __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ - __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ - __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ -} PINT_Type; - -/* ---------------------------------------------------------------------------- - -- PINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Register_Masks PINT Register Masks - * @{ - */ - -/*! @name ISEL - Pin Interrupt Mode register */ -/*! @{ */ -#define PINT_ISEL_PMODE_MASK (0xFFU) -#define PINT_ISEL_PMODE_SHIFT (0U) -#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) -/*! @} */ - -/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ -/*! @{ */ -#define PINT_IENR_ENRL_MASK (0xFFU) -#define PINT_IENR_ENRL_SHIFT (0U) -#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) -/*! @} */ - -/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ -/*! @{ */ -#define PINT_SIENR_SETENRL_MASK (0xFFU) -#define PINT_SIENR_SETENRL_SHIFT (0U) -#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) -/*! @} */ - -/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ -/*! @{ */ -#define PINT_CIENR_CENRL_MASK (0xFFU) -#define PINT_CIENR_CENRL_SHIFT (0U) -#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) -/*! @} */ - -/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ -/*! @{ */ -#define PINT_IENF_ENAF_MASK (0xFFU) -#define PINT_IENF_ENAF_SHIFT (0U) -#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) -/*! @} */ - -/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ -/*! @{ */ -#define PINT_SIENF_SETENAF_MASK (0xFFU) -#define PINT_SIENF_SETENAF_SHIFT (0U) -#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) -/*! @} */ - -/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ -/*! @{ */ -#define PINT_CIENF_CENAF_MASK (0xFFU) -#define PINT_CIENF_CENAF_SHIFT (0U) -#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) -/*! @} */ - -/*! @name RISE - Pin interrupt rising edge register */ -/*! @{ */ -#define PINT_RISE_RDET_MASK (0xFFU) -#define PINT_RISE_RDET_SHIFT (0U) -#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) -/*! @} */ - -/*! @name FALL - Pin interrupt falling edge register */ -/*! @{ */ -#define PINT_FALL_FDET_MASK (0xFFU) -#define PINT_FALL_FDET_SHIFT (0U) -#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) -/*! @} */ - -/*! @name IST - Pin interrupt status register */ -/*! @{ */ -#define PINT_IST_PSTAT_MASK (0xFFU) -#define PINT_IST_PSTAT_SHIFT (0U) -#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) -/*! @} */ - -/*! @name PMCTRL - Pattern match interrupt control register */ -/*! @{ */ -#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) -#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) -/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. - * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. - * 0b1..Pattern match. Interrupts are driven in response to pattern matches. - */ -#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) -#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) -#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) -/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. - * 0b0..Disabled. RXEV output to the CPU is disabled. - * 0b1..Enabled. RXEV output to the CPU is enabled. - */ -#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) -#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) -#define PINT_PMCTRL_PMAT_SHIFT (24U) -#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) -/*! @} */ - -/*! @name PMSRC - Pattern match interrupt bit-slice source register */ -/*! @{ */ -#define PINT_PMSRC_SRC0_MASK (0x700U) -#define PINT_PMSRC_SRC0_SHIFT (8U) -/*! SRC0 - Selects the input source for bit slice 0 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. - */ -#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) -#define PINT_PMSRC_SRC1_MASK (0x3800U) -#define PINT_PMSRC_SRC1_SHIFT (11U) -/*! SRC1 - Selects the input source for bit slice 1 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. - */ -#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) -#define PINT_PMSRC_SRC2_MASK (0x1C000U) -#define PINT_PMSRC_SRC2_SHIFT (14U) -/*! SRC2 - Selects the input source for bit slice 2 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. - */ -#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) -#define PINT_PMSRC_SRC3_MASK (0xE0000U) -#define PINT_PMSRC_SRC3_SHIFT (17U) -/*! SRC3 - Selects the input source for bit slice 3 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. - */ -#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) -#define PINT_PMSRC_SRC4_MASK (0x700000U) -#define PINT_PMSRC_SRC4_SHIFT (20U) -/*! SRC4 - Selects the input source for bit slice 4 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. - */ -#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) -#define PINT_PMSRC_SRC5_MASK (0x3800000U) -#define PINT_PMSRC_SRC5_SHIFT (23U) -/*! SRC5 - Selects the input source for bit slice 5 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. - */ -#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) -#define PINT_PMSRC_SRC6_MASK (0x1C000000U) -#define PINT_PMSRC_SRC6_SHIFT (26U) -/*! SRC6 - Selects the input source for bit slice 6 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. - */ -#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) -#define PINT_PMSRC_SRC7_MASK (0xE0000000U) -#define PINT_PMSRC_SRC7_SHIFT (29U) -/*! SRC7 - Selects the input source for bit slice 7 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. - */ -#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) -/*! @} */ - -/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ -/*! @{ */ -#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) -#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) -/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. - * 0b0..No effect. Slice 0 is not an endpoint. - * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) -#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) -#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) -/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. - * 0b0..No effect. Slice 1 is not an endpoint. - * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) -#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) -#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) -/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. - * 0b0..No effect. Slice 2 is not an endpoint. - * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) -#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) -#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) -/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. - * 0b0..No effect. Slice 3 is not an endpoint. - * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) -#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) -#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) -/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. - * 0b0..No effect. Slice 4 is not an endpoint. - * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) -#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) -#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) -/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. - * 0b0..No effect. Slice 5 is not an endpoint. - * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) -#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) -#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) -/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. - * 0b0..No effect. Slice 6 is not an endpoint. - * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) -#define PINT_PMCFG_CFG0_MASK (0x700U) -#define PINT_PMCFG_CFG0_SHIFT (8U) -/*! CFG0 - Specifies the match contribution condition for bit slice 0. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) -#define PINT_PMCFG_CFG1_MASK (0x3800U) -#define PINT_PMCFG_CFG1_SHIFT (11U) -/*! CFG1 - Specifies the match contribution condition for bit slice 1. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) -#define PINT_PMCFG_CFG2_MASK (0x1C000U) -#define PINT_PMCFG_CFG2_SHIFT (14U) -/*! CFG2 - Specifies the match contribution condition for bit slice 2. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) -#define PINT_PMCFG_CFG3_MASK (0xE0000U) -#define PINT_PMCFG_CFG3_SHIFT (17U) -/*! CFG3 - Specifies the match contribution condition for bit slice 3. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) -#define PINT_PMCFG_CFG4_MASK (0x700000U) -#define PINT_PMCFG_CFG4_SHIFT (20U) -/*! CFG4 - Specifies the match contribution condition for bit slice 4. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) -#define PINT_PMCFG_CFG5_MASK (0x3800000U) -#define PINT_PMCFG_CFG5_SHIFT (23U) -/*! CFG5 - Specifies the match contribution condition for bit slice 5. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) -#define PINT_PMCFG_CFG6_MASK (0x1C000000U) -#define PINT_PMCFG_CFG6_SHIFT (26U) -/*! CFG6 - Specifies the match contribution condition for bit slice 6. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) -#define PINT_PMCFG_CFG7_MASK (0xE0000000U) -#define PINT_PMCFG_CFG7_SHIFT (29U) -/*! CFG7 - Specifies the match contribution condition for bit slice 7. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PINT_Register_Masks */ - - -/* PINT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral PINT base address */ - #define PINT_BASE (0x50004000u) - /** Peripheral PINT base address */ - #define PINT_BASE_NS (0x40004000u) - /** Peripheral PINT base pointer */ - #define PINT ((PINT_Type *)PINT_BASE) - /** Peripheral PINT base pointer */ - #define PINT_NS ((PINT_Type *)PINT_BASE_NS) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE (0x50005000u) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE_NS (0x40005000u) - /** Peripheral SECPINT base pointer */ - #define SECPINT ((PINT_Type *)SECPINT_BASE) - /** Peripheral SECPINT base pointer */ - #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS { PINT, SECPINT } - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } -#else - /** Peripheral PINT base address */ - #define PINT_BASE (0x40004000u) - /** Peripheral PINT base pointer */ - #define PINT ((PINT_Type *)PINT_BASE) - /** Peripheral SECPINT base address */ - #define SECPINT_BASE (0x40005000u) - /** Peripheral SECPINT base pointer */ - #define SECPINT ((PINT_Type *)SECPINT_BASE) - /** Array initializer of PINT peripheral base addresses */ - #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } - /** Array initializer of PINT peripheral base pointers */ - #define PINT_BASE_PTRS { PINT, SECPINT } -#endif -/** Interrupt vectors for the PINT peripheral type */ -#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } - -/*! - * @} - */ /* end of group PINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PLU Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer - * @{ - */ - -/** PLU - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x20 */ - __IO uint32_t INP[5]; /**< LUT0 input 0 MUX..LUT25 input 4 MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ - uint8_t RESERVED_0[12]; - } LUT[26]; - uint8_t RESERVED_0[1216]; - __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ - uint8_t RESERVED_1[152]; - __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ - __IO uint32_t WAKEINT; /**< Wakeup interrupt control for PLU, offset: 0x904 */ - uint8_t RESERVED_2[760]; - __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ -} PLU_Type; - -/* ---------------------------------------------------------------------------- - -- PLU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PLU_Register_Masks PLU Register Masks - * @{ - */ - -/*! @name LUT_INP - LUT0 input 0 MUX..LUT25 input 4 MUX */ -/*! @{ */ -#define PLU_LUT_INP_LUT_INP_MASK (0x3FU) -#define PLU_LUT_INP_LUT_INP_SHIFT (0U) -/*! LUT_INP - Selects the input source to be connected to LUT25 input4. - * 0b000000..The PLU primary inputs 0. - * 0b000001..The PLU primary inputs 1. - * 0b000010..The PLU primary inputs 2. - * 0b000011..The PLU primary inputs 3. - * 0b000100..The PLU primary inputs 4. - * 0b000101..The PLU primary inputs 5. - * 0b000110..Tie low. - * 0b000111..The output of LUT1. - * 0b001000..The output of LUT2. - * 0b001001..The output of LUT3. - * 0b001010..The output of LUT4. - * 0b001011..The output of LUT5. - * 0b001100..The output of LUT6. - * 0b001101..The output of LUT7. - * 0b001110..The output of LUT8. - * 0b001111..The output of LUT9. - * 0b010000..The output of LUT10. - * 0b010001..The output of LUT11. - * 0b010010..The output of LUT12. - * 0b010011..The output of LUT13. - * 0b010100..The output of LUT14. - * 0b010101..The output of LUT15. - * 0b010110..The output of LUT16. - * 0b010111..The output of LUT17. - * 0b011000..The output of LUT18. - * 0b011001..The output of LUT19. - * 0b011010..The output of LUT20. - * 0b011011..The output of LUT21. - * 0b011100..The output of LUT22. - * 0b011101..The output of LUT23. - * 0b011110..The output of LUT24. - * 0b011111..The output of LUT25. - * 0b100000..state(0). - * 0b100001..state(1). - * 0b100010..state(2). - * 0b100011..state(3). - */ -#define PLU_LUT_INP_LUT_INP(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_LUT_INP_SHIFT)) & PLU_LUT_INP_LUT_INP_MASK) -/*! @} */ - -/* The count of PLU_LUT_INP */ -#define PLU_LUT_INP_COUNT (26U) - -/* The count of PLU_LUT_INP */ -#define PLU_LUT_INP_COUNT2 (5U) - -/*! @name LUT_T_LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ -/*! @{ */ -#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_MASK (0xFFFFFFFFU) -#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_SHIFT (0U) -#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_SHIFT)) & PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_MASK) -/*! @} */ - -/* The count of PLU_LUT_T_LUT_TRUTH */ -#define PLU_LUT_T_LUT_TRUTH_COUNT (26U) - -/*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ -/*! @{ */ -#define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) -#define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) -#define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) -/*! @} */ - -/*! @name WAKEINT - Wakeup interrupt control for PLU */ -/*! @{ */ -#define PLU_WAKEINT_MASK_MASK (0xFFU) -#define PLU_WAKEINT_MASK_SHIFT (0U) -#define PLU_WAKEINT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_MASK_SHIFT)) & PLU_WAKEINT_MASK_MASK) -#define PLU_WAKEINT_FILTER_MODE_MASK (0x300U) -#define PLU_WAKEINT_FILTER_MODE_SHIFT (8U) -/*! FILTER_MODE - control input of the PLU, add filtering for glitch - * 0b00..Bypass mode. - * 0b01..Filter 1 clock period. - * 0b10..Filter 2 clock period. - * 0b11..Filter 3 clock period. - */ -#define PLU_WAKEINT_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_FILTER_MODE_SHIFT)) & PLU_WAKEINT_FILTER_MODE_MASK) -#define PLU_WAKEINT_FILTER_CLKSEL_MASK (0xC00U) -#define PLU_WAKEINT_FILTER_CLKSEL_SHIFT (10U) -#define PLU_WAKEINT_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_FILTER_CLKSEL_MASK) -#define PLU_WAKEINT_LATCH_ENABLE_MASK (0x1000U) -#define PLU_WAKEINT_LATCH_ENABLE_SHIFT (12U) -#define PLU_WAKEINT_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_LATCH_ENABLE_MASK) -#define PLU_WAKEINT_INTR_CLEAR_MASK (0x2000U) -#define PLU_WAKEINT_INTR_CLEAR_SHIFT (13U) -#define PLU_WAKEINT_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_INTR_CLEAR_MASK) -/*! @} */ - -/*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ -/*! @{ */ -#define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) -#define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) -/*! OUTPUTn - Selects the source to be connected to PLU Output 7. - * 0b00000..The PLU output 0. - * 0b00001..The PLU output 1. - * 0b00010..The PLU output 2. - * 0b00011..The PLU output 3. - * 0b00100..The PLU output 4. - * 0b00101..The PLU output 5. - * 0b00110..The PLU output 6. - * 0b00111..The PLU output 7. - * 0b01000..The PLU output 8. - * 0b01001..The PLU output 9. - * 0b01010..The PLU output 10. - * 0b01011..The PLU output 11. - * 0b01100..The PLU output 12. - * 0b01101..The PLU output 13. - * 0b01110..The PLU output 14. - * 0b01111..The PLU output 15. - * 0b10000..The PLU output 16. - * 0b10001..The PLU output 17. - * 0b10010..The PLU output 18. - * 0b10011..The PLU output 19. - * 0b10100..The PLU output 20. - * 0b10101..The PLU output 21. - * 0b10110..The PLU output 22. - * 0b10111..The PLU output 23. - * 0b11000..The PLU output 24. - * 0b11001..The PLU output 25. - * 0b11010..state(0). - * 0b11011..state(1). - * 0b11100..state(2). - * 0b11101..state(3). - */ -#define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK) -/*! @} */ - -/* The count of PLU_OUTPUT_MUX */ -#define PLU_OUTPUT_MUX_COUNT (8U) - - -/*! - * @} - */ /* end of group PLU_Register_Masks */ - - -/* PLU - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral PLU base address */ - #define PLU_BASE (0x5003D000u) - /** Peripheral PLU base address */ - #define PLU_BASE_NS (0x4003D000u) - /** Peripheral PLU base pointer */ - #define PLU ((PLU_Type *)PLU_BASE) - /** Peripheral PLU base pointer */ - #define PLU_NS ((PLU_Type *)PLU_BASE_NS) - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS { PLU_BASE } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS { PLU } - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS_NS { PLU_BASE_NS } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS_NS { PLU_NS } -#else - /** Peripheral PLU base address */ - #define PLU_BASE (0x4003D000u) - /** Peripheral PLU base pointer */ - #define PLU ((PLU_Type *)PLU_BASE) - /** Array initializer of PLU peripheral base addresses */ - #define PLU_BASE_ADDRS { PLU_BASE } - /** Array initializer of PLU peripheral base pointers */ - #define PLU_BASE_PTRS { PLU } -#endif - -/*! - * @} - */ /* end of group PLU_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer - * @{ - */ - -/** PMC - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[8]; - __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */ - __IO uint32_t RESETCAUSE; /**< Reset Cause register [Reset by: PoR], offset: 0xC */ - uint8_t RESERVED_1[32]; - __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ - uint8_t RESERVED_2[4]; - __IO uint32_t BODCORE; /**< Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x38 */ - uint8_t RESERVED_3[8]; - __IO uint32_t FRO1M; /**< 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x44 */ - __IO uint32_t FRO32K; /**< 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x48 */ - __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */ - __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */ - uint8_t RESERVED_4[20]; - __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */ - uint8_t RESERVED_5[8]; - __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */ - uint8_t RESERVED_6[12]; - __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */ - uint8_t RESERVED_7[16]; - __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */ - __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */ - uint8_t RESERVED_8[16]; - __IO uint32_t PDSLEEPCFG0; /**< Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xB0 */ - uint8_t RESERVED_9[4]; - __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */ - uint8_t RESERVED_10[4]; - __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */ - uint8_t RESERVED_11[4]; - __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */ -} PMC_Type; - -/* ---------------------------------------------------------------------------- - -- PMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Register_Masks PMC Register Masks - * @{ - */ - -/*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) -/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). - * 0b0..Reset event from DEEP POWER DOWN mode is disable. - * 0b1..Reset event from DEEP POWER DOWN mode is enable. - */ -#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) -#define PMC_RESETCTRL_BODVBATRESETENABLE_MASK (0x2U) -#define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT (1U) -/*! BODVBATRESETENABLE - BOD VBAT reset enable. - * 0b0..BOD VBAT reset is disable. - * 0b1..BOD VBAT reset is enable. - */ -#define PMC_RESETCTRL_BODVBATRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK) -#define PMC_RESETCTRL_BODCORERESETENABLE_MASK (0x4U) -#define PMC_RESETCTRL_BODCORERESETENABLE_SHIFT (2U) -/*! BODCORERESETENABLE - BOD CORE reset enable. - * 0b0..BOD CORE reset is disable. - * 0b1..BOD CORE reset is enable. - */ -#define PMC_RESETCTRL_BODCORERESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENABLE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENABLE_MASK) -#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) -#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) -/*! SWRRESETENABLE - Software reset enable. - * 0b0..Software reset is disable. - * 0b1..Software reset is enable. - */ -#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) -/*! @} */ - -/*! @name RESETCAUSE - Reset Cause register [Reset by: PoR] */ -/*! @{ */ -#define PMC_RESETCAUSE_POR_MASK (0x1U) -#define PMC_RESETCAUSE_POR_SHIFT (0U) -#define PMC_RESETCAUSE_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_POR_SHIFT)) & PMC_RESETCAUSE_POR_MASK) -#define PMC_RESETCAUSE_PADRESET_MASK (0x2U) -#define PMC_RESETCAUSE_PADRESET_SHIFT (1U) -#define PMC_RESETCAUSE_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_PADRESET_SHIFT)) & PMC_RESETCAUSE_PADRESET_MASK) -#define PMC_RESETCAUSE_BODRESET_MASK (0x4U) -#define PMC_RESETCAUSE_BODRESET_SHIFT (2U) -#define PMC_RESETCAUSE_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_BODRESET_SHIFT)) & PMC_RESETCAUSE_BODRESET_MASK) -#define PMC_RESETCAUSE_SYSTEMRESET_MASK (0x8U) -#define PMC_RESETCAUSE_SYSTEMRESET_SHIFT (3U) -#define PMC_RESETCAUSE_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SYSTEMRESET_SHIFT)) & PMC_RESETCAUSE_SYSTEMRESET_MASK) -#define PMC_RESETCAUSE_WDTRESET_MASK (0x10U) -#define PMC_RESETCAUSE_WDTRESET_SHIFT (4U) -#define PMC_RESETCAUSE_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_WDTRESET_SHIFT)) & PMC_RESETCAUSE_WDTRESET_MASK) -#define PMC_RESETCAUSE_SWRRESET_MASK (0x20U) -#define PMC_RESETCAUSE_SWRRESET_SHIFT (5U) -#define PMC_RESETCAUSE_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SWRRESET_SHIFT)) & PMC_RESETCAUSE_SWRRESET_MASK) -#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK (0x40U) -#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT (6U) -#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT)) & PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK) -#define PMC_RESETCAUSE_DPDRESET_RTC_MASK (0x80U) -#define PMC_RESETCAUSE_DPDRESET_RTC_SHIFT (7U) -#define PMC_RESETCAUSE_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_RTC_SHIFT)) & PMC_RESETCAUSE_DPDRESET_RTC_MASK) -#define PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK (0x100U) -#define PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT (8U) -#define PMC_RESETCAUSE_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT)) & PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK) -/*! @} */ - -/*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */ -/*! @{ */ -#define PMC_BODVBAT_TRIGLVL_MASK (0x1FU) -#define PMC_BODVBAT_TRIGLVL_SHIFT (0U) -/*! TRIGLVL - BoD trigger level. - * 0b00000..1.00 V. - * 0b00001..1.10 V. - * 0b00010..1.20 V. - * 0b00011..1.30 V. - * 0b00100..1.40 V. - * 0b00101..1.50 V. - * 0b00110..1.60 V. - * 0b00111..1.65 V. - * 0b01000..1.70 V. - * 0b01001..1.75 V. - * 0b01010..1.80 V. - * 0b01011..1.90 V. - * 0b01100..2.00 V. - * 0b01101..2.10 V. - * 0b01110..2.20 V. - * 0b01111..2.30 V. - * 0b10000..2.40 V. - * 0b10001..2.50 V. - * 0b10010..2.60 V. - * 0b10011..2.70 V. - * 0b10100..2.806 V. - * 0b10101..2.90 V. - * 0b10110..3.00 V. - * 0b10111..3.10 V. - * 0b11000..3.20 V. - * 0b11001..3.30 V. - * 0b11010..3.30 V. - * 0b11011..3.30 V. - * 0b11100..3.30 V. - * 0b11101..3.30 V. - * 0b11110..3.30 V. - * 0b11111..3.30 V. - */ -#define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK) -#define PMC_BODVBAT_HYST_MASK (0x60U) -#define PMC_BODVBAT_HYST_SHIFT (5U) -/*! HYST - BoD Hysteresis control. - * 0b00..25 mV. - * 0b01..50 mV. - * 0b10..75 mV. - * 0b11..100 mV. - */ -#define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK) -/*! @} */ - -/*! @name BODCORE - Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ -#define PMC_BODCORE_TRIGLVL_MASK (0x7U) -#define PMC_BODCORE_TRIGLVL_SHIFT (0U) -/*! TRIGLVL - BoD trigger level. - * 0b000..0.60 V. - * 0b001..0.65 V. - * 0b010..0.70 V. - * 0b011..0.75 V. - * 0b100..0.80 V. - * 0b101..0.85 V. - * 0b110..0.90 V. - * 0b111..0.95 V. - */ -#define PMC_BODCORE_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_TRIGLVL_SHIFT)) & PMC_BODCORE_TRIGLVL_MASK) -#define PMC_BODCORE_HYST_MASK (0x30U) -#define PMC_BODCORE_HYST_SHIFT (4U) -/*! HYST - BoD Core Hysteresis control. - * 0b00..25 mV. - * 0b01..50 mV. - * 0b10..75 mV. - * 0b11..100 mV. - */ -#define PMC_BODCORE_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_HYST_SHIFT)) & PMC_BODCORE_HYST_MASK) -/*! @} */ - -/*! @name FRO1M - 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ -#define PMC_FRO1M_FREQSEL_MASK (0x7FU) -#define PMC_FRO1M_FREQSEL_SHIFT (0U) -#define PMC_FRO1M_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_FREQSEL_SHIFT)) & PMC_FRO1M_FREQSEL_MASK) -#define PMC_FRO1M_ATBCTRL_MASK (0x180U) -#define PMC_FRO1M_ATBCTRL_SHIFT (7U) -#define PMC_FRO1M_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_ATBCTRL_SHIFT)) & PMC_FRO1M_ATBCTRL_MASK) -#define PMC_FRO1M_DIVSEL_MASK (0x3E00U) -#define PMC_FRO1M_DIVSEL_SHIFT (9U) -/*! DIVSEL - Divider selection bits. - * 0b00000..2.0. - * 0b00001..4.0. - * 0b00010..6.0. - * 0b00011..8.0. - * 0b00100..10.0. - * 0b00101..12.0. - * 0b00110..14.0. - * 0b00111..16.0. - * 0b01000..18.0. - * 0b01001..20.0. - * 0b01010..22.0. - * 0b01011..24.0. - * 0b01100..26.0. - * 0b01101..28.0. - * 0b01110..30.0. - * 0b01111..32.0. - * 0b10000..34.0. - * 0b10001..36.0. - * 0b10010..38.0. - * 0b10011..40.0. - * 0b10100..42.0. - * 0b10101..44.0. - * 0b10110..46.0. - * 0b10111..48.0. - * 0b11000..50.0. - * 0b11001..52.0. - * 0b11010..54.0. - * 0b11011..56.0. - * 0b11100..58.0. - * 0b11101..60.0. - * 0b11110..62.0. - * 0b11111..1.0. - */ -#define PMC_FRO1M_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_DIVSEL_SHIFT)) & PMC_FRO1M_DIVSEL_MASK) -/*! @} */ - -/*! @name FRO32K - 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ -#define PMC_FRO32K_NTAT_MASK (0xEU) -#define PMC_FRO32K_NTAT_SHIFT (1U) -#define PMC_FRO32K_NTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_NTAT_SHIFT)) & PMC_FRO32K_NTAT_MASK) -#define PMC_FRO32K_PTAT_MASK (0x70U) -#define PMC_FRO32K_PTAT_SHIFT (4U) -#define PMC_FRO32K_PTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_PTAT_SHIFT)) & PMC_FRO32K_PTAT_MASK) -#define PMC_FRO32K_CAPCAL_MASK (0xFF80U) -#define PMC_FRO32K_CAPCAL_SHIFT (7U) -#define PMC_FRO32K_CAPCAL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_CAPCAL_SHIFT)) & PMC_FRO32K_CAPCAL_MASK) -#define PMC_FRO32K_ATBCTRL_MASK (0x30000U) -#define PMC_FRO32K_ATBCTRL_SHIFT (16U) -#define PMC_FRO32K_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_ATBCTRL_SHIFT)) & PMC_FRO32K_ATBCTRL_MASK) -/*! @} */ - -/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ -#define PMC_XTAL32K_IREF_MASK (0x6U) -#define PMC_XTAL32K_IREF_SHIFT (1U) -#define PMC_XTAL32K_IREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK) -#define PMC_XTAL32K_TEST_MASK (0x8U) -#define PMC_XTAL32K_TEST_SHIFT (3U) -#define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK) -#define PMC_XTAL32K_IBIAS_MASK (0x30U) -#define PMC_XTAL32K_IBIAS_SHIFT (4U) -#define PMC_XTAL32K_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK) -#define PMC_XTAL32K_AMPL_MASK (0xC0U) -#define PMC_XTAL32K_AMPL_SHIFT (6U) -#define PMC_XTAL32K_AMPL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK) -#define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U) -#define PMC_XTAL32K_CAPBANKIN_SHIFT (8U) -#define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK) -#define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U) -#define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U) -#define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK) -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK (0x400000U) -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT (22U) -/*! CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set. - * 0b0..Sourced from CAPTESTSTART. - * 0b1..Sourced from calibration. - */ -#define PMC_XTAL32K_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT)) & PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK) -#define PMC_XTAL32K_CAPTESTSTART_MASK (0x800000U) -#define PMC_XTAL32K_CAPTESTSTART_SHIFT (23U) -#define PMC_XTAL32K_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTART_SHIFT)) & PMC_XTAL32K_CAPTESTSTART_MASK) -#define PMC_XTAL32K_CAPTESTENABLE_MASK (0x1000000U) -#define PMC_XTAL32K_CAPTESTENABLE_SHIFT (24U) -#define PMC_XTAL32K_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTENABLE_SHIFT)) & PMC_XTAL32K_CAPTESTENABLE_MASK) -#define PMC_XTAL32K_CAPTESTOSCINSEL_MASK (0x2000000U) -#define PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT (25U) -/*! CAPTESTOSCINSEL - Select the input for test. - * 0b0..Oscillator output pin (osc_out). - * 0b1..Oscillator input pin (osc_in). - */ -#define PMC_XTAL32K_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT)) & PMC_XTAL32K_CAPTESTOSCINSEL_MASK) -/*! @} */ - -/*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ -#define PMC_COMP_HYST_MASK (0x2U) -#define PMC_COMP_HYST_SHIFT (1U) -/*! HYST - Hysteris when hyst = '1'. - * 0b0..Hysteresis is disable. - * 0b1..Hysteresis is enable. - */ -#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) -#define PMC_COMP_VREFINPUT_MASK (0x4U) -#define PMC_COMP_VREFINPUT_SHIFT (2U) -/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). - * 0b0..Select internal VREF. - * 0b1..Select VDDA. - */ -#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) -#define PMC_COMP_LOWPOWER_MASK (0x8U) -#define PMC_COMP_LOWPOWER_SHIFT (3U) -/*! LOWPOWER - Low power mode. - * 0b0..High speed mode. - * 0b1..Low power mode (Low speed). - */ -#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) -#define PMC_COMP_PMUX_MASK (0x70U) -#define PMC_COMP_PMUX_SHIFT (4U) -/*! PMUX - Control word for P multiplexer:. - * 0b000..VREF (See fiedl VREFINPUT). - * 0b001..Pin P0_0. - * 0b010..Pin P0_9. - * 0b011..Pin P0_18. - * 0b100..Pin P1_14. - * 0b101..Pin P2_23. - */ -#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) -#define PMC_COMP_NMUX_MASK (0x380U) -#define PMC_COMP_NMUX_SHIFT (7U) -/*! NMUX - Control word for N multiplexer:. - * 0b000..VREF (See field VREFINPUT). - * 0b001..Pin P0_0. - * 0b010..Pin P0_9. - * 0b011..Pin P0_18. - * 0b100..Pin P1_14. - * 0b101..Pin P2_23. - */ -#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) -#define PMC_COMP_VREF_MASK (0x7C00U) -#define PMC_COMP_VREF_SHIFT (10U) -#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) -#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) -#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) -#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) -#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) -#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) -#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) -#define PMC_COMP_PMUXCAPT_MASK (0xE00000U) -#define PMC_COMP_PMUXCAPT_SHIFT (21U) -#define PMC_COMP_PMUXCAPT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUXCAPT_SHIFT)) & PMC_COMP_PMUXCAPT_MASK) -/*! @} */ - -/*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */ -/*! @{ */ -#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) -#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) -/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. - */ -#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) -#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) -#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) -/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. - */ -#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) -#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) -#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) -/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. - */ -#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) -#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) -#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) -/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. - * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. - * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3. - */ -#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK) -/*! @} */ - -/*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ -#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) -#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) -#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) -#define PMC_STATUSCLK_FRO1MCLKVALID_MASK (0x2U) -#define PMC_STATUSCLK_FRO1MCLKVALID_SHIFT (1U) -#define PMC_STATUSCLK_FRO1MCLKVALID(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_FRO1MCLKVALID_SHIFT)) & PMC_STATUSCLK_FRO1MCLKVALID_MASK) -#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) -#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) -/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. - * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared.. - * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared.. - */ -#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) -/*! @} */ - -/*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ -#define PMC_AOREG1_DATA31_0_MASK (0xFFFFFFFFU) -#define PMC_AOREG1_DATA31_0_SHIFT (0U) -#define PMC_AOREG1_DATA31_0(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DATA31_0_SHIFT)) & PMC_AOREG1_DATA31_0_MASK) -/*! @} */ - -/*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ -#define PMC_RTCOSC32K_SEL_MASK (0x1U) -#define PMC_RTCOSC32K_SEL_SHIFT (0U) -/*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . - * 0b0..FRO 32 KHz. - * 0b1..XTAL 32KHz. - */ -#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) -#define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU) -#define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U) -#define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK) -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U) -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U) -#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK) -#define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U) -#define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U) -#define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK) -#define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U) -#define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U) -#define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK) -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U) -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U) -#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK) -/*! @} */ - -/*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ -#define PMC_OSTIMER_SOFTRESET_MASK (0x1U) -#define PMC_OSTIMER_SOFTRESET_SHIFT (0U) -#define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK) -#define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U) -#define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U) -#define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK) -#define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U) -#define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U) -#define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK) -#define PMC_OSTIMER_OSC32KPD_MASK (0x8U) -#define PMC_OSTIMER_OSC32KPD_SHIFT (3U) -#define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK) -/*! @} */ - -/*! @name PDSLEEPCFG0 - Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ -/*! @{ */ -#define PMC_PDSLEEPCFG0_PDEN_DCDC_MASK (0x1U) -#define PMC_PDSLEEPCFG0_PDEN_DCDC_SHIFT (0U) -/*! PDEN_DCDC - Controls DCDC power during DEEP SLEEP (DCDC is always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..DCDC is powered on during low power mode.. - * 0b1..DCDC is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_DCDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_DCDC_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_DCDC_MASK) -#define PMC_PDSLEEPCFG0_PDEN_BIAS_MASK (0x2U) -#define PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT (1U) -/*! PDEN_BIAS - Controls Analog Bias power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..Analog Bias is powered on during low power mode.. - * 0b1..Analog Bias is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BIAS_MASK) -#define PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK (0x4U) -#define PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT (2U) -/*! PDEN_BODCORE - Controls Core Logic BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..BOD CORE is powered on during low power mode.. - * 0b1..BOD CORE is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK) -#define PMC_PDSLEEPCFG0_PDEN_BODVBAT_MASK (0x8U) -#define PMC_PDSLEEPCFG0_PDEN_BODVBAT_SHIFT (3U) -/*! PDEN_BODVBAT - Controls VBAT BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..BOD VBAT is powered on during low power mode.. - * 0b1..BOD VBAT is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODVBAT_MASK) -#define PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK (0x10U) -#define PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT (4U) -/*! PDEN_FRO1M - Controls 1 MHz Free Running Oscillator power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - * 0b0..FRO 1MHz is powered on during low power mode.. - * 0b1..FRO 1MHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_FRO1M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK) -#define PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK (0x20U) -#define PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT (5U) -/*! PDEN_FRO192M - Controls 192MHz Free Running Oscillator power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..FRO 192 MHz is powered on during low power mode.. - * 0b1..FRO 192 MHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK) -#define PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK (0x40U) -#define PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT (6U) -/*! PDEN_FRO32K - Controls power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - * 0b0..FRO 32 KHz is powered on during low power mode.. - * 0b1..FRO 32 KHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK) -#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK (0x80U) -#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT (7U) -/*! PDEN_XTAL32K - Controls crystal 32 KHz power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - * 0b0..crystal 32 KHz is powered on during low power mode.. - * 0b1..crystal 32 KHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK) -#define PMC_PDSLEEPCFG0_PDEN_XTAL32M_MASK (0x100U) -#define PMC_PDSLEEPCFG0_PDEN_XTAL32M_SHIFT (8U) -/*! PDEN_XTAL32M - Controls crystal 32 MHz power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..crystal 32 MHz is powered on during low power mode.. - * 0b1..crystal 32 MHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTAL32M_MASK) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_MASK (0x200U) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT (9U) -/*! PDEN_PLL0 - Controls System PLL (also refered as PLL0) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..System PLL (also refered as PLL0) is powered on during low power mode.. - * 0b1..System PLL (also refered as PLL0) is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_MASK) -#define PMC_PDSLEEPCFG0_PDEN_PLL1_MASK (0x400U) -#define PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT (10U) -/*! PDEN_PLL1 - Controls USB PLL (also refered as PLL1) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..USB PLL (also refered as PLL1) is powered on during low power mode.. - * 0b1..USB PLL (also refered as PLL1) is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL1_MASK) -#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK (0x800U) -#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT (11U) -/*! PDEN_USBFSPHY - Controls USB Full Speed phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..USB Full Speed phy is powered on during low power mode.. - * 0b1..USB Full Speed phy is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK) -#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY_MASK (0x1000U) -#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY_SHIFT (12U) -/*! PDEN_USBHSPHY - Controls USB High Speed Phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..USB High Speed Phy is powered on during low power mode.. - * 0b1..USB High Speed Phy is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_USBHSPHY_MASK) -#define PMC_PDSLEEPCFG0_PDEN_COMP_MASK (0x2000U) -#define PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT (13U) -/*! PDEN_COMP - Controls Analog Comparator power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..Analog Comparator is powered on during low power mode.. - * 0b1..Analog Comparator is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_COMP_MASK) -#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS_MASK (0x4000U) -#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS_SHIFT (14U) -/*! PDEN_TEMPSENS - Controls Temperature Sensor power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..Temperature Sensor is powered on during low power mode.. - * 0b1..Temperature Sensor is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_TEMPSENS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_TEMPSENS_MASK) -#define PMC_PDSLEEPCFG0_PDEN_GPADC_MASK (0x8000U) -#define PMC_PDSLEEPCFG0_PDEN_GPADC_SHIFT (15U) -/*! PDEN_GPADC - Controls General Purpose ADC (GPADC) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..General Purpose ADC (GPADC) is powered on during low power mode.. - * 0b1..General Purpose ADC (GPADC) is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_GPADC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_GPADC_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_GPADC_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK (0x10000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT (16U) -/*! PDEN_LDOMEM - Controls Memories LDO power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - * 0b0..Memories LDO is powered on during low power mode.. - * 0b1..Memories LDO is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_MASK (0x20000U) -#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_SHIFT (17U) -/*! PDEN_LDODEEPSLEEP - Controls Deep Sleep LDO power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..Deep Sleep LDO is powered on during low power mode.. - * 0b1..Deep Sleep LDO is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_MASK (0x40000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_SHIFT (18U) -/*! PDEN_LDOUSBHS - Controls USB high speed LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..USB high speed LDO is powered on during low power mode.. - * 0b1..USB high speed LDO is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_MASK) -#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS_MASK (0x80000U) -#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS_SHIFT (19U) -/*! PDEN_AUXBIAS - during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..is powered on during low power mode.. - * 0b1..is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_AUXBIAS_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M_MASK (0x100000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M_SHIFT (20U) -/*! PDEN_LDOXO32M - Controls crystal 32 MHz LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..crystal 32 MHz LDO is powered on during low power mode.. - * 0b1..crystal 32 MHz LDO is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOXO32M_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK (0x200000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT (21U) -/*! PDEN_LDOFLASHNV - Controls Flash NV (high voltage) LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..Flash NV (high voltage) is powered on during low power mode.. - * 0b1..Flash NV (high voltage) is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK) -#define PMC_PDSLEEPCFG0_PDEN_RNG_MASK (0x400000U) -#define PMC_PDSLEEPCFG0_PDEN_RNG_SHIFT (22U) -/*! PDEN_RNG - Controls True Random Number Genetaor (TRNG) clock sources power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..True Random Number Genetaor (TRNG) clock sources are powered on during low power mode.. - * 0b1..True Random Number Genetaor (TRNG) clock sources are powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_RNG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_RNG_MASK) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT (23U) -/*! PDEN_PLL0_SSCG - Controls PLL0 Spread Sprectrum module power during DEEP SLEEP (PLL0 Spread Spectrum is always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..PLL0 Spread Sprectrum module is powered on during low power mode.. - * 0b1..PLL0 Spread Sprectrum module is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK) -#define PMC_PDSLEEPCFG0_PDEN_ROM_MASK (0x1000000U) -#define PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT (24U) -/*! PDEN_ROM - Controls ROM power during DEEP SLEEP (ROM is always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..ROM is powered on during low power mode.. - * 0b1..ROM is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_ROM_MASK) -/*! @} */ - -/*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ -#define PMC_PDRUNCFG0_PDEN_DCDC_MASK (0x1U) -#define PMC_PDRUNCFG0_PDEN_DCDC_SHIFT (0U) -/*! PDEN_DCDC - Controls power to Bulk DCDC Converter. - * 0b0..DCDC is powered. - * 0b1..DCDC is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_DCDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_DCDC_SHIFT)) & PMC_PDRUNCFG0_PDEN_DCDC_MASK) -#define PMC_PDRUNCFG0_PDEN_BIAS_MASK (0x2U) -#define PMC_PDRUNCFG0_PDEN_BIAS_SHIFT (1U) -/*! PDEN_BIAS - Controls power to . - * 0b0..Analog Bias is powered. - * 0b1..Analog Bias is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_BIAS_MASK) -#define PMC_PDRUNCFG0_PDEN_BODCORE_MASK (0x4U) -#define PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT (2U) -/*! PDEN_BODCORE - Controls power to Core Brown Out Detector (BOD). - * 0b0..BOD CORE is powered. - * 0b1..BOD CORE is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODCORE_MASK) -#define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U) -#define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U) -/*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). - * 0b0..BOD VBAT is powered. - * 0b1..BOD VBAT is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK) -#define PMC_PDRUNCFG0_PDEN_FRO192M_MASK (0x20U) -#define PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT (5U) -/*! PDEN_FRO192M - Controls power to the Free Running Oscillator (FRO) 192 MHz; The 12MHz, 48 MHz and 96 MHz clocks are derived from this FRO. - * 0b0..FRO 192MHz is powered. - * 0b1..FRO 192MHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) -#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) -#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) -/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. - * 0b0..FRO32KHz is powered. - * 0b1..FRO32KHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) -#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) -#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) -/*! PDEN_XTAL32K - Controls power to crystal 32 KHz. - * 0b0..Crystal 32KHz is powered. - * 0b1..Crystal 32KHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) -#define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U) -#define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U) -/*! PDEN_XTAL32M - Controls power to crystal 32 MHz. - * 0b0..Crystal 32MHz is powered. - * 0b1..Crystal 32MHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK) -#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) -#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) -/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). - * 0b0..PLL0 is powered. - * 0b1..PLL0 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) -#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) -#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) -/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). - * 0b0..PLL1 is powered. - * 0b1..PLL1 is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) -#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) -#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) -/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. - * 0b0..USB Full Speed phy is powered. - * 0b1..USB Full Speed phy is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) -#define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U) -#define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U) -/*! PDEN_USBHSPHY - Controls power to USB High Speed Phy. - * 0b0..USB HS phy is powered. - * 0b1..USB HS phy is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK) -#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) -#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) -/*! PDEN_COMP - Controls power to Analog Comparator. - * 0b0..Analog Comparator is powered. - * 0b1..Analog Comparator is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) -#define PMC_PDRUNCFG0_PDEN_TEMPSENS_MASK (0x4000U) -#define PMC_PDRUNCFG0_PDEN_TEMPSENS_SHIFT (14U) -/*! PDEN_TEMPSENS - Controls power to Temperature Sensor. - * 0b0..Temperature Sensor is powered. - * 0b1..Temperature Sensor is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_TEMPSENS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_TEMPSENS_SHIFT)) & PMC_PDRUNCFG0_PDEN_TEMPSENS_MASK) -#define PMC_PDRUNCFG0_PDEN_GPADC_MASK (0x8000U) -#define PMC_PDRUNCFG0_PDEN_GPADC_SHIFT (15U) -/*! PDEN_GPADC - Controls power to General Purpose ADC (GPADC). - * 0b0..GPADC is powered. - * 0b1..GPADC is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_GPADC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_GPADC_SHIFT)) & PMC_PDRUNCFG0_PDEN_GPADC_MASK) -#define PMC_PDRUNCFG0_PDEN_LDOMEM_MASK (0x10000U) -#define PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT (16U) -/*! PDEN_LDOMEM - Controls power to Memories LDO. - * 0b0..Memories LDO is powered. - * 0b1..Memories LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOMEM_MASK) -#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_MASK (0x20000U) -#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_SHIFT (17U) -/*! PDEN_LDODEEPSLEEP - Controls power to Deep Sleep LDO. - * 0b0..Deep Sleep LDO is powered. - * 0b1..Deep Sleep LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_MASK) -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U) -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U) -/*! PDEN_LDOUSBHS - Controls power to USB high speed LDO. - * 0b0..USB high speed LDO is powered. - * 0b1..USB high speed LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK) -#define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U) -#define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U) -/*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) - * 0b0..auxiliary biasing is powered. - * 0b1..auxiliary biasing is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK) -#define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U) -#define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U) -/*! PDEN_LDOXO32M - Controls power to crystal 32 MHz LDO. - * 0b0..crystal 32 MHz LDO is powered. - * 0b1..crystal 32 MHz LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK) -#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK (0x200000U) -#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT (21U) -/*! PDEN_LDOFLASHNV - Controls power to Flasn NV (high voltage) LDO. - * 0b0..Flash NV LDO is powered. - * 0b1..Flash NV LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK) -#define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U) -#define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U) -/*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. - * 0b0..TRNG clocks are powered. - * 0b1..TRNG clocks are powered down. - */ -#define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK) -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) -/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. - * 0b0..PLL0 Sread spectrum module is powered. - * 0b1..PLL0 Sread spectrum module is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) -/*! @} */ - -/*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) -#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) -/*! @} */ - -/*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) -#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PMC_Register_Masks */ - - -/* PMC - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral PMC base address */ - #define PMC_BASE (0x50020000u) - /** Peripheral PMC base address */ - #define PMC_BASE_NS (0x40020000u) - /** Peripheral PMC base pointer */ - #define PMC ((PMC_Type *)PMC_BASE) - /** Peripheral PMC base pointer */ - #define PMC_NS ((PMC_Type *)PMC_BASE_NS) - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS { PMC_BASE } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS { PMC } - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS_NS { PMC_NS } -#else - /** Peripheral PMC base address */ - #define PMC_BASE (0x40020000u) - /** Peripheral PMC base pointer */ - #define PMC ((PMC_Type *)PMC_BASE) - /** Array initializer of PMC peripheral base addresses */ - #define PMC_BASE_ADDRS { PMC_BASE } - /** Array initializer of PMC peripheral base pointers */ - #define PMC_BASE_PTRS { PMC } -#endif - -/*! - * @} - */ /* end of group PMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- POWERQUAD Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer - * @{ - */ - -/** POWERQUAD - Register Layout Typedef */ -typedef struct { - __IO uint32_t OUTBASE; /**< Base address register for output region, offset: 0x0 */ - __IO uint32_t OUTFORMAT; /**< Output format, offset: 0x4 */ - __IO uint32_t TMPBASE; /**< Base address register for temp region, offset: 0x8 */ - __IO uint32_t TMPFORMAT; /**< Temp format, offset: 0xC */ - __IO uint32_t INABASE; /**< Base address register for input A region, offset: 0x10 */ - __IO uint32_t INAFORMAT; /**< Input A format, offset: 0x14 */ - __IO uint32_t INBBASE; /**< Base address register for input B region, offset: 0x18 */ - __IO uint32_t INBFORMAT; /**< Input B format, offset: 0x1C */ - uint8_t RESERVED_0[224]; - __IO uint32_t CONTROL; /**< PowerQuad Control register, offset: 0x100 */ - __IO uint32_t LENGTH; /**< Length register, offset: 0x104 */ - __IO uint32_t CPPRE; /**< Pre-scale register, offset: 0x108 */ - __IO uint32_t MISC; /**< Misc register, offset: 0x10C */ - __IO uint32_t CURSORY; /**< Cursory register, offset: 0x110 */ - uint8_t RESERVED_1[108]; - __IO uint32_t CORDIC_X; /**< Cordic input X register, offset: 0x180 */ - __IO uint32_t CORDIC_Y; /**< Cordic input Y register, offset: 0x184 */ - __IO uint32_t CORDIC_Z; /**< Cordic input Z register, offset: 0x188 */ - __IO uint32_t ERRSTAT; /**< Read/Write register where error statuses are captured (sticky), offset: 0x18C */ - __IO uint32_t INTREN; /**< INTERRUPT enable register, offset: 0x190 */ - __IO uint32_t EVENTEN; /**< Event Enable register, offset: 0x194 */ - __IO uint32_t INTRSTAT; /**< INTERRUPT STATUS register, offset: 0x198 */ - uint8_t RESERVED_2[100]; - __IO uint32_t GPREG[16]; /**< General purpose register bank N., array offset: 0x200, array step: 0x4 */ - __IO uint32_t COMPREG[8]; /**< Compute register bank, array offset: 0x240, array step: 0x4 */ -} POWERQUAD_Type; - -/* ---------------------------------------------------------------------------- - -- POWERQUAD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks - * @{ - */ - -/*! @name OUTBASE - Base address register for output region */ -/*! @{ */ -#define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U) -#define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK) -/*! @} */ - -/*! @name OUTFORMAT - Output format */ -/*! @{ */ -#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U) -#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U) -#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK) -#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U) -#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U) -#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK) -#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U) -#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U) -#define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK) -/*! @} */ - -/*! @name TMPBASE - Base address register for temp region */ -/*! @{ */ -#define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U) -#define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK) -/*! @} */ - -/*! @name TMPFORMAT - Temp format */ -/*! @{ */ -#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U) -#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U) -#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK) -#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U) -#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U) -#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK) -#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U) -#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U) -#define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK) -/*! @} */ - -/*! @name INABASE - Base address register for input A region */ -/*! @{ */ -#define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_INABASE_INABASE_SHIFT (0U) -#define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK) -/*! @} */ - -/*! @name INAFORMAT - Input A format */ -/*! @{ */ -#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U) -#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U) -#define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK) -#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U) -#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U) -#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK) -#define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U) -#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U) -#define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK) -/*! @} */ - -/*! @name INBBASE - Base address register for input B region */ -/*! @{ */ -#define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU) -#define POWERQUAD_INBBASE_INBBASE_SHIFT (0U) -#define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK) -/*! @} */ - -/*! @name INBFORMAT - Input B format */ -/*! @{ */ -#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U) -#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U) -#define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK) -#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U) -#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U) -#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK) -#define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U) -#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U) -#define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK) -/*! @} */ - -/*! @name CONTROL - PowerQuad Control register */ -/*! @{ */ -#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU) -#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U) -#define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK) -#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U) -#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U) -#define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK) -#define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U) -#define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U) -#define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK) -/*! @} */ - -/*! @name LENGTH - Length register */ -/*! @{ */ -#define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU) -#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U) -#define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK) -/*! @} */ - -/*! @name CPPRE - Pre-scale register */ -/*! @{ */ -#define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU) -#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U) -#define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK) -#define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U) -#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U) -#define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK) -#define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U) -#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U) -#define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK) -#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U) -#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U) -#define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK) -/*! @} */ - -/*! @name MISC - Misc register */ -/*! @{ */ -#define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU) -#define POWERQUAD_MISC_INST_MISC_SHIFT (0U) -#define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK) -/*! @} */ - -/*! @name CURSORY - Cursory register */ -/*! @{ */ -#define POWERQUAD_CURSORY_CURSORY_MASK (0x1U) -#define POWERQUAD_CURSORY_CURSORY_SHIFT (0U) -#define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK) -/*! @} */ - -/*! @name CORDIC_X - Cordic input X register */ -/*! @{ */ -#define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU) -#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U) -#define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK) -/*! @} */ - -/*! @name CORDIC_Y - Cordic input Y register */ -/*! @{ */ -#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU) -#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U) -#define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK) -/*! @} */ - -/*! @name CORDIC_Z - Cordic input Z register */ -/*! @{ */ -#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU) -#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U) -#define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK) -/*! @} */ - -/*! @name ERRSTAT - Read/Write register where error statuses are captured (sticky) */ -/*! @{ */ -#define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U) -#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U) -#define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK) -#define POWERQUAD_ERRSTAT_NAN_MASK (0x2U) -#define POWERQUAD_ERRSTAT_NAN_SHIFT (1U) -#define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK) -#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U) -#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U) -#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK) -#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U) -#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U) -#define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK) -#define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U) -#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U) -#define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK) -/*! @} */ - -/*! @name INTREN - INTERRUPT enable register */ -/*! @{ */ -#define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U) -#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U) -#define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK) -#define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U) -#define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U) -#define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK) -#define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U) -#define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U) -#define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK) -#define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U) -#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U) -#define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK) -#define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U) -#define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U) -#define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK) -#define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U) -#define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U) -#define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK) -/*! @} */ - -/*! @name EVENTEN - Event Enable register */ -/*! @{ */ -#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U) -#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U) -#define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK) -#define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U) -#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U) -#define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK) -#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U) -#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U) -#define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK) -#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U) -#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U) -#define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK) -#define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U) -#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U) -#define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK) -#define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U) -#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U) -#define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK) -/*! @} */ - -/*! @name INTRSTAT - INTERRUPT STATUS register */ -/*! @{ */ -#define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U) -#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U) -#define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK) -/*! @} */ - -/*! @name GPREG - General purpose register bank N. */ -/*! @{ */ -#define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU) -#define POWERQUAD_GPREG_GPREG_SHIFT (0U) -#define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK) -/*! @} */ - -/* The count of POWERQUAD_GPREG */ -#define POWERQUAD_GPREG_COUNT (16U) - -/*! @name COMPREGS_COMPREG - Compute register bank */ -/*! @{ */ -#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU) -#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U) -#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK) -/*! @} */ - -/* The count of POWERQUAD_COMPREGS_COMPREG */ -#define POWERQUAD_COMPREGS_COMPREG_COUNT (8U) - - -/*! - * @} - */ /* end of group POWERQUAD_Register_Masks */ - - -/* POWERQUAD - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral POWERQUAD base address */ - #define POWERQUAD_BASE (0x500A6000u) - /** Peripheral POWERQUAD base address */ - #define POWERQUAD_BASE_NS (0x400A6000u) - /** Peripheral POWERQUAD base pointer */ - #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) - /** Peripheral POWERQUAD base pointer */ - #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) - /** Array initializer of POWERQUAD peripheral base addresses */ - #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } - /** Array initializer of POWERQUAD peripheral base pointers */ - #define POWERQUAD_BASE_PTRS { POWERQUAD } - /** Array initializer of POWERQUAD peripheral base addresses */ - #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } - /** Array initializer of POWERQUAD peripheral base pointers */ - #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } -#else - /** Peripheral POWERQUAD base address */ - #define POWERQUAD_BASE (0x400A6000u) - /** Peripheral POWERQUAD base pointer */ - #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) - /** Array initializer of POWERQUAD peripheral base addresses */ - #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } - /** Array initializer of POWERQUAD peripheral base pointers */ - #define POWERQUAD_BASE_PTRS { POWERQUAD } -#endif - -/*! - * @} - */ /* end of group POWERQUAD_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PRINCE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer - * @{ - */ - -/** PRINCE - Register Layout Typedef */ -typedef struct { - __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */ - __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */ - __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */ - __IO uint32_t LOCK; /**< Lock register, offset: 0xC */ - __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */ - __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */ - __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */ - __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */ - __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */ - __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */ - __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */ - __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */ - __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */ - __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */ - __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */ - __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */ -} PRINCE_Type; - -/* ---------------------------------------------------------------------------- - -- PRINCE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PRINCE_Register_Masks PRINCE Register Masks - * @{ - */ - -/*! @name ENC_ENABLE - Encryption Enable register */ -/*! @{ */ -#define PRINCE_ENC_ENABLE_EN_MASK (0x1U) -#define PRINCE_ENC_ENABLE_EN_SHIFT (0U) -/*! EN - Encryption Enable. - * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled.. - * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled.. - */ -#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) -/*! @} */ - -/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ -/*! @{ */ -#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) -#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) -#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) -/*! @} */ - -/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ -/*! @{ */ -#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) -#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) -#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) -/*! @} */ - -/*! @name LOCK - Lock register */ -/*! @{ */ -#define PRINCE_LOCK_LOCKREG0_MASK (0x1U) -#define PRINCE_LOCK_LOCKREG0_SHIFT (0U) -/*! LOCKREG0 - Lock Region 0 registers. - * 0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. - * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) -#define PRINCE_LOCK_LOCKREG1_MASK (0x2U) -#define PRINCE_LOCK_LOCKREG1_SHIFT (1U) -/*! LOCKREG1 - Lock Region 1 registers. - * 0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. - * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) -#define PRINCE_LOCK_LOCKREG2_MASK (0x4U) -#define PRINCE_LOCK_LOCKREG2_SHIFT (2U) -/*! LOCKREG2 - Lock Region 2 registers. - * 0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. - * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. - */ -#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) -#define PRINCE_LOCK_LOCKMASK_MASK (0x100U) -#define PRINCE_LOCK_LOCKMASK_SHIFT (8U) -/*! LOCKMASK - Lock the Mask registers. - * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable.. - * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable.. - */ -#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK) -/*! @} */ - -/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ -/*! @{ */ -#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) -#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ -/*! @{ */ -#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) -#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR0 - Base Address for region 0 register */ -/*! @{ */ -#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) -#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) -#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) -#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ -/*! @{ */ -#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE0_EN_SHIFT (0U) -#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) -/*! @} */ - -/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ -/*! @{ */ -#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) -#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ -/*! @{ */ -#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) -#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR1 - Base Address for region 1 register */ -/*! @{ */ -#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) -#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) -#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) -#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ -/*! @{ */ -#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE1_EN_SHIFT (0U) -#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) -/*! @} */ - -/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ -/*! @{ */ -#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) -#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) -/*! @} */ - -/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ -/*! @{ */ -#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) -#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) -#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) -/*! @} */ - -/*! @name BASE_ADDR2 - Base Address for region 2 register */ -/*! @{ */ -#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) -#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) -#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) -#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) -#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) -#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) -/*! @} */ - -/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ -/*! @{ */ -#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) -#define PRINCE_SR_ENABLE2_EN_SHIFT (0U) -#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PRINCE_Register_Masks */ - - -/* PRINCE - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral PRINCE base address */ - #define PRINCE_BASE (0x50035000u) - /** Peripheral PRINCE base address */ - #define PRINCE_BASE_NS (0x40035000u) - /** Peripheral PRINCE base pointer */ - #define PRINCE ((PRINCE_Type *)PRINCE_BASE) - /** Peripheral PRINCE base pointer */ - #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS) - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS { PRINCE_BASE } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS { PRINCE } - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS_NS { PRINCE_NS } -#else - /** Peripheral PRINCE base address */ - #define PRINCE_BASE (0x40035000u) - /** Peripheral PRINCE base pointer */ - #define PRINCE ((PRINCE_Type *)PRINCE_BASE) - /** Array initializer of PRINCE peripheral base addresses */ - #define PRINCE_BASE_ADDRS { PRINCE_BASE } - /** Array initializer of PRINCE peripheral base pointers */ - #define PRINCE_BASE_PTRS { PRINCE } -#endif - -/*! - * @} - */ /* end of group PRINCE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PUF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer - * @{ - */ - -/** PUF - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */ - __IO uint32_t KEYINDEX; /**< PUF Key Index register, offset: 0x4 */ - __IO uint32_t KEYSIZE; /**< PUF Key Size register, offset: 0x8 */ - uint8_t RESERVED_0[20]; - __I uint32_t STAT; /**< PUF Status register, offset: 0x20 */ - uint8_t RESERVED_1[4]; - __I uint32_t ALLOW; /**< PUF Allow register, offset: 0x28 */ - uint8_t RESERVED_2[20]; - __O uint32_t KEYINPUT; /**< PUF Key Input register, offset: 0x40 */ - __O uint32_t CODEINPUT; /**< PUF Code Input register, offset: 0x44 */ - __I uint32_t CODEOUTPUT; /**< PUF Code Output register, offset: 0x48 */ - uint8_t RESERVED_3[20]; - __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index register, offset: 0x60 */ - __I uint32_t KEYOUTPUT; /**< PUF Key Output register, offset: 0x64 */ - uint8_t RESERVED_4[116]; - __IO uint32_t IFSTAT; /**< PUF Interface Status and clear register, offset: 0xDC */ - uint8_t RESERVED_5[28]; - __I uint32_t VERSION; /**< PUF version register., offset: 0xFC */ - __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */ - __IO uint32_t INTSTAT; /**< PUF interrupt status, offset: 0x104 */ - __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ - __IO uint32_t CFG; /**< PUF config register for block bits, offset: 0x10C */ - uint8_t RESERVED_6[240]; - __IO uint32_t KEYLOCK; /**< Only reset in case of full IC reset, offset: 0x200 */ - __IO uint32_t KEYENABLE; /**< , offset: 0x204 */ - __O uint32_t KEYRESET; /**< Reinitialize Keys shift registers counters, offset: 0x208 */ - __IO uint32_t IDXBLK_L; /**< , offset: 0x20C */ - __IO uint32_t IDXBLK_H_DP; /**< , offset: 0x210 */ - __O uint32_t KEYMASK[4]; /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */ - uint8_t RESERVED_7[48]; - __IO uint32_t IDXBLK_H; /**< , offset: 0x254 */ - __IO uint32_t IDXBLK_L_DP; /**< , offset: 0x258 */ - __I uint32_t SHIFT_STATUS; /**< , offset: 0x25C */ -} PUF_Type; - -/* ---------------------------------------------------------------------------- - -- PUF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_Register_Masks PUF Register Masks - * @{ - */ - -/*! @name CTRL - PUF Control register */ -/*! @{ */ -#define PUF_CTRL_ZEROIZE_MASK (0x1U) -#define PUF_CTRL_ZEROIZE_SHIFT (0U) -#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) -#define PUF_CTRL_ENROLL_MASK (0x2U) -#define PUF_CTRL_ENROLL_SHIFT (1U) -#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) -#define PUF_CTRL_START_MASK (0x4U) -#define PUF_CTRL_START_SHIFT (2U) -#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) -#define PUF_CTRL_GENERATEKEY_MASK (0x8U) -#define PUF_CTRL_GENERATEKEY_SHIFT (3U) -#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) -#define PUF_CTRL_SETKEY_MASK (0x10U) -#define PUF_CTRL_SETKEY_SHIFT (4U) -#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) -#define PUF_CTRL_GETKEY_MASK (0x40U) -#define PUF_CTRL_GETKEY_SHIFT (6U) -#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) -/*! @} */ - -/*! @name KEYINDEX - PUF Key Index register */ -/*! @{ */ -#define PUF_KEYINDEX_KEYIDX_MASK (0xFU) -#define PUF_KEYINDEX_KEYIDX_SHIFT (0U) -#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) -/*! @} */ - -/*! @name KEYSIZE - PUF Key Size register */ -/*! @{ */ -#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) -#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U) -#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) -/*! @} */ - -/*! @name STAT - PUF Status register */ -/*! @{ */ -#define PUF_STAT_BUSY_MASK (0x1U) -#define PUF_STAT_BUSY_SHIFT (0U) -#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) -#define PUF_STAT_SUCCESS_MASK (0x2U) -#define PUF_STAT_SUCCESS_SHIFT (1U) -#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) -#define PUF_STAT_ERROR_MASK (0x4U) -#define PUF_STAT_ERROR_SHIFT (2U) -#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) -#define PUF_STAT_KEYINREQ_MASK (0x10U) -#define PUF_STAT_KEYINREQ_SHIFT (4U) -#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) -#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U) -#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U) -#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) -#define PUF_STAT_CODEINREQ_MASK (0x40U) -#define PUF_STAT_CODEINREQ_SHIFT (6U) -#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) -#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U) -#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U) -#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) -/*! @} */ - -/*! @name ALLOW - PUF Allow register */ -/*! @{ */ -#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U) -#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U) -#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) -#define PUF_ALLOW_ALLOWSTART_MASK (0x2U) -#define PUF_ALLOW_ALLOWSTART_SHIFT (1U) -#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) -#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) -#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) -#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) -#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) -#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) -#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) -/*! @} */ - -/*! @name KEYINPUT - PUF Key Input register */ -/*! @{ */ -#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) -#define PUF_KEYINPUT_KEYIN_SHIFT (0U) -#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) -/*! @} */ - -/*! @name CODEINPUT - PUF Code Input register */ -/*! @{ */ -#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) -#define PUF_CODEINPUT_CODEIN_SHIFT (0U) -#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) -/*! @} */ - -/*! @name CODEOUTPUT - PUF Code Output register */ -/*! @{ */ -#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) -#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) -#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) -/*! @} */ - -/*! @name KEYOUTINDEX - PUF Key Output Index register */ -/*! @{ */ -#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU) -#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) -#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) -/*! @} */ - -/*! @name KEYOUTPUT - PUF Key Output register */ -/*! @{ */ -#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) -#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) -#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) -/*! @} */ - -/*! @name IFSTAT - PUF Interface Status and clear register */ -/*! @{ */ -#define PUF_IFSTAT_ERROR_MASK (0x1U) -#define PUF_IFSTAT_ERROR_SHIFT (0U) -#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) -/*! @} */ - -/*! @name VERSION - PUF version register. */ -/*! @{ */ -#define PUF_VERSION_KEYOUT_MASK (0xFFFFFFFFU) -#define PUF_VERSION_KEYOUT_SHIFT (0U) -#define PUF_VERSION_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_KEYOUT_SHIFT)) & PUF_VERSION_KEYOUT_MASK) -/*! @} */ - -/*! @name INTEN - PUF Interrupt Enable */ -/*! @{ */ -#define PUF_INTEN_READYEN_MASK (0x1U) -#define PUF_INTEN_READYEN_SHIFT (0U) -#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) -#define PUF_INTEN_SUCCESEN_MASK (0x2U) -#define PUF_INTEN_SUCCESEN_SHIFT (1U) -#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK) -#define PUF_INTEN_ERROREN_MASK (0x4U) -#define PUF_INTEN_ERROREN_SHIFT (2U) -#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) -#define PUF_INTEN_KEYINREQEN_MASK (0x10U) -#define PUF_INTEN_KEYINREQEN_SHIFT (4U) -#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) -#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) -#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) -#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) -#define PUF_INTEN_CODEINREQEN_MASK (0x40U) -#define PUF_INTEN_CODEINREQEN_SHIFT (6U) -#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) -#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) -#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) -#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) -/*! @} */ - -/*! @name INTSTAT - PUF interrupt status */ -/*! @{ */ -#define PUF_INTSTAT_READY_MASK (0x1U) -#define PUF_INTSTAT_READY_SHIFT (0U) -#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) -#define PUF_INTSTAT_SUCCESS_MASK (0x2U) -#define PUF_INTSTAT_SUCCESS_SHIFT (1U) -#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) -#define PUF_INTSTAT_ERROR_MASK (0x4U) -#define PUF_INTSTAT_ERROR_SHIFT (2U) -#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) -#define PUF_INTSTAT_KEYINREQ_MASK (0x10U) -#define PUF_INTSTAT_KEYINREQ_SHIFT (4U) -#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) -#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) -#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) -#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) -#define PUF_INTSTAT_CODEINREQ_MASK (0x40U) -#define PUF_INTSTAT_CODEINREQ_SHIFT (6U) -#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) -#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) -#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) -#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) -/*! @} */ - -/*! @name PWRCTRL - PUF RAM Power Control */ -/*! @{ */ -#define PUF_PWRCTRL_RAMON_MASK (0x1U) -#define PUF_PWRCTRL_RAMON_SHIFT (0U) -#define PUF_PWRCTRL_RAMON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK) -#define PUF_PWRCTRL_RAMSTAT_MASK (0x2U) -#define PUF_PWRCTRL_RAMSTAT_SHIFT (1U) -#define PUF_PWRCTRL_RAMSTAT(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK) -/*! @} */ - -/*! @name CFG - PUF config register for block bits */ -/*! @{ */ -#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U) -#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U) -#define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK) -#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U) -#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U) -#define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK) -/*! @} */ - -/*! @name KEYLOCK - Only reset in case of full IC reset */ -/*! @{ */ -#define PUF_KEYLOCK_KEY0_MASK (0x3U) -#define PUF_KEYLOCK_KEY0_SHIFT (0U) -#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK) -#define PUF_KEYLOCK_KEY1_MASK (0xCU) -#define PUF_KEYLOCK_KEY1_SHIFT (2U) -#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK) -#define PUF_KEYLOCK_KEY2_MASK (0x30U) -#define PUF_KEYLOCK_KEY2_SHIFT (4U) -#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK) -#define PUF_KEYLOCK_KEY3_MASK (0xC0U) -#define PUF_KEYLOCK_KEY3_SHIFT (6U) -#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK) -/*! @} */ - -/*! @name KEYENABLE - */ -/*! @{ */ -#define PUF_KEYENABLE_KEY0_MASK (0x3U) -#define PUF_KEYENABLE_KEY0_SHIFT (0U) -#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK) -#define PUF_KEYENABLE_KEY1_MASK (0xCU) -#define PUF_KEYENABLE_KEY1_SHIFT (2U) -#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK) -#define PUF_KEYENABLE_KEY2_MASK (0x30U) -#define PUF_KEYENABLE_KEY2_SHIFT (4U) -#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK) -#define PUF_KEYENABLE_KEY3_MASK (0xC0U) -#define PUF_KEYENABLE_KEY3_SHIFT (6U) -#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK) -/*! @} */ - -/*! @name KEYRESET - Reinitialize Keys shift registers counters */ -/*! @{ */ -#define PUF_KEYRESET_KEY0_MASK (0x3U) -#define PUF_KEYRESET_KEY0_SHIFT (0U) -#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK) -#define PUF_KEYRESET_KEY1_MASK (0xCU) -#define PUF_KEYRESET_KEY1_SHIFT (2U) -#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK) -#define PUF_KEYRESET_KEY2_MASK (0x30U) -#define PUF_KEYRESET_KEY2_SHIFT (4U) -#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK) -#define PUF_KEYRESET_KEY3_MASK (0xC0U) -#define PUF_KEYRESET_KEY3_SHIFT (6U) -#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK) -/*! @} */ - -/*! @name IDXBLK_L - */ -/*! @{ */ -#define PUF_IDXBLK_L_IDX0_MASK (0x3U) -#define PUF_IDXBLK_L_IDX0_SHIFT (0U) -#define PUF_IDXBLK_L_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX0_SHIFT)) & PUF_IDXBLK_L_IDX0_MASK) -#define PUF_IDXBLK_L_IDX1_MASK (0xCU) -#define PUF_IDXBLK_L_IDX1_SHIFT (2U) -#define PUF_IDXBLK_L_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK) -#define PUF_IDXBLK_L_IDX2_MASK (0x30U) -#define PUF_IDXBLK_L_IDX2_SHIFT (4U) -#define PUF_IDXBLK_L_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK) -#define PUF_IDXBLK_L_IDX3_MASK (0xC0U) -#define PUF_IDXBLK_L_IDX3_SHIFT (6U) -#define PUF_IDXBLK_L_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK) -#define PUF_IDXBLK_L_IDX4_MASK (0x300U) -#define PUF_IDXBLK_L_IDX4_SHIFT (8U) -#define PUF_IDXBLK_L_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK) -#define PUF_IDXBLK_L_IDX5_MASK (0xC00U) -#define PUF_IDXBLK_L_IDX5_SHIFT (10U) -#define PUF_IDXBLK_L_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK) -#define PUF_IDXBLK_L_IDX6_MASK (0x3000U) -#define PUF_IDXBLK_L_IDX6_SHIFT (12U) -#define PUF_IDXBLK_L_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK) -#define PUF_IDXBLK_L_IDX7_MASK (0xC000U) -#define PUF_IDXBLK_L_IDX7_SHIFT (14U) -#define PUF_IDXBLK_L_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK) -#define PUF_IDXBLK_L_LOCK_IDX_MASK (0xC0000000U) -#define PUF_IDXBLK_L_LOCK_IDX_SHIFT (30U) -#define PUF_IDXBLK_L_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK) -/*! @} */ - -/*! @name IDXBLK_H_DP - */ -/*! @{ */ -#define PUF_IDXBLK_H_DP_IDX8_MASK (0x3U) -#define PUF_IDXBLK_H_DP_IDX8_SHIFT (0U) -#define PUF_IDXBLK_H_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK) -#define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) -#define PUF_IDXBLK_H_DP_IDX9_SHIFT (2U) -#define PUF_IDXBLK_H_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK) -#define PUF_IDXBLK_H_DP_IDX10_MASK (0x30U) -#define PUF_IDXBLK_H_DP_IDX10_SHIFT (4U) -#define PUF_IDXBLK_H_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK) -#define PUF_IDXBLK_H_DP_IDX11_MASK (0xC0U) -#define PUF_IDXBLK_H_DP_IDX11_SHIFT (6U) -#define PUF_IDXBLK_H_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK) -#define PUF_IDXBLK_H_DP_IDX12_MASK (0x300U) -#define PUF_IDXBLK_H_DP_IDX12_SHIFT (8U) -#define PUF_IDXBLK_H_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK) -#define PUF_IDXBLK_H_DP_IDX13_MASK (0xC00U) -#define PUF_IDXBLK_H_DP_IDX13_SHIFT (10U) -#define PUF_IDXBLK_H_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK) -#define PUF_IDXBLK_H_DP_IDX14_MASK (0x3000U) -#define PUF_IDXBLK_H_DP_IDX14_SHIFT (12U) -#define PUF_IDXBLK_H_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK) -#define PUF_IDXBLK_H_DP_IDX15_MASK (0xC000U) -#define PUF_IDXBLK_H_DP_IDX15_SHIFT (14U) -#define PUF_IDXBLK_H_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK) -/*! @} */ - -/*! @name KEYMASK - Only reset in case of full IC reset */ -/*! @{ */ -#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) -#define PUF_KEYMASK_KEYMASK_SHIFT (0U) -#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK) -/*! @} */ - -/* The count of PUF_KEYMASK */ -#define PUF_KEYMASK_COUNT (4U) - -/*! @name IDXBLK_H - */ -/*! @{ */ -#define PUF_IDXBLK_H_IDX8_MASK (0x3U) -#define PUF_IDXBLK_H_IDX8_SHIFT (0U) -#define PUF_IDXBLK_H_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK) -#define PUF_IDXBLK_H_IDX9_MASK (0xCU) -#define PUF_IDXBLK_H_IDX9_SHIFT (2U) -#define PUF_IDXBLK_H_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK) -#define PUF_IDXBLK_H_IDX10_MASK (0x30U) -#define PUF_IDXBLK_H_IDX10_SHIFT (4U) -#define PUF_IDXBLK_H_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK) -#define PUF_IDXBLK_H_IDX11_MASK (0xC0U) -#define PUF_IDXBLK_H_IDX11_SHIFT (6U) -#define PUF_IDXBLK_H_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK) -#define PUF_IDXBLK_H_IDX12_MASK (0x300U) -#define PUF_IDXBLK_H_IDX12_SHIFT (8U) -#define PUF_IDXBLK_H_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK) -#define PUF_IDXBLK_H_IDX13_MASK (0xC00U) -#define PUF_IDXBLK_H_IDX13_SHIFT (10U) -#define PUF_IDXBLK_H_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK) -#define PUF_IDXBLK_H_IDX14_MASK (0x3000U) -#define PUF_IDXBLK_H_IDX14_SHIFT (12U) -#define PUF_IDXBLK_H_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK) -#define PUF_IDXBLK_H_IDX15_MASK (0xC000U) -#define PUF_IDXBLK_H_IDX15_SHIFT (14U) -#define PUF_IDXBLK_H_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK) -#define PUF_IDXBLK_H_LOCK_IDX_MASK (0xC0000000U) -#define PUF_IDXBLK_H_LOCK_IDX_SHIFT (30U) -#define PUF_IDXBLK_H_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK) -/*! @} */ - -/*! @name IDXBLK_L_DP - */ -/*! @{ */ -#define PUF_IDXBLK_L_DP_IDX0_MASK (0x3U) -#define PUF_IDXBLK_L_DP_IDX0_SHIFT (0U) -#define PUF_IDXBLK_L_DP_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX0_SHIFT)) & PUF_IDXBLK_L_DP_IDX0_MASK) -#define PUF_IDXBLK_L_DP_IDX1_MASK (0xCU) -#define PUF_IDXBLK_L_DP_IDX1_SHIFT (2U) -#define PUF_IDXBLK_L_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK) -#define PUF_IDXBLK_L_DP_IDX2_MASK (0x30U) -#define PUF_IDXBLK_L_DP_IDX2_SHIFT (4U) -#define PUF_IDXBLK_L_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK) -#define PUF_IDXBLK_L_DP_IDX3_MASK (0xC0U) -#define PUF_IDXBLK_L_DP_IDX3_SHIFT (6U) -#define PUF_IDXBLK_L_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK) -#define PUF_IDXBLK_L_DP_IDX4_MASK (0x300U) -#define PUF_IDXBLK_L_DP_IDX4_SHIFT (8U) -#define PUF_IDXBLK_L_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK) -#define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) -#define PUF_IDXBLK_L_DP_IDX5_SHIFT (10U) -#define PUF_IDXBLK_L_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK) -#define PUF_IDXBLK_L_DP_IDX6_MASK (0x3000U) -#define PUF_IDXBLK_L_DP_IDX6_SHIFT (12U) -#define PUF_IDXBLK_L_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK) -#define PUF_IDXBLK_L_DP_IDX7_MASK (0xC000U) -#define PUF_IDXBLK_L_DP_IDX7_SHIFT (14U) -#define PUF_IDXBLK_L_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK) -/*! @} */ - -/*! @name SHIFT_STATUS - */ -/*! @{ */ -#define PUF_SHIFT_STATUS_KEY0_MASK (0xFU) -#define PUF_SHIFT_STATUS_KEY0_SHIFT (0U) -#define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK) -#define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U) -#define PUF_SHIFT_STATUS_KEY1_SHIFT (4U) -#define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK) -#define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U) -#define PUF_SHIFT_STATUS_KEY2_SHIFT (8U) -#define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK) -#define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U) -#define PUF_SHIFT_STATUS_KEY3_SHIFT (12U) -#define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PUF_Register_Masks */ - - -/* PUF - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral PUF base address */ - #define PUF_BASE (0x5003B000u) - /** Peripheral PUF base address */ - #define PUF_BASE_NS (0x4003B000u) - /** Peripheral PUF base pointer */ - #define PUF ((PUF_Type *)PUF_BASE) - /** Peripheral PUF base pointer */ - #define PUF_NS ((PUF_Type *)PUF_BASE_NS) - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS { PUF_BASE } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS { PUF } - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS_NS { PUF_BASE_NS } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS_NS { PUF_NS } -#else - /** Peripheral PUF base address */ - #define PUF_BASE (0x4003B000u) - /** Peripheral PUF base pointer */ - #define PUF ((PUF_Type *)PUF_BASE) - /** Array initializer of PUF peripheral base addresses */ - #define PUF_BASE_ADDRS { PUF_BASE } - /** Array initializer of PUF peripheral base pointers */ - #define PUF_BASE_PTRS { PUF } -#endif -/** Interrupt vectors for the PUF peripheral type */ -#define PUF_IRQS { PUF_IRQn } - -/*! - * @} - */ /* end of group PUF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RNG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer - * @{ - */ - -/** RNG - Register Layout Typedef */ -typedef struct { - __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */ - __I uint32_t ENCRYPTED_NUMBER; /**< This register contains a random 32 bit number which is pre-computed, offset: 0x4 */ - __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */ - __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */ - __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */ - __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */ - __IO uint32_t MISC_CFG; /**< , offset: 0x18 */ - uint8_t RESERVED_0[4056]; - __IO uint32_t POWERDOWN; /**< Powerdown mode (standard but certainly useless here), offset: 0xFF4 */ - uint8_t RESERVED_1[4]; - __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */ -} RNG_Type; - -/* ---------------------------------------------------------------------------- - -- RNG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RNG_Register_Masks RNG Register Masks - * @{ - */ - -/*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */ -/*! @{ */ -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU) -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U) -#define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK) -/*! @} */ - -/*! @name ENCRYPTED_NUMBER - This register contains a random 32 bit number which is pre-computed */ -/*! @{ */ -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK (0xFFFFFFFFU) -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT (0U) -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT)) & RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK) -/*! @} */ - -/*! @name COUNTER_VAL - */ -/*! @{ */ -#define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU) -#define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U) -#define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK) -#define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x1F00U) -#define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U) -#define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK) -/*! @} */ - -/*! @name COUNTER_CFG - */ -/*! @{ */ -#define RNG_COUNTER_CFG_MODE_MASK (0x3U) -#define RNG_COUNTER_CFG_MODE_SHIFT (0U) -#define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK) -#define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU) -#define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U) -#define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK) -#define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U) -#define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U) -#define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK) -#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_MASK (0x100U) -#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_SHIFT (8U) -#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_SHIFT)) & RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_MASK) -#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_MASK (0x200U) -#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_SHIFT (9U) -#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_SHIFT)) & RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_MASK) -/*! @} */ - -/*! @name ONLINE_TEST_CFG - */ -/*! @{ */ -#define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U) -#define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U) -#define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK) -#define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U) -#define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U) -#define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK) -/*! @} */ - -/*! @name ONLINE_TEST_VAL - */ -/*! @{ */ -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU) -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U) -#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK) -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U) -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U) -#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U) -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U) -#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) -/*! @} */ - -/*! @name MISC_CFG - */ -/*! @{ */ -#define RNG_MISC_CFG_AES_RESEED_MASK (0x1U) -#define RNG_MISC_CFG_AES_RESEED_SHIFT (0U) -#define RNG_MISC_CFG_AES_RESEED(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_RESEED_SHIFT)) & RNG_MISC_CFG_AES_RESEED_MASK) -#define RNG_MISC_CFG_AES_DT_CFG_MASK (0x2U) -#define RNG_MISC_CFG_AES_DT_CFG_SHIFT (1U) -#define RNG_MISC_CFG_AES_DT_CFG(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_DT_CFG_SHIFT)) & RNG_MISC_CFG_AES_DT_CFG_MASK) -/*! @} */ - -/*! @name POWERDOWN - Powerdown mode (standard but certainly useless here) */ -/*! @{ */ -#define RNG_POWERDOWN_SOFT_RESET_MASK (0x1U) -#define RNG_POWERDOWN_SOFT_RESET_SHIFT (0U) -#define RNG_POWERDOWN_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_SOFT_RESET_MASK) -#define RNG_POWERDOWN_FORCE_SOFT_RESET_MASK (0x2U) -#define RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT (1U) -#define RNG_POWERDOWN_FORCE_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_FORCE_SOFT_RESET_MASK) -#define RNG_POWERDOWN_POWERDOWN_MASK (0x80000000U) -#define RNG_POWERDOWN_POWERDOWN_SHIFT (31U) -#define RNG_POWERDOWN_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_POWERDOWN_SHIFT)) & RNG_POWERDOWN_POWERDOWN_MASK) -/*! @} */ - -/*! @name MODULEID - IP identifier */ -/*! @{ */ -#define RNG_MODULEID_APERTURE_MASK (0xFFU) -#define RNG_MODULEID_APERTURE_SHIFT (0U) -#define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK) -#define RNG_MODULEID_MIN_REV_MASK (0xF00U) -#define RNG_MODULEID_MIN_REV_SHIFT (8U) -#define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK) -#define RNG_MODULEID_MAJ_REV_MASK (0xF000U) -#define RNG_MODULEID_MAJ_REV_SHIFT (12U) -#define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK) -#define RNG_MODULEID_ID_MASK (0xFFFF0000U) -#define RNG_MODULEID_ID_SHIFT (16U) -#define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group RNG_Register_Masks */ - - -/* RNG - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral RNG base address */ - #define RNG_BASE (0x5003A000u) - /** Peripheral RNG base address */ - #define RNG_BASE_NS (0x4003A000u) - /** Peripheral RNG base pointer */ - #define RNG ((RNG_Type *)RNG_BASE) - /** Peripheral RNG base pointer */ - #define RNG_NS ((RNG_Type *)RNG_BASE_NS) - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS { RNG_BASE } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS { RNG } - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS_NS { RNG_BASE_NS } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS_NS { RNG_NS } -#else - /** Peripheral RNG base address */ - #define RNG_BASE (0x4003A000u) - /** Peripheral RNG base pointer */ - #define RNG ((RNG_Type *)RNG_BASE) - /** Array initializer of RNG peripheral base addresses */ - #define RNG_BASE_ADDRS { RNG_BASE } - /** Array initializer of RNG peripheral base pointers */ - #define RNG_BASE_PTRS { RNG } -#endif - -/*! - * @} - */ /* end of group RNG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer - * @{ - */ - -/** RTC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ - __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ - __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ - __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ - __I uint32_t SUBSEC; /**< RTC Sub-second Counter register, offset: 0x10 */ - uint8_t RESERVED_0[44]; - __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ -} RTC_Type; - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/*! @name CTRL - RTC control register */ -/*! @{ */ -#define RTC_CTRL_SWRESET_MASK (0x1U) -#define RTC_CTRL_SWRESET_SHIFT (0U) -/*! SWRESET - Software reset control - * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. - * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. - */ -#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) -#define RTC_CTRL_ALARM1HZ_MASK (0x4U) -#define RTC_CTRL_ALARM1HZ_SHIFT (2U) -/*! ALARM1HZ - RTC 1 Hz timer alarm flag status. - * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. - * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. - */ -#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) -#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) -#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) -/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. - * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. - * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. - */ -#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) -#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) -#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) -/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. - * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. - */ -#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) -#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) -#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) -/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. - * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. - */ -#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) -#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) -#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) -/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). - * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. The 1 kHz RTC timer is enabled. - */ -#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) -#define RTC_CTRL_RTC_EN_MASK (0x80U) -#define RTC_CTRL_RTC_EN_SHIFT (7U) -/*! RTC_EN - RTC enable. - * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register. - * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register. - */ -#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) -#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) -#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) -/*! RTC_OSC_PD - RTC oscillator power-down control. - * 0b0..See RTC_OSC_BYPASS - * 0b1..RTC oscillator is powered-down. - */ -#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) -#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) -#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) -/*! RTC_OSC_BYPASS - RTC oscillator bypass control. - * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. - * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. - */ -#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) -#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U) -#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U) -/*! RTC_SUBSEC_ENA - RTC Sub-second counter control. - * 0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second counter, this bit will always read-back as a '0'. - * 0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip exits deep power-down mode. - */ -#define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK) -/*! @} */ - -/*! @name MATCH - RTC match register */ -/*! @{ */ -#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) -#define RTC_MATCH_MATVAL_SHIFT (0U) -#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) -/*! @} */ - -/*! @name COUNT - RTC counter register */ -/*! @{ */ -#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) -#define RTC_COUNT_VAL_SHIFT (0U) -#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) -/*! @} */ - -/*! @name WAKE - High-resolution/wake-up timer control register */ -/*! @{ */ -#define RTC_WAKE_VAL_MASK (0xFFFFU) -#define RTC_WAKE_VAL_SHIFT (0U) -#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) -/*! @} */ - -/*! @name SUBSEC - RTC Sub-second Counter register */ -/*! @{ */ -#define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU) -#define RTC_SUBSEC_SUBSEC_SHIFT (0U) -#define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK) -/*! @} */ - -/*! @name GPREG - General Purpose register */ -/*! @{ */ -#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) -#define RTC_GPREG_GPDATA_SHIFT (0U) -#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) -/*! @} */ - -/* The count of RTC_GPREG */ -#define RTC_GPREG_COUNT (8U) - - -/*! - * @} - */ /* end of group RTC_Register_Masks */ - - -/* RTC - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral RTC base address */ - #define RTC_BASE (0x5002C000u) - /** Peripheral RTC base address */ - #define RTC_BASE_NS (0x4002C000u) - /** Peripheral RTC base pointer */ - #define RTC ((RTC_Type *)RTC_BASE) - /** Peripheral RTC base pointer */ - #define RTC_NS ((RTC_Type *)RTC_BASE_NS) - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS { RTC_BASE } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS { RTC } - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS_NS { RTC_NS } -#else - /** Peripheral RTC base address */ - #define RTC_BASE (0x4002C000u) - /** Peripheral RTC base pointer */ - #define RTC ((RTC_Type *)RTC_BASE) - /** Array initializer of RTC peripheral base addresses */ - #define RTC_BASE_ADDRS { RTC_BASE } - /** Array initializer of RTC peripheral base pointers */ - #define RTC_BASE_PTRS { RTC } -#endif -/** Interrupt vectors for the RTC peripheral type */ -#define RTC_IRQS { RTC_IRQn } - -/*! - * @} - */ /* end of group RTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SCT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer - * @{ - */ - -/** SCT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ - __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ - __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ - __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ - __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ - __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ - uint8_t RESERVED_0[40]; - __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ - __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ - __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ - __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ - __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ - __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ - __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ - __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */ - __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */ - uint8_t RESERVED_1[140]; - __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ - __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ - __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ - __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ - union { /* offset: 0x100 */ - __IO uint32_t SCTCAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ - __IO uint32_t SCTMATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ - }; - uint8_t RESERVED_2[216]; - union { /* offset: 0x200 */ - __IO uint32_t SCTCAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ - __IO uint32_t SCTMATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ - }; - uint8_t RESERVED_3[216]; - struct { /* offset: 0x300, array step: 0x8 */ - __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ - __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ - } EVENT[10]; - uint8_t RESERVED_4[432]; - struct { /* offset: 0x500, array step: 0x8 */ - __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ - __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ - } OUT[10]; -} SCT_Type; - -/* ---------------------------------------------------------------------------- - -- SCT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Register_Masks SCT Register Masks - * @{ - */ - -/*! @name CONFIG - SCT configuration register */ -/*! @{ */ -#define SCT_CONFIG_UNIFY_MASK (0x1U) -#define SCT_CONFIG_UNIFY_SHIFT (0U) -/*! UNIFY - SCT operation - * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. - * 0b1..The SCT operates as a unified 32-bit counter. - */ -#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) -#define SCT_CONFIG_CLKMODE_MASK (0x6U) -#define SCT_CONFIG_CLKMODE_SHIFT (1U) -/*! CLKMODE - SCT clock mode - * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. - * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode. - * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. - * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock. - */ -#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) -#define SCT_CONFIG_CKSEL_MASK (0x78U) -#define SCT_CONFIG_CKSEL_SHIFT (3U) -/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register. - * 0b0000..Rising edges on input 0. - * 0b0001..Falling edges on input 0. - * 0b0010..Rising edges on input 1. - * 0b0011..Falling edges on input 1. - * 0b0100..Rising edges on input 2. - * 0b0101..Falling edges on input 2. - * 0b0110..Rising edges on input 3. - * 0b0111..Falling edges on input 3. - */ -#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) -#define SCT_CONFIG_NORELAOD_L_MASK (0x80U) -#define SCT_CONFIG_NORELAOD_L_SHIFT (7U) -#define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK) -#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) -#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) -#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) -#define SCT_CONFIG_INSYNC_MASK (0x1E00U) -#define SCT_CONFIG_INSYNC_SHIFT (9U) -#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) -#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) -#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) -#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) -#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) -#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) -#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) -/*! @} */ - -/*! @name CTRL - SCT control register */ -/*! @{ */ -#define SCT_CTRL_DOWN_L_MASK (0x1U) -#define SCT_CTRL_DOWN_L_SHIFT (0U) -#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) -#define SCT_CTRL_STOP_L_MASK (0x2U) -#define SCT_CTRL_STOP_L_SHIFT (1U) -#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) -#define SCT_CTRL_HALT_L_MASK (0x4U) -#define SCT_CTRL_HALT_L_SHIFT (2U) -#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) -#define SCT_CTRL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRL_CLRCTR_L_SHIFT (3U) -#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) -#define SCT_CTRL_BIDIR_L_MASK (0x10U) -#define SCT_CTRL_BIDIR_L_SHIFT (4U) -/*! BIDIR_L - L or unified counter direction select - * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. - * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) -#define SCT_CTRL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRL_PRE_L_SHIFT (5U) -#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) -#define SCT_CTRL_DOWN_H_MASK (0x10000U) -#define SCT_CTRL_DOWN_H_SHIFT (16U) -#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) -#define SCT_CTRL_STOP_H_MASK (0x20000U) -#define SCT_CTRL_STOP_H_SHIFT (17U) -#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) -#define SCT_CTRL_HALT_H_MASK (0x40000U) -#define SCT_CTRL_HALT_H_SHIFT (18U) -#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) -#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) -#define SCT_CTRL_CLRCTR_H_SHIFT (19U) -#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) -#define SCT_CTRL_BIDIR_H_MASK (0x100000U) -#define SCT_CTRL_BIDIR_H_SHIFT (20U) -/*! BIDIR_H - Direction select - * 0b0..The H counter counts up to its limit condition, then is cleared to zero. - * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) -#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) -#define SCT_CTRL_PRE_H_SHIFT (21U) -#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) -/*! @} */ - -/*! @name LIMIT - SCT limit event select register */ -/*! @{ */ -#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) -#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) -#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) -#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) -#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) -#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) -/*! @} */ - -/*! @name HALT - SCT halt event select register */ -/*! @{ */ -#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) -#define SCT_HALT_HALTMSK_L_SHIFT (0U) -#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) -#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) -#define SCT_HALT_HALTMSK_H_SHIFT (16U) -#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) -/*! @} */ - -/*! @name STOP - SCT stop event select register */ -/*! @{ */ -#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) -#define SCT_STOP_STOPMSK_L_SHIFT (0U) -#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) -#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) -#define SCT_STOP_STOPMSK_H_SHIFT (16U) -#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) -/*! @} */ - -/*! @name START - SCT start event select register */ -/*! @{ */ -#define SCT_START_STARTMSK_L_MASK (0xFFFFU) -#define SCT_START_STARTMSK_L_SHIFT (0U) -#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) -#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) -#define SCT_START_STARTMSK_H_SHIFT (16U) -#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) -/*! @} */ - -/*! @name COUNT - SCT counter register */ -/*! @{ */ -#define SCT_COUNT_CTR_L_MASK (0xFFFFU) -#define SCT_COUNT_CTR_L_SHIFT (0U) -#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) -#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) -#define SCT_COUNT_CTR_H_SHIFT (16U) -#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) -/*! @} */ - -/*! @name STATE - SCT state register */ -/*! @{ */ -#define SCT_STATE_STATE_L_MASK (0x1FU) -#define SCT_STATE_STATE_L_SHIFT (0U) -#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) -#define SCT_STATE_STATE_H_MASK (0x1F0000U) -#define SCT_STATE_STATE_H_SHIFT (16U) -#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) -/*! @} */ - -/*! @name INPUT - SCT input register */ -/*! @{ */ -#define SCT_INPUT_AIN0_MASK (0x1U) -#define SCT_INPUT_AIN0_SHIFT (0U) -#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) -#define SCT_INPUT_AIN1_MASK (0x2U) -#define SCT_INPUT_AIN1_SHIFT (1U) -#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) -#define SCT_INPUT_AIN2_MASK (0x4U) -#define SCT_INPUT_AIN2_SHIFT (2U) -#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) -#define SCT_INPUT_AIN3_MASK (0x8U) -#define SCT_INPUT_AIN3_SHIFT (3U) -#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) -#define SCT_INPUT_AIN4_MASK (0x10U) -#define SCT_INPUT_AIN4_SHIFT (4U) -#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) -#define SCT_INPUT_AIN5_MASK (0x20U) -#define SCT_INPUT_AIN5_SHIFT (5U) -#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) -#define SCT_INPUT_AIN6_MASK (0x40U) -#define SCT_INPUT_AIN6_SHIFT (6U) -#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) -#define SCT_INPUT_AIN7_MASK (0x80U) -#define SCT_INPUT_AIN7_SHIFT (7U) -#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) -#define SCT_INPUT_AIN8_MASK (0x100U) -#define SCT_INPUT_AIN8_SHIFT (8U) -#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) -#define SCT_INPUT_AIN9_MASK (0x200U) -#define SCT_INPUT_AIN9_SHIFT (9U) -#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) -#define SCT_INPUT_AIN10_MASK (0x400U) -#define SCT_INPUT_AIN10_SHIFT (10U) -#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) -#define SCT_INPUT_AIN11_MASK (0x800U) -#define SCT_INPUT_AIN11_SHIFT (11U) -#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) -#define SCT_INPUT_AIN12_MASK (0x1000U) -#define SCT_INPUT_AIN12_SHIFT (12U) -#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) -#define SCT_INPUT_AIN13_MASK (0x2000U) -#define SCT_INPUT_AIN13_SHIFT (13U) -#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) -#define SCT_INPUT_AIN14_MASK (0x4000U) -#define SCT_INPUT_AIN14_SHIFT (14U) -#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) -#define SCT_INPUT_AIN15_MASK (0x8000U) -#define SCT_INPUT_AIN15_SHIFT (15U) -#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) -#define SCT_INPUT_SIN0_MASK (0x10000U) -#define SCT_INPUT_SIN0_SHIFT (16U) -#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) -#define SCT_INPUT_SIN1_MASK (0x20000U) -#define SCT_INPUT_SIN1_SHIFT (17U) -#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) -#define SCT_INPUT_SIN2_MASK (0x40000U) -#define SCT_INPUT_SIN2_SHIFT (18U) -#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) -#define SCT_INPUT_SIN3_MASK (0x80000U) -#define SCT_INPUT_SIN3_SHIFT (19U) -#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) -#define SCT_INPUT_SIN4_MASK (0x100000U) -#define SCT_INPUT_SIN4_SHIFT (20U) -#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) -#define SCT_INPUT_SIN5_MASK (0x200000U) -#define SCT_INPUT_SIN5_SHIFT (21U) -#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) -#define SCT_INPUT_SIN6_MASK (0x400000U) -#define SCT_INPUT_SIN6_SHIFT (22U) -#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) -#define SCT_INPUT_SIN7_MASK (0x800000U) -#define SCT_INPUT_SIN7_SHIFT (23U) -#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) -#define SCT_INPUT_SIN8_MASK (0x1000000U) -#define SCT_INPUT_SIN8_SHIFT (24U) -#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) -#define SCT_INPUT_SIN9_MASK (0x2000000U) -#define SCT_INPUT_SIN9_SHIFT (25U) -#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) -#define SCT_INPUT_SIN10_MASK (0x4000000U) -#define SCT_INPUT_SIN10_SHIFT (26U) -#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) -#define SCT_INPUT_SIN11_MASK (0x8000000U) -#define SCT_INPUT_SIN11_SHIFT (27U) -#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) -#define SCT_INPUT_SIN12_MASK (0x10000000U) -#define SCT_INPUT_SIN12_SHIFT (28U) -#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) -#define SCT_INPUT_SIN13_MASK (0x20000000U) -#define SCT_INPUT_SIN13_SHIFT (29U) -#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) -#define SCT_INPUT_SIN14_MASK (0x40000000U) -#define SCT_INPUT_SIN14_SHIFT (30U) -#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) -#define SCT_INPUT_SIN15_MASK (0x80000000U) -#define SCT_INPUT_SIN15_SHIFT (31U) -#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) -/*! @} */ - -/*! @name REGMODE - SCT match/capture mode register */ -/*! @{ */ -#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) -#define SCT_REGMODE_REGMOD_L_SHIFT (0U) -#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) -#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) -#define SCT_REGMODE_REGMOD_H_SHIFT (16U) -#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) -/*! @} */ - -/*! @name OUTPUT - SCT output register */ -/*! @{ */ -#define SCT_OUTPUT_OUT_MASK (0xFFFFU) -#define SCT_OUTPUT_OUT_SHIFT (0U) -#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) -/*! @} */ - -/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ -/*! @{ */ -#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) -#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) -/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) -#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) -/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) -#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) -/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) -#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) -/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) -#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) -/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) -#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) -/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) -#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) -/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) -#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) -/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) -#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) -/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) -#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) -/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) -#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) -/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) -#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) -/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) -/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) -/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) -/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) -/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) -/*! @} */ - -/*! @name RES - SCT conflict resolution register */ -/*! @{ */ -#define SCT_RES_O0RES_MASK (0x3U) -#define SCT_RES_O0RES_SHIFT (0U) -/*! O0RES - Effect of simultaneous set and clear on output 0. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR0 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) -#define SCT_RES_O1RES_MASK (0xCU) -#define SCT_RES_O1RES_SHIFT (2U) -/*! O1RES - Effect of simultaneous set and clear on output 1. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR1 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) -#define SCT_RES_O2RES_MASK (0x30U) -#define SCT_RES_O2RES_SHIFT (4U) -/*! O2RES - Effect of simultaneous set and clear on output 2. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output n (or set based on the SETCLR2 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) -#define SCT_RES_O3RES_MASK (0xC0U) -#define SCT_RES_O3RES_SHIFT (6U) -/*! O3RES - Effect of simultaneous set and clear on output 3. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR3 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) -#define SCT_RES_O4RES_MASK (0x300U) -#define SCT_RES_O4RES_SHIFT (8U) -/*! O4RES - Effect of simultaneous set and clear on output 4. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR4 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) -#define SCT_RES_O5RES_MASK (0xC00U) -#define SCT_RES_O5RES_SHIFT (10U) -/*! O5RES - Effect of simultaneous set and clear on output 5. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR5 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) -#define SCT_RES_O6RES_MASK (0x3000U) -#define SCT_RES_O6RES_SHIFT (12U) -/*! O6RES - Effect of simultaneous set and clear on output 6. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR6 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) -#define SCT_RES_O7RES_MASK (0xC000U) -#define SCT_RES_O7RES_SHIFT (14U) -/*! O7RES - Effect of simultaneous set and clear on output 7. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output n (or set based on the SETCLR7 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) -#define SCT_RES_O8RES_MASK (0x30000U) -#define SCT_RES_O8RES_SHIFT (16U) -/*! O8RES - Effect of simultaneous set and clear on output 8. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR8 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) -#define SCT_RES_O9RES_MASK (0xC0000U) -#define SCT_RES_O9RES_SHIFT (18U) -/*! O9RES - Effect of simultaneous set and clear on output 9. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR9 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) -#define SCT_RES_O10RES_MASK (0x300000U) -#define SCT_RES_O10RES_SHIFT (20U) -/*! O10RES - Effect of simultaneous set and clear on output 10. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR10 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) -#define SCT_RES_O11RES_MASK (0xC00000U) -#define SCT_RES_O11RES_SHIFT (22U) -/*! O11RES - Effect of simultaneous set and clear on output 11. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR11 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) -#define SCT_RES_O12RES_MASK (0x3000000U) -#define SCT_RES_O12RES_SHIFT (24U) -/*! O12RES - Effect of simultaneous set and clear on output 12. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR12 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) -#define SCT_RES_O13RES_MASK (0xC000000U) -#define SCT_RES_O13RES_SHIFT (26U) -/*! O13RES - Effect of simultaneous set and clear on output 13. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR13 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) -#define SCT_RES_O14RES_MASK (0x30000000U) -#define SCT_RES_O14RES_SHIFT (28U) -/*! O14RES - Effect of simultaneous set and clear on output 14. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR14 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) -#define SCT_RES_O15RES_MASK (0xC0000000U) -#define SCT_RES_O15RES_SHIFT (30U) -/*! O15RES - Effect of simultaneous set and clear on output 15. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR15 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) -/*! @} */ - -/*! @name DMA0REQUEST - SCT DMA request 0 register */ -/*! @{ */ -#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU) -#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U) -#define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK) -#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U) -#define SCT_DMA0REQUEST_DRL0_SHIFT (30U) -#define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK) -#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U) -#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U) -#define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK) -/*! @} */ - -/*! @name DMA1REQUEST - SCT DMA request 1 register */ -/*! @{ */ -#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU) -#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U) -#define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK) -#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U) -#define SCT_DMA1REQUEST_DRL1_SHIFT (30U) -#define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK) -#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U) -#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U) -#define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK) -/*! @} */ - -/*! @name EVEN - SCT event interrupt enable register */ -/*! @{ */ -#define SCT_EVEN_IEN_MASK (0xFFFFU) -#define SCT_EVEN_IEN_SHIFT (0U) -#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) -/*! @} */ - -/*! @name EVFLAG - SCT event flag register */ -/*! @{ */ -#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) -#define SCT_EVFLAG_FLAG_SHIFT (0U) -#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) -/*! @} */ - -/*! @name CONEN - SCT conflict interrupt enable register */ -/*! @{ */ -#define SCT_CONEN_NCEN_MASK (0xFFFFU) -#define SCT_CONEN_NCEN_SHIFT (0U) -#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) -/*! @} */ - -/*! @name CONFLAG - SCT conflict flag register */ -/*! @{ */ -#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) -#define SCT_CONFLAG_NCFLAG_SHIFT (0U) -#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) -#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) -#define SCT_CONFLAG_BUSERRL_SHIFT (30U) -#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) -#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) -#define SCT_CONFLAG_BUSERRH_SHIFT (31U) -#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) -/*! @} */ - -/*! @name SCTCAP - SCT capture register of capture channel */ -/*! @{ */ -#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU) -#define SCT_SCTCAP_CAPn_L_SHIFT (0U) -#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK) -#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U) -#define SCT_SCTCAP_CAPn_H_SHIFT (16U) -#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTCAP */ -#define SCT_SCTCAP_COUNT (10U) - -/*! @name SCTMATCH - SCT match value register of match channels */ -/*! @{ */ -#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU) -#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U) -#define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK) -#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U) -#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U) -#define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTMATCH */ -#define SCT_SCTMATCH_COUNT (10U) - -/*! @name SCTCAPCTRL - SCT capture control register */ -/*! @{ */ -#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU) -#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U) -#define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK) -#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) -#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U) -#define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTCAPCTRL */ -#define SCT_SCTCAPCTRL_COUNT (10U) - -/*! @name SCTMATCHREL - SCT match reload value register */ -/*! @{ */ -#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU) -#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U) -#define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK) -#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U) -#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U) -#define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTMATCHREL */ -#define SCT_SCTMATCHREL_COUNT (10U) - -/*! @name EVENT_STATE - SCT event state register 0 */ -/*! @{ */ -#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU) -#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U) -#define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK) -/*! @} */ - -/* The count of SCT_EVENT_STATE */ -#define SCT_EVENT_STATE_COUNT (10U) - -/*! @name EVENT_CTRL - SCT event control register 0 */ -/*! @{ */ -#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU) -#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U) -#define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK) -#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U) -#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U) -/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. - * 0b0..Selects the L state and the L match register selected by MATCHSEL. - * 0b1..Selects the H state and the H match register selected by MATCHSEL. - */ -#define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK) -#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U) -#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U) -/*! OUTSEL - Input/output select - * 0b0..Selects the inputs selected by IOSEL. - * 0b1..Selects the outputs selected by IOSEL. - */ -#define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK) -#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U) -#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U) -#define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK) -#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U) -#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U) -/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . - * 0b00..LOW - * 0b01..Rise - * 0b10..Fall - * 0b11..HIGH - */ -#define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK) -#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U) -#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U) -/*! COMBMODE - Selects how the specified match and I/O condition are used and combined. - * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. - * 0b01..MATCH. Uses the specified match only. - * 0b10..IO. Uses the specified I/O condition only. - * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. - */ -#define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK) -#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U) -#define SCT_EVENT_CTRL_STATELD_SHIFT (14U) -/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. - * 0b0..STATEV value is added into STATE (the carry-out is ignored). - * 0b1..STATEV value is loaded into STATE. - */ -#define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK) -#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U) -#define SCT_EVENT_CTRL_STATEV_SHIFT (15U) -#define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK) -#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U) -#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U) -#define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK) -#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U) -#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U) -/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. - * 0b00..Direction independent. This event is triggered regardless of the count direction. - * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. - * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. - */ -#define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK) -/*! @} */ - -/* The count of SCT_EVENT_CTRL */ -#define SCT_EVENT_CTRL_COUNT (10U) - -/*! @name OUT_SET - SCT output 0 set register */ -/*! @{ */ -#define SCT_OUT_SET_SET_MASK (0xFFFFU) -#define SCT_OUT_SET_SET_SHIFT (0U) -#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) -/*! @} */ - -/* The count of SCT_OUT_SET */ -#define SCT_OUT_SET_COUNT (10U) - -/*! @name OUT_CLR - SCT output 0 clear register */ -/*! @{ */ -#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) -#define SCT_OUT_CLR_CLR_SHIFT (0U) -#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) -/*! @} */ - -/* The count of SCT_OUT_CLR */ -#define SCT_OUT_CLR_COUNT (10U) - - -/*! - * @} - */ /* end of group SCT_Register_Masks */ - - -/* SCT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral SCT0 base address */ - #define SCT0_BASE (0x50085000u) - /** Peripheral SCT0 base address */ - #define SCT0_BASE_NS (0x40085000u) - /** Peripheral SCT0 base pointer */ - #define SCT0 ((SCT_Type *)SCT0_BASE) - /** Peripheral SCT0 base pointer */ - #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS { SCT0_BASE } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS { SCT0 } - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS_NS { SCT0_NS } -#else - /** Peripheral SCT0 base address */ - #define SCT0_BASE (0x40085000u) - /** Peripheral SCT0 base pointer */ - #define SCT0 ((SCT_Type *)SCT0_BASE) - /** Array initializer of SCT peripheral base addresses */ - #define SCT_BASE_ADDRS { SCT0_BASE } - /** Array initializer of SCT peripheral base pointers */ - #define SCT_BASE_PTRS { SCT0 } -#endif -/** Interrupt vectors for the SCT peripheral type */ -#define SCT_IRQS { SCT0_IRQn } - -/*! - * @} - */ /* end of group SCT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SDIF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer - * @{ - */ - -/** SDIF - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ - __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */ - __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */ - __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */ - __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */ - __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */ - __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */ - __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */ - __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */ - __IO uint32_t CMD; /**< Command register, offset: 0x2C */ - __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */ - __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */ - __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */ - __IO uint32_t STATUS; /**< Status register, offset: 0x48 */ - __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */ - __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */ - __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */ - uint8_t RESERVED_1[4]; - __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */ - __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */ - __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */ - uint8_t RESERVED_2[16]; - __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */ - uint8_t RESERVED_3[4]; - __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */ - __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */ - __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */ - __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */ - __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */ - __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */ - __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */ - uint8_t RESERVED_4[100]; - __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */ - __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */ - uint8_t RESERVED_5[248]; - __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */ -} SDIF_Type; - -/* ---------------------------------------------------------------------------- - -- SDIF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDIF_Register_Masks SDIF Register Masks - * @{ - */ - -/*! @name CTRL - Control register */ -/*! @{ */ -#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U) -#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U) -#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK) -#define SDIF_CTRL_FIFO_RESET_MASK (0x2U) -#define SDIF_CTRL_FIFO_RESET_SHIFT (1U) -#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK) -#define SDIF_CTRL_DMA_RESET_MASK (0x4U) -#define SDIF_CTRL_DMA_RESET_SHIFT (2U) -#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK) -#define SDIF_CTRL_INT_ENABLE_MASK (0x10U) -#define SDIF_CTRL_INT_ENABLE_SHIFT (4U) -#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK) -#define SDIF_CTRL_READ_WAIT_MASK (0x40U) -#define SDIF_CTRL_READ_WAIT_SHIFT (6U) -#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK) -#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U) -#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) -#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK) -#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U) -#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U) -#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK) -#define SDIF_CTRL_SEND_CCSD_MASK (0x200U) -#define SDIF_CTRL_SEND_CCSD_SHIFT (9U) -#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK) -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U) -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) -#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK) -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U) -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) -#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK) -#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U) -#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U) -#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK) -#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U) -#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U) -#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK) -#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U) -#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U) -#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK) -#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U) -#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) -#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) -/*! @} */ - -/*! @name PWREN - Power Enable register */ -/*! @{ */ -#define SDIF_PWREN_POWER_ENABLE0_MASK (0x1U) -#define SDIF_PWREN_POWER_ENABLE0_SHIFT (0U) -#define SDIF_PWREN_POWER_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK) -#define SDIF_PWREN_POWER_ENABLE1_MASK (0x2U) -#define SDIF_PWREN_POWER_ENABLE1_SHIFT (1U) -#define SDIF_PWREN_POWER_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK) -/*! @} */ - -/*! @name CLKDIV - Clock Divider register */ -/*! @{ */ -#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU) -#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U) -#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK) -/*! @} */ - -/*! @name CLKENA - Clock Enable register */ -/*! @{ */ -#define SDIF_CLKENA_CCLK0_ENABLE_MASK (0x1U) -#define SDIF_CLKENA_CCLK0_ENABLE_SHIFT (0U) -#define SDIF_CLKENA_CCLK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK) -#define SDIF_CLKENA_CCLK1_ENABLE_MASK (0x2U) -#define SDIF_CLKENA_CCLK1_ENABLE_SHIFT (1U) -#define SDIF_CLKENA_CCLK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK) -#define SDIF_CLKENA_CCLK0_LOW_POWER_MASK (0x10000U) -#define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT (16U) -#define SDIF_CLKENA_CCLK0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK) -#define SDIF_CLKENA_CCLK1_LOW_POWER_MASK (0x20000U) -#define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT (17U) -#define SDIF_CLKENA_CCLK1_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK) -/*! @} */ - -/*! @name TMOUT - Time-out register */ -/*! @{ */ -#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU) -#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) -#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK) -#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U) -#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U) -#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK) -/*! @} */ - -/*! @name CTYPE - Card Type register */ -/*! @{ */ -#define SDIF_CTYPE_CARD0_WIDTH0_MASK (0x1U) -#define SDIF_CTYPE_CARD0_WIDTH0_SHIFT (0U) -#define SDIF_CTYPE_CARD0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK) -#define SDIF_CTYPE_CARD1_WIDTH0_MASK (0x2U) -#define SDIF_CTYPE_CARD1_WIDTH0_SHIFT (1U) -#define SDIF_CTYPE_CARD1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK) -#define SDIF_CTYPE_CARD0_WIDTH1_MASK (0x10000U) -#define SDIF_CTYPE_CARD0_WIDTH1_SHIFT (16U) -#define SDIF_CTYPE_CARD0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK) -#define SDIF_CTYPE_CARD1_WIDTH1_MASK (0x20000U) -#define SDIF_CTYPE_CARD1_WIDTH1_SHIFT (17U) -#define SDIF_CTYPE_CARD1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK) -/*! @} */ - -/*! @name BLKSIZ - Block Size register */ -/*! @{ */ -#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU) -#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U) -#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK) -/*! @} */ - -/*! @name BYTCNT - Byte Count register */ -/*! @{ */ -#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U) -#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK) -/*! @} */ - -/*! @name INTMASK - Interrupt Mask register */ -/*! @{ */ -#define SDIF_INTMASK_CDET_MASK (0x1U) -#define SDIF_INTMASK_CDET_SHIFT (0U) -#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK) -#define SDIF_INTMASK_RE_MASK (0x2U) -#define SDIF_INTMASK_RE_SHIFT (1U) -#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK) -#define SDIF_INTMASK_CDONE_MASK (0x4U) -#define SDIF_INTMASK_CDONE_SHIFT (2U) -#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK) -#define SDIF_INTMASK_DTO_MASK (0x8U) -#define SDIF_INTMASK_DTO_SHIFT (3U) -#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK) -#define SDIF_INTMASK_TXDR_MASK (0x10U) -#define SDIF_INTMASK_TXDR_SHIFT (4U) -#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK) -#define SDIF_INTMASK_RXDR_MASK (0x20U) -#define SDIF_INTMASK_RXDR_SHIFT (5U) -#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK) -#define SDIF_INTMASK_RCRC_MASK (0x40U) -#define SDIF_INTMASK_RCRC_SHIFT (6U) -#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK) -#define SDIF_INTMASK_DCRC_MASK (0x80U) -#define SDIF_INTMASK_DCRC_SHIFT (7U) -#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK) -#define SDIF_INTMASK_RTO_MASK (0x100U) -#define SDIF_INTMASK_RTO_SHIFT (8U) -#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK) -#define SDIF_INTMASK_DRTO_MASK (0x200U) -#define SDIF_INTMASK_DRTO_SHIFT (9U) -#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK) -#define SDIF_INTMASK_HTO_MASK (0x400U) -#define SDIF_INTMASK_HTO_SHIFT (10U) -#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK) -#define SDIF_INTMASK_FRUN_MASK (0x800U) -#define SDIF_INTMASK_FRUN_SHIFT (11U) -#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK) -#define SDIF_INTMASK_HLE_MASK (0x1000U) -#define SDIF_INTMASK_HLE_SHIFT (12U) -#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK) -#define SDIF_INTMASK_SBE_MASK (0x2000U) -#define SDIF_INTMASK_SBE_SHIFT (13U) -#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK) -#define SDIF_INTMASK_ACD_MASK (0x4000U) -#define SDIF_INTMASK_ACD_SHIFT (14U) -#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK) -#define SDIF_INTMASK_EBE_MASK (0x8000U) -#define SDIF_INTMASK_EBE_SHIFT (15U) -#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK) -#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U) -#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U) -#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK) -/*! @} */ - -/*! @name CMDARG - Command Argument register */ -/*! @{ */ -#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU) -#define SDIF_CMDARG_CMD_ARG_SHIFT (0U) -#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK) -/*! @} */ - -/*! @name CMD - Command register */ -/*! @{ */ -#define SDIF_CMD_CMD_INDEX_MASK (0x3FU) -#define SDIF_CMD_CMD_INDEX_SHIFT (0U) -#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK) -#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U) -#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U) -#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK) -#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U) -#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U) -#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK) -#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U) -#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) -#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK) -#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U) -#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U) -#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK) -#define SDIF_CMD_READ_WRITE_MASK (0x400U) -#define SDIF_CMD_READ_WRITE_SHIFT (10U) -#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK) -#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U) -#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U) -#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK) -#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U) -#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U) -#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK) -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U) -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) -#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK) -#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U) -#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U) -#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK) -#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U) -#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U) -#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK) -#define SDIF_CMD_CARD_NUMBER_MASK (0x1F0000U) -#define SDIF_CMD_CARD_NUMBER_SHIFT (16U) -/*! CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed - * 0b00000..Command will be execute on SDCARD 0 - * 0b00001..Command will be execute on SDCARD 1 - */ -#define SDIF_CMD_CARD_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK) -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U) -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U) -#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK) -#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U) -#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U) -#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK) -#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U) -#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U) -#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK) -#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U) -#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U) -#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK) -#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U) -#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U) -#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK) -#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U) -#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U) -#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK) -#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U) -#define SDIF_CMD_BOOT_MODE_SHIFT (27U) -#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK) -#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U) -#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U) -#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK) -#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U) -#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U) -#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK) -#define SDIF_CMD_START_CMD_MASK (0x80000000U) -#define SDIF_CMD_START_CMD_SHIFT (31U) -#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK) -/*! @} */ - -/*! @name RESP - Response register */ -/*! @{ */ -#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU) -#define SDIF_RESP_RESPONSE_SHIFT (0U) -#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK) -/*! @} */ - -/* The count of SDIF_RESP */ -#define SDIF_RESP_COUNT (4U) - -/*! @name MINTSTS - Masked Interrupt Status register */ -/*! @{ */ -#define SDIF_MINTSTS_CDET_MASK (0x1U) -#define SDIF_MINTSTS_CDET_SHIFT (0U) -#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK) -#define SDIF_MINTSTS_RE_MASK (0x2U) -#define SDIF_MINTSTS_RE_SHIFT (1U) -#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK) -#define SDIF_MINTSTS_CDONE_MASK (0x4U) -#define SDIF_MINTSTS_CDONE_SHIFT (2U) -#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK) -#define SDIF_MINTSTS_DTO_MASK (0x8U) -#define SDIF_MINTSTS_DTO_SHIFT (3U) -#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK) -#define SDIF_MINTSTS_TXDR_MASK (0x10U) -#define SDIF_MINTSTS_TXDR_SHIFT (4U) -#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK) -#define SDIF_MINTSTS_RXDR_MASK (0x20U) -#define SDIF_MINTSTS_RXDR_SHIFT (5U) -#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK) -#define SDIF_MINTSTS_RCRC_MASK (0x40U) -#define SDIF_MINTSTS_RCRC_SHIFT (6U) -#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK) -#define SDIF_MINTSTS_DCRC_MASK (0x80U) -#define SDIF_MINTSTS_DCRC_SHIFT (7U) -#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK) -#define SDIF_MINTSTS_RTO_MASK (0x100U) -#define SDIF_MINTSTS_RTO_SHIFT (8U) -#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK) -#define SDIF_MINTSTS_DRTO_MASK (0x200U) -#define SDIF_MINTSTS_DRTO_SHIFT (9U) -#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK) -#define SDIF_MINTSTS_HTO_MASK (0x400U) -#define SDIF_MINTSTS_HTO_SHIFT (10U) -#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK) -#define SDIF_MINTSTS_FRUN_MASK (0x800U) -#define SDIF_MINTSTS_FRUN_SHIFT (11U) -#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK) -#define SDIF_MINTSTS_HLE_MASK (0x1000U) -#define SDIF_MINTSTS_HLE_SHIFT (12U) -#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK) -#define SDIF_MINTSTS_SBE_MASK (0x2000U) -#define SDIF_MINTSTS_SBE_SHIFT (13U) -#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK) -#define SDIF_MINTSTS_ACD_MASK (0x4000U) -#define SDIF_MINTSTS_ACD_SHIFT (14U) -#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK) -#define SDIF_MINTSTS_EBE_MASK (0x8000U) -#define SDIF_MINTSTS_EBE_SHIFT (15U) -#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK) -#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U) -#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U) -#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK) -/*! @} */ - -/*! @name RINTSTS - Raw Interrupt Status register */ -/*! @{ */ -#define SDIF_RINTSTS_CDET_MASK (0x1U) -#define SDIF_RINTSTS_CDET_SHIFT (0U) -#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK) -#define SDIF_RINTSTS_RE_MASK (0x2U) -#define SDIF_RINTSTS_RE_SHIFT (1U) -#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK) -#define SDIF_RINTSTS_CDONE_MASK (0x4U) -#define SDIF_RINTSTS_CDONE_SHIFT (2U) -#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK) -#define SDIF_RINTSTS_DTO_MASK (0x8U) -#define SDIF_RINTSTS_DTO_SHIFT (3U) -#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK) -#define SDIF_RINTSTS_TXDR_MASK (0x10U) -#define SDIF_RINTSTS_TXDR_SHIFT (4U) -#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK) -#define SDIF_RINTSTS_RXDR_MASK (0x20U) -#define SDIF_RINTSTS_RXDR_SHIFT (5U) -#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK) -#define SDIF_RINTSTS_RCRC_MASK (0x40U) -#define SDIF_RINTSTS_RCRC_SHIFT (6U) -#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK) -#define SDIF_RINTSTS_DCRC_MASK (0x80U) -#define SDIF_RINTSTS_DCRC_SHIFT (7U) -#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK) -#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U) -#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U) -#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK) -#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U) -#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U) -#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK) -#define SDIF_RINTSTS_HTO_MASK (0x400U) -#define SDIF_RINTSTS_HTO_SHIFT (10U) -#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK) -#define SDIF_RINTSTS_FRUN_MASK (0x800U) -#define SDIF_RINTSTS_FRUN_SHIFT (11U) -#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK) -#define SDIF_RINTSTS_HLE_MASK (0x1000U) -#define SDIF_RINTSTS_HLE_SHIFT (12U) -#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK) -#define SDIF_RINTSTS_SBE_MASK (0x2000U) -#define SDIF_RINTSTS_SBE_SHIFT (13U) -#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK) -#define SDIF_RINTSTS_ACD_MASK (0x4000U) -#define SDIF_RINTSTS_ACD_SHIFT (14U) -#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK) -#define SDIF_RINTSTS_EBE_MASK (0x8000U) -#define SDIF_RINTSTS_EBE_SHIFT (15U) -#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK) -#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U) -#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U) -#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK) -/*! @} */ - -/*! @name STATUS - Status register */ -/*! @{ */ -#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U) -#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) -#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK) -#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U) -#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) -#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK) -#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U) -#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U) -#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK) -#define SDIF_STATUS_FIFO_FULL_MASK (0x8U) -#define SDIF_STATUS_FIFO_FULL_SHIFT (3U) -#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK) -#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U) -#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U) -#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK) -#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U) -#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U) -#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK) -#define SDIF_STATUS_DATA_BUSY_MASK (0x200U) -#define SDIF_STATUS_DATA_BUSY_SHIFT (9U) -#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK) -#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U) -#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) -#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK) -#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) -#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U) -#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK) -#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U) -#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U) -#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK) -#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U) -#define SDIF_STATUS_DMA_ACK_SHIFT (30U) -#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK) -#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U) -#define SDIF_STATUS_DMA_REQ_SHIFT (31U) -#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK) -/*! @} */ - -/*! @name FIFOTH - FIFO Threshold Watermark register */ -/*! @{ */ -#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU) -#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U) -#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK) -#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U) -#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U) -#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK) -#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U) -#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U) -#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK) -/*! @} */ - -/*! @name CDETECT - Card Detect register */ -/*! @{ */ -#define SDIF_CDETECT_CARD0_DETECT_MASK (0x1U) -#define SDIF_CDETECT_CARD0_DETECT_SHIFT (0U) -#define SDIF_CDETECT_CARD0_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK) -#define SDIF_CDETECT_CARD1_DETECT_MASK (0x2U) -#define SDIF_CDETECT_CARD1_DETECT_SHIFT (1U) -#define SDIF_CDETECT_CARD1_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK) -/*! @} */ - -/*! @name WRTPRT - Write Protect register */ -/*! @{ */ -#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U) -#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U) -#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK) -/*! @} */ - -/*! @name TCBCNT - Transferred CIU Card Byte Count register */ -/*! @{ */ -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) -#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK) -/*! @} */ - -/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */ -/*! @{ */ -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU) -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) -#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK) -/*! @} */ - -/*! @name DEBNCE - Debounce Count register */ -/*! @{ */ -#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU) -#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) -#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK) -/*! @} */ - -/*! @name RST_N - Hardware Reset */ -/*! @{ */ -#define SDIF_RST_N_CARD_RESET_MASK (0x1U) -#define SDIF_RST_N_CARD_RESET_SHIFT (0U) -#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK) -/*! @} */ - -/*! @name BMOD - Bus Mode register */ -/*! @{ */ -#define SDIF_BMOD_SWR_MASK (0x1U) -#define SDIF_BMOD_SWR_SHIFT (0U) -#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK) -#define SDIF_BMOD_FB_MASK (0x2U) -#define SDIF_BMOD_FB_SHIFT (1U) -#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK) -#define SDIF_BMOD_DSL_MASK (0x7CU) -#define SDIF_BMOD_DSL_SHIFT (2U) -#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK) -#define SDIF_BMOD_DE_MASK (0x80U) -#define SDIF_BMOD_DE_SHIFT (7U) -#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK) -#define SDIF_BMOD_PBL_MASK (0x700U) -#define SDIF_BMOD_PBL_SHIFT (8U) -#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK) -/*! @} */ - -/*! @name PLDMND - Poll Demand register */ -/*! @{ */ -#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU) -#define SDIF_PLDMND_PD_SHIFT (0U) -#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK) -/*! @} */ - -/*! @name DBADDR - Descriptor List Base Address register */ -/*! @{ */ -#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU) -#define SDIF_DBADDR_SDL_SHIFT (0U) -#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK) -/*! @} */ - -/*! @name IDSTS - Internal DMAC Status register */ -/*! @{ */ -#define SDIF_IDSTS_TI_MASK (0x1U) -#define SDIF_IDSTS_TI_SHIFT (0U) -#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK) -#define SDIF_IDSTS_RI_MASK (0x2U) -#define SDIF_IDSTS_RI_SHIFT (1U) -#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK) -#define SDIF_IDSTS_FBE_MASK (0x4U) -#define SDIF_IDSTS_FBE_SHIFT (2U) -#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK) -#define SDIF_IDSTS_DU_MASK (0x10U) -#define SDIF_IDSTS_DU_SHIFT (4U) -#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK) -#define SDIF_IDSTS_CES_MASK (0x20U) -#define SDIF_IDSTS_CES_SHIFT (5U) -#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK) -#define SDIF_IDSTS_NIS_MASK (0x100U) -#define SDIF_IDSTS_NIS_SHIFT (8U) -#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK) -#define SDIF_IDSTS_AIS_MASK (0x200U) -#define SDIF_IDSTS_AIS_SHIFT (9U) -#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK) -#define SDIF_IDSTS_EB_MASK (0x1C00U) -#define SDIF_IDSTS_EB_SHIFT (10U) -#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK) -#define SDIF_IDSTS_FSM_MASK (0x1E000U) -#define SDIF_IDSTS_FSM_SHIFT (13U) -#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK) -/*! @} */ - -/*! @name IDINTEN - Internal DMAC Interrupt Enable register */ -/*! @{ */ -#define SDIF_IDINTEN_TI_MASK (0x1U) -#define SDIF_IDINTEN_TI_SHIFT (0U) -#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK) -#define SDIF_IDINTEN_RI_MASK (0x2U) -#define SDIF_IDINTEN_RI_SHIFT (1U) -#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK) -#define SDIF_IDINTEN_FBE_MASK (0x4U) -#define SDIF_IDINTEN_FBE_SHIFT (2U) -#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK) -#define SDIF_IDINTEN_DU_MASK (0x10U) -#define SDIF_IDINTEN_DU_SHIFT (4U) -#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK) -#define SDIF_IDINTEN_CES_MASK (0x20U) -#define SDIF_IDINTEN_CES_SHIFT (5U) -#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK) -#define SDIF_IDINTEN_NIS_MASK (0x100U) -#define SDIF_IDINTEN_NIS_SHIFT (8U) -#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK) -#define SDIF_IDINTEN_AIS_MASK (0x200U) -#define SDIF_IDINTEN_AIS_SHIFT (9U) -#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK) -/*! @} */ - -/*! @name DSCADDR - Current Host Descriptor Address register */ -/*! @{ */ -#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU) -#define SDIF_DSCADDR_HDA_SHIFT (0U) -#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK) -/*! @} */ - -/*! @name BUFADDR - Current Buffer Descriptor Address register */ -/*! @{ */ -#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU) -#define SDIF_BUFADDR_HBA_SHIFT (0U) -#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK) -/*! @} */ - -/*! @name CARDTHRCTL - Card Threshold Control */ -/*! @{ */ -#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U) -#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U) -#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK) -#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U) -#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U) -#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK) -#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U) -#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U) -#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK) -/*! @} */ - -/*! @name BACKENDPWR - Power control */ -/*! @{ */ -#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U) -#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U) -#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK) -/*! @} */ - -/*! @name FIFO - SDIF FIFO */ -/*! @{ */ -#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU) -#define SDIF_FIFO_DATA_SHIFT (0U) -#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK) -/*! @} */ - -/* The count of SDIF_FIFO */ -#define SDIF_FIFO_COUNT (64U) - - -/*! - * @} - */ /* end of group SDIF_Register_Masks */ - - -/* SDIF - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral SDIF base address */ - #define SDIF_BASE (0x5009B000u) - /** Peripheral SDIF base address */ - #define SDIF_BASE_NS (0x4009B000u) - /** Peripheral SDIF base pointer */ - #define SDIF ((SDIF_Type *)SDIF_BASE) - /** Peripheral SDIF base pointer */ - #define SDIF_NS ((SDIF_Type *)SDIF_BASE_NS) - /** Array initializer of SDIF peripheral base addresses */ - #define SDIF_BASE_ADDRS { SDIF_BASE } - /** Array initializer of SDIF peripheral base pointers */ - #define SDIF_BASE_PTRS { SDIF } - /** Array initializer of SDIF peripheral base addresses */ - #define SDIF_BASE_ADDRS_NS { SDIF_BASE_NS } - /** Array initializer of SDIF peripheral base pointers */ - #define SDIF_BASE_PTRS_NS { SDIF_NS } -#else - /** Peripheral SDIF base address */ - #define SDIF_BASE (0x4009B000u) - /** Peripheral SDIF base pointer */ - #define SDIF ((SDIF_Type *)SDIF_BASE) - /** Array initializer of SDIF peripheral base addresses */ - #define SDIF_BASE_ADDRS { SDIF_BASE } - /** Array initializer of SDIF peripheral base pointers */ - #define SDIF_BASE_PTRS { SDIF } -#endif -/** Interrupt vectors for the SDIF peripheral type */ -#define SDIF_IRQS { SDIO_IRQn } - -/*! - * @} - */ /* end of group SDIF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer - * @{ - */ - -/** SPI - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[1024]; - __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ - __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ - __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ - __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ - __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ - __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ - uint8_t RESERVED_2[2516]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_6[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_7[440]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} SPI_Type; - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/*! @name CFG - SPI Configuration register */ -/*! @{ */ -#define SPI_CFG_ENABLE_MASK (0x1U) -#define SPI_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - SPI enable. - * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. - * 0b1..Enabled. The SPI is enabled for operation. - */ -#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) -#define SPI_CFG_MASTER_MASK (0x4U) -#define SPI_CFG_MASTER_SHIFT (2U) -/*! MASTER - Master mode select. - * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. - * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. - */ -#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) -#define SPI_CFG_LSBF_MASK (0x8U) -#define SPI_CFG_LSBF_SHIFT (3U) -/*! LSBF - LSB First mode enable. - * 0b0..Standard. Data is transmitted and received in standard MSB first order. - * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). - */ -#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) -#define SPI_CFG_CPHA_MASK (0x10U) -#define SPI_CFG_CPHA_SHIFT (4U) -/*! CPHA - Clock Phase select. - * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge. - * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge. - */ -#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) -#define SPI_CFG_CPOL_MASK (0x20U) -#define SPI_CFG_CPOL_SHIFT (5U) -/*! CPOL - Clock Polarity select. - * 0b0..Low. The rest state of the clock (between transfers) is low. - * 0b1..High. The rest state of the clock (between transfers) is high. - */ -#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) -#define SPI_CFG_LOOP_MASK (0x80U) -#define SPI_CFG_LOOP_SHIFT (7U) -/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. - * 0b0..Disabled. - * 0b1..Enabled. - */ -#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) -#define SPI_CFG_SPOL0_MASK (0x100U) -#define SPI_CFG_SPOL0_SHIFT (8U) -/*! SPOL0 - SSEL0 Polarity select. - * 0b0..Low. The SSEL0 pin is active low. - * 0b1..High. The SSEL0 pin is active high. - */ -#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) -#define SPI_CFG_SPOL1_MASK (0x200U) -#define SPI_CFG_SPOL1_SHIFT (9U) -/*! SPOL1 - SSEL1 Polarity select. - * 0b0..Low. The SSEL1 pin is active low. - * 0b1..High. The SSEL1 pin is active high. - */ -#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) -#define SPI_CFG_SPOL2_MASK (0x400U) -#define SPI_CFG_SPOL2_SHIFT (10U) -/*! SPOL2 - SSEL2 Polarity select. - * 0b0..Low. The SSEL2 pin is active low. - * 0b1..High. The SSEL2 pin is active high. - */ -#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) -#define SPI_CFG_SPOL3_MASK (0x800U) -#define SPI_CFG_SPOL3_SHIFT (11U) -/*! SPOL3 - SSEL3 Polarity select. - * 0b0..Low. The SSEL3 pin is active low. - * 0b1..High. The SSEL3 pin is active high. - */ -#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) -/*! @} */ - -/*! @name DLY - SPI Delay register */ -/*! @{ */ -#define SPI_DLY_PRE_DELAY_MASK (0xFU) -#define SPI_DLY_PRE_DELAY_SHIFT (0U) -#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) -#define SPI_DLY_POST_DELAY_MASK (0xF0U) -#define SPI_DLY_POST_DELAY_SHIFT (4U) -#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) -#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) -#define SPI_DLY_FRAME_DELAY_SHIFT (8U) -#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) -#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) -#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) -#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) -/*! @} */ - -/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ -/*! @{ */ -#define SPI_STAT_SSA_MASK (0x10U) -#define SPI_STAT_SSA_SHIFT (4U) -#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) -#define SPI_STAT_SSD_MASK (0x20U) -#define SPI_STAT_SSD_SHIFT (5U) -#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) -#define SPI_STAT_STALLED_MASK (0x40U) -#define SPI_STAT_STALLED_SHIFT (6U) -#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) -#define SPI_STAT_ENDTRANSFER_MASK (0x80U) -#define SPI_STAT_ENDTRANSFER_SHIFT (7U) -#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) -#define SPI_STAT_MSTIDLE_MASK (0x100U) -#define SPI_STAT_MSTIDLE_SHIFT (8U) -#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ -#define SPI_INTENSET_SSAEN_MASK (0x10U) -#define SPI_INTENSET_SSAEN_SHIFT (4U) -/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. - * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. - * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. - */ -#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) -#define SPI_INTENSET_SSDEN_MASK (0x20U) -#define SPI_INTENSET_SSDEN_SHIFT (5U) -/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. - * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. - * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. - */ -#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) -#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) -#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) -/*! MSTIDLEEN - Master idle interrupt enable. - * 0b0..No interrupt will be generated when the SPI master function is idle. - * 0b1..An interrupt will be generated when the SPI master function is fully idle. - */ -#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) -/*! @} */ - -/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ -/*! @{ */ -#define SPI_INTENCLR_SSAEN_MASK (0x10U) -#define SPI_INTENCLR_SSAEN_SHIFT (4U) -#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) -#define SPI_INTENCLR_SSDEN_MASK (0x20U) -#define SPI_INTENCLR_SSDEN_SHIFT (5U) -#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) -#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) -#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) -#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) -/*! @} */ - -/*! @name DIV - SPI clock Divider */ -/*! @{ */ -#define SPI_DIV_DIVVAL_MASK (0xFFFFU) -#define SPI_DIV_DIVVAL_SHIFT (0U) -#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - SPI Interrupt Status */ -/*! @{ */ -#define SPI_INTSTAT_SSA_MASK (0x10U) -#define SPI_INTSTAT_SSA_SHIFT (4U) -#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) -#define SPI_INTSTAT_SSD_MASK (0x20U) -#define SPI_INTSTAT_SSD_SHIFT (5U) -#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) -#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) -#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) -#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ -#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) -#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) -#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) -#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) -#define SPI_FIFOCFG_SIZE_MASK (0x30U) -#define SPI_FIFOCFG_SIZE_SHIFT (4U) -#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) -#define SPI_FIFOCFG_DMATX_MASK (0x1000U) -#define SPI_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) -#define SPI_FIFOCFG_DMARX_MASK (0x2000U) -#define SPI_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) -#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) -#define SPI_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) -#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) -#define SPI_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) -#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) -#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) -#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) -#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) -#define SPI_FIFOCFG_POPDBG_MASK (0x40000U) -#define SPI_FIFOCFG_POPDBG_SHIFT (18U) -/*! POPDBG - Pop FIFO for debug reads. - * 0b0..Debug reads of the FIFO do not pop the FIFO. - * 0b1..A debug read will cause the FIFO to pop. - */ -#define SPI_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ -#define SPI_FIFOSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOSTAT_TXERR_SHIFT (0U) -#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) -#define SPI_FIFOSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOSTAT_RXERR_SHIFT (1U) -#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) -#define SPI_FIFOSTAT_PERINT_MASK (0x8U) -#define SPI_FIFOSTAT_PERINT_SHIFT (3U) -#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) -#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) -#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) -#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) -#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) -#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) -#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) -#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) -#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) -#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) -#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ -#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) -#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) -#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) -#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) -#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) -#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) -#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ -#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) -#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) -#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) -#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) -#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - */ -#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) -#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ -#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) -#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) -#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) -#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) -#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) -#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) -#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) -#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ -#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) -#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) -#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) -#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) -#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) -#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) -#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) -#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) -#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ -#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) -#define SPI_FIFOWR_TXDATA_SHIFT (0U) -#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) -#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) -#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) -/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL0 asserted. - * 0b1..SSEL0 not asserted. - */ -#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) -#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) -#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) -/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL1 asserted. - * 0b1..SSEL1 not asserted. - */ -#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) -#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) -#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) -/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL2 asserted. - * 0b1..SSEL2 not asserted. - */ -#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) -#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) -#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) -/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL3 asserted. - * 0b1..SSEL3 not asserted. - */ -#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) -#define SPI_FIFOWR_EOT_MASK (0x100000U) -#define SPI_FIFOWR_EOT_SHIFT (20U) -/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register. - * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. - * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. - */ -#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) -#define SPI_FIFOWR_EOF_MASK (0x200000U) -#define SPI_FIFOWR_EOF_SHIFT (21U) -/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. - * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. - * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted. - */ -#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) -#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) -#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) -/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA. - * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received. - * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. - */ -#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) -#define SPI_FIFOWR_LEN_MASK (0xF000000U) -#define SPI_FIFOWR_LEN_SHIFT (24U) -#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ -#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORD_RXDATA_SHIFT (0U) -#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) -#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) -#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) -#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) -#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) -#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) -#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) -#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) -#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) -#define SPI_FIFORD_SOT_MASK (0x100000U) -#define SPI_FIFORD_SOT_SHIFT (20U) -#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ -#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) -#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) -#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) -#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) -#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) -#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) -#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) -#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) -#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ -#define SPI_ID_APERTURE_MASK (0xFFU) -#define SPI_ID_APERTURE_SHIFT (0U) -#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) -#define SPI_ID_MINOR_REV_MASK (0xF00U) -#define SPI_ID_MINOR_REV_SHIFT (8U) -#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) -#define SPI_ID_MAJOR_REV_MASK (0xF000U) -#define SPI_ID_MAJOR_REV_SHIFT (12U) -#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) -#define SPI_ID_ID_MASK (0xFFFF0000U) -#define SPI_ID_ID_SHIFT (16U) -#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SPI_Register_Masks */ - - -/* SPI - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral SPI0 base address */ - #define SPI0_BASE (0x50086000u) - /** Peripheral SPI0 base address */ - #define SPI0_BASE_NS (0x40086000u) - /** Peripheral SPI0 base pointer */ - #define SPI0 ((SPI_Type *)SPI0_BASE) - /** Peripheral SPI0 base pointer */ - #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) - /** Peripheral SPI1 base address */ - #define SPI1_BASE (0x50087000u) - /** Peripheral SPI1 base address */ - #define SPI1_BASE_NS (0x40087000u) - /** Peripheral SPI1 base pointer */ - #define SPI1 ((SPI_Type *)SPI1_BASE) - /** Peripheral SPI1 base pointer */ - #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) - /** Peripheral SPI2 base address */ - #define SPI2_BASE (0x50088000u) - /** Peripheral SPI2 base address */ - #define SPI2_BASE_NS (0x40088000u) - /** Peripheral SPI2 base pointer */ - #define SPI2 ((SPI_Type *)SPI2_BASE) - /** Peripheral SPI2 base pointer */ - #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS) - /** Peripheral SPI3 base address */ - #define SPI3_BASE (0x50089000u) - /** Peripheral SPI3 base address */ - #define SPI3_BASE_NS (0x40089000u) - /** Peripheral SPI3 base pointer */ - #define SPI3 ((SPI_Type *)SPI3_BASE) - /** Peripheral SPI3 base pointer */ - #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) - /** Peripheral SPI4 base address */ - #define SPI4_BASE (0x5008A000u) - /** Peripheral SPI4 base address */ - #define SPI4_BASE_NS (0x4008A000u) - /** Peripheral SPI4 base pointer */ - #define SPI4 ((SPI_Type *)SPI4_BASE) - /** Peripheral SPI4 base pointer */ - #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) - /** Peripheral SPI5 base address */ - #define SPI5_BASE (0x50096000u) - /** Peripheral SPI5 base address */ - #define SPI5_BASE_NS (0x40096000u) - /** Peripheral SPI5 base pointer */ - #define SPI5 ((SPI_Type *)SPI5_BASE) - /** Peripheral SPI5 base pointer */ - #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS) - /** Peripheral SPI6 base address */ - #define SPI6_BASE (0x50097000u) - /** Peripheral SPI6 base address */ - #define SPI6_BASE_NS (0x40097000u) - /** Peripheral SPI6 base pointer */ - #define SPI6 ((SPI_Type *)SPI6_BASE) - /** Peripheral SPI6 base pointer */ - #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) - /** Peripheral SPI7 base address */ - #define SPI7_BASE (0x50098000u) - /** Peripheral SPI7 base address */ - #define SPI7_BASE_NS (0x40098000u) - /** Peripheral SPI7 base pointer */ - #define SPI7 ((SPI_Type *)SPI7_BASE) - /** Peripheral SPI7 base pointer */ - #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) - /** Peripheral SPI8 base address */ - #define SPI8_BASE (0x5009F000u) - /** Peripheral SPI8 base address */ - #define SPI8_BASE_NS (0x4009F000u) - /** Peripheral SPI8 base pointer */ - #define SPI8 ((SPI_Type *)SPI8_BASE) - /** Peripheral SPI8 base pointer */ - #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS } -#else - /** Peripheral SPI0 base address */ - #define SPI0_BASE (0x40086000u) - /** Peripheral SPI0 base pointer */ - #define SPI0 ((SPI_Type *)SPI0_BASE) - /** Peripheral SPI1 base address */ - #define SPI1_BASE (0x40087000u) - /** Peripheral SPI1 base pointer */ - #define SPI1 ((SPI_Type *)SPI1_BASE) - /** Peripheral SPI2 base address */ - #define SPI2_BASE (0x40088000u) - /** Peripheral SPI2 base pointer */ - #define SPI2 ((SPI_Type *)SPI2_BASE) - /** Peripheral SPI3 base address */ - #define SPI3_BASE (0x40089000u) - /** Peripheral SPI3 base pointer */ - #define SPI3 ((SPI_Type *)SPI3_BASE) - /** Peripheral SPI4 base address */ - #define SPI4_BASE (0x4008A000u) - /** Peripheral SPI4 base pointer */ - #define SPI4 ((SPI_Type *)SPI4_BASE) - /** Peripheral SPI5 base address */ - #define SPI5_BASE (0x40096000u) - /** Peripheral SPI5 base pointer */ - #define SPI5 ((SPI_Type *)SPI5_BASE) - /** Peripheral SPI6 base address */ - #define SPI6_BASE (0x40097000u) - /** Peripheral SPI6 base pointer */ - #define SPI6 ((SPI_Type *)SPI6_BASE) - /** Peripheral SPI7 base address */ - #define SPI7_BASE (0x40098000u) - /** Peripheral SPI7 base pointer */ - #define SPI7 ((SPI_Type *)SPI7_BASE) - /** Peripheral SPI8 base address */ - #define SPI8_BASE (0x4009F000u) - /** Peripheral SPI8 base pointer */ - #define SPI8 ((SPI_Type *)SPI8_BASE) - /** Array initializer of SPI peripheral base addresses */ - #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } - /** Array initializer of SPI peripheral base pointers */ - #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } -#endif -/** Interrupt vectors for the SPI peripheral type */ -#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, LSPI_HS_IRQn } - -/*! - * @} - */ /* end of group SPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer - * @{ - */ - -/** SYSCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */ - uint8_t RESERVED_1[36]; - __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ - __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ - __IO uint32_t CPU1TCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */ - uint8_t RESERVED_2[4]; - __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ - uint8_t RESERVED_3[180]; - union { /* offset: 0x100 */ - struct { /* offset: 0x100 */ - __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */ - __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */ - __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */ - } PRESETCTRL; - __IO uint32_t PRESETCTRLX[3]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */ - }; - uint8_t RESERVED_4[20]; - __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */ - uint8_t RESERVED_5[20]; - __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset contro clearl register, array offset: 0x140, array step: 0x4 */ - uint8_t RESERVED_6[20]; - __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */ - uint8_t RESERVED_7[156]; - union { /* offset: 0x200 */ - struct { /* offset: 0x200 */ - __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */ - __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */ - __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */ - } AHBCLKCTRL; - __IO uint32_t AHBCLKCTRLX[3]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */ - }; - uint8_t RESERVED_8[20]; - __IO uint32_t AHBCLKCTRLSET[3]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */ - uint8_t RESERVED_9[20]; - __IO uint32_t AHBCLKCTRLCLR[3]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_10[20]; - union { /* offset: 0x260 */ - struct { /* offset: 0x260 */ - __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */ - __IO uint32_t SYSTICKCLKSEL1; /**< System Tick Timer for CPU1 source select, offset: 0x264 */ - } SYSTICKCLKSEL; - __IO uint32_t SYSTICKCLKSELX[2]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */ - }; - __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */ - union { /* offset: 0x26C */ - struct { /* offset: 0x26C */ - __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */ - __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */ - __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */ - __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */ - __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */ - } CTIMERCLKSEL; - __IO uint32_t CTIMERCLKSELX[5]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */ - }; - __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */ - __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */ - __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */ - uint8_t RESERVED_11[4]; - __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */ - __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */ - uint8_t RESERVED_12[12]; - __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ - __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ - __IO uint32_t USB1CLKSEL; /**< HS USB clock source select - NOT USED, offset: 0x2AC */ - union { /* offset: 0x2B0 */ - struct { /* offset: 0x2B0 */ - __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */ - __IO uint32_t FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */ - __IO uint32_t FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */ - __IO uint32_t FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */ - __IO uint32_t FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */ - __IO uint32_t FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */ - __IO uint32_t FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */ - __IO uint32_t FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */ - } FCCLKSEL; - __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */ - }; - __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */ - uint8_t RESERVED_13[12]; - __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ - uint8_t RESERVED_14[12]; - __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ - uint8_t RESERVED_15[4]; - __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ - uint8_t RESERVED_16[4]; - __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */ - __IO uint32_t SYSTICKCLKDIV1; /**< System Tick Timer divider for CPU1, offset: 0x304 */ - __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ - uint8_t RESERVED_17[20]; - union { /* offset: 0x320 */ - struct { /* offset: 0x320 */ - __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */ - __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */ - __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */ - __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */ - __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */ - __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */ - __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */ - __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */ - } FLEXFRGCTRL; - __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */ - }; - uint8_t RESERVED_18[64]; - __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ - __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ - __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ - __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ - uint8_t RESERVED_19[4]; - __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ - __IO uint32_t USB0CLKDIV; /**< USB0 Clock divider, offset: 0x398 */ - uint8_t RESERVED_20[16]; - __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ - uint8_t RESERVED_21[4]; - __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ - uint8_t RESERVED_22[4]; - __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ - uint8_t RESERVED_23[4]; - __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */ - uint8_t RESERVED_24[52]; - __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */ - __IO uint32_t FMCCR; /**< FMC configuration register - INTERNAL USE ONLY, offset: 0x400 */ - uint8_t RESERVED_25[8]; - __IO uint32_t USB0CLKCTRL; /**< USB0 clock control, offset: 0x40C */ - __I uint32_t USB0CLKSTAT; /**< USB0 clock status, offset: 0x410 */ - uint8_t RESERVED_26[8]; - __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */ - __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ - __IO uint32_t USB1CLKCTRL; /**< USB1 clock control, offset: 0x424 */ - __I uint32_t USB1CLKSTAT; /**< USB1 clock status, offset: 0x428 */ - uint8_t RESERVED_27[36]; - __IO uint32_t FLASHBANKENABLE; /**< Flash Banks control, offset: 0x450 */ - uint8_t RESERVED_28[12]; - __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */ - uint8_t RESERVED_29[252]; - __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ - __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */ - __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */ - __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */ - __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */ - uint8_t RESERVED_30[12]; - __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */ - __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */ - __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */ - __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ - __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */ - __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */ - uint8_t RESERVED_31[52]; - __IO uint32_t EFUSECLKCTRL; /**< eFUSE controller clock enable, offset: 0x5CC */ - uint8_t RESERVED_32[176]; - __IO uint32_t STARTER[2]; /**< Start logic wake-up enable register, array offset: 0x680, array step: 0x4 */ - uint8_t RESERVED_33[24]; - __O uint32_t STARTERSET[2]; /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */ - uint8_t RESERVED_34[24]; - __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTER, array offset: 0x6C0, array step: 0x4 */ - uint8_t RESERVED_35[184]; - __IO uint32_t HARDWARESLEEP; /**< Hardware Sleep control, offset: 0x780 */ - uint8_t RESERVED_36[124]; - __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ - __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ - __IO uint32_t CPSTACK; /**< Coprocessor Stack Address, offset: 0x808 */ - __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */ - uint8_t RESERVED_37[240]; - __IO uint32_t DICE_REG0; /**< Composite Device Identifier, offset: 0x900 */ - __IO uint32_t DICE_REG1; /**< Composite Device Identifier, offset: 0x904 */ - __IO uint32_t DICE_REG2; /**< Composite Device Identifier, offset: 0x908 */ - __IO uint32_t DICE_REG3; /**< Composite Device Identifier, offset: 0x90C */ - __IO uint32_t DICE_REG4; /**< Composite Device Identifier, offset: 0x910 */ - __IO uint32_t DICE_REG5; /**< Composite Device Identifier, offset: 0x914 */ - __IO uint32_t DICE_REG6; /**< Composite Device Identifier, offset: 0x918 */ - __IO uint32_t DICE_REG7; /**< Composite Device Identifier, offset: 0x91C */ - uint8_t RESERVED_38[248]; - __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */ - uint8_t RESERVED_39[244]; - __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ - __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ - uint8_t RESERVED_40[748]; - __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ - __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */ - uint8_t RESERVED_41[404]; - __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers -- FOR INTERNAl USE ONLY, offset: 0xFA0 */ - __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY, offset: 0xFA4 */ - __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY, offset: 0xFA8 */ - uint8_t RESERVED_42[4]; - __O uint32_t CODESECURITYPROTTEST; /**< Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY, offset: 0xFB0 */ - __O uint32_t CODESECURITYPROTCPU0; /**< Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY, offset: 0xFB4 */ - __O uint32_t CODESECURITYPROTCPU1; /**< Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY, offset: 0xFB8 */ - __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY, offset: 0xFBC */ - __IO uint32_t DEBUG_AUTH_SCRATCH; /**< Debug authentication scratch registers -- FOR INTERNAL USE ONLY, offset: 0xFC0 */ - uint8_t RESERVED_43[16]; - __IO uint32_t CPUCFG; /**< CPUs configuration register, offset: 0xFD4 */ - uint8_t RESERVED_44[20]; - __IO uint32_t PERIPHENCFG; /**< peripheral enable configuration -- FOR INTERNAL USE ONLY, offset: 0xFEC */ - uint8_t RESERVED_45[8]; - __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ - __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ -} SYSCON_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Register_Masks SYSCON Register Masks - * @{ - */ - -/*! @name MEMORYREMAP - Memory Remap control register */ -/*! @{ */ -#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) -#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) -/*! MAP - Select the location of the vector table :. - * 0b00..Vector Table in ROM. - * 0b01..Vector Table in RAM. - * 0b10..Vector Table in Flash. - * 0b11..Vector Table in Flash. - */ -#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK) -/*! @} */ - -/*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */ -/*! @{ */ -#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_MASK (0x3U) -#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_SHIFT (0U) -#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_MASK) -#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_MASK (0xCU) -#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_SHIFT (2U) -#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_MASK) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_MASK (0x30U) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_SHIFT (4U) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_MASK) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_MASK (0xC0U) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_SHIFT (6U) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_MASK) -#define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0x300U) -#define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (8U) -#define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK) -#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U) -#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U) -#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK (0x3000U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT (12U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK (0xC000U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT (14U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK) -#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U) -#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U) -#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK) -#define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U) -#define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U) -#define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK) -#define SYSCON_AHBMATPRIO_PRI_SHA2_MASK (0x300000U) -#define SYSCON_AHBMATPRIO_PRI_SHA2_SHIFT (20U) -#define SYSCON_AHBMATPRIO_PRI_SHA2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SHA2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SHA2_MASK) -#define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC00000U) -#define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (22U) -#define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) -#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U) -#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U) -#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) -/*! @} */ - -/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ -/*! @{ */ -#define SYSCON_CPU0STCKCAL_CAL_MASK (0xFFFFFFU) -#define SYSCON_CPU0STCKCAL_CAL_SHIFT (0U) -#define SYSCON_CPU0STCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_CAL_SHIFT)) & SYSCON_CPU0STCKCAL_CAL_MASK) -#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) -#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) -#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) -#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ -/*! @{ */ -#define SYSCON_CPU0NSTCKCAL_CAL_MASK (0xFFFFFFU) -#define SYSCON_CPU0NSTCKCAL_CAL_SHIFT (0U) -#define SYSCON_CPU0NSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_CAL_SHIFT)) & SYSCON_CPU0NSTCKCAL_CAL_MASK) -#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) -#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) -#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) -#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name CPU1TCKCAL - System tick calibration for CPU1 */ -/*! @{ */ -#define SYSCON_CPU1TCKCAL_CAL_MASK (0xFFFFFFU) -#define SYSCON_CPU1TCKCAL_CAL_SHIFT (0U) -#define SYSCON_CPU1TCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_CAL_SHIFT)) & SYSCON_CPU1TCKCAL_CAL_MASK) -#define SYSCON_CPU1TCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU1TCKCAL_SKEW_SHIFT (24U) -#define SYSCON_CPU1TCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_SKEW_SHIFT)) & SYSCON_CPU1TCKCAL_SKEW_MASK) -#define SYSCON_CPU1TCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU1TCKCAL_NOREF_SHIFT (25U) -#define SYSCON_CPU1TCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_NOREF_SHIFT)) & SYSCON_CPU1TCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name NMISRC - NMI Source Select */ -/*! @{ */ -#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) -#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) -#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) -#define SYSCON_NMISRC_IRQCPU1_MASK (0x3F00U) -#define SYSCON_NMISRC_IRQCPU1_SHIFT (8U) -#define SYSCON_NMISRC_IRQCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK) -#define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U) -#define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U) -#define SYSCON_NMISRC_NMIENCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK) -#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) -#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) -#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) -/*! @} */ - -/*! @name PRESETCTRL0 - Peripheral reset control 0 */ -/*! @{ */ -#define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U) -/*! ROM_RST - ROM reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK) -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) -/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) -/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U) -/*! SRAM_CTRL3_RST - SRAM Controller 3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK) -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U) -/*! SRAM_CTRL4_RST - SRAM Controller 4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK) -#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) -/*! FLASH_RST - Flash controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) -#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) -/*! FMC_RST - FMC controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) -#define SYSCON_PRESETCTRL0_MUX0_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL0_MUX0_RST_SHIFT (11U) -/*! MUX0_RST - Input Mux 0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_MUX0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX0_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX0_RST_MASK) -#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) -/*! IOCON_RST - I/O controller reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) -#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) -/*! GPIO0_RST - GPIO0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) -#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) -/*! GPIO1_RST - GPIO1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) -#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U) -/*! GPIO2_RST - GPIO2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) -#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U) -/*! GPIO3_RST - GPIO3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) -#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) -/*! PINT_RST - Pin interrupt (PINT) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) -#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) -/*! GINT_RST - Group interrupt (GINT) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) -#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) -/*! DMA0_RST - DMA0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) -#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) -/*! CRCGEN_RST - CRCGEN reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) -#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) -/*! WWDT_RST - Watchdog Timer reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) -#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) -#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) -/*! RTC_RST - Real Time Clock (RTC) reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) -#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) -/*! MAILBOX_RST - Inter CPU communication Mailbox reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) -#define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U) -/*! ADC_RST - ADC reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRL1 - Peripheral reset control 1 */ -/*! @{ */ -#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) -#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) -/*! MRT_RST - MRT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) -#define SYSCON_PRESETCTRL1_OSTIMER0_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL1_OSTIMER0_RST_SHIFT (1U) -/*! OSTIMER0_RST - OS Timer 0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_OSTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER0_RST_MASK) -#define SYSCON_PRESETCTRL1_SCT0_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL1_SCT0_RST_SHIFT (2U) -/*! SCT0_RST - SCT0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT0_RST_MASK) -#define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT (6U) -/*! SCTIPU_RST - SCTIPU reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_SCTIPU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK) -#define SYSCON_PRESETCTRL1_UTICK0_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL1_UTICK0_RST_SHIFT (10U) -/*! UTICK0_RST - UTICK0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK0_RST_MASK) -#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) -/*! FC0_RST - FC0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) -#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) -/*! FC1_RST - FC1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) -#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) -/*! FC2_RST - FC2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) -#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) -/*! FC3_RST - FC3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) -#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) -/*! FC4_RST - FC4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) -#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) -/*! FC5_RST - FC5 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) -#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) -/*! FC6_RST - FC6 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) -#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) -/*! FC7_RST - FC7 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) -#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) -/*! TIMER2_RST - Timer 2 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) -#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) -#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) -/*! USB0_DEV_RST - USB0 DEV reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) -#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) -/*! TIMER0_RST - Timer 0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) -#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) -/*! TIMER1_RST - Timer 1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) -#define SYSCON_PRESETCTRL1_PVT_RST_MASK (0x10000000U) -#define SYSCON_PRESETCTRL1_PVT_RST_SHIFT (28U) -/*! PVT_RST - PVT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_PVT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_PVT_RST_SHIFT)) & SYSCON_PRESETCTRL1_PVT_RST_MASK) -#define SYSCON_PRESETCTRL1_EZHA_RST_MASK (0x40000000U) -#define SYSCON_PRESETCTRL1_EZHA_RST_SHIFT (30U) -/*! EZHA_RST - EZH a reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_EZHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHA_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHA_RST_MASK) -#define SYSCON_PRESETCTRL1_EZHB_RST_MASK (0x80000000U) -#define SYSCON_PRESETCTRL1_EZHB_RST_SHIFT (31U) -/*! EZHB_RST - EZH b reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_EZHB_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHB_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHB_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRL2 - Peripheral reset control 2 */ -/*! @{ */ -#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) -/*! DMA1_RST - DMA1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) -#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) -/*! COMP_RST - Comparator reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) -#define SYSCON_PRESETCTRL2_SDIO_RST_MASK (0x8U) -#define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT (3U) -/*! SDIO_RST - SDIO reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK) -#define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U) -/*! USB1_HOST_RST - USB1 Host reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK) -#define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U) -#define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U) -/*! USB1_DEV_RST - USB1 dev reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK) -#define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U) -#define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U) -/*! USB1_RAM_RST - USB1 RAM reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK) -#define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U) -/*! USB1_PHY_RST - USB1 PHY reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK) -#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) -/*! FREQME_RST - Frequency meter reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) -#define SYSCON_PRESETCTRL2_GPIO4_RST_MASK (0x200U) -#define SYSCON_PRESETCTRL2_GPIO4_RST_SHIFT (9U) -/*! GPIO4_RST - GPIO4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO4_RST_MASK) -#define SYSCON_PRESETCTRL2_GPIO5_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL2_GPIO5_RST_SHIFT (10U) -/*! GPIO5_RST - GPIO5 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO5_RST_MASK) -#define SYSCON_PRESETCTRL2_OTP_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL2_OTP_RST_SHIFT (12U) -/*! OTP_RST - OTP reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_OTP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL2_OTP_RST_MASK) -#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) -/*! RNG_RST - RNG reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) -#define SYSCON_PRESETCTRL2_MUX1_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL2_MUX1_RST_SHIFT (14U) -/*! MUX1_RST - Peripheral Input Mux 1 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_MUX1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_MUX1_RST_SHIFT)) & SYSCON_PRESETCTRL2_MUX1_RST_MASK) -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) -/*! USB0_HOSTM_RST - USB0 Host Master reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) -/*! USB0_HOSTS_RST - USB0 Host Slave reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) -#define SYSCON_PRESETCTRL2_HASH0_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL2_HASH0_RST_SHIFT (18U) -/*! HASH0_RST - HASH0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_HASH0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH0_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH0_RST_MASK) -#define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U) -/*! PQ_RST - Power Quad reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK) -#define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U) -/*! PLULUT_RST - PLU LUT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK) -#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) -/*! TIMER3_RST - Timer 3 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) -#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) -/*! TIMER4_RST - Timer 4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) -#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) -#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) -/*! PUF_RST - PUF reset control reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) -#define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U) -#define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U) -/*! CASPER_RST - Casper reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK) -#define SYSCON_PRESETCTRL2_CAPT0_RST_MASK (0x2000000U) -#define SYSCON_PRESETCTRL2_CAPT0_RST_SHIFT (25U) -/*! CAPT0_RST - CAPT0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_CAPT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CAPT0_RST_SHIFT)) & SYSCON_PRESETCTRL2_CAPT0_RST_MASK) -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U) -/*! ANALOG_CTRL_RST - analog control reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK) -#define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U) -#define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U) -/*! HS_LSPI_RST - HS LSPI reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK) -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) -/*! GPIO_SEC_RST - GPIO secure reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) -/*! GPIO_SEC_INT_RST - GPIO secure int reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK) -/*! @} */ - -/*! @name PRESETCTRLX - Peripheral reset control register */ -/*! @{ */ -#define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLX_DATA_SHIFT (0U) -#define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLX */ -#define SYSCON_PRESETCTRLX_COUNT (3U) - -/*! @name PRESETCTRLSET - Peripheral reset control set register */ -/*! @{ */ -#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) -#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLSET */ -#define SYSCON_PRESETCTRLSET_COUNT (3U) - -/*! @name PRESETCTRLCLR - Peripheral reset contro clearl register */ -/*! @{ */ -#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) -#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLCLR */ -#define SYSCON_PRESETCTRLCLR_COUNT (3U) - -/*! @name SWR_RESET - generate a software_reset */ -/*! @{ */ -#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) -#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) -/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. - * 0b01011010000000000000000000000001..Generate a software reset. - * 0b00000000000000000000000000000000..Bloc is not reset. - */ -#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL0 - AHB Clock control 0 */ -/*! @{ */ -#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) -#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) -/*! ROM - Enables the clock for the ROM. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) -/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) -/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U) -/*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U) -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U) -/*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK) -#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) -#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) -/*! FLASH - Enables the clock for the Flash controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) -#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) -#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) -/*! FMC - Enables the clock for the FMC controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) -#define SYSCON_AHBCLKCTRL0_MUX0_MASK (0x800U) -#define SYSCON_AHBCLKCTRL0_MUX0_SHIFT (11U) -/*! MUX0 - Enables the clock for the Input Mux 0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX0_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX0_MASK) -#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) -/*! IOCON - Enables the clock for the I/O controller. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) -#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) -/*! GPIO0 - Enables the clock for the GPIO0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) -#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) -/*! GPIO1 - Enables the clock for the GPIO1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) -#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U) -/*! GPIO2 - Enables the clock for the GPIO2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) -#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U) -/*! GPIO3 - Enables the clock for the GPIO3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) -#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) -/*! PINT - Enables the clock for the Pin interrupt (PINT). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) -#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) -/*! GINT - Enables the clock for the Group interrupt (GINT). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) -#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) -/*! DMA0 - Enables the clock for the DMA0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) -#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) -/*! CRCGEN - Enables the clock for the CRCGEN. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) -#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) -/*! WWDT - Enables the clock for the Watchdog Timer. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) -#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) -/*! RTC - Enables the clock for the Real Time Clock (RTC). - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) -#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) -/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) -#define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U) -/*! ADC - Enables the clock for the ADC. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL1 - AHB Clock control 1 */ -/*! @{ */ -#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) -#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) -/*! MRT - Enables the clock for the MRT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) -#define SYSCON_AHBCLKCTRL1_OSTIMER0_MASK (0x2U) -#define SYSCON_AHBCLKCTRL1_OSTIMER0_SHIFT (1U) -/*! OSTIMER0 - Enables the clock for the OS Timer 0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER0_MASK) -#define SYSCON_AHBCLKCTRL1_SCT0_MASK (0x4U) -#define SYSCON_AHBCLKCTRL1_SCT0_SHIFT (2U) -/*! SCT0 - Enables the clock for the SCT0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT0_MASK) -#define SYSCON_AHBCLKCTRL1_SCTIPU_MASK (0x40U) -#define SYSCON_AHBCLKCTRL1_SCTIPU_SHIFT (6U) -/*! SCTIPU - Enables the clock for the SCTIPU. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_SCTIPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCTIPU_SHIFT)) & SYSCON_AHBCLKCTRL1_SCTIPU_MASK) -#define SYSCON_AHBCLKCTRL1_UTICK0_MASK (0x400U) -#define SYSCON_AHBCLKCTRL1_UTICK0_SHIFT (10U) -/*! UTICK0 - Enables the clock for the UTICK0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK0_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK0_MASK) -#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) -#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) -/*! FC0 - Enables the clock for the FC0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) -#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) -/*! FC1 - Enables the clock for the FC1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) -#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) -/*! FC2 - Enables the clock for the FC2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) -#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) -/*! FC3 - Enables the clock for the FC3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) -#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) -/*! FC4 - Enables the clock for the FC4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) -#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) -/*! FC5 - Enables the clock for the FC5. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) -#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) -/*! FC6 - Enables the clock for the FC6. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) -#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) -/*! FC7 - Enables the clock for the FC7. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) -#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) -/*! TIMER2 - Enables the clock for the Timer 2. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) -#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) -#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) -/*! USB0_DEV - Enables the clock for the USB0 DEV. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) -#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) -/*! TIMER0 - Enables the clock for the Timer 0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) -#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) -/*! TIMER1 - Enables the clock for the Timer 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) -#define SYSCON_AHBCLKCTRL1_PVT_MASK (0x10000000U) -#define SYSCON_AHBCLKCTRL1_PVT_SHIFT (28U) -/*! PVT - Enables the clock for the PVT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_PVT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_PVT_SHIFT)) & SYSCON_AHBCLKCTRL1_PVT_MASK) -#define SYSCON_AHBCLKCTRL1_EZHA_MASK (0x40000000U) -#define SYSCON_AHBCLKCTRL1_EZHA_SHIFT (30U) -/*! EZHA - Enables the clock for the EZH a. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_EZHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHA_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHA_MASK) -#define SYSCON_AHBCLKCTRL1_EZHB_MASK (0x80000000U) -#define SYSCON_AHBCLKCTRL1_EZHB_SHIFT (31U) -/*! EZHB - Enables the clock for the EZH b. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_EZHB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHB_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHB_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL2 - AHB Clock control 2 */ -/*! @{ */ -#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) -#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) -/*! DMA1 - Enables the clock for the DMA1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) -#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) -#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) -/*! COMP - Enables the clock for the Comparator. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) -#define SYSCON_AHBCLKCTRL2_SDIO_MASK (0x8U) -#define SYSCON_AHBCLKCTRL2_SDIO_SHIFT (3U) -/*! SDIO - Enables the clock for the SDIO. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK) -#define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U) -#define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U) -/*! USB1_HOST - Enables the clock for the USB1 Host. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK) -#define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U) -#define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U) -/*! USB1_DEV - Enables the clock for the USB1 dev. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK) -#define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U) -#define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U) -/*! USB1_RAM - Enables the clock for the USB1 RAM. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK) -#define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U) -#define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U) -/*! USB1_PHY - Enables the clock for the USB1 PHY. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK) -#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) -#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) -/*! FREQME - Enables the clock for the Frequency meter. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) -#define SYSCON_AHBCLKCTRL2_GPIO4_MASK (0x200U) -#define SYSCON_AHBCLKCTRL2_GPIO4_SHIFT (9U) -/*! GPIO4 - Enables the clock for the GPIO4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO4_MASK) -#define SYSCON_AHBCLKCTRL2_GPIO5_MASK (0x400U) -#define SYSCON_AHBCLKCTRL2_GPIO5_SHIFT (10U) -/*! GPIO5 - Enables the clock for the GPIO5. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO5_MASK) -#define SYSCON_AHBCLKCTRL2_OTP_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL2_OTP_SHIFT (12U) -/*! OTP - Enables the clock for the OTP. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_OTP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_OTP_SHIFT)) & SYSCON_AHBCLKCTRL2_OTP_MASK) -#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) -/*! RNG - Enables the clock for the RNG. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) -#define SYSCON_AHBCLKCTRL2_MUX1_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL2_MUX1_SHIFT (14U) -/*! MUX1 - Enables the clock for the Peripheral Input Mux 1. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_MUX1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_MUX1_SHIFT)) & SYSCON_AHBCLKCTRL2_MUX1_MASK) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) -/*! USB0_HOSTM - Enables the clock for the USB0 Host Master. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) -/*! USB0_HOSTS - Enables the clock for the USB0 Host Slave. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) -#define SYSCON_AHBCLKCTRL2_HASH0_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL2_HASH0_SHIFT (18U) -/*! HASH0 - Enables the clock for the HASH0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_HASH0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH0_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH0_MASK) -#define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U) -/*! PQ - Enables the clock for the Power Quad. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK) -#define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U) -/*! PLULUT - Enables the clock for the PLU LUT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK) -#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) -/*! TIMER3 - Enables the clock for the Timer 3. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) -#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) -/*! TIMER4 - Enables the clock for the Timer 4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) -#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) -/*! PUF - Enables the clock for the PUF reset control. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) -#define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U) -#define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U) -/*! CASPER - Enables the clock for the Casper. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK) -#define SYSCON_AHBCLKCTRL2_CAPT0_MASK (0x2000000U) -#define SYSCON_AHBCLKCTRL2_CAPT0_SHIFT (25U) -/*! CAPT0 - Enables the clock for the CAPT0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_CAPT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CAPT0_SHIFT)) & SYSCON_AHBCLKCTRL2_CAPT0_MASK) -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) -/*! ANALOG_CTRL - Enables the clock for the analog control. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) -#define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U) -#define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U) -/*! HS_LSPI - Enables the clock for the HS LSPI. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) -/*! GPIO_SEC - Enables the clock for the GPIO secure. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) -/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK) -/*! @} */ - -/*! @name AHBCLKCTRLX - Peripheral reset control register */ -/*! @{ */ -#define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U) -#define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLX */ -#define SYSCON_AHBCLKCTRLX_COUNT (3U) - -/*! @name AHBCLKCTRLSET - Peripheral reset control register */ -/*! @{ */ -#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) -#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLSET */ -#define SYSCON_AHBCLKCTRLSET_COUNT (3U) - -/*! @name AHBCLKCTRLCLR - Peripheral reset control register */ -/*! @{ */ -#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) -#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLCLR */ -#define SYSCON_AHBCLKCTRLCLR_COUNT (3U) - -/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ -/*! @{ */ -#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) -/*! SEL - System Tick Timer for CPU0 source select. - * 0b000..System Tick 0 divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKSEL1 - System Tick Timer for CPU1 source select */ -/*! @{ */ -#define SYSCON_SYSTICKCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT (0U) -/*! SEL - System Tick Timer for CPU1 source select. - * 0b000..System Tick 1 divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SYSTICKCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL1_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKSELX - Peripheral reset control register */ -/*! @{ */ -#define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U) -#define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_SYSTICKCLKSELX */ -#define SYSCON_SYSTICKCLKSELX_COUNT (2U) - -/*! @name TRACECLKSEL - Trace clock source select */ -/*! @{ */ -#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) -#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) -/*! SEL - Trace clock source select. - * 0b000..Trace divided clock. - * 0b001..FRO 1MHz clock. - * 0b010..Oscillator 32 kHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */ -/*! @{ */ -#define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U) -/*! SEL - CTimer 0 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */ -/*! @{ */ -#define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U) -/*! SEL - CTimer 1 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */ -/*! @{ */ -#define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U) -/*! SEL - CTimer 2 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */ -/*! @{ */ -#define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U) -/*! SEL - CTimer 3 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */ -/*! @{ */ -#define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U) -#define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U) -/*! SEL - CTimer 4 clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CTIMERCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK) -/*! @} */ - -/*! @name CTIMERCLKSELX - Peripheral reset control register */ -/*! @{ */ -#define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U) -#define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_CTIMERCLKSELX */ -#define SYSCON_CTIMERCLKSELX_COUNT (5U) - -/*! @name MAINCLKSELA - Main clock A source select */ -/*! @{ */ -#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) -#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) -/*! SEL - Main clock A source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) -/*! @} */ - -/*! @name MAINCLKSELB - Main clock source select */ -/*! @{ */ -#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) -#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) -/*! SEL - Main clock source select. - * 0b000..Main Clock A. - * 0b001..PLL0 clock. - * 0b010..PLL1 clock. - * 0b011..Oscillator 32 kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) -/*! @} */ - -/*! @name CLKOUTSEL - CLKOUT clock source select */ -/*! @{ */ -#define SYSCON_CLKOUTSEL_SEL_MASK (0x7U) -#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) -/*! SEL - CLKOUT clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..CLKIN clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..PLL1 clock. - * 0b110..Oscillator 32kHz clock. - * 0b111..No clock. - */ -#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) -/*! @} */ - -/*! @name PLL0CLKSEL - PLL0 clock source select */ -/*! @{ */ -#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) -#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) -/*! SEL - PLL0 clock source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..Oscillator 32kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name PLL1CLKSEL - PLL1 clock source select */ -/*! @{ */ -#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) -#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) -/*! SEL - PLL1 clock source select. - * 0b000..FRO 12 MHz clock. - * 0b001..CLKIN clock. - * 0b010..FRO 1MHz clock. - * 0b011..Oscillator 32kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name ADCCLKSEL - ADC clock source select */ -/*! @{ */ -#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) -#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) -/*! SEL - ADC clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..FRO 96 MHz clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name USB0CLKSEL - FS USB clock source select */ -/*! @{ */ -#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) -#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) -/*! SEL - FS USB clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..PLL1 clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name USB1CLKSEL - HS USB clock source select - NOT USED */ -/*! @{ */ -#define SYSCON_USB1CLKSEL_SEL_MASK (0x7U) -#define SYSCON_USB1CLKSEL_SEL_SHIFT (0U) -/*! SEL - HS USB clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..CLKIN clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..PLL1 clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_USB1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */ -/*! @{ */ -#define SYSCON_FCCLKSEL0_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL0_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */ -/*! @{ */ -#define SYSCON_FCCLKSEL1_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL1_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */ -/*! @{ */ -#define SYSCON_FCCLKSEL2_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL2_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */ -/*! @{ */ -#define SYSCON_FCCLKSEL3_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL3_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */ -/*! @{ */ -#define SYSCON_FCCLKSEL4_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL4_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */ -/*! @{ */ -#define SYSCON_FCCLKSEL5_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL5_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL5_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */ -/*! @{ */ -#define SYSCON_FCCLKSEL6_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL6_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL6_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */ -/*! @{ */ -#define SYSCON_FCCLKSEL7_SEL_MASK (0x7U) -#define SYSCON_FCCLKSEL7_SEL_SHIFT (0U) -/*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..MCLK clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_FCCLKSEL7_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK) -/*! @} */ - -/*! @name FCCLKSELX - Peripheral reset control register */ -/*! @{ */ -#define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_FCCLKSELX_DATA_SHIFT (0U) -#define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_FCCLKSELX */ -#define SYSCON_FCCLKSELX_COUNT (8U) - -/*! @name HSLSPICLKSEL - HS LSPI clock source select */ -/*! @{ */ -#define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U) -#define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U) -/*! SEL - HS LSPI clock source select. - * 0b000..Main clock. - * 0b001..system PLL divided clock. - * 0b010..FRO 12 MHz clock. - * 0b011..FRO 96 MHz clock. - * 0b100..FRO 1MHz clock. - * 0b101..No clock. - * 0b110..Oscillator 32 kHz clock. - * 0b111..No clock. - */ -#define SYSCON_HSLSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK) -/*! @} */ - -/*! @name MCLKCLKSEL - MCLK clock source select */ -/*! @{ */ -#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) -#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) -/*! SEL - MCLK clock source select. - * 0b000..FRO 96 MHz clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ -/*! @{ */ -#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) -/*! SEL - SCTimer/PWM clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..CLKIN clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..MCLK clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SDIOCLKSEL - SDIO clock source select */ -/*! @{ */ -#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U) -/*! SEL - SDIO clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..PLL1 clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */ -/*! @{ */ -#define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU) -#define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U) -#define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK) -#define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U) -#define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK) -#define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U) -#define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK) -#define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U) -#define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK) -/*! @} */ - -/*! @name SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 */ -/*! @{ */ -#define SYSCON_SYSTICKCLKDIV1_DIV_MASK (0xFFU) -#define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT (0U) -#define SYSCON_SYSTICKCLKDIV1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK) -#define SYSCON_SYSTICKCLKDIV1_RESET_MASK (0x20000000U) -#define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SYSTICKCLKDIV1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK) -#define SYSCON_SYSTICKCLKDIV1_HALT_MASK (0x40000000U) -#define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SYSTICKCLKDIV1_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK) -#define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK (0x80000000U) -#define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SYSTICKCLKDIV1_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK) -/*! @} */ - -/*! @name TRACECLKDIV - TRACE clock divider */ -/*! @{ */ -#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) -#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) -#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) -#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) -#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) -#define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_TRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */ -/*! @{ */ -#define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U) -#define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK) -#define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U) -#define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */ -/*! @{ */ -#define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U) -#define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK) -#define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U) -#define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */ -/*! @{ */ -#define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U) -#define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK) -#define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U) -#define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */ -/*! @{ */ -#define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U) -#define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK) -#define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U) -#define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */ -/*! @{ */ -#define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U) -#define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK) -#define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U) -#define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */ -/*! @{ */ -#define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U) -#define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK) -#define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U) -#define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */ -/*! @{ */ -#define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U) -#define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK) -#define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U) -#define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */ -/*! @{ */ -#define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU) -#define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U) -#define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK) -#define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U) -#define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U) -#define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK) -/*! @} */ - -/*! @name FLEXFRGXCTRL - Peripheral reset control register */ -/*! @{ */ -#define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU) -#define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U) -#define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK) -/*! @} */ - -/* The count of SYSCON_FLEXFRGXCTRL */ -#define SYSCON_FLEXFRGXCTRL_COUNT (8U) - -/*! @name AHBCLKDIV - System clock divider */ -/*! @{ */ -#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) -#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) -#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) -#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) -#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name CLKOUTDIV - CLKOUT clock divider */ -/*! @{ */ -#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) -#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) -#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) -#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) -#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) -#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) -#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) -#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ -/*! @{ */ -#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) -#define SYSCON_FROHFDIV_DIV_SHIFT (0U) -#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) -#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) -#define SYSCON_FROHFDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) -#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) -#define SYSCON_FROHFDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) -#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name WDTCLKDIV - WDT clock divider */ -/*! @{ */ -#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) -#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) -#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) -#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) -#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) -#define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_WDTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name ADCCLKDIV - ADC clock divider */ -/*! @{ */ -#define SYSCON_ADCCLKDIV_DIV_MASK (0x7U) -#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) -#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) -#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) -#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) -#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name USB0CLKDIV - USB0 Clock divider */ -/*! @{ */ -#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) -#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) -#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) -#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) -#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name MCLKDIV - I2S MCLK clock divider */ -/*! @{ */ -#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_MCLKDIV_DIV_SHIFT (0U) -#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) -#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_MCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) -#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_MCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) -#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name SCTCLKDIV - SCT/PWM clock divider */ -/*! @{ */ -#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) -#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) -#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) -#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) -#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name SDIOCLKDIV - SDIO clock divider */ -/*! @{ */ -#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U) -#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK) -#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK) -#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK) -#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name PLL0CLKDIV - PLL0 clock divider */ -/*! @{ */ -#define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU) -#define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U) -#define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK) -#define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U) -#define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U) -/*! RESET - Resets the divider counter. - * 0b1..Divider is reset. - * 0b0..Divider is not reset. - */ -#define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK) -#define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U) -#define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U) -/*! HALT - Halts the divider counter. - * 0b1..Divider clock is stoped. - * 0b0..Divider clock is running. - */ -#define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK) -#define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U) -#define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U) -/*! REQFLAG - Divider status flag. - * 0b1..Clock frequency is not stable. - * 0b0..Divider clock is stable. - */ -#define SYSCON_PLL0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK) -/*! @} */ - -/*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */ -/*! @{ */ -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU) -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U) -/*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL). - * 0b00000000000000000000000000000001..update all clock configuration. - * 0b00000000000000000000000000000000..all hardware clock configruration are freeze. - */ -#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK) -/*! @} */ - -/*! @name FMCCR - FMC configuration register - INTERNAL USE ONLY */ -/*! @{ */ -#define SYSCON_FMCCR_FETCHCTL_MASK (0x3U) -#define SYSCON_FMCCR_FETCHCTL_SHIFT (0U) -/*! FETCHCTL - Fetch control - * 0b00..No buffering (bypass always used) for Fetch cycles - * 0b01..One buffer is used for all Fetch cycles - * 0b10..All buffers can be used for Fetch cycles - */ -#define SYSCON_FMCCR_FETCHCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCTL_SHIFT)) & SYSCON_FMCCR_FETCHCTL_MASK) -#define SYSCON_FMCCR_DATACTL_MASK (0xCU) -#define SYSCON_FMCCR_DATACTL_SHIFT (2U) -/*! DATACTL - Data control - * 0b00..No buffering (bypass always used) for Data cycles - * 0b01..One buffer is used for all Data cycles - * 0b10..All buffers can be used for Data cycles - */ -#define SYSCON_FMCCR_DATACTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACTL_SHIFT)) & SYSCON_FMCCR_DATACTL_MASK) -#define SYSCON_FMCCR_ACCEL_MASK (0x10U) -#define SYSCON_FMCCR_ACCEL_SHIFT (4U) -#define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) -#define SYSCON_FMCCR_PREFEN_MASK (0x20U) -#define SYSCON_FMCCR_PREFEN_SHIFT (5U) -#define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) -#define SYSCON_FMCCR_PREFOVR_MASK (0x40U) -#define SYSCON_FMCCR_PREFOVR_SHIFT (6U) -#define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) -#define SYSCON_FMCCR_PREFCRI_MASK (0x700U) -#define SYSCON_FMCCR_PREFCRI_SHIFT (8U) -#define SYSCON_FMCCR_PREFCRI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFCRI_SHIFT)) & SYSCON_FMCCR_PREFCRI_MASK) -#define SYSCON_FMCCR_FMCTIM_MASK (0x1F000U) -#define SYSCON_FMCCR_FMCTIM_SHIFT (12U) -#define SYSCON_FMCCR_FMCTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FMCTIM_SHIFT)) & SYSCON_FMCCR_FMCTIM_MASK) -#define SYSCON_FMCCR_PFISLRU_MASK (0x20000U) -#define SYSCON_FMCCR_PFISLRU_SHIFT (17U) -#define SYSCON_FMCCR_PFISLRU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PFISLRU_SHIFT)) & SYSCON_FMCCR_PFISLRU_MASK) -#define SYSCON_FMCCR_PFADAP_MASK (0x40000U) -#define SYSCON_FMCCR_PFADAP_SHIFT (18U) -#define SYSCON_FMCCR_PFADAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PFADAP_SHIFT)) & SYSCON_FMCCR_PFADAP_MASK) -/*! @} */ - -/*! @name USB0CLKCTRL - USB0 clock control */ -/*! @{ */ -#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U) -#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U) -/*! AP_FS_DEV_CLK - USB0 Device USB0_NEEDCLK signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK) -#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U) -#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U) -/*! POL_FS_DEV_CLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. - * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. - * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK) -#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U) -#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U) -/*! AP_FS_HOST_CLK - USB0 Host USB0_NEEDCLK signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK) -#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U) -#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U) -/*! POL_FS_HOST_CLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. - * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. - * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. - */ -#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK) -#define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK (0x10U) -#define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT (4U) -/*! PU_DISABLE - Internal pull-up disable control. - * 0b1..Internal pull-up disable. - * 0b0..Internal pull-up enable. - */ -#define SYSCON_USB0CLKCTRL_PU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK) -/*! @} */ - -/*! @name USB0CLKSTAT - USB0 clock status */ -/*! @{ */ -#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) -#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) -/*! DEV_NEED_CLKST - USB0 Device USB0_NEEDCLK signal status:. - * 0b1..USB0 Device clock is high. - * 0b0..USB0 Device clock is low. - */ -#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK) -#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) -#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) -/*! HOST_NEED_CLKST - USB0 Host USB0_NEEDCLK signal status:. - * 0b1..USB0 Host clock is high. - * 0b0..USB0 Host clock is low. - */ -#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK) -/*! @} */ - -/*! @name FMCFLUSH - FMCflush control */ -/*! @{ */ -#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) -#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) -#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) -/*! @} */ - -/*! @name MCLKIO - MCLK control */ -/*! @{ */ -#define SYSCON_MCLKIO_MCLKIO_MASK (0xFFFFFFFFU) -#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) -/*! MCLKIO - MCLK control. - * 0b00000000000000000000000000000000..input mode. - * 0b00000000000000000000000000000001..output mode. - */ -#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) -/*! @} */ - -/*! @name USB1CLKCTRL - USB1 clock control */ -/*! @{ */ -#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_MASK (0x1U) -#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_SHIFT (0U) -/*! AP_HS_DEV_CLK - USB1 Device need_clock signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_MASK) -#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_MASK (0x2U) -#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_SHIFT (1U) -/*! POL_HS_DEV_CLK - USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt:. - * 0b0..Falling edge of device need_clock triggers wake-up. - * 0b1..Rising edge of device need_clock triggers wake-up. - */ -#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_MASK) -#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_MASK (0x4U) -#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_SHIFT (2U) -/*! AP_HS_HOST_CLK - USB1 Host need_clock signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. - */ -#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_MASK) -#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_MASK (0x8U) -#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_SHIFT (3U) -/*! POL_HS_HOST_CLK - USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt: 0 Falling edge of device need_clock triggers wake-up. - * 0b0..Falling edge of device need_clock triggers wake-up. - * 0b1..Rising edge of device need_clock triggers wake-up. - */ -#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_MASK) -#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) -#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) -/*! HS_DEV_WAKEUP_N - External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to synchronous control logic:. - * 0b0..Forces USB1 PHY to wake-up. - * 0b1..Normal USB1 PHY behavior. - */ -#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK) -/*! @} */ - -/*! @name USB1CLKSTAT - USB1 clock status */ -/*! @{ */ -#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) -#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) -/*! DEV_NEED_CLKST - USB1 Device need_clock signal status:. - * 0b1..USB1 Device clock is high. - * 0b0..USB1 Device clock is low. - */ -#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK) -#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) -#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) -/*! HOST_NEED_CLKST - USB1 Host need_clock signal status:. - * 0b1..USB1 Host clock is high. - * 0b0..USB1 Host clock is low. - */ -#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK) -/*! @} */ - -/*! @name FLASHBANKENABLE - Flash Banks control */ -/*! @{ */ -#define SYSCON_FLASHBANKENABLE_BANK0_MASK (0xFU) -#define SYSCON_FLASHBANKENABLE_BANK0_SHIFT (0U) -/*! BANK0 - Flash Bank0 control. - * 0b0000..Flash BANK0 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - * 0b1010..1010: Flash BANK0 checker is disabled (all Flash pages inside this bank can be erased and programmed). - */ -#define SYSCON_FLASHBANKENABLE_BANK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK0_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK0_MASK) -#define SYSCON_FLASHBANKENABLE_BANK1_MASK (0xF0U) -#define SYSCON_FLASHBANKENABLE_BANK1_SHIFT (4U) -/*! BANK1 - Flash Bank1 control. - * 0b0000..Flash BANK1 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - * 0b1010..1010: Flash BANK1 checker is disabled (all Flash pages inside this bank can be erased and programmed). - */ -#define SYSCON_FLASHBANKENABLE_BANK1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK1_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK1_MASK) -#define SYSCON_FLASHBANKENABLE_BANK2_MASK (0xF00U) -#define SYSCON_FLASHBANKENABLE_BANK2_SHIFT (8U) -/*! BANK2 - Flash Bank2 control. - * 0b0000..Flash BANK2 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - * 0b1010..1010: Flash BANK2 checker is disabled (all Flash pages inside this bank can be erased and programmed). - */ -#define SYSCON_FLASHBANKENABLE_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK2_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK2_MASK) -/*! @} */ - -/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */ -/*! @{ */ -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U) -/*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. - * 0b00..0 degree shift. - * 0b01..90 degree shift. - * 0b10..180 degree shift. - * 0b11..270 degree shift. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U) -/*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. - * 0b00..0 degree shift. - * 0b01..90 degree shift. - * 0b10..180 degree shift. - * 0b11..270 degree shift. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK) -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U) -/*! PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. - * 0b0..Bypassed. - * 0b1..Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. - */ -#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U) -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U) -/*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field. - * 0b1..Enable drive delay. - * 0b0..Disable drive delay. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U) -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U) -/*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. - * 0b1..Enables sample delay. - * 0b0..Disables sample delay. - */ -#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK) -/*! @} */ - -/*! @name PLL1CTRL - PLL1 550m control */ -/*! @{ */ -#define SYSCON_PLL1CTRL_SELR_MASK (0xFU) -#define SYSCON_PLL1CTRL_SELR_SHIFT (0U) -#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) -#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) -#define SYSCON_PLL1CTRL_SELI_SHIFT (4U) -#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) -#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) -#define SYSCON_PLL1CTRL_SELP_SHIFT (10U) -#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) -#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) -#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) -/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - * 0b1..PLL input clock is sent directly to the PLL output. - * 0b0..use PLL. - */ -#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) -/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - * 0b1..bypass of the divide-by-2 divider in the post-divider. - * 0b0..use the divide-by-2 divider in the post-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) -#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) -#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) -#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) -#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) -#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) -/*! BWDIRECT - control of the bandwidth of the PLL. - * 0b1..modify the bandwidth of the PLL directly. - * 0b0..the bandwidth is changed synchronously with the feedback-divider. - */ -#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) -#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) -#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) -/*! BYPASSPREDIV - bypass of the pre-divider. - * 0b1..bypass of the pre-divider. - * 0b0..use the pre-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) -/*! BYPASSPOSTDIV - bypass of the post-divider. - * 0b1..bypass of the post-divider. - * 0b0..use the post-divider. - */ -#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) -#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) -#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) -/*! CLKEN - enable the output clock. - * 0b1..Enable the output clock. - * 0b0..Disable the output clock. - */ -#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) -#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) -#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) -#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) -#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) -#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) -#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) -#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) -#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) -/*! SKEWEN - Skew mode. - * 0b1..skewmode is enable. - * 0b0..skewmode is disable. - */ -#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK) -/*! @} */ - -/*! @name PLL1STAT - PLL1 550m status */ -/*! @{ */ -#define SYSCON_PLL1STAT_LOCK_MASK (0x1U) -#define SYSCON_PLL1STAT_LOCK_SHIFT (0U) -#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) -#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) -#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) -#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) -#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) -#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) -#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) -#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) -#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) -#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) -#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) -#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) -#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) -/*! @} */ - -/*! @name PLL1NDEC - PLL1 550m N divider */ -/*! @{ */ -#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) -#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) -#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) -#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) -#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) -#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) -/*! @} */ - -/*! @name PLL1MDEC - PLL1 550m M divider */ -/*! @{ */ -#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) -#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) -#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) -#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) -#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) -#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) -/*! @} */ - -/*! @name PLL1PDEC - PLL1 550m P divider */ -/*! @{ */ -#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) -#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) -#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) -#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) -#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) -#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) -/*! @} */ - -/*! @name PLL0CTRL - PLL0 550m control */ -/*! @{ */ -#define SYSCON_PLL0CTRL_SELR_MASK (0xFU) -#define SYSCON_PLL0CTRL_SELR_SHIFT (0U) -#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) -#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) -#define SYSCON_PLL0CTRL_SELI_SHIFT (4U) -#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) -#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) -#define SYSCON_PLL0CTRL_SELP_SHIFT (10U) -#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) -#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) -#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) -/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). - * 0b1..Bypass PLL input clock is sent directly to the PLL output. - * 0b0..use PLL. - */ -#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) -/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. - * 0b1..bypass of the divide-by-2 divider in the post-divider. - * 0b0..use the divide-by-2 divider in the post-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) -#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) -#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) -#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) -#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) -#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) -/*! BWDIRECT - Control of the bandwidth of the PLL. - * 0b1..modify the bandwidth of the PLL directly. - * 0b0..the bandwidth is changed synchronously with the feedback-divider. - */ -#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) -#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) -#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) -/*! BYPASSPREDIV - bypass of the pre-divider. - * 0b1..bypass of the pre-divider. - * 0b0..use the pre-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) -/*! BYPASSPOSTDIV - bypass of the post-divider. - * 0b1..bypass of the post-divider. - * 0b0..use the post-divider. - */ -#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) -#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) -#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) -/*! CLKEN - enable the output clock. - * 0b1..enable the output clock. - * 0b0..disable the output clock. - */ -#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) -#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) -#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) -/*! FRMEN - free running mode. - * 0b1..free running mode is enable. - * 0b0..free running mode is disable. - */ -#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) -#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) -#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) -#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) -#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) -#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) -/*! SKEWEN - skew mode. - * 0b1..skew mode is enable. - * 0b0..skew mode is disable. - */ -#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK) -/*! @} */ - -/*! @name PLL0STAT - PLL0 550m status */ -/*! @{ */ -#define SYSCON_PLL0STAT_LOCK_MASK (0x1U) -#define SYSCON_PLL0STAT_LOCK_SHIFT (0U) -#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) -#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) -#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) -#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) -#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) -#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) -#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) -#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) -#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) -#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) -#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) -#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) -#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) -/*! @} */ - -/*! @name PLL0NDEC - PLL0 550m N divider */ -/*! @{ */ -#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) -#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) -#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) -#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) -#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) -#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) -/*! @} */ - -/*! @name PLL0PDEC - PLL0 550m P divider */ -/*! @{ */ -#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) -#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) -#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) -#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) -#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) -#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) -/*! @} */ - -/*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */ -/*! @{ */ -#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) -#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) -#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) -/*! @} */ - -/*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */ -/*! @{ */ -#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) -#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) -#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) -#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) -#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) -#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) -#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) -#define SYSCON_PLL0SSCG1_MF_SHIFT (2U) -#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) -#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) -#define SYSCON_PLL0SSCG1_MR_SHIFT (5U) -#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) -#define SYSCON_PLL0SSCG1_MC_MASK (0x300U) -#define SYSCON_PLL0SSCG1_MC_SHIFT (8U) -#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) -#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) -#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) -#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) -#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) -#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) -#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) -#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) -#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) -#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) -#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) -#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) -#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) -/*! @} */ - -/*! @name EFUSECLKCTRL - eFUSE controller clock enable */ -/*! @{ */ -#define SYSCON_EFUSECLKCTRL_EFUSECLKENA_MASK (0x1U) -#define SYSCON_EFUSECLKCTRL_EFUSECLKENA_SHIFT (0U) -#define SYSCON_EFUSECLKCTRL_EFUSECLKENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EFUSECLKCTRL_EFUSECLKENA_SHIFT)) & SYSCON_EFUSECLKCTRL_EFUSECLKENA_MASK) -/*! @} */ - -/*! @name STARTER - Start logic wake-up enable register */ -/*! @{ */ -#define SYSCON_STARTER_GPIO_INT04_MASK (0x1U) -#define SYSCON_STARTER_GPIO_INT04_SHIFT (0U) -/*! GPIO_INT04 - GPIO_INT04 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT04(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT04_SHIFT)) & SYSCON_STARTER_GPIO_INT04_MASK) -#define SYSCON_STARTER_SYS_MASK (0x1U) -#define SYSCON_STARTER_SYS_SHIFT (0U) -/*! SYS - SYS interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SYS_SHIFT)) & SYSCON_STARTER_SYS_MASK) -#define SYSCON_STARTER_GPIO_INT05_MASK (0x2U) -#define SYSCON_STARTER_GPIO_INT05_SHIFT (1U) -/*! GPIO_INT05 - GPIO_INT05 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT05(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT05_SHIFT)) & SYSCON_STARTER_GPIO_INT05_MASK) -#define SYSCON_STARTER_SDMA0_MASK (0x2U) -#define SYSCON_STARTER_SDMA0_SHIFT (1U) -/*! SDMA0 - SDMA0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA0_SHIFT)) & SYSCON_STARTER_SDMA0_MASK) -#define SYSCON_STARTER_GINT0_MASK (0x4U) -#define SYSCON_STARTER_GINT0_SHIFT (2U) -/*! GINT0 - GINT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK) -#define SYSCON_STARTER_GPIO_INT06_MASK (0x4U) -#define SYSCON_STARTER_GPIO_INT06_SHIFT (2U) -/*! GPIO_INT06 - GPIO_INT06 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT06(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT06_SHIFT)) & SYSCON_STARTER_GPIO_INT06_MASK) -#define SYSCON_STARTER_GINT1_MASK (0x8U) -#define SYSCON_STARTER_GINT1_SHIFT (3U) -/*! GINT1 - GINT1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK) -#define SYSCON_STARTER_GPIO_INT07_MASK (0x8U) -#define SYSCON_STARTER_GPIO_INT07_SHIFT (3U) -/*! GPIO_INT07 - GPIO_INT07 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT07(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT07_SHIFT)) & SYSCON_STARTER_GPIO_INT07_MASK) -#define SYSCON_STARTER_CTIMER2_MASK (0x10U) -#define SYSCON_STARTER_CTIMER2_SHIFT (4U) -/*! CTIMER2 - CTIMER2 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK) -#define SYSCON_STARTER_PIO_INT0_MASK (0x10U) -#define SYSCON_STARTER_PIO_INT0_SHIFT (4U) -/*! PIO_INT0 - PIO_INT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT0_SHIFT)) & SYSCON_STARTER_PIO_INT0_MASK) -#define SYSCON_STARTER_CTIMER4_MASK (0x20U) -#define SYSCON_STARTER_CTIMER4_SHIFT (5U) -/*! CTIMER4 - CTIMER4 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK) -#define SYSCON_STARTER_PIO_INT1_MASK (0x20U) -#define SYSCON_STARTER_PIO_INT1_SHIFT (5U) -/*! PIO_INT1 - PIO_INT1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT1_SHIFT)) & SYSCON_STARTER_PIO_INT1_MASK) -#define SYSCON_STARTER_OS_EVENT_MASK (0x40U) -#define SYSCON_STARTER_OS_EVENT_SHIFT (6U) -/*! OS_EVENT - OS_EVENT interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_OS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_OS_EVENT_SHIFT)) & SYSCON_STARTER_OS_EVENT_MASK) -#define SYSCON_STARTER_PIO_INT2_MASK (0x40U) -#define SYSCON_STARTER_PIO_INT2_SHIFT (6U) -/*! PIO_INT2 - PIO_INT2 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT2_SHIFT)) & SYSCON_STARTER_PIO_INT2_MASK) -#define SYSCON_STARTER_PIO_INT3_MASK (0x80U) -#define SYSCON_STARTER_PIO_INT3_SHIFT (7U) -/*! PIO_INT3 - PIO_INT3 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT3_SHIFT)) & SYSCON_STARTER_PIO_INT3_MASK) -#define SYSCON_STARTER_UTICK0_MASK (0x100U) -#define SYSCON_STARTER_UTICK0_SHIFT (8U) -/*! UTICK0 - UTICK0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK0_SHIFT)) & SYSCON_STARTER_UTICK0_MASK) -#define SYSCON_STARTER_MRT0_MASK (0x200U) -#define SYSCON_STARTER_MRT0_SHIFT (9U) -/*! MRT0 - MRT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT0_SHIFT)) & SYSCON_STARTER_MRT0_MASK) -#define SYSCON_STARTER_CTIMER0_MASK (0x400U) -#define SYSCON_STARTER_CTIMER0_SHIFT (10U) -/*! CTIMER0 - CTIMER0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK) -#define SYSCON_STARTER_SDIO_MASK (0x400U) -#define SYSCON_STARTER_SDIO_SHIFT (10U) -/*! SDIO - SDIO interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDIO_SHIFT)) & SYSCON_STARTER_SDIO_MASK) -#define SYSCON_STARTER_CTIMER1_MASK (0x800U) -#define SYSCON_STARTER_CTIMER1_SHIFT (11U) -/*! CTIMER1 - CTIMER1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK) -#define SYSCON_STARTER_SCT0_MASK (0x1000U) -#define SYSCON_STARTER_SCT0_SHIFT (12U) -/*! SCT0 - SCT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK) -#define SYSCON_STARTER_CTIMER3_MASK (0x2000U) -#define SYSCON_STARTER_CTIMER3_SHIFT (13U) -/*! CTIMER3 - CTIMER3 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK) -#define SYSCON_STARTER_FLEXINT0_MASK (0x4000U) -#define SYSCON_STARTER_FLEXINT0_SHIFT (14U) -/*! FLEXINT0 - FLEXINT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT0_SHIFT)) & SYSCON_STARTER_FLEXINT0_MASK) -#define SYSCON_STARTER_FLEXINT1_MASK (0x8000U) -#define SYSCON_STARTER_FLEXINT1_SHIFT (15U) -/*! FLEXINT1 - FLEXINT1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT1_SHIFT)) & SYSCON_STARTER_FLEXINT1_MASK) -#define SYSCON_STARTER_USB1_MASK (0x8000U) -#define SYSCON_STARTER_USB1_SHIFT (15U) -/*! USB1 - USB1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK) -#define SYSCON_STARTER_FLEXINT2_MASK (0x10000U) -#define SYSCON_STARTER_FLEXINT2_SHIFT (16U) -/*! FLEXINT2 - FLEXINT2 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT2_SHIFT)) & SYSCON_STARTER_FLEXINT2_MASK) -#define SYSCON_STARTER_USB1_NEEDCLK_MASK (0x10000U) -#define SYSCON_STARTER_USB1_NEEDCLK_SHIFT (16U) -/*! USB1_NEEDCLK - USB1_NEEDCLK interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB1_NEEDCLK_MASK) -#define SYSCON_STARTER_FLEXINT3_MASK (0x20000U) -#define SYSCON_STARTER_FLEXINT3_SHIFT (17U) -/*! FLEXINT3 - FLEXINT3 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT3_SHIFT)) & SYSCON_STARTER_FLEXINT3_MASK) -#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK (0x20000U) -#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT (17U) -/*! SEC_HYPERVISOR_CALL - SEC_HYPERVISOR_CALL interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_HYPERVISOR_CALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT)) & SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK) -#define SYSCON_STARTER_FLEXINT4_MASK (0x40000U) -#define SYSCON_STARTER_FLEXINT4_SHIFT (18U) -/*! FLEXINT4 - FLEXINT4 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT4_SHIFT)) & SYSCON_STARTER_FLEXINT4_MASK) -#define SYSCON_STARTER_SEC_GPIO_INT00_MASK (0x40000U) -#define SYSCON_STARTER_SEC_GPIO_INT00_SHIFT (18U) -/*! SEC_GPIO_INT00 - SEC_GPIO_INT00 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_GPIO_INT00(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT00_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT00_MASK) -#define SYSCON_STARTER_FLEXINT5_MASK (0x80000U) -#define SYSCON_STARTER_FLEXINT5_SHIFT (19U) -/*! FLEXINT5 - FLEXINT5 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT5_SHIFT)) & SYSCON_STARTER_FLEXINT5_MASK) -#define SYSCON_STARTER_SEC_GPIO_INT01_MASK (0x80000U) -#define SYSCON_STARTER_SEC_GPIO_INT01_SHIFT (19U) -/*! SEC_GPIO_INT01 - SEC_GPIO_INT01 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_GPIO_INT01(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT01_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT01_MASK) -#define SYSCON_STARTER_FLEXINT6_MASK (0x100000U) -#define SYSCON_STARTER_FLEXINT6_SHIFT (20U) -/*! FLEXINT6 - FLEXINT6 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT6_SHIFT)) & SYSCON_STARTER_FLEXINT6_MASK) -#define SYSCON_STARTER_PLU_MASK (0x100000U) -#define SYSCON_STARTER_PLU_SHIFT (20U) -/*! PLU - PLU interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PLU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PLU_SHIFT)) & SYSCON_STARTER_PLU_MASK) -#define SYSCON_STARTER_FLEXINT7_MASK (0x200000U) -#define SYSCON_STARTER_FLEXINT7_SHIFT (21U) -/*! FLEXINT7 - FLEXINT7 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT7_SHIFT)) & SYSCON_STARTER_FLEXINT7_MASK) -#define SYSCON_STARTER_SEC_VIO_MASK (0x200000U) -#define SYSCON_STARTER_SEC_VIO_SHIFT (21U) -/*! SEC_VIO - SEC_VIO interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_VIO_SHIFT)) & SYSCON_STARTER_SEC_VIO_MASK) -#define SYSCON_STARTER_ADC0_MASK (0x400000U) -#define SYSCON_STARTER_ADC0_SHIFT (22U) -/*! ADC0 - ADC0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SHIFT)) & SYSCON_STARTER_ADC0_MASK) -#define SYSCON_STARTER_SHA_MASK (0x400000U) -#define SYSCON_STARTER_SHA_SHIFT (22U) -/*! SHA - SHA interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SHA_SHIFT)) & SYSCON_STARTER_SHA_MASK) -#define SYSCON_STARTER_CASER_MASK (0x800000U) -#define SYSCON_STARTER_CASER_SHIFT (23U) -/*! CASER - CASER interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CASER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CASER_SHIFT)) & SYSCON_STARTER_CASER_MASK) -#define SYSCON_STARTER_ADC0_THCMP_OVR_MASK (0x1000000U) -#define SYSCON_STARTER_ADC0_THCMP_OVR_SHIFT (24U) -/*! ADC0_THCMP_OVR - ADC0_THCMP_OVR interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ADC0_THCMP_OVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_THCMP_OVR_SHIFT)) & SYSCON_STARTER_ADC0_THCMP_OVR_MASK) -#define SYSCON_STARTER_QDDKEY_MASK (0x1000000U) -#define SYSCON_STARTER_QDDKEY_SHIFT (24U) -/*! QDDKEY - QDDKEY interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_QDDKEY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_QDDKEY_SHIFT)) & SYSCON_STARTER_QDDKEY_MASK) -#define SYSCON_STARTER_PQ_MASK (0x2000000U) -#define SYSCON_STARTER_PQ_SHIFT (25U) -/*! PQ - PQ interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PQ_SHIFT)) & SYSCON_STARTER_PQ_MASK) -#define SYSCON_STARTER_SDMA1_MASK (0x4000000U) -#define SYSCON_STARTER_SDMA1_SHIFT (26U) -/*! SDMA1 - SDMA1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA1_SHIFT)) & SYSCON_STARTER_SDMA1_MASK) -#define SYSCON_STARTER_LSPI_HS_MASK (0x8000000U) -#define SYSCON_STARTER_LSPI_HS_SHIFT (27U) -/*! LSPI_HS - LSPI_HS interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_LSPI_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_LSPI_HS_SHIFT)) & SYSCON_STARTER_LSPI_HS_MASK) -#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U) -#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U) -/*! USB0_NEEDCLK - USB0_NEEDCLK interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK) -#define SYSCON_STARTER_USB0_MASK (0x10000000U) -#define SYSCON_STARTER_USB0_SHIFT (28U) -/*! USB0 - USB0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK) -#define SYSCON_STARTER_RTC_LITE0_MASK (0x20000000U) -#define SYSCON_STARTER_RTC_LITE0_SHIFT (29U) -/*! RTC_LITE0 - RTC_LITE0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_RTC_LITE0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_LITE0_SHIFT)) & SYSCON_STARTER_RTC_LITE0_MASK) -#define SYSCON_STARTER_EZH_ARCH_B0_MASK (0x40000000U) -#define SYSCON_STARTER_EZH_ARCH_B0_SHIFT (30U) -/*! EZH_ARCH_B0 - EZH_ARCH_B0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_EZH_ARCH_B0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_EZH_ARCH_B0_SHIFT)) & SYSCON_STARTER_EZH_ARCH_B0_MASK) -#define SYSCON_STARTER_WAKEUPPADS_MASK (0x80000000U) -#define SYSCON_STARTER_WAKEUPPADS_SHIFT (31U) -#define SYSCON_STARTER_WAKEUPPADS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUPPADS_SHIFT)) & SYSCON_STARTER_WAKEUPPADS_MASK) -#define SYSCON_STARTER_WAKEUP_MAILBOX0_MASK (0x80000000U) -#define SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT (31U) -/*! WAKEUP_MAILBOX0 - WAKEUP_MAILBOX0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_WAKEUP_MAILBOX0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT)) & SYSCON_STARTER_WAKEUP_MAILBOX0_MASK) -/*! @} */ - -/* The count of SYSCON_STARTER */ -#define SYSCON_STARTER_COUNT (2U) - -/*! @name STARTERSET - Set bits in STARTER */ -/*! @{ */ -#define SYSCON_STARTERSET_GPIO_INT04_SET_MASK (0x1U) -#define SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT (0U) -#define SYSCON_STARTERSET_GPIO_INT04_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT04_SET_MASK) -#define SYSCON_STARTERSET_SYS_SET_MASK (0x1U) -#define SYSCON_STARTERSET_SYS_SET_SHIFT (0U) -#define SYSCON_STARTERSET_SYS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SYS_SET_SHIFT)) & SYSCON_STARTERSET_SYS_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT05_SET_MASK (0x2U) -#define SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT (1U) -#define SYSCON_STARTERSET_GPIO_INT05_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT05_SET_MASK) -#define SYSCON_STARTERSET_SDMA0_SET_MASK (0x2U) -#define SYSCON_STARTERSET_SDMA0_SET_SHIFT (1U) -#define SYSCON_STARTERSET_SDMA0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA0_SET_SHIFT)) & SYSCON_STARTERSET_SDMA0_SET_MASK) -#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK (0x4U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT (2U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT06_SET_MASK (0x4U) -#define SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT (2U) -#define SYSCON_STARTERSET_GPIO_INT06_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT06_SET_MASK) -#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK (0x8U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT (3U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT07_SET_MASK (0x8U) -#define SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT (3U) -#define SYSCON_STARTERSET_GPIO_INT07_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT07_SET_MASK) -#define SYSCON_STARTERSET_CTIMER2_SET_MASK (0x10U) -#define SYSCON_STARTERSET_CTIMER2_SET_SHIFT (4U) -#define SYSCON_STARTERSET_CTIMER2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER2_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER2_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT00_SET_MASK (0x10U) -#define SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT (4U) -#define SYSCON_STARTERSET_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT00_SET_MASK) -#define SYSCON_STARTERSET_CTIMER4_SET_MASK (0x20U) -#define SYSCON_STARTERSET_CTIMER4_SET_SHIFT (5U) -#define SYSCON_STARTERSET_CTIMER4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER4_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER4_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT01_SET_MASK (0x20U) -#define SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT (5U) -#define SYSCON_STARTERSET_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT01_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT02_SET_MASK (0x40U) -#define SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT (6U) -#define SYSCON_STARTERSET_GPIO_INT02_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT02_SET_MASK) -#define SYSCON_STARTERSET_OS_EVENT_SET_MASK (0x40U) -#define SYSCON_STARTERSET_OS_EVENT_SET_SHIFT (6U) -#define SYSCON_STARTERSET_OS_EVENT_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_OS_EVENT_SET_SHIFT)) & SYSCON_STARTERSET_OS_EVENT_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT03_SET_MASK (0x80U) -#define SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT (7U) -#define SYSCON_STARTERSET_GPIO_INT03_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT03_SET_MASK) -#define SYSCON_STARTERSET_UTICK0_SET_MASK (0x100U) -#define SYSCON_STARTERSET_UTICK0_SET_SHIFT (8U) -#define SYSCON_STARTERSET_UTICK0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_UTICK0_SET_SHIFT)) & SYSCON_STARTERSET_UTICK0_SET_MASK) -#define SYSCON_STARTERSET_MRT0_SET_MASK (0x200U) -#define SYSCON_STARTERSET_MRT0_SET_SHIFT (9U) -#define SYSCON_STARTERSET_MRT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_MRT0_SET_SHIFT)) & SYSCON_STARTERSET_MRT0_SET_MASK) -#define SYSCON_STARTERSET_CTIMER0_SET_MASK (0x400U) -#define SYSCON_STARTERSET_CTIMER0_SET_SHIFT (10U) -#define SYSCON_STARTERSET_CTIMER0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER0_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER0_SET_MASK) -#define SYSCON_STARTERSET_SDIO_SET_MASK (0x400U) -#define SYSCON_STARTERSET_SDIO_SET_SHIFT (10U) -#define SYSCON_STARTERSET_SDIO_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDIO_SET_SHIFT)) & SYSCON_STARTERSET_SDIO_SET_MASK) -#define SYSCON_STARTERSET_CTIMER1_SET_MASK (0x800U) -#define SYSCON_STARTERSET_CTIMER1_SET_SHIFT (11U) -#define SYSCON_STARTERSET_CTIMER1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER1_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER1_SET_MASK) -#define SYSCON_STARTERSET_SCT0_SET_MASK (0x1000U) -#define SYSCON_STARTERSET_SCT0_SET_SHIFT (12U) -#define SYSCON_STARTERSET_SCT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SCT0_SET_SHIFT)) & SYSCON_STARTERSET_SCT0_SET_MASK) -#define SYSCON_STARTERSET_CTIMER3_SET_MASK (0x2000U) -#define SYSCON_STARTERSET_CTIMER3_SET_SHIFT (13U) -#define SYSCON_STARTERSET_CTIMER3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER3_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER3_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT0_SET_MASK (0x4000U) -#define SYSCON_STARTERSET_FLEXINT0_SET_SHIFT (14U) -#define SYSCON_STARTERSET_FLEXINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT0_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT1_SET_MASK (0x8000U) -#define SYSCON_STARTERSET_FLEXINT1_SET_SHIFT (15U) -#define SYSCON_STARTERSET_FLEXINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT1_SET_MASK) -#define SYSCON_STARTERSET_USB1_SET_MASK (0x8000U) -#define SYSCON_STARTERSET_USB1_SET_SHIFT (15U) -#define SYSCON_STARTERSET_USB1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB1_SET_SHIFT)) & SYSCON_STARTERSET_USB1_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT2_SET_MASK (0x10000U) -#define SYSCON_STARTERSET_FLEXINT2_SET_SHIFT (16U) -#define SYSCON_STARTERSET_FLEXINT2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT2_SET_MASK) -#define SYSCON_STARTERSET_USB1_NEEDCLK_SET_MASK (0x10000U) -#define SYSCON_STARTERSET_USB1_NEEDCLK_SET_SHIFT (16U) -#define SYSCON_STARTERSET_USB1_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB1_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB1_NEEDCLK_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT3_SET_MASK (0x20000U) -#define SYSCON_STARTERSET_FLEXINT3_SET_SHIFT (17U) -#define SYSCON_STARTERSET_FLEXINT3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT3_SET_MASK) -#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK (0x20000U) -#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT (17U) -#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT)) & SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT4_SET_MASK (0x40000U) -#define SYSCON_STARTERSET_FLEXINT4_SET_SHIFT (18U) -#define SYSCON_STARTERSET_FLEXINT4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT4_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT4_SET_MASK) -#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK (0x40000U) -#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT (18U) -#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT5_SET_MASK (0x80000U) -#define SYSCON_STARTERSET_FLEXINT5_SET_SHIFT (19U) -#define SYSCON_STARTERSET_FLEXINT5_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT5_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT5_SET_MASK) -#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK (0x80000U) -#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT (19U) -#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT6_SET_MASK (0x100000U) -#define SYSCON_STARTERSET_FLEXINT6_SET_SHIFT (20U) -#define SYSCON_STARTERSET_FLEXINT6_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT6_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT6_SET_MASK) -#define SYSCON_STARTERSET_PLU_SET_MASK (0x100000U) -#define SYSCON_STARTERSET_PLU_SET_SHIFT (20U) -#define SYSCON_STARTERSET_PLU_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PLU_SET_SHIFT)) & SYSCON_STARTERSET_PLU_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT7_SET_MASK (0x200000U) -#define SYSCON_STARTERSET_FLEXINT7_SET_SHIFT (21U) -#define SYSCON_STARTERSET_FLEXINT7_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT7_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT7_SET_MASK) -#define SYSCON_STARTERSET_SEC_VIO_SET_MASK (0x200000U) -#define SYSCON_STARTERSET_SEC_VIO_SET_SHIFT (21U) -#define SYSCON_STARTERSET_SEC_VIO_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_VIO_SET_SHIFT)) & SYSCON_STARTERSET_SEC_VIO_SET_MASK) -#define SYSCON_STARTERSET_ADC0_SET_MASK (0x400000U) -#define SYSCON_STARTERSET_ADC0_SET_SHIFT (22U) -#define SYSCON_STARTERSET_ADC0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_SET_MASK) -#define SYSCON_STARTERSET_SHA_SET_MASK (0x400000U) -#define SYSCON_STARTERSET_SHA_SET_SHIFT (22U) -#define SYSCON_STARTERSET_SHA_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SHA_SET_SHIFT)) & SYSCON_STARTERSET_SHA_SET_MASK) -#define SYSCON_STARTERSET_CASER_SET_MASK (0x800000U) -#define SYSCON_STARTERSET_CASER_SET_SHIFT (23U) -#define SYSCON_STARTERSET_CASER_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CASER_SET_SHIFT)) & SYSCON_STARTERSET_CASER_SET_MASK) -#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK (0x1000000U) -#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT (24U) -#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK) -#define SYSCON_STARTERSET_QDDKEY_SET_MASK (0x1000000U) -#define SYSCON_STARTERSET_QDDKEY_SET_SHIFT (24U) -#define SYSCON_STARTERSET_QDDKEY_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_QDDKEY_SET_SHIFT)) & SYSCON_STARTERSET_QDDKEY_SET_MASK) -#define SYSCON_STARTERSET_PQ_SET_MASK (0x2000000U) -#define SYSCON_STARTERSET_PQ_SET_SHIFT (25U) -#define SYSCON_STARTERSET_PQ_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PQ_SET_SHIFT)) & SYSCON_STARTERSET_PQ_SET_MASK) -#define SYSCON_STARTERSET_SDMA1_SET_MASK (0x4000000U) -#define SYSCON_STARTERSET_SDMA1_SET_SHIFT (26U) -#define SYSCON_STARTERSET_SDMA1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA1_SET_SHIFT)) & SYSCON_STARTERSET_SDMA1_SET_MASK) -#define SYSCON_STARTERSET_LSPI_HS_SET_MASK (0x8000000U) -#define SYSCON_STARTERSET_LSPI_HS_SET_SHIFT (27U) -#define SYSCON_STARTERSET_LSPI_HS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_LSPI_HS_SET_SHIFT)) & SYSCON_STARTERSET_LSPI_HS_SET_MASK) -#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK (0x8000000U) -#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT (27U) -#define SYSCON_STARTERSET_USB0_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK) -#define SYSCON_STARTERSET_USB0_SET_MASK (0x10000000U) -#define SYSCON_STARTERSET_USB0_SET_SHIFT (28U) -#define SYSCON_STARTERSET_USB0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_SET_SHIFT)) & SYSCON_STARTERSET_USB0_SET_MASK) -#define SYSCON_STARTERSET_RTC_LITE0_SET_MASK (0x20000000U) -#define SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT (29U) -#define SYSCON_STARTERSET_RTC_LITE0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT)) & SYSCON_STARTERSET_RTC_LITE0_SET_MASK) -#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK (0x40000000U) -#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT (30U) -#define SYSCON_STARTERSET_EZH_ARCH_B0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT)) & SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK) -#define SYSCON_STARTERSET_WAKEUPPADS_SET_MASK (0x80000000U) -#define SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT (31U) -#define SYSCON_STARTERSET_WAKEUPPADS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUPPADS_SET_MASK) -#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK (0x80000000U) -#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT (31U) -#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERSET */ -#define SYSCON_STARTERSET_COUNT (2U) - -/*! @name STARTERCLR - Clear bits in STARTER */ -/*! @{ */ -#define SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK (0x1U) -#define SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT (0U) -#define SYSCON_STARTERCLR_GPIO_INT04_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK) -#define SYSCON_STARTERCLR_SYS_CLR_MASK (0x1U) -#define SYSCON_STARTERCLR_SYS_CLR_SHIFT (0U) -#define SYSCON_STARTERCLR_SYS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SYS_CLR_SHIFT)) & SYSCON_STARTERCLR_SYS_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK (0x2U) -#define SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT (1U) -#define SYSCON_STARTERCLR_GPIO_INT05_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK) -#define SYSCON_STARTERCLR_SDMA0_CLR_MASK (0x2U) -#define SYSCON_STARTERCLR_SDMA0_CLR_SHIFT (1U) -#define SYSCON_STARTERCLR_SDMA0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA0_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA0_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK (0x4U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT (2U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK (0x4U) -#define SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT (2U) -#define SYSCON_STARTERCLR_GPIO_INT06_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK (0x8U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT (3U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK (0x8U) -#define SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT (3U) -#define SYSCON_STARTERCLR_GPIO_INT07_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER2_CLR_MASK (0x10U) -#define SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT (4U) -#define SYSCON_STARTERCLR_CTIMER2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER2_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK (0x10U) -#define SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT (4U) -#define SYSCON_STARTERCLR_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER4_CLR_MASK (0x20U) -#define SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT (5U) -#define SYSCON_STARTERCLR_CTIMER4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER4_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK (0x20U) -#define SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT (5U) -#define SYSCON_STARTERCLR_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK (0x40U) -#define SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT (6U) -#define SYSCON_STARTERCLR_GPIO_INT02_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK) -#define SYSCON_STARTERCLR_OS_EVENT_CLR_MASK (0x40U) -#define SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT (6U) -#define SYSCON_STARTERCLR_OS_EVENT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT)) & SYSCON_STARTERCLR_OS_EVENT_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK (0x80U) -#define SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT (7U) -#define SYSCON_STARTERCLR_GPIO_INT03_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK) -#define SYSCON_STARTERCLR_UTICK0_CLR_MASK (0x100U) -#define SYSCON_STARTERCLR_UTICK0_CLR_SHIFT (8U) -#define SYSCON_STARTERCLR_UTICK0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_UTICK0_CLR_SHIFT)) & SYSCON_STARTERCLR_UTICK0_CLR_MASK) -#define SYSCON_STARTERCLR_MRT0_CLR_MASK (0x200U) -#define SYSCON_STARTERCLR_MRT0_CLR_SHIFT (9U) -#define SYSCON_STARTERCLR_MRT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_MRT0_CLR_SHIFT)) & SYSCON_STARTERCLR_MRT0_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER0_CLR_MASK (0x400U) -#define SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT (10U) -#define SYSCON_STARTERCLR_CTIMER0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER0_CLR_MASK) -#define SYSCON_STARTERCLR_SDIO_CLR_MASK (0x400U) -#define SYSCON_STARTERCLR_SDIO_CLR_SHIFT (10U) -#define SYSCON_STARTERCLR_SDIO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDIO_CLR_SHIFT)) & SYSCON_STARTERCLR_SDIO_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER1_CLR_MASK (0x800U) -#define SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT (11U) -#define SYSCON_STARTERCLR_CTIMER1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER1_CLR_MASK) -#define SYSCON_STARTERCLR_SCT0_CLR_MASK (0x1000U) -#define SYSCON_STARTERCLR_SCT0_CLR_SHIFT (12U) -#define SYSCON_STARTERCLR_SCT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SCT0_CLR_SHIFT)) & SYSCON_STARTERCLR_SCT0_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER3_CLR_MASK (0x2000U) -#define SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT (13U) -#define SYSCON_STARTERCLR_CTIMER3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER3_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT0_CLR_MASK (0x4000U) -#define SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT (14U) -#define SYSCON_STARTERCLR_FLEXINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT0_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT1_CLR_MASK (0x8000U) -#define SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT (15U) -#define SYSCON_STARTERCLR_FLEXINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT1_CLR_MASK) -#define SYSCON_STARTERCLR_USB1_CLR_MASK (0x8000U) -#define SYSCON_STARTERCLR_USB1_CLR_SHIFT (15U) -#define SYSCON_STARTERCLR_USB1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB1_CLR_SHIFT)) & SYSCON_STARTERCLR_USB1_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT2_CLR_MASK (0x10000U) -#define SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT (16U) -#define SYSCON_STARTERCLR_FLEXINT2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT2_CLR_MASK) -#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_MASK (0x10000U) -#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_SHIFT (16U) -#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT3_CLR_MASK (0x20000U) -#define SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT (17U) -#define SYSCON_STARTERCLR_FLEXINT3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT3_CLR_MASK) -#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK (0x20000U) -#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT (17U) -#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT4_CLR_MASK (0x40000U) -#define SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT (18U) -#define SYSCON_STARTERCLR_FLEXINT4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT4_CLR_MASK) -#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK (0x40000U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT (18U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT5_CLR_MASK (0x80000U) -#define SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT (19U) -#define SYSCON_STARTERCLR_FLEXINT5_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT5_CLR_MASK) -#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK (0x80000U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT (19U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT6_CLR_MASK (0x100000U) -#define SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT (20U) -#define SYSCON_STARTERCLR_FLEXINT6_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT6_CLR_MASK) -#define SYSCON_STARTERCLR_PLU_CLR_MASK (0x100000U) -#define SYSCON_STARTERCLR_PLU_CLR_SHIFT (20U) -#define SYSCON_STARTERCLR_PLU_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PLU_CLR_SHIFT)) & SYSCON_STARTERCLR_PLU_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT7_CLR_MASK (0x200000U) -#define SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT (21U) -#define SYSCON_STARTERCLR_FLEXINT7_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT7_CLR_MASK) -#define SYSCON_STARTERCLR_SEC_VIO_CLR_MASK (0x200000U) -#define SYSCON_STARTERCLR_SEC_VIO_CLR_SHIFT (21U) -#define SYSCON_STARTERCLR_SEC_VIO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_VIO_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_VIO_CLR_MASK) -#define SYSCON_STARTERCLR_ADC0_CLR_MASK (0x400000U) -#define SYSCON_STARTERCLR_ADC0_CLR_SHIFT (22U) -#define SYSCON_STARTERCLR_ADC0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_CLR_MASK) -#define SYSCON_STARTERCLR_SHA_CLR_MASK (0x400000U) -#define SYSCON_STARTERCLR_SHA_CLR_SHIFT (22U) -#define SYSCON_STARTERCLR_SHA_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SHA_CLR_SHIFT)) & SYSCON_STARTERCLR_SHA_CLR_MASK) -#define SYSCON_STARTERCLR_CASER_CLR_MASK (0x800000U) -#define SYSCON_STARTERCLR_CASER_CLR_SHIFT (23U) -#define SYSCON_STARTERCLR_CASER_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CASER_CLR_SHIFT)) & SYSCON_STARTERCLR_CASER_CLR_MASK) -#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK (0x1000000U) -#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT (24U) -#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK) -#define SYSCON_STARTERCLR_QDDKEY_CLR_MASK (0x1000000U) -#define SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT (24U) -#define SYSCON_STARTERCLR_QDDKEY_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT)) & SYSCON_STARTERCLR_QDDKEY_CLR_MASK) -#define SYSCON_STARTERCLR_PQ_CLR_MASK (0x2000000U) -#define SYSCON_STARTERCLR_PQ_CLR_SHIFT (25U) -#define SYSCON_STARTERCLR_PQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PQ_CLR_SHIFT)) & SYSCON_STARTERCLR_PQ_CLR_MASK) -#define SYSCON_STARTERCLR_SDMA1_CLR_MASK (0x4000000U) -#define SYSCON_STARTERCLR_SDMA1_CLR_SHIFT (26U) -#define SYSCON_STARTERCLR_SDMA1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA1_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA1_CLR_MASK) -#define SYSCON_STARTERCLR_LSPI_HS_CLR_MASK (0x8000000U) -#define SYSCON_STARTERCLR_LSPI_HS_CLR_SHIFT (27U) -#define SYSCON_STARTERCLR_LSPI_HS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_LSPI_HS_CLR_SHIFT)) & SYSCON_STARTERCLR_LSPI_HS_CLR_MASK) -#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK (0x8000000U) -#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT (27U) -#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK) -#define SYSCON_STARTERCLR_USB0_CLR_MASK (0x10000000U) -#define SYSCON_STARTERCLR_USB0_CLR_SHIFT (28U) -#define SYSCON_STARTERCLR_USB0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_CLR_MASK) -#define SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK (0x20000000U) -#define SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT (29U) -#define SYSCON_STARTERCLR_RTC_LITE0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT)) & SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK) -#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK (0x40000000U) -#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT (30U) -#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT)) & SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK) -#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK (0x80000000U) -#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT (31U) -#define SYSCON_STARTERCLR_WAKEUPPADS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK) -#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK (0x80000000U) -#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT (31U) -#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERCLR */ -#define SYSCON_STARTERCLR_COUNT (2U) - -/*! @name HARDWARESLEEP - Hardware Sleep control */ -/*! @{ */ -#define SYSCON_HARDWARESLEEP_FORCED_MASK (0x1U) -#define SYSCON_HARDWARESLEEP_FORCED_SHIFT (0U) -#define SYSCON_HARDWARESLEEP_FORCED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_FORCED_SHIFT)) & SYSCON_HARDWARESLEEP_FORCED_MASK) -#define SYSCON_HARDWARESLEEP_PERIPHERALS_MASK (0x2U) -#define SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT (1U) -#define SYSCON_HARDWARESLEEP_PERIPHERALS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT)) & SYSCON_HARDWARESLEEP_PERIPHERALS_MASK) -#define SYSCON_HARDWARESLEEP_SDMA0_MASK (0x8U) -#define SYSCON_HARDWARESLEEP_SDMA0_SHIFT (3U) -#define SYSCON_HARDWARESLEEP_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA0_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA0_MASK) -#define SYSCON_HARDWARESLEEP_SDMA1_MASK (0x20U) -#define SYSCON_HARDWARESLEEP_SDMA1_SHIFT (5U) -#define SYSCON_HARDWARESLEEP_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA1_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA1_MASK) -/*! @} */ - -/*! @name CPUCTRL - CPU Control for multiple processors */ -/*! @{ */ -#define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U) -#define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U) -/*! CPU1CLKEN - CPU1 clock enable. - * 0b1..The CPU1 clock is enabled. - * 0b0..The CPU1 clock is not enabled. - */ -#define SYSCON_CPUCTRL_CPU1CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK) -#define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U) -#define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U) -/*! CPU1RSTEN - CPU1 reset. - * 0b1..The CPU1 is being reset. - * 0b0..The CPU1 is not being reset. - */ -#define SYSCON_CPUCTRL_CPU1RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK) -/*! @} */ - -/*! @name CPBOOT - Coprocessor Boot Address */ -/*! @{ */ -#define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFFFFU) -#define SYSCON_CPBOOT_CPBOOT_SHIFT (0U) -#define SYSCON_CPBOOT_CPBOOT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK) -/*! @} */ - -/*! @name CPSTACK - Coprocessor Stack Address */ -/*! @{ */ -#define SYSCON_CPSTACK_CPSTACK_MASK (0xFFFFFFFFU) -#define SYSCON_CPSTACK_CPSTACK_SHIFT (0U) -#define SYSCON_CPSTACK_CPSTACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTACK_CPSTACK_SHIFT)) & SYSCON_CPSTACK_CPSTACK_MASK) -/*! @} */ - -/*! @name CPSTAT - CPU Status */ -/*! @{ */ -#define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U) -#define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U) -/*! CPU0SLEEPING - The CPU0 sleeping state. - * 0b1..the CPU is sleeping. - * 0b0..the CPU is not sleeping. - */ -#define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK) -#define SYSCON_CPSTAT_CPU1SLEEPING_MASK (0x2U) -#define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT (1U) -/*! CPU1SLEEPING - The CPU1 sleeping state. - * 0b1..the CPU is sleeping. - * 0b0..the CPU is not sleeping. - */ -#define SYSCON_CPSTAT_CPU1SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK) -#define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U) -#define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U) -/*! CPU0LOCKUP - The CPU0 lockup state. - * 0b1..the CPU is in lockup. - * 0b0..the CPU is not in lockup. - */ -#define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK) -#define SYSCON_CPSTAT_CPU1LOCKUP_MASK (0x8U) -#define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT (3U) -/*! CPU1LOCKUP - The CPU1 lockup state. - * 0b1..the CPU is in lockup. - * 0b0..the CPU is not in lockup. - */ -#define SYSCON_CPSTAT_CPU1LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK) -/*! @} */ - -/*! @name DICE_REG0 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG0_DICE_REG0_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG0_DICE_REG0_SHIFT (0U) -#define SYSCON_DICE_REG0_DICE_REG0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG0_DICE_REG0_SHIFT)) & SYSCON_DICE_REG0_DICE_REG0_MASK) -/*! @} */ - -/*! @name DICE_REG1 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG1_DICE_REG1_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG1_DICE_REG1_SHIFT (0U) -#define SYSCON_DICE_REG1_DICE_REG1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG1_DICE_REG1_SHIFT)) & SYSCON_DICE_REG1_DICE_REG1_MASK) -/*! @} */ - -/*! @name DICE_REG2 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG2_DICE_REG2_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG2_DICE_REG2_SHIFT (0U) -#define SYSCON_DICE_REG2_DICE_REG2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG2_DICE_REG2_SHIFT)) & SYSCON_DICE_REG2_DICE_REG2_MASK) -/*! @} */ - -/*! @name DICE_REG3 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG3_DICE_REG3_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG3_DICE_REG3_SHIFT (0U) -#define SYSCON_DICE_REG3_DICE_REG3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG3_DICE_REG3_SHIFT)) & SYSCON_DICE_REG3_DICE_REG3_MASK) -/*! @} */ - -/*! @name DICE_REG4 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG4_DICE_REG4_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG4_DICE_REG4_SHIFT (0U) -#define SYSCON_DICE_REG4_DICE_REG4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG4_DICE_REG4_SHIFT)) & SYSCON_DICE_REG4_DICE_REG4_MASK) -/*! @} */ - -/*! @name DICE_REG5 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG5_DICE_REG5_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG5_DICE_REG5_SHIFT (0U) -#define SYSCON_DICE_REG5_DICE_REG5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG5_DICE_REG5_SHIFT)) & SYSCON_DICE_REG5_DICE_REG5_MASK) -/*! @} */ - -/*! @name DICE_REG6 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG6_DICE_REG6_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG6_DICE_REG6_SHIFT (0U) -#define SYSCON_DICE_REG6_DICE_REG6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG6_DICE_REG6_SHIFT)) & SYSCON_DICE_REG6_DICE_REG6_MASK) -/*! @} */ - -/*! @name DICE_REG7 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG7_DICE_REG7_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG7_DICE_REG7_SHIFT (0U) -#define SYSCON_DICE_REG7_DICE_REG7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG7_DICE_REG7_SHIFT)) & SYSCON_DICE_REG7_DICE_REG7_MASK) -/*! @} */ - -/*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */ -/*! @{ */ -#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_MASK (0x1U) -#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_SHIFT (0U) -/*! FLASH48MHZ_ENA - Enable Flash 48 MHz clock. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_MASK) -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) -/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) -/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) -/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) -/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) -#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) -#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) -/*! CLKIN_ENA - Enable clock_in clock for clock module. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) -/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) -/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) -/*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) -/*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK) -/*! @} */ - -/*! @name COMP_INT_CTRL - Comparator Interrupt control */ -/*! @{ */ -#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) -#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) -/*! INT_ENABLE - Analog Comparator interrupt enable control:. - * 0b1..interrupt enable. - * 0b0..interrupt disable. - */ -#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) -#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) -#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) -/*! INT_CLEAR - Analog Comparator interrupt clear. - * 0b0..No effect. - * 0b1..Clear the interrupt. Self-cleared bit. - */ -#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) -#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) -#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) -/*! INT_CTRL - Comparator interrupt type selector:. - * 0b000..The analog comparator interrupt edge sensitive is disabled. - * 0b010..analog comparator interrupt is rising edge sensitive. - * 0b100..analog comparator interrupt is falling edge sensitive. - * 0b110..analog comparator interrupt is rising and falling edge sensitive. - * 0b001..The analog comparator interrupt level sensitive is disabled. - * 0b011..Analog Comparator interrupt is high level sensitive. - * 0b101..Analog Comparator interrupt is low level sensitive. - * 0b111..The analog comparator interrupt level sensitive is disabled. - */ -#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) -#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) -#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) -/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. - * 0b0..Select Analog Comparator filtered output as input for interrupt detection. - * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when Analog comparator is used as wake up source in Power down mode. - */ -#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK) -/*! @} */ - -/*! @name COMP_INT_STATUS - Comparator Interrupt status */ -/*! @{ */ -#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) -#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) -/*! STATUS - Interrupt status BEFORE Interrupt Enable. - * 0b0..no interrupt pending. - * 0b1..interrupt pending. - */ -#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) -#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) -#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) -/*! INT_STATUS - Interrupt status AFTER Interrupt Enable. - * 0b0..no interrupt pending. - * 0b1..interrupt pending. - */ -#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) -#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) -#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) -/*! VAL - comparator analog output. - * 0b1..P+ is greater than P-. - * 0b0..P+ is smaller than P-. - */ -#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK) -/*! @} */ - -/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ -/*! @{ */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) -/*! ROM - Control automatic clock gating of ROM controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U) -/*! RAMX_CTRL - Control automatic clock gating of RAMX controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U) -/*! RAM0_CTRL - Control automatic clock gating of RAM0 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U) -/*! RAM1_CTRL - Control automatic clock gating of RAM1 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U) -/*! RAM2_CTRL - Control automatic clock gating of RAM2 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK (0x20U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT (5U) -/*! RAM3_CTRL - Control automatic clock gating of RAM3 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK (0x40U) -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT (6U) -/*! RAM4_CTRL - Control automatic clock gating of RAM4 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) -/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) -/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH_MASK (0x200U) -#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH_SHIFT (9U) -/*! FLASH - Control automatic clock gating of FLASH controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_FLASH_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_FLASH_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_FMC_MASK (0x400U) -#define SYSCON_AUTOCLKGATEOVERRIDE_FMC_SHIFT (10U) -/*! FMC - Control automatic clock gating of FMC controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_FMC_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_FMC_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) -/*! CRCGEN - Control automatic clock gating of CRCGEN controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) -/*! SDMA0 - Control automatic clock gating of DMA0 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) -/*! SDMA1 - Control automatic clock gating of DMA1 controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_USB_MASK (0x4000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_USB_SHIFT (14U) -/*! USB - Control automatic clock gating of USB controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_USB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) -/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) -/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. - * 0b1100000011011110..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0000000000000000..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) -/*! @} */ - -/*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */ -/*! @{ */ -#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) -#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) -/*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. - * 0b1..bypass of the first stage of synchonization inside GPIO_INT module. - * 0b0..use the first stage of synchonization inside GPIO_INT module. - */ -#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) -/*! @} */ - -/*! @name DEBUG_LOCK_EN - Control write access to security registers -- FOR INTERNAl USE ONLY */ -/*! @{ */ -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) -/*! LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, CODESECURITYPROTCPU1, CM33_DEBUG_FEATURES, MCM33_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. - * 0b1010..1010: Enable write access to all 6 registers. - * 0b0000..Any other value than b1010: disable write access to all 6 registers. - */ -#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) -/*! @} */ - -/*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY */ -/*! @{ */ -#define SYSCON_DEBUG_FEATURES_CM33_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_CM33_DBGEN_SHIFT (0U) -/*! CM33_DBGEN - CM33 (CPU0) Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_DBGEN_MASK) -#define SYSCON_DEBUG_FEATURES_CM33_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_CM33_NIDEN_SHIFT (2U) -/*! CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_NIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN_SHIFT (4U) -/*! CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_SPIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_SHIFT (6U) -/*! CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN_MASK (0x300U) -#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN_SHIFT (8U) -/*! MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_MCM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_MCM33_DBGEN_MASK) -#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN_MASK (0xC00U) -#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN_SHIFT (10U) -/*! MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_MCM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_MCM33_NIDEN_MASK) -/*! @} */ - -/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY */ -/*! @{ */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_SHIFT (0U) -/*! CM33_DBGEN - CM33 (CPU0) Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_SHIFT (2U) -/*! CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_SHIFT (4U) -/*! CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_SHIFT (6U) -/*! CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_MASK (0x300U) -#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_SHIFT (8U) -/*! MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_MASK (0xC00U) -#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_SHIFT (10U) -/*! MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:. - * 0b10..10: Invasive debug is enabled. - * 0b01..Any other value than b10: invasive debug is disable. - */ -#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_MASK) -/*! @} */ - -/*! @name CODESECURITYPROTTEST - Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY */ -/*! @{ */ -#define SYSCON_CODESECURITYPROTTEST_SEC_CODE_MASK (0xFFFFFFFFU) -#define SYSCON_CODESECURITYPROTTEST_SEC_CODE_SHIFT (0U) -/*! SEC_CODE - Security code to allow test access : 0x12345678. - * 0b00010010001101000101011001111000..Security code to allow test access. - * 0b00000000000000000000000000000000..test access is not allowed. - */ -#define SYSCON_CODESECURITYPROTTEST_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTTEST_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTTEST_SEC_CODE_MASK) -/*! @} */ - -/*! @name CODESECURITYPROTCPU0 - Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY */ -/*! @{ */ -#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE_MASK (0xFFFFFFFFU) -#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE_SHIFT (0U) -/*! SEC_CODE - Security code to allow CPU0 DAP: 0x12345678. - * 0b00010010001101000101011001111000..Security code to allow CPU0 DAP. - * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. - */ -#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTCPU0_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTCPU0_SEC_CODE_MASK) -/*! @} */ - -/*! @name CODESECURITYPROTCPU1 - Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY */ -/*! @{ */ -#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE_MASK (0xFFFFFFFFU) -#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE_SHIFT (0U) -/*! SEC_CODE - Security code to allow CPU1 DAP: 0x12345678. - * 0b00010010001101000101011001111000..Security code to allow CPU1 DAP. - * 0b00000000000000000000000000000000..CPU1 DAP is not allowed. - */ -#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTCPU1_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTCPU1_SEC_CODE_MASK) -/*! @} */ - -/*! @name KEY_BLOCK - block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY */ -/*! @{ */ -#define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU) -#define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U) -#define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK) -/*! @} */ - -/*! @name DEBUG_AUTH_SCRATCH - Debug authentication scratch registers -- FOR INTERNAL USE ONLY */ -/*! @{ */ -#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_MASK (0xFFFFFFFFU) -#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_SHIFT (0U) -#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_SHIFT)) & SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_MASK) -/*! @} */ - -/*! @name CPUCFG - CPUs configuration register */ -/*! @{ */ -#define SYSCON_CPUCFG_CPU1ENABLE_MASK (0x4U) -#define SYSCON_CPUCFG_CPU1ENABLE_SHIFT (2U) -/*! CPU1ENABLE - Enable CPU1. - * 0b0..CPU1 is disable (Processor in reset). - * 0b1..CPU1 is enable. - */ -#define SYSCON_CPUCFG_CPU1ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCFG_CPU1ENABLE_SHIFT)) & SYSCON_CPUCFG_CPU1ENABLE_MASK) -/*! @} */ - -/*! @name PERIPHENCFG - peripheral enable configuration -- FOR INTERNAL USE ONLY */ -/*! @{ */ -#define SYSCON_PERIPHENCFG_SCTEN_MASK (0x1U) -#define SYSCON_PERIPHENCFG_SCTEN_SHIFT (0U) -/*! SCTEN - SCT enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_SCTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_SCTEN_SHIFT)) & SYSCON_PERIPHENCFG_SCTEN_MASK) -#define SYSCON_PERIPHENCFG_ADCEN_MASK (0x2U) -#define SYSCON_PERIPHENCFG_ADCEN_SHIFT (1U) -/*! ADCEN - ADC enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_ADCEN_SHIFT)) & SYSCON_PERIPHENCFG_ADCEN_MASK) -#define SYSCON_PERIPHENCFG_USB0EN_MASK (0x4U) -#define SYSCON_PERIPHENCFG_USB0EN_SHIFT (2U) -/*! USB0EN - USB0 enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_USB0EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_USB0EN_SHIFT)) & SYSCON_PERIPHENCFG_USB0EN_MASK) -#define SYSCON_PERIPHENCFG_PUFFEN_MASK (0x40U) -#define SYSCON_PERIPHENCFG_PUFFEN_SHIFT (6U) -/*! PUFFEN - Puff enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_PUFFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_PUFFEN_SHIFT)) & SYSCON_PERIPHENCFG_PUFFEN_MASK) -#define SYSCON_PERIPHENCFG_USB1EN_MASK (0x400U) -#define SYSCON_PERIPHENCFG_USB1EN_SHIFT (10U) -/*! USB1EN - USB1 enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_USB1EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_USB1EN_SHIFT)) & SYSCON_PERIPHENCFG_USB1EN_MASK) -#define SYSCON_PERIPHENCFG_SDIOEN_MASK (0x800U) -#define SYSCON_PERIPHENCFG_SDIOEN_SHIFT (11U) -/*! SDIOEN - SDIO enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_SDIOEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_SDIOEN_SHIFT)) & SYSCON_PERIPHENCFG_SDIOEN_MASK) -#define SYSCON_PERIPHENCFG_HASHEN_MASK (0x1000U) -#define SYSCON_PERIPHENCFG_HASHEN_SHIFT (12U) -/*! HASHEN - HASH enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_HASHEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_HASHEN_SHIFT)) & SYSCON_PERIPHENCFG_HASHEN_MASK) -#define SYSCON_PERIPHENCFG_PRINCEEN_MASK (0x4000U) -#define SYSCON_PERIPHENCFG_PRINCEEN_SHIFT (14U) -/*! PRINCEEN - PRINCE enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_PRINCEEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_PRINCEEN_SHIFT)) & SYSCON_PERIPHENCFG_PRINCEEN_MASK) -/*! @} */ - -/*! @name DEVICE_ID0 - Device ID */ -/*! @{ */ -#define SYSCON_DEVICE_ID0_PARTCONFIG_MASK (0xFFU) -#define SYSCON_DEVICE_ID0_PARTCONFIG_SHIFT (0U) -#define SYSCON_DEVICE_ID0_PARTCONFIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTCONFIG_SHIFT)) & SYSCON_DEVICE_ID0_PARTCONFIG_MASK) -#define SYSCON_DEVICE_ID0_SRAM_SIZE_MASK (0xF00U) -#define SYSCON_DEVICE_ID0_SRAM_SIZE_SHIFT (8U) -#define SYSCON_DEVICE_ID0_SRAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_SRAM_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_SRAM_SIZE_MASK) -#define SYSCON_DEVICE_ID0_FLASH_SIZE_MASK (0x7000U) -#define SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT (12U) -#define SYSCON_DEVICE_ID0_FLASH_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_FLASH_SIZE_MASK) -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) -#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) -#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_MASK (0x7000000U) -#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_SHIFT (24U) -#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_SHIFT)) & SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_MASK) -/*! @} */ - -/*! @name DIEID - Chip revision ID and Number */ -/*! @{ */ -#define SYSCON_DIEID_REV_ID_MASK (0xFU) -#define SYSCON_DIEID_REV_ID_SHIFT (0U) -#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) -#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCON_Register_Masks */ - - -/* SYSCON - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral SYSCON base address */ - #define SYSCON_BASE (0x50000000u) - /** Peripheral SYSCON base address */ - #define SYSCON_BASE_NS (0x40000000u) - /** Peripheral SYSCON base pointer */ - #define SYSCON ((SYSCON_Type *)SYSCON_BASE) - /** Peripheral SYSCON base pointer */ - #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS { SYSCON_BASE } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS { SYSCON } - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS_NS { SYSCON_NS } -#else - /** Peripheral SYSCON base address */ - #define SYSCON_BASE (0x40000000u) - /** Peripheral SYSCON base pointer */ - #define SYSCON ((SYSCON_Type *)SYSCON_BASE) - /** Array initializer of SYSCON peripheral base addresses */ - #define SYSCON_BASE_ADDRS { SYSCON_BASE } - /** Array initializer of SYSCON peripheral base pointers */ - #define SYSCON_BASE_PTRS { SYSCON } -#endif - -/*! - * @} - */ /* end of group SYSCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCTL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer - * @{ - */ - -/** SYSCTL - Register Layout Typedef */ -typedef struct { - __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */ - uint8_t RESERVED_0[60]; - __IO uint32_t FCCTRLSEL[8]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_1[32]; - __IO uint32_t SHAREDCTRLSET[2]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[120]; - __I uint32_t USB_HS_STATUS; /**< Status register for USB HS, offset: 0x100 */ -} SYSCTL_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCTL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks - * @{ - */ - -/*! @name UPDATELCKOUT - update lock out control */ -/*! @{ */ -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) -/*! UPDATELCKOUT - All Registers - * 0b0..Normal Mode. Can be written to. - * 0b1..Protected Mode. Cannot be written to. - */ -#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK) -/*! @} */ - -/*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */ -/*! @{ */ -#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) -#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) -/*! SCKINSEL - Selects the source for SCK going into this Flexcomm. - * 0b00..Selects the dedicated FCn_SCK function for this Flexcomm. - * 0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) -#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) -#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) -/*! WSINSEL - Selects the source for WS going into this Flexcomm. - * 0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. - * 0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) -#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) -#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) -/*! DATAINSEL - Selects the source for DATA input to this Flexcomm. - * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. - * 0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) -#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) -#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) -/*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm. - * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. - * 0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). - * 0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). - * 0b11..Reserved. - */ -#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK) -/*! @} */ - -/* The count of SYSCTL_FCCTRLSEL */ -#define SYSCTL_FCCTRLSEL_COUNT (8U) - -/*! @name SHARECTRLSET_SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ -/*! @{ */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) -/*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set. - * 0b000..SCK for this shared signal set comes from Flexcomm 0. - * 0b001..SCK for this shared signal set comes from Flexcomm 1. - * 0b010..SCK for this shared signal set comes from Flexcomm 2. - * 0b011..SCK for this shared signal set comes from Flexcomm 3. - * 0b100..SCK for this shared signal set comes from Flexcomm 4. - * 0b101..SCK for this shared signal set comes from Flexcomm 5. - * 0b110..SCK for this shared signal set comes from Flexcomm 6. - * 0b111..SCK for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) -/*! SHAREDWSSEL - Selects the source for WS of this shared signal set. - * 0b000..WS for this shared signal set comes from Flexcomm 0. - * 0b001..WS for this shared signal set comes from Flexcomm 1. - * 0b010..WS for this shared signal set comes from Flexcomm 2. - * 0b011..WS for this shared signal set comes from Flexcomm 3. - * 0b100..WS for this shared signal set comes from Flexcomm 4. - * 0b101..WS for this shared signal set comes from Flexcomm 5. - * 0b110..WS for this shared signal set comes from Flexcomm 6. - * 0b111..WS for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) -/*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set. - * 0b000..DATA input for this shared signal set comes from Flexcomm 0. - * 0b001..DATA input for this shared signal set comes from Flexcomm 1. - * 0b010..DATA input for this shared signal set comes from Flexcomm 2. - * 0b011..DATA input for this shared signal set comes from Flexcomm 3. - * 0b100..DATA input for this shared signal set comes from Flexcomm 4. - * 0b101..DATA input for this shared signal set comes from Flexcomm 5. - * 0b110..DATA input for this shared signal set comes from Flexcomm 6. - * 0b111..DATA input for this shared signal set comes from Flexcomm 7. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) -/*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC0 does not contribute to this shared set. - * 0b1..Data output from FC0 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) -/*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC1 does not contribute to this shared set. - * 0b1..Data output from FC1 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK (0x40000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_SHIFT (18U) -/*! F20DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC2 does not contribute to this shared set. - * 0b1..Data output from FC2 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_MASK (0x80000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT (19U) -/*! FC3DATAOUTEN - Controls FC3 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC3 does not contribute to this shared set. - * 0b1..Data output from FC3 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) -/*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC4 does not contribute to this shared set. - * 0b1..Data output from FC4 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) -/*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC5 does not contribute to this shared set. - * 0b1..Data output from FC5 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) -/*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC6 does not contribute to this shared set. - * 0b1..Data output from FC6 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) -/*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC7 does not contribute to this shared set. - * 0b1..Data output from FC7 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK) -/*! @} */ - -/* The count of SYSCTL_SHARECTRLSET_SHAREDCTRLSET */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_COUNT (2U) - -/*! @name USB_HS_STATUS - Status register for USB HS */ -/*! @{ */ -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U) -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U) -/*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. - * 0b0..3v3 supply is good. - * 0b1..3v3 supply is too low. - */ -#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCTL_Register_Masks */ - - -/* SYSCTL - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE (0x50023000u) - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE_NS (0x40023000u) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS { SYSCTL } - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } -#else - /** Peripheral SYSCTL base address */ - #define SYSCTL_BASE (0x40023000u) - /** Peripheral SYSCTL base pointer */ - #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) - /** Array initializer of SYSCTL peripheral base addresses */ - #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } - /** Array initializer of SYSCTL peripheral base pointers */ - #define SYSCTL_BASE_PTRS { SYSCTL } -#endif - -/*! - * @} - */ /* end of group SYSCTL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer - * @{ - */ - -/** USART - Register Layout Typedef */ -typedef struct { - __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ - __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ - __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ - uint8_t RESERVED_0[12]; - __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ - __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ - __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ - __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ - uint8_t RESERVED_1[3536]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_2[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_3[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_4[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_6[440]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} USART_Type; - -/* ---------------------------------------------------------------------------- - -- USART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Register_Masks USART Register Masks - * @{ - */ - -/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ -/*! @{ */ -#define USART_CFG_ENABLE_MASK (0x1U) -#define USART_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - USART Enable. - * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. - * 0b1..Enabled. The USART is enabled for operation. - */ -#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) -#define USART_CFG_DATALEN_MASK (0xCU) -#define USART_CFG_DATALEN_SHIFT (2U) -/*! DATALEN - Selects the data size for the USART. - * 0b00..7 bit Data length. - * 0b01..8 bit Data length. - * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. - * 0b11..Reserved. - */ -#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) -#define USART_CFG_PARITYSEL_MASK (0x30U) -#define USART_CFG_PARITYSEL_SHIFT (4U) -/*! PARITYSEL - Selects what type of parity is used by the USART. - * 0b00..No parity. - * 0b01..Reserved. - * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. - * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. - */ -#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) -#define USART_CFG_STOPLEN_MASK (0x40U) -#define USART_CFG_STOPLEN_SHIFT (6U) -/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. - * 0b0..1 stop bit. - * 0b1..2 stop bits. This setting should only be used for asynchronous communication. - */ -#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) -#define USART_CFG_MODE32K_MASK (0x80U) -#define USART_CFG_MODE32K_SHIFT (7U) -/*! MODE32K - Selects standard or 32 kHz clocking mode. - * 0b0..Disabled. USART uses standard clocking. - * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. - */ -#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) -#define USART_CFG_LINMODE_MASK (0x100U) -#define USART_CFG_LINMODE_SHIFT (8U) -/*! LINMODE - LIN break mode enable. - * 0b0..Disabled. Break detect and generate is configured for normal operation. - * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. - */ -#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) -#define USART_CFG_CTSEN_MASK (0x200U) -#define USART_CFG_CTSEN_SHIFT (9U) -/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. - * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. - * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. - */ -#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) -#define USART_CFG_SYNCEN_MASK (0x800U) -#define USART_CFG_SYNCEN_SHIFT (11U) -/*! SYNCEN - Selects synchronous or asynchronous operation. - * 0b0..Asynchronous mode. - * 0b1..Synchronous mode. - */ -#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) -#define USART_CFG_CLKPOL_MASK (0x1000U) -#define USART_CFG_CLKPOL_SHIFT (12U) -/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. - * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. - * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. - */ -#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) -#define USART_CFG_SYNCMST_MASK (0x4000U) -#define USART_CFG_SYNCMST_SHIFT (14U) -/*! SYNCMST - Synchronous mode Master select. - * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. - * 0b1..Master. When synchronous mode is enabled, the USART is a master. - */ -#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) -#define USART_CFG_LOOP_MASK (0x8000U) -#define USART_CFG_LOOP_SHIFT (15U) -/*! LOOP - Selects data loopback mode. - * 0b0..Normal operation. - * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. - */ -#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) -#define USART_CFG_OETA_MASK (0x40000U) -#define USART_CFG_OETA_SHIFT (18U) -/*! OETA - Output Enable Turnaround time enable for RS-485 operation. - * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. - * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. - */ -#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) -#define USART_CFG_AUTOADDR_MASK (0x80000U) -#define USART_CFG_AUTOADDR_SHIFT (19U) -/*! AUTOADDR - Automatic Address matching enable. - * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). - * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. - */ -#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) -#define USART_CFG_OESEL_MASK (0x100000U) -#define USART_CFG_OESEL_SHIFT (20U) -/*! OESEL - Output Enable Select. - * 0b0..Standard. The RTS signal is used as the standard flow control function. - * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. - */ -#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) -#define USART_CFG_OEPOL_MASK (0x200000U) -#define USART_CFG_OEPOL_SHIFT (21U) -/*! OEPOL - Output Enable Polarity. - * 0b0..Low. If selected by OESEL, the output enable is active low. - * 0b1..High. If selected by OESEL, the output enable is active high. - */ -#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) -#define USART_CFG_RXPOL_MASK (0x400000U) -#define USART_CFG_RXPOL_SHIFT (22U) -/*! RXPOL - Receive data polarity. - * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. - * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. - */ -#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) -#define USART_CFG_TXPOL_MASK (0x800000U) -#define USART_CFG_TXPOL_SHIFT (23U) -/*! TXPOL - Transmit data polarity. - * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. - * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. - */ -#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) -/*! @} */ - -/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ -/*! @{ */ -#define USART_CTL_TXBRKEN_MASK (0x2U) -#define USART_CTL_TXBRKEN_SHIFT (1U) -/*! TXBRKEN - Break Enable. - * 0b0..Normal operation. - * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. - */ -#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) -#define USART_CTL_ADDRDET_MASK (0x4U) -#define USART_CTL_ADDRDET_SHIFT (2U) -/*! ADDRDET - Enable address detect mode. - * 0b0..Disabled. The USART presents all incoming data. - * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. - */ -#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) -#define USART_CTL_TXDIS_MASK (0x40U) -#define USART_CTL_TXDIS_SHIFT (6U) -/*! TXDIS - Transmit Disable. - * 0b0..Not disabled. USART transmitter is not disabled. - * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. - */ -#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) -#define USART_CTL_CC_MASK (0x100U) -#define USART_CTL_CC_SHIFT (8U) -/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. - * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. - * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). - */ -#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) -#define USART_CTL_CLRCCONRX_MASK (0x200U) -#define USART_CTL_CLRCCONRX_SHIFT (9U) -/*! CLRCCONRX - Clear Continuous Clock. - * 0b0..No effect. No effect on the CC bit. - * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. - */ -#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) -#define USART_CTL_AUTOBAUD_MASK (0x10000U) -#define USART_CTL_AUTOBAUD_SHIFT (16U) -/*! AUTOBAUD - Autobaud enable. - * 0b0..Disabled. USART is in normal operating mode. - * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. - */ -#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) -/*! @} */ - -/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ -/*! @{ */ -#define USART_STAT_RXIDLE_MASK (0x2U) -#define USART_STAT_RXIDLE_SHIFT (1U) -#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) -#define USART_STAT_TXIDLE_MASK (0x8U) -#define USART_STAT_TXIDLE_SHIFT (3U) -#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) -#define USART_STAT_CTS_MASK (0x10U) -#define USART_STAT_CTS_SHIFT (4U) -#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) -#define USART_STAT_DELTACTS_MASK (0x20U) -#define USART_STAT_DELTACTS_SHIFT (5U) -#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) -#define USART_STAT_TXDISSTAT_MASK (0x40U) -#define USART_STAT_TXDISSTAT_SHIFT (6U) -#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) -#define USART_STAT_RXBRK_MASK (0x400U) -#define USART_STAT_RXBRK_SHIFT (10U) -#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) -#define USART_STAT_DELTARXBRK_MASK (0x800U) -#define USART_STAT_DELTARXBRK_SHIFT (11U) -#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) -#define USART_STAT_START_MASK (0x1000U) -#define USART_STAT_START_SHIFT (12U) -#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) -#define USART_STAT_FRAMERRINT_MASK (0x2000U) -#define USART_STAT_FRAMERRINT_SHIFT (13U) -#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) -#define USART_STAT_PARITYERRINT_MASK (0x4000U) -#define USART_STAT_PARITYERRINT_SHIFT (14U) -#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) -#define USART_STAT_RXNOISEINT_MASK (0x8000U) -#define USART_STAT_RXNOISEINT_SHIFT (15U) -#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) -#define USART_STAT_ABERR_MASK (0x10000U) -#define USART_STAT_ABERR_SHIFT (16U) -#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ -#define USART_INTENSET_TXIDLEEN_MASK (0x8U) -#define USART_INTENSET_TXIDLEEN_SHIFT (3U) -#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) -#define USART_INTENSET_DELTACTSEN_MASK (0x20U) -#define USART_INTENSET_DELTACTSEN_SHIFT (5U) -#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) -#define USART_INTENSET_TXDISEN_MASK (0x40U) -#define USART_INTENSET_TXDISEN_SHIFT (6U) -#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) -#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) -#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) -#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) -#define USART_INTENSET_STARTEN_MASK (0x1000U) -#define USART_INTENSET_STARTEN_SHIFT (12U) -#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) -#define USART_INTENSET_FRAMERREN_MASK (0x2000U) -#define USART_INTENSET_FRAMERREN_SHIFT (13U) -#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) -#define USART_INTENSET_PARITYERREN_MASK (0x4000U) -#define USART_INTENSET_PARITYERREN_SHIFT (14U) -#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) -#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) -#define USART_INTENSET_RXNOISEEN_SHIFT (15U) -#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) -#define USART_INTENSET_ABERREN_MASK (0x10000U) -#define USART_INTENSET_ABERREN_SHIFT (16U) -#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ -/*! @{ */ -#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) -#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) -#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) -#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) -#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) -#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) -#define USART_INTENCLR_TXDISCLR_MASK (0x40U) -#define USART_INTENCLR_TXDISCLR_SHIFT (6U) -#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) -#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) -#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) -#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) -#define USART_INTENCLR_STARTCLR_MASK (0x1000U) -#define USART_INTENCLR_STARTCLR_SHIFT (12U) -#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) -#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) -#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) -#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) -#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) -#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) -#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) -#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) -#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) -#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) -#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) -#define USART_INTENCLR_ABERRCLR_SHIFT (16U) -#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) -/*! @} */ - -/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ -/*! @{ */ -#define USART_BRG_BRGVAL_MASK (0xFFFFU) -#define USART_BRG_BRGVAL_SHIFT (0U) -#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ -/*! @{ */ -#define USART_INTSTAT_TXIDLE_MASK (0x8U) -#define USART_INTSTAT_TXIDLE_SHIFT (3U) -#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) -#define USART_INTSTAT_DELTACTS_MASK (0x20U) -#define USART_INTSTAT_DELTACTS_SHIFT (5U) -#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) -#define USART_INTSTAT_TXDISINT_MASK (0x40U) -#define USART_INTSTAT_TXDISINT_SHIFT (6U) -#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) -#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) -#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) -#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) -#define USART_INTSTAT_START_MASK (0x1000U) -#define USART_INTSTAT_START_SHIFT (12U) -#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) -#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) -#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) -#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) -#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) -#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) -#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) -#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) -#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) -#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) -#define USART_INTSTAT_ABERRINT_MASK (0x10000U) -#define USART_INTSTAT_ABERRINT_SHIFT (16U) -#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) -/*! @} */ - -/*! @name OSR - Oversample selection register for asynchronous communication. */ -/*! @{ */ -#define USART_OSR_OSRVAL_MASK (0xFU) -#define USART_OSR_OSRVAL_SHIFT (0U) -#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) -/*! @} */ - -/*! @name ADDR - Address register for automatic address matching. */ -/*! @{ */ -#define USART_ADDR_ADDRESS_MASK (0xFFU) -#define USART_ADDR_ADDRESS_SHIFT (0U) -#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ -#define USART_FIFOCFG_ENABLETX_MASK (0x1U) -#define USART_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) -#define USART_FIFOCFG_ENABLERX_MASK (0x2U) -#define USART_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) -#define USART_FIFOCFG_SIZE_MASK (0x30U) -#define USART_FIFOCFG_SIZE_SHIFT (4U) -#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) -#define USART_FIFOCFG_DMATX_MASK (0x1000U) -#define USART_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) -#define USART_FIFOCFG_DMARX_MASK (0x2000U) -#define USART_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) -#define USART_FIFOCFG_WAKETX_MASK (0x4000U) -#define USART_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) -#define USART_FIFOCFG_WAKERX_MASK (0x8000U) -#define USART_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) -#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) -#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) -#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) -#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) -#define USART_FIFOCFG_POPDBG_MASK (0x40000U) -#define USART_FIFOCFG_POPDBG_SHIFT (18U) -/*! POPDBG - Pop FIFO for debug reads. - * 0b0..Debug reads of the FIFO do not pop the FIFO. - * 0b1..A debug read will cause the FIFO to pop. - */ -#define USART_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ -#define USART_FIFOSTAT_TXERR_MASK (0x1U) -#define USART_FIFOSTAT_TXERR_SHIFT (0U) -#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) -#define USART_FIFOSTAT_RXERR_MASK (0x2U) -#define USART_FIFOSTAT_RXERR_SHIFT (1U) -#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) -#define USART_FIFOSTAT_PERINT_MASK (0x8U) -#define USART_FIFOSTAT_PERINT_SHIFT (3U) -#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) -#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) -#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) -#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) -#define USART_FIFOSTAT_RXFULL_MASK (0x80U) -#define USART_FIFOSTAT_RXFULL_SHIFT (7U) -#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) -#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define USART_FIFOSTAT_TXLVL_SHIFT (8U) -#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) -#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define USART_FIFOSTAT_RXLVL_SHIFT (16U) -#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ -#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) -#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) -#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) -#define USART_FIFOTRIG_TXLVL_SHIFT (8U) -#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) -#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define USART_FIFOTRIG_RXLVL_SHIFT (16U) -#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ -#define USART_FIFOINTENSET_TXERR_MASK (0x1U) -#define USART_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) -#define USART_FIFOINTENSET_RXERR_MASK (0x2U) -#define USART_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) -#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) -#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - */ -#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) -#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) -#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ -#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) -#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) -#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) -#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) -#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) -#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) -#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) -#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ -#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) -#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) -#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) -#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) -#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) -#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) -#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) -#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) -#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) -#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) -#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ -#define USART_FIFOWR_TXDATA_MASK (0x1FFU) -#define USART_FIFOWR_TXDATA_SHIFT (0U) -#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ -#define USART_FIFORD_RXDATA_MASK (0x1FFU) -#define USART_FIFORD_RXDATA_SHIFT (0U) -#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) -#define USART_FIFORD_FRAMERR_MASK (0x2000U) -#define USART_FIFORD_FRAMERR_SHIFT (13U) -#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) -#define USART_FIFORD_PARITYERR_MASK (0x4000U) -#define USART_FIFORD_PARITYERR_SHIFT (14U) -#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) -#define USART_FIFORD_RXNOISE_MASK (0x8000U) -#define USART_FIFORD_RXNOISE_SHIFT (15U) -#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ -#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) -#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) -#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) -#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) -#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) -#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) -#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) -#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) -#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) -#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) -#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ -#define USART_ID_APERTURE_MASK (0xFFU) -#define USART_ID_APERTURE_SHIFT (0U) -#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) -#define USART_ID_MINOR_REV_MASK (0xF00U) -#define USART_ID_MINOR_REV_SHIFT (8U) -#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) -#define USART_ID_MAJOR_REV_MASK (0xF000U) -#define USART_ID_MAJOR_REV_SHIFT (12U) -#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) -#define USART_ID_ID_MASK (0xFFFF0000U) -#define USART_ID_ID_SHIFT (16U) -#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USART_Register_Masks */ - - -/* USART - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral USART0 base address */ - #define USART0_BASE (0x50086000u) - /** Peripheral USART0 base address */ - #define USART0_BASE_NS (0x40086000u) - /** Peripheral USART0 base pointer */ - #define USART0 ((USART_Type *)USART0_BASE) - /** Peripheral USART0 base pointer */ - #define USART0_NS ((USART_Type *)USART0_BASE_NS) - /** Peripheral USART1 base address */ - #define USART1_BASE (0x50087000u) - /** Peripheral USART1 base address */ - #define USART1_BASE_NS (0x40087000u) - /** Peripheral USART1 base pointer */ - #define USART1 ((USART_Type *)USART1_BASE) - /** Peripheral USART1 base pointer */ - #define USART1_NS ((USART_Type *)USART1_BASE_NS) - /** Peripheral USART2 base address */ - #define USART2_BASE (0x50088000u) - /** Peripheral USART2 base address */ - #define USART2_BASE_NS (0x40088000u) - /** Peripheral USART2 base pointer */ - #define USART2 ((USART_Type *)USART2_BASE) - /** Peripheral USART2 base pointer */ - #define USART2_NS ((USART_Type *)USART2_BASE_NS) - /** Peripheral USART3 base address */ - #define USART3_BASE (0x50089000u) - /** Peripheral USART3 base address */ - #define USART3_BASE_NS (0x40089000u) - /** Peripheral USART3 base pointer */ - #define USART3 ((USART_Type *)USART3_BASE) - /** Peripheral USART3 base pointer */ - #define USART3_NS ((USART_Type *)USART3_BASE_NS) - /** Peripheral USART4 base address */ - #define USART4_BASE (0x5008A000u) - /** Peripheral USART4 base address */ - #define USART4_BASE_NS (0x4008A000u) - /** Peripheral USART4 base pointer */ - #define USART4 ((USART_Type *)USART4_BASE) - /** Peripheral USART4 base pointer */ - #define USART4_NS ((USART_Type *)USART4_BASE_NS) - /** Peripheral USART5 base address */ - #define USART5_BASE (0x50096000u) - /** Peripheral USART5 base address */ - #define USART5_BASE_NS (0x40096000u) - /** Peripheral USART5 base pointer */ - #define USART5 ((USART_Type *)USART5_BASE) - /** Peripheral USART5 base pointer */ - #define USART5_NS ((USART_Type *)USART5_BASE_NS) - /** Peripheral USART6 base address */ - #define USART6_BASE (0x50097000u) - /** Peripheral USART6 base address */ - #define USART6_BASE_NS (0x40097000u) - /** Peripheral USART6 base pointer */ - #define USART6 ((USART_Type *)USART6_BASE) - /** Peripheral USART6 base pointer */ - #define USART6_NS ((USART_Type *)USART6_BASE_NS) - /** Peripheral USART7 base address */ - #define USART7_BASE (0x50098000u) - /** Peripheral USART7 base address */ - #define USART7_BASE_NS (0x40098000u) - /** Peripheral USART7 base pointer */ - #define USART7 ((USART_Type *)USART7_BASE) - /** Peripheral USART7 base pointer */ - #define USART7_NS ((USART_Type *)USART7_BASE_NS) - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } -#else - /** Peripheral USART0 base address */ - #define USART0_BASE (0x40086000u) - /** Peripheral USART0 base pointer */ - #define USART0 ((USART_Type *)USART0_BASE) - /** Peripheral USART1 base address */ - #define USART1_BASE (0x40087000u) - /** Peripheral USART1 base pointer */ - #define USART1 ((USART_Type *)USART1_BASE) - /** Peripheral USART2 base address */ - #define USART2_BASE (0x40088000u) - /** Peripheral USART2 base pointer */ - #define USART2 ((USART_Type *)USART2_BASE) - /** Peripheral USART3 base address */ - #define USART3_BASE (0x40089000u) - /** Peripheral USART3 base pointer */ - #define USART3 ((USART_Type *)USART3_BASE) - /** Peripheral USART4 base address */ - #define USART4_BASE (0x4008A000u) - /** Peripheral USART4 base pointer */ - #define USART4 ((USART_Type *)USART4_BASE) - /** Peripheral USART5 base address */ - #define USART5_BASE (0x40096000u) - /** Peripheral USART5 base pointer */ - #define USART5 ((USART_Type *)USART5_BASE) - /** Peripheral USART6 base address */ - #define USART6_BASE (0x40097000u) - /** Peripheral USART6 base pointer */ - #define USART6 ((USART_Type *)USART6_BASE) - /** Peripheral USART7 base address */ - #define USART7_BASE (0x40098000u) - /** Peripheral USART7 base pointer */ - #define USART7 ((USART_Type *)USART7_BASE) - /** Array initializer of USART peripheral base addresses */ - #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } - /** Array initializer of USART peripheral base pointers */ - #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } -#endif -/** Interrupt vectors for the USART peripheral type */ -#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group USART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer - * @{ - */ - -/** USB - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ - __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ -} USB_Type; - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status register */ -/*! @{ */ -#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) -#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) -#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) -#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) -#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: - * 0b0..USB_NEEDCLK has normal function. - * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. - */ -#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) -#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -/*! LPM_SUP - LPM Supported: - * 0b0..LPM not supported. - * 0b1..LPM supported. - */ -#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) -#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) -#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) -#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -/*! INTONNAK_CO - Interrupt on NAK for control OUT EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) -#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -/*! INTONNAK_CI - Interrupt on NAK for control IN EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) -#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USB_DEVCMDSTAT_DCON_SHIFT (16U) -#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) -#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) -#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) -#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) -#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) -#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) -#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) -#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) -#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) -#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) -#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) -/*! @} */ - -/*! @name INFO - USB Info register */ -/*! @{ */ -#define USB_INFO_FRAME_NR_MASK (0x7FFU) -#define USB_INFO_FRAME_NR_SHIFT (0U) -#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) -#define USB_INFO_ERR_CODE_MASK (0x7800U) -#define USB_INFO_ERR_CODE_SHIFT (11U) -/*! ERR_CODE - The error code which last occurred: - * 0b0000..No error - * 0b0001..PID encoding error - * 0b0010..PID unknown - * 0b0011..Packet unexpected - * 0b0100..Token CRC error - * 0b0101..Data CRC error - * 0b0110..Time out - * 0b0111..Babble - * 0b1000..Truncated EOP - * 0b1001..Sent/Received NAK - * 0b1010..Sent Stall - * 0b1011..Overrun - * 0b1100..Sent empty packet - * 0b1101..Bitstuff error - * 0b1110..Sync error - * 0b1111..Wrong data toggle - */ -#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) -#define USB_INFO_MINREV_MASK (0xFF0000U) -#define USB_INFO_MINREV_SHIFT (16U) -#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) -#define USB_INFO_MAJREV_MASK (0xFF000000U) -#define USB_INFO_MAJREV_SHIFT (24U) -#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) -/*! @} */ - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -/*! @{ */ -#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) -#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) -#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) -/*! @} */ - -/*! @name DATABUFSTART - USB Data buffer start address */ -/*! @{ */ -#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) -#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) -#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) -/*! @} */ - -/*! @name LPM - USB Link Power Management register */ -/*! @{ */ -#define USB_LPM_HIRD_HW_MASK (0xFU) -#define USB_LPM_HIRD_HW_SHIFT (0U) -#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) -#define USB_LPM_HIRD_SW_MASK (0xF0U) -#define USB_LPM_HIRD_SW_SHIFT (4U) -#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) -#define USB_LPM_DATA_PENDING_MASK (0x100U) -#define USB_LPM_DATA_PENDING_SHIFT (8U) -#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) -/*! @} */ - -/*! @name EPSKIP - USB Endpoint skip */ -/*! @{ */ -#define USB_EPSKIP_SKIP_MASK (0x3FFU) -#define USB_EPSKIP_SKIP_SHIFT (0U) -#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) -/*! @} */ - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -/*! @{ */ -#define USB_EPINUSE_BUF_MASK (0x3FCU) -#define USB_EPINUSE_BUF_SHIFT (2U) -#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) -/*! @} */ - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ -/*! @{ */ -#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) -#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) -#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) -/*! @} */ - -/*! @name INTSTAT - USB interrupt status register */ -/*! @{ */ -#define USB_INTSTAT_EP0OUT_MASK (0x1U) -#define USB_INTSTAT_EP0OUT_SHIFT (0U) -#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) -#define USB_INTSTAT_EP0IN_MASK (0x2U) -#define USB_INTSTAT_EP0IN_SHIFT (1U) -#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) -#define USB_INTSTAT_EP1OUT_MASK (0x4U) -#define USB_INTSTAT_EP1OUT_SHIFT (2U) -#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) -#define USB_INTSTAT_EP1IN_MASK (0x8U) -#define USB_INTSTAT_EP1IN_SHIFT (3U) -#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) -#define USB_INTSTAT_EP2OUT_MASK (0x10U) -#define USB_INTSTAT_EP2OUT_SHIFT (4U) -#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) -#define USB_INTSTAT_EP2IN_MASK (0x20U) -#define USB_INTSTAT_EP2IN_SHIFT (5U) -#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) -#define USB_INTSTAT_EP3OUT_MASK (0x40U) -#define USB_INTSTAT_EP3OUT_SHIFT (6U) -#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) -#define USB_INTSTAT_EP3IN_MASK (0x80U) -#define USB_INTSTAT_EP3IN_SHIFT (7U) -#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) -#define USB_INTSTAT_EP4OUT_MASK (0x100U) -#define USB_INTSTAT_EP4OUT_SHIFT (8U) -#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) -#define USB_INTSTAT_EP4IN_MASK (0x200U) -#define USB_INTSTAT_EP4IN_SHIFT (9U) -#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) -#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USB_INTSTAT_FRAME_INT_SHIFT (30U) -#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) -#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USB_INTSTAT_DEV_INT_SHIFT (31U) -#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) -/*! @} */ - -/*! @name INTEN - USB interrupt enable register */ -/*! @{ */ -#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) -#define USB_INTEN_EP_INT_EN_SHIFT (0U) -#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) -#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) -#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) -#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USB_INTEN_DEV_INT_EN_SHIFT (31U) -#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) -/*! @} */ - -/*! @name INTSETSTAT - USB set interrupt status register */ -/*! @{ */ -#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) -#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) -#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) -#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) -#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) -/*! @} */ - -/*! @name EPTOGGLE - USB Endpoint toggle register */ -/*! @{ */ -#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) -#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) -#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USB_Register_Masks */ - - -/* USB - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral USB0 base address */ - #define USB0_BASE (0x50084000u) - /** Peripheral USB0 base address */ - #define USB0_BASE_NS (0x40084000u) - /** Peripheral USB0 base pointer */ - #define USB0 ((USB_Type *)USB0_BASE) - /** Peripheral USB0 base pointer */ - #define USB0_NS ((USB_Type *)USB0_BASE_NS) - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS { USB0_BASE } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS { USB0 } - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS_NS { USB0_BASE_NS } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS_NS { USB0_NS } -#else - /** Peripheral USB0 base address */ - #define USB0_BASE (0x40084000u) - /** Peripheral USB0 base pointer */ - #define USB0 ((USB_Type *)USB0_BASE) - /** Array initializer of USB peripheral base addresses */ - #define USB_BASE_ADDRS { USB0_BASE } - /** Array initializer of USB peripheral base pointers */ - #define USB_BASE_PTRS { USB0 } -#endif -/** Interrupt vectors for the USB peripheral type */ -#define USB_IRQS { USB0_IRQn } -#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBFSH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer - * @{ - */ - -/** USBFSH - Register Layout Typedef */ -typedef struct { - __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */ - __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */ - __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */ - __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */ - __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ - __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ - __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ - __IO uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ - __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ - __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ - __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ - __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ - __IO uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ - __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ - __IO uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ - __IO uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ - __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ - __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ - __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ - __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */ - __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */ - __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */ - uint8_t RESERVED_0[4]; - __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */ -} USBFSH_Type; - -/* ---------------------------------------------------------------------------- - -- USBFSH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBFSH_Register_Masks USBFSH Register Masks - * @{ - */ - -/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ -/*! @{ */ -#define USBFSH_HCREVISION_REV_MASK (0xFFU) -#define USBFSH_HCREVISION_REV_SHIFT (0U) -#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) -/*! @} */ - -/*! @name HCCONTROL - Defines the operating modes of the HC */ -/*! @{ */ -#define USBFSH_HCCONTROL_CBSR_MASK (0x3U) -#define USBFSH_HCCONTROL_CBSR_SHIFT (0U) -#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) -#define USBFSH_HCCONTROL_PLE_MASK (0x4U) -#define USBFSH_HCCONTROL_PLE_SHIFT (2U) -#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) -#define USBFSH_HCCONTROL_IE_MASK (0x8U) -#define USBFSH_HCCONTROL_IE_SHIFT (3U) -#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) -#define USBFSH_HCCONTROL_CLE_MASK (0x10U) -#define USBFSH_HCCONTROL_CLE_SHIFT (4U) -#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) -#define USBFSH_HCCONTROL_BLE_MASK (0x20U) -#define USBFSH_HCCONTROL_BLE_SHIFT (5U) -#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) -#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) -#define USBFSH_HCCONTROL_HCFS_SHIFT (6U) -#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) -#define USBFSH_HCCONTROL_IR_MASK (0x100U) -#define USBFSH_HCCONTROL_IR_SHIFT (8U) -#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) -#define USBFSH_HCCONTROL_RWC_MASK (0x200U) -#define USBFSH_HCCONTROL_RWC_SHIFT (9U) -#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) -#define USBFSH_HCCONTROL_RWE_MASK (0x400U) -#define USBFSH_HCCONTROL_RWE_SHIFT (10U) -#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) -/*! @} */ - -/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ -/*! @{ */ -#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) -#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) -#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) -#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) -#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) -#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) -#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) -#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) -#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) -#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) -#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) -#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) -#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) -#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) -#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) -/*! @} */ - -/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ -/*! @{ */ -#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) -#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) -#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) -#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) -#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) -#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) -#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) -#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) -#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) -#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) -#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) -#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) -#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) -#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) -#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) -#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) -#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) -/*! @} */ - -/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ -/*! @{ */ -#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) -#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) -#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) -#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) -#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) -#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) -#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) -#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) -#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) -#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) -#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) -#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) -#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) -#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) -#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) -#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) -#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) -#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) -#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) -#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) -/*! @} */ - -/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ -/*! @{ */ -#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) -#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) -#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) -#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) -#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) -#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) -#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) -#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) -#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) -#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) -#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) -#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) -#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) -#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) -#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) -#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) -#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) -#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) -#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) -#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) -#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) -#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) -#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) -#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) -#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) -#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) -#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) -/*! @} */ - -/*! @name HCHCCA - Contains the physical address of the host controller communication area */ -/*! @{ */ -#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) -#define USBFSH_HCHCCA_HCCA_SHIFT (8U) -#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) -/*! @} */ - -/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ -/*! @{ */ -#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) -#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) -/*! @} */ - -/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ -/*! @{ */ -#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) -#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) -#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) -/*! @} */ - -/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ -/*! @{ */ -#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) -#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) -/*! @} */ - -/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ -/*! @{ */ -#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) -#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) -#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) -/*! @} */ - -/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ -/*! @{ */ -#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) -#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) -#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) -/*! @} */ - -/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ -/*! @{ */ -#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) -#define USBFSH_HCDONEHEAD_DH_SHIFT (4U) -#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) -/*! @} */ - -/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ -/*! @{ */ -#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) -#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) -#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) -#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) -#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) -#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) -#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) -#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) -#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) -/*! @} */ - -/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ -/*! @{ */ -#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) -#define USBFSH_HCFMREMAINING_FR_SHIFT (0U) -#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) -#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) -#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) -#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) -/*! @} */ - -/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ -/*! @{ */ -#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) -#define USBFSH_HCFMNUMBER_FN_SHIFT (0U) -#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) -/*! @} */ - -/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ -/*! @{ */ -#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) -#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) -#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) -/*! @} */ - -/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ -/*! @{ */ -#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) -#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) -#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) -/*! @} */ - -/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ -/*! @{ */ -#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) -#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) -#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) -#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) -#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) -#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) -#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) -#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) -#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) -#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) -#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) -#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) -#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) -#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) -#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) -#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) -#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) -#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) -#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) -#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) -#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) -/*! @} */ - -/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ -/*! @{ */ -#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) -#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) -#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) -#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) -#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) -#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) -/*! @} */ - -/*! @name HCRHSTATUS - This register is divided into two parts */ -/*! @{ */ -#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) -#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) -#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) -#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) -#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) -#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) -#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) -#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) -#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) -#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) -#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) -#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) -#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) -#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) -#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) -#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) -#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) -#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) -/*! @} */ - -/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ -/*! @{ */ -#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) -#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) -#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) -#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) -#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) -#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) -#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) -#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) -#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) -#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) -#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) -#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) -#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) -#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) -#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) -#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) -#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) -#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) -#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) -#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) -#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) -#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) -#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) -#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) -#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) -#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) -#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) -#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) -#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) -#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) -#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) -#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) -#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) -#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) -#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) -#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) -/*! @} */ - -/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ -/*! @{ */ -#define USBFSH_PORTMODE_ID_MASK (0x1U) -#define USBFSH_PORTMODE_ID_SHIFT (0U) -#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) -#define USBFSH_PORTMODE_ID_EN_MASK (0x100U) -#define USBFSH_PORTMODE_ID_EN_SHIFT (8U) -#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) -#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) -#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) -#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBFSH_Register_Masks */ - - -/* USBFSH - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral USBFSH base address */ - #define USBFSH_BASE (0x500A2000u) - /** Peripheral USBFSH base address */ - #define USBFSH_BASE_NS (0x400A2000u) - /** Peripheral USBFSH base pointer */ - #define USBFSH ((USBFSH_Type *)USBFSH_BASE) - /** Peripheral USBFSH base pointer */ - #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS) - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS { USBFSH_BASE } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS { USBFSH } - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS_NS { USBFSH_NS } -#else - /** Peripheral USBFSH base address */ - #define USBFSH_BASE (0x400A2000u) - /** Peripheral USBFSH base pointer */ - #define USBFSH ((USBFSH_Type *)USBFSH_BASE) - /** Array initializer of USBFSH peripheral base addresses */ - #define USBFSH_BASE_ADDRS { USBFSH_BASE } - /** Array initializer of USBFSH peripheral base pointers */ - #define USBFSH_BASE_PTRS { USBFSH } -#endif -/** Interrupt vectors for the USBFSH peripheral type */ -#define USBFSH_IRQS { USB0_IRQn } -#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBFSH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBHSD Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer - * @{ - */ - -/** USBHSD - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ - __I uint32_t INFO; /**< USB Info register, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ - uint8_t RESERVED_1[4]; - __IO uint32_t ULPIDEBUG; /**< UTMI/ULPI debug register, offset: 0x3C */ -} USBHSD_Type; - -/* ---------------------------------------------------------------------------- - -- USBHSD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSD_Register_Masks USBHSD Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status register */ -/*! @{ */ -#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) -#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) -#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) -#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) -#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) -#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK (0x400U) -#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT (10U) -#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK) -#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) -#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) -#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) -#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) -#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) -#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) -#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) -#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) -#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) -#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) -#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) -#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) -#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) -#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) -#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) -#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) -#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) -#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) -#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) -#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) -#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) -#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) -/*! @} */ - -/*! @name INFO - USB Info register */ -/*! @{ */ -#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) -#define USBHSD_INFO_FRAME_NR_SHIFT (0U) -#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) -#define USBHSD_INFO_ERR_CODE_MASK (0x7800U) -#define USBHSD_INFO_ERR_CODE_SHIFT (11U) -#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) -#define USBHSD_INFO_Minrev_MASK (0xFF0000U) -#define USBHSD_INFO_Minrev_SHIFT (16U) -#define USBHSD_INFO_Minrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK) -#define USBHSD_INFO_Majrev_MASK (0xFF000000U) -#define USBHSD_INFO_Majrev_SHIFT (24U) -#define USBHSD_INFO_Majrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK) -/*! @} */ - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -/*! @{ */ -#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) -#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) -#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) -#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) -#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) -#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) -/*! @} */ - -/*! @name DATABUFSTART - USB Data buffer start address */ -/*! @{ */ -#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) -#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) -#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) -/*! @} */ - -/*! @name LPM - USB Link Power Management register */ -/*! @{ */ -#define USBHSD_LPM_HIRD_HW_MASK (0xFU) -#define USBHSD_LPM_HIRD_HW_SHIFT (0U) -#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) -#define USBHSD_LPM_HIRD_SW_MASK (0xF0U) -#define USBHSD_LPM_HIRD_SW_SHIFT (4U) -#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) -#define USBHSD_LPM_DATA_PENDING_MASK (0x100U) -#define USBHSD_LPM_DATA_PENDING_SHIFT (8U) -#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) -/*! @} */ - -/*! @name EPSKIP - USB Endpoint skip */ -/*! @{ */ -#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) -#define USBHSD_EPSKIP_SKIP_SHIFT (0U) -#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) -/*! @} */ - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -/*! @{ */ -#define USBHSD_EPINUSE_BUF_MASK (0xFFCU) -#define USBHSD_EPINUSE_BUF_SHIFT (2U) -#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) -/*! @} */ - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ -/*! @{ */ -#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) -#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) -#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) -/*! @} */ - -/*! @name INTSTAT - USB interrupt status register */ -/*! @{ */ -#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) -#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) -#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) -#define USBHSD_INTSTAT_EP0IN_MASK (0x2U) -#define USBHSD_INTSTAT_EP0IN_SHIFT (1U) -#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) -#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) -#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) -#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) -#define USBHSD_INTSTAT_EP1IN_MASK (0x8U) -#define USBHSD_INTSTAT_EP1IN_SHIFT (3U) -#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) -#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) -#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) -#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) -#define USBHSD_INTSTAT_EP2IN_MASK (0x20U) -#define USBHSD_INTSTAT_EP2IN_SHIFT (5U) -#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) -#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) -#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) -#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) -#define USBHSD_INTSTAT_EP3IN_MASK (0x80U) -#define USBHSD_INTSTAT_EP3IN_SHIFT (7U) -#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) -#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) -#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) -#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) -#define USBHSD_INTSTAT_EP4IN_MASK (0x200U) -#define USBHSD_INTSTAT_EP4IN_SHIFT (9U) -#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) -#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) -#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) -#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) -#define USBHSD_INTSTAT_EP5IN_MASK (0x800U) -#define USBHSD_INTSTAT_EP5IN_SHIFT (11U) -#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) -#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) -#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) -#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) -#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) -/*! @} */ - -/*! @name INTEN - USB interrupt enable register */ -/*! @{ */ -#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) -#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) -#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) -#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) -#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) -#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) -#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) -/*! @} */ - -/*! @name INTSETSTAT - USB set interrupt status register */ -/*! @{ */ -#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) -#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) -#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) -#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) -#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) -/*! @} */ - -/*! @name EPTOGGLE - USB Endpoint toggle register */ -/*! @{ */ -#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) -#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) -#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) -/*! @} */ - -/*! @name ULPIDEBUG - UTMI/ULPI debug register */ -/*! @{ */ -#define USBHSD_ULPIDEBUG_PHY_ADDR_MASK (0xFFU) -#define USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT (0U) -#define USBHSD_ULPIDEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ADDR_MASK) -#define USBHSD_ULPIDEBUG_PHY_WDATA_MASK (0xFF00U) -#define USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT (8U) -#define USBHSD_ULPIDEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_WDATA_MASK) -#define USBHSD_ULPIDEBUG_PHY_RDATA_MASK (0xFF0000U) -#define USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT (16U) -#define USBHSD_ULPIDEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RDATA_MASK) -#define USBHSD_ULPIDEBUG_PHY_RW_MASK (0x1000000U) -#define USBHSD_ULPIDEBUG_PHY_RW_SHIFT (24U) -#define USBHSD_ULPIDEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RW_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RW_MASK) -#define USBHSD_ULPIDEBUG_PHY_ACCESS_MASK (0x2000000U) -#define USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT (25U) -#define USBHSD_ULPIDEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ACCESS_MASK) -#define USBHSD_ULPIDEBUG_PHY_MODE_MASK (0x80000000U) -#define USBHSD_ULPIDEBUG_PHY_MODE_SHIFT (31U) -#define USBHSD_ULPIDEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_MODE_SHIFT)) & USBHSD_ULPIDEBUG_PHY_MODE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBHSD_Register_Masks */ - - -/* USBHSD - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral USBHSD base address */ - #define USBHSD_BASE (0x50094000u) - /** Peripheral USBHSD base address */ - #define USBHSD_BASE_NS (0x40094000u) - /** Peripheral USBHSD base pointer */ - #define USBHSD ((USBHSD_Type *)USBHSD_BASE) - /** Peripheral USBHSD base pointer */ - #define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS) - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS { USBHSD_BASE } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS { USBHSD } - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS_NS { USBHSD_BASE_NS } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS_NS { USBHSD_NS } -#else - /** Peripheral USBHSD base address */ - #define USBHSD_BASE (0x40094000u) - /** Peripheral USBHSD base pointer */ - #define USBHSD ((USBHSD_Type *)USBHSD_BASE) - /** Array initializer of USBHSD peripheral base addresses */ - #define USBHSD_BASE_ADDRS { USBHSD_BASE } - /** Array initializer of USBHSD peripheral base pointers */ - #define USBHSD_BASE_PTRS { USBHSD } -#endif -/** Interrupt vectors for the USBHSD peripheral type */ -#define USBHSD_IRQS { USB1_IRQn } -#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBHSD_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBHSH Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer - * @{ - */ - -/** USBHSH - Register Layout Typedef */ -typedef struct { - __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ - __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ - __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x8 */ - __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ - __IO uint32_t ATL_PTD_BASE_ADDR; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ - __IO uint32_t ISO_PTD_BASE_ADDR; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ - __IO uint32_t INT_PTD_BASE_ADDR; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ - __IO uint32_t DATA_PAYLOAD_BASE_ADDR; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ - __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ - __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ - __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ - __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ - __IO uint32_t ATL_PTD_DONE_MAP; /**< Done map for each ATL PTD, offset: 0x30 */ - __IO uint32_t ATL_PTD_SKIP_MAP; /**< Skip map for each ATL PTD, offset: 0x34 */ - __IO uint32_t ISO_PTD_DONE_MAP; /**< Done map for each ISO PTD, offset: 0x38 */ - __IO uint32_t ISO_PTD_SKIP_MAP; /**< Skip map for each ISO PTD, offset: 0x3C */ - __IO uint32_t INT_PTD_DONE_MAP; /**< Done map for each INT PTD, offset: 0x40 */ - __IO uint32_t INT_PTD_SKIP_MAP; /**< Skip map for each INT PTD, offset: 0x44 */ - __IO uint32_t LAST_PTD_INUSE; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ - __IO uint32_t UTMIPLUS_ULPI_DEBUG; /**< Register to read/write registers in the attached USB PHY, offset: 0x4C */ - __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ -} USBHSH_Type; - -/* ---------------------------------------------------------------------------- - -- USBHSH Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBHSH_Register_Masks USBHSH Register Masks - * @{ - */ - -/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ -/*! @{ */ -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) -#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) -#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) -#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) -#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) -/*! @} */ - -/*! @name HCSPARAMS - Host Controller Structural Parameters */ -/*! @{ */ -#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) -#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) -#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) -#define USBHSH_HCSPARAMS_PPC_MASK (0x10U) -#define USBHSH_HCSPARAMS_PPC_SHIFT (4U) -#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) -#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) -#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) -#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) -/*! @} */ - -/*! @name HCCPARAMS - Host Controller Capability Parameters */ -/*! @{ */ -#define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U) -#define USBHSH_HCCPARAMS_LPMC_SHIFT (17U) -#define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK) -/*! @} */ - -/*! @name FLADJ_FRINDEX - Frame Length Adjustment */ -/*! @{ */ -#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) -#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) -#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) -#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) -#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) -#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) -/*! @} */ - -/*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */ -/*! @{ */ -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK (0x1F0U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT (4U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK (0xFFFFFE00U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT (9U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK) -/*! @} */ - -/*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */ -/*! @{ */ -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK (0x3E0U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK (0xFFFFFC00U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT (10U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK) -/*! @} */ - -/*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */ -/*! @{ */ -#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK (0x3E0U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK) -#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK (0xFFFFFC00U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT (10U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK) -/*! @} */ - -/*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */ -/*! @{ */ -#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U) -#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U) -#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK) -/*! @} */ - -/*! @name USBCMD - USB Command register */ -/*! @{ */ -#define USBHSH_USBCMD_RS_MASK (0x1U) -#define USBHSH_USBCMD_RS_SHIFT (0U) -#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) -#define USBHSH_USBCMD_HCRESET_MASK (0x2U) -#define USBHSH_USBCMD_HCRESET_SHIFT (1U) -#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) -#define USBHSH_USBCMD_FLS_MASK (0xCU) -#define USBHSH_USBCMD_FLS_SHIFT (2U) -#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) -#define USBHSH_USBCMD_LHCR_MASK (0x80U) -#define USBHSH_USBCMD_LHCR_SHIFT (7U) -#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) -#define USBHSH_USBCMD_ATL_EN_MASK (0x100U) -#define USBHSH_USBCMD_ATL_EN_SHIFT (8U) -#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) -#define USBHSH_USBCMD_ISO_EN_MASK (0x200U) -#define USBHSH_USBCMD_ISO_EN_SHIFT (9U) -#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) -#define USBHSH_USBCMD_INT_EN_MASK (0x400U) -#define USBHSH_USBCMD_INT_EN_SHIFT (10U) -#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) -#define USBHSH_USBCMD_HIRD_MASK (0xF000000U) -#define USBHSH_USBCMD_HIRD_SHIFT (24U) -#define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK) -#define USBHSH_USBCMD_LPM_RWU_MASK (0x10000000U) -#define USBHSH_USBCMD_LPM_RWU_SHIFT (28U) -#define USBHSH_USBCMD_LPM_RWU(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK) -/*! @} */ - -/*! @name USBSTS - USB Interrupt Status register */ -/*! @{ */ -#define USBHSH_USBSTS_PCD_MASK (0x4U) -#define USBHSH_USBSTS_PCD_SHIFT (2U) -#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) -#define USBHSH_USBSTS_FLR_MASK (0x8U) -#define USBHSH_USBSTS_FLR_SHIFT (3U) -#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) -#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) -#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) -#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) -#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) -#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) -#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) -#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) -#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) -#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) -#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) -#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) -#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) -/*! @} */ - -/*! @name USBINTR - USB Interrupt Enable register */ -/*! @{ */ -#define USBHSH_USBINTR_PCDE_MASK (0x4U) -#define USBHSH_USBINTR_PCDE_SHIFT (2U) -#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) -#define USBHSH_USBINTR_FLRE_MASK (0x8U) -#define USBHSH_USBINTR_FLRE_SHIFT (3U) -#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) -#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) -#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) -#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) -#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) -#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) -#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) -#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) -#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) -#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) -#define USBHSH_USBINTR_SOF_E_MASK (0x80000U) -#define USBHSH_USBINTR_SOF_E_SHIFT (19U) -#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) -/*! @} */ - -/*! @name PORTSC1 - Port Status and Control register */ -/*! @{ */ -#define USBHSH_PORTSC1_CCS_MASK (0x1U) -#define USBHSH_PORTSC1_CCS_SHIFT (0U) -#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) -#define USBHSH_PORTSC1_CSC_MASK (0x2U) -#define USBHSH_PORTSC1_CSC_SHIFT (1U) -#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) -#define USBHSH_PORTSC1_PED_MASK (0x4U) -#define USBHSH_PORTSC1_PED_SHIFT (2U) -#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) -#define USBHSH_PORTSC1_PEDC_MASK (0x8U) -#define USBHSH_PORTSC1_PEDC_SHIFT (3U) -#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) -#define USBHSH_PORTSC1_OCA_MASK (0x10U) -#define USBHSH_PORTSC1_OCA_SHIFT (4U) -#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) -#define USBHSH_PORTSC1_OCC_MASK (0x20U) -#define USBHSH_PORTSC1_OCC_SHIFT (5U) -#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) -#define USBHSH_PORTSC1_FPR_MASK (0x40U) -#define USBHSH_PORTSC1_FPR_SHIFT (6U) -#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) -#define USBHSH_PORTSC1_SUSP_MASK (0x80U) -#define USBHSH_PORTSC1_SUSP_SHIFT (7U) -#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) -#define USBHSH_PORTSC1_PR_MASK (0x100U) -#define USBHSH_PORTSC1_PR_SHIFT (8U) -#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) -#define USBHSH_PORTSC1_SUS_L1_MASK (0x200U) -#define USBHSH_PORTSC1_SUS_L1_SHIFT (9U) -#define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK) -#define USBHSH_PORTSC1_LS_MASK (0xC00U) -#define USBHSH_PORTSC1_LS_SHIFT (10U) -#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) -#define USBHSH_PORTSC1_PP_MASK (0x1000U) -#define USBHSH_PORTSC1_PP_SHIFT (12U) -#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) -#define USBHSH_PORTSC1_PIC_MASK (0xC000U) -#define USBHSH_PORTSC1_PIC_SHIFT (14U) -#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) -#define USBHSH_PORTSC1_PTC_MASK (0xF0000U) -#define USBHSH_PORTSC1_PTC_SHIFT (16U) -#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) -#define USBHSH_PORTSC1_PSPD_MASK (0x300000U) -#define USBHSH_PORTSC1_PSPD_SHIFT (20U) -#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) -#define USBHSH_PORTSC1_WOO_MASK (0x400000U) -#define USBHSH_PORTSC1_WOO_SHIFT (22U) -#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) -#define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U) -#define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U) -#define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK) -#define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U) -#define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U) -#define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK) -/*! @} */ - -/*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */ -/*! @{ */ -#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT (0U) -#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK) -/*! @} */ - -/*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */ -/*! @{ */ -#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT (0U) -#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK) -/*! @} */ - -/*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */ -/*! @{ */ -#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT (0U) -#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK) -/*! @} */ - -/*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */ -/*! @{ */ -#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT (0U) -#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK) -/*! @} */ - -/*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */ -/*! @{ */ -#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT (0U) -#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK) -/*! @} */ - -/*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */ -/*! @{ */ -#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT (0U) -#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK) -/*! @} */ - -/*! @name LAST_PTD_INUSE - Marks the last PTD in the list for ISO, INT and ATL */ -/*! @{ */ -#define USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK (0x1FU) -#define USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT (0U) -#define USBHSH_LAST_PTD_INUSE_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK) -#define USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK (0x1F00U) -#define USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT (8U) -#define USBHSH_LAST_PTD_INUSE_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK) -#define USBHSH_LAST_PTD_INUSE_INT_LAST_MASK (0x1F0000U) -#define USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT (16U) -#define USBHSH_LAST_PTD_INUSE_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_INT_LAST_MASK) -/*! @} */ - -/*! @name UTMIPLUS_ULPI_DEBUG - Register to read/write registers in the attached USB PHY */ -/*! @{ */ -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK (0xFFU) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT (0U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK (0xFF00U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT (8U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK (0xFF0000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT (16U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK (0x1000000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT (24U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK (0x2000000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT (25U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK (0x80000000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT (31U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK) -/*! @} */ - -/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ -/*! @{ */ -#define USBHSH_PORTMODE_ID0_MASK (0x1U) -#define USBHSH_PORTMODE_ID0_SHIFT (0U) -#define USBHSH_PORTMODE_ID0(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK) -#define USBHSH_PORTMODE_ID0_EN_MASK (0x100U) -#define USBHSH_PORTMODE_ID0_EN_SHIFT (8U) -#define USBHSH_PORTMODE_ID0_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK) -#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) -#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) -#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) -#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) -#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) -#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) -#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) -#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) -#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBHSH_Register_Masks */ - - -/* USBHSH - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral USBHSH base address */ - #define USBHSH_BASE (0x500A3000u) - /** Peripheral USBHSH base address */ - #define USBHSH_BASE_NS (0x400A3000u) - /** Peripheral USBHSH base pointer */ - #define USBHSH ((USBHSH_Type *)USBHSH_BASE) - /** Peripheral USBHSH base pointer */ - #define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS) - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS { USBHSH_BASE } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS { USBHSH } - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS_NS { USBHSH_BASE_NS } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS_NS { USBHSH_NS } -#else - /** Peripheral USBHSH base address */ - #define USBHSH_BASE (0x400A3000u) - /** Peripheral USBHSH base pointer */ - #define USBHSH ((USBHSH_Type *)USBHSH_BASE) - /** Array initializer of USBHSH peripheral base addresses */ - #define USBHSH_BASE_ADDRS { USBHSH_BASE } - /** Array initializer of USBHSH peripheral base pointers */ - #define USBHSH_BASE_PTRS { USBHSH } -#endif -/** Interrupt vectors for the USBHSH peripheral type */ -#define USBHSH_IRQS { USB1_IRQn } -#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USBHSH_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBPHY Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer - * @{ - */ - -/** USBPHY - Register Layout Typedef */ -typedef struct { - __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ - __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ - __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ - __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ - __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ - __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ - __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ - __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ - __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ - __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ - __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ - __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ - __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ - __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ - __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ - __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ - __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ - uint8_t RESERVED_0[12]; - __IO uint32_t DEBUG0; /**< USB PHY Debug Register 0, offset: 0x50 */ - __IO uint32_t DEBUG0_SET; /**< USB PHY Debug Register 0, offset: 0x54 */ - __IO uint32_t DEBUG0_CLR; /**< USB PHY Debug Register 0, offset: 0x58 */ - __IO uint32_t DEBUG0_TOG; /**< USB PHY Debug Register 0, offset: 0x5C */ - uint8_t RESERVED_1[16]; - __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ - __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ - __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ - __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ - __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ - uint8_t RESERVED_2[28]; - __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */ - __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */ - __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */ - __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */ - uint8_t RESERVED_3[16]; - __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */ - __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */ - __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */ - __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */ - __I uint32_t USB1_VBUS_DET_STAT; /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */ - uint8_t RESERVED_4[12]; - __IO uint32_t USB1_CHRG_DETECT; /**< USB PHY Charger Detect Control Register, offset: 0xE0 */ - __IO uint32_t USB1_CHRG_DETECT_SET; /**< USB PHY Charger Detect Control Register, offset: 0xE4 */ - __IO uint32_t USB1_CHRG_DETECT_CLR; /**< USB PHY Charger Detect Control Register, offset: 0xE8 */ - __IO uint32_t USB1_CHRG_DETECT_TOG; /**< USB PHY Charger Detect Control Register, offset: 0xEC */ - __I uint32_t USB1_CHRG_DET_STAT; /**< USB PHY Charger Detect Status Register, offset: 0xF0 */ - uint8_t RESERVED_5[12]; - __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100 */ - __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */ - __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */ - __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */ -} USBPHY_Type; - -/* ---------------------------------------------------------------------------- - -- USBPHY Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Register_Masks USBPHY Register Masks - * @{ - */ - -/*! @name PWD - USB PHY Power-Down Register */ -/*! @{ */ -#define USBPHY_PWD_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) -#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) -#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) -#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) -#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) -#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) -#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_SET - USB PHY Power-Down Register */ -/*! @{ */ -#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) -#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) -#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) -#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) -#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) -#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) -#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_CLR - USB PHY Power-Down Register */ -/*! @{ */ -#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) -#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) -#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) -#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) -#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) -#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) -#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) -/*! @} */ - -/*! @name PWD_TOG - USB PHY Power-Down Register */ -/*! @{ */ -#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the - */ -#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) -#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the - */ -#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) -#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror - */ -#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) -#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) - */ -#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) -#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed differential receiver. - */ -#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) -#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receive - */ -#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) -#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation. - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver - */ -#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) -/*! @} */ - -/*! @name TX - USB PHY Transmitter Control Register */ -/*! @{ */ -#define USBPHY_TX_D_CAL_MASK (0xFU) -#define USBPHY_TX_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) -#define USBPHY_TX_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) -#define USBPHY_TX_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK) -#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) -#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_SET - USB PHY Transmitter Control Register */ -/*! @{ */ -#define USBPHY_TX_SET_D_CAL_MASK (0xFU) -#define USBPHY_TX_SET_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) -#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) -#define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK) -#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) -#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_CLR - USB PHY Transmitter Control Register */ -/*! @{ */ -#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) -#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) -#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) -#define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK) -#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) -#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name TX_TOG - USB PHY Transmitter Control Register */ -/*! @{ */ -#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) -#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. - */ -#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) -#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) -#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) -#define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U) -#define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U) -#define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK) -#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) -#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) -/*! @} */ - -/*! @name RX - USB PHY Receiver Control Register */ -/*! @{ */ -#define USBPHY_RX_ENVADJ_MASK (0x7U) -#define USBPHY_RX_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) -#define USBPHY_RX_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) -#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_SET - USB PHY Receiver Control Register */ -/*! @{ */ -#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) -#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) -#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) -#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_CLR - USB PHY Receiver Control Register */ -/*! @{ */ -#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) -#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) -#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) -#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) -/*! @} */ - -/*! @name RX_TOG - USB PHY Receiver Control Register */ -/*! @{ */ -#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) -#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) -#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b100..reserved - * 0b101..reserved - * 0b110..reserved - * 0b111..reserved - */ -#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) -#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver - */ -#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) -/*! @} */ - -/*! @name CTRL - USB PHY General Control Register */ -/*! @{ */ -#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) -#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) -#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) -#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) -#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) -#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) -#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) -#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) -#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) -#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) -#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) -#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_SET - USB PHY General Control Register */ -/*! @{ */ -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) -#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) -#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) -#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) -#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) -#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) -#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) -#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_CLR - USB PHY General Control Register */ -/*! @{ */ -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) -#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) -#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) -#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) -#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) -#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_TOG - USB PHY General Control Register */ -/*! @{ */ -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins - */ -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) -#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) -#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) -#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) -#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) -#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) -#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) -#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) -/*! @} */ - -/*! @name STATUS - USB PHY Status Register */ -/*! @{ */ -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) -/*! HOSTDISCONDETECT_STATUS - * 0b0..USB cable disconnect has not been detected at the local host - * 0b1..USB cable disconnect has been detected at the local host - */ -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) -#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) -#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) -/*! DEVPLUGIN_STATUS - * 0b0..No attachment to a USB host is detected - * 0b1..Cable attachment to a USB host is detected - */ -#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) -#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) -#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) -#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) -#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) -#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) -#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) -/*! @} */ - -/*! @name DEBUG0 - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG0_SET - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_SET_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_SET_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG0_SET_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG0_CLR - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_CLR_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_CLR_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLR_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG0_TOG - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_TOG_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_TOG_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG0_TOG_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG1 - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% - */ -#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) -#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT (18U) -#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK) -#define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK (0x600000U) -#define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT (21U) -#define USBPHY_DEBUG1_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK) -/*! @} */ - -/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% - */ -#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK (0x600000U) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK) -/*! @} */ - -/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% - */ -#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK (0x600000U) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK) -/*! @} */ - -/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% - */ -#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK (0x600000U) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK) -/*! @} */ - -/*! @name VERSION - UTMI RTL Version */ -/*! @{ */ -#define USBPHY_VERSION_STEP_MASK (0xFFFFU) -#define USBPHY_VERSION_STEP_SHIFT (0U) -#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) -#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) -#define USBPHY_VERSION_MINOR_SHIFT (16U) -#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) -#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) -#define USBPHY_VERSION_MAJOR_SHIFT (24U) -#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) -/*! @} */ - -/*! @name PLL_SIC - USB PHY PLL Control/Status Register */ -/*! @{ */ -#define USBPHY_PLL_SIC_MISC2_CONTROL0_MASK (0x20U) -#define USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT (5U) -#define USBPHY_PLL_SIC_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_MISC2_CONTROL0_MASK) -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) -#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) -#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) -#define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U) -#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U) -#define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK) -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) -#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) -#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) -#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) -#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ -/*! @{ */ -#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK (0x20U) -#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT (5U) -#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK) -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) -#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) -#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) -#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U) -#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U) -#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) -#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ -/*! @{ */ -#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK (0x20U) -#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT (5U) -#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK) -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) -#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) -#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U) -#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U) -#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) -#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ -/*! @{ */ -#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK (0x20U) -#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT (5U) -#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK) -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) -#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) -#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) -#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) -#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) -#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) -#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U) -#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U) -#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias - */ -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) -#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) -#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 - */ -#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) -#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) -#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked - */ -#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x100000U) -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) -#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U) -#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U) -/*! EN_CHARGER_RESISTOR - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP - */ -#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U) -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U) -#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U) -/*! EN_CHARGER_RESISTOR - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP - */ -#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U) -/*! EN_CHARGER_RESISTOR - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V(Default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) -#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) -#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) -#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) -/*! VBUSVALID_TO_SESSVALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) -/*! PWRUP_CMPS - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U) -/*! EN_CHARGER_RESISTOR - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */ -/*! @{ */ -#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) -#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) -/*! SESSEND - * 0b0..The VBUS voltage is above the Session Valid threshold - * 0b1..The VBUS voltage is below the Session Valid threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) -#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) -#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) -/*! BVALID - * 0b0..The VBUS voltage is below the Session Valid threshold - * 0b1..The VBUS voltage is above the Session Valid threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) -#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) -#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) -/*! AVALID - * 0b0..The VBUS voltage is below the Session Valid threshold - * 0b1..The VBUS voltage is above the Session Valid threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) -/*! VBUS_VALID - * 0b0..VBUS is below the comparator threshold - * 0b1..VBUS is above the comparator threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) -/*! VBUS_VALID_3V - * 0b0..VBUS voltage is below VBUS_VALID_3V threshold - * 0b1..VBUS voltage is above VBUS_VALID_3V threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DETECT - USB PHY Charger Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U) -#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U) -#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. - */ -#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U) -#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U) -#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. - */ -#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U) -#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U) -#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. - */ -#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U) -#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U) -#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. - */ -#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U) -#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U) -/*! PLUG_CONTACT - * 0b0..No USB cable attachment has been detected - * 0b1..A USB cable attachment between the device and host has been detected - */ -#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK) -#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U) -#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U) -/*! CHRG_DETECTED - * 0b0..Standard Downstream Port (SDP) has been detected - * 0b1..Charging Port has been detected - */ -#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK) -#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U) -#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U) -/*! DM_STATE - * 0b0..USB_DM pin voltage is < 0.8V - * 0b1..USB_DM pin voltage is > 2.0V - */ -#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK) -#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U) -#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U) -/*! DP_STATE - * 0b0..USB_DP pin voltage is < 0.8V - * 0b1..USB_DP pin voltage is > 2.0V - */ -#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK) -#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U) -#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U) -/*! SECDET_DCP - * 0b0..Charging Downstream Port (CDP) has been detected - * 0b1..Downstream Charging Port (DCP) has been detected - */ -#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK) -/*! @} */ - -/*! @name ANACTRL - USB PHY Analog Control Register */ -/*! @{ */ -#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_SET - USB PHY Analog Control Register */ -/*! @{ */ -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_CLR - USB PHY Analog Control Register */ -/*! @{ */ -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) -/*! @} */ - -/*! @name ANACTRL_TOG - USB PHY Analog Control Register */ -/*! @{ */ -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. - */ -#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBPHY_Register_Masks */ - - -/* USBPHY - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral USBPHY base address */ - #define USBPHY_BASE (0x50038000u) - /** Peripheral USBPHY base address */ - #define USBPHY_BASE_NS (0x40038000u) - /** Peripheral USBPHY base pointer */ - #define USBPHY ((USBPHY_Type *)USBPHY_BASE) - /** Peripheral USBPHY base pointer */ - #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS { USBPHY_BASE } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS { USBPHY } - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS_NS { USBPHY_NS } -#else - /** Peripheral USBPHY base address */ - #define USBPHY_BASE (0x40038000u) - /** Peripheral USBPHY base pointer */ - #define USBPHY ((USBPHY_Type *)USBPHY_BASE) - /** Array initializer of USBPHY peripheral base addresses */ - #define USBPHY_BASE_ADDRS { USBPHY_BASE } - /** Array initializer of USBPHY peripheral base pointers */ - #define USBPHY_BASE_PTRS { USBPHY } -#endif - -/*! - * @} - */ /* end of group USBPHY_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- UTICK Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer - * @{ - */ - -/** UTICK - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ - __IO uint32_t STAT; /**< Status register., offset: 0x4 */ - __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ - __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ - __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ -} UTICK_Type; - -/* ---------------------------------------------------------------------------- - -- UTICK Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Register_Masks UTICK Register Masks - * @{ - */ - -/*! @name CTRL - Control register. */ -/*! @{ */ -#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) -#define UTICK_CTRL_DELAYVAL_SHIFT (0U) -#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) -#define UTICK_CTRL_REPEAT_MASK (0x80000000U) -#define UTICK_CTRL_REPEAT_SHIFT (31U) -#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) -/*! @} */ - -/*! @name STAT - Status register. */ -/*! @{ */ -#define UTICK_STAT_INTR_MASK (0x1U) -#define UTICK_STAT_INTR_SHIFT (0U) -#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) -#define UTICK_STAT_ACTIVE_MASK (0x2U) -#define UTICK_STAT_ACTIVE_SHIFT (1U) -#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) -/*! @} */ - -/*! @name CFG - Capture configuration register. */ -/*! @{ */ -#define UTICK_CFG_CAPEN0_MASK (0x1U) -#define UTICK_CFG_CAPEN0_SHIFT (0U) -#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) -#define UTICK_CFG_CAPEN1_MASK (0x2U) -#define UTICK_CFG_CAPEN1_SHIFT (1U) -#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) -#define UTICK_CFG_CAPEN2_MASK (0x4U) -#define UTICK_CFG_CAPEN2_SHIFT (2U) -#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) -#define UTICK_CFG_CAPEN3_MASK (0x8U) -#define UTICK_CFG_CAPEN3_SHIFT (3U) -#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) -#define UTICK_CFG_CAPPOL0_MASK (0x100U) -#define UTICK_CFG_CAPPOL0_SHIFT (8U) -#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) -#define UTICK_CFG_CAPPOL1_MASK (0x200U) -#define UTICK_CFG_CAPPOL1_SHIFT (9U) -#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) -#define UTICK_CFG_CAPPOL2_MASK (0x400U) -#define UTICK_CFG_CAPPOL2_SHIFT (10U) -#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) -#define UTICK_CFG_CAPPOL3_MASK (0x800U) -#define UTICK_CFG_CAPPOL3_SHIFT (11U) -#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) -/*! @} */ - -/*! @name CAPCLR - Capture clear register. */ -/*! @{ */ -#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) -#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) -#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) -#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) -#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) -#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) -#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) -#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) -#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) -#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) -#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) -#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) -/*! @} */ - -/*! @name CAP - Capture register . */ -/*! @{ */ -#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) -#define UTICK_CAP_CAP_VALUE_SHIFT (0U) -#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) -#define UTICK_CAP_VALID_MASK (0x80000000U) -#define UTICK_CAP_VALID_SHIFT (31U) -#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) -/*! @} */ - -/* The count of UTICK_CAP */ -#define UTICK_CAP_COUNT (4U) - - -/*! - * @} - */ /* end of group UTICK_Register_Masks */ - - -/* UTICK - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE (0x5000E000u) - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE_NS (0x4000E000u) - /** Peripheral UTICK0 base pointer */ - #define UTICK0 ((UTICK_Type *)UTICK0_BASE) - /** Peripheral UTICK0 base pointer */ - #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS { UTICK0_BASE } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS { UTICK0 } - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS_NS { UTICK0_NS } -#else - /** Peripheral UTICK0 base address */ - #define UTICK0_BASE (0x4000E000u) - /** Peripheral UTICK0 base pointer */ - #define UTICK0 ((UTICK_Type *)UTICK0_BASE) - /** Array initializer of UTICK peripheral base addresses */ - #define UTICK_BASE_ADDRS { UTICK0_BASE } - /** Array initializer of UTICK peripheral base pointers */ - #define UTICK_BASE_PTRS { UTICK0 } -#endif -/** Interrupt vectors for the UTICK peripheral type */ -#define UTICK_IRQS { UTICK0_IRQn } - -/*! - * @} - */ /* end of group UTICK_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- WWDT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer - * @{ - */ - -/** WWDT - Register Layout Typedef */ -typedef struct { - __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ - __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ - __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ - __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ - uint8_t RESERVED_0[4]; - __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ - __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ -} WWDT_Type; - -/* ---------------------------------------------------------------------------- - -- WWDT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Register_Masks WWDT Register Masks - * @{ - */ - -/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ -/*! @{ */ -#define WWDT_MOD_WDEN_MASK (0x1U) -#define WWDT_MOD_WDEN_SHIFT (0U) -/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently. - * 0b0..Stop. The watchdog timer is stopped. - * 0b1..Run. The watchdog timer is running. - */ -#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) -#define WWDT_MOD_WDRESET_MASK (0x2U) -#define WWDT_MOD_WDRESET_SHIFT (1U) -/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. - * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. - * 0b1..Reset. A watchdog time-out will cause a chip reset. - */ -#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) -#define WWDT_MOD_WDTOF_MASK (0x4U) -#define WWDT_MOD_WDTOF_SHIFT (2U) -#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) -#define WWDT_MOD_WDINT_MASK (0x8U) -#define WWDT_MOD_WDINT_SHIFT (3U) -#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) -#define WWDT_MOD_WDPROTECT_MASK (0x10U) -#define WWDT_MOD_WDPROTECT_SHIFT (4U) -/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. - * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. - * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. - */ -#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) -/*! @} */ - -/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ -/*! @{ */ -#define WWDT_TC_COUNT_MASK (0xFFFFFFU) -#define WWDT_TC_COUNT_SHIFT (0U) -#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) -/*! @} */ - -/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ -/*! @{ */ -#define WWDT_FEED_FEED_MASK (0xFFU) -#define WWDT_FEED_FEED_SHIFT (0U) -#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) -/*! @} */ - -/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ -/*! @{ */ -#define WWDT_TV_COUNT_MASK (0xFFFFFFU) -#define WWDT_TV_COUNT_SHIFT (0U) -#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) -/*! @} */ - -/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ -/*! @{ */ -#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) -#define WWDT_WARNINT_WARNINT_SHIFT (0U) -#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) -/*! @} */ - -/*! @name WINDOW - Watchdog Window compare value. */ -/*! @{ */ -#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) -#define WWDT_WINDOW_WINDOW_SHIFT (0U) -#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group WWDT_Register_Masks */ - - -/* WWDT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral WWDT base address */ - #define WWDT_BASE (0x5000C000u) - /** Peripheral WWDT base address */ - #define WWDT_BASE_NS (0x4000C000u) - /** Peripheral WWDT base pointer */ - #define WWDT ((WWDT_Type *)WWDT_BASE) - /** Peripheral WWDT base pointer */ - #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS) - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS { WWDT_BASE } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS { WWDT } - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS_NS { WWDT_NS } -#else - /** Peripheral WWDT base address */ - #define WWDT_BASE (0x4000C000u) - /** Peripheral WWDT base pointer */ - #define WWDT ((WWDT_Type *)WWDT_BASE) - /** Array initializer of WWDT peripheral base addresses */ - #define WWDT_BASE_ADDRS { WWDT_BASE } - /** Array initializer of WWDT peripheral base pointers */ - #define WWDT_BASE_PTRS { WWDT } -#endif -/** Interrupt vectors for the WWDT peripheral type */ -#define WWDT_IRQS { WDT_BOD_IRQn } - -/*! - * @} - */ /* end of group WWDT_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #else - #pragma pop - #endif -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/*! - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - * @{ - */ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang system_header - #endif -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma system_include -#endif - -/** - * @brief Mask and left-shift a bit field value for use in a register bit range. - * @param field Name of the register bit field. - * @param value Value of the bit field. - * @return Masked and shifted value. - */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) -/** - * @brief Mask and right-shift a register value to extract a bit field value. - * @param field Name of the register bit field. - * @param value Value of the register. - * @return Masked and shifted bit field value. - */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) - -/*! - * @} - */ /* end of group Bit_Field_Generic_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDK Compatibility - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDK_Compatibility_Symbols SDK Compatibility - * @{ - */ - -/** EMC CS base address */ -#define EMC_CS0_BASE (0x80000000u) -#define EMC_CS1_BASE (0x90000000u) -#define EMC_CS2_BASE (0x98000000u) -#define EMC_CS3_BASE (0x9C000000u) -#define EMC_DYCS0_BASE (0xA0000000u) -#define EMC_DYCS1_BASE (0xB0000000u) -#define EMC_DYCS2_BASE (0xC0000000u) -#define EMC_DYCS3_BASE (0xD0000000u) -#define EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE} -#define EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE} - -/** OTP API */ -typedef struct { - uint32_t (*otpInit)(void); /** Initializes OTP controller */ - uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask); /** Unlock one or more OTP banks for write access */ - uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask); /** Lock one or more OTP banks for write access */ - uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, - uint32_t lockWrite); /** Locks or unlocks write access to a register of an OTP bank and the write lock */ - uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, - uint32_t lockWrite); /** Locks or unlocks read access to a register of an OTP bank and the write lock */ - uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value); /** Program a single register in an OTP bank */ - uint32_t RESERVED_0[5]; - uint32_t (*rngRead)(void); /** Returns 32-bit number from hardware random number generator */ - uint32_t (*otpGetDriverVersion)(void); /** Returns the version of the OTP driver in ROM */ -} OTP_API_Type; - -/** ROM API */ -typedef struct { - __I uint32_t usbdApiBase; /** USB API Base */ - uint32_t RESERVED_0[13]; - __I OTP_API_Type *otpApiBase; /** OTP API Base */ - __I uint32_t aesApiBase; /** AES API Base */ - __I uint32_t secureApiBase; /** Secure API Base */ -} ROM_API_Type; - -/** ROM API base address */ -#define ROM_API_BASE (0x03000200u) -/** ROM API base pointer */ -#define ROM_API (*(ROM_API_Type**) ROM_API_BASE) -/** OTP API base pointer */ -#define OTP_API (ROM_API->otpApiBase) - -/*! - * @} - */ /* end of group SDK_Compatibility_Symbols */ - - -#endif /* _LPC55S69_CM33_CORE1_H_ */ - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core1_features.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core1_features.h deleted file mode 100644 index a9f4b6cc19..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core1_features.h +++ /dev/null @@ -1,292 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2018-08-22 -** Build: b190122 -** -** Abstract: -** Chip specific module features. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** -** ################################################################### -*/ - -#ifndef _LPC55S69_cm33_core1_FEATURES_H_ -#define _LPC55S69_cm33_core1_FEATURES_H_ - -/* SOC module features */ - -/* @brief CASPER availability on the SoC. */ -#define FSL_FEATURE_SOC_CASPER_COUNT (1) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (1) -/* @brief CTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_CTIMER_COUNT (5) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (2) -/* @brief FLASH availability on the SoC. */ -#define FSL_FEATURE_SOC_FLASH_COUNT (1) -/* @brief FLEXCOMM availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) -/* @brief GINT availability on the SoC. */ -#define FSL_FEATURE_SOC_GINT_COUNT (2) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (1) -/* @brief SECGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_SECGPIO_COUNT (1) -/* @brief HASHCRYPT availability on the SoC. */ -#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (8) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (8) -/* @brief INPUTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) -/* @brief IOCON availability on the SoC. */ -#define FSL_FEATURE_SOC_IOCON_COUNT (1) -/* @brief LPADC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPADC_COUNT (1) -/* @brief MAILBOX availability on the SoC. */ -#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) -/* @brief MRT availability on the SoC. */ -#define FSL_FEATURE_SOC_MRT_COUNT (1) -/* @brief OSTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) -/* @brief PINT availability on the SoC. */ -#define FSL_FEATURE_SOC_PINT_COUNT (1) -/* @brief SECPINT availability on the SoC. */ -#define FSL_FEATURE_SOC_SECPINT_COUNT (1) -/* @brief PMC availability on the SoC. */ -#define FSL_FEATURE_SOC_PMC_COUNT (1) -/* @brief POWERQUAD availability on the SoC. */ -#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) -/* @brief PUF availability on the SoC. */ -#define FSL_FEATURE_SOC_PUF_COUNT (1) -/* @brief RNG1 availability on the SoC. */ -#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCT availability on the SoC. */ -#define FSL_FEATURE_SOC_SCT_COUNT (1) -/* @brief SDIF availability on the SoC. */ -#define FSL_FEATURE_SOC_SDIF_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (9) -/* @brief SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCON_COUNT (1) -/* @brief SYSCTL1 availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) -/* @brief USART availability on the SoC. */ -#define FSL_FEATURE_SOC_USART_COUNT (8) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (1) -/* @brief USBFSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBFSH_COUNT (1) -/* @brief USBHSD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSD_COUNT (1) -/* @brief USBHSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSH_COUNT (1) -/* @brief USBPHY availability on the SoC. */ -#define FSL_FEATURE_SOC_USBPHY_COUNT (1) -/* @brief UTICK availability on the SoC. */ -#define FSL_FEATURE_SOC_UTICK_COUNT (1) -/* @brief WWDT availability on the SoC. */ -#define FSL_FEATURE_SOC_WWDT_COUNT (1) - -/* LPADC module features */ - -/* @brief FIFO availability on the SoC. */ -#define FSL_FEATURE_LPADC_FIFO_COUNT (2) -/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) -/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) -/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) -/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) -/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) -/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ -#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) -/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) -/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) -/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ -#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) -/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) -/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) -/* @brief Has calibration (bitfield CFG[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) -/* @brief Has offset trim (register OFSTRIM). */ -#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) - -/* CASPER module features */ - -/* @brief Base address of the CASPER dedicated RAM */ -#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) -/* @brief Interleaving of the CASPER dedicated RAM */ -#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1) - -/* DMA module features */ - -/* @brief Number of channels */ -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30) - -/* HASHCRYPT module features */ - -/* @brief the address of alias offset */ -#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) - -/* I2S module features */ - -/* @brief I2S support dual channel transfer. */ -#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) - -/* IOCON module features */ - -/* @brief Func bit field width */ -#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) - -/* MAILBOX module features */ - -/* @brief Mailbox side for current core */ -#define FSL_FEATURE_MAILBOX_SIDE_B (1) - -/* MRT module features */ - -/* @brief number of channels. */ -#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) - -/* PINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (10) - -/* POWERLIB module features */ - -/* @brief Niobe4's Powerlib API is different with other LPC series devices. */ -#define FSL_FEATURE_POWERLIB_NIOBE4_EXTEND (1) - -/* POWERQUAD module features */ - -/* @brief Sine and Cossine fix errata */ -#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1) - -/* PUF module features */ - -/* @brief Number of PUF key slots available on device. */ -#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) -/* @brief the shift status value */ -#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) - -/* SCT module features */ - -/* @brief Number of events */ -#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) -/* @brief Number of states */ -#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) -/* @brief Number of match capture */ -#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) -/* @brief Number of outputs */ -#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) - -/* SDIF module features */ - -/* @brief FIFO depth, every location is a WORD */ -#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) -/* @brief Max DMA buffer size */ -#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) -/* @brief Max source clock in HZ */ -#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) -/* @brief support 2 cards */ -#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) - -/* SECPINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) - -/* SYSCON module features */ - -/* @brief Pointer to ROM IAP entry functions */ -#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) -/* @brief Flash page size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) -/* @brief Flash sector size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) -/* @brief Flash size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592) -/* @brief Has Power Down mode */ -#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) -/* @brief CCM_ANALOG availability on the SoC. */ -#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) - -/* USB module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USB_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USB version */ -#define FSL_FEATURE_USB_VERSION (200) -/* @brief Number of the endpoint in USB FS */ -#define FSL_FEATURE_USB_EP_NUM (5) - -/* USBFSH module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBFSH version */ -#define FSL_FEATURE_USBFSH_VERSION (200) - -/* USBHSD module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBHSD version */ -#define FSL_FEATURE_USBHSD_VERSION (300) -/* @brief Number of the endpoint in USB HS */ -#define FSL_FEATURE_USBHSD_EP_NUM (6) - -/* USBHSH module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) -/* @brief USBHSH version */ -#define FSL_FEATURE_USBHSH_VERSION (300) - -/* UTICK module features */ - -/* @brief UTICK does not support PD configure. */ -#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) - -/* WWDT module features */ - -/* @brief WWDT does not support oscillator lock. */ -#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) -/* @brief WWDT does not support power down configure */ -#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) - -#endif /* _LPC55S69_cm33_core1_FEATURES_H_ */ - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/TOOLCHAIN_ARMC6/lib_power.ar b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/TOOLCHAIN_ARMC6/lib_power.ar deleted file mode 100644 index 16e59fbe10cb1be685ffe721a83a03887e80154a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8468 zcmb7Je{37am43UVevyt%Np`HninC%BM^$Zxq<%z7-E<||lx)kAFU_Svdo4*xjHy@> zS&EGl{}I#e^&p@?OXr+Ky{3h)F#`Y5KXg6hdN^DnBi97Z9fEU;#P#9Yo^nWWwy$Ye zi)o1>E&ILQo#k*P2knD)X1@2{eDmhb>~eS1u{V*OO5N|dN2`^f1kJWwYFbZU$nuDL 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file mode 100644 index d8e375e532..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/cmsis.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (C) 2009-2017 ARM Limited. All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * A generic CMSIS include header, pulling in LPC54608 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "fsl_device_registers.h" -#include "platform_regs.h" /* Platform registers */ -#include "platform_retarget.h" /* Peripherals base addresses */ - -#if defined(TARGET_LPC55S69_NS) -#include "cmsis_nvic.h" -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/fsl_device_registers.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/fsl_device_registers.h deleted file mode 100644 index 1455785a81..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/fsl_device_registers.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_DEVICE_REGISTERS_H__ -#define __FSL_DEVICE_REGISTERS_H__ - -/* - * Include the cpu specific register header files. - * - * The CPU macro should be declared in the project or makefile. - */ -#if (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JET98_cm33_core0)) - -#define LPC55S69_cm33_core0_SERIES - -/* CMSIS-style register definitions */ -#include "LPC55S69_cm33_core0.h" -/* CPU specific feature definitions */ -#include "LPC55S69_cm33_core0_features.h" - -#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JET98_cm33_core1)) - -#define LPC55S69_cm33_core1_SERIES - -/* CMSIS-style register definitions */ -#include "LPC55S69_cm33_core1.h" -/* CPU specific feature definitions */ -#include "LPC55S69_cm33_core1_features.h" - -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_DEVICE_REGISTERS_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/platform_regs.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/platform_regs.h deleted file mode 100644 index a7f45b9166..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/platform_regs.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2016-2018 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __ARM_LTD_NIOBE_REGS_H__ -#define __ARM_LTD_NIOBE_REGS_H__ - -#include -#include "platform_retarget.h" - -/* Secure System Control (SYSCTRL) Alias */ -#define CMSDK_SYSCTRL_BASE_S SYSCON_BASE + 0xFA4 - -/* sysctrl memory mapped register access structure */ -struct sysctrl_t { - union { - volatile uint32_t secdbgstat; /* (R/ ) Secure Debug Configuration - * Status Register*/ - volatile uint32_t secdbgset; /* ( /W) Secure Debug Configuration - * Set Register */ - volatile uint32_t secdbgclr; /* ( /W) Secure Debug Configuration - * Clear Register */ - }; -}; - -#endif /* __ARM_LTD_NIOBE_REGS_H__ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/platform_retarget.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/platform_retarget.h deleted file mode 100644 index f07308a949..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/platform_retarget.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2017-2018 Arm Limited - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/** - * \file platform_retarget.h - * \brief This file defines all the peripheral base addresses for Niobe platform. - */ - -#ifndef __ARM_LTD_NIOBE_RETARGET_H__ -#define __ARM_LTD_NIOBE_RETARGET_H__ - -#include "platform_regs.h" /* Platform registers */ -#include "LPC55S69_cm33_core0.h" - - -/* SRAM MPC ranges and limits */ -/* Internal memory */ -#define MPC_ISRAM0_RANGE_BASE_NS 0x20000000 -#define MPC_ISRAM0_RANGE_LIMIT_NS 0x2000FFFF -#define MPC_ISRAM0_RANGE_BASE_S 0x30000000 -#define MPC_ISRAM0_RANGE_LIMIT_S 0x3000FFFF - -#define MPC_ISRAM1_RANGE_BASE_NS 0x20010000 -#define MPC_ISRAM1_RANGE_LIMIT_NS 0x2001FFFF -#define MPC_ISRAM1_RANGE_BASE_S 0x30010000 -#define MPC_ISRAM1_RANGE_LIMIT_S 0x3001FFFF - -#define MPC_ISRAM2_RANGE_BASE_NS 0x20020000 -#define MPC_ISRAM2_RANGE_LIMIT_NS 0x2002FFFF -#define MPC_ISRAM2_RANGE_BASE_S 0x30020000 -#define MPC_ISRAM2_RANGE_LIMIT_S 0x3002FFFF - -#define MPC_ISRAM3_RANGE_BASE_NS 0x20030000 -#define MPC_ISRAM3_RANGE_LIMIT_NS 0x2003FFFF -#define MPC_ISRAM3_RANGE_BASE_S 0x30030000 -#define MPC_ISRAM3_RANGE_LIMIT_S 0x3003FFFF - -#define MPC_ISRAM4_RANGE_BASE_NS 0x20040000 -#define MPC_ISRAM4_RANGE_LIMIT_NS 0x20043FFF -#define MPC_ISRAM4_RANGE_BASE_S 0x30040000 -#define MPC_ISRAM4_RANGE_LIMIT_S 0x30043FFF - -/* Code SRAM memory */ -#define MPC_CODE_SRAM_RANGE_BASE_NS (0x04000000) -#define MPC_CODE_SRAM_RANGE_LIMIT_NS (0x04007FFF) -#define MPC_CODE_SRAM_RANGE_BASE_S (0x14000000) -#define MPC_CODE_SRAM_RANGE_LIMIT_S (0x14007FFF) - -/* Internal Flash memory */ -#define FLASH0_BASE_S (0x10000000) -#define FLASH0_BASE_NS (0x00000000) -#define FLASH0_SIZE (0x0009FFFF) /* 640 kB */ -#define FLASH0_SECTOR_SIZE (0x00008000) /* 32 kB */ -#define FLASH0_PAGE_SIZE (0x00000200) /* 512 B */ -#define FLASH0_PROGRAM_UNIT (0x4) /* Minimum write size */ - -#endif /* __ARM_LTD_NIOBE_RETARGET_H__ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/system_LPC55S69_cm33_core0.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/system_LPC55S69_cm33_core0.c deleted file mode 100644 index 2b2cd23ed4..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/system_LPC55S69_cm33_core0.c +++ /dev/null @@ -1,369 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b181219 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** -** ################################################################### -*/ - -/*! - * @file LPC55S69_cm33_core0 - * @version 1.0 - * @date 2018-08-22 - * @brief Device specific configuration file for LPC55S69_cm33_core0 - * (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "fsl_device_registers.h" - -/* PLL0 SSCG control1 */ -#define PLL_SSCG_MD_FRACT_P 0U -#define PLL_SSCG_MD_INT_P 25U -#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P) -#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P) - -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void) -{ - uint32_t preDiv = 1; - - /* Direct input is not used? */ - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0) - { - preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; - if (preDiv == 0) - { - preDiv = 1; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void) -{ - uint32_t postDiv = 1; - - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0) - { - if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) - { - postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; - } - else - { - postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); - } - if (postDiv == 0) - { - postDiv = 2; - } - } - return postDiv; -} - -/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ -static float findPll0MMult(void) -{ - float mMult = 1; - float mMult_fract; - uint32_t mMult_int; - - if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) - { - mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT; - } - else - { - mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P); - mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M)/(1 << PLL_SSCG_MD_INT_P)); - mMult = (float)mMult_int + mMult_fract; - } - if (mMult == 0) - { - mMult = 1; - } - return mMult; -} - -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void) -{ - uint32_t preDiv = 1; - - /* Direct input is not used? */ - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0) - { - preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; - if (preDiv == 0) - { - preDiv = 1; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL1 PDEC setting */ -static uint32_t findPll1PostDiv(void) -{ - uint32_t postDiv = 1; - - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0) - { - if (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) - { - postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; - } - else - { - postDiv = 2 * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); - } - if (postDiv == 0) - { - postDiv = 2; - } - } - return postDiv; -} - -/* Get multiplier (M) from PLL1 MDEC settings */ -static uint32_t findPll1MMult(void) -{ - uint32_t mMult = 1; - - mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; - - if (mMult == 0) - { - mMult = 1; - } - return mMult; -} - -/* Get FRO 12M Clk */ -/*! brief Return Frequency of FRO 12MHz - * return Frequency of FRO 12MHz - */ -static uint32_t CLOCK_GetFro12MFreq(void) -{ - return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ? - 0 : - (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U; -} - -/* Get FRO 1M Clk */ -/*! brief Return Frequency of FRO 1MHz - * return Frequency of FRO 1MHz - */ -static uint32_t CLOCK_GetFro1MFreq(void) -{ - return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U; -} - -/* Get EXT OSC Clk */ -/*! brief Return Frequency of External Clock - * return Frequency of External Clock. If no external clock is used returns 0. - */ -static uint32_t CLOCK_GetExtClkFreq(void) -{ - return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? CLK_CLK_IN : 0U; -} - -/* Get HF FRO Clk */ -/*! brief Return Frequency of High-Freq output of FRO - * return Frequency of High-Freq output of FRO - */ -static uint32_t CLOCK_GetFroHfFreq(void) -{ - return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ? - 0 : - (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U; -} - -/* Get RTC OSC Clk */ -/*! brief Return Frequency of 32kHz osc - * return Frequency of 32kHz osc - */ -static uint32_t CLOCK_GetOsc32KFreq(void) -{ - return ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(0))) ? - CLK_RTC_32K_CLK : - ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(1))) ? - CLK_RTC_32K_CLK : - 0U; -} - - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInit (void) { -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ - - SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access (enable PowerQuad) */ - - SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ - -#if defined(__MCUXPRESSO) - extern void(*const g_pfnVectors[]) (void); - SCB->VTOR = (uint32_t) &g_pfnVectors; -#else - extern void *__Vectors; - SCB->VTOR = (uint32_t) &__Vectors; -#endif - SYSCON->TRACECLKDIV = 0; -/* Optionally enable RAM banks that may be off by default at reset */ -#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) - SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK - | SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK; -#endif - SystemInitHook(); -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - float workRate; - uint64_t workRate1; - - switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) - { - case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ - switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = CLOCK_GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = CLOCK_GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = CLOCK_GetFro1MFreq(); - break; - default: /* = 0x03 = FRO 96 MHz (fro_hf) */ - clkRate = CLOCK_GetFroHfFreq(); - break; - } - break; - case 0x01: /* PLL0 clock (pll0_clk)*/ - switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = CLOCK_GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = CLOCK_GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = CLOCK_GetFro1MFreq(); - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = CLOCK_GetOsc32KFreq(); - break; - default: - break; - } - if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0)) - { - prediv = findPll0PreDiv(); - postdiv = findPll0PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* MDEC used for rate */ - workRate = (float)clkRate * (float)findPll0MMult(); - clkRate = (uint32_t)(workRate / ((float)postdiv)); - } - break; - case 0x02: /* PLL1 clock (pll1_clk)*/ - switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = CLOCK_GetFro12MFreq(); - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = CLOCK_GetExtClkFreq(); - break; - case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = CLOCK_GetFro1MFreq(); - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = CLOCK_GetOsc32KFreq(); - break; - default: - break; - } - if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0)) - { - /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ - prediv = findPll1PreDiv(); - postdiv = findPll1PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - - /* MDEC used for rate */ - workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult(); - clkRate = workRate1 / ((uint64_t)postdiv); - } - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = CLOCK_GetOsc32KFreq(); - break; - default: - break; - } - SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1); -} - -/* ---------------------------------------------------------------------------- - -- SystemInitHook() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInitHook (void) { - /* Void implementation of the weak function. */ -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/system_LPC55S69_cm33_core0.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/system_LPC55S69_cm33_core0.h deleted file mode 100644 index 705e6508a4..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/system_LPC55S69_cm33_core0.h +++ /dev/null @@ -1,110 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b181219 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** -** ################################################################### -*/ - -/*! - * @file LPC55S69_cm33_core0 - * @version 1.0 - * @date 2018-08-22 - * @brief Device specific configuration file for LPC55S69_cm33_core0 (header - * file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_LPC55S69_cm33_core0_H_ -#define _SYSTEM_LPC55S69_cm33_core0_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ -#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ -#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ -#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ -#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ -#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -/** - * @brief SystemInit function hook. - * - * This weak function allows to call specific initialization code during the - * SystemInit() execution.This can be used when an application specific code needs - * to be called as close to the reset entry as possible (for example the Multicore - * Manager MCMGR_EarlyInit() function call). - * NOTE: No global r/w variables can be used in this hook function because the - * initialization of these variables happens after this function. - */ -void SystemInitHook (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_LPC55S69_cm33_core0_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/system_LPC55S69_cm33_core1.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/system_LPC55S69_cm33_core1.h deleted file mode 100644 index 8da7ec5bdd..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/system_LPC55S69_cm33_core1.h +++ /dev/null @@ -1,110 +0,0 @@ -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JET98_cm33_core1 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b181219 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-08-22) -** Initial version based on v0.2UM -** -** ################################################################### -*/ - -/*! - * @file LPC55S69_cm33_core1 - * @version 1.0 - * @date 2018-08-22 - * @brief Device specific configuration file for LPC55S69_cm33_core1 (header - * file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_LPC55S69_cm33_core1_H_ -#define _SYSTEM_LPC55S69_cm33_core1_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ -#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ -#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ -#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ -#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ -#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -/** - * @brief SystemInit function hook. - * - * This weak function allows to call specific initialization code during the - * SystemInit() execution.This can be used when an application specific code needs - * to be called as close to the reset entry as possible (for example the Multicore - * Manager MCMGR_EarlyInit() function call). - * NOTE: No global r/w variables can be used in this hook function because the - * initialization of these variables happens after this function. - */ -void SystemInitHook (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_LPC55S69_cm33_core1_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_anactrl.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_anactrl.c deleted file mode 100644 index ac9c38a7c9..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_anactrl.c +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (c) 2018, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_anactrl.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.anactrl" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for ANACTRL module. - * - * @param base ANACTRL peripheral base address - */ -static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to ANACTRL bases for each instance. */ -static ANACTRL_Type *const s_anactrlBases[] = ANACTRL_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to ANACTRL clocks for each instance. */ -static const clock_ip_name_t s_anactrlClocks[] = ANALOGCTRL_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * brief Get the ANACTRL instance from peripheral base address. - * - * param base ANACTRL peripheral base address. - * return ANACTRL instance. - */ -static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_anactrlBases); instance++) - { - if (s_anactrlBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_anactrlBases)); - - return instance; -} - -/*! - * @brief Enable the access to ANACTRL registers and initialize ANACTRL module. - * - * @param base ANACTRL peripheral base address. - */ -void ANACTRL_Init(ANACTRL_Type *base) -{ - assert(NULL != base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock for ANACTRL instance. */ - CLOCK_EnableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief De-initialize ANACTRL module. - * - * @param base ANACTRL peripheral base address. - */ -void ANACTRL_Deinit(ANACTRL_Type *base) -{ - assert(NULL != base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock for ANACTRL instance. */ - CLOCK_DisableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Set the on-chip high-speed Free Running Oscillator. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure. - */ -void ANACTRL_SetFro192M(ANACTRL_Type *base, anactrl_fro192M_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32 = 0; - - /* Set FRO trim values. */ - base->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_WRTRIM_MASK; - tmp32 |= ANACTRL_FRO192M_CTRL_BIAS_TRIM(config->biasTrim) | ANACTRL_FRO192M_CTRL_TEMP_TRIM(config->tempTrim) | - ANACTRL_FRO192M_CTRL_DAC_TRIM(config->dacTrim); - - if (config->enable12MHzClk) - { - tmp32 |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK; - } - if (config->enable48MhzClk) - { - tmp32 |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK; - } - if (config->enable96MHzClk) - { - tmp32 |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; - } - - if (config->enableAnalogTestBus) - { - tmp32 |= ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK; - } - - base->FRO192M_CTRL |= tmp32; -} - -/*! - * @brief Get the default configuration of FRO192M. - * The default values are: - * code - * config->biasTrim = 0x1AU; - * config->tempTrim = 0x20U; - * config->enable12MHzClk = true; - * config->enable48MhzClk = true; - * config->dacTrim = 0x80U; - * config->enableAnalogTestBus = false; - * config->enable96MHzClk = false; - * encode - * @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure. - */ -void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - - config->biasTrim = 0x1AU; - config->tempTrim = 0x20U; - config->enable12MHzClk = true; - config->enable48MhzClk = true; - config->dacTrim = 0x80U; - config->enableAnalogTestBus = false; - config->enable96MHzClk = false; -} - -/*! - * @brief Set the 32 MHz Crystal oscillator. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure. - */ -void ANACTRL_SetXo32M(ANACTRL_Type *base, anactrl_xo32M_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32 = 0U; - - /* Set XO32M CTRL. */ - if (config->enableACBufferBypass) - { - tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; - } - if (config->enablePllUsbOutput) - { - tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; - } - if (config->enableSysCLkOutput) - { - tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; - } - base->XO32M_CTRL = tmp32; - - /* Set LDO XO32M. */ - tmp32 = ANACTRL_LDO_XO32M_HIGHZ(config->LDOOutputMode) | ANACTRL_LDO_XO32M_VOUT(config->LDOOutputLevel) | - ANACTRL_LDO_XO32M_IBIAS(config->bias) | ANACTRL_LDO_XO32M_STABMODE(config->stability); - if (config->enableLDOBypass) - { - tmp32 |= ANACTRL_LDO_XO32M_BYPASS_MASK; - } - - base->LDO_XO32M = tmp32; -} - -/*! - * @brief Get the default configuration of XO32M. - * The default values are: - * code - * config->enableACBufferBypass = false; - * config->enablePllUsbOutput = false; - * config->enableSysCLkOutput = false; - * config->enableLDOBypass = false; - * config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode; - * config->LDOOutputLevel = kANACTRL_LDOOutputLevel4; - * config->bias = 2U; - * config->stability = 3U; - * encode - * @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure. - */ -void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - - config->enableACBufferBypass = false; - config->enablePllUsbOutput = false; - config->enableSysCLkOutput = false; - config->enableLDOBypass = false; - config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode; - config->LDOOutputLevel = kANACTRL_LDOOutputLevel4; - config->bias = 2U; - config->stability = 3U; -} - -/*! - * @brief Set the ring oscillators. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to ring osc configuration structure. Refer to "anactrl_ring_osc_config_t" structure. - */ -void ANACTRL_SetRingOsc(ANACTRL_Type *base, anactrl_ring_osc_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32 = 0U; - - /* Configure the first ring oscillator. */ - tmp32 = ANACTRL_RINGO0_CTRL_SL(config->ringOscSel) | ANACTRL_RINGO0_CTRL_FS(config->ringOscFreqOutputDiv) | - ANACTRL_RINGO0_CTRL_SWN_SWP(config->pnRingOscMode) | ANACTRL_RINGO0_CTRL_E_ND0_MASK | - ANACTRL_RINGO0_CTRL_E_ND1_MASK | ANACTRL_RINGO0_CTRL_E_NR0_MASK | ANACTRL_RINGO0_CTRL_E_NR1_MASK | - ANACTRL_RINGO0_CTRL_E_IV0_MASK | ANACTRL_RINGO0_CTRL_E_IV1_MASK | ANACTRL_RINGO0_CTRL_E_PN0_MASK | - ANACTRL_RINGO0_CTRL_E_PN1_MASK | ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK | - ANACTRL_RINGO0_CTRL_DIVISOR(config->ringOscOutClkDiv); - base->RINGO0_CTRL = tmp32; - - /* Configure the second and third ring oscillator. */ - tmp32 = ANACTRL_RINGO1_CTRL_S(config->ringOscSel) | ANACTRL_RINGO1_CTRL_FS(config->ringOscFreqOutputDiv) | - ANACTRL_RINGO1_CTRL_E_R24_MASK | ANACTRL_RINGO1_CTRL_E_R35_MASK | ANACTRL_RINGO1_CTRL_E_M2_MASK | - ANACTRL_RINGO1_CTRL_E_M3_MASK | ANACTRL_RINGO1_CTRL_E_M4_MASK | ANACTRL_RINGO1_CTRL_E_M5_MASK | - ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK | ANACTRL_RINGO1_CTRL_DIVISOR(config->ringOscOutClkDiv); - base->RINGO1_CTRL = tmp32; - base->RINGO2_CTRL = tmp32; - - /* Ensure the Riongo module is enabled. */ - base->RINGO0_CTRL &= ~ANACTRL_RINGO0_CTRL_PD_MASK; - base->RINGO1_CTRL &= ~ANACTRL_RINGO1_CTRL_PD_MASK; - base->RINGO2_CTRL &= ~ANACTRL_RINGO2_CTRL_PD_MASK; -} - -/*! - * @brief Get the default configuration of ring oscillators. - * The default values are: - * code - * config->ringOscSel = kANACTRL_ShortRingOsc; - * config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput; - * config->pnRingOscMode = kANACTRL_NormalMode; - * config->ringOscOutClkDiv = 0U; - * encode - * @param config Pointer to ring oscillator configuration structure. Refer to "anactrl_ring_osc_config_t" structure. - */ -void ANACTRL_GetDefaultRingOscConfig(anactrl_ring_osc_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - - config->ringOscSel = kANACTRL_ShortRingOsc; - config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput; - config->pnRingOscMode = kANACTRL_NormalMode; - config->ringOscOutClkDiv = 0U; -} - -/*! - * @brief Measure Frequency - * - * This function measures target frequency according to a accurate reference frequency.The formula is: - * Ftarget = (CAPVAL * Freference) / ((1<= 2U); - - uint32_t targetClkFreq = 0U; - uint32_t capval = 0U; - - /* Init a measurement cycle. */ - base->FREQ_ME_CTRL = ANACTRL_FREQ_ME_CTRL_PROG_MASK + ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(scale); - while (ANACTRL_FREQ_ME_CTRL_PROG_MASK == (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_PROG_MASK)) - { - } - - /* Calculate the target clock frequency. */ - capval = (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK); - targetClkFreq = (capval * refClkFreq) / ((1 << scale) - 1); - - return targetClkFreq; -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_anactrl.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_anactrl.h deleted file mode 100644 index 60af30dc1b..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_anactrl.h +++ /dev/null @@ -1,458 +0,0 @@ -/* - * Copyright (c) 2018, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __FSL_ANACTRL_H__ -#define __FSL_ANACTRL_H__ - -#include "fsl_common.h" - -/*! - * @addtogroup anactrl - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief ANACTRL driver version. */ -#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */` - -/*! - * @brief ANACTRL interrupt flags - */ -enum _anactrl_interrupt_flags -{ - kANACTRL_BodVbatFlag = - ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before Interrupt Enable. */ - kANACTRL_BodVbatInterruptFlag = - ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status after Interrupt Enable. */ - kANACTRL_BodVbatPowerFlag = - ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power status output. */ - kANACTRL_BodCoreFlag = - ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before Interrupt Enable. */ - kANACTRL_BodCoreInterruptFlag = - ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status after Interrupt Enable. */ - kANACTRL_BodCorePowerFlag = - ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK, /*!< Current value of BOD CORE power status output. */ - kANACTRL_DcdcFlag = - ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK, /*!< DCDC Interrupt status before Interrupt Enable. */ - kANACTRL_DcdcInterruptFlag = - ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after Interrupt Enable. */ - kANACTRL_DcdcPowerFlag = - ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK, /*!< Current value of DCDC power status output. */ -}; - -/*! - * @brief ANACTRL interrupt control - */ -enum _anactrl_interrupt -{ - kANACTRL_BodVbatInterruptEnable = - ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt control. */ - kANACTRL_BodCoreInterruptEnable = - ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK, /*!< BOD CORE interrupt control. */ - kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK, /*!< DCDC interrupt control. */ - kANACTRL_BodVbatInterruptClear = - ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK, /*!< BOD VBAT interrupt clear.1: Clear the interrupt. - Self-cleared bit. */ - kANACTRL_BodCoreInterruptClear = - ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK, /*!< BOD CORE interrupt clear.1: Clear the interrupt. - Self-cleared bit. */ - kANACTRL_DcdcInterruptClear = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK, /*!< DCDC interrupt clear.1: Clear the - interrupt. Self-cleared bit. */ -}; - -/*! - * @brief ANACTRL status flags - */ -enum _anactrl_flags -{ - kANACTRL_PMUId = ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK, /*!< Power Management Unit (PMU) analog macro-bloc - identification number. */ - kANACTRL_OSCId = - ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK, /*!< Oscillators analog macro-bloc identification number. */ - kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK, /*!< Flash power-down status. */ - kANACTRL_FlashInitErrorFlag = - ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization error status. */ - kANACTRL_FinalTestFlag = - ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK, /*!< Indicates current status of final test. */ -}; - -/*! - * @brief ANACTRL FRO192M and XO32M status flags - */ -enum _anactrl_osc_flags -{ - kANACTRL_OutputClkValidFlag = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK, /*!< Output clock valid signal. */ - kANACTRL_CCOThresholdVoltageFlag = - ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK, /*!< CCO threshold voltage detector output (signal vcco_ok). */ - kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK - << 16U, /*!< Indicates XO out frequency statibilty. */ -}; - -/*! - * @brief LDO output mode - */ -typedef enum _anactrl_ldo_output_mode -{ - kANACTRL_LDOOutputHighNormalMode = 0U, /*!< Output in High normal state. */ - kANACTRL_LDOOutputHighImpedanceMode = 1U, /*!< Output in High Impedance state. */ -} anactrl_ldo_output_mode_t; - -/*! - * @brief LDO output level - */ -typedef enum _anactrl_ldo_output_level -{ - kANACTRL_LDOOutputLevel0 = 0U, /*!< Output level 0.750 V. */ - kANACTRL_LDOOutputLevel1, /*!< Output level 0.775 V. */ - kANACTRL_LDOOutputLevel2, /*!< Output level 0.800 V. */ - kANACTRL_LDOOutputLevel3, /*!< Output level 0.825 V. */ - kANACTRL_LDOOutputLevel4, /*!< Output level 0.850 V. */ - kANACTRL_LDOOutputLevel5, /*!< Output level 0.875 V. */ - kANACTRL_LDOOutputLevel6, /*!< Output level 0.900 V. */ - kANACTRL_LDOOutputLevel7, /*!< Output level 0.925 V. */ -} anactrl_ldo_output_level_t; - -/*! - * @brief Select short or long ring osc - */ -typedef enum _anactrl_ring_osc_selector -{ - kANACTRL_ShortRingOsc = 0U, /*!< Select short ring osc (few elements). */ - kANACTRL_LongRingOsc = 1U, /*!< Select long ring osc (many elements). */ -} anactrl_ring_osc_selector_t; - -/*! - * @brief Ring osc frequency output divider - */ -typedef enum _anactrl_ring_osc_freq_output_divider -{ - kANACTRL_HighFreqOutput = 0U, /*!< High frequency output (frequency lower than 100 MHz). */ - kANACTRL_LowFreqOutput = 1U, /*!< Low frequency output (frequency lower than 10 MHz). */ -} anactrl_ring_osc_freq_output_divider_t; - -/*! - * @brief PN-Ring osc (P-Transistor and N-Transistor processing) control. - */ -typedef enum _anactrl_pn_ring_osc_mode -{ - kANACTRL_NormalMode = 0U, /*!< Normal mode. */ - kANACTRL_PMonitorPTransistorMode = 1U, /*!< P-Monitor mode. Measure with weak P transistor. */ - kANACTRL_PMonitorNTransistorMode = 2U, /*!< P-Monitor mode. Measure with weak N transistor. */ - kANACTRL_NotUse = 3U, /*!< Do not use. */ -} anactrl_pn_ring_osc_mode_t; - -/*! - * @breif Configuration for FRO192M - * - * This structure holds the configuration settings for the on-chip high-speed Free Running Oscillator. To initialize - * this structure to reasonable defaults, call the ANACTRL_GetDefaultFro192MConfig() function and pass a - * pointer to your config structure instance. - */ -typedef struct _anactrl_fro192M_config -{ - uint8_t biasTrim; /*!< Set bias trimming value (course frequency trimming). */ - uint8_t tempTrim; /*!< Set temperature coefficient trimming value. */ - uint8_t dacTrim; /*!< Set curdac trimming value (fine frequency trimming) This trim is used to - adjust the frequency, given that the bias and temperature trim are set. */ - bool enable12MHzClk; /*!< Enable 12MHz clock. */ - bool enable48MhzClk; /*!< Enable 48MHz clock. */ - bool enable96MHzClk; /*!< Enable 96MHz clock. */ - bool enableAnalogTestBus; /*!< Enable analog test bus. */ -} anactrl_fro192M_config_t; - -/*! - * @breif Configuration for XO32M - * - * This structure holds the configuration settings for the 32 MHz crystal oscillator. To initialize this - * structure to reasonable defaults, call the ANACTRL_GetDefaultXo32MConfig() function and pass a - * pointer to your config structure instance. - */ -typedef struct _anactrl_xo32M_config -{ - bool enableACBufferBypass; /*!< Enable XO AC buffer bypass in pll and top level. */ - bool enablePllUsbOutput; /*!< Enable XO 32 MHz output to USB HS PLL. */ - bool enableSysCLkOutput; /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */ - bool enableLDOBypass; /*!< Activate LDO bypass. */ - anactrl_ldo_output_mode_t LDOOutputMode; /*!< Set LDO output mode. */ - anactrl_ldo_output_level_t LDOOutputLevel; /*!< Set LDO output level. */ - uint8_t bias; /*!< Adjust the biasing current. */ - uint8_t stability; /*!< Stability configuration. */ -} anactrl_xo32M_config_t; - -/*! - * @breif Configuration for ring oscillator - * - * This structure holds the configuration settings for the three ring oscillators. To initialize this - * structure to reasonable defaults, call the ANACTRL_GetDefaultRingOscConfig() function and pass a - * pointer to your config structure instance. - */ -typedef struct _anactrl_ring_osc_config -{ - anactrl_ring_osc_selector_t ringOscSel; - anactrl_ring_osc_freq_output_divider_t ringOscFreqOutputDiv; - anactrl_pn_ring_osc_mode_t pnRingOscMode; - uint8_t ringOscOutClkDiv; -} anactrl_ring_osc_config_t; -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Enable the access to ANACTRL registers and initialize ANACTRL module. - * - * @param base ANACTRL peripheral base address. - */ -void ANACTRL_Init(ANACTRL_Type *base); - -/*! - * @brief De-initialize ANACTRL module. - * - * @param base ANACTRL peripheral base address. - */ -void ANACTRL_Deinit(ANACTRL_Type *base); -/* @} */ - -/*! - * @name Set oscillators - * @{ - */ - -/*! - * @brief Set the on-chip high-speed Free Running Oscillator. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure. - */ -void ANACTRL_SetFro192M(ANACTRL_Type *base, anactrl_fro192M_config_t *config); - -/*! - * @brief Get the default configuration of FRO192M. - * The default values are: - * code - * config->biasTrim = 0x1AU; - * config->tempTrim = 0x20U; - * config->enable12MHzClk = true; - * config->enable48MhzClk = true; - * config->dacTrim = 0x80U; - * config->enableAnalogTestBus = false; - * config->enable96MHzClk = false; - * encode - * @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure. - */ -void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config); - -/*! - * @brief Set the 32 MHz Crystal oscillator. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure. - */ -void ANACTRL_SetXo32M(ANACTRL_Type *base, anactrl_xo32M_config_t *config); - -/*! - * @brief Get the default configuration of XO32M. - * The default values are: - * code - * config->enableACBufferBypass = false; - * config->enablePllUsbOutput = false; - * config->enableSysCLkOutput = false; - * config->enableLDOBypass = false; - * config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode; - * config->LDOOutputLevel = kANACTRL_LDOOutputLevel4; - * config->bias = 2U; - * config->stability = 3U; - * encode - * @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure. - */ -void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config); - -/*! - * @brief Set the ring oscillators. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to ring osc configuration structure. Refer to "anactrl_ring_osc_config_t" structure. - */ -void ANACTRL_SetRingOsc(ANACTRL_Type *base, anactrl_ring_osc_config_t *config); - -/*! - * @brief Get the default configuration of ring oscillators. - * The default values are: - * code - * config->ringOscSel = kANACTRL_ShortRingOsc; - * config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput; - * config->pnRingOscMode = kANACTRL_NormalMode; - * config->ringOscOutClkDiv = 0U; - * encode - * @param config Pointer to ring oscillator configuration structure. Refer to "anactrl_ring_osc_config_t" structure. - */ -void ANACTRL_GetDefaultRingOscConfig(anactrl_ring_osc_config_t *config); -/* @} */ - -/*! - * @name ADC control - * @{ - */ - -/*! - * @brief Enable VBAT divider branch. - * - * @param base ANACTRL peripheral base address. - * @param enable switcher to the function. - */ -static inline void ANACTRL_EnableAdcVBATDivider(ANACTRL_Type *base, bool enable) -{ - if (enable) - { - base->ADC_CTRL |= ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK; - } - else - { - base->ADC_CTRL &= ~ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK; - } -} -/* @} */ - -/*! - * @name Measure Frequency - * @{ - */ - -/*! - * @brief Measure Frequency - * - * This function measures target frequency according to a accurate reference frequency.The formula is: - * Ftarget = (CAPVAL * Freference) / ((1<BOD_DCDC_INT_CTRL |= (0x15U & mask); -} - -/*! - * @brief Disable the ANACTRL interrupts. - * - * @param bas ANACTRL peripheral base address. - * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. - */ -static inline void ANACTRL_DisableInterrupt(ANACTRL_Type *base, uint32_t mask) -{ - base->BOD_DCDC_INT_CTRL = (base->BOD_DCDC_INT_CTRL & ~0x2AU) | (mask & 0x2AU); -} -/* @} */ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Get ANACTRL status flags. - * - * This function gets Analog control status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_flags. - * For example, to check whether the flash is in power down mode: - * @code - * if (kANACTRL_FlashPowerDownFlag & ANACTRL_ANACTRL_GetStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL status flags which are given in the enumerators in the @ref _anactrl_flags. - */ -static inline uint32_t ANACTRL_GetStatusFlags(ANACTRL_Type *base) -{ - return base->ANALOG_CTRL_STATUS; -} - -/*! - * @brief Get ANACTRL oscillators status flags. - * - * This function gets Anactrl oscillators status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_osc_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_osc_flags. - * For example, to check whether the FRO192M clock output is valid: - * @code - * if (kANACTRL_OutputClkValidFlag & ANACTRL_ANACTRL_GetOscStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. - */ -static inline uint32_t ANACTRL_GetOscStatusFlags(ANACTRL_Type *base) -{ - return (base->FRO192M_STATUS & 0xFFU) | ((base->XO32M_STATUS & 0xFFU) << 16U); -} - -/*! - * @brief Get ANACTRL interrupt status flags. - * - * This function gets Anactrl interrupt status flags. The flags are returned as the logical - * OR value of the enumerators @ref _anactrl_interrupt_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _anactrl_interrupt_flags. - * For example, to check whether the VBAT voltage level is above the threshold: - * @code - * if (kANACTRL_BodVbatPowerFlag & ANACTRL_ANACTRL_GetInterruptStatusFlags(ANACTRL)) - * { - * ... - * } - * @endcode - * - * @param base ANACTRL peripheral base address. - * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. - */ -static inline uint32_t ANACTRL_GetInterruptStatusFlags(ANACTRL_Type *base) -{ - return base->BOD_DCDC_INT_STATUS & 0x1FFU; -} -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/* @}*/ - -#endif /* __FSL_ANACTRL_H__ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_casper.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_casper.c deleted file mode 100644 index 543869bd8a..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_casper.c +++ /dev/null @@ -1,2662 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_casper.h" -#include /* ceil TODO check if really need it */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.casper" -#endif - -#define CASPER_RAM_BASE_NS (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS) - -#if defined(FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED) && FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED -#define CASPER_RAM_OFFSET (0xE) -#define INTERLEAVE(addr) \ - (((((((addr) >> 2) & 0x00000001) << CASPER_RAM_OFFSET) + (((addr) >> 3) << 2) + ((addr)&0x00000003)) & 0xFFFF) | \ - s_casperRamBase) -#define DEINTERLEAVE(addr) INTERLEAVE(addr) -#define GET_WORD(addr) (*((uint32_t *)DEINTERLEAVE((uint32_t)(addr)))) -#define GET_DWORD(addr) (((uint64_t)GET_WORD(addr)) | (((uint64_t)GET_WORD(((uint32_t)(addr)) + 4)) << 32)) -#define SET_WORD(addr, value) *((uint32_t *)INTERLEAVE((uint32_t)(addr))) = ((uint32_t)(value)) -#define SET_DWORD(addr, value) \ - do \ - { \ - SET_WORD(addr, (uint32_t)(value & 0xFFFFFFFF)); \ - SET_WORD(((uint32_t)(addr)) + 4, (uint32_t)((value & 0xFFFFFFFF00000000) >> 32)); \ - } while (0) - -/* memcopy is always word aligned */ -/* interleaved to interleaved - static void CASPER_MEMCPY_I2I(void *dst, const void *src, size_t siz) - */ -#define CASPER_MEMCPY_I2I(dst, src, siz) \ - \ -{ \ - uint32_t *dst32 = (uint32_t *)dst, *src32 = (uint32_t *)src; \ - int i; \ - for (i = 0; i < siz / 4; i++) \ - { \ - SET_WORD(&dst32[i], GET_WORD(&src32[i])); \ - } \ - \ -} - -/* interleaved to non-interleaved - static void CASPER_MEMCPY_I2N(void *dst, const void *src, size_t siz) - */ -#define CASPER_MEMCPY_I2N(dst, src, siz) \ - \ -{ \ - uint32_t *dst32 = (uint32_t *)dst, *src32 = (uint32_t *)src; \ - int i; \ - for (i = 0; i < siz / 4; i++) \ - { \ - dst32[i] = GET_WORD(&src32[i]); \ - } \ - \ -} - -/* non-interleaved to interleaved - static void CASPER_MEMCPY_N2I(void *dst, const void *src, size_t siz) - */ -#define CASPER_MEMCPY_N2I(dst, src, siz) \ - \ -{ \ - volatile uint32_t *dst32 = (uint32_t *)dst, *src32 = (uint32_t *)src; \ - volatile int i; \ - for (i = 0; i < siz / 4; i++) \ - { \ - SET_WORD(&dst32[i], src32[i]); \ - } \ - \ -} -#else -#define GET_WORD(addr) (*((uint32_t *)(addr))) -#define GET_DWORD(addr) (*((uint64_t *)(addr))) -#define SET_WORD(addr, value) *((uint32_t *)(addr)) = ((uint32_t)(value)) -#define SET_DWORD(addr, value) *((uint64_t *)(addr)) = ((uint64_t)(value)) - -#define CASPER_MEMCPY_I2I(dst, src, siz) memcpy(dst, src, siz) -#define CASPER_MEMCPY_I2N(dst, src, siz) memcpy(dst, src, siz) -#define CASPER_MEMCPY_N2I(dst, src, siz) memcpy(dst, src, siz) -#endif - -#define WORK_BUFF_MUL4 (N_wordlen_max * 4 + 2) /* ! working buffer is 4xN_wordlen to allow in place math */ -#define N_bytelen (N_wordlen * 4) /* for memory copy and the like */ -#define N_dwordlen (N_wordlen / 2) - -#define PreZeroW(i, w_out) \ - for (i = 0; i < N_wordlen; i += 4) \ - { \ - SET_WORD(&w_out[i + 0], 0); \ - SET_WORD(&w_out[i + 1], 0); \ - SET_WORD(&w_out[i + 2], 0); \ - SET_WORD(&w_out[i + 3], 0); \ - } /* unrolled partly */ -#define PreZeroW2up(i, w_out) \ - for (i = N_wordlen; i <= N_wordlen * 2; i += 4) \ - { \ - SET_WORD(&w_out[i + 0], 0); \ - SET_WORD(&w_out[i + 1], 0); \ - SET_WORD(&w_out[i + 2], 0); \ - SET_WORD(&w_out[i + 3], 0); \ - } /* unrolled partly */ - -/* Macros for the ECC component in Casper */ - -/* CASPER memory layout for ECC */ -#define CASPER_NUM_LIMBS (NUM_LIMBS + 4) // number of limbs needed by CASPER is 2 double words longer - -#define CASPER_MEM ((uint32_t *)msg_ret) -#define CASPER_OFFSET CASPER_NUM_LIMBS // offset in the CASPER memory where we can start writing - -#define MOD_SCRATCH_START (CASPER_OFFSET) -#define MOD_SCRATCH_SIZE (1 * CASPER_NUM_LIMBS) - -#define INOUT_SCRATCH_START (MOD_SCRATCH_START + MOD_SCRATCH_SIZE) -#define INOUT_SCRATCH_SIZE ((3 * 3) * CASPER_NUM_LIMBS) - -#define ECC_SCRATCH_START (INOUT_SCRATCH_START + INOUT_SCRATCH_SIZE) -#define ECC_SCRATCH_SIZE (9 * CASPER_NUM_LIMBS) - -#define LUT_SCRATCH_START (ECC_SCRATCH_START + ECC_SCRATCH_SIZE) -#define LUT_SCRATCH_SIZE (48 * NUM_LIMBS + 3 * CASPER_NUM_LIMBS) - -/* Currently these macros work on 32-bit platforms */ - -#define add(c1, c0, a, b) \ - \ -do \ - { \ - uint32_t _t; \ - _t = a + b; \ - c1 = (_t < a); \ - c0 = _t; \ - \ -} \ - while (0) - -#define add_cout(carry, c, a, b) add(carry, c, a, b) - -#define add_cout_cin(carryout, c, a, b, carryin) \ - do \ - { \ - uint64_t _t = (uint64_t)a + b + carryin; \ - c = (uint32_t)_t; \ - carryout = (uint32_t)(_t >> 32); \ - } while (0) - -#define sub_borrowout(borrow, c, a, b) \ - do \ - { \ - uint32_t _b = (b > a); \ - c = a - b; \ - borrow = _b; \ - } while (0) - -#define sub_borrowin_borrowout(borrowout, c, a, b, borrowin) \ - do \ - { \ - uint32_t _t, _borrow1, _borrow2; \ - sub_borrowout(_borrow1, _t, a, b); \ - sub_borrowout(_borrow2, c, _t, borrowin); \ - borrowout = _borrow1 + _borrow2; \ - } while (0) - -#define sub_borrowout_1(borrow, c, a) \ - do \ - { \ - uint32_t _b = 0; \ - c = a - b; \ - borrow = _b; \ - } while (0) - -#define sub_borrowin_borrowout_1(borrowout, c, a, borrowin) \ - do \ - { \ - uint32_t _t, _borrow1, _borrow2; \ - sub_borrowout_1(_borrow1, _t, a); \ - sub_borrowout(_borrow2, c, _t, borrowin); \ - borrowout = _borrow1 + _borrow2; \ - } while (0) - -/* 32 x 32 --> 64-bit multiplication -* (c1,c0) = a * b -*/ -#define mul(c1, c0, a, b) \ - \ -do \ - { \ - uint64_t __m; \ - __m = (uint64_t)a * (uint64_t)b; \ - c0 = (uint32_t)__m; \ - c1 = (uint32_t)(__m >> (uint64_t)32); \ - \ -} \ - while (0) - -/* Multiply-and-accumulate -* (c1,c0) = a*b+c0 - */ -#define muladd(c1, c0, a, b) \ - \ -do \ - { \ - uint32_t __ma = c0; \ - mul(c1, c0, a, b); \ - c0 = c0 + __ma; \ - c1 = c1 + (c0 < __ma); \ - \ -} \ - while (0) - -/* Multiply-and-accumulate-accumulate -* (c1,c0) = a*b+c0+c1 -*/ -#define muladdadd(c1, c0, a, b) \ - \ -do \ - { \ - uint32_t __maa0 = c0, __maa1 = c1; \ - mul(c1, c0, a, b); \ - c0 = c0 + __maa0; \ - c1 = c1 + (c0 < __maa0); \ - c0 = c0 + __maa1; \ - c1 = c1 + (c0 < __maa1); \ - \ -} \ - while (0) - -#if CASPER_ECC_P256 - -/* Recoding length for the secure scalar multiplication: -* Use n=256 and w=4 --> compute ciel(384/3) = 86 + 1 digits -*/ -#define CASPER_RECODE_LENGTH 87 -#define invert(c, a) invert_mod_p256(c, a) -#define ONE NISTr256 - -/* Shift right by 1 <= c <= 31. z[] and x[] in system RAM, no interleaving macros used. */ -#define shiftrightSysram(z, x, c) \ - do \ - { \ - z[0] = (x[1] << (32 - (c))) | (x[0] >> (c)); \ - z[1] = (x[2] << (32 - (c))) | (x[1] >> (c)); \ - z[2] = (x[3] << (32 - (c))) | (x[2] >> (c)); \ - z[3] = (x[4] << (32 - (c))) | (x[3] >> (c)); \ - z[4] = (x[5] << (32 - (c))) | (x[4] >> (c)); \ - z[5] = (x[6] << (32 - (c))) | (x[5] >> (c)); \ - z[6] = (x[7] << (32 - (c))) | (x[6] >> (c)); \ - z[7] = (x[7] >> (c)); \ - } while (0) - -#elif CASPER_ECC_P384 - -/* Recoding length for the secure scalar multiplication: - * Use n=384 and w=4 --> compute ciel(384/3) = 128 + 1 digits - */ -#define CASPER_RECODE_LENGTH 129 -#define invert(c, a) invert_mod_p384(c, a) -#define ONE NISTr384 - -/* Shift right by 1 <= c <= 31. z[] and x[] in system RAM, no interleaving macros used. */ -#define shiftrightSysram(z, x, c) \ - do \ - { \ - z[0] = (x[1] << (32 - (c))) | (x[0] >> (c)); \ - z[1] = (x[2] << (32 - (c))) | (x[1] >> (c)); \ - z[2] = (x[3] << (32 - (c))) | (x[2] >> (c)); \ - z[3] = (x[4] << (32 - (c))) | (x[3] >> (c)); \ - z[4] = (x[5] << (32 - (c))) | (x[4] >> (c)); \ - z[5] = (x[6] << (32 - (c))) | (x[5] >> (c)); \ - z[6] = (x[7] << (32 - (c))) | (x[6] >> (c)); \ - z[7] = (x[8] << (32 - (c))) | (x[7] >> (c)); \ - z[8] = (x[9] << (32 - (c))) | (x[8] >> (c)); \ - z[9] = (x[10] << (32 - (c))) | (x[9] >> (c)); \ - z[10] = (x[11] << (32 - (c))) | (x[10] >> (c)); \ - z[11] = (x[11] >> (c)); \ - } while (0) - -#else -#error "Define proper NIST curve" -#endif - -#define multiply_casper(c, a, b) MultprecCiosMul_ct(c, a, b, &CASPER_MEM[MOD_SCRATCH_START], Np) -#define square_casper(c, a) multiply_casper(c, a, a) -#define sub_casper(c, a, b) CASPER_montsub(c, a, b, &CASPER_MEM[MOD_SCRATCH_START]) -#define add_casper(c, a, b) CASPER_montadd(c, a, b, &CASPER_MEM[MOD_SCRATCH_START]) -#define mul2_casper(c, a) add_casper(c, a, a) -#define half(c, a, b) CASPER_half(c, a, b) -#define copy(c, a) CASPER_MEMCPY(c, a, NUM_LIMBS * sizeof(uint32_t)) - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* The model for this algo is that it can be implemented for a fixed size RSA key */ -/* for max speed. If this is made into a variable (to allow varying size), then */ -/* it will be slower by a bit. */ -/* The file is compiled with N_bitlen passed in as number of bits of the RSA key */ -/* #define N_bitlen 2048 */ -static size_t N_wordlen = 0; /* ! number of words (e.g. 4096/32 is 128 words) */ - -static uint32_t s_casperRamBase = CASPER_RAM_BASE_NS; -static unsigned *msg_ret = (unsigned *)CASPER_RAM_BASE_NS; - -#if CASPER_ECC_P256 -/* NISTp-256 = 2^256-2^224+2^192+2^96-1 */ -static uint32_t NISTp256[NUM_LIMBS] = {0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, - 0x00000000, 0x00000000, 0x00000001, 0xffffffff}; - -/* The cardinality of the curve E(F_p) */ -static uint32_t NISTp256_q[NUM_LIMBS] = {0xfc632551, 0xf3b9cac2, 0xa7179e84, 0xbce6faad, - 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff}; - -/* R = 2^256 mod p, the value "1" in Montgomery form. */ -static uint32_t NISTr256[NUM_LIMBS] = {0x00000001, 0x00000000, 0x00000000, 0xffffffff, - 0xffffffff, 0xffffffff, 0xfffffffe, 0x00000000}; - -static uint32_t Np[2] = {1, 0}; -#endif /* CASPER_ECC_P256 */ - -#if CASPER_ECC_P384 -/* NISTp-384 = 2^384 - 2^128 - 2^96 + 2^32 - 1 */ -static uint32_t NISTp384[NUM_LIMBS] = {0xffffffff, 0x00000000, 0x00000000, 0xffffffff, 0xfffffffe, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}; - -/* The cardinality of the curve E(F_p) */ -static uint32_t NISTp384_q[NUM_LIMBS] = {0xccc52973, 0xecec196a, 0x48b0a77a, 0x581a0db2, 0xf4372ddf, 0xc7634d81, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}; - -/* R = 2^256 mod p, the value "1" in Montgomery form. */ -static uint32_t NISTr384[NUM_LIMBS] = {0x00000001, 0xffffffff, 0xffffffff, 0x00000000, 0x1, 0, 0, 0, 0, 0, 0, 0}; - -// -p^-1 mod 2^64 = 0x100000001 -static uint32_t Np[2] = {1, 1}; -#endif /* CASPER_ECC_P384 */ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/* Convert a projective point (X1 : Y1 : Z1) - * to the affine point (X3, Y3) = (X1/Z1^2,Y1/Z1^3) - * The memory of (X3, Y3) and (X1 : Y1 : Z1) should not overlap - */ -void Jac_toAffine(uint32_t *X3, uint32_t *Y3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1); - -/* Return 1 if (X1: Y1: Z1) is on the curve -* Y^2 = X^3 -3XZ^4 + bZ^6 -* and return 0 otherwise. -*/ -int Jac_oncurve(uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *b); - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2 : Y2 : Z2) - * where (X1: Y1: Z1) != (X2 : Y2 : Z2) - * (X3 : Y3: Z3) may be the same as one of the inputs. - */ -void Jac_addition(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *Z1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *Z2); - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2, Y2) - * where (X1: Y1: Z1) != (X2, Y2) - * (X3 : Y3: Z3) may not overlap with (X1: Y1: Z1). - * Source: 2004 Hankerson–Menezes–Vanstone, page 91. - */ -void Jac_add_affine( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *X2, uint32_t *Y2); - -/* Point doubling from: 2004 Hankerson–Menezes–Vanstone, page 91. - * Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X1 : Y1 : Z1) - * (X3 : Y3: Z3) may be the same as the input. - */ -void Jac_double(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1); - -/* Constant time elliptic curve scalar multiplication. - * Source: https://eprint.iacr.org/2014/130.pdf - * when using w = 4. - * Computes (X3 : Y3 : Z3) = k * (X1, Y1) \in E(F_p) - * p is the prime used to define the finite field F_p - * q is the (prime) order of the curve - */ -void Jac_scalar_multiplication( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *k, uint32_t *p, uint32_t *q); - -/* Compute the double scalar multiplication -* (X3 : Y3 : Z3) = k1 * (X1, Y1) + k2 * (X2, Y2) -* Using Shamir's trick and precomputing 16 points. -* This code is *not* constant time since this is used -* for verification only. -*/ -void double_scalar_multiplication(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *k1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *k2); - -#if CASPER_ECC_P384 -/* Compute inversion modulo NIST-p384 using Fermats little theorem. - * Using c = a^(p-2) = a^(-1) mod p. - * This computes the modular inversion if all arithmetic is "regular" - * modular arithmetic or computes automatically the Montgomery inverse - * if all arithmetic is Montgomery arithmetic. - */ -static void invert_mod_p384(uint32_t *c, uint32_t *a); -#endif /* CASPER_ECC_P384 */ - -#if CASPER_ECC_P256 -/* Modular inversion for NIST-P256 */ -static void invert_mod_p256(uint32_t *c, uint32_t *a); -#endif /* CASPER_ECC_P256 */ - -// A and C do not need to be in Casper memory -static void toMontgomery(uint32_t *C, uint32_t *A); - -static void CASPER_montsub(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod); -static void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod); - -/* Compute c = a/2 mod p where b is scratch space. */ -static void CASPER_half(uint32_t *c, uint32_t *a, uint32_t *b); - -static uint8_t int8abs(int8_t v); - -/* Constant time select c = a if m = 0 or -* c = b if m = 1 -* a, b, c are n words -*/ -static void casper_select(uint32_t *c, uint32_t *a, uint32_t *b, int m, int n); - -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n); - -#if 0 -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n(uint32_t *c, uint32_t *a, uint32_t *b, int n); - -/* Dumb n-limb subtraction of c=a-b, return borrow. */ -static uint32_t sub_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n); -#endif - -/* Dumb n-limb subtraction of c=a-b, return borrow. */ -static uint32_t sub_n(uint32_t *c, uint32_t *a, uint32_t *b, int n); - -static void MultprecCiosMul_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np); - -static void shiftright(uint32_t *z, uint32_t *x, int c); -static void shiftleft(uint32_t *z, uint32_t *x, int c); - -/******************************************************************************* - * Code - ******************************************************************************/ - -__STATIC_FORCEINLINE uint32_t CA_MK_OFF(const void *addr) -{ - return ((uint32_t)addr - s_casperRamBase); -} - -#if 1 -__STATIC_FORCEINLINE void Accel_done(void) -{ - register uint32_t status; - do - { - status = CASPER->STATUS; - } while (0 == (status & CASPER_STATUS_DONE_MASK)); -} - -__STATIC_FORCEINLINE void Accel_SetABCD_Addr(uint32_t ab, uint32_t cd) -{ - CASPER->CTRL0 = ab | (cd << 16); /* CDoffset << 16 | ABoffset */ -} - -__STATIC_FORCEINLINE void Accel_crypto_mul(uint32_t ctrl1) -{ - CASPER->CTRL1 = ctrl1; -} -#else -#include "intrinsics.h" -#define Accel_done() \ - { \ - register uint32_t status; \ - do \ - { \ - status = CASPER_Rd32b(CASPER_CP_STATUS); \ - } while (0 == (status & CASPER_STATUS_DONE_MASK)); \ - } -#if 0 -__STATIC_FORCEINLINE void Accel_done(void) -{ - register uint32_t status; - do - { - status = CASPER->STATUS; - } while (0 == (status & CASPER_STATUS_DONE_MASK)); -} -#endif -#define Accel_SetABCD_Addr(ab, cd) CASPER_Wr32b((uint32_t)ab | ((uint32_t)cd << 16), CASPER_CP_CTRL0); -#define Accel_crypto_mul(ctrl1) CASPER_Wr32b((uint32_t)ctrl1, CASPER_CP_CTRL1); -#endif - -__STATIC_FORCEINLINE uint32_t Accel_IterOpcodeResaddr(uint32_t iter, uint32_t opcode, uint32_t resAddr) -{ - return CASPER_CTRL1_ITER(iter) | CASPER_CTRL1_MODE(opcode) | (resAddr << 16); -} - -void CASPER_MEMCPY(void *dst, const void *src, size_t siz) -{ - bool bdst = ((((uint32_t)dst) | 0x10000000u) >= (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && - (((uint32_t)dst) | 0x10000000u) < (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); - - bool bsrc = ((((uint32_t)src) | 0x10000000u) >= (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && - (((uint32_t)src) | 0x10000000u) < (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); - - if (bdst && bsrc) - { - CASPER_MEMCPY_I2I(dst, src, siz); - } - else if (bdst && !bsrc) - { - CASPER_MEMCPY_N2I(dst, src, siz); - } - else if (!bdst && bsrc) - { - CASPER_MEMCPY_I2N(dst, src, siz); - } - else - { - memcpy(dst, src, siz); - } -} - -/* Constant time select c = a if m = 0 or - * c = b if m = 1 - * a, b, c are n words - */ -static void casper_select(uint32_t *c, uint32_t *a, uint32_t *b, int m, int n) -{ - uint32_t m1 = 0 - m, m2 = ~m1; - int i; - - for (i = 0; i < n; i++) - { - SET_WORD(&c[i], (GET_WORD(&a[i]) & m2) | (GET_WORD(&b[i]) & m1)); - } -} - -/* Compute R`, which is R mod N. This is done using subtraction */ -/* R has 1 in N_wordlen, but we do not fill it in since borrowed. */ -/* Exp-pubkey only used to optimize for exp=3 */ -void MultprecMontCalcRp(unsigned Rp[], const unsigned exp_pubkey, const unsigned Nmod[]) -{ - int i; - - /* R is 2^n where n is 1 bit longer than Nmod, so 1 followed by 32 or 64 0 words for example */ - /* Note that Nmod's upper most bit has to be 1 by definition, so one subtract is enough. We */ - /* do not set the 1 since it is "borrowed" so no point */ - PreZeroW(i, Rp); - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpSub64, CA_MK_OFF(Rp))); - Accel_done(); - /* final borrow cannot happen since we know we started with a larger number */ -} - -/* MultprecMultiply - multiple w=u*v (per Knuth) */ -/* w_out is 2x the size of u and v */ -void MultprecMultiply(unsigned w_out[], const unsigned u[], const unsigned v[]) -{ - int i, j; - - /* Knuth 4.3.1 - Algorithm M */ - /* Compute w = u * v */ - /* u and v are N bits long in 32 bit word form */ - /* w is 2*N bits long in 32 bit word form */ - /* Note: We just multiply in place */ - - /* Step 1. Fill w[t-1:0] with 0s, the upper half will be written as we go */ - PreZeroW(i, w_out); - - /* We do 1st pass NOSUM so we do not have to 0 output */ - Accel_SetABCD_Addr(CA_MK_OFF(&v[0]), CA_MK_OFF(u)); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2 - 1, kCASPER_OpMul6464NoSum, CA_MK_OFF(&w_out[0]))); - Accel_done(); - /* Step 2. iterate over N words of v using j */ - for (j = 2; j < N_wordlen; j += 2) - { - /* Step 2b. Check for 0 on v word - skip if so since we 0ed already */ - /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ - if (GET_WORD(&v[j]) || GET_WORD(&v[j + 1])) - { - Accel_SetABCD_Addr(CA_MK_OFF(&v[j]), CA_MK_OFF(u)); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2 - 1, kCASPER_OpMul6464Sum, CA_MK_OFF(&w_out[j]))); - Accel_done(); - } - } -} - -/* MultprecModulo performs divide to get remainer as needed for RSA */ -/* This performs (q,r) = u/v, but we do not keep q */ -/* r_out is module (remainder) and is 2*N */ -/* u is in r_out (1st N) at start (passed in) */ -/* v is N long */ -void MultprecModulo(unsigned r_out[], const unsigned v[], int top) -{ - uint64_t u64; /* use 64 bit math mixed with 32 bit */ - unsigned u32; /* allows us to work on U in 32 bit */ - unsigned u_n, ul16, uh16, *u_shft; /* u_shft is because r_out is u initially */ - unsigned vl16, vh16, v_Nm1; - unsigned q_hat, r_hat, q_over; - unsigned borrow, carry; - int i, j, tmp; - - /* Knuth 4.3.1 - Algorithm D */ - /* Compute q = u / v giving remainder r = u mod v */ - /* -- we only want r, so we build qhat but do not store the Qs */ - /* v is N long, with u,q,r 2N long because u is slowly replavced by r. */ - /* We normalize/unnormlize per Knuth in the buffer (not copied) */ - - /* Step 1. Normalize value so MSb is in v[n-1]. Remember that v is */ - /* the public key - to call it a 2048 bit number, they cannot have 0 */ - /* in the MSb (or it would be less than 2048 bits) and so we know we */ - /* are normalized already. Therefore, u is effectively shifted already. */ - /* For u, we have it in r_out. u[n] holds any overflow */ - /* Since divide on CM3/4 is 32/32=32, we break into 16 bit halves, but */ - /* multiply can be 32x32=64. */ - u_n = 0; - u_shft = r_out; /* u (shifted) is in r_out */ - - v_Nm1 = GET_WORD(&v[N_wordlen - 1]); /* MSw of public key */ - vl16 = v_Nm1 & 0xFFFF; /* lower 16 */ - vh16 = v_Nm1 >> 16; /* upper 16 */ - /* Step 2. Iterate j from m-n down to 0 (M selected per Knuth as 2*N) */ - for (j = top; j >= 0; j--) - { - /* Step 3. estimate q_hat as (U[j+n]*B + U[j+n-1]) / V[n-1] */ - /* Note: using subset of Knuth algo since v is 1/2 len of u (which is */ - /* from multiply or x^2 leading into this). */ - u32 = u_n; /* pickup u4u3u2, knowing u4 is 0 */ - u64 = ((uint64_t)u_n << 32) | GET_WORD(&u_shft[j + N_wordlen - 1]); - ul16 = u64 & 0xFFFF; /* lower 16 */ - uh16 = (u64 >> 16) & 0xFFFF; /* upper 16 */ - - /* we see if even possible (u large enough relative to v) */ - if ((u32 - v_Nm1) <= u32) - { - u32 -= v_Nm1; - q_over = 1; /* overflow from the sub */ - } - else - q_over = 0; - - /* q_hat = u32 / vh16 -- is the upper partial value */ - /* estimate; if too much, then back down by 1 or 2 */ - q_hat = u32 / vh16; - r_hat = u32 - (q_hat * vh16); - /* see if Q is more than 16 bits or remainder is too large (over div) */ - if ((q_hat == 0x10000) || ((q_hat * vl16) > ((r_hat << 16) | uh16))) - { - /* too much - undo a division */ - q_hat--; - r_hat += vh16; - /* check if still too much */ - if ((r_hat < 0x10000) && ((q_hat * vl16) > ((r_hat << 16) | uh16))) - q_hat--; /* yes, so undo a 2nd */ - } - - /* compose u3u2uh16, then sub q_hat*v if OK */ - u64 = (((uint64_t)u32 << 16) | uh16) - ((uint64_t)q_hat * v_Nm1); - if (u64 >> 48) - { - /* no, so add v back */ - u32 = (unsigned)(u64 + v_Nm1); - q_hat--; - } - else - u32 = (unsigned)u64; - - tmp = q_hat << 16; /* quotient upper part */ - - /* divide lower part: q = u2uh16ul16 / v. */ - /* estimate and add back if over divdied */ - q_hat = u32 / vh16; - r_hat = u32 - (q_hat * vh16); - if ((q_hat == 0x10000) || ((q_hat * vl16) > ((r_hat << 16) | ul16))) - { - /* too much - undo a division */ - q_hat--; - r_hat += vh16; - /* check if still too much */ - if ((r_hat < 0x10000) && ((q_hat * vl16) > ((r_hat << 16) | ul16))) - q_hat--; /* yes, so undo a 2nd */ - } - - /* compose u2uh16ul16, then sub q_hat*v if OK */ - u64 = (((uint64_t)u32 << 16) | ul16) - ((uint64_t)q_hat * v_Nm1); - if (u64 >> 48) - { - /* no, so add v back */ - r_hat = (unsigned)(u64 + v_Nm1); - q_hat--; - } - else - r_hat = (unsigned)u64; - - q_hat |= tmp; /* other half of the quotient */ - while (q_over || - ((uint64_t)q_hat * GET_WORD(&v[N_wordlen - 2])) > - ((1LL << 32) * r_hat) + (uint64_t)GET_WORD(&u_shft[j + N_wordlen - 2])) - { /* if Qhat>b, then reduce to b-1, then adjust up Rhat */ - q_hat--; - r_hat += v_Nm1; - if (r_hat < v_Nm1) - break; /* no overflow */ - /* else repeat since Rhat >= b */ - } - - /* Step 4. Multiply and subtract. We know the amount, */ - /* so we do the schoolboy math. Have to do on */ - /* the large value. */ - if (q_hat) - { - borrow = 0; - for (i = 0; i < N_wordlen; i++) - { - u64 = (uint64_t)q_hat * GET_WORD(&v[i]) + borrow; - borrow = (unsigned)(u64 >> 32); - if (GET_WORD(&u_shft[i + j]) < (unsigned)u64) - borrow++; /* carry the overflow */ - SET_WORD(&u_shft[i + j], GET_WORD(&u_shft[i + j]) - (unsigned)u64); - } - u_n -= borrow; /* overflow from shift left does not fit otherwise */ - } - - /* Store 5. (update Q - we don't), and add back V to remainder if we over-subtracted */ - /* That restores remainder to correct (we could only be off by 1) */ - /* This should happen very rarely. */ - if (u_n) - { - carry = 0; - for (i = 0; i < N_wordlen; i++) - { - SET_WORD(&u_shft[i + j], GET_WORD(&u_shft[i + j]) + carry); - carry = (GET_WORD(&u_shft[i + j]) < carry) ? 1 : 0; - SET_WORD(&u_shft[i + j], GET_WORD(&u_shft[i + j]) + GET_WORD(&v[i])); - if (GET_WORD(&u_shft[i + j]) < GET_WORD(&v[i])) - carry++; - } - } - u_n = GET_WORD(&u_shft[j + N_wordlen - 1]); /* hold upper part of u to catch overflow (to borrow from) */ - } - /* low N bits of r are valid as remainder */ -} - -/* We convert X into a Mont form number. Note length of arrays: */ -/* x is N_wordlen, Nmod is N_wordlen */ -/* Rp is N_wordlen (it is R` which is R mod N) */ -/* Xmont_out is N_wordlen*2+1 */ -void MultprecMontPrepareX(unsigned Xmont_out[], const unsigned x[], const unsigned Rp[], const unsigned Nmod[]) -{ - MultprecMultiply(Xmont_out, x, Rp); - MultprecModulo(Xmont_out, Nmod, N_wordlen); -} - -void MultprecGenNp64(const unsigned *Nmod, unsigned *np64_ret) /* only pass the low order double word */ -{ - uint64_t nprime, Nmod_0; - Nmod_0 = GET_WORD(&Nmod[0]) | ((uint64_t)GET_WORD(&Nmod[1]) << 32); - -#define COMP_NPN_1 ((2 - Nmod_0 * nprime) * nprime) /* computes N`*N0=1 mod 2^P where P is the partial built up */ - nprime = (((2 + Nmod_0) & 4) << 1) + Nmod_0; /* mod 2^4 */ - nprime = COMP_NPN_1; - nprime = COMP_NPN_1; - nprime = COMP_NPN_1; - nprime = COMP_NPN_1; - /* 8 multiplies of uint64_t */ - *((uint64_t *)np64_ret) = (~0LL - nprime) + 1LL; -} - -/* CIOS Multiply. This is the Coarse Integrated form where the values are */ -/* multiplied and reduced for each step of "i". This uses less memory and */ -/* is faster as a result. Note that this is used to square as well as mul, */ -/* so not as fast as pure squaring could be. */ -void MultprecCiosMul( - unsigned w_out[], const unsigned a[], const unsigned b[], const unsigned Nmod[], const unsigned *Np) -{ - int i, j; - uint64_t *m64 = (uint64_t *)&msg_ret[kCASPER_RamOffset_M64]; - uint64_t Np64; - uint64_t carry; - uint64_t *a64, *b64, *w64, *N64; - - Np64 = *(uint64_t *)Np; - - a64 = (uint64_t *)a; - b64 = (uint64_t *)b; - w64 = (uint64_t *)w_out; - N64 = (uint64_t *)Nmod; - - if (a) - { /* if !a, we are reducing only */ - PreZeroW(i, w_out); - } - SET_DWORD(&w64[N_dwordlen], 0); - SET_DWORD(&w64[N_dwordlen + 1], 0); - /* with accelerator */ - - /* loop i and then reduce after each j round */ - for (i = 0; i < N_dwordlen; i++) - { - /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ - /* push-pull: we do a*b and then separately m*n (reduce) */ - if (a) - { /* if mul&reduce vs. reduce only */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(&b64[i]), CA_MK_OFF(a64)); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); - Accel_done(); - /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ - /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ - /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ - /* w64[N_dwordlen+1] = g_carry; */ - carry = (GET_DWORD(&w64[N_dwordlen]) < carry); - SET_DWORD(&w64[N_dwordlen + 1], carry); - } - SET_DWORD(&m64[0], GET_DWORD(&w64[0]) * Np64); /* prime for 1st; modulo a double-word */ - - /* we are reducing, so the 1st [0th] 64 bit value product is tossed, but we */ - /* need its carry. We let the accel do this separately - really need a mode to */ - /* do this "reduce" since it is natural */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(m64), CA_MK_OFF(&N64[0])); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); - Accel_done(); - carry = (GET_DWORD(&w64[N_dwordlen]) < carry); - - Accel_SetABCD_Addr(CA_MK_OFF(&w64[1]), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); - - Accel_done(); - SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1]) + carry)); - } - - /* now check if need to subtract Nmod */ - if (GET_WORD(&w_out[N_wordlen])) - j = 1; /* we have to subtract for sure if carry up */ - else - { - j = 0; - for (i = N_wordlen - 1; i >= 0; i--) - if (GET_WORD(&w_out[i]) != GET_WORD(&Nmod[i])) - { - j = GET_WORD(&w_out[i]) > GET_WORD(&Nmod[i]); /* if larger sub */ - break; /* we would remove the break if worrying about side channel */ - } - } - if (!j) - return; /* Is smaller than Nmod, so done. */ - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpSub64, CA_MK_OFF(w_out))); - Accel_done(); - /* last borrow is OK since we know it could only be <2N and */ -} - -/* RSA_MontSignatureToPlaintextFast: */ -/* MsgRet[] = Message return buffer - must be large enough to hold input and output (4*N+2) */ -/* exp_pubkey = the "e" that the value is raised to. Usually 3 or 0x10001. */ -/* signature = N bitpos len long "message" to process in Montgomery form - so saving conversion (divide) */ -/* pubkey = N bitpos len long public key to process signature with */ -/* returns: 0 */ -/* */ -/* Algo: compute M = signaturen^e mod public_key */ -/* where M is original plaintext, signature is signed value */ -/* note: e is usually either 0x3 or 0x10001 */ -int RSA_MontSignatureToPlaintextFast(const unsigned mont_signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]) -{ - int bidx = 0; - int bitpos; - unsigned np64[2]; - - /* MsgRet working area: */ - /* 0..N = RESULT, starting with S` */ - /* N..N*2 = S` and then working BASE during math. */ - /* N*2..N*4+2 = temp working area for Mont mul */ - - /* 1. Copy sig into MsgRet so we have one working result buffer */ - CASPER_MEMCPY_I2I(&MsgRet[kCASPER_RamOffset_Result], mont_signature, N_bytelen); - MultprecGenNp64(pubkey, np64); /* Generate N` from LSW of N (LSW being lowest 64b word) */ - bitpos = 31 - __CLZ(exp_pubkey); /* count of bits after the left most 1 */ - while (--bitpos >= 0) - { - /* This operates on: */ - /* result = 1; */ - /* base = signature */ - /* loop while exponent bits from MSb to LSb */ - /* if (exp bit is 1) */ - /* result = result * base */ - /* base = base^2 */ - /* Because the MSb of exp is always 1 by definition, we can invert this a bit: */ - /* base = signature` */ - /* result = base; equivalent to result = 1*base from 1st pass, but now square is needed 1st */ - /* loop while exponent bits from MSb-1 to LSb */ - /* base = base^2 */ - /* if (exp bit is 1) */ - /* result = result * base */ - /* This ends up doing the same thing but skips two wasteful steps of multiplying by 1 and */ - /* a final squaring never used. */ - /* */ - /* Next we have the problem that CIOS mul needs a separate dest buffer. So, we bounce */ - /* base between base and temp, and likewise for result. */ - MultprecCiosMul(&MsgRet[bidx ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], - &MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], - &MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], pubkey, np64); - if (exp_pubkey & (1 << bitpos)) /* where e is 1 */ - { - /* result has result, so we need to work into other temp area */ - MultprecCiosMul(&MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], - &MsgRet[kCASPER_RamOffset_Result], - &MsgRet[bidx ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], pubkey, np64); - /* we have to copy back to result */ - - // CASPER_MEMCPY_I2I(&MsgRet[kCASPER_RamOffset_Result], - // &MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], N_bytelen); - } - else - bidx = ~bidx; - } - - CASPER_MEMCPY_I2I(&MsgRet[kCASPER_RamOffset_Result], - &MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], N_bytelen); - - /* final step is one more reduction to get back to normal form (ie. divide R out) */ - MultprecCiosMul(&MsgRet[kCASPER_RamOffset_Result], NULL, NULL, pubkey, np64); - return (0); /* always 0 */ -} - -/* RSA_SignatureToPlaintextFast: */ -/* MsgRet[] = Message return buffer - must be large enough to hold input and output (4*N+2) */ -/* exp_pubkey = the "e" that the value is raised to. Usually 3 or 0x10001. */ -/* signature = N bitpos len long "message" to process in normal form - so converted to Mont form */ -/* pubkey = N bitpos len long public key to process signature with */ -/* returns: 0 */ -/* */ -/* Algo: compute M = signaturen^e mod public_key */ -/* where M is original plaintext, signature is signed value */ -/* note: e is usually either 0x3 or 0x10001 */ -int RSA_SignatureToPlaintextFast(const unsigned signature[N_wordlen_max], - const unsigned exp_pubkey, - const unsigned pubkey[N_wordlen_max], - unsigned MsgRet[WORK_BUFF_MUL4]) -{ - /* MsgRet working area: */ - /* 0..N = RESULT, starting with S`; it is used for R` just during creation of S` */ - /* N..N*2 = S` and then working BASE during math. Note overflow beyond N*2 when making S` */ - /* N*2..N*4+2 = temp working area for Mont mul */ - - MultprecMontCalcRp(&MsgRet[kCASPER_RamOffset_Result], exp_pubkey, pubkey); /* calculate R` (=R mod N) */ - MultprecMontPrepareX(&MsgRet[kCASPER_RamOffset_Base], signature, &MsgRet[kCASPER_RamOffset_Result], - pubkey); /* X*R1` mod N */ - return (RSA_MontSignatureToPlaintextFast(&MsgRet[kCASPER_RamOffset_Base], exp_pubkey, pubkey, MsgRet)); -} - -/*! - * brief Performs modular exponentiation - (A^E) mod N. - * - * This function performs modular exponentiation. - * - * param base CASPER base address - * param signature first addend (in little endian format) - * param pubN modulus (in little endian format) - * param wordLen Size of pubN in bytes - * param pubE exponent - * param[out] plaintext Output array to store result of operation (in little endian format) - */ -void CASPER_ModExp( - CASPER_Type *base, const uint8_t *signature, const uint8_t *pubN, size_t wordLen, uint32_t pubE, uint8_t *plaintext) -{ -#define PK_LOC &msg_ret[kCASPER_RamOffset_Modulus] -#define SIG_LOC &msg_ret[kCASPER_RamOffset_Modulus + N_wordlen_max] - - N_wordlen = wordLen; /* set global variable for key length - used by RSA_SignatureToPlaintextFast() */ - CASPER_MEMCPY_N2I(PK_LOC, pubN, N_bytelen); - CASPER_MEMCPY_N2I(SIG_LOC, signature, N_bytelen); - RSA_SignatureToPlaintextFast((const unsigned *)(SIG_LOC), pubE, (const unsigned *)(PK_LOC), msg_ret); - - CASPER_MEMCPY_I2N(plaintext, msg_ret, N_bytelen); -} - -/*! - * brief Enables clock and disables reset for CASPER peripheral. - * - * Enable clock and disable reset for CASPER. - * - * param base CASPER base address - */ -void CASPER_Init(CASPER_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Casper); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - RESET_PeripheralReset(kCASPER_RST_SHIFT_RSTn); - /* If Casper init is called with secure address, use secure addres also for accessing Casper RAM. */ - s_casperRamBase = CASPER_RAM_BASE_NS | ((uint32_t)base & 0x10000000u); - msg_ret = (unsigned *)s_casperRamBase; -} - -/*! - * brief Disables clock for CASPER peripheral. - * - * Disable clock and enable reset. - * - * param base CASPER base address - */ -void CASPER_Deinit(CASPER_Type *base) -{ - RESET_SetPeripheralReset(kCASPER_RST_SHIFT_RSTn); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Casper); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/* New ECC code which uses Casper. */ - -/* Set the prime modulus mod in Casper memory. - */ -void CASPER_ecc_init(void) -{ -#if CASPER_ECC_P256 - N_wordlen = 256 / 32; - uint32_t *mod = NISTp256; -#elif CASPER_ECC_P384 - N_wordlen = 384 / 32; - uint32_t *mod = NISTp384; -#endif - CASPER_MEMCPY(&CASPER_MEM[MOD_SCRATCH_START], mod, NUM_LIMBS * sizeof(uint32_t)); - uint8_t a[(CASPER_NUM_LIMBS - NUM_LIMBS) * sizeof(uint32_t)] = {0}; - CASPER_MEMCPY(&CASPER_MEM[MOD_SCRATCH_START + NUM_LIMBS], a, (CASPER_NUM_LIMBS - NUM_LIMBS) * sizeof(uint32_t)); -} - -void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2) -{ - uint32_t a[NUM_LIMBS]; - uint32_t b[NUM_LIMBS]; - int c = 0; - CASPER_MEMCPY(a, op1, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(b, op2, NUM_LIMBS * sizeof(uint32_t)); - - do - { - int _i; - c = a[0] ^ b[0]; - for (_i = 1; _i < NUM_LIMBS; _i++) - { - c |= (a[_i] ^ b[_i]); - } - } while (0); - - *res = c; -} - -void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1) -{ - uint32_t a[NUM_LIMBS]; - int c = 0; - CASPER_MEMCPY(a, op1, NUM_LIMBS * sizeof(uint32_t)); - - do - { - int _i; - c = a[0]; - for (_i = 1; _i < NUM_LIMBS; _i++) - { - c |= a[_i]; - } - } while (0); - - *res = c; -} - -#if CASPER_ECC_P256 -void CASPER_ECC_SECP256R1_Mul( - CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]) -{ - uint32_t X1[8] = {0}; - uint32_t Y1[8] = {0}; - toMontgomery(X1, X); - toMontgomery(Y1, Y); - - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], X1, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], Y1, NUM_LIMBS * sizeof(uint32_t)); - - Jac_scalar_multiplication(&CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 7 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 8 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], scalar, NISTp256, NISTp256_q); - - Jac_toAffine(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 7 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 8 * CASPER_NUM_LIMBS]); - - /* Montgomery to Normal */ - /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ - uint32_t one[CASPER_NUM_LIMBS] = {0x0}; - one[0] = 0x1u; - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], one, CASPER_NUM_LIMBS * sizeof(uint32_t)); - multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); - multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); - - /* copy out to result */ - CASPER_MEMCPY(resX, &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(resY, &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], NUM_LIMBS * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base, - uint32_t resX[8], - uint32_t resY[8], - uint32_t X1[8], - uint32_t Y1[8], - uint32_t scalar1[8], - uint32_t X2[8], - uint32_t Y2[8], - uint32_t scalar2[8]) -{ - uint32_t zeroes[CASPER_NUM_LIMBS] = {0}; - - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], X1, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], Y1, NUM_LIMBS * sizeof(uint32_t)); - - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], X2, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], Y2, NUM_LIMBS * sizeof(uint32_t)); - - toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); - toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS]); - toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS]); - toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS]); - - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], zeroes, CASPER_NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], zeroes, CASPER_NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], zeroes, CASPER_NUM_LIMBS * sizeof(uint32_t)); - double_scalar_multiplication(&CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], scalar1, - &CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], scalar2); - - Jac_toAffine(&CASPER_MEM[LUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[LUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS]); - - uint32_t one[CASPER_NUM_LIMBS] = {0x0}; - one[0] = 0x1u; - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], one, CASPER_NUM_LIMBS * sizeof(uint32_t)); - multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], - &CASPER_MEM[LUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); - multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], - &CASPER_MEM[LUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); - - CASPER_MEMCPY(resX, (&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS]), NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(resY, (&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS]), NUM_LIMBS * sizeof(uint32_t)); -} -#endif /* CASPER_ECC_P256 */ - -#if CASPER_ECC_P384 -void CASPER_ECC_SECP384R1_Mul( - CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]) -{ - uint32_t X1[12] = {0}; - uint32_t Y1[12] = {0}; - toMontgomery(X1, X); - toMontgomery(Y1, Y); - - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], X1, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], Y1, NUM_LIMBS * sizeof(uint32_t)); - - Jac_scalar_multiplication(&CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 7 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 8 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], scalar, NISTp384, NISTp384_q); - - Jac_toAffine(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 7 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 8 * CASPER_NUM_LIMBS]); - - /* Montgomery to Normal */ - /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ - uint32_t one[12] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], one, NUM_LIMBS * sizeof(uint32_t)); - multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); - multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); - - /* copy out to result */ - CASPER_MEMCPY(resX, &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(resY, &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], NUM_LIMBS * sizeof(uint32_t)); -} - -void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, - uint32_t resX[12], - uint32_t resY[12], - uint32_t X1[12], - uint32_t Y1[12], - uint32_t scalar1[12], - uint32_t X2[12], - uint32_t Y2[12], - uint32_t scalar2[12]) -{ - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], X1, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], Y1, NUM_LIMBS * sizeof(uint32_t)); - - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], X2, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], Y2, NUM_LIMBS * sizeof(uint32_t)); - - toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); - toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS]); - toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS]); - toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS]); - - double_scalar_multiplication(&CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], scalar1, - &CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], scalar2); - - Jac_toAffine(&CASPER_MEM[LUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[LUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS]); - - uint32_t one[12] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], one, NUM_LIMBS * sizeof(uint32_t)); - multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], - &CASPER_MEM[LUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); - multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], - &CASPER_MEM[LUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); - - CASPER_MEMCPY(resX, (&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS]), NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(resY, (&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS]), NUM_LIMBS * sizeof(uint32_t)); -} -#endif /* CASPER_ECC_P384 */ - -// CIOS Multiply. This is the Coarse Integrated form where the values are -// multiplied and reduced for each step of "i". This uses less memory and -// is faster as a result. Note that this is used to square as well as mul, -// so not as fast as pure squaring could be. -static void MultprecCiosMul_ct( - uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np) -{ - int i; - uint64_t *m64 = (uint64_t *)&msg_ret[kCASPER_RamOffset_M64]; - uint64_t Np64; - uint64_t carry; - uint64_t *a64, *b64, *w64, *N64; - uint32_t *T1 = &CASPER_MEM[0], borrow; - - Np64 = *(uint64_t *)Np; - - a64 = (uint64_t *)a; - b64 = (uint64_t *)b; - w64 = (uint64_t *)w_out; - N64 = (uint64_t *)Nmod; - - if (a) - { /* if !a, we are reducing only */ - PreZeroW(i, w_out); - } - SET_DWORD(&w64[N_dwordlen], 0); - SET_DWORD(&w64[N_dwordlen + 1], 0); - /* with accelerator */ - - /* loop i and then reduce after each j round */ - for (i = 0; i < N_dwordlen; i++) - { - /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ - /* push-pull: we do a*b and then separately m*n (reduce) */ - if (a) - { /* if mul&reduce vs. reduce only */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(&b64[i]), CA_MK_OFF(a64)); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); - Accel_done(); - /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ - /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ - /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ - /* w64[N_dwordlen+1] = g_carry; */ - carry = (GET_DWORD(&w64[N_dwordlen]) < carry); - SET_DWORD(&w64[N_dwordlen + 1], carry); - } - SET_DWORD(&m64[0], GET_DWORD(&w64[0]) * Np64); /* prime for 1st; modulo a double-word */ - - /* we are reducing, so the 1st [0th] 64 bit value product is tossed, but we */ - /* need its carry. We let the accel do this separately - really need a mode to */ - /* do this "reduce" since it is natural */ - carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(m64), CA_MK_OFF(&N64[0])); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); - Accel_done(); - carry = (GET_DWORD(&w64[N_dwordlen]) < carry); - - Accel_SetABCD_Addr(CA_MK_OFF(&w64[1]), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); - - Accel_done(); - SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1]) + carry)); - } - - /* now check if need to subtract Nmod */ - CASPER_MEMCPY_I2I(T1, w_out, (NUM_LIMBS + 1) * sizeof(uint32_t)); - - /* Compute w = w - N */ - Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen, kCASPER_OpSub64, CA_MK_OFF(w_out))); - Accel_done(); - - // if w_out > T1 then there was a borrow - borrow = (GET_WORD(&((uint32_t *)w_out)[NUM_LIMBS]) > GET_WORD(&T1[NUM_LIMBS])); - - SET_WORD(&w_out[NUM_LIMBS + 1], 0); - SET_WORD(&w_out[NUM_LIMBS], 0); - casper_select(w_out, w_out, T1, borrow, NUM_LIMBS); -} - -/* Compute C = A - B % mod -* Assumes all operand have two extra limbs to store carry. -*/ -void CASPER_montsub(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) -{ - uint64_t *b64, *c64, *m64, *tmp; - int borrow; - - b64 = (uint64_t *)B; - c64 = (uint64_t *)C; - m64 = (uint64_t *)mod; - - tmp = (uint64_t *)&CASPER_MEM[0]; - - CASPER_MEMCPY(tmp, A, NUM_LIMBS * sizeof(uint32_t)); - // uint32_t temp32 = GET_WORD(&tmp[NUM_LIMBS - 1]); - - /* Compute tmp = A - B. */ - Accel_SetABCD_Addr(CA_MK_OFF(b64), 0); - - Accel_crypto_mul(Accel_IterOpcodeResaddr(NUM_LIMBS / 2 - 1, kCASPER_OpSub64, CA_MK_OFF(tmp))); - Accel_done(); - - // borrow = (GET_WORD(&((uint32_t*)tmp)[NUM_LIMBS - 1]) > temp32); - borrow = ((GET_WORD(&((uint32_t *)tmp)[NUM_LIMBS - 1])) > GET_WORD(&A[NUM_LIMBS - 1])); - CASPER_MEMCPY(c64, tmp, NUM_LIMBS * sizeof(uint32_t)); - - /* Compute C = Mod + tmp */ - Accel_SetABCD_Addr(CA_MK_OFF(m64), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(NUM_LIMBS / 2 - 1, kCASPER_OpAdd64, CA_MK_OFF(c64))); - Accel_done(); - - casper_select(C, (uint32_t *)tmp, C, borrow, NUM_LIMBS); -} - -/* Compute C = A + B % mod -* Assumes all operand have two extra limbs to store carry. -*/ -void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) -{ - uint64_t *b64, *c64, *m64, *tmp; - int borrow; - - b64 = (uint64_t *)B; - c64 = (uint64_t *)C; - m64 = (uint64_t *)mod; - - tmp = (uint64_t *)&CASPER_MEM[0]; - - CASPER_MEMCPY(tmp, A, NUM_LIMBS * sizeof(uint32_t)); - SET_DWORD(&tmp[NUM_LIMBS / 2], 0); - SET_DWORD(&b64[NUM_LIMBS / 2], 0); - SET_DWORD(&m64[NUM_LIMBS / 2], 0); - - /* Compute tmp = A + B using one additonal double-length limb. */ - Accel_SetABCD_Addr(CA_MK_OFF(b64), 0); - - Accel_crypto_mul(Accel_IterOpcodeResaddr(NUM_LIMBS / 2, kCASPER_OpAdd64, CA_MK_OFF(tmp))); - Accel_done(); - - CASPER_MEMCPY(c64, tmp, (NUM_LIMBS + 2) * sizeof(uint32_t)); - - /* Compute C = Mod - tmp */ - Accel_SetABCD_Addr(CA_MK_OFF(m64), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(NUM_LIMBS / 2, kCASPER_OpSub64, CA_MK_OFF(c64))); - Accel_done(); - - // borrow = g_carry; - borrow = (GET_WORD(&C[NUM_LIMBS]) > GET_WORD(&(((uint32_t *)tmp)[NUM_LIMBS]))); - casper_select(C, C, (uint32_t *)tmp, borrow, NUM_LIMBS); -} - -/* Compute c = a/2 mod p where b is scratch space. */ -void CASPER_half(uint32_t *c, uint32_t *a, uint32_t *b) -{ - shiftright(b, a, 1); /* Compute a/2 and (a+p)/2 */ - - /* Compute tmp = a + p using one additonal double-length limb. */ - CASPER_MEMCPY(c, a, NUM_LIMBS * sizeof(uint32_t)); - SET_WORD(&c[NUM_LIMBS], 0); - SET_WORD(&c[NUM_LIMBS + 1], 0); - - Accel_SetABCD_Addr(CA_MK_OFF(((uint64_t *)&CASPER_MEM[MOD_SCRATCH_START])), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(NUM_LIMBS / 2, kCASPER_OpAdd64, CA_MK_OFF(((uint64_t *)c)))); - Accel_done(); - - shiftright(c, c, 1); - SET_WORD(&c[NUM_LIMBS - 1], GET_WORD(&c[NUM_LIMBS - 1]) | (GET_WORD(&c[NUM_LIMBS]) << 31)); - SET_WORD(&c[NUM_LIMBS], 0); - casper_select(c, b, c, (GET_WORD(&a[0]) & 1), NUM_LIMBS); -} - -static uint32_t casper_get_word(uint32_t *addr) -{ - return GET_WORD(addr); -} - -#if CASPER_ECC_P256 -/* Shift right by 1 <= c <= 31. */ -static void shiftright(uint32_t *z, uint32_t *x, int c) -{ - do - { - SET_WORD((&z[0]), (GET_WORD(&x[1]) << (32 - (c))) | (GET_WORD(&x[0]) >> (c))); - SET_WORD((&z[1]), (GET_WORD(&x[2]) << (32 - (c))) | (GET_WORD(&x[1]) >> (c))); - SET_WORD((&z[2]), (GET_WORD(&x[3]) << (32 - (c))) | (GET_WORD(&x[2]) >> (c))); - SET_WORD((&z[3]), (GET_WORD(&x[4]) << (32 - (c))) | (GET_WORD(&x[3]) >> (c))); - SET_WORD((&z[4]), (GET_WORD(&x[5]) << (32 - (c))) | (GET_WORD(&x[4]) >> (c))); - SET_WORD((&z[5]), (GET_WORD(&x[6]) << (32 - (c))) | (GET_WORD(&x[5]) >> (c))); - SET_WORD((&z[6]), (GET_WORD(&x[7]) << (32 - (c))) | (GET_WORD(&x[6]) >> (c))); - SET_WORD((&z[7]), (GET_WORD(&x[7]) >> (c))); - - } while (0); -} - -/* Shift left by 1 <= c <= 31. */ -static void shiftleft(uint32_t *z, uint32_t *x, int c) -{ - do - { - SET_WORD(&z[7], (GET_WORD(&x[7]) << (c)) | GET_WORD(&z[6]) >> (32 - (c))); - SET_WORD(&z[6], (GET_WORD(&x[6]) << (c)) | GET_WORD(&z[5]) >> (32 - (c))); - SET_WORD(&z[5], (GET_WORD(&x[5]) << (c)) | GET_WORD(&z[4]) >> (32 - (c))); - SET_WORD(&z[4], (GET_WORD(&x[4]) << (c)) | GET_WORD(&z[3]) >> (32 - (c))); - SET_WORD(&z[3], (GET_WORD(&x[3]) << (c)) | GET_WORD(&z[2]) >> (32 - (c))); - SET_WORD(&z[2], (GET_WORD(&x[2]) << (c)) | GET_WORD(&z[1]) >> (32 - (c))); - SET_WORD(&z[1], (GET_WORD(&x[1]) << (c)) | GET_WORD(&z[0]) >> (32 - (c))); - SET_WORD(&z[0], (GET_WORD(&x[0]) << (c))); - } while (0); -} -#else -/* Shift right by 1 <= c <= 31. */ -static void shiftright(uint32_t *z, uint32_t *x, int c) -{ - do - { - SET_WORD(&z[0], (GET_WORD(&x[1]) << (32 - (c))) | (GET_WORD(&x[0]) >> (c))); - SET_WORD(&z[1], (GET_WORD(&x[2]) << (32 - (c))) | (GET_WORD(&x[1]) >> (c))); - SET_WORD(&z[2], (GET_WORD(&x[3]) << (32 - (c))) | (GET_WORD(&x[2]) >> (c))); - SET_WORD(&z[3], (GET_WORD(&x[4]) << (32 - (c))) | (GET_WORD(&x[3]) >> (c))); - SET_WORD(&z[4], (GET_WORD(&x[5]) << (32 - (c))) | (GET_WORD(&x[4]) >> (c))); - SET_WORD(&z[5], (GET_WORD(&x[6]) << (32 - (c))) | (GET_WORD(&x[5]) >> (c))); - SET_WORD(&z[6], (GET_WORD(&x[7]) << (32 - (c))) | (GET_WORD(&x[6]) >> (c))); - SET_WORD(&z[7], (GET_WORD(&x[8]) << (32 - (c))) | (GET_WORD(&x[7]) >> (c))); - SET_WORD(&z[8], (GET_WORD(&x[9]) << (32 - (c))) | (GET_WORD(&x[8]) >> (c))); - SET_WORD(&z[9], (GET_WORD(&x[10]) << (32 - (c))) | (GET_WORD(&x[9]) >> (c))); - SET_WORD(&z[10], (GET_WORD(&x[11]) << (32 - (c))) | (GET_WORD(&x[10]) >> (c))); - SET_WORD(&z[11], (GET_WORD(&x[11]) >> (c))); - } while (0); -} - -/* Shift left by 1 <= c <= 31. */ -static void shiftleft(uint32_t *z, uint32_t *x, int c) -{ - do - { - SET_WORD(&z[11], (GET_WORD(&x[11]) << (c)) | GET_WORD(&z[10]) >> (32 - (c))); - SET_WORD(&z[10], (GET_WORD(&x[10]) << (c)) | GET_WORD(&z[9]) >> (32 - (c))); - SET_WORD(&z[9], (GET_WORD(&x[9]) << (c)) | GET_WORD(&z[8]) >> (32 - (c))); - SET_WORD(&z[8], (GET_WORD(&x[8]) << (c)) | GET_WORD(&z[7]) >> (32 - (c))); - SET_WORD(&z[7], (GET_WORD(&x[7]) << (c)) | GET_WORD(&z[6]) >> (32 - (c))); - SET_WORD(&z[6], (GET_WORD(&x[6]) << (c)) | GET_WORD(&z[5]) >> (32 - (c))); - SET_WORD(&z[5], (GET_WORD(&x[5]) << (c)) | GET_WORD(&z[4]) >> (32 - (c))); - SET_WORD(&z[4], (GET_WORD(&x[4]) << (c)) | GET_WORD(&z[3]) >> (32 - (c))); - SET_WORD(&z[3], (GET_WORD(&x[3]) << (c)) | GET_WORD(&z[2]) >> (32 - (c))); - SET_WORD(&z[2], (GET_WORD(&x[2]) << (c)) | GET_WORD(&z[1]) >> (32 - (c))); - SET_WORD(&z[1], (GET_WORD(&x[1]) << (c)) | GET_WORD(&z[0]) >> (32 - (c))); - SET_WORD(&z[0], (GET_WORD(&x[0]) << (c))); - } while (0); -} -#endif - -/* Convert a projective point (X1 : Y1 : Z1) - * to the affine point (X3, Y3) = (X1/Z1^2,Y1/Z1^3) - * The memory of (X3, Y3) and (X1 : Y1 : Z1) should not overlap - */ -void Jac_toAffine(uint32_t *X3, uint32_t *Y3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1) -{ - uint32_t *T1, *T2; - - T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; - T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; - - square_casper(T1, Z1); // Z^2 - multiply_casper(T2, T1, Z1); // Z^3 - - // Montgomery inverse - invert(T1, T2); // Z^-3 - - multiply_casper(Y3, Y1, T1); // Y3 = Y/Z^3 - multiply_casper(T2, T1, Z1); // Z^-2 - multiply_casper(X3, X1, T2); // X3 = X/Z^2 -} - -/* Return 1 if (X1: Y1: Z1) is on the curve - * Y^2 = X^3 -3XZ^4 + bZ^6 - * and return 0 otherwise. - */ -int Jac_oncurve(uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *b) -{ - uint32_t *T1, *T2, *T3, *T4, *T5, *T6; - int m; - - T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; - T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; - T3 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; - T4 = &CASPER_MEM[ECC_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; - T5 = &CASPER_MEM[ECC_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; - T6 = &CASPER_MEM[ECC_SCRATCH_START + 5 * CASPER_NUM_LIMBS]; - - square_casper(T1, Y1); // Y^2 - square_casper(T6, X1); // X^2 - multiply_casper(T2, T6, X1); // X^3 - - square_casper(T3, Z1); // Z^2 - square_casper(T4, T3); // Z^4 - multiply_casper(T6, T4, T3); // Z^6 - multiply_casper(T3, b, T6); // bZ^6 - - multiply_casper(T6, T4, X1); // XZ^4 - - mul2_casper(T5, T6); - add_casper(T4, T5, T6); // 3XZ^4 - - sub_casper(T2, T2, T4); // X^3-3XZ^4 - add_casper(T2, T2, T3); // X^3-3XZ^4+bZ^6 - - CASPER_ECC_equal(&m, T1, T2); - if (m != 0) - { - return 0; - } - return 1; -} - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2 : Y2 : Z2) - * where (X1: Y1: Z1) != (X2 : Y2 : Z2) - * (X3 : Y3: Z3) may be the same as one of the inputs. - */ -void Jac_addition(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *Z1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *Z2) -{ - uint32_t *Z1Z1, *Z2Z2, *U1, *S1, *J, *H, *V, *t0, *t1; - int m1, m2; - - Z1Z1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; - Z2Z2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; - U1 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; - S1 = &CASPER_MEM[ECC_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; - J = &CASPER_MEM[ECC_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; - H = &CASPER_MEM[ECC_SCRATCH_START + 5 * CASPER_NUM_LIMBS]; - V = &CASPER_MEM[ECC_SCRATCH_START + 6 * CASPER_NUM_LIMBS]; - t0 = &CASPER_MEM[ECC_SCRATCH_START + 7 * CASPER_NUM_LIMBS]; - t1 = &CASPER_MEM[ECC_SCRATCH_START + 8 * CASPER_NUM_LIMBS]; - - CASPER_ECC_equal_to_zero(&m1, Z1); - CASPER_ECC_equal_to_zero(&m2, Z2); - if (m1 == 0) - { - CASPER_MEMCPY(X3, X2, NUM_LIMBS * 4); - CASPER_MEMCPY(Y3, Y2, NUM_LIMBS * 4); - CASPER_MEMCPY(Z3, Z2, NUM_LIMBS * 4); - return; - } - if (m2 == 0) - { - CASPER_MEMCPY(X3, X1, NUM_LIMBS * 4); - CASPER_MEMCPY(Y3, Y1, NUM_LIMBS * 4); - CASPER_MEMCPY(Z3, Z1, NUM_LIMBS * 4); - return; - } - - square_casper(Z1Z1, Z1); - square_casper(Z2Z2, Z2); - multiply_casper(U1, X1, Z2Z2); - multiply_casper(H, X2, Z1Z1); /* if H equals U1 then X's are the same */ - multiply_casper(t0, Z2, Z2Z2); - multiply_casper(S1, Y1, t0); - multiply_casper(t0, Z1, Z1Z1); - multiply_casper(J, Y2, t0); /* if (S1 == J) then Y's are the same */ - - CASPER_ECC_equal(&m1, H, U1); /* If H and U1 match then the X-coordinates are the same. */ - CASPER_ECC_equal(&m2, S1, J); /* If S1 and J match then the Y-coordinates are the same. */ - if (m1 == 0) - { - if (m2 == 0) - { - Jac_double(X3, Y3, Z3, X1, Y1, Z1); - return; - } - /* else { - We work with the point at infinity. - The Z-coordinate will be set to zero in this function. - } */ - } - - sub_casper(H, H, U1); - mul2_casper(t0, H); - square_casper(t1, t0); - sub_casper(t0, J, S1); - multiply_casper(J, H, t1); - multiply_casper(V, U1, t1); - mul2_casper(U1, t0); - square_casper(t0, U1); - mul2_casper(t1, V); - sub_casper(t0, t0, J); - sub_casper(X3, t0, t1); - sub_casper(t0, V, X3); - multiply_casper(t1, S1, J); - mul2_casper(t1, t1); - multiply_casper(V, U1, t0); - sub_casper(Y3, V, t1); - add_casper(V, Z1, Z2); - square_casper(t1, V); - sub_casper(t1, t1, Z1Z1); - sub_casper(t1, t1, Z2Z2); - multiply_casper(Z3, t1, H); -} - -/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2, Y2) - * where (X1: Y1: Z1) != (X2, Y2) - * (X3 : Y3: Z3) may not overlap with (X1: Y1: Z1). - * Source: 2004 Hankerson–Menezes–Vanstone, page 91. - */ -void Jac_add_affine( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *X2, uint32_t *Y2) -{ - uint32_t *T1, *T2, *T3, *T4, *T5; - int m1, m2; - - T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; - T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; - T3 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; - T4 = &CASPER_MEM[ECC_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; - T5 = &CASPER_MEM[ECC_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; - - CASPER_ECC_equal_to_zero(&m1, Z1); - if (m1 == 0) - { - CASPER_MEMCPY(X3, X2, NUM_LIMBS * 4); - CASPER_MEMCPY(Y3, Y2, NUM_LIMBS * 4); - CASPER_MEMCPY(Z3, ONE, NUM_LIMBS * 4); - return; - } - - copy(T5, Z1); - square_casper(T3, Z1); - multiply_casper(T2, T3, Z1); - multiply_casper(T4, T3, X2); - multiply_casper(T3, T2, Y2); - - CASPER_ECC_equal(&m1, T4, X1); - CASPER_ECC_equal(&m2, T3, Y1); - if (m1 == 0) - { - if (m2 == 0) - { - Jac_double(X3, Y3, Z3, X1, Y1, Z1); - return; - } - /* else { - We work with the point at infinity. - The Z-coordinate will be set to zero in this function. - } */ - } - - sub_casper(T1, T4, X1); - sub_casper(T2, T3, Y1); - multiply_casper(Z3, T5, T1); - square_casper(T3, T1); - multiply_casper(T4, T3, T1); - multiply_casper(T5, T3, X1); - mul2_casper(T1, T5); - square_casper(X3, T2); - sub_casper(X3, X3, T1); - sub_casper(X3, X3, T4); - sub_casper(T3, T5, X3); - multiply_casper(T1, T3, T2); - multiply_casper(T2, T4, Y1); - sub_casper(Y3, T1, T2); -} - -extern uint32_t casper_get_word(uint32_t *addr); - -/* Point doubling from: 2004 Hankerson–Menezes–Vanstone, page 91. - * Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X1 : Y1 : Z1) - * (X3 : Y3: Z3) may be the same as the input. - */ -void Jac_double(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1) -{ - uint32_t *T1, *T2, *T3, *T4, *T5; - - T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; - T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; - T3 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; - T4 = &CASPER_MEM[ECC_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; - T5 = &CASPER_MEM[ECC_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; - - square_casper(T1, Z1); - sub_casper(T3, X1, T1); - add_casper(T1, X1, T1); - multiply_casper(T4, T3, T1); - - mul2_casper(T3, T4); - - add_casper(T2, T3, T4); - - mul2_casper(Y3, Y1); - - copy(T5, Z1); - multiply_casper(Z3, Y3, T5); - - square_casper(T5, Y3); - - multiply_casper(T3, T5, X1); - - square_casper(Y3, T5); - - half(T5, Y3, T4); - - square_casper(X3, T2); - - mul2_casper(T1, T3); - - sub_casper(X3, X3, T1); - - sub_casper(T1, T3, X3); - - multiply_casper(T3, T1, T2); - - sub_casper(Y3, T3, T5); -} - -/* Recoding for a signed fixed window. - * Source: https://eprint.iacr.org/2014/130.pdf, Algorithm 6 - * Recode the n-bit integer k into ciel(log2(n)/(w-1)) digits - * where each digit is in - * { +/- 1, +/- 3, ..., +/- 2^(w-1)-1 } - * and put the result in c. - */ -static void recode(int8_t *c, uint32_t *k, int n, int w) -{ - int i, t; - uint32_t K[NUM_LIMBS] = {0}; - memcpy(K, k, (size_t)ceil(n / 8.)); - t = (n + (w - 2)) / (w - 1); - for (i = 0; i < t; i++) - { - c[i] = (K[0] & ((1 << w) - 1)) - (1 << (w - 1)); - shiftrightSysram(K, K, w - 1); - add_n_1(K, K, (uint32_t)c[i] >> 31, NUM_LIMBS); - } - c[t] = K[0]; -} - -static uint32_t sub_n(uint32_t *c, uint32_t *a, uint32_t *b, int n) -{ - int i; - uint32_t borrow; - sub_borrowout(borrow, GET_WORD(&c[0]), a[0], GET_WORD(&b[0])); - for (i = 1; i < n; i++) - { - sub_borrowin_borrowout(borrow, GET_WORD(&c[i]), a[i], GET_WORD(&b[i]), borrow); - } - return borrow; -} - -#if 0 -/* Dumb n-limb subtraction of c=a-b, return borrow. */ -static uint32_t sub_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n) { - int i; - uint32_t borrow; - sub_borrowout(borrow, c[0], a[0], b); - for (i = 1; i < n; i++) { - sub_borrowin_borrowout_1(borrow, c[i], a[i], borrow); - } - return borrow; -} - -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n(uint32_t *c, uint32_t *a, uint32_t *b, int n) { - int i; - uint32_t carry; - add_cout(carry, c[0], a[0], b[0]); - for (i = 1; i < n; i++) { - add_cout_cin(carry, c[i], a[i], b[i], carry); - } - return carry; -} -#endif - -/* Dumb n-limb addition of c=a+b, return carry. */ -static uint32_t add_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n) -{ - int i; - uint32_t carry; - add_cout(carry, c[0], a[0], b); - for (i = 1; i < n; i++) - { - add_cout_cin(carry, c[i], a[i], 0, carry); - } - return carry; -} - -// http://graphics.stanford.edu/~seander/bithacks.html#IntegerAbs -static uint8_t int8abs(int8_t v) -{ - int8_t const mask = v >> 7; - return (v + mask) ^ mask; -} - -/* Constant time elliptic curve scalar multiplication. - * Source: https://eprint.iacr.org/2014/130.pdf - * when using w = 4. - * Computes (X3 : Y3 : Z3) = k * (X1, Y1) \in E(F_p) - * p is the prime used to define the finite field F_p - * q is the (prime) order of the curve - */ -void Jac_scalar_multiplication( - uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *k, uint32_t *p, uint32_t *q) -{ - uint32_t *scalar, *M, *X, *Y, *Z, *mem; - int i, sign, odd; - // int8_t *rec; - uint8_t index; - - /* Point to the start of the LUT table space. */ - mem = &CASPER_MEM[LUT_SCRATCH_START]; - - scalar = &CASPER_MEM[LUT_SCRATCH_START + 12 * CASPER_NUM_LIMBS]; - X = &CASPER_MEM[LUT_SCRATCH_START + 13 * CASPER_NUM_LIMBS]; - Y = &CASPER_MEM[LUT_SCRATCH_START + 14 * CASPER_NUM_LIMBS]; - Z = &CASPER_MEM[LUT_SCRATCH_START + 15 * CASPER_NUM_LIMBS]; - M = &CASPER_MEM[LUT_SCRATCH_START + 16 * CASPER_NUM_LIMBS]; - - /* Point to memory the recoded scalar. - * CASPER_RECODE_LENGTH bytes is needed. - */ - // rec = (int8_t*)&CASPER_MEM[LUT_SCRATCH_START + 17 * CASPER_NUM_LIMBS]; - int8_t rec[CASPER_RECODE_LENGTH]; - - CASPER_MEMCPY(scalar, k, sizeof(uint32_t) * NUM_LIMBS); - -/* Precomputation: compute 1*P, 3*P, 5*P, and 7*P */ -#define LUT(P, x) (mem + (3 * ((P)-1) / 2 + (x)) * CASPER_NUM_LIMBS) - - /* Set 1*P */ - copy(Z3, ONE); - copy(LUT(1, 0), X1); - copy(LUT(1, 1), Y1); - copy(LUT(1, 2), Z3); - - /* Compute 2*P */ - Jac_double(X3, Y3, Z3, X1, Y1, Z3); - - /* Compute 3*P = 2P + P */ - Jac_add_affine(LUT(3, 0), LUT(3, 1), LUT(3, 2), X3, Y3, Z3, X1, Y1); - - /* Compute 5*P = 3P + 2P */ - Jac_addition(LUT(5, 0), LUT(5, 1), LUT(5, 2), LUT(3, 0), LUT(3, 1), LUT(3, 2), X3, Y3, Z3); - - /* Compute 7*P = 5P + 2P */ - Jac_addition(LUT(7, 0), LUT(7, 1), LUT(7, 2), LUT(5, 0), LUT(5, 1), LUT(5, 2), X3, Y3, Z3); - - /* Recode the scalar */ - odd = casper_get_word(&scalar[0]) & 1u; - sub_n(M, q, scalar, NUM_LIMBS); // todo!!! - casper_select(scalar, M, scalar, odd, NUM_LIMBS); - - /* Use n=384 and w=4 --> compute ciel(384/3) = 128 + 1 digits */ - uint32_t scalarSysram[/*CASPER_*/ NUM_LIMBS]; - CASPER_MEMCPY(scalarSysram, scalar, /*CASPER_*/ NUM_LIMBS * sizeof(uint32_t)); - recode(rec, scalarSysram, N_bitlen, 4); - - /* Set the first value. */ - index = int8abs(rec[CASPER_RECODE_LENGTH - 1]); - sign = ((uint8_t)rec[CASPER_RECODE_LENGTH - 1]) >> 7; - copy(X3, LUT(index, 0)); - copy(Y3, LUT(index, 1)); - copy(Z3, LUT(index, 2)); - -/* Get the correct LUT element in constant time by touching - * all elements and masking out the correct one. - */ - -#define GET_LUT(x, y, z, index) \ - do \ - { \ - int m; \ - copy(x, LUT(1, 0)); \ - copy(y, LUT(1, 1)); \ - copy(z, LUT(1, 2)); \ - m = (index == 3); \ - casper_select(x, x, LUT(3, 0), m, NUM_LIMBS); \ - casper_select(y, y, LUT(3, 1), m, NUM_LIMBS); \ - casper_select(z, z, LUT(3, 2), m, NUM_LIMBS); \ - m = (index == 5); \ - casper_select(x, x, LUT(5, 0), m, NUM_LIMBS); \ - casper_select(y, y, LUT(5, 1), m, NUM_LIMBS); \ - casper_select(z, z, LUT(5, 2), m, NUM_LIMBS); \ - m = (index == 7); \ - casper_select(x, x, LUT(7, 0), m, NUM_LIMBS); \ - casper_select(y, y, LUT(7, 1), m, NUM_LIMBS); \ - casper_select(z, z, LUT(7, 2), m, NUM_LIMBS); \ - } while (0) - - GET_LUT(X3, Y3, Z3, index); - - /* Compute -y and select the positive or negative point. */ - sub_n(M, p, Y3, NUM_LIMBS); // todo!!! - casper_select(Y3, Y3, M, sign, NUM_LIMBS); - - for (i = CASPER_RECODE_LENGTH - 2; i >= 0; i--) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - - index = int8abs(rec[i]); - sign = ((uint8_t)rec[i]) >> 7; - - GET_LUT(X, Y, Z, index); - - /* Compute -y and select the positive or negative point. */ - sub_n(scalar, p, Y, NUM_LIMBS); // todo!!! - casper_select(scalar, Y, scalar, sign, NUM_LIMBS); - - Jac_addition(X3, Y3, Z3, X3, Y3, Z3, X, scalar, Z); - } - - sub_n(M, p, Y3, NUM_LIMBS); // todo!!! - - casper_select(Y3, M, Y3, odd, NUM_LIMBS); -} - -#undef LUT -#undef GET_LUT - -/* - * Pre-compute the following 16 points: - * 00 00 = 0*P + 0*Q <-- Not needed when using sliding windows - * 00 01 = 0*P + 1*Q <-- Not needed when using sliding windows - * 00 10 = 0*P + 2*Q - * 00 11 = 0*P + 3*Q - * - * 01 00 = 1*P + 0*Q <-- Not needed when using sliding windows - * 01 01 = 1*P + 1*Q <-- Not needed when using sliding windows - * 01 10 = 1*P + 2*Q - * 01 11 = 1*P + 3*Q - * - * 10 00 = 2*P + 0*Q - * 10 01 = 2*P + 1*Q - * 10 10 = 2*P + 2*Q - * 10 11 = 2*P + 3*Q - * - * 11 00 = 3*P + 0*Q - * 11 01 = 3*P + 1*Q - * 11 10 = 3*P + 2*Q - * 11 11 = 3*P + 3*Q - * - * index = (bitsi||bitsj)-2 - (biti != 0)*2 - * - * Input: P = (X1 : Y1 : Z1) and - * Q = (X2 : Y2 : Z2) - * Output: mem, memory location for the LUT. - */ - -#define LUT_LIMBS NUM_LIMBS - -static void precompute_double_scalar_LUT(uint32_t *Px, uint32_t *Py, uint32_t *Qx, uint32_t *Qy) -{ - uint32_t *Q2x, *Q2y, *Q2z, *P2x, *P2y, *P2z, *Z, *mem; - int index = 0; - - Q2x = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 0 * CASPER_NUM_LIMBS]; - Q2y = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 1 * CASPER_NUM_LIMBS]; - Q2z = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 2 * CASPER_NUM_LIMBS]; - - /* Re-use memory from different scratch space since no - * projective point addition is used below. */ - P2x = &CASPER_MEM[ECC_SCRATCH_START + 5 * CASPER_NUM_LIMBS]; - P2z = &CASPER_MEM[ECC_SCRATCH_START + 6 * CASPER_NUM_LIMBS]; - P2y = &CASPER_MEM[ECC_SCRATCH_START + 7 * CASPER_NUM_LIMBS]; - Z = &CASPER_MEM[ECC_SCRATCH_START + 8 * CASPER_NUM_LIMBS]; - - mem = &CASPER_MEM[LUT_SCRATCH_START]; - - copy(Z, ONE); - - // 00 10 = 0*P + 2*Q - Jac_double(Q2x, Q2y, Q2z, Qx, Qy, Z); - copy(&mem[index], Q2x); - index += LUT_LIMBS; - copy(&mem[index], Q2y); - index += LUT_LIMBS; - copy(&mem[index], Q2z); - index += LUT_LIMBS; - - // 00 11 = 0*P + 3*Q - Jac_add_affine(P2x, P2y, P2z, Q2x, Q2y, Q2z, Qx, Qy); - copy(&mem[index], P2x); - index += LUT_LIMBS; - copy(&mem[index], P2y); - index += LUT_LIMBS; - copy(&mem[index], P2z); - index += LUT_LIMBS; - - // 01 10 = 1*P + 2*Q - Jac_add_affine(P2x, P2y, P2z, Q2x, Q2y, Q2z, Px, Py); - copy(&mem[index], P2x); - index += LUT_LIMBS; - copy(&mem[index], P2y); - index += LUT_LIMBS; - copy(&mem[index], P2z); - index += LUT_LIMBS; - - // 01 11 = 1*P + 3*Q - Jac_add_affine(P2x, P2y, P2z, P2x, P2y, P2z, Qx, Qy); - copy(&mem[index], P2x); - index += LUT_LIMBS; - copy(&mem[index], P2y); - index += LUT_LIMBS; - copy(&mem[index], P2z); - index += LUT_LIMBS; - - // 10 00 = 2*P + 0*Q - Jac_double(P2x, P2y, P2z, Px, Py, Z); - copy(&mem[index], P2x); - index += LUT_LIMBS; - copy(&mem[index], P2y); - index += LUT_LIMBS; - copy(&mem[index], P2z); - index += LUT_LIMBS; - - // 10 01 = 2*P + 1*Q - Jac_add_affine(Q2x, Q2y, Q2z, P2x, P2y, P2z, Qx, Qy); - copy(&mem[index], Q2x); - index += LUT_LIMBS; - copy(&mem[index], Q2y); - index += LUT_LIMBS; - copy(&mem[index], Q2z); - index += LUT_LIMBS; - - // 10 10 = 2*P + 2*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - copy(&mem[index], Q2x); - index += LUT_LIMBS; - copy(&mem[index], Q2y); - index += LUT_LIMBS; - copy(&mem[index], Q2z); - index += LUT_LIMBS; - - // 10 11 = 2*P + 3*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - copy(&mem[index], Q2x); - index += LUT_LIMBS; - copy(&mem[index], Q2y); - index += LUT_LIMBS; - copy(&mem[index], Q2z); - index += LUT_LIMBS; - - // 11 00 = 3*P + 0*Q - Jac_add_affine(P2x, P2y, P2z, P2x, P2y, P2z, Px, Py); - copy(&mem[index], P2x); - index += LUT_LIMBS; - copy(&mem[index], P2y); - index += LUT_LIMBS; - copy(&mem[index], P2z); - index += LUT_LIMBS; - - // 11 01 = 3*P + 1*Q - Jac_add_affine(Q2x, Q2y, Q2z, P2x, P2y, P2z, Qx, Qy); - copy(&mem[index], Q2x); - index += LUT_LIMBS; - copy(&mem[index], Q2y); - index += LUT_LIMBS; - copy(&mem[index], Q2z); - index += LUT_LIMBS; - - // 11 10 = 3*P + 2*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - copy(&mem[index], Q2x); - index += LUT_LIMBS; - copy(&mem[index], Q2y); - index += LUT_LIMBS; - copy(&mem[index], Q2z); - index += LUT_LIMBS; - - // 11 11 = 3*P + 3*Q - Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - copy(&mem[index], Q2x); - index += LUT_LIMBS; - copy(&mem[index], Q2y); - index += LUT_LIMBS; - copy(&mem[index], Q2z); - index += LUT_LIMBS; -} - -#define GETLUTX(x) (3 * (x)*LUT_LIMBS) -#define GETLUTY(x) (3 * (x)*LUT_LIMBS + 1 * LUT_LIMBS) -#define GETLUTZ(x) (3 * (x)*LUT_LIMBS + 2 * LUT_LIMBS) - -/* Compute the double scalar multiplication - * (X3 : Y3 : Z3) = k1 * (X1, Y1) + k2 * (X2, Y2) - * Using Shamir's trick and precomputing 16 points. - * This code is *not* constant time since this is used - * for verification only. - */ -void double_scalar_multiplication(uint32_t *X3, - uint32_t *Y3, - uint32_t *Z3, - uint32_t *X1, - uint32_t *Y1, - uint32_t *k1, - uint32_t *X2, - uint32_t *Y2, - uint32_t *k2) -{ - uint32_t index, c = 0; - uint32_t *p1, *p2, x1, x2, *lut, *Tx, *Ty, *Tz; - - precompute_double_scalar_LUT(X1, Y1, X2, Y2); - - lut = &CASPER_MEM[LUT_SCRATCH_START]; - p1 = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS]; - p2 = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 1 * CASPER_NUM_LIMBS]; - - Tx = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 2 * CASPER_NUM_LIMBS]; - Ty = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 3 * CASPER_NUM_LIMBS]; - Tz = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 4 * CASPER_NUM_LIMBS]; - - CASPER_MEMCPY(p1, k1, sizeof(uint32_t) * NUM_LIMBS); - CASPER_MEMCPY(p2, k2, sizeof(uint32_t) * NUM_LIMBS); - - /* Check if we can slide. */ - while (((casper_get_word(&p1[NUM_LIMBS - 1]) | casper_get_word(&p2[NUM_LIMBS - 1])) >> 31) == 0 && c < 256) - { - shiftleft(p1, p1, 1); - shiftleft(p2, p2, 1); - c++; - /* No doubling needed. */ - } - - /* Set the first value. */ - x1 = casper_get_word(&p1[NUM_LIMBS - 1]) >> 30; - x2 = casper_get_word(&p2[NUM_LIMBS - 1]) >> 30; - index = (x2 | (x1 << 2)) - 2 - (x1 != 0) * 2; - shiftleft(p1, p1, 2); - shiftleft(p2, p2, 2); - - copy(X3, &lut[GETLUTX(index)]); - copy(Y3, &lut[GETLUTY(index)]); - copy(Z3, &lut[GETLUTZ(index)]); - c += 2; - -// todo: create an is_zero function -#if CASPER_ECC_P256 - while ((casper_get_word(&p1[0]) | casper_get_word(&p1[1]) | casper_get_word(&p1[2]) | casper_get_word(&p1[3]) | - casper_get_word(&p1[4]) | casper_get_word(&p1[5]) | casper_get_word(&p1[6]) | casper_get_word(&p1[7]) | - casper_get_word(&p2[0]) | casper_get_word(&p2[1]) | casper_get_word(&p2[2]) | casper_get_word(&p2[3]) | - casper_get_word(&p2[4]) | casper_get_word(&p2[5]) | casper_get_word(&p2[6]) | casper_get_word(&p2[7])) != 0) - { -#elif CASPER_ECC_P384 - while ((casper_get_word(&p1[0]) | casper_get_word(&p1[1]) | casper_get_word(&p1[2]) | casper_get_word(&p1[3]) | - casper_get_word(&p1[4]) | casper_get_word(&p1[5]) | casper_get_word(&p1[6]) | casper_get_word(&p1[7]) | - casper_get_word(&p1[8]) | casper_get_word(&p1[9]) | casper_get_word(&p1[10]) | casper_get_word(&p1[11]) | - casper_get_word(&p2[0]) | casper_get_word(&p2[1]) | casper_get_word(&p2[2]) | casper_get_word(&p2[3]) | - casper_get_word(&p2[4]) | casper_get_word(&p2[5]) | casper_get_word(&p2[6]) | casper_get_word(&p2[7]) | - casper_get_word(&p2[8]) | casper_get_word(&p2[9]) | casper_get_word(&p2[10]) | casper_get_word(&p2[11])) != - 0) - { -#endif - /* Check if we can slide. */ - while (((casper_get_word(&p1[NUM_LIMBS - 1]) | casper_get_word(&p2[NUM_LIMBS - 1])) >> 31) == 0 && c < N_bitlen) - { - shiftleft(p1, p1, 1); - shiftleft(p2, p2, 1); - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - c++; - } - - if (c >= (N_bitlen - 1)) - break; - - /* Double twice. */ - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - - /* Add in the correct value. */ - x1 = casper_get_word(&p1[NUM_LIMBS - 1]) >> 30; - x2 = casper_get_word(&p2[NUM_LIMBS - 1]) >> 30; - index = (x2 | (x1 << 2)) - 2 - (x1 != 0) * 2; - - shiftleft(p1, p1, 2); - shiftleft(p2, p2, 2); - - copy(Tx, &lut[GETLUTX(index)]); - copy(Ty, &lut[GETLUTY(index)]); - copy(Tz, &lut[GETLUTZ(index)]); - - Jac_addition(X3, Y3, Z3, X3, Y3, Z3, Tx, Ty, - Tz); //&lut[GETLUTX(index)], &lut[GETLUTY(index)], &lut[GETLUTZ(index)]); - c += 2; - } - - /* Special case in the end. */ - if (c == (N_bitlen - 1)) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - x1 = casper_get_word(&p1[NUM_LIMBS - 1]) >> 31; - x2 = casper_get_word(&p2[NUM_LIMBS - 1]) >> 31; - if (x1) - { - Jac_add_affine(X3, Y3, Z3, X3, Y3, Z3, X1, Y1); - } - if (x2) - { - Jac_add_affine(X3, Y3, Z3, X3, Y3, Z3, X2, Y2); - } - c++; - } - - while (c < N_bitlen) - { - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - c++; - } -} - -#if CASPER_ECC_P256 -static void invert_mod_p256(uint32_t *c, uint32_t *a) -{ - int i; - uint32_t *t, *t2, *s1, *s2, *s4, *s8, *tmp; - - /* Assuming it is safe to use the ECC scratch size. */ - t = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; - t2 = &CASPER_MEM[ECC_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; - s1 = &CASPER_MEM[ECC_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; - s2 = &CASPER_MEM[ECC_SCRATCH_START + 5 * CASPER_NUM_LIMBS]; - s4 = &CASPER_MEM[ECC_SCRATCH_START + 6 * CASPER_NUM_LIMBS]; - s8 = &CASPER_MEM[ECC_SCRATCH_START + 7 * CASPER_NUM_LIMBS]; - tmp = &CASPER_MEM[ECC_SCRATCH_START + 8 * CASPER_NUM_LIMBS]; - - // t2 = n^(2^1)*n # 11 - square_casper(tmp, a); - multiply_casper(t2, tmp, a); - - // s1 = t2^(2^2)*t2 # F - square_casper(s1, t2); - square_casper(tmp, s1); - multiply_casper(s1, tmp, t2); - - // s2 = s1^(2^4)*s1 # FF - square_casper(s2, s1); - // for (i = 1; i < 4; i++) square(s2, s2); - square_casper(tmp, s2); - square_casper(s2, tmp); - square_casper(tmp, s2); - multiply_casper(s2, tmp, s1); - - // s4 = s2^(2^8)*s2 # FFFF - square_casper(s4, s2); - for (i = 1; i < 7; i += 2) - { - square_casper(tmp, s4); - square_casper(s4, tmp); - } - square_casper(tmp, s4); - multiply_casper(s4, tmp, s2); - - // s8 = s4^(2^16)*s4 # FFFFFFFF - square_casper(s8, s4); - for (i = 1; i < 15; i += 2) - { - square_casper(tmp, s8); - square_casper(s8, tmp); - } - square_casper(tmp, s8); - multiply_casper(s8, tmp, s4); - - // t = s8^(2^32)*n # ffffffff00000001 - square_casper(tmp, s8); - for (i = 1; i < 31; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - square_casper(t, tmp); - multiply_casper(tmp, t, a); - - // t = t^(2^128)*s8 # ffffffff00000001000000000000000000000000ffffffff - for (i = 0; i < 128; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - multiply_casper(t, tmp, s8); - - // t = t^(2^32)*s8 # ffffffff00000001000000000000000000000000ffffffffffffffff - for (i = 0; i < 32; i += 2) - { - square_casper(tmp, t); - square_casper(t, tmp); - } - multiply_casper(tmp, t, s8); - - // t = t^(2^16)*s4 # ffffffff00000001000000000000000000000000ffffffffffffffffffff - for (i = 0; i < 16; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - multiply_casper(t, tmp, s4); - - // t = t^(2^8)*s2 # ffffffff00000001000000000000000000000000ffffffffffffffffffffff - for (i = 0; i < 8; i += 2) - { - square_casper(tmp, t); - square_casper(t, tmp); - } - multiply_casper(tmp, t, s2); - - // t = t^(2^4)*s1 # ffffffff00000001000000000000000000000000fffffffffffffffffffffff - for (i = 0; i < 4; i += 2) - { - square_casper(t, tmp); - square_casper(tmp, t); - } - multiply_casper(t, tmp, s1); - - // t = t^(2^2)*t2 - square_casper(tmp, t); - square_casper(t, tmp); - multiply_casper(tmp, t, t2); - - // t = t^(2^2)*n # ffffffff00000001000000000000000000000000fffffffffffffffffffffffd - square_casper(t, tmp); - square_casper(tmp, t); - multiply_casper(c, tmp, a); -} - -// A and C do not need to be in Casper memory -static void toMontgomery(uint32_t *C, uint32_t *A) -{ - /* R^2 = 2^512 mod p, used to convert values to Montgomery form. */ - uint32_t R2[NUM_LIMBS] = {0x00000003, 0x00000000, 0xffffffff, 0xfffffffb, 0xfffffffe, 0xffffffff, 0xfffffffd, 0x4}; - uint32_t *T1, *T2, *T3; - T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; - T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; - T3 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; - - CASPER_MEMCPY(T1, R2, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(T2, A, NUM_LIMBS * sizeof(uint32_t)); - - multiply_casper(T3, T2, T1); - CASPER_MEMCPY(C, T3, NUM_LIMBS * sizeof(uint32_t)); -} -#endif /* CASPER_ECC_P256 */ - -/* Compute inversion modulo NIST-p384 using Fermats little theorem. - * Using c = a^(p-2) = a^(-1) mod p. - * This computes the modular inversion if all arithmetic is "regular" - * modular arithmetic or computes automatically the Montgomery inverse - * if all arithmetic is Montgomery arithmetic. - */ -#if CASPER_ECC_P384 -static void invert_mod_p384(uint32_t *c, uint32_t *a) -{ - int i; - uint32_t *e, *d, *tmp, *t0, *t1, *t2, *t3, *t4, *t5, *t6; // 10 residues needed - - /* Assuming it is safe to use the LUT scratch size. - * Hence, do not invert while elements in the LUT are needed. - */ - e = &CASPER_MEM[LUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; - d = &CASPER_MEM[LUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; - tmp = &CASPER_MEM[LUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; - t0 = &CASPER_MEM[LUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; - t1 = &CASPER_MEM[LUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; - t2 = &CASPER_MEM[LUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS]; - t3 = &CASPER_MEM[LUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS]; - t4 = &CASPER_MEM[LUT_SCRATCH_START + 7 * CASPER_NUM_LIMBS]; - t5 = &CASPER_MEM[LUT_SCRATCH_START + 8 * CASPER_NUM_LIMBS]; - t6 = &CASPER_MEM[LUT_SCRATCH_START + 9 * CASPER_NUM_LIMBS]; - - square_casper(tmp, a); // 2 - square_casper(t1, tmp); // 4 - square_casper(tmp, t1); // 8 - multiply_casper(t2, tmp, t1); // 12 - multiply_casper(d, a, t2); // 13 - multiply_casper(e, d, a); // 14 - multiply_casper(t0, e, a); // 15 - - // t1 = t0^(2^4)*t0 # ff - square_casper(tmp, t0); - square_casper(t1, tmp); - square_casper(tmp, t1); - square_casper(t2, tmp); - multiply_casper(t1, t2, t0); - - // t2 = t1^(2^8)*t1 # 4f - square_casper(tmp, t1); - for (i = 0; i < 3; i++) - { - square_casper(t3, tmp); - square_casper(tmp, t3); - } - square_casper(t3, tmp); - multiply_casper(t2, t3, t1); - - // t3 = t2^(2^16)*t2 # 8f - square_casper(tmp, t2); - for (i = 0; i < 7; i++) - { - square_casper(t4, tmp); - square_casper(tmp, t4); - } - square_casper(t4, tmp); - multiply_casper(t3, t4, t2); - - // t4 = t3^(2^32)*t3 # 16f - square_casper(tmp, t3); - for (i = 0; i < 15; i++) - { - square_casper(t5, tmp); - square_casper(tmp, t5); - } - square_casper(t5, tmp); - multiply_casper(t4, t5, t3); - - // t5 = t4^(2^64)*t4 # 32f - square_casper(tmp, t4); - for (i = 0; i < 31; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t4); - - // t5 = t5^(2^64)*t4 # 48f - square_casper(tmp, t5); - for (i = 0; i < 31; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t4); - - // t5 = t5^(2^32)*t3 # 56f - square_casper(tmp, t5); - for (i = 0; i < 15; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t3); - - // t5 = t5^(2^16)*t2 # 60f - square_casper(tmp, t5); - for (i = 0; i < 7; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t2); - - // t5 = t5^(2^8)*t1 # 62f - square_casper(tmp, t5); - for (i = 0; i < 3; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t1); - - // n = t5^(2^4)*t0 # 63f - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t0); - - // n = n^(2^4)*e - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, e); - - // n = n^(2^32)*t3 - square_casper(tmp, t5); - for (i = 0; i < 15; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t3); - - // n = n^(2^64) - square_casper(tmp, t5); - for (i = 0; i < 31; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t5, tmp); - - // n = n^(2^16)*t2 - square_casper(tmp, t5); - for (i = 0; i < 7; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t2); - - // n = n^(2^8)*t1 - square_casper(tmp, t5); - for (i = 0; i < 3; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t1); - - // n = n^(2^4)*t0 - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(t5, t6, t0); - - // n = n^(2^4)*d - square_casper(tmp, t5); - for (i = 0; i < 1; i++) - { - square_casper(t6, tmp); - square_casper(tmp, t6); - } - square_casper(t6, tmp); - multiply_casper(c, t6, d); -} - -// A and C do not need to be in Casper memory -static void toMontgomery(uint32_t *C, uint32_t *A) -{ - /* R^2 = 2^768 mod p, used to convert values to Montgomery form. */ - uint32_t R2[NUM_LIMBS] = {0x00000001, 0xfffffffe, 0x00000000, 0x00000002, 0x00000000, 0xfffffffe, - 0x00000000, 0x00000002, 0x1, 0x0, 0x0, 0x0}; - uint32_t *T1, *T2, *T3; - T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; - T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; - T3 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; - - CASPER_MEMCPY(T1, R2, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(T2, A, NUM_LIMBS * sizeof(uint32_t)); - - multiply_casper(T3, T2, T1); - CASPER_MEMCPY(C, T3, NUM_LIMBS * sizeof(uint32_t)); -} -#endif /* CASPER_ECC_P384 */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_casper.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_casper.h deleted file mode 100644 index b7cc9dbe06..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_casper.h +++ /dev/null @@ -1,301 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CASPER_H_ -#define _FSL_CASPER_H_ - -#include "fsl_common.h" - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! - * @addtogroup casper_driver - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief CASPER driver version. Version 2.0.2. - * - * Current version: 2.0.2 - * - * Change log: - * - Version 2.0.0 - * - Initial version - * - Version 2.0.1 - * - Bug fix KPSDK-24531 double_scalar_multiplication() result may be all zeroes for some specific input - * - Version 2.0.2 - * - Bug fix KPSDK-25015 CASPER_MEMCPY hard-fault on LPC55xx when both source and destination buffers are outside of CASPER_RAM - */ -#define FSL_CASPER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/*! @brief CASPER operation - * - */ -typedef enum _casper_operation -{ - kCASPER_OpMul6464NoSum = 0x01, /*! Walking 1 or more of J loop, doing r=a*b using 64x64=128*/ - kCASPER_OpMul6464Sum = - 0x02, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but assume inner j loop*/ - kCASPER_OpMul6464FullSum = - 0x03, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but sum all of w. */ - kCASPER_OpMul6464Reduce = - 0x04, /*! Walking 1 or more of J loop, doing c,r[-1]=r+a*b using 64x64=128, but skip 1st write*/ - kCASPER_OpAdd64 = 0x08, /*! Walking add with off_AB, and in/out off_RES doing c,r=r+a+c using 64+64=65*/ - kCASPER_OpSub64 = 0x09, /*! Walking subtract with off_AB, and in/out off_RES doing r=r-a uding 64-64=64, with last - borrow implicit if any*/ - kCASPER_OpDouble64 = 0x0A, /*! Walking add to self with off_RES doing c,r=r+r+c using 64+64=65*/ - kCASPER_OpXor64 = 0x0B, /*! Walking XOR with off_AB, and in/out off_RES doing r=r^a using 64^64=64*/ - kCASPER_OpShiftLeft32 = - 0x10, /*! Walking shift left doing r1,r=(b*D)|r1, where D is 2^amt and is loaded by app (off_CD not used)*/ - kCASPER_OpShiftRight32 = 0x11, /*! Walking shift right doing r,r1=(b*D)|r1, where D is 2^(32-amt) and is loaded by - app (off_CD not used) and off_RES starts at MSW*/ - kCASPER_OpCopy = 0x14, /*! Copy from ABoff to resoff, 64b at a time*/ - kCASPER_OpRemask = 0x15, /*! Copy and mask from ABoff to resoff, 64b at a time*/ - kCASPER_OpCompare = 0x16, /*! Compare two arrays, running all the way to the end*/ - kCASPER_OpCompareFast = 0x17, /*! Compare two arrays, stopping on 1st !=*/ -} casper_operation_t; - -#define CASPER_CP 1 -#define CASPER_CP_CTRL0 (0x0 >> 2) -#define CASPER_CP_CTRL1 (0x4 >> 2) -#define CASPER_CP_LOADER (0x8 >> 2) -#define CASPER_CP_STATUS (0xC >> 2) -#define CASPER_CP_INTENSET (0x10 >> 2) -#define CASPER_CP_INTENCLR (0x14 >> 2) -#define CASPER_CP_INTSTAT (0x18 >> 2) -#define CASPER_CP_AREG (0x20 >> 2) -#define CASPER_CP_BREG (0x24 >> 2) -#define CASPER_CP_CREG (0x28 >> 2) -#define CASPER_CP_DREG (0x2C >> 2) -#define CASPER_CP_RES0 (0x30 >> 2) -#define CASPER_CP_RES1 (0x34 >> 2) -#define CASPER_CP_RES2 (0x38 >> 2) -#define CASPER_CP_RES3 (0x3C >> 2) -#define CASPER_CP_MASK (0x60 >> 2) -#define CASPER_CP_REMASK (0x64 >> 2) -#define CASPER_CP_LOCK (0x80 >> 2) -#define CASPER_CP_ID (0xFFC >> 2) -/* mcr (cp, opc1, value, CRn, CRm, opc2) */ -#define CASPER_Wr32b(value, off) __arm_mcr(CASPER_CP, 0, value, ((off >> 4)), (off), 0) -/* mcrr(coproc, opc1, value, CRm) */ -#define CASPER_Wr64b(value, off) __arm_mcrr(CASPER_CP, 0, value, off) -/* mrc(coproc, opc1, CRn, CRm, opc2) */ -#define CASPER_Rd32b(off) __arm_mrc(CASPER_CP, 0, ((off >> 4)), (off), 0) - -/* The model for this algo is that it can be implemented for a fixed size RSA key */ -/* for max speed. If this is made into a variable (to allow varying size), then */ -/* it will be slower by a bit. */ -/* The file is compiled with N_bitlen passed in as number of bits of the RSA key */ -/* #define N_bitlen 2048 */ -#define N_wordlen_max (4096 / 32) - -#define CASPER_ECC_P256 1 -#define CASPER_ECC_P384 0 - -#if CASPER_ECC_P256 -#define N_bitlen 256 -#endif /* CASPER_ECC_P256 */ - -#if CASPER_ECC_P384 -#define N_bitlen 384 -#endif /* CASPER_ECC_P256 */ - -#define NUM_LIMBS (N_bitlen / 32) - -enum -{ - kCASPER_RamOffset_Result = 0x0u, - kCASPER_RamOffset_Base = (N_wordlen_max + 8u), - kCASPER_RamOffset_TempBase = (2u * N_wordlen_max + 16u), - kCASPER_RamOffset_Modulus = (kCASPER_RamOffset_TempBase + N_wordlen_max + 4u), - kCASPER_RamOffset_M64 = 1022, -}; - -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup casper_driver - * @{ - */ - -/*! - * @brief Enables clock and disables reset for CASPER peripheral. - * - * Enable clock and disable reset for CASPER. - * - * @param base CASPER base address - */ -void CASPER_Init(CASPER_Type *base); - -/*! - * @brief Disables clock for CASPER peripheral. - * - * Disable clock and enable reset. - * - * @param base CASPER base address - */ -void CASPER_Deinit(CASPER_Type *base); - -/*! - *@} - */ /* end of casper_driver */ - -/******************************************************************************* - * PKHA API - ******************************************************************************/ - -/*! - * @addtogroup casper_driver_pkha - * @{ - */ - -/*! - * @brief Performs modular exponentiation - (A^E) mod N. - * - * This function performs modular exponentiation. - * - * @param base CASPER base address - * @param signature first addend (in little endian format) - * @param pubN modulus (in little endian format) - * @param wordLen Size of pubN in bytes - * @param pubE exponent - * @param[out] plaintext Output array to store result of operation (in little endian format) - */ -void CASPER_ModExp(CASPER_Type *base, - const uint8_t *signature, - const uint8_t *pubN, - size_t wordLen, - uint32_t pubE, - uint8_t *plaintext); - -void CASPER_ecc_init(void); - -/*! - * @brief Performs ECC secp256r1 point single scalar multiplication - * - * This function performs ECC secp256r1 point single scalar multiplication - * [resX; resY] = scalar * [X; Y] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate in normal form, little endian. - * @param[out] resY Output Y affine coordinate in normal form, little endian. - * @param X Input X affine coordinate in normal form, little endian. - * @param Y Input Y affine coordinate in normal form, little endian. - * @param scalar Input scalar integer, in normal form, little endian. - */ -void CASPER_ECC_SECP256R1_Mul( - CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]); - -/*! - * @brief Performs ECC secp256r1 point double scalar multiplication - * - * This function performs ECC secp256r1 point double scalar multiplication - * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate. - * @param[out] resY Output Y affine coordinate. - * @param X1 Input X1 affine coordinate. - * @param Y1 Input Y1 affine coordinate. - * @param scalar1 Input scalar1 integer. - * @param X2 Input X2 affine coordinate. - * @param Y2 Input Y2 affine coordinate. - * @param scalar2 Input scalar2 integer. - */ -void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base, - uint32_t resX[8], - uint32_t resY[8], - uint32_t X1[8], - uint32_t Y1[8], - uint32_t scalar1[8], - uint32_t X2[8], - uint32_t Y2[8], - uint32_t scalar2[8]); - -/*! - * @brief Performs ECC secp384r1 point single scalar multiplication - * - * This function performs ECC secp384r1 point single scalar multiplication - * [resX; resY] = scalar * [X; Y] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate in normal form, little endian. - * @param[out] resY Output Y affine coordinate in normal form, little endian. - * @param X Input X affine coordinate in normal form, little endian. - * @param Y Input Y affine coordinate in normal form, little endian. - * @param scalar Input scalar integer, in normal form, little endian. - */ -void CASPER_ECC_SECP384R1_Mul( - CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]); - -/*! - * @brief Performs ECC secp384r1 point double scalar multiplication - * - * This function performs ECC secp384r1 point double scalar multiplication - * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] - * Coordinates are affine in normal form, little endian. - * Scalars are little endian. - * All arrays are little endian byte arrays, uint32_t type is used - * only to enforce the 32-bit alignment (0-mod-4 address). - * - * @param base CASPER base address - * @param[out] resX Output X affine coordinate. - * @param[out] resY Output Y affine coordinate. - * @param X1 Input X1 affine coordinate. - * @param Y1 Input Y1 affine coordinate. - * @param scalar1 Input scalar1 integer. - * @param X2 Input X2 affine coordinate. - * @param Y2 Input Y2 affine coordinate. - * @param scalar2 Input scalar2 integer. - */ -void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, - uint32_t resX[12], - uint32_t resY[12], - uint32_t X1[12], - uint32_t Y1[12], - uint32_t scalar1[12], - uint32_t X2[12], - uint32_t Y2[12], - uint32_t scalar2[12]); - -void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2); -void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1); - -/*! - *@} - */ /* end of casper_driver_pkha */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_CASPER_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_clock.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_clock.c deleted file mode 100644 index 4ce8075fb9..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_clock.c +++ /dev/null @@ -1,1988 +0,0 @@ -/* - * Copyright (c) 2017 - 2018 , NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_clock.h" -#include "fsl_power.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.clock" -#endif -#define NVALMAX (0x100U) -#define PVALMAX (0x20U) -#define MVALMAX (0x10000U) - -#define PLL_MAX_N_DIV 0x100U - -/*-------------------------------------------------------------------------- -!!! If required these #defines can be moved to chip library file -----------------------------------------------------------------------------*/ - -#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 16 downto 0 */ -#define PLL_SSCG1_MDEC_VAL_M (0x3FFFC00ULL << PLL_SSCG1_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */ -#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ -#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P) -#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ -#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P) - -#define PLL_MIN_CCO_FREQ_MHZ (275000000U) -#define PLL_MAX_CCO_FREQ_MHZ (550000000U) -#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */ -#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */ -#define PLL_MIN_IN_SSMODE (3000000U) -#define PLL_MAX_IN_SSMODE (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */ - -/* PLL NDEC reg */ -#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) -/* PLL PDEC reg */ -#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) -/* SSCG control0 */ -#define PLL_SSCG1_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M) - -/* PLL0 SSCG control1 */ -#define PLL0_SSCG_MD_FRACT_P 0U -#define PLL0_SSCG_MD_INT_P 25U -#define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) -#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P) - -#define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_FRACT_M) -#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M) - -/* Saved value of PLL output rate, computed whenever needed to save run-time - computation on each call to retrive the PLL rate. */ -static uint32_t s_Pll0_Freq; -static uint32_t s_Pll1_Freq; - -/** External clock rate on the CLKIN pin in Hz. If not used, - set this to 0. Otherwise, set it to the exact rate in Hz this pin is - being driven at. */ -static uint32_t s_Ext_Clk_Freq = 16000000U; -static uint32_t s_I2S_Mclk_Freq = 0U; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void); -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void); -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void); -/* Get multiplier (M) from PLL0 MDEC and SSCG settings */ -static float findPll0MMult(void); -/* Get the greatest common divisor */ -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); -/* Set PLL output based on desired output rate */ -static pll_error_t CLOCK_GetPll0Config( - uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); -/* Update local PLL rate variable */ -static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup); - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Clock Selection for IP */ -/** - * brief Configure the clock selection muxes. - * param connection : Clock to be configured. - * return Nothing - */ -void CLOCK_AttachClk(clock_attach_id_t connection) -{ - uint8_t mux; - uint8_t sel; - uint16_t item; - uint32_t i; - volatile uint32_t *pClkSel; - - pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); - - if (connection != kNONE_to_NONE) - { - for (i = 0U; i < 2U; i++) - { - if (connection == 0U) - { - break; - } - item = (uint16_t)GET_ID_ITEM(connection); - if (item) - { - mux = GET_ID_ITEM_MUX(item); - sel = GET_ID_ITEM_SEL(item); - if (mux == CM_RTCOSC32KCLKSEL) - { - PMC->RTCOSC32K |= sel; - } - else - { - pClkSel[mux] = sel; - } - } - connection = GET_ID_NEXT_ITEM(connection); /* pick up next descriptor */ - } - } -} - -/* Return the actual clock attach id */ -/** - * brief Get the actual clock attach id. - * This fuction uses the offset in input attach id, then it reads the actual source value in - * the register and combine the offset to obtain an actual attach id. - * param attachId : Clock attach id to get. - * return Clock source value. - */ -clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) -{ - uint8_t mux; - uint8_t actualSel; - uint32_t i; - uint32_t actualAttachId = 0U; - uint32_t selector = GET_ID_SELECTOR(attachId); - volatile uint32_t *pClkSel; - - pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); - - if (attachId == kNONE_to_NONE) - { - return kNONE_to_NONE; - } - - for (i = 0U; i < 2U; i++) - { - mux = GET_ID_ITEM_MUX(attachId); - if (attachId) - { - if (mux == CM_RTCOSC32KCLKSEL) - { - actualSel = PMC->RTCOSC32K; - } - else - { - actualSel = pClkSel[mux]; - } - - /* Consider the combination of two registers */ - actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); - } - attachId = GET_ID_NEXT_ITEM(attachId); /*!< pick up next descriptor */ - } - - actualAttachId |= selector; - - return (clock_attach_id_t)actualAttachId; -} - -/* Set IP Clock Divider */ -/** - * brief Setup peripheral clock dividers. - * param div_name : Clock divider name - * param divided_by_value: Value to be divided - * param reset : Whether to reset the divider counter. - * return Nothing - */ -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) -{ - volatile uint32_t *pClkDiv; - - pClkDiv = &(SYSCON->SYSTICKCLKDIV0); - if (reset) - { - pClkDiv[div_name] = 1U << 29U; - } - if (divided_by_value == 0U) /*!< halt */ - { - pClkDiv[div_name] = 1U << 30U; - } - else - { - pClkDiv[div_name] = (divided_by_value - 1U); - } -} - -/* Set RTC 1KHz Clock Divider */ -/** - * brief Setup rtc 1khz clock divider. - * param divided_by_value: Value to be divided - * return Nothing - */ -void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value) -{ - PMC->RTCOSC32K |= (((divided_by_value - 28U) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT) | PMC_RTCOSC32K_CLK1KHZDIV_MASK); -} - -/* Set RTC 1KHz Clock Divider */ -/** - * brief Setup rtc 1hz clock divider. - * param divided_by_value: Value to be divided - * return Nothing - */ -void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value) -{ - if (divided_by_value == 0U) /*!< halt */ - { - PMC->RTCOSC32K |= (1U << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT); - } - else - { - PMC->RTCOSC32K |= - (((divided_by_value - 31744U) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT) | PMC_RTCOSC32K_CLK1HZDIV_MASK); - } -} - -/* Set FRO Clocking */ -/** - * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). - * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is - * enabled. - * param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) - * return returns success or fail status. - */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq) -{ - if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U)) - { - return kStatus_Fail; - } - /* Enable Analog Control module */ - SYSCON->PRESETCTRLCLR[2] = (1U << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT); - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK; - /* Power up the FRO192M */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); - - if (iFreq == 96000000U) - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(1); - } - else if (iFreq == 48000000U) - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(1); - } - else - { - ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(1); - } - return 0U; -} - -/* Set the FLASH wait states for the passed frequency */ -/** - * brief Set the flash wait states for the input freuqency. - * param iFreq : Input frequency - * return Nothing - */ -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) -{ - uint32_t num_wait_states; - float f_num_wait_states = 0.00000009 * ((float)iFreq); - /* Rational : timing is closed at 100MHz+10% tolerance, hence the ¡®9¡¯ in the formula above */ - num_wait_states = (uint32_t)f_num_wait_states; - - /* - * It is guaranteed by design that "num_wait_states = 8" - * will fit all frequencies (below and including) 100 MHz. - */ - if (num_wait_states >= 9) - { - num_wait_states = 8; - } - - /* Don't alter other bits */ - SYSCON->FMCCR = (SYSCON->FMCCR & ~SYSCON_FMCCR_FMCTIM_MASK) | - ((num_wait_states << SYSCON_FMCCR_FMCTIM_SHIFT) & SYSCON_FMCCR_FMCTIM_MASK); -} - -/* Set EXT OSC Clk */ -/** - * brief Initialize the external osc clock to given frequency. - * param iFreq : Desired frequency (must be equal to exact rate in Hz) - * return returns success or fail status. - */ -status_t CLOCK_SetupExtClocking(uint32_t iFreq) -{ - if (iFreq >= 32000000U) - { - return kStatus_Fail; - } - /* Turn on power for crystal 32 MHz */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); - /* Enable clock_in clock for clock module. */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; - - s_Ext_Clk_Freq = iFreq; - return 0U; -} - -/* Set I2S MCLK Clk */ -/** - * brief Initialize the I2S MCLK clock to given frequency. - * param iFreq : Desired frequency (must be equal to exact rate in Hz) - * return returns success or fail status. - */ -status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq) -{ - s_I2S_Mclk_Freq = iFreq; - return 0U; -} - -/* Get CLOCK OUT Clk */ -/*! brief Return Frequency of ClockOut - * return Frequency of ClockOut - */ -uint32_t CLOCK_GetClockOutClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->CLKOUTSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - - case 2U: - freq = CLOCK_GetExtClkFreq(); - break; - - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - - case 5U: - freq = CLOCK_GetPll1OutFreq(); - break; - - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - - case 7U: - freq = 0U; - break; - - default: - break; - } - return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); -} - -/* Get ADC Clk */ -/*! brief Return Frequency of Adc Clock - * return Frequency of Adc. - */ -uint32_t CLOCK_GetAdcClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->ADCCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetFroHfFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - break; - } - - return freq / ((SYSCON->ADCCLKDIV & SYSCON_ADCCLKDIV_DIV_MASK) + 1U); -} - -/* Get USB0 Clk */ -/*! brief Return Frequency of Usb0 Clock - * return Frequency of Usb0 Clock. - */ -uint32_t CLOCK_GetUsb0ClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->USB0CLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 5U: - freq = CLOCK_GetPll1OutFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - break; - } - - return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U); -} - -/* Get USB1 Clk */ -/*! brief Return Frequency of Usb1 Clock - * return Frequency of Usb1 Clock. - */ -uint32_t CLOCK_GetUsb1ClkFreq(void) -{ - return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) ? s_Ext_Clk_Freq : 0U; -} - -/* Get MCLK Clk */ -/*! brief Return Frequency of MClk Clock - * return Frequency of MClk Clock. - */ -uint32_t CLOCK_GetMclkClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->MCLKCLKSEL) - { - case 0U: - freq = CLOCK_GetFroHfFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - break; - } - - return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U); -} - -/* Get SCTIMER Clk */ -/*! brief Return Frequency of SCTimer Clock - * return Frequency of SCTimer Clock. - */ -uint32_t CLOCK_GetSctClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->SCTCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetExtClkFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - break; - } - - return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U); -} - -/* Get SDIO Clk */ -/*! brief Return Frequency of SDIO Clock - * return Frequency of SDIO Clock. - */ -uint32_t CLOCK_GetSdioClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->SDIOCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 5U: - freq = CLOCK_GetPll1OutFreq(); - break; - case 7U: - freq = 0U; - break; - default: - break; - } - - return freq / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U); -} - -/* Get FRO 12M Clk */ -/*! brief Return Frequency of FRO 12MHz - * return Frequency of FRO 12MHz - */ -uint32_t CLOCK_GetFro12MFreq(void) -{ - return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ? - 0 : - (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U; -} - -/* Get FRO 1M Clk */ -/*! brief Return Frequency of FRO 1MHz - * return Frequency of FRO 1MHz - */ -uint32_t CLOCK_GetFro1MFreq(void) -{ - return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U; -} - -/* Get EXT OSC Clk */ -/*! brief Return Frequency of External Clock - * return Frequency of External Clock. If no external clock is used returns 0. - */ -uint32_t CLOCK_GetExtClkFreq(void) -{ - return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? s_Ext_Clk_Freq : 0U; -} - -/* Get WATCH DOG Clk */ -/*! brief Return Frequency of Watchdog - * return Frequency of Watchdog - */ -uint32_t CLOCK_GetWdtClkFreq(void) -{ - return CLOCK_GetFro1MFreq() / ((SYSCON->WDTCLKDIV & SYSCON_WDTCLKDIV_DIV_MASK) + 1U); -} - -/* Get HF FRO Clk */ -/*! brief Return Frequency of High-Freq output of FRO - * return Frequency of High-Freq output of FRO - */ -uint32_t CLOCK_GetFroHfFreq(void) -{ - return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ? - 0 : - (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U; -} - -/* Get SYSTEM PLL Clk */ -/*! brief Return Frequency of PLL - * return Frequency of PLL - */ -uint32_t CLOCK_GetPll0OutFreq(void) -{ - return s_Pll0_Freq; -} - -/* Get USB PLL Clk */ -/*! brief Return Frequency of USB PLL - * return Frequency of PLL - */ -uint32_t CLOCK_GetPll1OutFreq(void) -{ - return s_Pll1_Freq; -} - -/* Get RTC OSC Clk */ -/*! brief Return Frequency of 32kHz osc - * return Frequency of 32kHz osc - */ -uint32_t CLOCK_GetOsc32KFreq(void) -{ - return ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(0))) ? - CLK_RTC_32K_CLK : - ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(1))) ? - CLK_RTC_32K_CLK : - 0U; -} - -/* Get MAIN Clk */ -/*! brief Return Frequency of Core System - * return Frequency of Core System - */ -uint32_t CLOCK_GetCoreSysClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->MAINCLKSELB) - { - case 0U: - if (SYSCON->MAINCLKSELA == 0U) - { - freq = CLOCK_GetFro12MFreq(); - } - else if (SYSCON->MAINCLKSELA == 1U) - { - freq = CLOCK_GetExtClkFreq(); - } - else if (SYSCON->MAINCLKSELA == 2U) - { - freq = CLOCK_GetFro1MFreq(); - } - else if (SYSCON->MAINCLKSELA == 3U) - { - freq = CLOCK_GetFroHfFreq(); - } - else - { - } - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 2U: - freq = CLOCK_GetPll1OutFreq(); - break; - - case 3U: - freq = CLOCK_GetOsc32KFreq(); - break; - - default: - break; - } - - return freq; -} - -/* Get I2S MCLK Clk */ -/*! brief Return Frequency of I2S MCLK Clock - * return Frequency of I2S MCLK Clock - */ -uint32_t CLOCK_GetI2SMClkFreq(void) -{ - return s_I2S_Mclk_Freq; -} - -/* Get FLEXCOMM input clock */ -/*! brief Return Frequency of flexcomm input clock - * param id : flexcomm instance id - * return Frequency value - */ -uint32_t CLOCK_GetFlexCommInputClock(uint32_t id) -{ - uint32_t freq = 0U; - - switch (SYSCON->FCCLKSELX[id]) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); - break; - case 2U: - freq = CLOCK_GetFro12MFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - break; - } - - return freq; -} - -/* Get FLEXCOMM Clk */ -uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) -{ - uint32_t freq = 0U; - - freq = CLOCK_GetFlexCommInputClock(id); - return freq / (1 + - (SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK) / - ((SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK) + 1U)); -} - -/* Get HS_LPSI Clk */ -uint32_t CLOCK_GetHsLspiClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->HSLSPICLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); - break; - case 2U: - freq = CLOCK_GetFro12MFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - break; - } - - return freq; -} - -/* Get CTimer Clk */ -/*! brief Return Frequency of CTimer functional Clock - * return Frequency of CTimer functional Clock - */ -uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) -{ - uint32_t freq = 0U; - - switch (SYSCON->CTIMERCLKSELX[id]) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPll0OutFreq(); - break; - case 3U: - freq = CLOCK_GetFroHfFreq(); - break; - case 4U: - freq = CLOCK_GetFro1MFreq(); - break; - case 5U: - freq = CLOCK_GetI2SMClkFreq(); - break; - case 6U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - break; - } - - return freq; -} - -/* Get Systick Clk */ -/*! brief Return Frequency of SystickClock - * return Frequency of Systick Clock - */ -uint32_t CLOCK_GetSystickClkFreq(uint32_t id) -{ - volatile uint32_t *pSystickClkDiv; - pSystickClkDiv = &(SYSCON->SYSTICKCLKDIV0); - uint32_t freq = 0U; - - switch (SYSCON->SYSTICKCLKSELX[id]) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq() / ((pSystickClkDiv[id] & 0xffU) + 1U); - break; - case 1U: - freq = CLOCK_GetFro1MFreq(); - break; - case 2U: - freq = CLOCK_GetOsc32KFreq(); - break; - case 7U: - freq = 0U; - break; - - default: - break; - } - - return freq; -} - -/* Set FlexComm Clock */ -/** - * brief Set the flexcomm output frequency. - * param id : flexcomm instance id - * freq : output frequency - * return 0 : the frequency range is out of range. - * 1 : switch successfully. - */ -uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq) -{ - uint32_t input = CLOCK_GetFlexCommClkFreq(id); - uint32_t mul; - - if ((freq > 48000000) || (freq > input) || (input / freq >= 2)) - { - /* FRG output frequency should be less than equal to 48MHz */ - return 0; - } - else - { - mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq); - SYSCON->FLEXFRGXCTRL[id] = (mul << 8U) | 0xFFU; - return 1; - } -} - -/* Get IP Clk */ -/*! brief Return Frequency of selected clock - * return Frequency of selected clock - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName) -{ - uint32_t freq; - switch (clockName) - { - case kCLOCK_CoreSysClk: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case kCLOCK_BusClk: - freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); - break; - case kCLOCK_ClockOut: - freq = CLOCK_GetClockOutClkFreq(); - break; - case kCLOCK_Adc: - freq = CLOCK_GetAdcClkFreq(); - break; - case kCLOCK_Usb0: - freq = CLOCK_GetUsb0ClkFreq(); - break; - case kCLOCK_Usb1: - freq = CLOCK_GetUsb1ClkFreq(); - break; - case kCLOCK_Pll1Out: - freq = CLOCK_GetPll1OutFreq(); - break; - case kCLOCK_Mclk: - freq = CLOCK_GetMclkClkFreq(); - break; - case kCLOCK_FroHf: - freq = CLOCK_GetFroHfFreq(); - break; - case kCLOCK_Fro12M: - freq = CLOCK_GetFro12MFreq(); - break; - case kCLOCK_ExtClk: - freq = CLOCK_GetExtClkFreq(); - break; - case kCLOCK_Pll0Out: - freq = CLOCK_GetPll0OutFreq(); - break; - case kCLOCK_WdtClk: - freq = CLOCK_GetWdtClkFreq(); - break; - case kCLOCK_Sct: - freq = CLOCK_GetSctClkFreq(); - break; - case kCLOCK_SDio: - freq = CLOCK_GetSdioClkFreq(); - break; - case kCLOCK_FlexI2S: - freq = CLOCK_GetI2SMClkFreq(); - break; - case kCLOCK_Flexcomm0: - freq = CLOCK_GetFlexCommClkFreq(0U); - break; - case kCLOCK_Flexcomm1: - freq = CLOCK_GetFlexCommClkFreq(1U); - break; - case kCLOCK_Flexcomm2: - freq = CLOCK_GetFlexCommClkFreq(2U); - break; - case kCLOCK_Flexcomm3: - freq = CLOCK_GetFlexCommClkFreq(3U); - break; - case kCLOCK_Flexcomm4: - freq = CLOCK_GetFlexCommClkFreq(4U); - break; - case kCLOCK_Flexcomm5: - freq = CLOCK_GetFlexCommClkFreq(5U); - break; - case kCLOCK_Flexcomm6: - freq = CLOCK_GetFlexCommClkFreq(6U); - break; - case kCLOCK_Flexcomm7: - freq = CLOCK_GetFlexCommClkFreq(7U); - break; - case kCLOCK_HsLspi: - freq = CLOCK_GetHsLspiClkFreq(); - break; - case kCLOCK_CTmier0: - freq = CLOCK_GetCTimerClkFreq(0U); - break; - case kCLOCK_CTmier1: - freq = CLOCK_GetCTimerClkFreq(1U); - break; - case kCLOCK_CTmier2: - freq = CLOCK_GetCTimerClkFreq(2U); - break; - case kCLOCK_CTmier3: - freq = CLOCK_GetCTimerClkFreq(3U); - break; - case kCLOCK_CTmier4: - freq = CLOCK_GetCTimerClkFreq(4U); - break; - case kCLOCK_Systick0: - freq = CLOCK_GetSystickClkFreq(0U); - break; - case kCLOCK_Systick1: - freq = CLOCK_GetSystickClkFreq(1U); - break; - default: - freq = 0U; - break; - } - return freq; -} - -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) -{ - uint32_t seli, selp; - /* bandwidth: compute selP from Multiplier */ - if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) - { - selp = (M >> 2U) + 1U; - if (selp >= 31U) - { - selp = 31U; - } - *pSelP = selp; - - if (M >= 32768) - { - seli = 1; - } - else if (M >= 16384) - { - seli = 2; - } - else if (M >= 4096) - { - seli = 4; - } - else if (M >= 1002) - { - seli = 8; - } - else if (M >= 120) - { - seli = 4 * ((1024/(M/2 + 9)) + 1); - } - else - { - seli = 4 * (M/8 + 1); - } - - if (seli >= 63) - { - seli = 63; - } - *pSelI = seli; - - *pSelR = 0U; - } - else - { - *pSelP = 3U; - *pSelI = 4U; - *pSelR = 4U; - } -} - -/* Get predivider (N) from PLL0 NDEC setting */ -static uint32_t findPll0PreDiv(void) -{ - uint32_t preDiv = 1; - - /* Direct input is not used? */ - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0) - { - preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; - if (preDiv == 0) - { - preDiv = 1; - } - } - return preDiv; -} - -/* Get predivider (N) from PLL1 NDEC setting */ -static uint32_t findPll1PreDiv(void) -{ - uint32_t preDiv = 1; - - /* Direct input is not used? */ - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0) - { - preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; - if (preDiv == 0) - { - preDiv = 1; - } - } - return preDiv; -} - -/* Get postdivider (P) from PLL0 PDEC setting */ -static uint32_t findPll0PostDiv(void) -{ - uint32_t postDiv = 1; - - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0) - { - if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) - { - postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; - } - else - { - postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); - } - if (postDiv == 0) - { - postDiv = 2; - } - } - return postDiv; -} - -/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ -static float findPll0MMult(void) -{ - float mMult = 1; - float mMult_fract; - uint32_t mMult_int; - - if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) - { - mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT; - } - else - { - mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P); - mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M)/(1 << PLL0_SSCG_MD_INT_P)); - mMult = (float)mMult_int + mMult_fract; - } - if (mMult == 0) - { - mMult = 1; - } - return mMult; -} - - -/* Find greatest common divisor between m and n */ -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) -{ - uint32_t tmp; - - while (n != 0U) - { - tmp = n; - n = m % n; - m = tmp; - } - - return m; -} - -/* - * Set PLL0 output based on desired output rate. - * In this function, the it calculates the PLL0 setting for output frequency from input clock - * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. - * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. - */ -static pll_error_t CLOCK_GetPll0ConfigInternal( - uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) -{ - uint32_t nDivOutHz, fccoHz; - uint32_t pllPreDivider, pllMultiplier, pllPostDivider; - uint32_t pllDirectInput, pllDirectOutput; - uint32_t pllSelP, pllSelI, pllSelR, uplimoff; - - /* Baseline parameters (no input or output dividers) */ - pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ - pllPostDivider = 1U; /* 1 implies post-divider will be disabled */ - pllDirectOutput = 1U; - - /* Verify output rate parameter */ - if (foutHz > PLL_MAX_CCO_FREQ_MHZ) - { - /* Maximum PLL output with post divider=1 cannot go above this frequency */ - return kStatus_PLL_OutputTooHigh; - } - if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) - { - /* Minmum PLL output with maximum post divider cannot go below this frequency */ - return kStatus_PLL_OutputTooLow; - } - - /* If using SS mode, input clock needs to be between 3MHz and 20MHz */ - if (useSS) - { - /* Verify input rate parameter */ - if (finHz < PLL_MIN_IN_SSMODE) - { - /* Input clock into the PLL cannot be lower than this */ - return kStatus_PLL_InputTooLow; - } - /* PLL input in SS mode must be under 20MHz */ - if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX)) - { - return kStatus_PLL_InputTooHigh; - } - } - else - { - /* Verify input rate parameter */ - if (finHz < PLL_LOWER_IN_LIMIT) - { - /* Input clock into the PLL cannot be lower than this */ - return kStatus_PLL_InputTooLow; - } - if (finHz > PLL_HIGHER_IN_LIMIT) - { - /* Input clock into the PLL cannot be higher than this */ - return kStatus_PLL_InputTooHigh; - } - } - - /* Find the optimal CCO frequency for the output and input that - will keep it inside the PLL CCO range. This may require - tweaking the post-divider for the PLL. */ - fccoHz = foutHz; - while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) - { - /* CCO output is less than minimum CCO range, so the CCO output - needs to be bumped up and the post-divider is used to bring - the PLL output back down. */ - pllPostDivider++; - if (pllPostDivider > PVALMAX) - { - return kStatus_PLL_OutsideIntLimit; - } - - /* Target CCO goes up, PLL output goes down */ - /* divide-by-2 divider in the post-divider is always work*/ - fccoHz = foutHz * (pllPostDivider * 2U); - pllDirectOutput = 0U; - } - - /* Determine if a pre-divider is needed to get the best frequency */ - if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) - { - uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz); - - if (a > PLL_LOWER_IN_LIMIT) - { - a = finHz / a; - if ((a != 0U) && (a < PLL_MAX_N_DIV)) - { - pllPreDivider = a; - } - } - } - - /* Bypass pre-divider hardware if pre-divider is 1 */ - if (pllPreDivider > 1U) - { - pllDirectInput = 0U; - } - else - { - pllDirectInput = 1U; - } - - /* Determine PLL multipler */ - nDivOutHz = (finHz / pllPreDivider); - pllMultiplier = (fccoHz / nDivOutHz); - - /* Find optimal values for filter */ - if (useSS == false) - { - /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ - if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) - { - pllMultiplier++; - } - - /* Setup filtering */ - pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); - uplimoff = 0U; - - /* Get encoded value for M (mult) and use manual filter, disable SS mode */ - pSetup->pllsscg[1] = (PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1U << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT); - } - else - { - uint64_t fc; - - /* Filtering will be handled by SSC */ - pllSelR = pllSelI = pllSelP = 0U; - uplimoff = 1U; - - /* The PLL multiplier will get very close and slightly under the - desired target frequency. A small fractional component can be - added to fine tune the frequency upwards to the target. */ - fc = ((uint64_t)(fccoHz % nDivOutHz) << 25U) / nDivOutHz; - - /* Set multiplier */ - pSetup->pllsscg[0] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) | PLL0_SSCG_MD_FRACT_SET((uint32_t)fc)); - pSetup->pllsscg[1] = PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U; - } - - /* Get encoded values for N (prediv) and P (postdiv) */ - pSetup->pllndec = PLL_NDEC_VAL_SET(pllPreDivider); - pSetup->pllpdec = PLL_PDEC_VAL_SET(pllPostDivider); - - /* PLL control */ - pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */ - (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */ - (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */ - (0 << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */ - (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */ - (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */ - (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */ - (1 << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */ - - return kStatus_PLL_Success; -} - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) -/* Alloct the static buffer for cache. */ -static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; -static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; -static uint32_t s_PllSetupCacheIdx = 0U; -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - -/* - * Calculate the PLL setting values from input clock freq to output freq. - */ -static pll_error_t CLOCK_GetPll0Config( - uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) -{ - pll_error_t retErr; -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - uint32_t i; - - for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) - { - if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i])) - { - /* Hit the target in cache buffer. */ - pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl; - pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec; - pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec; - pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0]; - pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1]; - retErr = kStatus_PLL_Success; - break; - } - } - - if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - { - return retErr; - } -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - retErr = CLOCK_GetPll0ConfigInternal(finHz, foutHz, pSetup, useSS); - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - /* Cache the most recent calulation result into buffer. */ - s_FinHzCache[s_PllSetupCacheIdx] = finHz; - s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; - s_UseSSCache[s_PllSetupCacheIdx] = useSS; - - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0]; - s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1]; - /* Update the index for next available buffer. */ - s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - return retErr; -} - -/* Update local PLL rate variable */ -static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup) -{ - s_Pll0_Freq = CLOCK_GetPLL0OutFromSetup(pSetup); -} - -/* Return System PLL input clock rate */ -/*! brief Return PLL0 input clock rate -* return PLL0 input clock rate -*/ -uint32_t CLOCK_GetPLL0InClockRate(void) -{ - uint32_t clkRate = 0U; - - switch ((SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)) - { - case 0x00U: - clkRate = CLK_FRO_12MHZ; - break; - - case 0x01U: - clkRate = CLOCK_GetExtClkFreq(); - break; - - case 0x02U: - clkRate = CLOCK_GetFro1MFreq(); - break; - - case 0x03U: - clkRate = CLOCK_GetOsc32KFreq(); - break; - - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Return PLL1 input clock rate */ -uint32_t CLOCK_GetPLL1InClockRate(void) -{ - uint32_t clkRate = 0U; - - switch ((SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)) - { - case 0x00U: - clkRate = CLK_FRO_12MHZ; - break; - - case 0x01U: - clkRate = CLOCK_GetExtClkFreq(); - break; - - case 0x02U: - clkRate = CLOCK_GetFro1MFreq(); - break; - - case 0x03U: - clkRate = CLOCK_GetOsc32KFreq(); - break; - - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Return PLL0 output clock rate from setup structure */ -/*! brief Return PLL0 output clock rate from setup structure -* param pSetup : Pointer to a PLL setup structure -* return PLL0 output clock rate the setup structure will generate -*/ -uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup) -{ - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - float workRate = 0; - - /* Get the input clock frequency of PLL. */ - clkRate = CLOCK_GetPLL0InClockRate(); - - if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0)) - { - prediv = findPll0PreDiv(); - postdiv = findPll0PostDiv(); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* MDEC used for rate */ - workRate = (float)clkRate * (float)findPll0MMult(); - clkRate = (uint32_t)(workRate / ((float)postdiv)); - } - - return (uint32_t)workRate; -} - -/* Set the current PLL0 Rate */ -/*! brief Store the current PLL rate -* param rate: Current rate of the PLL -* return Nothing -**/ -void CLOCK_SetStoredPLL0ClockRate(uint32_t rate) -{ - s_Pll0_Freq = rate; -} - -/* Return PLL0 output clock rate */ -/*! brief Return PLL0 output clock rate -* param recompute : Forces a PLL rate recomputation if true -* return PLL0 output clock rate -* note The PLL rate is cached in the driver in a variable as -* the rate computation function can take some time to perform. It -* is recommended to use 'false' with the 'recompute' parameter. -*/ -uint32_t CLOCK_GetPLL0OutClockRate(bool recompute) -{ - pll_setup_t Setup; - uint32_t rate; - - if ((recompute) || (s_Pll0_Freq == 0U)) - { - Setup.pllctrl = SYSCON->PLL0CTRL; - Setup.pllndec = SYSCON->PLL0NDEC; - Setup.pllpdec = SYSCON->PLL0PDEC; - Setup.pllsscg[0] = SYSCON->PLL0SSCG0; - Setup.pllsscg[1] = SYSCON->PLL0SSCG1; - - CLOCK_GetPLL0OutFromSetupUpdate(&Setup); - } - - rate = s_Pll0_Freq; - - return rate; -} - -/* Set PLL0 output based on the passed PLL setup data */ -/*! brief Set PLL output based on the passed PLL setup data -* param pControl : Pointer to populated PLL control structure to generate setup with -* param pSetup : Pointer to PLL setup structure to be filled -* return PLL_ERROR_SUCCESS on success, or PLL setup error code -* note Actual frequency for setup may vary from the desired frequency based on the -* accuracy of input clocks, rounding, non-fractional PLL mode, etc. -*/ -pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup) -{ - uint32_t inRate; - bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U); - - pll_error_t pllError; - - /* Determine input rate for the PLL */ - if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U) - { - inRate = pControl->inputRate; - } - else - { - inRate = CLOCK_GetPLL0InClockRate(); - } - - /* PLL flag options */ - pllError = CLOCK_GetPll0Config(inRate, pControl->desiredRate, pSetup, useSS); - if ((useSS) && (pllError == kStatus_PLL_Success)) - { - /* If using SS mode, then some tweaks are made to the generated setup */ - pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; - if (pControl->mfDither) - { - pSetup->pllsscg[1] |= (1U << SYSCON_PLL0SSCG1_DITHER_SHIFT); - } - } - - return pllError; -} - -/* Set PLL0 output from PLL setup structure */ -/*! brief Set PLL output from PLL setup structure (precise frequency) -* param pSetup : Pointer to populated PLL setup structure -* param flagcfg : Flag configuration for PLL config structure -* return PLL_ERROR_SUCCESS on success, or PLL setup error code -* note This function will power off the PLL, setup the PLL with the -* new setup data, and then optionally powerup the PLL, wait for PLL lock, -* and adjust system voltages to the new PLL rate. The function will not -* alter any source clocks (ie, main systen clock) that may use the PLL, -* so these should be setup prior to and after exiting the function. -*/ -pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg) -{ - uint32_t inRate, clkRate, prediv; - - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL0); - POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); - - pSetup->flags = flagcfg; - - /* Write PLL setup data */ - SYSCON->PLL0CTRL = pSetup->pllctrl; - SYSCON->PLL0NDEC = pSetup->pllndec; - SYSCON->PLL0NDEC = pSetup->pllndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL0PDEC = pSetup->pllpdec; - SYSCON->PLL0PDEC = pSetup->pllpdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; - SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; - SYSCON->PLL0SSCG1 = - pSetup->pllsscg[1] | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1U << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL0); - POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) - { - inRate = CLOCK_GetPLL0InClockRate(); - prediv = findPll0PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000) && (clkRate <= 20000000)) - { - while (CLOCK_IsPLL0Locked() == false) - { - } - } - } - - /* Update current programmed PLL rate var */ - CLOCK_GetPLL0OutFromSetupUpdate(pSetup); - - /* System voltage adjustment, occurs prior to setting main system clock */ - if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U) - { - POWER_SetVoltageForFreq(s_Pll0_Freq); - } - - return kStatus_PLL_Success; -} - -/* Setup PLL Frequency from pre-calculated value */ -/** -* brief Set PLL0 output from PLL setup structure (precise frequency) -* param pSetup : Pointer to populated PLL setup structure -* return kStatus_PLL_Success on success, or PLL setup error code -* note This function will power off the PLL, setup the PLL with the -* new setup data, and then optionally powerup the PLL, wait for PLL lock, -* and adjust system voltages to the new PLL rate. The function will not -* alter any source clocks (ie, main systen clock) that may use the PLL, -* so these should be setup prior to and after exiting the function. -*/ -pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup) -{ - uint32_t inRate, clkRate, prediv; - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL0); - POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); - - /* Write PLL setup data */ - SYSCON->PLL0CTRL = pSetup->pllctrl; - SYSCON->PLL0NDEC = pSetup->pllndec; - SYSCON->PLL0NDEC = pSetup->pllndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL0PDEC = pSetup->pllpdec; - SYSCON->PLL0PDEC = pSetup->pllpdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; - SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; - SYSCON->PLL0SSCG1 = - pSetup->pllsscg[1] | (1U << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL0); - POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) - { - inRate = CLOCK_GetPLL0InClockRate(); - prediv = findPll0PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000) && (clkRate <= 20000000)) - { - while (CLOCK_IsPLL0Locked() == false) - { - } - } - } - - /* Update current programmed PLL rate var */ - s_Pll0_Freq = pSetup->pllRate; - - return kStatus_PLL_Success; -} - -/* Setup PLL1 Frequency from pre-calculated value */ -/** -* brief Set PLL1 output from PLL setup structure (precise frequency) -* param pSetup : Pointer to populated PLL setup structure -* return kStatus_PLL_Success on success, or PLL setup error code -* note This function will power off the PLL, setup the PLL with the -* new setup data, and then optionally powerup the PLL, wait for PLL lock, -* and adjust system voltages to the new PLL rate. The function will not -* alter any source clocks (ie, main systen clock) that may use the PLL, -* so these should be setup prior to and after exiting the function. -*/ -pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) -{ - uint32_t inRate, clkRate, prediv; - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_PLL1); - - /* Write PLL setup data */ - SYSCON->PLL1CTRL = pSetup->pllctrl; - SYSCON->PLL1NDEC = pSetup->pllndec; - SYSCON->PLL1NDEC = pSetup->pllndec | (1U << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */ - SYSCON->PLL1PDEC = pSetup->pllpdec; - SYSCON->PLL1PDEC = pSetup->pllpdec | (1U << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */ - SYSCON->PLL1MDEC = pSetup->pllmdec; - SYSCON->PLL1MDEC = pSetup->pllmdec | (1U << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */ - - POWER_DisablePD(kPDRUNCFG_PD_PLL1); - - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) - { - inRate = CLOCK_GetPLL1InClockRate(); - prediv = findPll1PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000) && (clkRate <= 20000000)) - { - while (CLOCK_IsPLL1Locked() == false) - { - } - } - } - - /* Update current programmed PLL rate var */ - s_Pll0_Freq = pSetup->pllRate; - - return kStatus_PLL_Success; -} - -/* Set PLL0 clock based on the input frequency and multiplier */ -/*! brief Set PLL0 output based on the multiplier and input frequency -* param multiply_by : multiplier -* param input_freq : Clock input frequency of the PLL -* return Nothing -* note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this -* function does not disable or enable PLL power, wait for PLL lock, -* or adjust system voltages. These must be done in the application. -* The function will not alter any source clocks (ie, main systen clock) -* that may use the PLL, so these should be setup prior to and after -* exiting the function. -*/ -void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq) -{ - uint32_t cco_freq = input_freq * multiply_by; - uint32_t pdec = 1U; - uint32_t selr; - uint32_t seli; - uint32_t selp; - uint32_t mdec, ndec; - - while (cco_freq < 275000000U) - { - multiply_by <<= 1U; /* double value in each iteration */ - pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ - cco_freq = input_freq * multiply_by; - } - - selr = 0U; - - if (multiply_by >= 32768) - { - seli = 1; - } - else if (multiply_by >= 16384) - { - seli = 2; - } - else if (multiply_by >= 4096) - { - seli = 4; - } - else if (multiply_by >= 1002) - { - seli = 8; - } - else if (multiply_by >= 120) - { - seli = 4 * ((1024/(multiply_by/2 + 9)) + 1); - } - else - { - seli = 4 * (multiply_by/8 + 1); - } - - if (seli >= 63U) - { - seli = 63U; - } - selp = (multiply_by >> 2U) + 1U; - { - selp = 31U; - } - - if (pdec > 1U) - { - pdec = pdec / 2U; /* Account for minus 1 encoding */ - /* Translate P value */ - } - - mdec = PLL_SSCG1_MDEC_VAL_SET(multiply_by); - ndec = 0x1U; /* pre divide by 1 (hardcoded) */ - - SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK |SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) | SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) | - (selr << SYSCON_PLL0CTRL_SELR_SHIFT) | (seli << SYSCON_PLL0CTRL_SELI_SHIFT) | - (selp << SYSCON_PLL0CTRL_SELP_SHIFT); - SYSCON->PLL0PDEC = pdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */ - SYSCON->PLL0NDEC = ndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */ - SYSCON->PLL0SSCG1 = mdec | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */ -} - -/* Enable USB DEVICE FULL SPEED clock */ -/*! brief Enable USB Device FS clock. -* param src : clock source -* param freq: clock frequency -* Enable USB Device Full Speed clock. -*/ -bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq) -{ - bool ret = true; - - CLOCK_DisableClock(kCLOCK_Usbd0); - - if (kCLOCK_UsbfsSrcFro == src) - { - switch (freq) - { - case 96000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ - break; - - default: - ret = false; - break; - } - /* Turn ON FRO HF */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); - /* Enable FRO 96MHz output */ - ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; - /* Select FRO 96 or 48 MHz */ - CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); - } - else - { - /*Set the USB PLL as the Usb0 CLK*/ - POWER_DisablePD(kPDRUNCFG_PD_PLL1); - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /*!< Ensure XTAL32K is on */ - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /*!< Ensure XTAL32K is on */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /*!< Ensure CLK_IN is on */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; - - CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL0 clock source selector to XTAL16M */ - - const pll_setup_t pll1Setup = { - .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(16U) | SYSCON_PLL1CTRL_SELP(7U), - .pllndec = SYSCON_PLL1NDEC_NDIV(1U), - .pllpdec = SYSCON_PLL1PDEC_PDIV(4U), - .pllmdec = SYSCON_PLL1MDEC_MDIV(24U), - .pllRate = 48000000U, - .flags = PLL_SETUPFLAG_WAITLOCK, - }; - - CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ - - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); - CLOCK_AttachClk(kPLL1_to_USB0_CLK); - uint32_t delay = 100000; - while (delay--) - { - __asm("nop"); - } - } - CLOCK_EnableClock(kCLOCK_Usbd0); - CLOCK_EnableClock(kCLOCK_UsbRam1); - - return ret; -} - -/* Enable USB HOST FULL SPEED clock */ -/*! brief Enable USB HOST FS clock. -* param src : clock source -* param freq: clock frequency -* Enable USB HOST Full Speed clock. -*/ -bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq) -{ - bool ret = true; - - CLOCK_DisableClock(kCLOCK_Usbhmr0); - CLOCK_DisableClock(kCLOCK_Usbhsl0); - - if (kCLOCK_UsbfsSrcFro == src) - { - switch (freq) - { - case 96000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ - break; - - default: - ret = false; - break; - } - /* Turn ON FRO HF */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); - /* Enable FRO 96MHz output */ - ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; - /* Select FRO 96 MHz */ - CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); - } - else - { - /*Set the USB PLL as the Usb0 CLK*/ - POWER_DisablePD(kPDRUNCFG_PD_PLL1); - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /*!< Ensure XTAL32K is on */ - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /*!< Ensure XTAL32K is on */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /*!< Ensure CLK_IN is on */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; - - CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL0 clock source selector to XTAL16M */ - - const pll_setup_t pll1Setup = { - .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(16U) | SYSCON_PLL1CTRL_SELP(7U), - .pllndec = SYSCON_PLL1NDEC_NDIV(1U), - .pllpdec = SYSCON_PLL1PDEC_PDIV(4U), - .pllmdec = SYSCON_PLL1MDEC_MDIV(24U), - .pllRate = 48000000U, - .flags = PLL_SETUPFLAG_WAITLOCK, - }; - - CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ - - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); - CLOCK_AttachClk(kPLL1_to_USB0_CLK); - uint32_t delay = 100000; - while (delay--) - { - __asm("nop"); - } - } - CLOCK_EnableClock(kCLOCK_Usbhmr0); - CLOCK_EnableClock(kCLOCK_Usbhsl0); - CLOCK_EnableClock(kCLOCK_UsbRam1); - - return ret; -} - -/* Enable USB PHY clock */ -bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) -{ - volatile uint32_t i; - - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); - POWER_DisablePD(kPDRUNCFG_PD_FRO32K); /*!< Ensure FRO32k is on */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32K); /*!< Ensure xtal32k is on */ - POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /*!< Ensure xtal32k is on */ - POWER_DisablePD(kPDRUNCFG_PD_LDOUSBHS); /*!< Ensure xtal32k is on */ - - /* wait to make sure PHY power is fully up */ - i = 100000; - while (i--) - { - __asm("nop"); - } - - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL(1); - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_PHY(1); - - USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; - USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | USBPHY_PLL_SIC_PLL_DIV_SEL(0x06); - USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK; - USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK; - USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK; - USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK; - USBPHY->PLL_SIC_SET = - USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK; /* enables auto power down of PHY PLL during suspend */ - - USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; - USBPHY->PWD_SET = 0x0; - - return true; -} - -/* Enable USB DEVICE HIGH SPEED clock */ -bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq) -{ - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_DEV(1); - - /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); - return true; -} - -/* Enable USB HOST HIGH SPEED clock */ -bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq) -{ - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); - SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_HOST(1); - - /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); - - return true; -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_clock.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_clock.h deleted file mode 100644 index d709c5aaac..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_clock.h +++ /dev/null @@ -1,1288 +0,0 @@ -/* - * Copyright (c) 2017 - 2018 , NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CLOCK_H_ -#define _FSL_CLOCK_H_ - -#include "fsl_device_registers.h" -#include -#include -#include - -/*! @addtogroup clock */ -/*! @{ */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CLOCK driver version 2.0.3. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -/*! @brief Configure whether driver controls clock - * - * When set to 0, peripheral drivers will enable clock in initialize function - * and disable clock in de-initialize function. When set to 1, peripheral - * driver will not control the clock, application could control the clock out of - * the driver. - * - * @note All drivers share this feature switcher. If it is set to 1, application - * should handle clock enable and disable for all drivers. - */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) -#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 -#endif - -/*! - * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. - * - * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function - * would cache the recent calulation and accelerate the execution to get the - * right settings. - */ -#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT -#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U -#endif - -/*! @brief Clock ip name array for ROM. */ -#define ROM_CLOCKS \ - { \ - kCLOCK_Rom \ - } -/*! @brief Clock ip name array for SRAM. */ -#define SRAM_CLOCKS \ - { \ - kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4 \ - } -/*! @brief Clock ip name array for FLASH. */ -#define FLASH_CLOCKS \ - { \ - kCLOCK_Flash \ - } -/*! @brief Clock ip name array for FMC. */ -#define FMC_CLOCKS \ - { \ - kCLOCK_Fmc \ - } -/*! @brief Clock ip name array for INPUTMUX. */ -#define INPUTMUX_CLOCKS \ - { \ - kCLOCK_InputMux0, kCLOCK_InputMux1 \ - } -/*! @brief Clock ip name array for IOCON. */ -#define IOCON_CLOCKS \ - { \ - kCLOCK_Iocon \ - } -/*! @brief Clock ip name array for GPIO. */ -#define GPIO_CLOCKS \ - { \ - kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ - } -/*! @brief Clock ip name array for PINT. */ -#define PINT_CLOCKS \ - { \ - kCLOCK_Pint \ - } -/*! @brief Clock ip name array for GINT. */ -#define GINT_CLOCKS \ - { \ - kCLOCK_Gint, kCLOCK_Gint \ - } -/*! @brief Clock ip name array for DMA. */ -#define DMA_CLOCKS \ - { \ - kCLOCK_Dma0, kCLOCK_Dma1 \ - } -/*! @brief Clock ip name array for CRC. */ -#define CRC_CLOCKS \ - { \ - kCLOCK_Crc \ - } -/*! @brief Clock ip name array for WWDT. */ -#define WWDT_CLOCKS \ - { \ - kCLOCK_Wwdt \ - } -/*! @brief Clock ip name array for RTC. */ -#define RTC_CLOCKS \ - { \ - kCLOCK_Rtc \ - } -/*! @brief Clock ip name array for Mailbox. */ -#define MAILBOX_CLOCKS \ - { \ - kCLOCK_Mailbox \ - } -/*! @brief Clock ip name array for LPADC. */ -#define LPADC_CLOCKS \ - { \ - kCLOCK_Adc0 \ - } -/*! @brief Clock ip name array for MRT. */ -#define MRT_CLOCKS \ - { \ - kCLOCK_Mrt \ - } -/*! @brief Clock ip name array for OSTIMER. */ -#define OSTIMER_CLOCKS \ - { \ - kCLOCK_OsTimer0 \ - } -/*! @brief Clock ip name array for SCT0. */ -#define SCT_CLOCKS \ - { \ - kCLOCK_Sct0 \ - } -/*! @brief Clock ip name array for SCTIPU. */ -#define SCTIPU_CLOCKS \ - { \ - kCLOCK_Sctipu \ - } -/*! @brief Clock ip name array for UTICK. */ -#define UTICK_CLOCKS \ - { \ - kCLOCK_Utick0 \ - } -/*! @brief Clock ip name array for FLEXCOMM. */ -#define FLEXCOMM_CLOCKS \ - { \ - kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ - kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \ - } -/*! @brief Clock ip name array for LPUART. */ -#define LPUART_CLOCKS \ - { \ - kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ - kCLOCK_MinUart6, kCLOCK_MinUart7 \ - } - -/*! @brief Clock ip name array for BI2C. */ -#define BI2C_CLOCKS \ - { \ - kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \ - } -/*! @brief Clock ip name array for LSPI. */ -#define LPSPI_CLOCKS \ - { \ - kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \ - } -/*! @brief Clock ip name array for FLEXI2S. */ -#define FLEXI2S_CLOCKS \ - { \ - kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ - kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \ - } -/*! @brief Clock ip name array for USBTYPC. */ -#define USBTYPC_CLOCKS \ - { \ - kCLOCK_UsbTypc \ - } -/*! @brief Clock ip name array for CTIMER. */ -#define CTIMER_CLOCKS \ - { \ - kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ - } -/*! @brief Clock ip name array for PVT */ -#define PVT_CLOCKS \ - { \ - kCLOCK_Pvt \ - } -/*! @brief Clock ip name array for EZHA */ -#define EZHA_CLOCKS \ - { \ - kCLOCK_Ezha \ - } -/*! @brief Clock ip name array for EZHB */ -#define EZHB_CLOCKS \ - { \ - kCLOCK_Ezhb \ - } -/*! @brief Clock ip name array for COMP */ -#define COMP_CLOCKS \ - { \ - kCLOCK_Comp \ - } -/*! @brief Clock ip name array for SDIO. */ -#define SDIO_CLOCKS \ - { \ - kCLOCK_Sdio \ - } -/*! @brief Clock ip name array for USB1CLK. */ -#define USB1CLK_CLOCKS \ - { \ - kCLOCK_Usb1Clk \ - } -/*! @brief Clock ip name array for FREQME. */ -#define FREQME_CLOCKS \ - { \ - kCLOCK_Freqme \ - } -/*! @brief Clock ip name array for USBRAM. */ -#define USBRAM_CLOCKS \ - { \ - kCLOCK_UsbRam1 \ - } -/*! @brief Clock ip name array for OTP. */ -#define OTP_CLOCKS \ - { \ - kCLOCK_Otp \ - } -/*! @brief Clock ip name array for RNG. */ -#define RNG_CLOCKS \ - { \ - kCLOCK_Rng \ - } -/*! @brief Clock ip name array for USBHMR0. */ -#define USBHMR0_CLOCKS \ - { \ - kCLOCK_Usbhmr0 \ - } -/*! @brief Clock ip name array for USBHSL0. */ -#define USBHSL0_CLOCKS \ - { \ - kCLOCK_Usbhsl0 \ - } -/*! @brief Clock ip name array for HashCrypt. */ -#define HASHCRYPT_CLOCKS \ - { \ - kCLOCK_HashCrypt \ - } -/*! @brief Clock ip name array for PowerQuad. */ -#define POWERQUAD_CLOCKS \ - { \ - kCLOCK_PowerQuad \ - } -/*! @brief Clock ip name array for PLULUT. */ -#define PLULUT_CLOCKS \ - { \ - kCLOCK_PluLut \ - } -/*! @brief Clock ip name array for PUF. */ -#define PUF_CLOCKS \ - { \ - kCLOCK_Puf \ - } -/*! @brief Clock ip name array for CASPER. */ -#define CASPER_CLOCKS \ - { \ - kCLOCK_Casper \ - } -/*! @brief Clock ip name array for ANALOGCTRL. */ -#define ANALOGCTRL_CLOCKS \ - { \ - kCLOCK_AnalogCtrl \ - } -/*! @brief Clock ip name array for HS_LSPI. */ -#define HS_LSPI_CLOCKS \ - { \ - kCLOCK_Hs_Lspi \ - } -/*! @brief Clock ip name array for GPIO_SEC. */ -#define GPIO_SEC_CLOCKS \ - { \ - kCLOCK_Gpio_Sec \ - } -/*! @brief Clock ip name array for GPIO_SEC_INT. */ -#define GPIO_SEC_INT_CLOCKS \ - { \ - kCLOCK_Gpio_Sec_Int \ - } -/*! @brief Clock ip name array for USBD. */ -#define USBD_CLOCKS \ - { \ - kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \ - } -/*! @brief Clock ip name array for USBH. */ -#define USBH_CLOCKS \ - { \ - kCLOCK_Usbh1 \ - } -#define PLU_CLOCKS \ - { \ - kCLOCK_PluLut \ - } -#define SYSCTL_CLOCKS \ - { \ - kCLOCK_Sysctl \ - } -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -/*------------------------------------------------------------------------------ - clock_ip_name_t definition: -------------------------------------------------------------------------------*/ - -#define CLK_GATE_REG_OFFSET_SHIFT 8U -#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U -#define CLK_GATE_BIT_SHIFT_SHIFT 0U -#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU - -#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ - ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ - (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) - -#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) -#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) - -#define AHB_CLK_CTRL0 0 -#define AHB_CLK_CTRL1 1 -#define AHB_CLK_CTRL2 2 - -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -typedef enum _clock_ip_name -{ - kCLOCK_IpInvalid = 0U, - kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), - kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), - kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), - kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), - kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), - kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), - kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), - kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), - kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), - kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), - kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), - kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), - kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), - kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), - kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), - kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), - kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), - kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), - kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), - kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), - kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), - kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), - kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), - kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), - kCLOCK_Sctipu = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6), - kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), - kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_UsbTypc = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 20), - kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), - kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), - kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), - kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), - kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), - kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30), - kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), - kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), - kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), - kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), - kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), - kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), - kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), - kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), - kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), - kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9), - kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10), - kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12), - kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), - kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), - kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), - kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), - kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), - kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), - kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), - kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), - kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), - kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), - kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), - kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), - kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27), - kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28), - kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), - kCLOCK_Gpio_sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30) -} clock_ip_name_t; - -/*! @brief Peripherals clock source definition. */ -#define BUS_CLK kCLOCK_BusClk - -#define I2C0_CLK_SRC BUS_CLK - -/*! @brief Clock name used to get clock frequency. */ -typedef enum _clock_name -{ - kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ - kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ - kCLOCK_ClockOut, /*!< CLOCKOUT */ - kCLOCK_FroHf, /*!< FRO48/96 */ - kCLOCK_Adc, /*!< ADC */ - kCLOCK_Usb0, /*!< USB0 */ - kCLOCK_Usb1, /*!< USB1 */ - kCLOCK_Pll1Out, /*!< PLL1 Output */ - kCLOCK_Mclk, /*!< MCLK */ - kCLOCK_Sct, /*!< SCT */ - kCLOCK_SDio, /*!< SDIO */ - kCLOCK_Fro12M, /*!< FRO12M */ - kCLOCK_ExtClk, /*!< External Clock */ - kCLOCK_Pll0Out, /*!< PLL0 Output */ - kCLOCK_WdtClk, /*!< Watchdog clock */ - kCLOCK_FlexI2S, /*!< FlexI2S clock */ - kCLOCK_Flexcomm0, /*!< Flexcomm0Clock */ - kCLOCK_Flexcomm1, /*!< Flexcomm1Clock */ - kCLOCK_Flexcomm2, /*!< Flexcomm2Clock */ - kCLOCK_Flexcomm3, /*!< Flexcomm3Clock */ - kCLOCK_Flexcomm4, /*!< Flexcomm4Clock */ - kCLOCK_Flexcomm5, /*!< Flexcomm5Clock */ - kCLOCK_Flexcomm6, /*!< Flexcomm6Clock */ - kCLOCK_Flexcomm7, /*!< Flexcomm7Clock */ - kCLOCK_HsLspi, /*!< HS LPSPI Clock */ - kCLOCK_CTmier0, /*!< CTmier0Clock */ - kCLOCK_CTmier1, /*!< CTmier1Clock */ - kCLOCK_CTmier2, /*!< CTmier2Clock */ - kCLOCK_CTmier3, /*!< CTmier3Clock */ - kCLOCK_CTmier4, /*!< CTmier4Clock */ - kCLOCK_Systick0, /*!< System Tick 0 Clock */ - kCLOCK_Systick1, /*!< System Tick 1 Clock */ - -} clock_name_t; - -/*! @brief Clock Mux Switches -* The encoding is as follows each connection identified is 32bits wide while 24bits are valuable -* starting from LSB upwards -* -* [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* -* -*/ - -#define CLK_ATTACH_ID(mux, sel, pos) (((mux << 0U) | ((sel + 1) & 0xFU) << 8U) << (pos * 12U)) -#define MUX_A(mux, sel) CLK_ATTACH_ID(mux, sel, 0U) -#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID(mux, sel, 1U) | (selector << 24U)) - -#define GET_ID_ITEM(connection) ((connection)&0xFFFU) -#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U) -#define GET_ID_ITEM_MUX(connection) ((connection)&0xFFU) -#define GET_ID_ITEM_SEL(connection) ((((connection)&0xF00U) >> 8U) - 1U) -#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) - -#define CM_SYSTICKCLKSEL0 0 -#define CM_SYSTICKCLKSEL1 1 -#define CM_TRACECLKSEL 2 -#define CM_CTIMERCLKSEL0 3 -#define CM_CTIMERCLKSEL1 4 -#define CM_CTIMERCLKSEL2 5 -#define CM_CTIMERCLKSEL3 6 -#define CM_CTIMERCLKSEL4 7 -#define CM_MAINCLKSELA 8 -#define CM_MAINCLKSELB 9 -#define CM_CLKOUTCLKSEL 10 -#define CM_PLL0CLKSEL 12 -#define CM_PLL1CLKSEL 13 -#define CM_ADCASYNCCLKSEL 17 -#define CM_USB0CLKSEL 18 -#define CM_FXCOMCLKSEL0 20 -#define CM_FXCOMCLKSEL1 21 -#define CM_FXCOMCLKSEL2 22 -#define CM_FXCOMCLKSEL3 23 -#define CM_FXCOMCLKSEL4 24 -#define CM_FXCOMCLKSEL5 25 -#define CM_FXCOMCLKSEL6 26 -#define CM_FXCOMCLKSEL7 27 -#define CM_HSLSPICLKSEL 28 -#define CM_MCLKCLKSEL 32 -#define CM_SCTCLKSEL 36 -#define CM_SDIOCLKSEL 38 - -#define CM_RTCOSC32KCLKSEL 63 - -typedef enum _clock_attach_id -{ - - kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), - kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), - kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), - kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), - kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), - kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), - kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), - - kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), - kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), - kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), - kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), - kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), - kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), - kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), - kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), - - kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), - kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), - kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), - kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), - kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), - - kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), - kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), - kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), - kFRO1M_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3), /* Need confirm */ - kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), - - kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), - kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), - kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3), - kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5), - kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), - - kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), - kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), - kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), - kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), - kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), - kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), - kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), - kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), - - kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), - kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), - kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), - kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), - kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), - kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), - kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), - kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), - - kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), - kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), - kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), - kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), - kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), - kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), - kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), - kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), - - kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), - kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), - kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), - kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), - kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), - kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), - kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), - kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), - - kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), - kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), - kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), - kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), - kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), - kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), - kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), - kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), - - kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), - kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), - kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), - kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), - kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), - kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), - kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), - kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), - - kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), - kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), - kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), - kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), - kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), - kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), - kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), - kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), - - kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), - kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), - kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), - kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), - kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), - kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), - kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), - kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), - - kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), - kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), - kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), - kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), - kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), - kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), - kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), - - kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), - kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), - kFRO1M_to_MCLK = MUX_A(CM_MCLKCLKSEL, 2), /* Need confirm */ - kMAIN_CLK_to_MCLK = MUX_A(CM_MCLKCLKSEL, 3), /* Need confirm */ - kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), - - kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), - kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), - kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), - kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), - kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5), - kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), - - kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), - kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), - kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), - kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5), - kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), - - kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), - kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), - - kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), - kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), - kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), - kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), - - kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), - kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), - kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), - kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), - - kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0), - kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1), - kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2), - kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7), - - kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), - kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), - kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), - kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), - kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), - - kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), - kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), - kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), - kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), - kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), - kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), - kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), - - kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), - kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), - kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), - kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), - kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), - kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), - kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), - - kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), - kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), - kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), - kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), - kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), - kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), - kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), - - kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), - kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), - kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), - kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), - kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), - kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), - kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), - - kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), - kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), - kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), - kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), - kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), - kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), - kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), - kNONE_to_NONE = (int)0x80000000U, -} clock_attach_id_t; - -/* Clock dividers */ -typedef enum _clock_div_name -{ - kCLOCK_DivSystickClk0 = 0, - kCLOCK_DivSystickClk1 = 1, - kCLOCK_DivArmTrClkDiv = 2, - kCLOCK_DivFlexFrg0 = 8, - kCLOCK_DivFlexFrg1 = 9, - kCLOCK_DivFlexFrg2 = 10, - kCLOCK_DivFlexFrg3 = 11, - kCLOCK_DivFlexFrg4 = 12, - kCLOCK_DivFlexFrg5 = 13, - kCLOCK_DivFlexFrg6 = 14, - kCLOCK_DivFlexFrg7 = 15, - kCLOCK_DivAhbClk = 32, - kCLOCK_DivClkOut = 33, - kCLOCK_DivFrohfClk = 34, - kCLOCK_DivWdtClk = 35, - kCLOCK_DivAdcAsyncClk = 37, - kCLOCK_DivUsb0Clk = 38, - kCLOCK_DivMClk = 43, - kCLOCK_DivSctClk = 45, - kCLOCK_DivSdioClk = 47, - kCLOCK_DivPll0Clk = 49 -} clock_div_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief Enable the clock for specific IP. - * @param name : Clock to be enabled. - * @return Nothing - */ -static inline void CLOCK_EnableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); -} -/** - * @brief Disable the clock for specific IP. - * @param name : Clock to be Disabled. - * @return Nothing - */ -static inline void CLOCK_DisableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); -} -/** - * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). - * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is - * enabled. - * @param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) - * @return returns success or fail status. - */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq); -/** - * @brief Set the flash wait states for the input freuqency. - * @param iFreq : Input frequency - * @return Nothing - */ -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq); -/** - * @brief Initialize the external osc clock to given frequency. - * @param iFreq : Desired frequency (must be equal to exact rate in Hz) - * @return returns success or fail status. - */ -status_t CLOCK_SetupExtClocking(uint32_t iFreq); -/** - * @brief Initialize the I2S MCLK clock to given frequency. - * @param iFreq : Desired frequency (must be equal to exact rate in Hz) - * @return returns success or fail status. - */ -status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq); -/** - * @brief Configure the clock selection muxes. - * @param connection : Clock to be configured. - * @return Nothing - */ -void CLOCK_AttachClk(clock_attach_id_t connection); -/** - * @brief Get the actual clock attach id. - * This fuction uses the offset in input attach id, then it reads the actual source value in - * the register and combine the offset to obtain an actual attach id. - * @param attachId : Clock attach id to get. - * @return Clock source value. - */ -clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); -/** - * @brief Setup peripheral clock dividers. - * @param div_name : Clock divider name - * @param divided_by_value: Value to be divided - * @param reset : Whether to reset the divider counter. - * @return Nothing - */ -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); -/** - * @brief Setup rtc 1khz clock divider. - * @param divided_by_value: Value to be divided - * @return Nothing - */ -void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value); -/** - * @brief Setup rtc 1hz clock divider. - * @param divided_by_value: Value to be divided - * @return Nothing - */ -void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value); - -/** - * @brief Set the flexcomm output frequency. - * @param id : flexcomm instance id - * freq : output frequency - * @return 0 : the frequency range is out of range. - * 1 : switch successfully. - */ -uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq); - -/*! @brief Return Frequency of flexcomm input clock - * @param id : flexcomm instance id - * @return Frequency value - */ -uint32_t CLOCK_GetFlexCommInputClock(uint32_t id); - -/*! @brief Return Frequency of selected clock - * @return Frequency of selected clock - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName); -/*! @brief Return Frequency of FRO 12MHz - * @return Frequency of FRO 12MHz - */ -uint32_t CLOCK_GetFro12MFreq(void); -/*! @brief Return Frequency of FRO 1MHz - * @return Frequency of FRO 1MHz - */ -uint32_t CLOCK_GetFro1MFreq(void); -/*! @brief Return Frequency of ClockOut - * @return Frequency of ClockOut - */ -uint32_t CLOCK_GetClockOutClkFreq(void); -/*! @brief Return Frequency of Adc Clock - * @return Frequency of Adc. - */ -uint32_t CLOCK_GetAdcClkFreq(void); -/*! @brief Return Frequency of Usb0 Clock - * @return Frequency of Usb0 Clock. - */ -uint32_t CLOCK_GetUsb0ClkFreq(void); -/*! @brief Return Frequency of Usb1 Clock - * @return Frequency of Usb1 Clock. - */ -uint32_t CLOCK_GetUsb1ClkFreq(void); -/*! @brief Return Frequency of MClk Clock - * @return Frequency of MClk Clock. - */ -uint32_t CLOCK_GetMclkClkFreq(void); -/*! @brief Return Frequency of SCTimer Clock - * @return Frequency of SCTimer Clock. - */ -uint32_t CLOCK_GetSctClkFreq(void); -/*! @brief Return Frequency of SDIO Clock - * @return Frequency of SDIO Clock. - */ -uint32_t CLOCK_GetSdioClkFreq(void); -/*! @brief Return Frequency of External Clock - * @return Frequency of External Clock. If no external clock is used returns 0. - */ -uint32_t CLOCK_GetExtClkFreq(void); -/*! @brief Return Frequency of Watchdog - * @return Frequency of Watchdog - */ -uint32_t CLOCK_GetWdtClkFreq(void); -/*! @brief Return Frequency of High-Freq output of FRO - * @return Frequency of High-Freq output of FRO - */ -uint32_t CLOCK_GetFroHfFreq(void); -/*! @brief Return Frequency of PLL - * @return Frequency of PLL - */ -uint32_t CLOCK_GetPll0OutFreq(void); -/*! @brief Return Frequency of USB PLL - * @return Frequency of PLL - */ -uint32_t CLOCK_GetPll1OutFreq(void); -/*! @brief Return Frequency of 32kHz osc - * @return Frequency of 32kHz osc - */ -uint32_t CLOCK_GetOsc32KFreq(void); -/*! @brief Return Frequency of Core System - * @return Frequency of Core System - */ -uint32_t CLOCK_GetCoreSysClkFreq(void); -/*! @brief Return Frequency of I2S MCLK Clock - * @return Frequency of I2S MCLK Clock - */ -uint32_t CLOCK_GetI2SMClkFreq(void); -/*! @brief Return Frequency of CTimer functional Clock - * @return Frequency of CTimer functional Clock - */ -uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); -/*! @brief Return Frequency of SystickClock - * @return Frequency of Systick Clock - */ -uint32_t CLOCK_GetSystickClkFreq(uint32_t id); - -/*! @brief Return PLL0 input clock rate -* @return PLL0 input clock rate -*/ -uint32_t CLOCK_GetPLL0InClockRate(void); - -/*! @brief Return PLL1 input clock rate -* @return PLL1 input clock rate -*/ -uint32_t CLOCK_GetPLL1InClockRate(void); - -/*! @brief Return PLL0 output clock rate -* @param recompute : Forces a PLL rate recomputation if true -* @return PLL0 output clock rate -* @note The PLL rate is cached in the driver in a variable as -* the rate computation function can take some time to perform. It -* is recommended to use 'false' with the 'recompute' parameter. -*/ -uint32_t CLOCK_GetPLL0OutClockRate(bool recompute); - -/*! @brief Return PLL1 output clock rate -* @param recompute : Forces a PLL rate recomputation if true -* @return PLL1 output clock rate -* @note The PLL rate is cached in the driver in a variable as -* the rate computation function can take some time to perform. It -* is recommended to use 'false' with the 'recompute' parameter. -*/ -uint32_t CLOCK_GetPLL1OutClockRate(bool recompute); - -/*! @brief Enables and disables PLL0 bypass mode -* @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass -* @return PLL0 output clock rate -*/ -__STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass) -{ - if (bypass) - { - SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); - } - else - { - SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); - } -} - -/*! @brief Enables and disables PLL1 bypass mode -* @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass -* @return PLL1 output clock rate -*/ -__STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass) -{ - if (bypass) - { - SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); - } - else - { - SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); - } -} - -/*! @brief Check if PLL is locked or not -* @return true if the PLL is locked, false if not locked -*/ -__STATIC_INLINE bool CLOCK_IsPLL0Locked(void) -{ - return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0); -} - -/*! @brief Check if PLL1 is locked or not - * @return true if the PLL1 is locked, false if not locked - */ -__STATIC_INLINE bool CLOCK_IsPLL1Locked(void) -{ - return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0); -} - -/*! @brief Store the current PLL0 rate -* @param rate: Current rate of the PLL0 -* @return Nothing -**/ -void CLOCK_SetStoredPLL0ClockRate(uint32_t rate); - -/*! @brief PLL configuration structure flags for 'flags' field -* These flags control how the PLL configuration function sets up the PLL setup structure.
-* -* When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the -* configuration structure must be assigned with the expected PLL frequency. If the -* PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration -* function and the driver will determine the PLL rate from the currently selected -* PLL source. This flag might be used to configure the PLL input clock more accurately -* when using the WDT oscillator or a more dyanmic CLKIN source.
-* -* When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the -* automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider -* are not used.
-*/ -#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */ -#define PLL_CONFIGFLAG_FORCENOFRACT (1 << 2) -/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ - -/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency - * See (MF) field in the PLL0SSCG1 register in the UM. - */ -typedef enum _ss_progmodfm -{ - kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */ - kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */ - kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */ - kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */ - kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ - kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ - kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ - kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */ -} ss_progmodfm_t; - -/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth - * See (MR) field in the PLL0SSCG1 register in the UM. - */ -typedef enum _ss_progmoddp -{ - kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ - kSS_MR_K1 = (1 << 23), /*!< k = 1 */ - kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */ - kSS_MR_K2 = (3 << 23), /*!< k = 2 */ - kSS_MR_K3 = (4 << 23), /*!< k = 3 */ - kSS_MR_K4 = (5 << 23), /*!< k = 4 */ - kSS_MR_K6 = (6 << 23), /*!< k = 6 */ - kSS_MR_K8 = (7 << 23) /*!< k = 8 */ -} ss_progmoddp_t; - -/*! @brief PLL Spread Spectrum (SS) Modulation waveform control - * See (MC) field in the PLL0SSCG1 register in the UM.
- * Compensation for low pass filtering of the PLL to get a triangular - * modulation at the output of the PLL, giving a flat frequency spectrum. - */ -typedef enum _ss_modwvctrl -{ - kSS_MC_NOC = (0 << 26), /*!< no compensation */ - kSS_MC_RECC = (2 << 26), /*!< recommended setting */ - kSS_MC_MAXC = (3 << 26), /*!< max. compensation */ -} ss_modwvctrl_t; - -/*! @brief PLL configuration structure -* -* This structure can be used to configure the settings for a PLL -* setup structure. Fill in the desired configuration for the PLL -* and call the PLL setup function to fill in a PLL setup structure. -*/ -typedef struct _pll_config -{ - uint32_t desiredRate; /*!< Desired PLL rate in Hz */ - uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ - uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ - ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - ss_modwvctrl_t - ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ - bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - -} pll_config_t; - -/*! @brief PLL setup structure flags for 'flags' field -* These flags control how the PLL setup function sets up the PLL -*/ -#define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */ -#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ -#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */ -#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1 << 3) /*!< Use feedback divider by 2 in divider path */ - -/*! @brief PLL0 setup structure -* This structure can be used to pre-build a PLL setup configuration -* at run-time and quickly set the PLL to the configuration. It can be -* populated with the PLL setup function. If powering up or waiting -* for PLL lock, the PLL input clock source should be configured prior -* to PLL setup. -*/ -typedef struct _pll_setup -{ - uint32_t pllctrl; /*!< PLL control register PLL0CTRL */ - uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */ - uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */ - uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */ - uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/ - uint32_t pllRate; /*!< Acutal PLL rate */ - uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ -} pll_setup_t; - -/*! @brief PLL status definitions -*/ -typedef enum _pll_error -{ - kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ - kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ - kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ - kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ - kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ - kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */ - kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */ - kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */ -} pll_error_t; - -/*! @brief USB FS clock source definition. */ -typedef enum _clock_usbfs_src -{ - kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */ - kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */ - kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ - kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */ - - kCLOCK_UsbfsSrcNone = - SYSCON_USB0CLKSEL_SEL(7) /*!COMP &= ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK); - - PMC->COMP |= (config->enLowPower << PMC_COMP_LOWPOWER_SHIFT) /*Select if enter low power mode*/ - | (config->enHysteris << PMC_COMP_HYST_SHIFT) /*select if enable hysteresis*/ - | config->pmuxInput /*pmux input source select*/ - | config->nmuxInput; /*nmux input source select */ -} - -void CMP_Deinit(void) -{ -/*disable the clock to the register interface*/ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Comp); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_cmp.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_cmp.h deleted file mode 100644 index f0990cf668..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_cmp.h +++ /dev/null @@ -1,293 +0,0 @@ -/* - * Copyright 2018 NXP -* All rights reserved. -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef __FSL_CMP_H_ -#define __FSL_CMP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup cmp_1 - * @{ - */ - -/****************************************************************************** - * Definitions. - *****************************************************************************/ -/*! @name Driver version */ -/*@{*/ -/*! @brief Driver version 2.0.0. */ -#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U)) -/*@}*/ - -/*! @brief VREF select */ -enum _cmp_vref_select -{ - KCMP_VREFSelectVDDA = 1U, /*!< Select VDDA as VREF*/ - KCMP_VREFSelectInternalVREF = 0U, /*!< select internal VREF as VREF*/ -}; - -/*! @brief cmp interrupt type */ -typedef enum _cmp_interrupt_type -{ - kCMP_EdgeDisable = 0U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< disable edge sensitive */ - kCMP_EdgeRising = 2U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Edge sensitive, falling edge */ - kCMP_EdgeFalling = 4U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Edge sensitive, rising edge */ - kCMP_EdgeRisingFalling = 6U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Edge sensitive, rising and falling edge */ - - kCMP_LevelDisable = 1U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< disable level sensitive */ - kCMP_LevelHigh = 3U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Level sensitive, high level */ - kCMP_LevelLow = 5U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Level sensitive, low level */ - kCMP_LevelDisable1 = 7U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< disable level sensitive */ -} cmp_interrupt_type_t; - -/*! @brief cmp Pmux input source */ -typedef enum _cmp_pmux_input -{ - kCMP_PInputVREF = 0U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from VREF */ - kCMP_PInputP0_0 = 1U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P0_0 */ - kCMP_PInputP0_9 = 2U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P0_9 */ - kCMP_PInputP0_18 = 3U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P0_18 */ - kCMP_PInputP1_14 = 4U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P1_14 */ - kCMP_PInputP2_23 = 5U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P2_23 */ -} cmp_pmux_input_t; - -/*! @brief cmp Nmux input source */ -typedef enum _cmp_nmux_input -{ - kCMP_NInputVREF = 0U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from VREF */ - kCMP_NInputP0_0 = 1U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P0_0 */ - kCMP_NInputP0_9 = 2U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P0_9 */ - kCMP_NInputP0_18 = 3U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P0_18 */ - kCMP_NInputP1_14 = 4U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P1_14 */ - kCMP_NInputP2_23 = 5U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P2_23 */ -} cmp_nmux_input_t; - -/*! @brief cmp configurataions */ -typedef struct _cmp_config -{ - bool enHysteris; /*!< low hysteresis */ - bool enLowPower; /*!COMP &= ~PMC_COMP_PMUX_MASK; - PMC->COMP |= pmux_select_source; -} - -/*! - * @brief select input source for nmux. - * - * @param nmux_select_source reference cmp_nmux_input_t above. - */ -static inline void CMP_NmuxSelect(cmp_nmux_input_t nmux_select_source) -{ - PMC->COMP &= ~PMC_COMP_NMUX_MASK; - PMC->COMP |= nmux_select_source; -} - -/*! - * @brief switch cmp work mode. - * - * @param enable true is enter low power mode, false is enter fast mode - */ -static inline void CMP_EnableLowePowerMode(bool enable) -{ - if (enable) - { - PMC->COMP |= PMC_COMP_LOWPOWER_MASK; - } - else - { - PMC->COMP &= ~PMC_COMP_LOWPOWER_MASK; - } -} - -/*! - * @brief Control reference voltage step, per steps of (VREFINPUT/31). - * - * @param step reference voltage step, per steps of (VREFINPUT/31). - */ -static inline void CMP_SetRefStep(uint32_t step) -{ - PMC->COMP |= step << PMC_COMP_VREF_SHIFT; -} - -/*! - * @brief cmp enable hysteresis. - * - */ -static inline void CMP_EnableHysteresis(bool enable) -{ - if (enable) - { - PMC->COMP |= PMC_COMP_HYST_MASK; - } - else - { - PMC->COMP &= ~PMC_COMP_HYST_MASK; - } -} - -/*! - * @brief VREF select between internal VREF and VDDA (for the resistive ladder). - * - * @param select 1 is Select VDDA, 0 is Select internal VREF. - */ -static inline void CMP_VREFSelect(uint32_t select) -{ - if (select) - { - PMC->COMP |= PMC_COMP_VREFINPUT_MASK; - } - else - { - PMC->COMP &= ~PMC_COMP_VREFINPUT_MASK; - } -} - -/*! - * @brief comparator analog output. - * - * @return 1 indicates p is greater than n, 0 indicates n is greater than p. - */ -static inline uint32_t CMP_GetOutput(void) -{ - return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK) ? 1 : 0; -} - -/* @} */ - -/*! - * @name cmp interrupt - * @{ - */ - -/*! - * @brief cmp enable interrupt. - * - */ -static inline void CMP_EnableInterrupt(void) -{ - SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK; -} - -/*! - * @brief cmp disable interrupt. - * - */ -static inline void CMP_DisableInterrupt(void) -{ - SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK; -} - -/*! - * @brief Select which Analog comparator output (filtered or un-filtered) is used for interrupt detection. - * - * @param enable true is Select Analog Comparator raw output (unfiltered) as input for interrupt detection. - * false is Select Analog Comparator filtered output as input for interrupt detection. - */ -static inline void CMP_InterruptSourceSelect(bool enable) -{ - if (enable) - { - SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; - } - else - { - SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; - } -} - -/*! - * @brief cmp get status. - * - * @return true is interrupt pending, false is no interrupt pending. - */ -static inline bool CMP_GetStatus(void) -{ - return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK) ? true : false; -} - -/*! - * @brief cmp clear interrupt status. - * - */ -static inline void CMP_ClearStatus(void) -{ - SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK; -} - -/*! - * @brief Comparator interrupt type select. - * - * @param type reference cmp_interrupt_type_t. - */ -static inline void CMP_InterruptTypeSelect(cmp_interrupt_type_t cmp_interrupt_type) -{ - SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_CTRL_MASK; - SYSCON->COMP_INT_CTRL |= cmp_interrupt_type; -} - -/*! - * @brief cmp get interrupt status. - * - * @return true is interrupt pending, false is no interrupt pending. - */ -static inline bool CMP_GetInterruptStatus(void) -{ - return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) ? true : false; -} -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ -#endif /* __FSL_CMP_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_common.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_common.c deleted file mode 100644 index 39e78bcd9f..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_common.c +++ /dev/null @@ -1,147 +0,0 @@ -/* -* Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP -* All rights reserved. -* -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#include "fsl_common.h" -#define SDK_MEM_MAGIC_NUMBER 12345U - -typedef struct _mem_align_control_block -{ - uint16_t identifier; /*!< Identifier for the memory control block. */ - uint16_t offset; /*!< offset from aligned address to real address */ -} mem_align_cb_t; - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.common" -#endif - -#ifndef __GIC_PRIO_BITS -#if defined(ENABLE_RAM_VECTOR_TABLE) -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) -{ -/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) - extern uint32_t Image$$VECTOR_ROM$$Base[]; - extern uint32_t Image$$VECTOR_RAM$$Base[]; - extern uint32_t Image$$RW_m_data$$Base[]; - -#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base -#define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) -#elif defined(__ICCARM__) - extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; -#elif defined(__GNUC__) - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; - extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; - uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); -#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ - uint32_t n; - uint32_t ret; - uint32_t irqMaskValue; - - irqMaskValue = DisableGlobalIRQ(); - if (SCB->VTOR != (uint32_t)__VECTOR_RAM) - { - /* Copy the vector table from ROM to RAM */ - for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) - { - __VECTOR_RAM[n] = __VECTOR_TABLE[n]; - } - /* Point the VTOR to the position of vector table */ - SCB->VTOR = (uint32_t)__VECTOR_RAM; - } - - ret = __VECTOR_RAM[irq + 16]; - /* make sure the __VECTOR_RAM is noncachable */ - __VECTOR_RAM[irq + 16] = irqHandler; - - EnableGlobalIRQ(irqMaskValue); - -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif - - return ret; -} -#endif /* ENABLE_RAM_VECTOR_TABLE. */ -#endif /* __GIC_PRIO_BITS. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) -#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) - -void EnableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERSET[index] = 1u << intNumber; - EnableIRQ(interrupt); /* also enable interrupt at NVIC */ -} - -void DisableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - DisableIRQ(interrupt); /* also disable interrupt at NVIC */ - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERCLR[index] = 1u << intNumber; -} -#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -void *SDK_Malloc(size_t size, size_t alignbytes) -{ - mem_align_cb_t *p_cb = NULL; - uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t); - void *p_align_addr, *p_addr = malloc(alignedsize); - - if (!p_addr) - { - return NULL; - } - - p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes); - - p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4); - p_cb->identifier = SDK_MEM_MAGIC_NUMBER; - p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr; - - return (void *)p_align_addr; -} - -void SDK_Free(void *ptr) -{ - mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4); - - if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) - { - return; - } - - free((void *)((uint32_t)ptr - p_cb->offset)); -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_common.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_common.h deleted file mode 100644 index d8a74ce412..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_common.h +++ /dev/null @@ -1,585 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_COMMON_H_ -#define _FSL_COMMON_H_ - -#include -#include -#include -#include -#include - -#if defined(__ICCARM__) -#include -#endif - -#include "fsl_device_registers.h" - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Construct a status code value from a group and code number. */ -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) - -/*! @brief Construct the version number for drivers. */ -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) - -/*! @name Driver version */ -/*@{*/ -/*! @brief common driver version 2.0.1. */ -#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/* Debug console type definition. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ - -/*! @brief Status group numbers. */ -enum _status_groups -{ - kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ - kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ - kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ - kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ - kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ - kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ - kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ - kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ - kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ - kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ - kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ - kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ - kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ - kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ - kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ - kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ - kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ - kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ - kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ - kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ - kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ - kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ - kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ - kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ - kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ - kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ - kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ - kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ - kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ - kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ - kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ - kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ - kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ - kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ - kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ - kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ - kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ - kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ - kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ - kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ - kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ - kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ - kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ - kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ - kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ - kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ - kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ - kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ - kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ - kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ - kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ - kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ - kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ - kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ - kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ - kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ - kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ - kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ - kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ - kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ - kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ - kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ - kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ - kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ - kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ - kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ - kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ - kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ - kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ - kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ - kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ - - kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ - kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ - kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ - kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ - kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ - kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ - kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ - kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ - kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ - kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ - kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ - kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ - kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ - kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ - kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ - kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ - kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ - kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ - kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ -}; - -/*! @brief Generic status return codes. */ -enum _generic_status -{ - kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), - kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), - kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), - kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), - kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), - kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), - kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), -}; - -/*! @brief Type used for all status and error return values. */ -typedef int32_t status_t; - -/* - * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t - * defined in previous of this file. - */ -#include "fsl_clock.h" - -/* - * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral - */ -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) -#include "fsl_reset.h" -#endif - -/* - * Macro guard for whether to use default weak IRQ implementation in drivers - */ -#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ -#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 -#endif - -/*! @name Min/max macros */ -/* @{ */ -#if !defined(MIN) -#define MIN(a, b) ((a) < (b) ? (a) : (b)) -#endif - -#if !defined(MAX) -#define MAX(a, b) ((a) > (b) ? (a) : (b)) -#endif -/* @} */ - -/*! @brief Computes the number of elements in an array. */ -#if !defined(ARRAY_SIZE) -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -#endif - -/*! @name UINT16_MAX/UINT32_MAX value */ -/* @{ */ -#if !defined(UINT16_MAX) -#define UINT16_MAX ((uint16_t)-1) -#endif - -#if !defined(UINT32_MAX) -#define UINT32_MAX ((uint32_t)-1) -#endif -/* @} */ - -/*! @name Timer utilities */ -/* @{ */ -/*! Macro to convert a microsecond period to raw count value */ -#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) -/*! Macro to convert a raw count value to microsecond */ -#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) - -/*! Macro to convert a millisecond period to raw count value */ -#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) -/*! Macro to convert a raw count value to millisecond */ -#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) -/* @} */ - -/*! @name Alignment variable definition macros */ -/* @{ */ -#if (defined(__ICCARM__)) -/** - * Workaround to disable MISRA C message suppress warnings for IAR compiler. - * http://supp.iar.com/Support/?note=24725 - */ -_Pragma("diag_suppress=Pm120") -#define SDK_PRAGMA(x) _Pragma(#x) - _Pragma("diag_error=Pm120") -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var -#endif -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var -#endif -#elif defined(__GNUC__) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) -#endif -#else -#error Toolchain not supported -#define SDK_ALIGN(var, alignbytes) var -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) var -#endif -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) var -#endif -#endif - -/*! Macro to change a value to a given size aligned value */ -#define SDK_SIZEALIGN(var, alignbytes) \ - ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) -/* @} */ - -/*! @name Non-cacheable region definition macros */ -/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or - * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, - * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables - * will be initialized to zero in system startup. - */ -/* @{ */ -#if (defined(__ICCARM__)) -#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) -#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" -#else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -#endif -#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var -#else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var -#endif -#elif(defined(__GNUC__)) -/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" - * in your projects to make sure the non-cacheable section variables will be initialized in system startup. - */ -#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) -#else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) -#endif -#else -#error Toolchain not supported. -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var -#endif -/* @} */ - -/*! @name Time sensitive region */ -/* @{ */ -#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE -#if (defined(__ICCARM__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" -#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" -#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func -#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func -#elif(defined(__GNUC__)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func -#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ -#else -#if (defined(__ICCARM__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func -#define AT_QUICKACCESS_SECTION_DATA(func) func -#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define AT_QUICKACCESS_SECTION_CODE(func) func -#define AT_QUICKACCESS_SECTION_DATA(func) func -#elif(defined(__GNUC__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func -#define AT_QUICKACCESS_SECTION_DATA(func) func -#else -#error Toolchain not supported. -#endif -#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ -/* @} */ - -/*! @name Ram Function */ -#if (defined(__ICCARM__)) -#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" -#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func -#elif(defined(__GNUC__)) -#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ -/* @} */ -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) - extern "C" -{ -#endif - - /*! - * @brief Enable specific interrupt. - * - * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt enabled successfully - * @retval kStatus_Fail Failed to enable the interrupt - */ - static inline status_t EnableIRQ(IRQn_Type interrupt) - { - if (NotAvail_IRQn == interrupt) - { - return kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - return kStatus_Fail; - } -#endif - -#if defined(__GIC_PRIO_BITS) - GIC_EnableIRQ(interrupt); -#else - NVIC_EnableIRQ(interrupt); -#endif - return kStatus_Success; - } - - /*! - * @brief Disable specific interrupt. - * - * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt disabled successfully - * @retval kStatus_Fail Failed to disable the interrupt - */ - static inline status_t DisableIRQ(IRQn_Type interrupt) - { - if (NotAvail_IRQn == interrupt) - { - return kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - return kStatus_Fail; - } -#endif - -#if defined(__GIC_PRIO_BITS) - GIC_DisableIRQ(interrupt); -#else - NVIC_DisableIRQ(interrupt); -#endif - return kStatus_Success; - } - - /*! - * @brief Disable the global IRQ - * - * Disable the global interrupt and return the current primask register. User is required to provided the primask - * register for the EnableGlobalIRQ(). - * - * @return Current primask value. - */ - static inline uint32_t DisableGlobalIRQ(void) - { -#if defined(CPSR_I_Msk) - uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; - - __disable_irq(); - - return cpsr; -#else - uint32_t regPrimask = __get_PRIMASK(); - - __disable_irq(); - - return regPrimask; -#endif - } - - /*! - * @brief Enable the global IRQ - * - * Set the primask register with the provided primask value but not just enable the primask. The idea is for the - * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to - * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. - * - * @param primask value of primask register to be restored. The primask value is supposed to be provided by the - * DisableGlobalIRQ(). - */ - static inline void EnableGlobalIRQ(uint32_t primask) - { -#if defined(CPSR_I_Msk) - __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); -#else - __set_PRIMASK(primask); -#endif - } - -#if defined(ENABLE_RAM_VECTOR_TABLE) - /*! - * @brief install IRQ handler - * - * @param irq IRQ number - * @param irqHandler IRQ handler address - * @return The old IRQ handler address - */ - uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); -#endif /* ENABLE_RAM_VECTOR_TABLE. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - /*! - * @brief Enable specific interrupt for wake-up from deep-sleep mode. - * - * Enable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). - * - * @param interrupt The IRQ number. - */ - void EnableDeepSleepIRQ(IRQn_Type interrupt); - - /*! - * @brief Disable specific interrupt for wake-up from deep-sleep mode. - * - * Disable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). - * - * @param interrupt The IRQ number. - */ - void DisableDeepSleepIRQ(IRQn_Type interrupt); -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - - /*! - * @brief Allocate memory with given alignment and aligned size. - * - * This is provided to support the dynamically allocated memory - * used in cache-able region. - * @param size The length required to malloc. - * @param alignbytes The alignment size. - * @retval The allocated memory. - */ - void *SDK_Malloc(size_t size, size_t alignbytes); - - /*! - * @brief Free memory. - * - * @param ptr The memory to be release. - */ - void SDK_Free(void *ptr); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_COMMON_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_crc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_crc.c deleted file mode 100644 index e63dd88b6d..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_crc.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_crc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_crc" -#endif - -#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT -/* @brief Default user configuration structure for CRC-CCITT */ -#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT -/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */ -#define CRC_DRIVER_DEFAULT_REVERSE_IN false -/*< Default is no bit reverse */ -#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false -/*< Default is without complement of written data */ -#define CRC_DRIVER_DEFAULT_REVERSE_OUT false -/*< Default is no bit reverse */ -#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false -/*< Default is without complement of CRC data register read data */ -#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU -/*< Default initial checksum */ -#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Enables and configures the CRC peripheral module. - * - * This functions enables the CRC peripheral clock in the LPC SYSCON block. - * It also configures the CRC engine and starts checksum computation by writing the seed. - * - * param base CRC peripheral address. - * param config CRC module configuration structure. - */ -void CRC_Init(CRC_Type *base, const crc_config_t *config) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable clock to CRC */ - CLOCK_EnableClock(kCLOCK_Crc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_CRC_HAS_NO_RESET) && FSL_FEATURE_CRC_HAS_NO_RESET) - RESET_PeripheralReset(kCRC_RST_SHIFT_RSTn); -#endif - - /* configure CRC module and write the seed */ - base->MODE = 0 | CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) | - CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) | - CRC_MODE_CMPL_SUM(config->complementOut); - base->SEED = config->seed; -} - -/*! - * brief Loads default values to CRC protocol configuration structure. - * - * Loads default values to CRC protocol configuration structure. The default values are: - * code - * config->polynomial = kCRC_Polynomial_CRC_CCITT; - * config->reverseIn = false; - * config->complementIn = false; - * config->reverseOut = false; - * config->complementOut = false; - * config->seed = 0xFFFFU; - * endcode - * - * param config CRC protocol configuration structure - */ -void CRC_GetDefaultConfig(crc_config_t *config) -{ - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - - static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN, - CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT, - CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED}; - - *config = default_config; -} - -/*! - * brief resets CRC peripheral module. - * - * param base CRC peripheral address. - */ -void CRC_Reset(CRC_Type *base) -{ - crc_config_t config; - CRC_GetDefaultConfig(&config); - CRC_Init(base, &config); -} - -/*! - * brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. - * - * The values, including seed, can be used to resume CRC calculation later. - - * param base CRC peripheral address. - * param config CRC protocol configuration structure - */ -void CRC_GetConfig(CRC_Type *base, crc_config_t *config) -{ - /* extract CRC mode settings */ - uint32_t mode = base->MODE; - config->polynomial = (crc_polynomial_t)((mode & CRC_MODE_CRC_POLY_MASK) >> CRC_MODE_CRC_POLY_SHIFT); - config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK); - config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK); - config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK); - config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK); - - /* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */ - base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT)); - - /* now we can obtain intermediate raw CRC sum value */ - config->seed = base->SUM; - - /* restore original CRC sum bit reverse and 1's complement setting */ - base->MODE = mode; -} - -/*! - * brief Writes data to the CRC module. - * - * Writes input data buffer bytes to CRC data register. - * - * param base CRC peripheral address. - * param data Input data stream, MSByte in data[0]. - * param dataSize Size of the input data buffer in bytes. - */ -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) -{ - const uint32_t *data32; - - /* 8-bit reads and writes till source address is aligned 4 bytes */ - while ((dataSize) && ((uint32_t)data & 3U)) - { - *((__O uint8_t *)&(base->WR_DATA)) = *data; - data++; - dataSize--; - } - - /* use 32-bit reads and writes as long as possible */ - data32 = (const uint32_t *)data; - while (dataSize >= sizeof(uint32_t)) - { - *((__O uint32_t *)&(base->WR_DATA)) = *data32; - data32++; - dataSize -= sizeof(uint32_t); - } - - data = (const uint8_t *)data32; - - /* 8-bit reads and writes till end of data buffer */ - while (dataSize) - { - *((__O uint8_t *)&(base->WR_DATA)) = *data; - data++; - dataSize--; - } -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_crc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_crc.h deleted file mode 100644 index ac3500afaa..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_crc.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CRC_H_ -#define _FSL_CRC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup crc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CRC driver version. Version 2.0.1. - * - * Current version: 2.0.1 - * - * Change log: - * - Version 2.0.0 - * - initial version - * - Version 2.0.1 - * - add explicit type cast when writing to WR_DATA - */ -#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -#ifndef CRC_DRIVER_CUSTOM_DEFAULTS -/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */ -#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1 -#endif - -/*! @brief CRC polynomials to use. */ -typedef enum _crc_polynomial -{ - kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */ - kCRC_Polynomial_CRC_16 = 1U, /*!< x^16+x^15+x^2+1 */ - kCRC_Polynomial_CRC_32 = 2U /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */ -} crc_polynomial_t; - -/*! -* @brief CRC protocol configuration. -* -* This structure holds the configuration for the CRC protocol. -* -*/ -typedef struct _crc_config -{ - crc_polynomial_t polynomial; /*!< CRC polynomial. */ - bool reverseIn; /*!< Reverse bits on input. */ - bool complementIn; /*!< Perform 1's complement on input. */ - bool reverseOut; /*!< Reverse bits on output. */ - bool complementOut; /*!< Perform 1's complement on output. */ - uint32_t seed; /*!< Starting checksum value. */ -} crc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enables and configures the CRC peripheral module. - * - * This functions enables the CRC peripheral clock in the LPC SYSCON block. - * It also configures the CRC engine and starts checksum computation by writing the seed. - * - * @param base CRC peripheral address. - * @param config CRC module configuration structure. - */ -void CRC_Init(CRC_Type *base, const crc_config_t *config); - -/*! - * @brief Disables the CRC peripheral module. - * - * This functions disables the CRC peripheral clock in the LPC SYSCON block. - * - * @param base CRC peripheral address. - */ -static inline void CRC_Deinit(CRC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* disable clock to CRC */ - CLOCK_DisableClock(kCLOCK_Crc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief resets CRC peripheral module. - * - * @param base CRC peripheral address. - */ -void CRC_Reset(CRC_Type *base); - -/*! - * @brief Loads default values to CRC protocol configuration structure. - * - * Loads default values to CRC protocol configuration structure. The default values are: - * @code - * config->polynomial = kCRC_Polynomial_CRC_CCITT; - * config->reverseIn = false; - * config->complementIn = false; - * config->reverseOut = false; - * config->complementOut = false; - * config->seed = 0xFFFFU; - * @endcode - * - * @param config CRC protocol configuration structure - */ -void CRC_GetDefaultConfig(crc_config_t *config); - -/*! - * @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. - * - * The values, including seed, can be used to resume CRC calculation later. - - * @param base CRC peripheral address. - * @param config CRC protocol configuration structure - */ -void CRC_GetConfig(CRC_Type *base, crc_config_t *config); - -/*! - * @brief Writes data to the CRC module. - * - * Writes input data buffer bytes to CRC data register. - * - * @param base CRC peripheral address. - * @param data Input data stream, MSByte in data[0]. - * @param dataSize Size of the input data buffer in bytes. - */ -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); - -/*! - * @brief Reads 32-bit checksum from the CRC module. - * - * Reads CRC data register. - * - * @param base CRC peripheral address. - * @return final 32-bit checksum, after configured bit reverse and complement operations. - */ -static inline uint32_t CRC_Get32bitResult(CRC_Type *base) -{ - return base->SUM; -} - -/*! - * @brief Reads 16-bit checksum from the CRC module. - * - * Reads CRC data register. - * - * @param base CRC peripheral address. - * @return final 16-bit checksum, after configured bit reverse and complement operations. - */ -static inline uint16_t CRC_Get16bitResult(CRC_Type *base) -{ - return (uint16_t)base->SUM; -} - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_CRC_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_ctimer.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_ctimer.c deleted file mode 100644 index 4d87d004c4..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_ctimer.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_ctimer.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.ctimer" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base Ctimer peripheral base address - * - * @return The Timer instance - */ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to Timer bases for each instance. */ -static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to Timer clocks for each instance. */ -static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; -#else -/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; -#endif -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/*! @brief Pointers real ISRs installed by drivers for each instance. */ -static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0}; - -/*! @brief Callback type installed by drivers for each instance. */ -static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback}; - -/*! @brief Array to map timer instance to IRQ number. */ -static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base) -{ - uint32_t instance; - uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ctimerArrayCount; instance++) - { - if (s_ctimerBases[instance] == base) - { - break; - } - } - - assert(instance < ctimerArrayCount); - - return instance; -} - -/*! - * brief Ungates the clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application before using the driver. - * - * param base Ctimer peripheral base address - * param config Pointer to the user configuration structure. - */ -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) -{ - assert(config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the timer clock*/ - CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/* Reset the module. */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) - RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/* Setup the cimer mode and count select */ -#if !defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE - base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); -#endif - /* Setup the timer prescale value */ - base->PR = CTIMER_PR_PRVAL(config->prescale); -} - -/*! - * brief Gates the timer clock. - * - * param base Ctimer peripheral base address - */ -void CTIMER_Deinit(CTIMER_Type *base) -{ - uint32_t index = CTIMER_GetInstance(base); - /* Stop the timer */ - base->TCR &= ~CTIMER_TCR_CEN_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the timer clock*/ - CLOCK_DisableClock(s_ctimerClocks[index]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Disable IRQ at NVIC Level */ - DisableIRQ(s_ctimerIRQ[index]); -} - -/*! - * brief Fills in the timers configuration structure with the default settings. - * - * The default values are: - * code - * config->mode = kCTIMER_TimerMode; - * config->input = kCTIMER_Capture_0; - * config->prescale = 0; - * endcode - * param config Pointer to the user configuration structure. - */ -void CTIMER_GetDefaultConfig(ctimer_config_t *config) -{ - assert(config); - - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - - /* Run as a timer */ - config->mode = kCTIMER_TimerMode; - /* This field is ignored when mode is timer */ - config->input = kCTIMER_Capture_0; - /* Timer counter is incremented on every APB bus clock */ - config->prescale = 0; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function will assign match channel 3 to set the PWM cycle. - * - * note When setting PWM output from multiple output pins, all should use the same PWM - * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. - * - * param base Ctimer peripheral base address - * param matchChannel Match pin to be used to output the PWM signal - * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 - * param pwmFreq_Hz PWM signal frequency in Hz - * param srcClock_Hz Timer counter clock in Hz - * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt is generated - * - * return kStatus_Success on success - * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle - */ -status_t CTIMER_SetupPwm(CTIMER_Type *base, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt) -{ - assert(pwmFreq_Hz > 0); - - uint32_t reg; - uint32_t period, pulsePeriod = 0; - uint32_t timerClock = srcClock_Hz / (base->PR + 1); - uint32_t index = CTIMER_GetInstance(base); - - if (matchChannel == kCTIMER_Match_3) - { - return kStatus_Fail; - } - - /* Enable PWM mode on the channel */ - base->PWMC |= (1U << matchChannel); - - /* Clear the stop, reset and interrupt bits for this channel */ - reg = base->MCR; - reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); - - /* If call back function is valid then enable match interrupt for the channel */ - if (enableInt) - { - reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); - } - - /* Reset the counter when match on channel 3 */ - reg |= CTIMER_MCR_MR3R_MASK; - - base->MCR = reg; - - /* Calculate PWM period match value */ - period = (timerClock / pwmFreq_Hz) - 1; - - /* Calculate pulse width match value */ - if (dutyCyclePercent == 0) - { - pulsePeriod = period + 1; - } - else - { - pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; - } - - /* Match on channel 3 will define the PWM period */ - base->MR[kCTIMER_Match_3] = period; - - /* This will define the PWM pulse period */ - base->MR[matchChannel] = pulsePeriod; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); - /* If call back function is valid then enable interrupt and update the call back function */ - if (enableInt) - { - EnableIRQ(s_ctimerIRQ[index]); - } - - return kStatus_Success; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function will assign match channel 3 to set the PWM cycle. - * - * note When setting PWM output from multiple output pins, all should use the same PWM - * period - * - * param base Ctimer peripheral base address - * param matchChannel Match pin to be used to output the PWM signal - * param pwmPeriod PWM period match value - * param pulsePeriod Pulse width match value - * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt is generated - * - * return kStatus_Success on success - * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period - */ -status_t CTIMER_SetupPwmPeriod( - CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt) -{ -/* Some CTimers only have 16bits , so the value is limited*/ -#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B - assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU))); -#endif - - uint32_t reg; - uint32_t index = CTIMER_GetInstance(base); - - if (matchChannel == kCTIMER_Match_3) - { - return kStatus_Fail; - } - - /* Enable PWM mode on the channel */ - base->PWMC |= (1U << matchChannel); - - /* Clear the stop, reset and interrupt bits for this channel */ - reg = base->MCR; - reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); - - /* If call back function is valid then enable match interrupt for the channel */ - if (enableInt) - { - reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); - } - - /* Reset the counter when match on channel 3 */ - reg |= CTIMER_MCR_MR3R_MASK; - - base->MCR = reg; - - /* Match on channel 3 will define the PWM period */ - base->MR[kCTIMER_Match_3] = pwmPeriod; - - /* This will define the PWM pulse period */ - base->MR[matchChannel] = pulsePeriod; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); - /* If call back function is valid then enable interrupt and update the call back function */ - if (enableInt) - { - EnableIRQ(s_ctimerIRQ[index]); - } - - return kStatus_Success; -} - -/*! - * brief Updates the duty cycle of an active PWM signal. - * - * note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution. - * - * param base Ctimer peripheral base address - * param matchChannel Match pin to be used to output the PWM signal - * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent) -{ - uint32_t pulsePeriod = 0, period; - - /* Match channel 3 defines the PWM period */ - period = base->MR[kCTIMER_Match_3]; - - /* Calculate pulse width match value */ - pulsePeriod = (period * dutyCyclePercent) / 100; - - /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent == 0) - { - pulsePeriod = period + 1; - } - else - { - pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; - } - - /* Update dutycycle */ - base->MR[matchChannel] = pulsePeriod; -} - -/*! - * brief Setup the match register. - * - * User configuration is used to setup the match value and action to be taken when a match occurs. - * - * param base Ctimer peripheral base address - * param matchChannel Match register to configure - * param config Pointer to the match configuration structure - */ -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) -{ -/* Some CTimers only have 16bits , so the value is limited*/ -#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B - assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU)); -#endif - uint32_t reg; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the counter operation when a match on this channel occurs */ - reg = base->MCR; - reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); - reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3))); - reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3))); - reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); - base->MCR = reg; - - reg = base->EMR; - /* Set the match output operation when a match on this channel occurs */ - reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2)); - reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2)); - - /* Set the initial state of the EM bit/output */ - reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel); - reg |= (uint32_t)config->outPinInitState << matchChannel; - base->EMR = reg; - - /* Set the match value */ - base->MR[matchChannel] = config->matchValue; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); - /* If interrupt is enabled then enable interrupt and update the call back function */ - if (config->enableInterrupt) - { - EnableIRQ(s_ctimerIRQ[index]); - } -} - -#if !defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE -/*! - * brief Setup the capture. - * - * param base Ctimer peripheral base address - * param capture Capture channel to configure - * param edge Edge on the channel that will trigger a capture - * param enableInt Flag to enable channel interrupts, if enabled then the registered call back - * is called upon capture - */ -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt) -{ - uint32_t reg = base->CCR; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the capture edge */ - reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3)); - reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3)); - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture)); - /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ - if (enableInt) - { - reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3); - EnableIRQ(s_ctimerIRQ[index]); - } - base->CCR = reg; -} -#endif - -/*! - * brief Register callback. - * - * param base Ctimer peripheral base address - * param cb_func callback function - * param cb_type callback function type, singular or multiple - */ -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) -{ - uint32_t index = CTIMER_GetInstance(base); - s_ctimerCallback[index] = cb_func; - ctimerCallbackType[index] = cb_type; -} - -void CTIMER_GenericIRQHandler(uint32_t index) -{ - uint32_t int_stat, i, mask; - /* Get Interrupt status flags */ - int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); - /* Clear the status flags that were set */ - CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); - if (ctimerCallbackType[index] == kCTIMER_SingleCallback) - { - if (s_ctimerCallback[index][0]) - { - s_ctimerCallback[index][0](int_stat); - } - } - else - { -#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE - for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++) -#else -#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT - for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) -#else - for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -#endif - { - mask = 0x01 << i; - /* For each status flag bit that was set call the callback function if it is valid */ - if ((int_stat & mask) && (s_ctimerCallback[index][i])) - { - s_ctimerCallback[index][i](int_stat); - } - } - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(CTIMER0) -void CTIMER0_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(0); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CTIMER1) -void CTIMER1_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(1); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CTIMER2) -void CTIMER2_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(2); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CTIMER3) -void CTIMER3_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(3); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CTIMER4) -void CTIMER4_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(4); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_ctimer.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_ctimer.h deleted file mode 100644 index 3319125a80..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_ctimer.h +++ /dev/null @@ -1,488 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_CTIMER_H_ -#define _FSL_CTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ctimer - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */ -/*@}*/ - -/*! @brief List of Timer capture channels */ -typedef enum _ctimer_capture_channel -{ - kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ - kCTIMER_Capture_1, /*!< Timer capture channel 1 */ - kCTIMER_Capture_2, /*!< Timer capture channel 2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - kCTIMER_Capture_3 /*!< Timer capture channel 3 */ -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -} ctimer_capture_channel_t; - -/*! @brief List of capture edge options */ -typedef enum _ctimer_capture_edge -{ - kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ - kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ - kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ -} ctimer_capture_edge_t; - -/*! @brief List of Timer match registers */ -typedef enum _ctimer_match -{ - kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ - kCTIMER_Match_1, /*!< Timer match register 1 */ - kCTIMER_Match_2, /*!< Timer match register 2 */ - kCTIMER_Match_3 /*!< Timer match register 3 */ -} ctimer_match_t; - -/*! @brief List of output control options */ -typedef enum _ctimer_match_output_control -{ - kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ - kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ - kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ - kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ -} ctimer_match_output_control_t; - -/*! @brief List of Timer modes */ -typedef enum _ctimer_timer_mode -{ - kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ - kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ - kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ - kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ -} ctimer_timer_mode_t; - -/*! @brief List of Timer interrupts */ -typedef enum _ctimer_interrupt_enable -{ - kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ - kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ - kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ - kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ - kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ - kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ -#endif -} ctimer_interrupt_enable_t; - -/*! @brief List of Timer flags */ -typedef enum _ctimer_status_flags -{ - kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ - kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ - kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ - kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ - kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ - kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ -#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT - kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -#endif -} ctimer_status_flags_t; - -typedef void (*ctimer_callback_t)(uint32_t flags); - -/*! @brief Callback type when registering for a callback. When registering a callback - * an array of function pointers is passed the size could be 1 or 8, the callback - * type will tell that. - */ -typedef enum -{ - kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. - based on the status flags different channels needs to be handled differently */ - kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. - for both match/capture */ -} ctimer_callback_type_t; - -/*! - * @brief Match configuration - * - * This structure holds the configuration settings for each match register. - */ -typedef struct _ctimer_match_config -{ - uint32_t matchValue; /*!< This is stored in the match register */ - bool enableCounterReset; /*!< true: Match will reset the counter - false: Match will not reser the counter */ - bool enableCounterStop; /*!< true: Match will stop the counter - false: Match will not stop the counter */ - ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ - bool outPinInitState; /*!< Initial value of the EM bit/output */ - bool enableInterrupt; /*!< true: Generate interrupt upon match - false: Do not generate interrupt on match */ - -} ctimer_match_config_t; - -/*! - * @brief Timer configuration structure - * - * This structure holds the configuration settings for the Timer peripheral. To initialize this - * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _ctimer_config -{ - ctimer_timer_mode_t mode; /*!< Timer mode */ - ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer - modes that rely on this input signal to increment TC */ - uint32_t prescale; /*!< Prescale value */ -} ctimer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application before using the driver. - * - * @param base Ctimer peripheral base address - * @param config Pointer to the user configuration structure. - */ -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); - -/*! - * @brief Gates the timer clock. - * - * @param base Ctimer peripheral base address - */ -void CTIMER_Deinit(CTIMER_Type *base); - -/*! - * @brief Fills in the timers configuration structure with the default settings. - * - * The default values are: - * @code - * config->mode = kCTIMER_TimerMode; - * config->input = kCTIMER_Capture_0; - * config->prescale = 0; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void CTIMER_GetDefaultConfig(ctimer_config_t *config); - -/*! @}*/ - -/*! - * @name PWM setup operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function will assign match channel 3 to set the PWM cycle. - * - * @note When setting PWM output from multiple output pins, all should use the same PWM - * period - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param pwmPeriod PWM period match value - * @param pulsePeriod Pulse width match value - * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt is generated - * - * @return kStatus_Success on success - * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period - */ -status_t CTIMER_SetupPwmPeriod( - CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt); - -/*! - * @brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function will assign match channel 3 to set the PWM cycle. - * - * @note When setting PWM output from multiple output pins, all should use the same PWM - * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz Timer counter clock in Hz - * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt is generated - * - * @return kStatus_Success on success - * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle - */ -status_t CTIMER_SetupPwm(CTIMER_Type *base, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt); - -/*! - * @brief Updates the pulse period of an active PWM signal. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param pulsePeriod New PWM pulse width match value - */ -static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) -{ - /* Update PWM pulse period match value */ - base->MR[matchChannel] = pulsePeriod; -} - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * @note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent); - -/*! @}*/ - -/*! - * @brief Setup the match register. - * - * User configuration is used to setup the match value and action to be taken when a match occurs. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match register to configure - * @param config Pointer to the match configuration structure - */ -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); - -/*! - * @brief Setup the capture. - * - * @param base Ctimer peripheral base address - * @param capture Capture channel to configure - * @param edge Edge on the channel that will trigger a capture - * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back - * is called upon capture - */ -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt); - -/*! - * @brief Get the timer count value from TC register. - * - * @param base Ctimer peripheral base address. - * @return return the timer count value. - */ -static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base) -{ - return (base->TC); -} - -/*! - * @brief Register callback. - * - * @param base Ctimer peripheral base address - * @param cb_func callback function - * @param cb_type callback function type, singular or multiple - */ -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Enable match interrupts */ - base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - -/* Enable capture interrupts */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - ); -#endif -} - -/*! - * @brief Disables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Disable match interrupts */ - base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); - -/* Disable capture interrupts */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - )); -#endif -} - -/*! - * @brief Gets the enabled Timer interrupts. - * - * @param base Ctimer peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) -{ - uint32_t enabledIntrs = 0; - - /* Get all the match interrupts enabled */ - enabledIntrs = - base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - -/* Get all the capture interrupts enabled */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - ); -#endif - - return enabledIntrs; -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the Timer status flags. - * - * @param base Ctimer peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) -{ - return base->IR; -} - -/*! - * @brief Clears the Timer status flags. - * - * @param base Ctimer peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) -{ - base->IR = mask; -} - -/*! @}*/ - -/*! - * @name Counter Start and Stop - * @{ - */ - -/*! - * @brief Starts the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StartTimer(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CEN_MASK; -} - -/*! - * @brief Stops the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StopTimer(CTIMER_Type *base) -{ - base->TCR &= ~CTIMER_TCR_CEN_MASK; -} - -/*! @}*/ - -/*! - * @brief Reset the counter. - * - * The timer counter and prescale counter are reset on the next positive edge of the APB clock. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_Reset(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CRST_MASK; - base->TCR &= ~CTIMER_TCR_CRST_MASK; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_CTIMER_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_dma.c deleted file mode 100644 index 3e7aa6b293..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_dma.c +++ /dev/null @@ -1,734 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_dma" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for DMA. - * - * @param base DMA peripheral base address. - */ -static uint32_t DMA_GetInstance(DMA_Type *base); - -/*! - * @brief Get virtual channel number. - * - * @param base DMA peripheral base address. - */ -static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map DMA instance number to base pointer. */ -static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map DMA instance number to clock name. */ -static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) -/*! @brief Pointers to DMA resets for each instance. */ -static const reset_ip_name_t s_dmaResets[] = DMA_RSTS_N; -#endif /*! @brief Array to map DMA instance number to IRQ number. */ -static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; - -/*! @brief Pointers to transfer handle for each DMA channel. */ -static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS]; - -SDK_ALIGN(dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -#if defined(DMA1) -SDK_ALIGN(dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], - FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); -static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0, s_dma_descriptor_table1}; -#else -static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0}; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t DMA_GetInstance(DMA_Type *base) -{ - uint32_t instance; - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) - { - if (s_dmaBases[instance] == base) - { - break; - } - } - assert(instance < ARRAY_SIZE(s_dmaBases)); - - return instance; -} - -static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base) -{ - uint32_t startChannel = 0, instance = 0; - uint32_t i = 0; - - instance = DMA_GetInstance(base); - - /* Compute start channel */ - for (i = 0; i < instance; i++) - { - startChannel += FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]); - } - - return startChannel; -} - -/*! - * brief Initializes DMA peripheral. - * - * This function enable the DMA clock, set descriptor table and - * enable DMA peripheral. - * - * param base DMA peripheral base address. - */ -void DMA_Init(DMA_Type *base) -{ - uint32_t instance = DMA_GetInstance(base); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable dma clock gate */ - CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) - /* Reset the DMA module */ - RESET_PeripheralReset(s_dmaResets[DMA_GetInstance(base)]); -#endif - /* set descriptor table */ - base->SRAMBASE = (uint32_t)s_dma_descriptor_table[instance]; - /* enable dma peripheral */ - base->CTRL |= DMA_CTRL_ENABLE_MASK; -} - -/*! - * brief Deinitializes DMA peripheral. - * - * This function gates the DMA clock. - * - * param base DMA peripheral base address. - */ -void DMA_Deinit(DMA_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Disable DMA peripheral */ - base->CTRL &= ~(DMA_CTRL_ENABLE_MASK); -} - -/*! - * brief Set trigger settings of DMA channel. - * deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. - * - * param base DMA peripheral base address. - * param channel DMA channel number. - * param trigger trigger configuration. - */ -void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger) -{ - assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger)); - - uint32_t tmp = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | - DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK); - tmp = base->CHANNEL[channel].CFG & (~tmp); - tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); - base->CHANNEL[channel].CFG = tmp; -} - -/*! - * brief Gets the remaining bytes of the current DMA descriptor transfer. - * - * param base DMA peripheral base address. - * param channel DMA channel number. - * return The number of bytes which have not been transferred yet. - */ -uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - - /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes - * impossible to distinguish between: - * - transfer finishes (represented by value '0x3FF') - * - and remaining 1024 bytes to transfer (value 0x3FF) - * for all descriptor in chain, except the last one. - * If you decide to use this function, please use 1023 transfers as maximal value */ - - /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */ - if ((!DMA_ChannelIsActive(base, channel)) && - (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> - DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))) - { - return 0; - } - - return ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> - DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + - 1; -} - -/* Verify and convert dma_xfercfg_t to XFERCFG register */ -static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) -{ - assert(xfercfg != NULL); - /* check source increment */ - assert((xfercfg->srcInc <= kDMA_AddressInterleave4xWidth) && (xfercfg->dstInc <= kDMA_AddressInterleave4xWidth)); - /* check data width */ - assert(xfercfg->byteWidth <= kDMA_Transfer32BitWidth); - /* check transfer count */ - assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT); - - uint32_t xfer = 0; - - /* set valid flag - descriptor is ready now */ - xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid); - /* set reload - allow link to next descriptor */ - xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload); - /* set swtrig flag - start transfer */ - xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig); - /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig); - /* set INTA */ - xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA); - /* set INTB */ - xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB); - /* set data width */ - xfer |= DMA_CHANNEL_XFERCFG_WIDTH(xfercfg->byteWidth == 4 ? 2 : xfercfg->byteWidth - 1); - /* set source increment value */ - xfer |= DMA_CHANNEL_XFERCFG_SRCINC((xfercfg->srcInc == kDMA_AddressInterleave4xWidth) ? (xfercfg->srcInc - 1) : - xfercfg->srcInc); - /* set destination increment value */ - xfer |= DMA_CHANNEL_XFERCFG_DSTINC((xfercfg->dstInc == kDMA_AddressInterleave4xWidth) ? (xfercfg->dstInc - 1) : - xfercfg->dstInc); - /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1); - - /* store xferCFG */ - *xfercfg_addr = xfer; -} - -/*! - * brief setup dma descriptor - * - * param desc DMA descriptor address. - * param xfercfg Transfer configuration for DMA descriptor. - * param srcStartAddr Start address of source address. - * param dstStartAddr Start address of destination address. - * param nextDesc Address of next descriptor in chain. - */ -void DMA_SetupDescriptor( - dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) -{ - assert(((uint32_t)nextDesc & (DMA_LINK_DESCRIPTOR_ADDRESS_ALIGN - 1)) == 0U); - - uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; - - width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; - srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; - dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; - transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; - - /* covert register value to actual value */ - if (width == 2U) - { - width = kDMA_Transfer32BitWidth; - } - else - { - width += 1U; - } - - if (srcInc == 3U) - { - srcInc = kDMA_AddressInterleave4xWidth; - } - - if (dstInc == 3U) - { - dstInc = kDMA_AddressInterleave4xWidth; - } - - desc->xfercfg = xfercfg; - desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS(srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS(dstStartAddr, dstInc, transferCount * width, width); - ; - desc->linkToNextDesc = nextDesc; -} - -/*! - * brief Create application specific DMA descriptor - * to be used in a chain in transfer - * deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor - * param desc DMA descriptor address. - * param xfercfg Transfer configuration for DMA descriptor. - * param srcAddr Address of last item to transmit - * param dstAddr Address of last item to receive. - * param nextDesc Address of next descriptor in chain. - */ -void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc) -{ - assert(((uint32_t)nextDesc & (DMA_LINK_DESCRIPTOR_ADDRESS_ALIGN - 1)) == 0U); - assert((NULL != srcAddr) && (0 == (uint32_t)srcAddr % xfercfg->byteWidth)); - assert((NULL != dstAddr) && (0 == (uint32_t)dstAddr % xfercfg->byteWidth)); - - uint32_t xfercfg_reg = 0; - - DMA_SetupXferCFG(xfercfg, &xfercfg_reg); - - /* Set descriptor structure */ - DMA_SetupDescriptor(desc, xfercfg_reg, srcAddr, dstAddr, nextDesc); -} - -/*! - * brief Abort running transfer by handle. - * - * This function aborts DMA transfer specified by handle. - * - * param handle DMA handle pointer. - */ -void DMA_AbortTransfer(dma_handle_t *handle) -{ - assert(NULL != handle); - - DMA_DisableChannel(handle->base, handle->channel); - while (DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & (1U << DMA_CHANNEL_INDEX(handle->channel))) - { - } - DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1U << DMA_CHANNEL_INDEX(handle->channel); - DMA_EnableChannel(handle->base, handle->channel); -} - -/*! - * brief Creates the DMA handle. - * - * This function is called if using transaction API for DMA. This function - * initializes the internal state of DMA handle. - * - * param handle DMA handle pointer. The DMA handle stores callback function and - * parameters. - * param base DMA peripheral base address. - * param channel DMA channel number. - */ -void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) -{ - assert((NULL != handle) && (channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - - int32_t dmaInstance; - uint32_t startChannel = 0; - /* base address is invalid DMA instance */ - dmaInstance = DMA_GetInstance(base); - startChannel = DMA_GetVirtualStartChannel(base); - - memset(handle, 0, sizeof(*handle)); - handle->base = base; - handle->channel = channel; - s_DMAHandle[startChannel + channel] = handle; - /* Enable NVIC interrupt */ - EnableIRQ(s_dmaIRQNumber[dmaInstance]); - /* Enable channel interrupt */ - DMA_EnableChannelInterrupts(handle->base, channel); -} - -/*! - * brief Installs a callback function for the DMA transfer. - * - * This callback is called in DMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. - * - * param handle DMA handle pointer. - * param callback DMA callback function pointer. - * param userData Parameter for callback function. - */ -void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData) -{ - assert(handle != NULL); - - handle->callback = callback; - handle->userData = userData; -} - -/*! - * brief Prepares the DMA transfer structure. - * deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer and - * DMA_PrepareChannelXfer. - * This function prepares the transfer configuration structure according to the user input. - * - * param config The user configuration structure of type dma_transfer_t. - * param srcAddr DMA transfer source address. - * param dstAddr DMA transfer destination address. - * param byteWidth DMA transfer destination address width(bytes). - * param transferBytes DMA transfer bytes to be transferred. - * param type DMA transfer type. - * param nextDesc Chain custom descriptor to transfer. - * note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in - * source address error(SAE). - */ -void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc) -{ - uint32_t xfer_count; - assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); - assert((byteWidth == 1) || (byteWidth == 2) || (byteWidth == 4)); - assert(((uint32_t)nextDesc & (DMA_LINK_DESCRIPTOR_ADDRESS_ALIGN - 1)) == 0U); - - /* check max */ - xfer_count = transferBytes / byteWidth; - assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0 == transferBytes % byteWidth)); - - memset(config, 0, sizeof(*config)); - switch (type) - { - case kDMA_MemoryToMemory: - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 1; - config->isPeriph = false; - break; - case kDMA_PeripheralToMemory: - /* Peripheral register - source doesn't increment */ - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 1; - config->isPeriph = true; - break; - case kDMA_MemoryToPeripheral: - /* Peripheral register - destination doesn't increment */ - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - break; - case kDMA_StaticToStatic: - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - break; - default: - return; - } - - config->dstAddr = (uint8_t *)dstAddr; - config->srcAddr = (uint8_t *)srcAddr; - config->nextDesc = (uint8_t *)nextDesc; - config->xfercfg.transferCount = xfer_count; - config->xfercfg.byteWidth = byteWidth; - config->xfercfg.intA = true; - config->xfercfg.reload = nextDesc != NULL; - config->xfercfg.valid = true; -} - -/*! - * brief set channel config. - * - * This function provide a interface to configure channel configuration reisters. - * - * param base DMA base address. - * param channel DMA channel number. - * param config channel configurations structure. - */ -void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph) -{ - assert(channel <= FSL_FEATURE_DMA_MAX_CHANNELS); - - uint32_t tmp = DMA_CHANNEL_CFG_PERIPHREQEN_MASK; - - if (trigger != NULL) - { - tmp |= DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | - DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK; - } - - tmp = base->CHANNEL[channel].CFG & (~tmp); - - if (trigger != NULL) - { - tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); - } - - tmp |= DMA_CHANNEL_CFG_PERIPHREQEN(isPeriph); - - base->CHANNEL[channel].CFG = tmp; -} - -/*! - * brief Prepare channel transfer configurations. - * - * This function used to prepare channel transfer configurations. - * - * param config Pointer to DMA channel transfer configuration structure. - * param srcStartAddr source start address. - * param dstStartAddr destination start address. - * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * param type transfer type. - * param trigger DMA channel trigger configurations. - * param nextDesc address of next descriptor. - */ -void DMA_PrepareChannelTransfer(dma_channel_config_t *config, - void *srcStartAddr, - void *dstStartAddr, - uint32_t xferCfg, - dma_transfer_type_t type, - dma_channel_trigger_t *trigger, - void *nextDesc) -{ - assert((NULL != config) && (NULL != srcStartAddr) && (NULL != dstStartAddr)); - assert(((uint32_t)nextDesc & (DMA_LINK_DESCRIPTOR_ADDRESS_ALIGN - 1)) == 0U); - - /* check max */ - memset(config, 0, sizeof(*config)); - - switch (type) - { - case kDMA_MemoryToMemory: - config->isPeriph = false; - break; - case kDMA_PeripheralToMemory: - config->isPeriph = true; - break; - case kDMA_MemoryToPeripheral: - config->isPeriph = true; - break; - case kDMA_StaticToStatic: - config->isPeriph = true; - break; - default: - return; - } - - config->dstStartAddr = (uint8_t *)dstStartAddr; - config->srcStartAddr = (uint8_t *)srcStartAddr; - config->nextDesc = (uint8_t *)nextDesc; - config->trigger = trigger; - config->xferCfg = xferCfg; -} - -/*! - * brief Install DMA descriptor memory. - * - * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong - * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has - * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. - * User should be take care about the address of DMA descriptor pool which required align with 512BYTE. - * - * param handle Pointer to DMA channel transfer handle. - * param addr DMA descriptor address - * param num DMA descriptor number. - */ -void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr) -{ - assert(addr != NULL); - assert(((uint32_t)addr & (FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE - 1U)) == 0U); - - /* reconfigure the DMA descriptor base address */ - base->SRAMBASE = (uint32_t)addr; -} - -/*! - * brief Submits the DMA channel transfer request. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * param handle DMA handle pointer. - * param config Pointer to DMA transfer configuration structure. - * retval kStatus_DMA_Success It means submit transfer request succeed. - * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config) -{ - assert((NULL != handle) && (NULL != config)); - assert(handle->channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - /* Previous transfer has not finished */ - if (DMA_ChannelIsActive(handle->base, handle->channel)) - { - return kStatus_DMA_Busy; - } - - DMA_SetupDescriptor(descriptor, config->xferCfg, config->srcStartAddr, config->dstStartAddr, config->nextDesc); - DMA_SetChannelConfig(handle->base, handle->channel, config->trigger, config->isPeriph); - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg; - - return kStatus_Success; -} - -/*! - * brief Submits the DMA transfer request. - * deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * param handle DMA handle pointer. - * param config Pointer to DMA transfer configuration structure. - * retval kStatus_DMA_Success It means submit transfer request succeed. - * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) -{ - assert((NULL != handle) && (NULL != config)); - assert(handle->channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - /* Previous transfer has not finished */ - if (DMA_ChannelIsActive(handle->base, handle->channel)) - { - return kStatus_DMA_Busy; - } - - /* enable/disable peripheral request */ - if (config->isPeriph) - { - DMA_EnableChannelPeriphRq(handle->base, handle->channel); - } - else - { - DMA_DisableChannelPeriphRq(handle->base, handle->channel); - } - - DMA_CreateDescriptor(descriptor, &config->xfercfg, config->srcAddr, config->dstAddr, config->nextDesc); - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg; - - return kStatus_Success; -} - -/*! - * brief DMA start transfer. - * - * This function enables the channel request. User can call this function after submitting the transfer request - * or before submitting the transfer request. - * - * param handle DMA handle pointer. - */ -void DMA_StartTransfer(dma_handle_t *handle) -{ - assert(NULL != handle); - - uint32_t channel = handle->channel; - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); - - /* enable channel */ - DMA_EnableChannel(handle->base, channel); - - /* user software trigger if Peripheral request not enabled */ - if (((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_TRIGBURST_MASK) != 0U) || - ((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_TRIGTYPE_MASK) != DMA_CHANNEL_CFG_TRIGTYPE(1U))) - { - handle->base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; - } -} - -void DMA_IRQHandle(DMA_Type *base) -{ - dma_handle_t *handle; - int32_t channel_index; - uint32_t startChannel = DMA_GetVirtualStartChannel(base); - uint32_t i = 0; - - /* Find channels that have completed transfer */ - for (i = 0; i < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++) - { - handle = s_DMAHandle[i + startChannel]; - /* Handle is not present */ - if (NULL == handle) - { - continue; - } - channel_index = DMA_CHANNEL_INDEX(handle->channel); - /* Channel uses INTA flag */ - if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1U << channel_index)) - { - /* Clear INTA flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1U << channel_index)); - if (handle->callback) - { - (handle->callback)(handle, handle->userData, true, kDMA_IntA); - } - } - /* Channel uses INTB flag */ - if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1U << channel_index)) - { - /* Clear INTB flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1U << channel_index)); - if (handle->callback) - { - (handle->callback)(handle, handle->userData, true, kDMA_IntB); - } - } - /* Error flag */ - if (DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1U << channel_index)) - { - /* Clear error flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1U << channel_index)); - if (handle->callback) - { - (handle->callback)(handle, handle->userData, false, kDMA_IntError); - } - } - } -} - -void DMA0_DriverIRQHandler(void) -{ - DMA_IRQHandle(DMA0); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#if defined(DMA1) -void DMA1_DriverIRQHandler(void) -{ - DMA_IRQHandle(DMA1); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_dma.h deleted file mode 100644 index bb3d2f0b29..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_dma.h +++ /dev/null @@ -1,649 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_DMA_H_ -#define _FSL_DMA_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dma - * @{ - */ - -/*! @file */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DMA driver version */ -#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1. */ -/*@}*/ - -#define DMA_MAX_TRANSFER_COUNT 0x400 - -#if defined FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT) -#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) -#endif - -/* Channel group consists of 32 channels. channel_group = (channel / 32) */ -#define DMA_CHANNEL_GROUP(channel) (((uint8_t)(channel)) >> 5U) -/* Channel index in channel group. channel_index = (channel % 32) */ -#define DMA_CHANNEL_INDEX(channel) (((uint8_t)(channel)) & 0x1F) -/*! @brief DMA linked descriptor address algin size */ -#define DMA_LINK_DESCRIPTOR_ADDRESS_ALIGN (16) -#define DMA_COMMON_REG_GET(base, channel, reg) \ - (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) -#define DMA_COMMON_CONST_REG_GET(base, channel, reg) \ - (((volatile const uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) -#define DMA_COMMON_REG_SET(base, channel, reg, value) \ - (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value)) - -/*! @brief DMA descriptor end address calculate -* @param start, start address -* @param inc, address interleave size -* @param bytes, transfer bytes -* @param width, transfer width -*/ -#define DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) ((void *)((uint32_t)(start) + inc * bytes - inc * width)) - -/*! @brief DMA channel transfer configurations macro -* @param reload, true is reload link descriptor after current exhaust, false is not -* @param clrTrig, true is clear trigger status, wait software trigger, false is not -* @param intA, enable interruptA -* @param intB, enable interruptB -* @param width,transfer width -* @param srcInc, source address interleave size -* @param dstInc, destination address interleave size -* @param bytes, transfer bytes -*/ -#define DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes) \ - DMA_CHANNEL_XFERCFG_CFGVALID_MASK | DMA_CHANNEL_XFERCFG_RELOAD(reload) | DMA_CHANNEL_XFERCFG_CLRTRIG(clrTrig) | \ - DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) | \ - DMA_CHANNEL_XFERCFG_WIDTH(width == 4 ? 2 : (width - 1)) | \ - DMA_CHANNEL_XFERCFG_SRCINC(srcInc == 4 ? (srcInc - 1) : srcInc) | \ - DMA_CHANNEL_XFERCFG_DSTINC(dstInc == 4 ? (srcInc - 1) : dstInc) | \ - DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1) - -/*! @brief DMA transfer status */ -enum _dma_transfer_status -{ - kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the - transfer request. */ -}; - -/*! @brief dma address interleave size */ -enum _dma_addr_interleave_size -{ - kDMA_AddressInterleave0xWidth = 0U, /*!< dma source/destination address no interleave */ - kDMA_AddressInterleave1xWidth = 1U, /*!< dma source/destination address interleave 1xwidth */ - kDMA_AddressInterleave2xWidth = 2U, /*!< dma source/destination address interleave 2xwidth */ - kDMA_AddressInterleave4xWidth = 4U, /*!< dma source/destination address interleave 3xwidth */ -}; - -/*! @brief dma transfer width */ -enum _dma_transfer_width -{ - kDMA_Transfer8BitWidth = 1U, /*!< dma channel transfer bit width is 8 bit */ - kDMA_Transfer16BitWidth = 2U, /*!< dma channel transfer bit width is 16 bit */ - kDMA_Transfer32BitWidth = 4U, /*!< dma channel transfer bit width is 32 bit */ -}; - -/*! @brief DMA descriptor structure */ -typedef struct _dma_descriptor -{ - volatile uint32_t xfercfg; /*!< Transfer configuration */ - void *srcEndAddr; /*!< Last source address of DMA transfer */ - void *dstEndAddr; /*!< Last destination address of DMA transfer */ - void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ -} dma_descriptor_t; - -/*! @brief DMA transfer configuration */ -typedef struct _dma_xfercfg -{ - bool valid; /*!< Descriptor is ready to transfer */ - bool reload; /*!< Reload channel configuration register after - current descriptor is exhausted */ - bool swtrig; /*!< Perform software trigger. Transfer if fired - when 'valid' is set */ - bool clrtrig; /*!< Clear trigger */ - bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */ - bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */ - uint8_t byteWidth; /*!< Byte width of data to transfer */ - uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */ - uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */ - uint16_t transferCount; /*!< Number of transfers */ -} dma_xfercfg_t; - -/*! @brief DMA channel priority */ -typedef enum _dma_priority -{ - kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ - kDMA_ChannelPriority1, /*!< Channel priority 1 */ - kDMA_ChannelPriority2, /*!< Channel priority 2 */ - kDMA_ChannelPriority3, /*!< Channel priority 3 */ - kDMA_ChannelPriority4, /*!< Channel priority 4 */ - kDMA_ChannelPriority5, /*!< Channel priority 5 */ - kDMA_ChannelPriority6, /*!< Channel priority 6 */ - kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ -} dma_priority_t; - -/*! @brief DMA interrupt flags */ -typedef enum _dma_int -{ - kDMA_IntA, /*!< DMA interrupt flag A */ - kDMA_IntB, /*!< DMA interrupt flag B */ - kDMA_IntError, /*!< DMA interrupt flag error */ -} dma_irq_t; - -/*! @brief DMA trigger type*/ -typedef enum _dma_trigger_type -{ - kDMA_NoTrigger = 0, /*!< Trigger is disabled */ - kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */ - kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | - DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ - kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */ - kDMA_RisingEdgeTrigger = - DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ -} dma_trigger_type_t; - -/*! @brief DMA trigger burst */ -typedef enum _dma_trigger_burst -{ - kDMA_SingleTransfer = 0, /*!< Single transfer */ - kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ - kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ - kDMA_EdgeBurstTransfer2 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ - kDMA_EdgeBurstTransfer4 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ - kDMA_EdgeBurstTransfer8 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ - kDMA_EdgeBurstTransfer16 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ - kDMA_EdgeBurstTransfer32 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ - kDMA_EdgeBurstTransfer64 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ - kDMA_EdgeBurstTransfer128 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ - kDMA_EdgeBurstTransfer256 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ - kDMA_EdgeBurstTransfer512 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ - kDMA_EdgeBurstTransfer1024 = - DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ -} dma_trigger_burst_t; - -/*! @brief DMA burst wrapping */ -typedef enum _dma_burst_wrap -{ - kDMA_NoWrap = 0, /*!< Wrapping is disabled */ - kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ - kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ - kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | - DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ -} dma_burst_wrap_t; - -/*! @brief DMA transfer type */ -typedef enum _dma_transfer_type -{ - kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */ - kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */ - kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/ - kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */ -} dma_transfer_type_t; - -/*! @brief DMA channel trigger */ -typedef struct _dma_channel_trigger -{ - dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */ - dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */ - dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */ -} dma_channel_trigger_t; - -/*! @brief DMA channel trigger */ -typedef struct _dma_channel_config -{ - void *srcStartAddr; /*!< Source data address */ - void *dstStartAddr; /*!< Destination data address */ - void *nextDesc; /*!< Chain custom descriptor */ - uint32_t xferCfg; /*!< channel transfer configurations */ - dma_channel_trigger_t *trigger; /*!< DMA trigger type */ - bool isPeriph; /*!< select the request type */ -} dma_channel_config_t; - -/*! @brief DMA transfer configuration */ -typedef struct _dma_transfer_config -{ - uint8_t *srcAddr; /*!< Source data address */ - uint8_t *dstAddr; /*!< Destination data address */ - uint8_t *nextDesc; /*!< Chain custom descriptor */ - dma_xfercfg_t xfercfg; /*!< Transfer options */ - bool isPeriph; /*!< DMA transfer is driven by peripheral */ -} dma_transfer_config_t; - -/*! @brief Callback for DMA */ -struct _dma_handle; - -/*! @brief Define Callback function for DMA. */ -typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode); - -/*! @brief DMA transfer handle structure */ -typedef struct _dma_handle -{ - dma_callback callback; /*!< Callback function. Invoked when transfer - of descriptor with interrupt flag finishes */ - void *userData; /*!< Callback function parameter */ - DMA_Type *base; /*!< DMA peripheral base address */ - uint8_t channel; /*!< DMA channel number */ -} dma_handle_t; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name DMA initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes DMA peripheral. - * - * This function enable the DMA clock, set descriptor table and - * enable DMA peripheral. - * - * @param base DMA peripheral base address. - */ -void DMA_Init(DMA_Type *base); - -/*! - * @brief Deinitializes DMA peripheral. - * - * This function gates the DMA clock. - * - * @param base DMA peripheral base address. - */ -void DMA_Deinit(DMA_Type *base); - -/*! - * @brief Install DMA descriptor memory. - * - * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong - * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has - * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. - * - * @param base DMA base address. - * @param addr DMA descriptor address - */ -void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr); - -/* @} */ -/*! - * @name DMA Channel Operation - * @{ - */ - -/*! -* @brief Return whether DMA channel is processing transfer -* -* @param base DMA peripheral base address. -* @param channel DMA channel number. -* @return True for active state, false otherwise. -*/ -static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false; -} - -/*! - * @brief Enables the interrupt source for the DMA transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1U << DMA_CHANNEL_INDEX(channel); -} - -/*! - * @brief Disables the interrupt source for the DMA transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1U << DMA_CHANNEL_INDEX(channel); -} - -/*! - * @brief Enable DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1U << DMA_CHANNEL_INDEX(channel); -} - -/*! - * @brief Disable DMA channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1U << DMA_CHANNEL_INDEX(channel); -} - -/*! - * @brief Set PERIPHREQEN of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; -} - -/*! - * @brief Get PERIPHREQEN value of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return True for enabled PeriphRq, false for disabled. - */ -static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; -} - -/*! - * @brief Set trigger settings of DMA channel. - * @deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param trigger trigger configuration. - */ -void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger); - -/*! - * @brief set channel config. - * - * This function provide a interface to configure channel configuration reisters. - * - * @param base DMA base address. - * @param channel DMA channel number. - * @param trigger channel configurations structure. -* @param isPeriph true is periph request, false is not. - */ -void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph); - -/*! - * @brief Gets the remaining bytes of the current DMA descriptor transfer. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return The number of bytes which have not been transferred yet. - */ -uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); - -/*! - * @brief Set priority of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param priority Channel priority value. - */ -static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - base->CHANNEL[channel].CFG = - (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); -} - -/*! - * @brief Get priority of channel configuration register. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @return Channel priority value. - */ -static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> - DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); -} - -/*! - * @brief Set channel configuration valid.. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_SetChannelConfigValid(DMA_Type *base, uint32_t channel) -{ - base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_CFGVALID_MASK; -} - -/*! - * @brief Do software trigger for the channel. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -static inline void DMA_DoChannelSoftwareTrigger(DMA_Type *base, uint32_t channel) -{ - base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; -} - -/*! - * @brief Load channel transfer configurations. - * - * @param base DMA peripheral base address. - * @param channel DMA channel number. - * @param xfer transfer configurations. - */ -static inline void DMA_LoadChannelTransferConfig(DMA_Type *base, uint32_t channel, uint32_t xfer) -{ - base->CHANNEL[channel].XFERCFG = xfer; -} - -/*! - * @brief Create application specific DMA descriptor - * to be used in a chain in transfer - * @deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor. - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcAddr Address of last item to transmit - * @param dstAddr Address of last item to receive. - * @param nextDesc Address of next descriptor in chain. - */ -void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc); - -/*! - * @brief setup dma descriptor - * - * @param desc DMA descriptor address. - * @param xfercfg Transfer configuration for DMA descriptor. - * @param srcStartAddr Start address of source address. - * @param dstStartAddr Start address of destination address. - * @param nextDesc Address of next descriptor in chain. - */ -void DMA_SetupDescriptor( - dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); - -/* @} */ - -/*! - * @name DMA Transactional Operation - * @{ - */ - -/*! - * @brief Abort running transfer by handle. - * - * This function aborts DMA transfer specified by handle. - * - * @param handle DMA handle pointer. - */ -void DMA_AbortTransfer(dma_handle_t *handle); - -/*! - * @brief Creates the DMA handle. - * - * This function is called if using transaction API for DMA. This function - * initializes the internal state of DMA handle. - * - * @param handle DMA handle pointer. The DMA handle stores callback function and - * parameters. - * @param base DMA peripheral base address. - * @param channel DMA channel number. - */ -void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel); - -/*! - * @brief Installs a callback function for the DMA transfer. - * - * This callback is called in DMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. - * - * @param handle DMA handle pointer. - * @param callback DMA callback function pointer. - * @param userData Parameter for callback function. - */ -void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData); - -/*! - * @brief Prepares the DMA transfer structure. - * @deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer. - * This function prepares the transfer configuration structure according to the user input. - * - * @param config The user configuration structure of type dma_transfer_t. - * @param srcAddr DMA transfer source address. - * @param dstAddr DMA transfer destination address. - * @param byteWidth DMA transfer destination address width(bytes). - * @param transferBytes DMA transfer bytes to be transferred. - * @param type DMA transfer type. - * @param nextDesc Chain custom descriptor to transfer. - * @note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in - * source address error(SAE). - */ -void DMA_PrepareTransfer(dma_transfer_config_t *config, - void *srcAddr, - void *dstAddr, - uint32_t byteWidth, - uint32_t transferBytes, - dma_transfer_type_t type, - void *nextDesc); - -/*! - * @brief Prepare channel transfer configurations. - * - * This function used to prepare channel transfer configurations. - * - * @param config Pointer to DMA channel transfer configuration structure. - * @param srcStartAddr source start address. - * @param dstStartAddr destination start address. - * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. - * @param type transfer type. - * @param trigger DMA channel trigger configurations. - * @param nextDesc address of next descriptor. - */ -void DMA_PrepareChannelTransfer(dma_channel_config_t *config, - void *srcStartAddr, - void *dstStartAddr, - uint32_t xferCfg, - dma_transfer_type_t type, - dma_channel_trigger_t *trigger, - void *nextDesc); - -/*! - * @brief Submits the DMA transfer request. - * @deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * @param handle DMA handle pointer. - * @param config Pointer to DMA transfer configuration structure. - * @retval kStatus_DMA_Success It means submit transfer request succeed. - * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config); - -/*! - * @brief Submits the DMA channel transfer request. - * - * This function submits the DMA transfer request according to the transfer configuration structure. - * If the user submits the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * This function should use together with DMA_PrepareChannelTransfer. - * - * @param handle DMA handle pointer. - * @param config Pointer to DMA channel transfer configuration structure. - * @retval kStatus_DMA_Success It means submit transfer request succeed. - * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config); - -/*! - * @brief DMA start transfer. - * - * This function enables the channel request. User can call this function after submitting the transfer request - * or before submitting the transfer request. - * - * @param handle DMA handle pointer. - */ -void DMA_StartTransfer(dma_handle_t *handle); - -/*! - * @brief DMA IRQ handler for descriptor transfer complete. - * - * This function clears the channel major interrupt flag and call - * the callback function if it is not NULL. - */ -void DMA_HandleIRQ(void); - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/* @} */ - -#endif /*_FSL_DMA_H_*/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_flexcomm.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_flexcomm.c deleted file mode 100644 index 8b8e72851f..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_flexcomm.c +++ /dev/null @@ -1,335 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! @brief Set the FLEXCOMM mode . */ -static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock); - -/*! @brief check whether flexcomm supports peripheral type */ -static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ -static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; - -/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ -static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; - -/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ -IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; - -/*! @brief Array to map FLEXCOMM instance number to base address. */ -static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief IDs of clock for each FLEXCOMM module */ -static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) -/*! @brief Pointers to FLEXCOMM resets for each instance. */ -static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* check whether flexcomm supports peripheral type */ -static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) -{ - if (periph == FLEXCOMM_PERIPH_NONE) - { - return true; - } - else if (periph <= FLEXCOMM_PERIPH_I2S_TX) - { - return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > (uint32_t)0 ? true : false; - } - else if (periph == FLEXCOMM_PERIPH_I2S_RX) - { - return (base->PSELID & (1 << 7)) > (uint32_t)0 ? true : false; - } - else - { - return false; - } -} - -/* Get the index corresponding to the FLEXCOMM */ -/*! brief Returns instance number for FLEXCOMM module with given base address. */ -uint32_t FLEXCOMM_GetInstance(void *base) -{ - int i; - - for (i = 0; i < FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) - { - if ((uint32_t)base == s_flexcommBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0; -} - -/* Changes FLEXCOMM mode */ -static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) -{ - /* Check whether peripheral type is present */ - if (!FLEXCOMM_PeripheralIsPresent(base, periph)) - { - return kStatus_OutOfRange; - } - - /* Flexcomm is locked to different peripheral type than expected */ - if ((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) && ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != periph)) - { - return kStatus_Fail; - } - - /* Check if we are asked to lock */ - if (lock) - { - base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; - } - else - { - base->PSELID = (uint32_t)periph; - } - - return kStatus_Success; -} - -/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) -{ - int idx = FLEXCOMM_GetInstance(base); - - if (idx < 0) - { - return kStatus_InvalidArgument; - } - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the peripheral clock */ - CLOCK_EnableClock(s_flexcommClocks[idx]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) - /* Reset the FLEXCOMM module */ - RESET_PeripheralReset(s_flexcommResets[idx]); -#endif - - /* Set the FLEXCOMM to given peripheral */ - return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); -} - -/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM - * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(base); - - /* Clear handler first to avoid execution of the handler with wrong handle */ - s_flexcommIrqHandler[instance] = NULL; - s_flexcommHandle[instance] = handle; - s_flexcommIrqHandler[instance] = handler; -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(FLEXCOMM0) -void FLEXCOMM0_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[0]); - s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM1) -void FLEXCOMM1_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[1]); - s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM2) -void FLEXCOMM2_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[2]); - s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM3) -void FLEXCOMM3_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[3]); - s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM4) -void FLEXCOMM4_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[4]); - s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#endif - -#if defined(FLEXCOMM5) -void FLEXCOMM5_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[5]); - s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM6) -void FLEXCOMM6_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[6]); - s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM7) -void FLEXCOMM7_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[7]); - s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM8) -void FLEXCOMM8_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[8]); - s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM9) -void FLEXCOMM9_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[9]); - s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM14) -void FLEXCOMM14_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM14); - assert(s_flexcommIrqHandler[instance]); - s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM15) -void FLEXCOMM15_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM14); - assert(s_flexcommIrqHandler[instance]); - s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_flexcomm.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_flexcomm.h deleted file mode 100644 index 915e3b81b1..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_flexcomm.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_FLEXCOMM_H_ -#define _FSL_FLEXCOMM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup flexcomm_driver - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexCOMM driver version 2.0.0. */ -#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief FLEXCOMM peripheral modes. */ -typedef enum -{ - FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ - FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ - FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ - FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ - FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ - FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ -} FLEXCOMM_PERIPH_T; - -/*! @brief Typedef for interrupt handler. */ -typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); - -/*! @brief Array with IRQ number for each FLEXCOMM module. */ -extern IRQn_Type const kFlexcommIrqs[]; - -/*! @brief Returns instance number for FLEXCOMM module with given base address. */ -uint32_t FLEXCOMM_GetInstance(void *base); - -/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); - -/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM - * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle); - -/*@}*/ - -#endif /* _FSL_FLEXCOMM_H_*/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_gint.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_gint.c deleted file mode 100644 index da60c3ccb7..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_gint.c +++ /dev/null @@ -1,392 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_gint.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.gint" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to GINT bases for each instance. */ -static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Clocks for each instance. */ -static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/*! @brief Resets for each instance. */ -static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS; -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/* @brief Irq number for each instance */ -static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS; - -/*! @brief Callback function array for GINT(s). */ -static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t GINT_GetInstance(GINT_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++) - { - if (s_gintBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_gintBases)); - - return instance; -} - -/*! - * brief Initialize GINT peripheral. - - * This function initializes the GINT peripheral and enables the clock. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_Init(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - s_gintCallback[instance] = NULL; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the peripheral clock */ - CLOCK_EnableClock(s_gintClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_gintResets[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -} - -/*! - * brief Setup GINT peripheral control parameters. - - * This function sets the control parameters of GINT peripheral. - * - * param base Base address of the GINT peripheral. - * param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. - * param trig Controls if the enabled inputs are level or edge sensitive based on polarity. - * param callback This function is called when configured group interrupt is generated. - * - * retval None. - */ -void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig)); - - /* Save callback pointer */ - s_gintCallback[instance] = callback; -} - -/*! - * brief Get GINT peripheral control parameters. - - * This function returns the control parameters of GINT peripheral. - * - * param base Base address of the GINT peripheral. - * param comb Pointer to store combine input value. - * param trig Pointer to store trigger value. - * param callback Pointer to store callback function. - * - * retval None. - */ -void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - *comb = (gint_comb_t)((base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT); - *trig = (gint_trig_t)((base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT); - *callback = s_gintCallback[instance]; -} - -/*! - * brief Configure GINT peripheral pins. - - * This function enables and controls the polarity of enabled pin(s) of a given port. - * - * param base Base address of the GINT peripheral. - * param port Port number. - * param polarityMask Each bit position selects the polarity of the corresponding enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * param enableMask Each bit position selects if the corresponding pin is enabled or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * retval None. - */ -void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask) -{ - base->PORT_POL[port] = polarityMask; - base->PORT_ENA[port] = enableMask; -} - -/*! - * brief Get GINT peripheral pin configuration. - - * This function returns the pin configuration of a given port. - * - * param base Base address of the GINT peripheral. - * param port Port number. - * param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding - enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled - or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * retval None. - */ -void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask) -{ - *polarityMask = base->PORT_POL[port]; - *enableMask = base->PORT_ENA[port]; -} - -/*! - * brief Enable callback. - - * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_EnableCallback(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - /* If GINT is configured in "AND" mode a spurious interrupt is generated. - Clear status and pending interrupt before enabling the irq in NVIC. */ - GINT_ClrStatus(base); - NVIC_ClearPendingIRQ(s_gintIRQ[instance]); - EnableIRQ(s_gintIRQ[instance]); -} - -/*! - * brief Disable callback. - - * This function disables the interrupt for the selected GINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * param base Base address of the peripheral. - * - * retval None. - */ -void GINT_DisableCallback(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - DisableIRQ(s_gintIRQ[instance]); - GINT_ClrStatus(base); - NVIC_ClearPendingIRQ(s_gintIRQ[instance]); -} - -/*! - * brief Deinitialize GINT peripheral. - - * This function disables the GINT clock. - * - * param base Base address of the GINT peripheral. - * - * retval None. - */ -void GINT_Deinit(GINT_Type *base) -{ - uint32_t instance; - - instance = GINT_GetInstance(base); - - /* Cleanup */ - GINT_DisableCallback(base); - s_gintCallback[instance] = NULL; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_gintResets[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the peripheral clock */ - CLOCK_DisableClock(s_gintClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(GINT0) -void GINT0_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[0] != NULL) - { - s_gintCallback[0](); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(GINT1) -void GINT1_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[1] != NULL) - { - s_gintCallback[1](); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(GINT2) -void GINT2_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[2] != NULL) - { - s_gintCallback[2](); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(GINT3) -void GINT3_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[3] != NULL) - { - s_gintCallback[3](); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(GINT4) -void GINT4_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[4] != NULL) - { - s_gintCallback[4](); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(GINT5) -void GINT5_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[5] != NULL) - { - s_gintCallback[5](); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(GINT6) -void GINT6_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[6] != NULL) - { - s_gintCallback[6](); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(GINT7) -void GINT7_DriverIRQHandler(void) -{ - /* Clear interrupt before callback */ - s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK; - /* Call user function */ - if (s_gintCallback[7] != NULL) - { - s_gintCallback[7](); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_gint.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_gint.h deleted file mode 100644 index 462618e5ea..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_gint.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_GINT_H_ -#define _FSL_GINT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup gint_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ -/*@}*/ - -/*! @brief GINT combine inputs type */ -typedef enum _gint_comb -{ - kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */ - kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */ -} gint_comb_t; - -/*! @brief GINT trigger type */ -typedef enum _gint_trig -{ - kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */ - kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */ -} gint_trig_t; - -/* @brief GINT port type */ -typedef enum _gint_port -{ - kGINT_Port0 = 0U, - kGINT_Port1 = 1U, -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U) - kGINT_Port2 = 2U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U) - kGINT_Port3 = 3U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U) - kGINT_Port4 = 4U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U) - kGINT_Port5 = 5U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U) - kGINT_Port6 = 6U, -#endif -#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U) - kGINT_Port7 = 7U, -#endif -} gint_port_t; - -/*! @brief GINT Callback function. */ -typedef void (*gint_cb_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize GINT peripheral. - - * This function initializes the GINT peripheral and enables the clock. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_Init(GINT_Type *base); - -/*! - * @brief Setup GINT peripheral control parameters. - - * This function sets the control parameters of GINT peripheral. - * - * @param base Base address of the GINT peripheral. - * @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. - * @param trig Controls if the enabled inputs are level or edge sensitive based on polarity. - * @param callback This function is called when configured group interrupt is generated. - * - * @retval None. - */ -void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback); - -/*! - * @brief Get GINT peripheral control parameters. - - * This function returns the control parameters of GINT peripheral. - * - * @param base Base address of the GINT peripheral. - * @param comb Pointer to store combine input value. - * @param trig Pointer to store trigger value. - * @param callback Pointer to store callback function. - * - * @retval None. - */ -void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback); - -/*! - * @brief Configure GINT peripheral pins. - - * This function enables and controls the polarity of enabled pin(s) of a given port. - * - * @param base Base address of the GINT peripheral. - * @param port Port number. - * @param polarityMask Each bit position selects the polarity of the corresponding enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * @param enableMask Each bit position selects if the corresponding pin is enabled or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * @retval None. - */ -void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask); - -/*! - * @brief Get GINT peripheral pin configuration. - - * This function returns the pin configuration of a given port. - * - * @param base Base address of the GINT peripheral. - * @param port Port number. - * @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding - enabled pin. - * 0 = The pin is active LOW. 1 = The pin is active HIGH. - * @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled - or not. - * 0 = The pin is disabled. 1 = The pin is enabled. - * - * @retval None. - */ -void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask); - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_EnableCallback(GINT_Type *base); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected GINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * @param base Base address of the peripheral. - * - * @retval None. - */ -void GINT_DisableCallback(GINT_Type *base); - -/*! - * @brief Clear GINT status. - - * This function clears the GINT status bit. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -static inline void GINT_ClrStatus(GINT_Type *base) -{ - base->CTRL |= GINT_CTRL_INT_MASK; -} - -/*! - * @brief Get GINT status. - - * This function returns the GINT status. - * - * @param base Base address of the GINT peripheral. - * - * @retval status = 0 No group interrupt request. = 1 Group interrupt request active. - */ -static inline uint32_t GINT_GetStatus(GINT_Type *base) -{ - return (base->CTRL & GINT_CTRL_INT_MASK); -} - -/*! - * @brief Deinitialize GINT peripheral. - - * This function disables the GINT clock. - * - * @param base Base address of the GINT peripheral. - * - * @retval None. - */ -void GINT_Deinit(GINT_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_GINT_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_gpio.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_gpio.c deleted file mode 100644 index ae5bd6f4a2..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_gpio.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_gpio.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map FGPIO instance number to clock name. */ -static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) -/*! @brief Pointers to GPIO resets for each instance. */ -static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; -#endif -/******************************************************************************* -* Prototypes -************ ******************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * brief Initializes the GPIO peripheral. - * - * This function ungates the GPIO clock. - * - * param base GPIO peripheral base pointer. - * param port GPIO port number. - */ -void GPIO_PortInit(GPIO_Type *base, uint32_t port) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - assert(port < ARRAY_SIZE(s_gpioClockName)); - - /* Upgate the GPIO clock */ - CLOCK_EnableClock(s_gpioClockName[port]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) - /* Reset the GPIO module */ - RESET_PeripheralReset(s_gpioResets[port]); -#endif -} - -/*! - * brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * code - * // Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * //Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * endcode - * - * param base GPIO peripheral base pointer(Typically GPIO) - * param port GPIO port number - * param pin GPIO pin number - * param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) -{ - if (config->pinDirection == kGPIO_DigitalInput) - { -#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) - base->DIRCLR[port] = 1U << pin; -#else - base->DIR[port] &= ~(1U << pin); -#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ - } - else - { - /* Set default output value */ - if (config->outputLogic == 0U) - { - base->CLR[port] = (1U << pin); - } - else - { - base->SET[port] = (1U << pin); - } -/* Set pin direction */ -#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) - base->DIRSET[port] = 1U << pin; -#else - base->DIR[port] |= 1U << pin; -#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ - } -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_gpio.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_gpio.h deleted file mode 100644 index f61b40d0d7..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_gpio.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _LPC_GPIO_H_ -#define _LPC_GPIO_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_gpio - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPC GPIO driver version 2.1.3. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) -/*@}*/ - -/*! @brief LPC GPIO direction definition */ -typedef enum _gpio_pin_direction -{ - kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ - kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ -} gpio_pin_direction_t; - -/*! - * @brief The GPIO pin configuration structure. - * - * Every pin can only be configured as either output pin or input pin at a time. - * If configured as a input pin, then leave the outputConfig unused. - */ -typedef struct _gpio_pin_config -{ - gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ - /* Output configurations, please ignore if configured as a input one */ - uint8_t outputLogic; /*!< Set default output logic, no use in input */ -} gpio_pin_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @name GPIO Configuration */ -/*@{*/ - -/*! - * @brief Initializes the GPIO peripheral. - * - * This function ungates the GPIO clock. - * - * @param base GPIO peripheral base pointer. - * @param port GPIO port number. - */ -void GPIO_PortInit(GPIO_Type *base, uint32_t port); - -/*! - * @brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * @code - * // Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * //Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * @endcode - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); - -/*@}*/ - -/*! @name GPIO Output Operations */ -/*@{*/ - -/*! - * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param output GPIO pin output logic level. - * - 0: corresponding pin output low-logic level. - * - 1: corresponding pin output high-logic level. - */ -static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) -{ - base->B[port][pin] = output; -} - -/*@}*/ -/*! @name GPIO Input Operations */ -/*@{*/ - -/*! - * @brief Reads the current input value of the GPIO PIN. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @retval GPIO port input value - * - 0: corresponding pin input low-logic level. - * - 1: corresponding pin input high-logic level. - */ -static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) -{ - return (uint32_t)base->B[port][pin]; -} - -/*@}*/ - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->SET[port] = mask; -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->CLR[port] = mask; -} - -/*! - * @brief Reverses current output logic of the multiple GPIO pins. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->NOT[port] = mask; -} - -/*@}*/ - -/*! - * @brief Reads the current input value of the whole GPIO port. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - */ -static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->PIN[port]; -} - -/*@}*/ -/*! @name GPIO Mask Operations */ -/*@{*/ - -/*! - * @brief Sets port mask, 0 - enable pin, 1 - disable pin. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->MASK[port] = mask; -} - -/*! - * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param output GPIO port output value. - */ -static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) -{ - base->MPIN[port] = output; -} - -/*! - * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be - * affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @retval masked GPIO port value - */ -static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->MPIN[port]; -} - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* _LPC_GPIO_H_*/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_hashcrypt.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_hashcrypt.c deleted file mode 100644 index f1caea979a..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_hashcrypt.c +++ /dev/null @@ -1,1307 +0,0 @@ -/* - * Copyright 2017-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_hashcrypt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.hashcrypt" -#endif - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*!< SHA-1 and SHA-256 block size */ -#define SHA_BLOCK_SIZE 64 -/*!< max number of blocks that can be proccessed in one run (master mode) */ -#define SHA_MASTER_MAX_BLOCKS 2048 - -/*!< Use standard C library memcpy */ -#define hashcrypt_memcpy memcpy - -/*! Internal states of the HASH creation process */ -typedef enum _hashcrypt_sha_algo_state -{ - kHASHCRYPT_HashInit = 1u, /*!< Init state, the NEW bit in SHA Control register has not been written yet. */ - kHASHCRYPT_HashUpdate, /*!< Update state, DIGEST registers contain running hash, NEW bit in SHA control register has - been written. */ -} hashcrypt_sha_algo_state_t; - -/*! 64-byte block represented as byte array of 16 32-bit words */ -typedef union _sha_hash_block -{ - uint32_t w[SHA_BLOCK_SIZE / 4]; /*!< array of 32-bit words */ - uint8_t b[SHA_BLOCK_SIZE]; /*!< byte array */ -} hashcrypt_sha_block_t; - -/*! internal sha context structure */ -typedef struct _hashcrypt_sha_ctx_internal -{ - hashcrypt_sha_block_t blk; /*!< memory buffer. only full 64-byte blocks are written to SHA during hash updates */ - size_t blksz; /*!< number of valid bytes in memory buffer */ - hashcrypt_algo_t algo; /*!< selected algorithm from the set of supported algorithms */ - hashcrypt_sha_algo_state_t state; /*!< finite machine state of the hash software process */ - size_t fullMessageSize; /*!< track message size during SHA_Update(). The value is used for padding. */ - uint32_t remainingBlcks; /*!< number of remaining blocks to process in AHB master mode */ - hashcrypt_callback_t hashCallback; /*!< pointer to HASH callback function */ - void - *userData; /*!< user data to be passed as an argument to callback function, once callback is invoked from isr */ -} hashcrypt_sha_ctx_internal_t; - -/*!< SHA-1 and SHA-256 digest length in bytes */ -enum _hashcrypt_sha_digest_len -{ - kHASHCRYPT_OutLenSha1 = 20u, - kHASHCRYPT_OutLenSha256 = 32u, -}; - -/*!< pointer to hash context structure used by isr */ -static hashcrypt_hash_ctx_t *s_ctx; - -/*!< macro for checking build time condition. It is used to assure the hashcrypt_sha_ctx_internal_t can fit into - * hashcrypt_hash_ctx_t */ -#define BUILD_ASSERT(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused)) - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * @brief Swap bytes withing 32-bit word. - * - * This function changes endianess of a 32-bit word. - * - * @param in 32-bit unsigned integer - * @return 32-bit unsigned integer with different endianess (big endian to little endian and vice versa). - */ - -#define swap_bytes(in) __REV(in) - -/*! - * @brief Increment a 16 byte integer. - * - * This function increments by one a 16 byte integer. - * - * @param input Pointer to a 16 byte integer to be incremented by one. - */ -static void ctrIncrement(uint8_t *input) -{ - int i = 15; - while (input[i] == (uint8_t)0xFFu) - { - input[i] = (uint8_t)0x00u; - i--; - if (i < 0) - { - return; - } - } - - if (i >= 0) - { - input[i] += (uint8_t)1u; - } -} - -/*! - * @brief LDM to SHA engine INDATA and ALIAS registers. - * - * This function writes 16 words starting from the src address (must be word aligned) - * to the dst address. Dst address does not increment (destination is peripheral module register INDATA). - * Src address increments to load 16 consecutive words. - * - * @param dst peripheral register address (word aligned) - * @param src address of the input 512-bit block (16 words) (word aligned) - * - */ -__STATIC_FORCEINLINE void hashcrypt_sha_ldm_stm_16_words(HASHCRYPT_Type *base, const uint32_t *src) -{ - /* - typedef struct _one_block - { - uint32_t a[8]; - } one_block_t; - - volatile one_block_t *ldst = (void *)(uintptr_t)(&base->INDATA); - one_block_t *lsrc = (void *)(uintptr_t)src; - *ldst = lsrc[0]; - *ldst = lsrc[1]; - */ - base->MEMADDR = FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET | HASHCRYPT_MEMADDR_BASE(src); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(1); -} - -/*! - * @brief Loads data to Hashcrypt engine INDATA register. - * - * This function writes desired number of bytes starting from the src address (must be word aligned) - * to the dst address. Dst address does not increment (destination is peripheral module register INDATA). - * Src address increments to load consecutive words. - * - * @param dst peripheral register address (word aligned) - * @param src address of the input block (word aligned) - * @param size number of bytes to write (word aligned) - * - */ -__STATIC_INLINE void hashcrypt_load_data(HASHCRYPT_Type *base, const uint32_t *src, size_t size) -{ - if (size >= sizeof(uint32_t)) - { - base->INDATA = src[0]; - size -= sizeof(uint32_t); - } - - for (int i = 0; i < size / 4; i++) - { - base->ALIAS[i] = src[i + 1]; - } -} - -/*! - * @brief Read OUTDATA registers. - * - * This function copies OUTDATA to output buffer. - * - * @param base Hachcrypt peripheral base address. - * @param[out] output Output buffer. - * @param Number of bytes to copy. - */ -static void hashcrypt_get_data(HASHCRYPT_Type *base, uint32_t *output, size_t outputSize) -{ - uint32_t digest[8]; - - while (0 == (base->STATUS & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK)) - { - } - - for (int i = 0; i < 8; i++) - { - digest[i] = swap_bytes(base->OUTDATA0[i]); - } - - if (outputSize > sizeof(digest)) - { - outputSize = sizeof(digest); - } - hashcrypt_memcpy(output, digest, outputSize); -} - -/*! - * @brief Initialize the Hashcrypt engine for new operation. - * - * This function sets NEW and MODE fields in Hashcrypt Control register to start new operation. - * - * @param base Hashcrypt peripheral base address. - * @param hashcrypt_algo_t Internal context. - */ -static void hashcrypt_engine_init(HASHCRYPT_Type *base, hashcrypt_algo_t algo) -{ - /* NEW bit must be set before we switch from previous mode otherwise new mode will not work correctly */ - base->CTRL = HASHCRYPT_CTRL_NEW_HASH(1); - base->CTRL = HASHCRYPT_CTRL_MODE(algo) | HASHCRYPT_CTRL_NEW_HASH(1); -} - -/*! - * @brief Loads user key to INDATA register. - * - * This function writes user key stored in handle into HashCrypt INDATA register. - * - * @param base Hashcrypt peripheral base address. - * @param handle Handle used for this request. - */ -static void hashcrypt_aes_load_userKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle) -{ - size_t keySize = 0; - - switch (handle->keySize) - { - case kHASHCRYPT_Aes128: - keySize = 16; - break; - case kHASHCRYPT_Aes192: - keySize = 24; - break; - case kHASHCRYPT_Aes256: - keySize = 32; - break; - default: - break; - } - if (keySize == 0) - { - return; - } - hashcrypt_load_data(base, &handle->keyWord[0], keySize); -} - -/*! - * @brief Performs AES encryption/decryption of one data block. - * - * This function encrypts/decrypts one block of data with specified size. - * - * @param base Hashcrypt peripheral base address. - * @param input input data - * @param output output data - * @param size size of data block to process in bytes (must be 16bytes multiple). - */ -static status_t hashcrypt_aes_one_block(HASHCRYPT_Type *base, const uint8_t *input, uint8_t *output, size_t size) -{ - status_t status = kStatus_Fail; - int idx = 0; - - /* we use AHB master mode as much as possible */ - /* however, it can work only with aligned input data */ - /* so, if unaligned, we do memcpy to temp buffer on stack, which is aligned, and use AHB mode to read data in */ - /* then we read data back to it and do memcpy to the output buffer */ - if (((uint32_t)input & 0x3u) || ((uint32_t)output & 0x3u)) - { - uint32_t temp[256 / sizeof(uint32_t)]; - int cnt = 0; - while (size) - { - size_t actSz = size >= 256u ? 256u : size; - size_t actSzOrig = actSz; - memcpy(temp, input + 256 * cnt, actSz); - size -= actSz; - base->MEMADDR = FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET | HASHCRYPT_MEMADDR_BASE(temp); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(actSz / 16); - int outidx = 0; - while (actSz) - { - while (0 == (base->STATUS & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK)) - { - } - for (int i = 0; i < 4; i++) - { - (temp + outidx)[i] = swap_bytes(base->OUTDATA0[i]); - } - outidx += HASHCRYPT_AES_BLOCK_SIZE / 4; - actSz -= HASHCRYPT_AES_BLOCK_SIZE; - } - memcpy(output + 256 * cnt, temp, actSzOrig); - cnt++; - } - } - else - { - base->MEMADDR = FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET | HASHCRYPT_MEMADDR_BASE(input); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(size / 16); - while (size >= HASHCRYPT_AES_BLOCK_SIZE) - { - /* Get result */ - while (0 == (base->STATUS & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK)) - { - } - - for (int i = 0; i < 4; i++) - { - ((uint32_t *)output + idx)[i] = swap_bytes(base->OUTDATA0[i]); - } - - idx += HASHCRYPT_AES_BLOCK_SIZE / 4; - size -= HASHCRYPT_AES_BLOCK_SIZE; - } - } - - if (0 == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Check validity of algoritm. - * - * This function checks the validity of input argument. - * - * @param algo Tested algorithm value. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t hashcrypt_sha_check_input_alg(HASHCRYPT_Type *base, hashcrypt_algo_t algo) -{ - if ((algo == kHASHCRYPT_Sha1) || (algo == kHASHCRYPT_Sha256)) - { - return kStatus_Success; - } - - if ((algo == kHASHCRYPT_Sha512) && (base->CONFIG & HASHCRYPT_CONFIG_SHA512_MASK)) - { - return kStatus_Success; - } - - return kStatus_InvalidArgument; -} - -/*! - * @brief Check validity of input arguments. - * - * This function checks the validity of input arguments. - * - * @param base SHA peripheral base address. - * @param ctx Memory buffer given by user application where the SHA_Init/SHA_Update/SHA_Finish store context. - * @param algo Tested algorithm value. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t hashcrypt_sha_check_input_args(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo) -{ - /* Check validity of input algorithm */ - if (kStatus_Success != hashcrypt_sha_check_input_alg(base, algo)) - { - return kStatus_InvalidArgument; - } - - if ((NULL == ctx) || (NULL == base)) - { - return kStatus_InvalidArgument; - } - - return kStatus_Success; -} - -/*! - * @brief Check validity of internal software context. - * - * This function checks if the internal context structure looks correct. - * - * @param ctxInternal Internal context. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t hashcrypt_sha_check_context(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ - if ((NULL == ctxInternal) || (kStatus_Success != hashcrypt_sha_check_input_alg(base, ctxInternal->algo))) - { - return kStatus_InvalidArgument; - } - return kStatus_Success; -} - -/*! - * @brief Load 512-bit block (16 words) into SHA engine. - * - * This function aligns the input block and moves it into SHA engine INDATA. - * CPU polls the WAITING bit and then moves data by using LDM and STM instructions. - * - * @param base SHA peripheral base address. - * @param blk 512-bit block - */ -static void hashcrypt_sha_one_block(HASHCRYPT_Type *base, const uint8_t *blk) -{ - uint32_t temp[SHA_BLOCK_SIZE / sizeof(uint32_t)]; - const uint32_t *actBlk; - - /* make sure the 512-bit block is word aligned */ - if ((uintptr_t)blk & 0x3u) - { - hashcrypt_memcpy(temp, blk, SHA_BLOCK_SIZE); - actBlk = (const uint32_t *)(uintptr_t)temp; - } - else - { - actBlk = (const uint32_t *)(uintptr_t)blk; - } - - /* poll waiting. */ - while (0 == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) - { - } - /* feed INDATA (and ALIASes). use STM instruction. */ - hashcrypt_sha_ldm_stm_16_words(base, actBlk); -} - -/*! - * @brief Adds message to current hash. - * - * This function merges the message to fill the internal buffer, empties the internal buffer if - * it becomes full, then process all remaining message data. - * - * - * @param base SHA peripheral base address. - * @param ctxInternal Internal context. - * @param message Input message. - * @param messageSize Size of input message in bytes. - * @return kStatus_Success. - */ -static status_t hashcrypt_sha_process_message_data(HASHCRYPT_Type *base, - hashcrypt_sha_ctx_internal_t *ctxInternal, - const uint8_t *message, - size_t messageSize) -{ - /* first fill the internal buffer to full block */ - if (ctxInternal->blksz) - { - size_t toCopy = SHA_BLOCK_SIZE - ctxInternal->blksz; - hashcrypt_memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy); - message += toCopy; - messageSize -= toCopy; - - /* process full internal block */ - hashcrypt_sha_one_block(base, &ctxInternal->blk.b[0]); - } - - /* process all full blocks in message[] */ - if (messageSize >= SHA_BLOCK_SIZE) - { - if ((uintptr_t)message & 0x3u) - { - while (messageSize >= SHA_BLOCK_SIZE) - { - hashcrypt_sha_one_block(base, message); - message += SHA_BLOCK_SIZE; - messageSize -= SHA_BLOCK_SIZE; - } - } - else - { - /* poll waiting. */ - while (0 == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) - { - } - uint32_t blkNum = (messageSize >> 6); /* div by 64 bytes */ - uint32_t blkBytes = blkNum * 64u; /* number of bytes in 64 bytes blocks */ - base->MEMADDR = FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET | HASHCRYPT_MEMADDR_BASE(message); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(blkNum); - message += blkBytes; - messageSize -= blkBytes; - while (0 == (base->STATUS & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK)) - { - } - } - } - - /* copy last incomplete message bytes into internal block */ - hashcrypt_memcpy(&ctxInternal->blk.b[0], message, messageSize); - ctxInternal->blksz = messageSize; - return kStatus_Success; -} - -/*! - * @brief Finalize the running hash to make digest. - * - * This function empties the internal buffer, adds padding bits, and generates final digest. - * - * @param base SHA peripheral base address. - * @param ctxInternal Internal context. - * @return kStatus_Success. - */ -static status_t hashcrypt_sha_finalize(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) -{ - hashcrypt_sha_block_t lastBlock; - - memset(&lastBlock, 0, sizeof(hashcrypt_sha_block_t)); - - /* this is last call, so need to flush buffered message bytes along with padding */ - if (ctxInternal->blksz <= 55u) - { - /* last data is 440 bits or less. */ - hashcrypt_memcpy(&lastBlock.b[0], &ctxInternal->blk.b[0], ctxInternal->blksz); - lastBlock.b[ctxInternal->blksz] = (uint8_t)0x80U; - lastBlock.w[SHA_BLOCK_SIZE / 4 - 1] = swap_bytes(8u * ctxInternal->fullMessageSize); - hashcrypt_sha_one_block(base, &lastBlock.b[0]); - } - else - { - if (ctxInternal->blksz < SHA_BLOCK_SIZE) - { - ctxInternal->blk.b[ctxInternal->blksz] = (uint8_t)0x80U; - for (uint32_t i = ctxInternal->blksz + 1u; i < SHA_BLOCK_SIZE; i++) - { - ctxInternal->blk.b[i] = 0; - } - } - else - { - lastBlock.b[0] = (uint8_t)0x80U; - } - - hashcrypt_sha_one_block(base, &ctxInternal->blk.b[0]); - lastBlock.w[SHA_BLOCK_SIZE / 4 - 1] = swap_bytes(8u * ctxInternal->fullMessageSize); - hashcrypt_sha_one_block(base, &lastBlock.b[0]); - } - /* poll wait for final digest */ - while (0 == (base->STATUS & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK)) - { - } - return kStatus_Success; -} - -/*! - * brief Create HASH on given data - * - * Perform the full SHA in one function call. The function is blocking. - * - * param base HASHCRYPT peripheral base address - * param algo Underlaying algorithm to use for hash computation. - * param input Input data - * param inputSize Size of input data in bytes - * param[out] output Output hash data - * param[out] outputSize Output parameter storing the size of the output hash in bytes - * return Status of the one call hash operation. - */ -status_t HASHCRYPT_SHA(HASHCRYPT_Type *base, - hashcrypt_algo_t algo, - const uint8_t *input, - size_t inputSize, - uint8_t *output, - size_t *outputSize) -{ - hashcrypt_hash_ctx_t hashCtx; - status_t status; - - status = HASHCRYPT_SHA_Init(base, &hashCtx, algo); - if (status != kStatus_Success) - { - return status; - } - - status = HASHCRYPT_SHA_Update(base, &hashCtx, input, inputSize); - if (status != kStatus_Success) - { - return status; - } - - status = HASHCRYPT_SHA_Finish(base, &hashCtx, output, outputSize); - - return status; -} - -/*! - * brief Initialize HASH context - * - * This function initializes the HASH. - * - * param base HASHCRYPT peripheral base address - * param[out] ctx Output hash context - * param algo Underlaying algorithm to use for hash computation. - * return Status of initialization - */ -status_t HASHCRYPT_SHA_Init(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo) -{ - status_t status; - - hashcrypt_sha_ctx_internal_t *ctxInternal; - /* compile time check for the correct structure size */ - BUILD_ASSERT(sizeof(hashcrypt_hash_ctx_t) >= sizeof(hashcrypt_sha_ctx_internal_t), hashcrypt_hash_ctx_t_size); - - status = hashcrypt_sha_check_input_args(base, ctx, algo); - if (status != kStatus_Success) - { - return status; - } - - /* set algorithm in context struct for later use */ - ctxInternal = (hashcrypt_sha_ctx_internal_t *)ctx; - ctxInternal->algo = algo; - ctxInternal->blksz = 0u; -#ifdef HASHCRYPT_SHA_DO_WIPE_CONTEXT - for (int i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++) - { - ctxInternal->blk.w[i] = 0u; - } -#endif /* HASHCRYPT_SHA_DO_WIPE_CONTEXT */ - ctxInternal->state = kHASHCRYPT_HashInit; - ctxInternal->fullMessageSize = 0; - return kStatus_Success; -} - -/*! - * brief Add data to current HASH - * - * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be - * hashed. The functions blocks. If it returns kStatus_Success, the running hash - * has been updated (HASHCRYPT has processed the input data), so the memory at \p input pointer - * can be released back to system. The HASHCRYPT context buffer is updated with the running hash - * and with all necessary information to support possible context switch. - * - * param base HASHCRYPT peripheral base address - * param[in,out] ctx HASH context - * param input Input data - * param inputSize Size of input data in bytes - * return Status of the hash update operation - */ -status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize) -{ - bool isUpdateState; - status_t status; - hashcrypt_sha_ctx_internal_t *ctxInternal; - size_t blockSize; - - if (inputSize == 0) - { - return kStatus_Success; - } - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)ctx; -#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT - status = hashcrypt_sha_check_context(base, ctxInternal); - if (kStatus_Success != status) - { - return status; - } -#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ - - ctxInternal->fullMessageSize += inputSize; - blockSize = SHA_BLOCK_SIZE; - /* if we are still less than 64 bytes, keep only in context */ - if ((ctxInternal->blksz + inputSize) <= blockSize) - { - hashcrypt_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize); - ctxInternal->blksz += inputSize; - return kStatus_Success; - } - else - { - isUpdateState = ctxInternal->state == kHASHCRYPT_HashUpdate; - if (!isUpdateState) - { - /* start NEW hash */ - hashcrypt_engine_init(base, ctxInternal->algo); - ctxInternal->state = kHASHCRYPT_HashUpdate; - } - } - - /* process message data */ - status = hashcrypt_sha_process_message_data(base, ctxInternal, input, inputSize); - return status; -} - -/*! - * brief Finalize hashing - * - * Outputs the final hash (computed by HASHCRYPT_HASH_Update()) and erases the context. - * - * param base HASHCRYPT peripheral base address - * param[in,out] ctx Input hash context - * param[out] output Output hash data - * param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of - * output[] buffer. On function return, it stores the number of updated output bytes. - * return Status of the hash finish operation - */ -status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize) -{ - size_t algOutSize = 0; - status_t status; - hashcrypt_sha_ctx_internal_t *ctxInternal; -#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT - uint32_t *ctxW; - uint32_t i; -#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ - - if (output == NULL) - { - return kStatus_InvalidArgument; - } - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)ctx; -#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT - status = hashcrypt_sha_check_context(base, ctxInternal); - if (kStatus_Success != status) - { - return status; - } -#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ - - if (ctxInternal->state == kHASHCRYPT_HashInit) - { - hashcrypt_engine_init(base, ctxInternal->algo); - } - - size_t outSize = 0u; - - /* compute algorithm output length */ - switch (ctxInternal->algo) - { - case kHASHCRYPT_Sha1: - outSize = kHASHCRYPT_OutLenSha1; - break; - case kHASHCRYPT_Sha256: - outSize = kHASHCRYPT_OutLenSha256; - break; - default: - break; - } - algOutSize = outSize; - - /* flush message last incomplete block, if there is any, and add padding bits */ - status = hashcrypt_sha_finalize(base, ctxInternal); - - if (outputSize) - { - if (algOutSize < *outputSize) - { - *outputSize = algOutSize; - } - else - { - algOutSize = *outputSize; - } - } - - hashcrypt_get_data(base, (uint32_t *)output, algOutSize); - -#ifdef HASHCRYPT_SHA_DO_WIPE_CONTEXT - ctxW = (uint32_t *)ctx; - for (i = 0; i < HASHCRYPT_HASH_CTX_SIZE; i++) - { - ctxW[i] = 0u; - } -#endif /* HASHCRYPT_SHA_DO_WIPE_CONTEXT */ - return status; -} - -/*! - * brief Initializes the HASHCRYPT handle for background hashing. - * - * This function initializes the hash context for background hashing - * (Non-blocking) APIs. This is less typical interface to hash function, but can be used - * for parallel processing, when main CPU has something else to do. - * Example is digital signature RSASSA-PKCS1-V1_5-VERIFY((n,e),M,S) algorithm, where - * background hashing of M can be started, then CPU can compute S^e mod n - * (in parallel with background hashing) and once the digest becomes available, - * CPU can proceed to comparison of EM with EM'. - * - * param base HASHCRYPT peripheral base address. - * param[out] ctx Hash context. - * param callback Callback function. - * param userData User data (to be passed as an argument to callback function, once callback is invoked from isr). - */ -void HASHCRYPT_SHA_SetCallback(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - hashcrypt_callback_t callback, - void *userData) -{ - hashcrypt_sha_ctx_internal_t *ctxInternal; - - s_ctx = ctx; - ctxInternal = (hashcrypt_sha_ctx_internal_t *)ctx; - ctxInternal->hashCallback = callback; - ctxInternal->userData = userData; - - EnableIRQ(HASHCRYPT_IRQn); -} - -/*! -* brief Create running hash on given data. -* -* Configures the HASHCRYPT to compute new running hash as AHB master -* and returns immediately. HASHCRYPT AHB Master mode supports only aligned \p input -* address and can be called only once per continuous block of data. Every call to this function -* must be preceded with HASHCRYPT_SHA_Init() and finished with HASHCRYPT_SHA_Finish(). -* Once callback function is invoked by HASHCRYPT isr, it should set a flag -* for the main application to finalize the hashing (padding) and to read out the final digest -* by calling HASHCRYPT_SHA_Finish(). -* -* param base HASHCRYPT peripheral base address -* param ctx Specifies callback. Last incomplete 512-bit block of the input is copied into clear buffer for padding. -* param input 32-bit word aligned pointer to Input data. -* param inputSize Size of input data in bytes (must be word aligned) -* return Status of the hash update operation. -*/ -status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - const uint8_t *input, - size_t inputSize) -{ - hashcrypt_sha_ctx_internal_t *ctxInternal; - uint32_t numBlocks; - status_t status; - - if (inputSize == 0) - { - return kStatus_Success; - } - - if ((uintptr_t)input & 0x3U) - { - return kStatus_Fail; - } - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)ctx; - status = hashcrypt_sha_check_context(base, ctxInternal); - if (kStatus_Success != status) - { - return status; - } - - ctxInternal->fullMessageSize = inputSize; - ctxInternal->remainingBlcks = inputSize / SHA_BLOCK_SIZE; - ctxInternal->blksz = inputSize % SHA_BLOCK_SIZE; - - /* copy last incomplete block to context */ - if ((ctxInternal->blksz > 0) && (ctxInternal->blksz <= SHA_BLOCK_SIZE)) - { - hashcrypt_memcpy((&ctxInternal->blk.b[0]), input + SHA_BLOCK_SIZE * ctxInternal->remainingBlcks, - ctxInternal->blksz); - } - - if (ctxInternal->remainingBlcks >= SHA_MASTER_MAX_BLOCKS) - { - numBlocks = SHA_MASTER_MAX_BLOCKS - 1; - } - else - { - numBlocks = ctxInternal->remainingBlcks; - } - /* update remainingBlks so that ISR can run another hash if necessary */ - ctxInternal->remainingBlcks -= numBlocks; - - /* compute hash using AHB Master mode for full blocks */ - if (numBlocks > 0) - { - ctxInternal->state = kHASHCRYPT_HashUpdate; - hashcrypt_engine_init(base, ctxInternal->algo); - - /* Enable digest and error interrupts and start hash */ - base->INTENSET = HASHCRYPT_INTENCLR_DIGEST_MASK | HASHCRYPT_INTENCLR_ERROR_MASK; - base->MEMADDR = FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET | HASHCRYPT_MEMADDR_BASE(input); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(numBlocks); - } - /* no full blocks, invoke callback directly */ - else - { - ctxInternal->hashCallback(HASHCRYPT, ctx, status, ctxInternal->userData); - } - - return status; -} - -/*! - * brief Set AES key to hashcrypt_handle_t struct and optionally to HASHCRYPT. - * - * Sets the AES key for encryption/decryption with the hashcrypt_handle_t structure. - * The hashcrypt_handle_t input argument specifies key source. - * - * param base HASHCRYPT peripheral base address. - * param handle Handle used for the request. - * param key 0-mod-4 aligned pointer to AES key. - * param keySize AES key size in bytes. Shall equal 16, 24 or 32. - * return status from set key operation - */ -status_t HASHCRYPT_AES_SetKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *key, size_t aesKeySize) -{ - switch (aesKeySize) - { - case 16: - handle->keySize = kHASHCRYPT_Aes128; - break; - case 24: - handle->keySize = kHASHCRYPT_Aes192; - break; - case 32: - handle->keySize = kHASHCRYPT_Aes256; - break; - default: - handle->keySize = kHASHCRYPT_InvalidKey; - break; - } - - if (handle->keySize == kHASHCRYPT_InvalidKey) - { - return kStatus_InvalidArgument; - } - - if (handle->keyType == kHASHCRYPT_SecretKey) - { - /* for kHASHCRYPT_SecretKey just return Success */ - return kStatus_Success; - } - else if (handle->keyType == kHASHCRYPT_UserKey) - { - /* only work with aligned key[] */ - if (0x3U & (uintptr_t)key) - { - return kStatus_InvalidArgument; - } - - /* move the key by 32-bit words */ - int i = 0; - while (aesKeySize) - { - aesKeySize -= sizeof(uint32_t); - handle->keyWord[i] = ((uint32_t *)(uintptr_t)key)[i]; - i++; - } - } - else - { - return kStatus_InvalidArgument; - } - - return kStatus_Success; -} - -/*! - * brief Encrypts AES on one or multiple 128-bit block(s). - * - * Encrypts AES. - * The source plaintext and destination ciphertext can overlap in system memory. - * - * param base HASHCRYPT peripheral base address - * param handle Handle used for this request. - * param plaintext Input plain text to encrypt - * param[out] ciphertext Output cipher text - * param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * return Status from encrypt operation - */ -status_t HASHCRYPT_AES_EncryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size) -{ - status_t status = kStatus_Fail; - - if ((size % 16u) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0 : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesEcb) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, plaintext, ciphertext, size); - - return status; -} - -/*! - * brief Decrypts AES on one or multiple 128-bit block(s). - * - * Decrypts AES. - * The source ciphertext and destination plaintext can overlap in system memory. - * - * param base HASHCRYPT peripheral base address - * param handle Handle used for this request. - * param ciphertext Input plain text to encrypt - * param[out] plaintext Output cipher text - * param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * return Status from decrypt operation - */ -status_t HASHCRYPT_AES_DecryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size) -{ - status_t status = kStatus_Fail; - - if ((size % 16u) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0 : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesEcb) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_DECRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, ciphertext, plaintext, size); - - return status; -} - -/*! - * brief Encrypts AES using CBC block mode. - * - * param base HASHCRYPT peripheral base address - * param handle Handle used for this request. - * param plaintext Input plain text to encrypt - * param[out] ciphertext Output cipher text - * param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * param iv Input initial vector to combine with the first input block. - * return Status from encrypt operation - */ -status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[16]) -{ - status_t status = kStatus_Fail; - - if ((size % 16u) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0 : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load 16b iv */ - hashcrypt_load_data(base, (uint32_t *)iv, 16); - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, plaintext, ciphertext, size); - - return status; -} - -/*! - * brief Decrypts AES using CBC block mode. - * - * param base HASHCRYPT peripheral base address - * param handle Handle used for this request. - * param ciphertext Input cipher text to decrypt - * param[out] plaintext Output plain text - * param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * param iv Input initial vector to combine with the first input block. - * return Status from decrypt operation - */ -status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[16]) -{ - status_t status = kStatus_Fail; - - if ((size % 16u) || (handle->keySize == kHASHCRYPT_InvalidKey)) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0 : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_DECRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load iv */ - hashcrypt_load_data(base, (uint32_t *)iv, 16); - - /* load message and get result */ - status = hashcrypt_aes_one_block(base, ciphertext, plaintext, size); - - return status; -} - -/*! - * brief Encrypts or decrypts AES using CTR block mode. - * - * Encrypts or decrypts AES using CTR block mode. - * AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption. - * The only difference between encryption and decryption is that, for encryption, the input argument - * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text - * and the output argument is plain text. - * - * param base HASHCRYPT peripheral base address - * param handle Handle used for this request. - * param input Input data for CTR block mode - * param[out] output Output data for CTR block mode - * param size Size of input and output data in bytes - * param[in,out] counter Input counter (updates on return) - * param[out] counterlast Output cipher of last counter, for chained CTR calls (statefull encryption). NULL can be - * passed if chained calls are - * not used. - * param[out] szLeft Output number of bytes in left unused in counterlast block. NULL can be passed if chained calls - * are not used. - * return Status from encrypt operation - */ -status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - uint8_t counter[HASHCRYPT_AES_BLOCK_SIZE], - uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE], - size_t *szLeft) -{ - uint32_t lastSize; - uint8_t lastBlock[HASHCRYPT_AES_BLOCK_SIZE] = {0}; - uint8_t *lastEncryptedCounter; - status_t status = kStatus_Fail; - - if (handle->keySize == kHASHCRYPT_InvalidKey) - { - return kStatus_InvalidArgument; - } - - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0 : 1u; - base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCtr) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | - HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | - HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | - HASHCRYPT_CRYPTCFG_MSW1ST(1); - - hashcrypt_engine_init(base, kHASHCRYPT_Aes); - - /* load key if kHASHCRYPT_UserKey is selected */ - if (handle->keyType == kHASHCRYPT_UserKey) - { - hashcrypt_aes_load_userKey(base, handle); - } - - /* load nonce */ - hashcrypt_load_data(base, (uint32_t *)counter, 16); - - lastSize = size % HASHCRYPT_AES_BLOCK_SIZE; - size -= lastSize; - - /* encrypt full 16byte blocks */ - hashcrypt_aes_one_block(base, input, output, size); - - while (size) - { - ctrIncrement(counter); - size -= 16u; - input += 16; - output += 16; - } - - if (lastSize) - { - if (counterlast) - { - lastEncryptedCounter = counterlast; - } - else - { - lastEncryptedCounter = lastBlock; - } - - /* Perform encryption with all zeros to get last counter. XOR with zeros doesn't change. */ - status = hashcrypt_aes_one_block(base, lastBlock, lastEncryptedCounter, HASHCRYPT_AES_BLOCK_SIZE); - if (status != kStatus_Success) - { - return status; - } - /* remain output = input XOR counterlast */ - for (uint32_t i = 0; i < lastSize; i++) - { - output[i] = input[i] ^ lastEncryptedCounter[i]; - } - /* Increment counter parameter */ - ctrIncrement(counter); - } - else - { - lastSize = HASHCRYPT_AES_BLOCK_SIZE; - /* no remaining bytes in couterlast so clearing it */ - if (counterlast) - { - memset(counterlast, 0, HASHCRYPT_AES_BLOCK_SIZE); - } - } - - if (szLeft) - { - *szLeft = HASHCRYPT_AES_BLOCK_SIZE - lastSize; - } - - return kStatus_Success; -} - -void HASH_IRQHandler(void) -{ - hashcrypt_sha_ctx_internal_t *ctxInternal; - HASHCRYPT_Type *base = HASHCRYPT; - uint32_t numBlocks; - status_t status; - - ctxInternal = (hashcrypt_sha_ctx_internal_t *)s_ctx; - - if (0 == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) - { - if (ctxInternal->remainingBlcks > 0) - { - if (ctxInternal->remainingBlcks >= SHA_MASTER_MAX_BLOCKS) - { - numBlocks = SHA_MASTER_MAX_BLOCKS - 1; - } - else - { - numBlocks = ctxInternal->remainingBlcks; - } - /* some blocks still remaining, update remainingBlcks for next ISR and start another hash */ - ctxInternal->remainingBlcks -= numBlocks; - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(numBlocks); - return; - } - /* no full blocks left, disable interrupts and AHB master mode */ - base->INTENCLR = HASHCRYPT_INTENCLR_DIGEST_MASK | HASHCRYPT_INTENCLR_ERROR_MASK; - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(0); - status = kStatus_Success; - } - else - { - status = kStatus_Fail; - } - - /* Invoke callback if there is one */ - if (NULL != ctxInternal->hashCallback) - { - ctxInternal->hashCallback(HASHCRYPT, s_ctx, status, ctxInternal->userData); - } -} - -/*! - * brief Enables clock and disables reset for HASHCRYPT peripheral. - * - * Enable clock and disable reset for HASHCRYPT. - * - * param base HASHCRYPT base address - */ -void HASHCRYPT_Init(HASHCRYPT_Type *base) -{ - RESET_PeripheralReset(kHASHCRYPT_RST_SHIFT_RSTn); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_HashCrypt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Disables clock for HASHCRYPT peripheral. - * - * Disable clock and enable reset. - * - * param base HASHCRYPT base address - */ -void HASHCRYPT_Deinit(HASHCRYPT_Type *base) -{ - RESET_SetPeripheralReset(kHASHCRYPT_RST_SHIFT_RSTn); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_HashCrypt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_hashcrypt.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_hashcrypt.h deleted file mode 100644 index 21ab61fc9b..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_hashcrypt.h +++ /dev/null @@ -1,420 +0,0 @@ -/* - * Copyright 2017-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_HASHCRYPT_H_ -#define _FSL_HASHCRYPT_H_ - -#include "fsl_common.h" - -/*! @brief HASHCRYPT status return codes. */ -enum _hashcrypt_status -{ - kStatus_HASHCRYPT_Again = - MAKE_STATUS(kStatusGroup_HASHCRYPT, 0), /*!< Non-blocking function shall be called again. */ -}; - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief HASHCRYPT driver version. Version 2.0.0. - * - * Current version: 2.0.0 - * - * Change log: - * - Version 2.0.0 - * - Initial version - */ -#define FSL_HASHCRYPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief Algorithm used for Hashcrypt operation */ -typedef enum _hashcrypt_algo_t -{ - kHASHCRYPT_Sha1 = 1, /*!< SHA_1 */ - kHASHCRYPT_Sha256 = 2, /*!< SHA_256 */ - kHASHCRYPT_Sha512 = 3, /*!< SHA_512 */ - kHASHCRYPT_Aes = 4, /*!< AES */ - kHASHCRYPT_AesIcb = 5, /*!< AES_ICB */ -} hashcrypt_algo_t; - -/*! @} */ - -/******************************************************************************* - * AES Definitions - *******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver_aes - * @{ - */ - -/*! AES block size in bytes */ -#define HASHCRYPT_AES_BLOCK_SIZE 16 -#define AES_ENCRYPT 0 -#define AES_DECRYPT 1 - -/*! @brief AES mode */ -typedef enum _hashcrypt_aes_mode_t -{ - kHASHCRYPT_AesEcb = 0U, /*!< AES ECB mode */ - kHASHCRYPT_AesCbc = 1U, /*!< AES CBC mode */ - kHASHCRYPT_AesCtr = 2U, /*!< AES CTR mode */ -} hashcrypt_aes_mode_t; - -/*! @brief Size of AES key */ -typedef enum _hashcrypt_aes_keysize_t -{ - kHASHCRYPT_Aes128 = 0U, /*!< AES 128 bit key */ - kHASHCRYPT_Aes192 = 1U, /*!< AES 192 bit key */ - kHASHCRYPT_Aes256 = 2U, /*!< AES 256 bit key */ - kHASHCRYPT_InvalidKey = 3U, /*!< AES invalid key */ -} hashcrypt_aes_keysize_t; - -/*! @brief HASHCRYPT key source selection. - * - */ -typedef enum _hashcrypt_key -{ - kHASHCRYPT_UserKey = 0xc3c3U, /*!< HASHCRYPT user key */ - kHASHCRYPT_SecretKey = 0x3c3cU, /*!< HASHCRYPT secret key (dedicated hw bus from PUF) */ -} hashcrypt_key_t; - -/*! @brief Specify HASHCRYPT's key resource. */ -typedef struct _hashcrypt_handle -{ - uint32_t keyWord[8]; /*!< Copy of user key (set by HASHCRYPT_AES_SetKey(). */ - hashcrypt_aes_keysize_t keySize; - hashcrypt_key_t keyType; /*!< For operations with key (such as AES encryption/decryption), specify key type. */ -} hashcrypt_handle_t; - -/*! - *@} - */ /* end of hashcrypt_driver_aes */ - -/******************************************************************************* - * HASH Definitions - ******************************************************************************/ -/*! - * @addtogroup hashcrypt_driver_hash - * @{ - */ - -/*! @brief HASHCRYPT HASH Context size. */ -#define HASHCRYPT_HASH_CTX_SIZE 22 - -/*! @brief Storage type used to save hash context. */ -typedef struct _hashcrypt_hash_ctx_t -{ - uint32_t x[HASHCRYPT_HASH_CTX_SIZE]; /*!< storage */ -} hashcrypt_hash_ctx_t; - -/*! @brief HASHCRYPT background hash callback function. */ -typedef void (*hashcrypt_callback_t)(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, status_t status, void *userData); - -/*! - *@} - */ /* end of hashcrypt_driver_hash */ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup hashcrypt_driver - * @{ - */ - -/*! - * @brief Enables clock and disables reset for HASHCRYPT peripheral. - * - * Enable clock and disable reset for HASHCRYPT. - * - * @param base HASHCRYPT base address - */ -void HASHCRYPT_Init(HASHCRYPT_Type *base); - -/*! - * @brief Disables clock for HASHCRYPT peripheral. - * - * Disable clock and enable reset. - * - * @param base HASHCRYPT base address - */ -void HASHCRYPT_Deinit(HASHCRYPT_Type *base); - -/*! - *@} - */ /* end of hashcrypt_driver */ - -/******************************************************************************* - * AES API - ******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver_aes - * @{ - */ - -/*! - * @brief Set AES key to hashcrypt_handle_t struct and optionally to HASHCRYPT. - * - * Sets the AES key for encryption/decryption with the hashcrypt_handle_t structure. - * The hashcrypt_handle_t input argument specifies key source. - * - * @param base HASHCRYPT peripheral base address. - * @param handle Handle used for the request. - * @param key 0-mod-4 aligned pointer to AES key. - * @param keySize AES key size in bytes. Shall equal 16, 24 or 32. - * @return status from set key operation - */ -status_t HASHCRYPT_AES_SetKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *key, size_t keySize); - -/*! - * @brief Encrypts AES on one or multiple 128-bit block(s). - * - * Encrypts AES. - * The source plaintext and destination ciphertext can overlap in system memory. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @return Status from encrypt operation - */ -status_t HASHCRYPT_AES_EncryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size); - -/*! - * @brief Decrypts AES on one or multiple 128-bit block(s). - * - * Decrypts AES. - * The source ciphertext and destination plaintext can overlap in system memory. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param ciphertext Input plain text to encrypt - * @param[out] plaintext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @return Status from decrypt operation - */ -status_t HASHCRYPT_AES_DecryptEcb( - HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size); - -/*! - * @brief Encrypts AES using CBC block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ -status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[16]); - -/*! - * @brief Decrypts AES using CBC block mode. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plain text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from decrypt operation - */ -status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[16]); - -/*! - * @brief Encrypts or decrypts AES using CTR block mode. - * - * Encrypts or decrypts AES using CTR block mode. - * AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption. - * The only difference between encryption and decryption is that, for encryption, the input argument - * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text - * and the output argument is plain text. - * - * @param base HASHCRYPT peripheral base address - * @param handle Handle used for this request. - * @param input Input data for CTR block mode - * @param[out] output Output data for CTR block mode - * @param size Size of input and output data in bytes - * @param[in,out] counter Input counter (updates on return) - * @param[out] counterlast Output cipher of last counter, for chained CTR calls (statefull encryption). NULL can be - * passed if chained calls are - * not used. - * @param[out] szLeft Output number of bytes in left unused in counterlast block. NULL can be passed if chained calls - * are not used. - * @return Status from encrypt operation - */ -status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, - hashcrypt_handle_t *handle, - const uint8_t *input, - uint8_t *output, - size_t size, - uint8_t counter[HASHCRYPT_AES_BLOCK_SIZE], - uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE], - size_t *szLeft); - -/*! - *@} - */ /* end of hashcrypt_driver_aes */ - -/******************************************************************************* - * HASH API - ******************************************************************************/ - -/*! - * @addtogroup hashcrypt_driver_hash - * @{ - */ - -/*! - * @brief Create HASH on given data - * - * Perform the full SHA in one function call. The function is blocking. - * - * @param base HASHCRYPT peripheral base address - * @param algo Underlaying algorithm to use for hash computation. - * @param input Input data - * @param inputSize Size of input data in bytes - * @param[out] output Output hash data - * @param[out] outputSize Output parameter storing the size of the output hash in bytes - * @return Status of the one call hash operation. - */ -status_t HASHCRYPT_SHA(HASHCRYPT_Type *base, - hashcrypt_algo_t algo, - const uint8_t *input, - size_t inputSize, - uint8_t *output, - size_t *outputSize); - -/*! - * @brief Initialize HASH context - * - * This function initializes the HASH. - * - * @param base HASHCRYPT peripheral base address - * @param[out] ctx Output hash context - * @param algo Underlaying algorithm to use for hash computation. - * @return Status of initialization - */ -status_t HASHCRYPT_SHA_Init(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo); - -/*! - * @brief Add data to current HASH - * - * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be - * hashed. The functions blocks. If it returns kStatus_Success, the running hash - * has been updated (HASHCRYPT has processed the input data), so the memory at \p input pointer - * can be released back to system. The HASHCRYPT context buffer is updated with the running hash - * and with all necessary information to support possible context switch. - * - * @param base HASHCRYPT peripheral base address - * @param[in,out] ctx HASH context - * @param input Input data - * @param inputSize Size of input data in bytes - * @return Status of the hash update operation - */ -status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize); - -/*! - * @brief Finalize hashing - * - * Outputs the final hash (computed by HASHCRYPT_HASH_Update()) and erases the context. - * - * @param base HASHCRYPT peripheral base address - * @param[in,out] ctx Input hash context - * @param[out] output Output hash data - * @param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of - * output[] buffer. On function return, it stores the number of updated output bytes. - * @return Status of the hash finish operation - */ -status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize); - -/*! - *@} - */ /* end of hashcrypt_driver_hash */ - -/*! -* @addtogroup hashcrypt_background_driver_hash -* @{ -*/ - -/*! - * @brief Initializes the HASHCRYPT handle for background hashing. - * - * This function initializes the hash context for background hashing - * (Non-blocking) APIs. This is less typical interface to hash function, but can be used - * for parallel processing, when main CPU has something else to do. - * Example is digital signature RSASSA-PKCS1-V1_5-VERIFY((n,e),M,S) algorithm, where - * background hashing of M can be started, then CPU can compute S^e mod n - * (in parallel with background hashing) and once the digest becomes available, - * CPU can proceed to comparison of EM with EM'. - * - * @param base HASHCRYPT peripheral base address. - * @param[out] ctx Hash context. - * @param callback Callback function. - * @param userData User data (to be passed as an argument to callback function, once callback is invoked from isr). - */ -void HASHCRYPT_SHA_SetCallback(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - hashcrypt_callback_t callback, - void *userData); - -/*! -* @brief Create running hash on given data. -* -* Configures the HASHCRYPT to compute new running hash as AHB master -* and returns immediately. HASHCRYPT AHB Master mode supports only aligned \p input -* address and can be called only once per continuous block of data. Every call to this function -* must be preceded with HASHCRYPT_SHA_Init() and finished with HASHCRYPT_SHA_Finish(). -* Once callback function is invoked by HASHCRYPT isr, it should set a flag -* for the main application to finalize the hashing (padding) and to read out the final digest -* by calling HASHCRYPT_SHA_Finish(). -* -* @param base HASHCRYPT peripheral base address -* @param ctx Specifies callback. Last incomplete 512-bit block of the input is copied into clear buffer for padding. -* @param input 32-bit word aligned pointer to Input data. -* @param inputSize Size of input data in bytes (must be word aligned) -* @return Status of the hash update operation. -*/ -status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, - hashcrypt_hash_ctx_t *ctx, - const uint8_t *input, - size_t inputSize); -/*! - *@} - */ /* end of hashcrypt_background_driver_hash */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_HASHCRYPT_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2c.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2c.c deleted file mode 100644 index 8cec745c37..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2c.c +++ /dev/null @@ -1,1856 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2c.h" -#include "fsl_flexcomm.h" -#include -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c" -#endif - -/*! @brief Common sets of flags used by the driver. */ -enum _i2c_flag_constants -{ - kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK, - kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK, -}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); -static void I2C_SlaveInternalStateMachineReset(I2C_Type *base); -static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal); -static uint32_t I2C_SlavePollPending(I2C_Type *base); -static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event); -static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle); -static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, - i2c_slave_handle_t *handle, - const void *txData, - size_t txSize, - void *rxData, - size_t rxSize, - uint32_t eventMask); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map i2c instance number to base address. */ -static const uint32_t s_i2cBaseAddrs[FSL_FEATURE_SOC_I2C_COUNT] = I2C_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_i2cIRQ[] = I2C_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The I2C peripheral base address. - * @return I2C instance number starting from 0. - */ -/*! - * brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * param base The I2C peripheral base address. - * return I2C instance number starting from 0. - */ -uint32_t I2C_GetInstance(I2C_Type *base) -{ - int i; - for (i = 0; i < FSL_FEATURE_SOC_I2C_COUNT; i++) - { - if ((uint32_t)base == s_i2cBaseAddrs[i]) - { - return i; - } - } - assert(false); - return 0; -} - -/*! - * brief Provides a default configuration for the I2C master peripheral. - * - * This function provides the following default configuration for the I2C master peripheral: - * code - * masterConfig->enableMaster = true; - * masterConfig->baudRate_Bps = 100000U; - * masterConfig->enableTimeout = false; - * endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with I2C_MasterInit(). - * - * param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. - */ -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) -{ - /* Initializes the configure structure to zero. */ - memset(masterConfig, 0, sizeof(*masterConfig)); - - masterConfig->enableMaster = true; - masterConfig->baudRate_Bps = 100000U; - masterConfig->enableTimeout = false; -} - -/*! - * brief Initializes the I2C master peripheral. - * - * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * param base The I2C peripheral base address. - * param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of - * defaults - * that you can override. - * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); - I2C_MasterEnable(base, masterConfig->enableMaster); - I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); -} - -/*! -* brief Deinitializes the I2C master peripheral. -* - * This function disables the I2C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * param base The I2C peripheral base address. - */ -void I2C_MasterDeinit(I2C_Type *base) -{ - I2C_MasterEnable(base, false); -} - -/*! - * brief Sets the I2C bus frequency for master transactions. - * - * The I2C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * param base The I2C peripheral base address. - * param srcClock_Hz I2C functional clock frequency in Hertz. - * param baudRate_Bps Requested bus frequency in bits per second. - */ -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) -{ - uint32_t scl, divider; - uint32_t best_scl, best_div; - uint32_t err, best_err; - - best_err = 0; - - for (scl = 9; scl >= 2; scl--) - { - /* calculated ideal divider value for given scl */ - divider = srcClock_Hz / (baudRate_Bps * scl * 2u); - - /* adjust it if it is out of range */ - divider = (divider > 0x10000u) ? 0x10000 : divider; - - /* calculate error */ - err = srcClock_Hz - (baudRate_Bps * scl * 2u * divider); - if ((err < best_err) || (best_err == 0)) - { - best_div = divider; - best_scl = scl; - best_err = err; - } - - if ((err == 0) || (divider >= 0x10000u)) - { - /* either exact value was found - or divider is at its max (it would even greater in the next iteration for sure) */ - break; - } - } - - base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1); - base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl - 2u) | I2C_MSTTIME_MSTSCLHIGH(best_scl - 2u); -} - -static uint32_t I2C_PendingStatusWait(I2C_Type *base) -{ - uint32_t status; - -#if I2C_WAIT_TIMEOUT - uint32_t waitTimes = I2C_WAIT_TIMEOUT; -#endif - - do - { - status = I2C_GetStatusFlags(base); -#if I2C_WAIT_TIMEOUT - } while (((status & I2C_STAT_MSTPENDING_MASK) == 0) && (--waitTimes)); - - if (waitTimes == 0) - { - return kStatus_I2C_Timeout; - } -#else - } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); -#endif - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - return status; -} - -/*! - * brief Sends a START on the I2C bus. - * - * This function is used to initiate a new master mode transfer by sending the START signal. - * The slave address is sent following the I2C START signal. - * - * param base I2C peripheral base pointer - * param address 7-bit slave device address. - * param direction Master transfer directions(transmit/receive). - * retval kStatus_Success Successfully send the start signal. - * retval kStatus_I2C_Busy Current bus is busy. - */ -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - status_t result; - result = I2C_PendingStatusWait(base); - if (result == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - /* Write Address and RW bit to data register */ - base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1u); - /* Start the transfer */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - - result = I2C_PendingStatusWait(base); - if (result == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - return kStatus_Success; -} - -/*! - * brief Sends a STOP signal on the I2C bus. - * - * retval kStatus_Success Successfully send the stop signal. - * retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterStop(I2C_Type *base) -{ - status_t result; - result = I2C_PendingStatusWait(base); - if (result == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - - result = I2C_PendingStatusWait(base); - if (result == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - return kStatus_Success; -} - -/*! - * brief Performs a polling send transfer on the I2C bus. - * - * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_I2C_Nak. - * - * param base The I2C peripheral base address. - * param txBuff The pointer to the data to be transferred. - * param txSize The length in bytes of the data to be transferred. - * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * retval kStatus_Success Data was sent successfully. - * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) -{ - uint32_t status; - uint32_t master_state; - status_t err; - - const uint8_t *buf = (const uint8_t *)(uintptr_t)txBuff; - - assert(txBuff); - - err = kStatus_Success; - while (txSize) - { - status = I2C_PendingStatusWait(base); - -#if I2C_WAIT_TIMEOUT - if (status == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } -#endif - - if (status & I2C_STAT_MSTARBLOSS_MASK) - { - return kStatus_I2C_ArbitrationLost; - } - - if (status & I2C_STAT_MSTSTSTPERR_MASK) - { - return kStatus_I2C_StartStopError; - } - - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - switch (master_state) - { - case I2C_STAT_MSTCODE_TXREADY: - /* ready to send next byte */ - base->MSTDAT = *buf++; - txSize--; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - break; - - case I2C_STAT_MSTCODE_NACKADR: - case I2C_STAT_MSTCODE_NACKDAT: - /* slave nacked the last byte */ - err = kStatus_I2C_Nak; - break; - - default: - /* unexpected state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - if (err != kStatus_Success) - { - return err; - } - } - - status = I2C_PendingStatusWait(base); - -#if I2C_WAIT_TIMEOUT - if (status == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } -#endif - - if ((status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) == 0) - { - if (!(flags & kI2C_TransferNoStopFlag)) - { - /* Initiate stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - status = I2C_PendingStatusWait(base); - if (status == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - } - - if (status & I2C_STAT_MSTARBLOSS_MASK) - { - return kStatus_I2C_ArbitrationLost; - } - - if (status & I2C_STAT_MSTSTSTPERR_MASK) - { - return kStatus_I2C_StartStopError; - } - - return kStatus_Success; -} - -/*! - * brief Performs a polling receive transfer on the I2C bus. - * - * param base The I2C peripheral base address. - * param rxBuff The pointer to the data to be transferred. - * param rxSize The length in bytes of the data to be transferred. - * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * retval kStatus_Success Data was received successfully. - * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) -{ - uint32_t status = 0; - uint32_t master_state; - status_t err; - - uint8_t *buf = (uint8_t *)(rxBuff); - - assert(rxBuff); - - err = kStatus_Success; - while (rxSize) - { - status = I2C_PendingStatusWait(base); - -#if I2C_WAIT_TIMEOUT - if (status == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } -#endif - - if (status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) - { - break; - } - - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - switch (master_state) - { - case I2C_STAT_MSTCODE_RXREADY: - /* ready to send next byte */ - *(buf++) = base->MSTDAT; - if (--rxSize) - { - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - } - else - { - if ((flags & kI2C_TransferNoStopFlag) == 0) - { - /* initiate NAK and stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - status = I2C_PendingStatusWait(base); - -#if I2C_WAIT_TIMEOUT - if (status == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } -#endif - } - } - break; - - case I2C_STAT_MSTCODE_NACKADR: - case I2C_STAT_MSTCODE_NACKDAT: - /* slave nacked the last byte */ - err = kStatus_I2C_Nak; - break; - - default: - /* unexpected state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - if (err != kStatus_Success) - { - return err; - } - } - - if (status & I2C_STAT_MSTARBLOSS_MASK) - { - return kStatus_I2C_ArbitrationLost; - } - - if (status & I2C_STAT_MSTSTSTPERR_MASK) - { - return kStatus_I2C_StartStopError; - } - - return kStatus_Success; -} - -/*! - * brief Performs a master polling transfer on the I2C bus. - * - * note The API does not return until the transfer succeeds or fails due - * to arbitration lost or receiving a NAK. - * - * param base I2C peripheral base address. - * param xfer Pointer to the transfer structure. - * retval kStatus_Success Successfully complete the data transmission. - * retval kStatus_I2C_Busy Previous transmission still not finished. - * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - */ -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) -{ - status_t result = kStatus_Success; - uint32_t subaddress; - uint8_t subaddrBuf[4]; - int i; - - assert(xfer); - - /* If repeated start is requested, send repeated start. */ - if (!(xfer->flags & kI2C_TransferNoStartFlag)) - { - if (xfer->subaddressSize) - { - result = I2C_MasterStart(base, xfer->slaveAddress, kI2C_Write); - if (result == kStatus_Success) - { - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = xfer->subaddressSize - 1; i >= 0; i--) - { - subaddrBuf[i] = subaddress & 0xff; - subaddress >>= 8; - } - /* Send subaddress. */ - result = I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, kI2C_TransferNoStopFlag); - if ((result == kStatus_Success) && (xfer->direction == kI2C_Read)) - { - result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); - } - } - } - else if (xfer->flags & kI2C_TransferRepeatedStartFlag) - { - result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); - } - else - { - result = I2C_MasterStart(base, xfer->slaveAddress, xfer->direction); - } - } - - if (result == kStatus_Success) - { - if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0)) - { - /* Transmit data. */ - result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - else - { - if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0)) - { - /* Receive Data. */ - result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - } - } - - if (result == kStatus_I2C_Nak) - { - I2C_MasterStop(base); - } - - return result; -} - -/*! - * brief Creates a new handle for the I2C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. - * - * param base The I2C peripheral base address. - * param[out] handle Pointer to the I2C master driver handle. - * param callback User provided pointer to the asynchronous callback function. - * param userData User provided pointer to the application callback data. - */ -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData) -{ - uint32_t instance; - - assert(handle); - - /* Clear out the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Save base and instance. */ - handle->completionCallback = callback; - handle->userData = userData; - - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_MasterTransferHandleIRQ, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); - EnableIRQ(s_i2cIRQ[instance]); -} - -/*! - * brief Performs a non-blocking transaction on the I2C bus. - * - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * param xfer The pointer to the transfer descriptor. - * retval kStatus_Success The transaction was started successfully. - * retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result; - - assert(handle); - assert(xfer); - assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != kIdleState) - { - return kStatus_I2C_Busy; - } - - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); - - /* Prepare transfer state machine. */ - result = I2C_InitTransferStateMachine(base, handle, xfer); - - /* Clear error flags. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, kI2C_MasterIrqFlags); - - return result; -} - -/*! - * brief Returns number of bytes transferred so far. - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * param[out] count Number of bytes transferred so far by the non-blocking transaction. - * retval kStatus_Success - * retval #kStatus_I2C_Busy - */ -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* There is no necessity to disable interrupts as we read a single integer value */ - *count = handle->transferCount; - return kStatus_Success; -} - -/*! - * brief Terminates a non-blocking I2C master transmission early. - * - * note It is not safe to call this function from an IRQ handler that has a higher priority than the - * I2C peripheral's IRQ priority. - * - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - * retval kStatus_Success A transaction was successfully aborted. - * retval #kStatus_I2C_Timeout Timeout during polling for flags. - */ -status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) -{ - uint32_t status; - uint32_t master_state; - - if (handle->state != kIdleState) - { - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); - - /* Wait until module is ready */ - status = I2C_PendingStatusWait(base); - -#if I2C_WAIT_TIMEOUT - if (status == kStatus_I2C_Timeout) - { - /* Reset handle to idle state. */ - handle->state = kIdleState; - return kStatus_I2C_Timeout; - } -#endif - - /* Get the state of the I2C module */ - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (master_state != I2C_STAT_MSTCODE_IDLE) - { - /* Send a stop command to finalize the transfer. */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - - /* Wait until the STOP is completed */ - status = I2C_PendingStatusWait(base); - if (status == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - - /* Reset handle. */ - handle->state = kIdleState; - } - return kStatus_Success; -} - -/*! - * @brief Prepares the transfer state machine and fills in the command buffer. - * @param handle Master nonblocking driver handle. - */ -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - struct _i2c_master_transfer *transfer; - - handle->transfer = *xfer; - transfer = &(handle->transfer); - - handle->transferCount = 0; - handle->remainingBytes = transfer->dataSize; - handle->buf = (uint8_t *)transfer->data; - handle->remainingSubaddr = 0; - - if (transfer->flags & kI2C_TransferNoStartFlag) - { - /* Start condition shall be ommited, switch directly to next phase */ - if (transfer->dataSize == 0) - { - handle->state = kStopState; - } - else if (handle->transfer.direction == kI2C_Write) - { - handle->state = kTransmitDataState; - } - else if (handle->transfer.direction == kI2C_Read) - { - handle->state = kReceiveDataState; - } - else - { - return kStatus_I2C_InvalidParameter; - } - } - else - { - if (transfer->subaddressSize != 0) - { - int i; - uint32_t subaddress; - - if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) - { - return kStatus_I2C_InvalidParameter; - } - - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = xfer->subaddressSize - 1; i >= 0; i--) - { - handle->subaddrBuf[i] = subaddress & 0xff; - subaddress >>= 8; - } - handle->remainingSubaddr = transfer->subaddressSize; - } - handle->state = kStartState; - } - - return kStatus_Success; -} - -/*! - * @brief Execute states until FIFOs are exhausted. - * @param handle Master nonblocking driver handle. - * @param[out] isDone Set to true if the transfer has completed. - * @retval #kStatus_Success - * @retval #kStatus_I2C_ArbitrationLost - * @retval #kStatus_I2C_Nak - */ -static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) -{ - uint32_t status; - uint32_t master_state; - struct _i2c_master_transfer *transfer; - status_t err; - - transfer = &(handle->transfer); - bool ignoreNak = ((handle->state == kStopState) && (handle->remainingBytes == 0U)) || - ((handle->state == kWaitForCompletionState) && (handle->remainingBytes == 0U)); - - *isDone = false; - - status = I2C_GetStatusFlags(base); - - if (status & I2C_STAT_MSTARBLOSS_MASK) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); - return kStatus_I2C_ArbitrationLost; - } - - if (status & I2C_STAT_MSTSTSTPERR_MASK) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); - return kStatus_I2C_StartStopError; - } - - if ((status & I2C_STAT_MSTPENDING_MASK) == 0) - { - return kStatus_I2C_Busy; - } - - /* Get the state of the I2C module */ - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT)) && (ignoreNak != true)) - { - /* Slave NACKed last byte, issue stop and return error */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - return kStatus_I2C_Nak; - } - - err = kStatus_Success; - switch (handle->state) - { - case kStartState: - if (handle->remainingSubaddr) - { - /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */ - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = kTransmitSubaddrState; - } - else if (transfer->direction == kI2C_Write) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = handle->remainingBytes ? kTransmitDataState : kStopState; - } - else - { - base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - handle->state = handle->remainingBytes ? kReceiveDataState : kStopState; - } - /* Send start condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - break; - - case kTransmitSubaddrState: - if (master_state != I2C_STAT_MSTCODE_TXREADY) - { - return kStatus_I2C_UnexpectedState; - } - - /* Most significant subaddress byte comes first */ - base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr]; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--(handle->remainingSubaddr)) - { - /* There are still subaddress bytes to be transmitted */ - break; - } - if (handle->remainingBytes) - { - /* There is data to be transferred, if there is write to read turnaround it is necessary to perform - * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState; - } - else - { - /* No more data, schedule stop condition */ - handle->state = kStopState; - } - break; - - case kTransmitDataState: - if (master_state != I2C_STAT_MSTCODE_TXREADY) - { - return kStatus_I2C_UnexpectedState; - } - base->MSTDAT = *(handle->buf)++; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--handle->remainingBytes == 0) - { - /* No more data, schedule stop condition */ - handle->state = kStopState; - } - handle->transferCount++; - break; - - case kReceiveDataState: - if (master_state != I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - *(handle->buf)++ = base->MSTDAT; - if (--handle->remainingBytes) - { - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - } - else - { - /* No more data expected, issue NACK and STOP right away */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - } - handle->transferCount++; - break; - - case kStopState: - if (transfer->flags & kI2C_TransferNoStopFlag) - { - /* Stop condition is omitted, we are done */ - *isDone = true; - handle->state = kIdleState; - break; - } - /* Send stop condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - break; - - case kWaitForCompletionState: - *isDone = true; - handle->state = kIdleState; - break; - - case kIdleState: - default: - /* State machine shall not be invoked again once it enters the idle state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - return err; -} - -/*! - * brief Reusable routine to handle master interrupts. - * note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * param base The I2C peripheral base address. - * param handle Pointer to the I2C master driver handle. - */ -void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (!handle) - { - return; - } - - result = I2C_RunTransferStateMachine(base, handle, &isDone); - - if (isDone || (result != kStatus_Success)) - { - /* Restore handle to idle state. */ - handle->state = kIdleState; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); - - /* Invoke callback. */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -/*! - * @brief Sets the hardware slave state machine to reset - * - * Per documentation, the only the state machine is reset, the configuration settings remain. - * - * @param base The I2C peripheral base address. - */ -static void I2C_SlaveInternalStateMachineReset(I2C_Type *base) -{ - I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */ -} - -/*! - * @brief Compute CLKDIV - * - * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency. - * This setting is used by hardware during slave clock stretching. - * - * @param base The I2C peripheral base address. - * @return status of the operation - */ -static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal) -{ - uint32_t dataSetupTime_ns; - - switch (busSpeed) - { - case kI2C_SlaveStandardMode: - dataSetupTime_ns = 250u; - break; - - case kI2C_SlaveFastMode: - dataSetupTime_ns = 100u; - break; - - case kI2C_SlaveFastModePlus: - dataSetupTime_ns = 50u; - break; - - case kI2C_SlaveHsMode: - dataSetupTime_ns = 10u; - break; - - default: - dataSetupTime_ns = 0; - break; - } - - if (0 == dataSetupTime_ns) - { - return kStatus_InvalidArgument; - } - - /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */ - *divVal = srcClock_Hz / 1000u; - *divVal = (*divVal) * dataSetupTime_ns; - *divVal = (*divVal) / 1000000u; - - if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK) - { - *divVal = I2C_CLKDIV_DIVVAL_MASK; - } - - return kStatus_Success; -} - -/*! - * @brief Poll wait for the SLVPENDING flag. - * - * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register. - * - * @param base The I2C peripheral base address. - * @return status register at time the SLVPENDING bit is read as set - */ -static uint32_t I2C_SlavePollPending(I2C_Type *base) -{ - uint32_t stat; - -#if I2C_WAIT_TIMEOUT - uint32_t waitTimes = I2C_WAIT_TIMEOUT; -#endif - do - { - stat = base->STAT; -#if I2C_WAIT_TIMEOUT - } while ((0u == (stat & I2C_STAT_SLVPENDING_MASK)) && (--waitTimes)); - - if (waitTimes == 0u) - { - return kStatus_I2C_Timeout; - } -#else - } while (0u == (stat & I2C_STAT_SLVPENDING_MASK)); -#endif - - return stat; -} - -/*! - * @brief Invoke event from I2C_SlaveTransferHandleIRQ(). - * - * Sets the event type to transfer structure and invokes the event callback, if it has been - * enabled by eventMask. - * - * @param base The I2C peripheral base address. - * @param handle The I2C slave handle for non-blocking APIs. - * @param event The I2C slave event to invoke. - */ -static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event) -{ - handle->transfer.event = event; - if ((handle->callback) && (handle->transfer.eventMask & event)) - { - handle->callback(base, &handle->transfer, handle->userData); - - /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */ - if (false == handle->isBusy) - { - if (((handle->transfer.txData) && (handle->transfer.txSize)) || - ((handle->transfer.rxData) && (handle->transfer.rxSize))) - { - handle->isBusy = true; - } - } - - /* Clear the transferred count now that we have a new buffer. */ - if ((event == kI2C_SlaveReceiveEvent) || (event == kI2C_SlaveTransmitEvent)) - { - handle->transfer.transferredCount = 0; - } - } -} - -/*! - * @brief Handle slave address match event. - * - * Called by Slave interrupt routine to ACK or NACK the matched address. - * It also determines master direction (read or write). - * - * @param base The I2C peripheral base address. - * @return true if the matched address is ACK'ed - * @return false if the matched address is NACK'ed - */ -static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle) -{ - uint8_t addressByte0; - - addressByte0 = (uint8_t)base->SLVDAT; - - /* store the matched address */ - handle->transfer.receivedAddress = addressByte0; - - /* R/nW */ - if (addressByte0 & 1u) - { - /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); - } - - /* NACK if we have no data in this transfer. */ - if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - return false; - } - - /* master wants to read, so slave transmit is next state */ - handle->slaveFsm = kI2C_SlaveFsmTransmit; - } - else - { - /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); - } - - /* NACK if we have no data in this transfer */ - if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - return false; - } - - /* master wants write, so slave receive is next state */ - handle->slaveFsm = kI2C_SlaveFsmReceive; - } - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - return true; -} - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. - * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only. - * @param txSize Size of txData buffer in bytes. - * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL - * if slave TX only. - * @param rxSize Size of rxData buffer in bytes. - * - * @retval #kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, - i2c_slave_handle_t *handle, - const void *txData, - size_t txSize, - void *rxData, - size_t rxSize, - uint32_t eventMask) -{ - status_t status; - - assert(handle); - - status = kStatus_Success; - - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); - - /* Return busy if another transaction is in progress. */ - if (handle->isBusy) - { - status = kStatus_I2C_Busy; - } - - /* Save transfer into handle. */ - handle->transfer.txData = (const uint8_t *)(uintptr_t)txData; - handle->transfer.txSize = txSize; - handle->transfer.rxData = (uint8_t *)rxData; - handle->transfer.rxSize = rxSize; - handle->transfer.transferredCount = 0; - handle->transfer.eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent; - handle->isBusy = true; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* Clear w1c flags. */ - base->STAT |= 0u; - - /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, kI2C_SlaveIrqFlags); - - return status; -} - -/*! - * brief Starts accepting master read from slave requests. - * - * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param transfer Pointer to #i2c_slave_transfer_t structure. - * param txData Pointer to data to send to master. - * param txSize Size of txData in bytes. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetSendBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask); -} - -/*! - * brief Starts accepting master write to slave requests. - * - * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param transfer Pointer to #i2c_slave_transfer_t structure. - * param rxData Pointer to data to store data from master. - * param rxSize Size of rxData in bytes. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetReceiveBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask); -} - -/*! - * brief Configures Slave Address n register. - * - * This function writes new value to Slave Address register. - * - * param base The I2C peripheral base address. - * param addressRegister The module supports multiple address registers. The parameter determines which one shall be - * changed. - * param address The slave address to be stored to the address register for matching. - * param addressDisable Disable matching of the specified address register. - */ -void I2C_SlaveSetAddress(I2C_Type *base, - i2c_slave_address_register_t addressRegister, - uint8_t address, - bool addressDisable) -{ - base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable); -} - -/*! - * brief Provides a default configuration for the I2C slave peripheral. - * - * This function provides the following default configuration for the I2C slave peripheral: - * code - * slaveConfig->enableSlave = true; - * slaveConfig->address0.disable = false; - * slaveConfig->address0.address = 0u; - * slaveConfig->address1.disable = true; - * slaveConfig->address2.disable = true; - * slaveConfig->address3.disable = true; - * slaveConfig->busSpeed = kI2C_SlaveStandardMode; - * endcode - * - * After calling this function, override any settings to customize the configuration, - * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the a - * address0.address member of the configuration structure with the desired slave address. - * - * param[out] slaveConfig User provided configuration structure that is set to default values. Refer to - * #i2c_slave_config_t. - */ -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) -{ - assert(slaveConfig); - - i2c_slave_config_t mySlaveConfig = {0}; - - /* default config enables slave address 0 match to general I2C call address zero */ - mySlaveConfig.enableSlave = true; - mySlaveConfig.address1.addressDisable = true; - mySlaveConfig.address2.addressDisable = true; - mySlaveConfig.address3.addressDisable = true; - - *slaveConfig = mySlaveConfig; -} - -/*! - * brief Initializes the I2C slave peripheral. - * - * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user - * provided configuration. - * - * param base The I2C peripheral base address. - * param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults - * that you can override. - * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide - * enough - * data setup time for master when slave stretches the clock. - */ -status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) -{ - status_t status; - uint32_t divVal = 0; - - /* configure data setup time used when slave stretches clock */ - status = I2C_SlaveDivVal(srcClock_Hz, slaveConfig->busSpeed, &divVal); - if (kStatus_Success != status) - { - return status; - } - - FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); - - /* I2C Clock Divider register */ - base->CLKDIV = divVal; - - /* set Slave address */ - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister0, slaveConfig->address0.address, - slaveConfig->address0.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister1, slaveConfig->address1.address, - slaveConfig->address1.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister2, slaveConfig->address2.address, - slaveConfig->address2.addressDisable); - I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister3, slaveConfig->address3.address, - slaveConfig->address3.addressDisable); - - /* set Slave address 0 qual */ - base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(slaveConfig->qualMode) | I2C_SLVQUAL0_SLVQUAL0(slaveConfig->qualAddress); - - /* set Slave enable */ - base->CFG = I2C_CFG_SLVEN(slaveConfig->enableSlave); - - return status; -} - -/*! -* brief Deinitializes the I2C slave peripheral. -* - * This function disables the I2C slave peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * param base The I2C peripheral base address. - */ -void I2C_SlaveDeinit(I2C_Type *base) -{ - I2C_SlaveEnable(base, false); -} - -/*! - * brief Performs a polling send transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * param base The I2C peripheral base address. - * param txBuff The pointer to the data to be transferred. - * param txSize The length in bytes of the data to be transferred. - * return kStatus_Success Data has been sent. - * return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). - */ -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) -{ - const uint8_t *buf = txBuff; - uint32_t stat; - bool slaveAddress; - bool slaveTransmit; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); - - /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */ - if (!(slaveAddress || slaveTransmit)) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - if (slaveAddress) - { - /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - - /* send bytes up to txSize */ - while (txSize) - { - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); - - if (!slaveTransmit) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - /* Write 8 bits of data to the SLVDAT register */ - base->SLVDAT = I2C_SLVDAT_DATA(*buf); - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* advance counters and pointers for next data */ - buf++; - txSize--; - - if (txSize) - { - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - } - - return kStatus_Success; -} - -/*! - * brief Performs a polling receive transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * param base The I2C peripheral base address. - * param rxBuff The pointer to the data to be transferred. - * param rxSize The length in bytes of the data to be transferred. - * return kStatus_Success Data has been received. - * return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). - */ -status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) -{ - uint8_t *buf = rxBuff; - uint32_t stat; - bool slaveAddress; - bool slaveReceive; - - /* Set the SLVEN bit to 1 in the CFG register. */ - I2C_SlaveEnable(base, true); - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - - /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); - - /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */ - if (!(slaveAddress || slaveReceive)) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - if (slaveAddress) - { - /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - - /* receive bytes up to rxSize */ - while (rxSize) - { - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); - - if (!slaveReceive) - { - I2C_SlaveInternalStateMachineReset(base); - return kStatus_Fail; - } - - /* Read 8 bits of data from the SLVDAT register */ - *buf = (uint8_t)base->SLVDAT; - - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - - /* advance counters and pointers for next data */ - buf++; - rxSize--; - - if (rxSize) - { - /* wait for SLVPENDING */ - stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } - } - } - - return kStatus_Success; -} - -/*! - * brief Creates a new handle for the I2C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. - * - * param base The I2C peripheral base address. - * param[out] handle Pointer to the I2C slave driver handle. - * param callback User provided pointer to the asynchronous callback function. - * param userData User provided pointer to the application callback data. - */ -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData) -{ - uint32_t instance; - - assert(handle); - - /* Clear out the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Save base and instance. */ - handle->callback = callback; - handle->userData = userData; - - /* initialize fsm */ - handle->slaveFsm = kI2C_SlaveFsmAddressMatch; - - /* store pointer to handle into transfer struct */ - handle->transfer.handle = handle; - - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_SlaveTransferHandleIRQ, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); - EnableIRQ(s_i2cIRQ[instance]); -} - -/*! - * brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. - * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. - * - * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * retval kStatus_Success Slave transfers were successfully started. - * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) -{ - return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask); -} - -/*! - * brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. - * - * param base I2C base pointer. - * param handle pointer to i2c_slave_handle_t structure. - * param count Number of bytes transferred so far by the non-blocking transaction. - * retval kStatus_InvalidArgument count is Invalid. - * retval kStatus_Success Successfully return the count. - */ -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (!handle->isBusy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* For an active transfer, just return the count from the handle. */ - *count = handle->transfer.transferredCount; - - return kStatus_Success; -} - -/*! - * brief Aborts the slave non-blocking transfers. - * note This API could be called at any time to stop slave for handling the bus events. - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * retval kStatus_Success - * retval #kStatus_I2C_Idle - */ -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) -{ - /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); - - /* Set the SLVEN bit to 0 in the CFG register. */ - I2C_SlaveEnable(base, false); - - handle->isBusy = false; - handle->transfer.txSize = 0; - handle->transfer.rxSize = 0; -} - -/*! - * brief Reusable routine to handle slave interrupts. - * note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * param base The I2C peripheral base address. - * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - */ -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) -{ - uint32_t i2cStatus = base->STAT; - - if (i2cStatus & I2C_STAT_SLVDESEL_MASK) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent); - I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK); - } - - /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */ - if (i2cStatus & I2C_STAT_SLVPENDING_MASK) - { - bool slaveAddress = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); - - if (slaveAddress) - { - I2C_SlaveAddressIRQ(base, handle); - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent); - } - else - { - switch (handle->slaveFsm) - { - case kI2C_SlaveFsmReceive: - { - bool slaveReceive = - (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); - - if (slaveReceive) - { - /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); - } - - /* receive a byte */ - if ((handle->transfer.rxData) && (handle->transfer.rxSize)) - { - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - *(handle->transfer.rxData) = (uint8_t)base->SLVDAT; - (handle->transfer.rxSize)--; - (handle->transfer.rxData)++; - (handle->transfer.transferredCount)++; - } - - /* is this last transaction for this transfer? allow next transaction */ - if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize)) - { - handle->isBusy = false; - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); - } - } - else - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - } - } - break; - - case kI2C_SlaveFsmTransmit: - { - bool slaveTransmit = - (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); - - if (slaveTransmit) - { - /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) - { - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); - } - - /* transmit a byte */ - if ((handle->transfer.txData) && (handle->transfer.txSize)) - { - base->SLVDAT = *(handle->transfer.txData); - /* continue transaction */ - base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - (handle->transfer.txSize)--; - (handle->transfer.txData)++; - (handle->transfer.transferredCount)++; - } - - /* is this last transaction for this transfer? allow next transaction */ - if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize)) - { - handle->isBusy = false; - I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); - } - } - else - { - base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; - } - } - break; - - default: - /* incorrect state, slv_abort()? */ - break; - } - } - } -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2c.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2c.h deleted file mode 100644 index 5470198aab..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2c.h +++ /dev/null @@ -1,1042 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2C_H_ -#define _FSL_I2C_H_ - -#include -#include "fsl_device_registers.h" -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define I2C_CFG_MASK 0x1f - -/*! - * @addtogroup i2c_driver - * @{ - */ - -/*! @file */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C driver version 2.0.3. */ -#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -/*! @brief Timeout times for waiting flag. */ -#ifndef I2C_WAIT_TIMEOUT -#define I2C_WAIT_TIMEOUT 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ -#endif - -/* definitions for MSTCODE bits in I2C Status register STAT */ -#define I2C_STAT_MSTCODE_IDLE (0) /*!< Master Idle State Code */ -#define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */ -#define I2C_STAT_MSTCODE_TXREADY (2) /*!< Master Transmit Ready State Code */ -#define I2C_STAT_MSTCODE_NACKADR (3) /*!< Master NACK by slave on address State Code */ -#define I2C_STAT_MSTCODE_NACKDAT (4) /*!< Master NACK by slave on data State Code */ - -/* definitions for SLVSTATE bits in I2C Status register STAT */ -#define I2C_STAT_SLVST_ADDR (0) -#define I2C_STAT_SLVST_RX (1) -#define I2C_STAT_SLVST_TX (2) - -/*! @brief I2C status return codes. */ -enum _i2c_status -{ - kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */ - kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */ - kStatus_I2C_Nak = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 2), /*!< The slave device sent a NAK in response to a byte. */ - kStatus_I2C_InvalidParameter = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 3), /*!< Unable to proceed due to invalid parameter. */ - kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */ - kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */ - kStatus_I2C_NoTransferInProgress = - MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 6), /*!< Attempt to abort a transfer when one is not in progress. */ - kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */ - kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), - kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), - kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 10), /*!< Timeout poling status flags. */ - kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 11), /*!< NAK received for Address */ -}; - -/*! @} */ - -/*! - * @addtogroup i2c_master_driver - * @{ - */ - -/*! - * @brief I2C master peripheral flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i2c_master_flags -{ - kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. */ - kI2C_MasterArbitrationLostFlag = - I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus */ - kI2C_MasterStartStopErrorFlag = - I2C_STAT_MSTSTSTPERR_MASK /*!< There was an error during start or stop phase of the transaction. */ -}; - -/*! @brief Direction of master and slave transfers. */ -typedef enum _i2c_direction -{ - kI2C_Write = 0U, /*!< Master transmit. */ - kI2C_Read = 1U /*!< Master receive. */ -} i2c_direction_t; - -/*! - * @brief Structure with settings to initialize the I2C master module. - * - * This structure holds configuration settings for the I2C peripheral. To initialize this - * structure to reasonable defaults, call the I2C_MasterGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _i2c_master_config -{ - bool enableMaster; /*!< Whether to enable master mode. */ - uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */ - bool enableTimeout; /*!< Enable internal timeout function. */ -} i2c_master_config_t; - -/* Forward declaration of the transfer descriptor and handle typedefs. */ -/*! @brief I2C master transfer typedef */ -typedef struct _i2c_master_transfer i2c_master_transfer_t; - -/*! @brief I2C master handle typedef */ -typedef struct _i2c_master_handle i2c_master_handle_t; - -/*! - * @brief Master completion callback function pointer type. - * - * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use - * in the call to I2C_MasterTransferCreateHandle(). - * - * @param base The I2C peripheral base address. - * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, - i2c_master_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! - * @brief Transfer option flags. - * - * @note These enumerations are intended to be OR'd together to form a bit mask of options for - * the #_i2c_master_transfer::flags field. - */ -enum _i2c_master_transfer_flags -{ - kI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ - kI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ - kI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ - kI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ -}; - -/*! @brief States for the state machine used by transactional APIs. */ -enum _i2c_transfer_states -{ - kIdleState = 0, - kTransmitSubaddrState, - kTransmitDataState, - kReceiveDataState, - kReceiveLastDataState, - kStartState, - kStopState, - kWaitForCompletionState -}; - -/*! - * @brief Non-blocking transfer descriptor structure. - * - * This structure is used to pass transaction parameters to the I2C_MasterTransferNonBlocking() API. - */ -struct _i2c_master_transfer -{ - uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available - options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */ - uint16_t slaveAddress; /*!< The 7-bit slave address. */ - i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */ - uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ - size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ - void *data; /*!< Pointer to data to transfer. */ - size_t dataSize; /*!< Number of bytes to transfer. */ -}; - -/*! - * @brief Driver handle for master non-blocking APIs. - * @note The contents of this structure are private and subject to change. - */ -struct _i2c_master_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint32_t transferCount; /*!< Indicates progress of the transfer */ - uint32_t remainingBytes; /*!< Remaining byte count in current state. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint32_t remainingSubaddr; - uint8_t subaddrBuf[4]; - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ - void *userData; /*!< Application data passed to callback. */ -}; - -/*! @} */ - -/*! - * @addtogroup i2c_slave_driver - * @{ - */ - -/*! -* @brief I2C slave peripheral flags. -* -* @note These enums are meant to be OR'd together to form a bit mask. -*/ -enum _i2c_slave_flags -{ - kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. */ - kI2C_SlaveNotStretching = - I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 = yes, 1 = no). */ - kI2C_SlaveSelected = I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. */ - kI2C_SaveDeselected = - I2C_STAT_SLVDESEL_MASK /*!< Indicates that slave was previously deselected (deselect event took place, w1c). */ -}; - -/*! @brief I2C slave address register. */ -typedef enum _i2c_slave_address_register -{ - kI2C_SlaveAddressRegister0 = 0U, /*!< Slave Address 0 register. */ - kI2C_SlaveAddressRegister1 = 1U, /*!< Slave Address 1 register. */ - kI2C_SlaveAddressRegister2 = 2U, /*!< Slave Address 2 register. */ - kI2C_SlaveAddressRegister3 = 3U, /*!< Slave Address 3 register. */ -} i2c_slave_address_register_t; - -/*! @brief Data structure with 7-bit Slave address and Slave address disable. */ -typedef struct _i2c_slave_address -{ - uint8_t address; /*!< 7-bit Slave address SLVADR. */ - bool addressDisable; /*!< Slave address disable SADISABLE. */ -} i2c_slave_address_t; - -/*! @brief I2C slave address match options. */ -typedef enum _i2c_slave_address_qual_mode -{ - kI2C_QualModeMask = 0U, /*!< The SLVQUAL0 field (qualAddress) is used as a logical mask for matching address0. */ - kI2C_QualModeExtend = - 1U, /*!< The SLVQUAL0 (qualAddress) field is used to extend address 0 matching in a range of addresses. */ -} i2c_slave_address_qual_mode_t; - -/*! @brief I2C slave bus speed options. */ -typedef enum _i2c_slave_bus_speed -{ - kI2C_SlaveStandardMode = 0U, - kI2C_SlaveFastMode = 1U, - kI2C_SlaveFastModePlus = 2U, - kI2C_SlaveHsMode = 3U, -} i2c_slave_bus_speed_t; - -/*! - * @brief Structure with settings to initialize the I2C slave module. - * - * This structure holds configuration settings for the I2C slave peripheral. To initialize this - * structure to reasonable defaults, call the I2C_SlaveGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _i2c_slave_config -{ - i2c_slave_address_t address0; /*!< Slave's 7-bit address and disable. */ - i2c_slave_address_t address1; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_t address2; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_t address3; /*!< Alternate slave 7-bit address and disable. */ - i2c_slave_address_qual_mode_t qualMode; /*!< Qualify mode for slave address 0. */ - uint8_t qualAddress; /*!< Slave address qualifier for address 0. */ - i2c_slave_bus_speed_t - busSpeed; /*!< Slave bus speed mode. If the slave function stretches SCL to allow for software response, it must - provide sufficient data setup time to the master before releasing the stretched clock. - This is accomplished by inserting one clock time of CLKDIV at that point. - The #busSpeed value is used to configure CLKDIV - such that one clock time is greater than the tSU;DAT value noted - in the I2C bus specification for the I2C mode that is being used. - If the #busSpeed mode is unknown at compile time, use the longest data setup time - kI2C_SlaveStandardMode (250 ns) */ - bool enableSlave; /*!< Enable slave mode. */ -} i2c_slave_config_t; - -/*! - * @brief Set of events sent to the callback for non blocking slave transfers. - * - * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together - * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable. - * Then, when the slave callback is invoked, it is passed the current event through its @a transfer - * parameter. - * - * @note These enumerations are meant to be OR'd together to form a bit mask of events. - */ -typedef enum _i2c_slave_transfer_event -{ - kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ - kI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit - (slave-transmitter role). */ - kI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received - data (slave-receiver role). */ - kI2C_SlaveCompletionEvent = 0x20U, /*!< All data in the active transfer have been consumed. */ - kI2C_SlaveDeselectedEvent = - 0x40U, /*!< The slave function has become deselected (SLVSEL flag changing from 1 to 0. */ - - /*! Bit mask of all available events. */ - kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | - kI2C_SlaveCompletionEvent | kI2C_SlaveDeselectedEvent, -} i2c_slave_transfer_event_t; - -/*! @brief I2C slave handle typedef. */ -typedef struct _i2c_slave_handle i2c_slave_handle_t; - -/*! @brief I2C slave transfer structure */ -typedef struct _i2c_slave_transfer -{ - i2c_slave_handle_t *handle; /*!< Pointer to handle that contains this transfer. */ - i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ - uint8_t receivedAddress; /*!< Matching address send by master. 7-bits plus R/nW bit0 */ - uint32_t eventMask; /*!< Mask of enabled events. */ - uint8_t *rxData; /*!< Transfer buffer for receive data */ - const uint8_t *txData; /*!< Transfer buffer for transmit data */ - size_t txSize; /*!< Transfer size */ - size_t rxSize; /*!< Transfer size */ - size_t transferredCount; /*!< Number of bytes transferred during this transfer. */ - status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for - #kI2C_SlaveCompletionEvent. */ -} i2c_slave_transfer_t; - -/*! - * @brief Slave event callback function pointer type. - * - * This callback is used only for the slave non-blocking transfer API. To install a callback, - * use the I2C_SlaveSetCallback() function after you have created a handle. - * - * @param base Base address for the I2C instance on which the event occurred. - * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *userData); - -/*! - * @brief I2C slave software finite state machine states. - */ -typedef enum _i2c_slave_fsm -{ - kI2C_SlaveFsmAddressMatch = 0u, - kI2C_SlaveFsmReceive = 2u, - kI2C_SlaveFsmTransmit = 3u, -} i2c_slave_fsm_t; - -/*! - * @brief I2C slave handle structure. - * @note The contents of this structure are private and subject to change. - */ -struct _i2c_slave_handle -{ - volatile i2c_slave_transfer_t transfer; /*!< I2C slave transfer. */ - volatile bool isBusy; /*!< Whether transfer is busy. */ - volatile i2c_slave_fsm_t slaveFsm; /*!< slave transfer state machine. */ - i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ - void *userData; /*!< Callback parameter passed to callback. */ -}; - -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup i2c_master_driver - * @{ - */ - -/*! @name Initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I2C master peripheral. - * - * This function provides the following default configuration for the I2C master peripheral: - * @code - * masterConfig->enableMaster = true; - * masterConfig->baudRate_Bps = 100000U; - * masterConfig->enableTimeout = false; - * @endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with I2C_MasterInit(). - * - * @param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. - */ -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); - -/*! - * @brief Initializes the I2C master peripheral. - * - * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * @param base The I2C peripheral base address. - * @param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of - * defaults - * that you can override. - * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! -* @brief Deinitializes the I2C master peripheral. -* - * This function disables the I2C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -void I2C_MasterDeinit(I2C_Type *base); - -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The I2C peripheral base address. - * @return I2C instance number starting from 0. - */ -uint32_t I2C_GetInstance(I2C_Type *base); - -/*! - * @brief Performs a software reset. - * - * Restores the I2C master peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -static inline void I2C_MasterReset(I2C_Type *base) -{ -} - -/*! - * @brief Enables or disables the I2C module as master. - * - * @param base The I2C peripheral base address. - * @param enable Pass true to enable or false to disable the specified I2C as master. - */ -static inline void I2C_MasterEnable(I2C_Type *base, bool enable) -{ - if (enable) - { - base->CFG = (base->CFG & I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; - } - else - { - base->CFG = (base->CFG & I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; - } -} - -/*@}*/ - -/*! @name Status */ -/*@{*/ - -/*! - * @brief Gets the I2C status flags. - * - * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * @param base The I2C peripheral base address. - * @return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * @see _i2c_master_flags - */ -static inline uint32_t I2C_GetStatusFlags(I2C_Type *base) -{ - return base->STAT; -} - -/*! - * @brief Clears the I2C master status flag state. - * - * The following status register flags can be cleared: - * - #kI2C_MasterArbitrationLostFlag - * - #kI2C_MasterStartStopErrorFlag - * - * Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_i2c_master_flags enumerators OR'd together. You may pass the result of a previous call to - * I2C_GetStatusFlags(). - * @see _i2c_master_flags. - */ -static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Allow clearing just master status flags */ - base->STAT = statusMask & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); -} - -/*@}*/ - -/*! @name Interrupts */ -/*@{*/ - -/*! - * @brief Enables the I2C master interrupt requests. - * - * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to enable. See #_i2c_master_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask) -{ - base->INTENSET = interruptMask; -} - -/*! - * @brief Disables the I2C master interrupt requests. - * - * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to disable. See #_i2c_master_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask) -{ - base->INTENCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I2C master interrupt requests. - * - * @param base The I2C peripheral base address. - * @return A bitmask composed of #_i2c_master_flags enumerators OR'd together to indicate the - * set of enabled interrupts. - */ -static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base) -{ - return base->INTSTAT; -} - -/*@}*/ - -/*! @name Bus operations */ -/*@{*/ - -/*! - * @brief Sets the I2C bus frequency for master transactions. - * - * The I2C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * @param base The I2C peripheral base address. - * @param srcClock_Hz I2C functional clock frequency in Hertz. - * @param baudRate_Bps Requested bus frequency in bits per second. - */ -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Returns whether the bus is idle. - * - * Requires the master mode to be enabled. - * - * @param base The I2C peripheral base address. - * @retval true Bus is busy. - * @retval false Bus is idle. - */ -static inline bool I2C_MasterGetBusIdleState(I2C_Type *base) -{ - /* True if MSTPENDING flag is set and MSTSTATE is zero == idle */ - return ((base->STAT & (I2C_STAT_MSTPENDING_MASK | I2C_STAT_MSTSTATE_MASK)) == I2C_STAT_MSTPENDING_MASK); -} - -/*! - * @brief Sends a START on the I2C bus. - * - * This function is used to initiate a new master mode transfer by sending the START signal. - * The slave address is sent following the I2C START signal. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy. - */ -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); - -/*! - * @brief Sends a STOP signal on the I2C bus. - * - * @retval kStatus_Success Successfully send the stop signal. - * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterStop(I2C_Type *base); - -/*! - * @brief Sends a REPEATED START on the I2C bus. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. - */ -static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - return I2C_MasterStart(base, address, direction); -} - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_I2C_Nak. - * - * @param base The I2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * @retval kStatus_Success Data was sent successfully. - * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * @param base The I2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers - * use kI2C_TransferDefaultFlag - * @retval kStatus_Success Data was received successfully. - * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. - */ -status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags); - -/*! - * @brief Performs a master polling transfer on the I2C bus. - * - * @note The API does not return until the transfer succeeds or fails due - * to arbitration lost or receiving a NAK. - * - * @param base I2C peripheral base address. - * @param xfer Pointer to the transfer structure. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - */ -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); - -/*@}*/ - -/*! @name Non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I2C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. - * - * @param base The I2C peripheral base address. - * @param[out] handle Pointer to the I2C master driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a non-blocking transaction on the I2C bus. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @param xfer The pointer to the transfer descriptor. - * @retval kStatus_Success The transaction was started successfully. - * @retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Returns number of bytes transferred so far. - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @param[out] count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_Success - * @retval #kStatus_I2C_Busy - */ -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); - -/*! - * @brief Terminates a non-blocking I2C master transmission early. - * - * @note It is not safe to call this function from an IRQ handler that has a higher priority than the - * I2C peripheral's IRQ priority. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - * @retval kStatus_Success A transaction was successfully aborted. - * @retval #kStatus_I2C_Timeout Timeout during polling for flags. - */ -status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); - -/*@}*/ - -/*! @name IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle master interrupts. - * @note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * @param base The I2C peripheral base address. - * @param handle Pointer to the I2C master driver handle. - */ -void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle); - -/*@}*/ - -/*! @} */ /* end of i2c_master_driver */ - -/*! - * @addtogroup i2c_slave_driver - * @{ - */ - -/*! @name Slave initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the I2C slave peripheral. - * - * This function provides the following default configuration for the I2C slave peripheral: - * @code - * slaveConfig->enableSlave = true; - * slaveConfig->address0.disable = false; - * slaveConfig->address0.address = 0u; - * slaveConfig->address1.disable = true; - * slaveConfig->address2.disable = true; - * slaveConfig->address3.disable = true; - * slaveConfig->busSpeed = kI2C_SlaveStandardMode; - * @endcode - * - * After calling this function, override any settings to customize the configuration, - * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the @a - * address0.address member of the configuration structure with the desired slave address. - * - * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to - * #i2c_slave_config_t. - */ -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); - -/*! - * @brief Initializes the I2C slave peripheral. - * - * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user - * provided configuration. - * - * @param base The I2C peripheral base address. - * @param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults - * that you can override. - * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide - * enough - * data setup time for master when slave stretches the clock. - */ -status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz); - -/*! - * @brief Configures Slave Address n register. - * - * This function writes new value to Slave Address register. - * - * @param base The I2C peripheral base address. - * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be - * changed. - * @param address The slave address to be stored to the address register for matching. - * @param addressDisable Disable matching of the specified address register. - */ -void I2C_SlaveSetAddress(I2C_Type *base, - i2c_slave_address_register_t addressRegister, - uint8_t address, - bool addressDisable); - -/*! -* @brief Deinitializes the I2C slave peripheral. -* - * This function disables the I2C slave peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The I2C peripheral base address. - */ -void I2C_SlaveDeinit(I2C_Type *base); - -/*! - * @brief Enables or disables the I2C module as slave. - * - * @param base The I2C peripheral base address. - * @param enable True to enable or flase to disable. - */ -static inline void I2C_SlaveEnable(I2C_Type *base, bool enable) -{ - /* Set or clear the SLVEN bit in the CFG register. */ - base->CFG = I2C_CFG_SLVEN(enable); -} - -/*@}*/ /* end of Slave initialization and deinitialization */ - -/*! @name Slave status */ -/*@{*/ - -/*! - * @brief Clears the I2C status flag state. - * - * The following status register flags can be cleared: - * - slave deselected flag - * - * Attempts to clear other flags has no effect. - * - * @param base The I2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to - * I2C_SlaveGetStatusFlags(). - * @see _i2c_slave_flags. - */ -static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - /* Allow clearing just slave status flags */ - base->STAT = statusMask & I2C_STAT_SLVDESEL_MASK; -} - -/*@}*/ /* end of Slave status */ - -/*! @name Slave bus operations */ -/*@{*/ - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * @param base The I2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @return kStatus_Success Data has been sent. - * @return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). - */ -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * The function executes blocking address phase and blocking data phase. - * - * @param base The I2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @return kStatus_Success Data has been received. - * @return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). - */ -status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); - -/*@}*/ /* end of Slave bus operations */ - -/*! @name Slave non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the I2C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. - * - * @param base The I2C peripheral base address. - * @param[out] handle Pointer to the I2C slave driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. - * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); - -/*! - * @brief Starts accepting master read from slave requests. - * - * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param transfer Pointer to #i2c_slave_transfer_t structure. - * @param txData Pointer to data to send to master. - * @param txSize Size of txData in bytes. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetSendBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask); - -/*! - * @brief Starts accepting master write to slave requests. - * - * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer - * from within the transfer callback. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param transfer Pointer to #i2c_slave_transfer_t structure. - * @param rxData Pointer to data to store data from master. - * @param rxSize Size of rxData in bytes. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveSetReceiveBuffer( - I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask); - -/*! - * @brief Returns the slave address sent by the I2C master. - * - * This function should only be called from the address match event callback #kI2C_SlaveAddressMatchEvent. - * - * @param base The I2C peripheral base address. - * @param transfer The I2C slave transfer. - * @return The 8-bit address matched by the I2C slave. Bit 0 contains the R/w direction bit, and - * the 7-bit slave address is in the upper 7 bits. - */ -static inline uint32_t I2C_SlaveGetReceivedAddress(I2C_Type *base, volatile i2c_slave_transfer_t *transfer) -{ - return transfer->receivedAddress; -} - -/*! - * @brief Aborts the slave non-blocking transfers. - * @note This API could be called at any time to stop slave for handling the bus events. - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - * @retval kStatus_Success - * @retval #kStatus_I2C_Idle - */ -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); - -/*! - * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_slave_handle_t structure. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); - -/*@}*/ /* end of Slave non-blocking */ - -/*! @name Slave IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle slave interrupts. - * @note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * @param base The I2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. - */ -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle); - -/*@}*/ /* end of Slave IRQ handler */ - -/*! @} */ /* end of i2c_slave_driver */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2C_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2c_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2c_dma.c deleted file mode 100644 index 14b6025a92..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2c_dma.c +++ /dev/null @@ -1,588 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2c_dma.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_dma" -#endif - -/*transfer = *xfer; - transfer = &(handle->transfer); - - handle->transferCount = 0; - handle->remainingBytesDMA = 0; - handle->buf = (uint8_t *)transfer->data; - handle->remainingSubaddr = 0; - - if (transfer->flags & kI2C_TransferNoStartFlag) - { - /* Start condition shall be ommited, switch directly to next phase */ - if (transfer->dataSize == 0) - { - handle->state = kStopState; - } - else if (handle->transfer.direction == kI2C_Write) - { - handle->state = xfer->dataSize = kTransmitDataState; - } - else if (handle->transfer.direction == kI2C_Read) - { - handle->state = (xfer->dataSize == 1) ? kReceiveLastDataState : kReceiveDataState; - } - else - { - return kStatus_I2C_InvalidParameter; - } - } - else - { - if (transfer->subaddressSize != 0) - { - int i; - uint32_t subaddress; - - if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) - { - return kStatus_I2C_InvalidParameter; - } - - /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ - subaddress = xfer->subaddress; - for (i = xfer->subaddressSize - 1; i >= 0; i--) - { - handle->subaddrBuf[i] = subaddress & 0xff; - subaddress >>= 8; - } - handle->remainingSubaddr = transfer->subaddressSize; - } - - handle->state = kStartState; - } - - return kStatus_Success; -} - -static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - int transfer_size; - dma_transfer_config_t xferConfig; - - /* Update transfer count */ - handle->transferCount = handle->buf - (uint8_t *)handle->transfer.data; - - /* Check if there is anything to be transferred at all */ - if (handle->remainingBytesDMA == 0) - { - /* No data to be transferrred, disable DMA */ - base->MSTCTL = 0; - return; - } - - /* Calculate transfer size */ - transfer_size = handle->remainingBytesDMA; - if (transfer_size > I2C_MAX_DMA_TRANSFER_COUNT) - { - transfer_size = I2C_MAX_DMA_TRANSFER_COUNT; - } - - switch (handle->transfer.direction) - { - case kI2C_Write: - DMA_PrepareTransfer(&xferConfig, handle->buf, (void *)&base->MSTDAT, sizeof(uint8_t), transfer_size, - kDMA_MemoryToPeripheral, NULL); - break; - - case kI2C_Read: - DMA_PrepareTransfer(&xferConfig, (void *)&base->MSTDAT, handle->buf, sizeof(uint8_t), transfer_size, - kDMA_PeripheralToMemory, NULL); - break; - - default: - /* This should never happen */ - assert(0); - break; - } - - DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - DMA_StartTransfer(handle->dmaHandle); - - handle->remainingBytesDMA -= transfer_size; - handle->buf += transfer_size; -} - -/*! - * @brief Execute states until the transfer is done. - * @param handle Master nonblocking driver handle. - * @param[out] isDone Set to true if the transfer has completed. - * @retval #kStatus_Success - * @retval #kStatus_I2C_ArbitrationLost - * @retval #kStatus_I2C_Nak - */ -static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone) -{ - uint32_t status; - uint32_t master_state; - struct _i2c_master_transfer *transfer; - dma_transfer_config_t xferConfig; - status_t err; - uint32_t start_flag = 0; - - transfer = &(handle->transfer); - - *isDone = false; - - status = I2C_GetStatusFlags(base); - - if (status & I2C_STAT_MSTARBLOSS_MASK) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_ArbitrationLost; - } - - if (status & I2C_STAT_MSTSTSTPERR_MASK) - { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = 0; - return kStatus_I2C_StartStopError; - } - - if ((status & I2C_STAT_MSTPENDING_MASK) == 0) - { - return kStatus_I2C_Busy; - } - - /* Get the state of the I2C module */ - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT)) - { - /* Slave NACKed last byte, issue stop and return error */ - DMA_AbortTransfer(handle->dmaHandle); - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - return kStatus_I2C_Nak; - } - - err = kStatus_Success; - - if (handle->state == kStartState) - { - /* set start flag for later use */ - start_flag = I2C_MSTCTL_MSTSTART_MASK; - - if (handle->remainingSubaddr) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = kTransmitSubaddrState; - } - else if (transfer->direction == kI2C_Write) - { - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - if (transfer->dataSize == 0) - { - /* No data to be transferred, initiate start and schedule stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = kStopState; - return err; - } - handle->state = kTransmitDataState; - } - else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0)) - { - base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - if (transfer->dataSize == 1) - { - /* The very last byte is always received by means of SW */ - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = kReceiveLastDataState; - return err; - } - handle->state = kReceiveDataState; - } - else - { - handle->state = kIdleState; - err = kStatus_I2C_UnexpectedState; - return err; - } - } - - switch (handle->state) - { - case kTransmitSubaddrState: - if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - - /* Prepare and submit DMA transfer. */ - DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (void *)&base->MSTDAT, sizeof(uint8_t), - handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL); - DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - DMA_StartTransfer(handle->dmaHandle); - handle->remainingSubaddr = 0; - if (transfer->dataSize) - { - /* There is data to be transferred, if there is write to read turnaround it is necessary to perform - * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState; - } - else - { - /* No more data, schedule stop condition */ - handle->state = kStopState; - } - break; - - case kTransmitDataState: - if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - handle->remainingBytesDMA = handle->transfer.dataSize; - - I2C_RunDMATransfer(base, handle); - - /* Schedule stop condition */ - handle->state = kStopState; - break; - - case kReceiveDataState: - if ((master_state != I2C_STAT_MSTCODE_RXREADY) && (!start_flag)) - { - return kStatus_I2C_UnexpectedState; - } - - base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - handle->remainingBytesDMA = handle->transfer.dataSize - 1; - - I2C_RunDMATransfer(base, handle); - - /* Schedule reception of last data byte */ - handle->state = kReceiveLastDataState; - break; - - case kReceiveLastDataState: - if (master_state != I2C_STAT_MSTCODE_RXREADY) - { - return kStatus_I2C_UnexpectedState; - } - - ((uint8_t *)transfer->data)[transfer->dataSize - 1] = base->MSTDAT; - handle->transferCount++; - - /* No more data expected, issue NACK and STOP right away */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - break; - - case kStopState: - if (transfer->flags & kI2C_TransferNoStopFlag) - { - /* Stop condition is omitted, we are done */ - *isDone = true; - handle->state = kIdleState; - break; - } - /* Send stop condition */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - break; - - case kWaitForCompletionState: - *isDone = true; - handle->state = kIdleState; - break; - - case kStartState: - case kIdleState: - default: - /* State machine shall not be invoked again once it enters the idle state */ - err = kStatus_I2C_UnexpectedState; - break; - } - - return err; -} - -void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (!handle) - { - return; - } - - result = I2C_RunTransferStateMachineDMA(base, handle, &isDone); - - if (isDone || (result != kStatus_Success)) - { - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, - I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); - - /* Invoke callback. */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData) -{ - i2c_master_dma_private_handle_t *dmaPrivateHandle; - - /* Don't do anything if we don't have a valid handle. */ - if (!handle) - { - return; - } - - dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData; - I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle); -} - -/*! - * brief Init the I2C handle which is used in transcational functions - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param callback pointer to user callback function - * param userData user param passed to the callback function - * param dmaHandle DMA handle pointer - */ -void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, - i2c_master_dma_handle_t *handle, - i2c_master_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *dmaHandle) -{ - uint32_t instance; - - assert(handle); - assert(dmaHandle); - - /* Zero handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = I2C_GetInstance(base); - - /* Set the user callback and userData. */ - handle->completionCallback = callback; - handle->userData = userData; - - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_MasterTransferDMAHandleIRQ, handle); - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, - I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); - EnableIRQ(s_i2cIRQ[instance]); - - /* Set the handle for DMA. */ - handle->dmaHandle = dmaHandle; - - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - DMA_SetCallback(dmaHandle, (dma_callback)I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]); -} - -/*! - * brief Performs a master dma non-blocking transfer on the I2C bus - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param xfer pointer to transfer structure of i2c_master_transfer_t - * retval kStatus_Success Sucessully complete the data transmission. - * retval kStatus_I2C_Busy Previous transmission still not finished. - * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. - */ -status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result; - - assert(handle); - assert(xfer); - assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != kIdleState) - { - return kStatus_I2C_Busy; - } - - /* Prepare transfer state machine. */ - result = I2C_InitTransferStateMachineDMA(base, handle, xfer); - - /* Clear error flags. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Enable I2C internal IRQ sources */ - I2C_EnableInterrupts(base, - I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_MSTPENDING_MASK); - - return result; -} - -/*! - * brief Get master transfer status during a dma non-blocking transfer - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - * param count Number of bytes transferred so far by the non-blocking transaction. - */ -status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* There is no necessity to disable interrupts as we read a single integer value */ - *count = handle->transferCount; - return kStatus_Success; -} - -/*! - * brief Abort a master dma non-blocking transfer in a early time - * - * param base I2C peripheral base address - * param handle pointer to i2c_master_dma_handle_t structure - */ -void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle) -{ - uint32_t status; - uint32_t master_state; - - if (handle->state != kIdleState) - { - DMA_AbortTransfer(handle->dmaHandle); - - /* Disable DMA */ - base->MSTCTL = 0; - - /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, - I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); - - /* Wait until module is ready */ - do - { - status = I2C_GetStatusFlags(base); - } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Get the state of the I2C module */ - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (master_state != I2C_STAT_MSTCODE_IDLE) - { - /* Send a stop command to finalize the transfer. */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - - /* Wait until module is ready */ - do - { - status = I2C_GetStatusFlags(base); - } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - } - - /* Reset the state to idle. */ - handle->state = kIdleState; - } -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2c_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2c_dma.h deleted file mode 100644 index a836b1e3e7..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2c_dma.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2C_DMA_H_ -#define _FSL_I2C_DMA_H_ - -#include "fsl_i2c.h" -#include "fsl_dma.h" - -/*! - * @addtogroup i2c_dma_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C DMA driver version 2.0.3. */ -#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */ -#define I2C_MAX_DMA_TRANSFER_COUNT 1024 - -/*! @brief I2C master dma handle typedef. */ -typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t; - -/*! @brief I2C master dma transfer callback typedef. */ -typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base, - i2c_master_dma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief I2C master dma transfer structure. */ -struct _i2c_master_dma_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint32_t transferCount; /*!< Indicates progress of the transfer */ - uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint32_t remainingSubaddr; - uint8_t subaddrBuf[4]; - dma_handle_t *dmaHandle; /*!< The DMA handler used. */ - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */ - void *userData; /*!< Callback parameter passed to callback function. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus. */ - -/*! - * @name I2C Block DMA Transfer Operation - * @{ - */ - -/*! - * @brief Init the I2C handle which is used in transcational functions - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param callback pointer to user callback function - * @param userData user param passed to the callback function - * @param dmaHandle DMA handle pointer - */ -void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, - i2c_master_dma_handle_t *handle, - i2c_master_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *dmaHandle); - -/*! - * @brief Performs a master dma non-blocking transfer on the I2C bus - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param xfer pointer to transfer structure of i2c_master_transfer_t - * @retval kStatus_Success Sucessully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. - */ -status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Get master transfer status during a dma non-blocking transfer - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - * @param count Number of bytes transferred so far by the non-blocking transaction. - */ -status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count); - -/*! - * @brief Abort a master dma non-blocking transfer in a early time - * - * @param base I2C peripheral base address - * @param handle pointer to i2c_master_dma_handle_t structure - */ -void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle); - -/* @} */ -#if defined(__cplusplus) -} -#endif /*_cplusplus. */ -/*@}*/ -#endif /*_FSL_I2C_DMA_H_*/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2s.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2s.c deleted file mode 100644 index a4611b2c03..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2s.c +++ /dev/null @@ -1,1053 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_i2s.h" -#include "fsl_flexcomm.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s" -#endif - -/* TODO - absent in device header files, should be there */ -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) - -/*! @brief I2S states. */ -enum _i2s_state -{ - kI2S_StateIdle = 0x0, /*!< Not performing transfer */ - kI2S_StateTx, /*!< Performing transmit */ - kI2S_StateTxWaitToWriteDummyData, /*!< Wait on FIFO in order to write final dummy data there */ - kI2S_StateTxWaitForEmptyFifo, /*!< Wait for FIFO to be flushed */ - kI2S_StateRx, /*!< Performing receive */ -}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -static void I2S_Config(I2S_Type *base, const i2s_config_t *config); -static void I2S_TxEnable(I2S_Type *base, bool enable); -static void I2S_RxEnable(I2S_Type *base, bool enable); -static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map i2c instance number to base address. */ -static const uint32_t s_i2sBaseAddrs[FSL_FEATURE_SOC_I2S_COUNT] = I2S_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_i2sIRQ[] = I2S_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * param base The I2C peripheral base address. - * return I2C instance number starting from 0. - */ -uint32_t I2S_GetInstance(I2S_Type *base) -{ - int i; - for (i = 0; i < FSL_FEATURE_SOC_I2S_COUNT; i++) - { - if ((uint32_t)base == s_i2sBaseAddrs[i]) - { - return i; - } - } - assert(false); - return 0; -} -/*! - * brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S transmission using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_TxGetDefaultConfig(). - * - * note This API should be called at the beginning of the application to use - * the I2S driver. - * - * param base I2S base pointer. - * param config pointer to I2S configuration structure. - */ -void I2S_TxInit(I2S_Type *base, const i2s_config_t *config) -{ - uint32_t cfg = 0U; - uint32_t trig = 0U; - - FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX); - I2S_Config(base, config); - - /* Configure FIFO */ - - cfg |= I2S_FIFOCFG_ENABLETX(1U); /* enable TX FIFO */ - cfg |= I2S_FIFOCFG_EMPTYTX(1U); /* empty TX FIFO */ - cfg |= I2S_FIFOCFG_TXI2SE0(config->txEmptyZero); /* transmit zero when buffer becomes empty or last item */ - cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ - trig |= I2S_FIFOTRIG_TXLVLENA(1U); /* enable TX FIFO trigger */ - trig |= I2S_FIFOTRIG_TXLVL(config->watermark); /* set TX FIFO trigger level */ - - base->FIFOCFG = cfg; - base->FIFOTRIG = trig; -} - -/*! - * brief Initializes the FLEXCOMM peripheral for I2S receive functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S receive using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_RxGetDefaultConfig(). - * - * note This API should be called at the beginning of the application to use - * the I2S driver. - * - * param base I2S base pointer. - * param config pointer to I2S configuration structure. - */ -void I2S_RxInit(I2S_Type *base, const i2s_config_t *config) -{ - uint32_t cfg = 0U; - uint32_t trig = 0U; - - FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX); - I2S_Config(base, config); - - /* Configure FIFO */ - - cfg |= I2S_FIFOCFG_ENABLERX(1U); /* enable RX FIFO */ - cfg |= I2S_FIFOCFG_EMPTYRX(1U); /* empty RX FIFO */ - cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ - trig |= I2S_FIFOTRIG_RXLVLENA(1U); /* enable RX FIFO trigger */ - trig |= I2S_FIFOTRIG_RXLVL(config->watermark); /* set RX FIFO trigger level */ - - base->FIFOCFG = cfg; - base->FIFOTRIG = trig; -} - -/*! - * brief Sets the I2S Tx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_TxInit(). - * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified - * before calling I2S_TxInit(). - * Example: - code - i2s_config_t config; - I2S_TxGetDefaultConfig(&config); - endcode - * - * Default values: - * code - * config->masterSlave = kI2S_MasterSlaveNormalMaster; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = true; - * config->pack48 = false; - * endcode - * - * param config pointer to I2S configuration structure. - */ -void I2S_TxGetDefaultConfig(i2s_config_t *config) -{ - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - - config->masterSlave = kI2S_MasterSlaveNormalMaster; - config->mode = kI2S_ModeI2sClassic; - config->rightLow = false; - config->leftJust = false; -#if defined(I2S_CFG1_PDMDATA) - config->pdmData = false; -#endif - config->sckPol = false; - config->wsPol = false; - config->divider = 1U; - config->oneChannel = false; - config->dataLength = 16U; - config->frameLength = 32U; - config->position = 0U; - config->watermark = 4U; - config->txEmptyZero = true; - config->pack48 = false; -} - -/*! - * brief Sets the I2S Rx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_RxInit(). - * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified - * before calling I2S_RxInit(). - * Example: - code - i2s_config_t config; - I2S_RxGetDefaultConfig(&config); - endcode - * - * Default values: - * code - * config->masterSlave = kI2S_MasterSlaveNormalSlave; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = false; - * config->pack48 = false; - * endcode - * - * param config pointer to I2S configuration structure. - */ -void I2S_RxGetDefaultConfig(i2s_config_t *config) -{ - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - - config->masterSlave = kI2S_MasterSlaveNormalSlave; - config->mode = kI2S_ModeI2sClassic; - config->rightLow = false; - config->leftJust = false; -#if defined(I2S_CFG1_PDMDATA) - config->pdmData = false; -#endif - config->sckPol = false; - config->wsPol = false; - config->divider = 1U; - config->oneChannel = false; - config->dataLength = 16U; - config->frameLength = 32U; - config->position = 0U; - config->watermark = 4U; - config->txEmptyZero = false; - config->pack48 = false; -} - -static void I2S_Config(I2S_Type *base, const i2s_config_t *config) -{ - assert(config); - - uint32_t cfg1 = 0U; - uint32_t cfg2 = 0U; - - /* set master/slave configuration */ - cfg1 |= I2S_CFG1_MSTSLVCFG(config->masterSlave); - - /* set I2S mode */ - cfg1 |= I2S_CFG1_MODE(config->mode); - - /* set right low (channel swap) */ - cfg1 |= I2S_CFG1_RIGHTLOW(config->rightLow); - - /* set data justification */ - cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust); - -#if defined(I2S_CFG1_PDMDATA) - /* set source to PDM dmic */ - cfg1 |= I2S_CFG1_PDMDATA(config->pdmData); -#endif - - /* set SCLK polarity */ - cfg1 |= I2S_CFG1_SCK_POL(config->sckPol); - - /* set WS polarity */ - cfg1 |= I2S_CFG1_WS_POL(config->wsPol); - - /* set mono mode */ - cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel); - - /* set data length */ - cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1U); - - /* set frame length */ - cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1U); - - /* set data position of this channel pair within the frame */ - cfg2 |= I2S_CFG2_POSITION(config->position); - - /* write to registers */ - base->CFG1 = cfg1; - base->CFG2 = cfg2; - - /* set the clock divider */ - base->DIV = I2S_DIV_DIV(config->divider - 1U); -} - -/*! - * brief De-initializes the I2S peripheral. - * - * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit - * or I2S_RxInit is called to enable the clock. - * - * param base I2S base pointer. - */ -void I2S_Deinit(I2S_Type *base) -{ - /* TODO gate FLEXCOMM clock via FLEXCOMM driver */ -} - -static void I2S_TxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - I2S_EnableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); - I2S_Enable(base); - } - else - { - I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); - I2S_Disable(base); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - } -} - -static void I2S_RxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - I2S_EnableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); - I2S_Enable(base); - } - else - { - I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); - I2S_Disable(base); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - } -} - -static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer) -{ - assert(transfer->data); - if (!transfer->data) - { - return kStatus_InvalidArgument; - } - - assert(transfer->dataSize > 0U); - if (transfer->dataSize <= 0U) - { - return kStatus_InvalidArgument; - } - - if (handle->dataLength == 4U) - { - /* No alignment and data length requirements */ - } - else if ((handle->dataLength >= 5U) && (handle->dataLength <= 8U)) - { - assert((((uint32_t)transfer->data) % 2U) == 0U); - if ((((uint32_t)transfer->data) % 2U) != 0U) - { - /* Data not 2-bytes aligned */ - return kStatus_InvalidArgument; - } - - assert((transfer->dataSize % 2U) == 0U); - if ((transfer->dataSize % 2U) != 0U) - { - /* Data not in pairs of left/right channel bytes */ - return kStatus_InvalidArgument; - } - } - else if ((handle->dataLength >= 9U) && (handle->dataLength <= 16U)) - { - assert((((uint32_t)transfer->data) % 4U) == 0U); - if ((((uint32_t)transfer->data) % 4U) != 0U) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - - assert((transfer->dataSize % 4U) == 0U); - if ((transfer->dataSize % 4U) != 0U) - { - /* Data lenght not multiply of 4 */ - return kStatus_InvalidArgument; - } - } - else if ((handle->dataLength >= 17U) && (handle->dataLength <= 24U)) - { - assert((transfer->dataSize % 6U) == 0U); - if ((transfer->dataSize % 6U) != 0U) - { - /* Data lenght not multiply of 6 */ - return kStatus_InvalidArgument; - } - - assert(!((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U))); - if ((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U)) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - } - else /* if (handle->dataLength >= 25U) */ - { - assert((((uint32_t)transfer->data) % 4U) == 0U); - if ((((uint32_t)transfer->data) % 4U) != 0U) - { - /* Data not 4-bytes aligned */ - return kStatus_InvalidArgument; - } - - if (handle->oneChannel) - { - assert((transfer->dataSize % 4U) == 0U); - if ((transfer->dataSize % 4U) != 0U) - { - /* Data lenght not multiply of 4 */ - return kStatus_InvalidArgument; - } - } - else - { - assert((transfer->dataSize % 8U) == 0U); - if ((transfer->dataSize % 8U) != 0U) - { - /* Data lenght not multiply of 8 */ - return kStatus_InvalidArgument; - } - } - } - - return kStatus_Success; -} - -/*! - * brief Initializes handle for transfer of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) -{ - uint32_t instance; - - assert(handle); - - /* Clear out the handle */ - memset(handle, 0U, sizeof(*handle)); - - /* Look up instance number */ - instance = I2S_GetInstance(base); - - /* Save callback and user data */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Remember some items set previously by configuration */ - handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT); - handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT); - - handle->useFifo48H = false; - - /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_TxHandleIRQ, handle); - - /* enable NVIC IRQ. */ - EnableIRQ(s_i2sIRQ[instance]); -} - -/*! - * brief Begins or queue sending of the given data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) -{ - assert(handle); - if (!handle) - { - return kStatus_InvalidArgument; - } - - status_t result; - - result = I2S_ValidateBuffer(handle, &transfer); - if (result != kStatus_Success) - { - return result; - } - - if (handle->i2sQueue[handle->queueUser].dataSize) - { - /* Previously prepared buffers not processed yet */ - return kStatus_I2S_Busy; - } - - handle->state = kI2S_StateTx; - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_TXLVL_MASK)) | I2S_FIFOTRIG_TXLVL(handle->watermark); - I2S_TxEnable(base, true); - - return kStatus_Success; -} - -/*! - * brief Aborts sending of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle) -{ - assert(handle); - - /* Disable I2S operation and interrupts */ - I2S_TxEnable(base, false); - - /* Reset state */ - handle->state = kI2S_StateIdle; - - /* Clear transfer queue */ - memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); - handle->queueDriver = 0U; - handle->queueUser = 0U; -} - -/*! - * brief Initializes handle for reception of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) -{ - uint32_t instance; - - assert(handle); - - /* Clear out the handle */ - memset(handle, 0U, sizeof(*handle)); - - /* Look up instance number */ - instance = I2S_GetInstance(base); - - /* Save callback and user data */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Remember some items set previously by configuration */ - handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT); - handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT); - - handle->useFifo48H = false; - - /* Register IRQ handling */ - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_RxHandleIRQ, handle); - - /* enable NVIC IRQ. */ - EnableIRQ(s_i2sIRQ[instance]); -} - -/*! - * brief Begins or queue reception of data into given buffer. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. - */ -status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) -{ - assert(handle); - if (!handle) - { - return kStatus_InvalidArgument; - } - - status_t result; - - result = I2S_ValidateBuffer(handle, &transfer); - if (result != kStatus_Success) - { - return result; - } - - if (handle->i2sQueue[handle->queueUser].dataSize) - { - /* Previously prepared buffers not processed yet */ - return kStatus_I2S_Busy; - } - - handle->state = kI2S_StateRx; - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_RXLVL_MASK)) | I2S_FIFOTRIG_RXLVL(handle->watermark); - I2S_RxEnable(base, true); - - return kStatus_Success; -} - -/*! - * brief Aborts receiving of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle) -{ - assert(handle); - - /* Disable I2S operation and interrupts */ - I2S_RxEnable(base, false); - - /* Reset state */ - handle->state = kI2S_StateIdle; - - /* Clear transfer queue */ - memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); - handle->queueDriver = 0U; - handle->queueUser = 0U; -} - -/*! - * brief Returns number of bytes transferred so far. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param[out] count number of bytes transferred so far by the non-blocking transaction. - * - * retval kStatus_Success - * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) -{ - assert(handle); - if (!handle) - { - return kStatus_InvalidArgument; - } - - assert(count); - if (!count) - { - return kStatus_InvalidArgument; - } - - if (handle->state == kI2S_StateIdle) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->transferCount; - - return kStatus_Success; -} - -/*! - * brief Returns number of buffer underruns or overruns. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param[out] count number of transmit errors encountered so far by the non-blocking transaction. - * - * retval kStatus_Success - * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) -{ - assert(handle); - if (!handle) - { - return kStatus_InvalidArgument; - } - - assert(count); - if (!count) - { - return kStatus_InvalidArgument; - } - - if (handle->state == kI2S_StateIdle) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->errorCount; - - return kStatus_Success; -} - -/*! - * brief Invoked from interrupt handler when transmit FIFO level decreases. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) -{ - uint32_t intstat = base->FIFOINTSTAT; - uint32_t data; - - if (intstat & I2S_FIFOINTSTAT_TXERR_MASK) - { - handle->errorCount++; - - /* Clear TX error interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U); - } - - if (intstat & I2S_FIFOINTSTAT_TXLVL_MASK) - { - if (handle->state == kI2S_StateTx) - { - /* Send data */ - - while ((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) && - (handle->i2sQueue[handle->queueDriver].dataSize > 0U)) - { - /* Write output data */ - if (handle->dataLength == 4U) - { - data = *(handle->i2sQueue[handle->queueDriver].data); - base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU); - handle->i2sQueue[handle->queueDriver].data++; - handle->transferCount++; - handle->i2sQueue[handle->queueDriver].dataSize--; - } - else if (handle->dataLength <= 8U) - { - data = *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data); - base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); - } - else if (handle->dataLength <= 16U) - { - base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - } - else if (handle->dataLength <= 24U) - { - if (handle->pack48) - { - if (handle->useFifo48H) - { - base->FIFOWR48H = *((volatile uint16_t *)(handle->i2sQueue[handle->queueDriver].data)); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); - handle->useFifo48H = false; - } - else - { - base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - handle->useFifo48H = true; - } - } - else - { - data = (uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++)); - data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 8U; - data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 16U; - if (handle->useFifo48H) - { - base->FIFOWR48H = data; - handle->useFifo48H = false; - } - else - { - base->FIFOWR = data; - handle->useFifo48H = true; - } - handle->transferCount += 3U; - handle->i2sQueue[handle->queueDriver].dataSize -= 3U; - } - } - else /* if (handle->dataLength <= 32U) */ - { - base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - } - - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* Actual data buffer sent out, switch to a next one */ - handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS; - - /* Notify user */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); - } - - /* Check if the next buffer contains anything to send */ - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* Everything has been written to FIFO */ - handle->state = kI2S_StateTxWaitToWriteDummyData; - break; - } - } - } - } - else if (handle->state == kI2S_StateTxWaitToWriteDummyData) - { - /* Write dummy data */ - if ((handle->dataLength > 16U) && (handle->dataLength < 25U)) - { - if (handle->useFifo48H) - { - base->FIFOWR48H = 0U; - handle->useFifo48H = false; - } - else - { - base->FIFOWR = 0U; - base->FIFOWR48H = 0U; - } - } - else - { - base->FIFOWR = 0U; - } - - /* Next time invoke this handler when FIFO becomes empty (TX level 0) */ - base->FIFOTRIG &= ~I2S_FIFOTRIG_TXLVL_MASK; - handle->state = kI2S_StateTxWaitForEmptyFifo; - } - else if (handle->state == kI2S_StateTxWaitForEmptyFifo) - { - /* FIFO, including additional dummy data, has been emptied now, - * all relevant data should have been output from peripheral */ - - /* Stop transfer */ - I2S_Disable(base); - I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - - /* Reset state */ - handle->state = kI2S_StateIdle; - - /* Notify user */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); - } - } - else - { - /* Do nothing */ - } - - /* Clear TX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_TXLVL(1U); - } -} - -/*! - * brief Invoked from interrupt handler when receive FIFO level decreases. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) -{ - uint32_t intstat = base->FIFOINTSTAT; - uint32_t data; - - if (intstat & I2S_FIFOINTSTAT_RXERR_MASK) - { - handle->errorCount++; - - /* Clear RX error interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U); - } - - if (intstat & I2S_FIFOINTSTAT_RXLVL_MASK) - { - while ((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) && (handle->i2sQueue[handle->queueDriver].dataSize > 0U)) - { - /* Read input data */ - if (handle->dataLength == 4U) - { - data = base->FIFORD; - *(handle->i2sQueue[handle->queueDriver].data) = ((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU); - handle->i2sQueue[handle->queueDriver].data++; - handle->transferCount++; - handle->i2sQueue[handle->queueDriver].dataSize--; - } - else if (handle->dataLength <= 8U) - { - data = base->FIFORD; - *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data) = - ((data >> 8U) & 0xFF00U) | (data & 0xFFU); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); - } - else if (handle->dataLength <= 16U) - { - data = base->FIFORD; - *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - } - else if (handle->dataLength <= 24U) - { - if (handle->pack48) - { - if (handle->useFifo48H) - { - data = base->FIFORD48H; - handle->useFifo48H = false; - - *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data) = data; - handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); - } - else - { - data = base->FIFORD; - handle->useFifo48H = true; - - *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - } - } - else - { - if (handle->useFifo48H) - { - data = base->FIFORD48H; - handle->useFifo48H = false; - } - else - { - data = base->FIFORD; - handle->useFifo48H = true; - } - - *(handle->i2sQueue[handle->queueDriver].data++) = data & 0xFFU; - *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 8U) & 0xFFU; - *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 16U) & 0xFFU; - handle->transferCount += 3U; - handle->i2sQueue[handle->queueDriver].dataSize -= 3U; - } - } - else /* if (handle->dataLength <= 32U) */ - { - data = base->FIFORD; - *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); - } - - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* Actual data buffer filled with input data, switch to a next one */ - handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS; - - /* Notify user */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); - } - - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) - { - /* No other buffer prepared to receive data into */ - - /* Disable I2S operation and interrupts */ - I2S_Disable(base); - I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - - /* Reset state */ - handle->state = kI2S_StateIdle; - - /* Notify user */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); - } - - /* Clear RX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); - - return; - } - } - } - - /* Clear RX level interrupt flag */ - base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); - } -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2s.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2s.h deleted file mode 100644 index 952f021f2b..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2s.h +++ /dev/null @@ -1,468 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2S_H_ -#define _FSL_I2S_H_ - -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup i2s_driver - * @{ - */ - -/*! @file */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2S driver version 2.0.2. - * - * Current version: 2.0.2 - * - * Change log: - * - Version 2.0.2 - * - Add ENABLE_IRQ handle after register i2s interrupt handle - * - Version 2.0.1 - * - Unify component full name to FLEXCOMM I2S(DMA) Driver - * - Version 2.0.0 - * - initial version - */ -#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -#ifndef I2S_NUM_BUFFERS - -/*! @brief Number of buffers . */ -#define I2S_NUM_BUFFERS (4) - -#endif - -/*! @brief I2S status codes. */ -enum _i2s_status -{ - kStatus_I2S_BufferComplete = - MAKE_STATUS(kStatusGroup_I2S, 0), /*!< Transfer from/into a single buffer has completed */ - kStatus_I2S_Done = MAKE_STATUS(kStatusGroup_I2S, 1), /*!< All buffers transfers have completed */ - kStatus_I2S_Busy = - MAKE_STATUS(kStatusGroup_I2S, 2), /*!< Already performing a transfer and cannot queue another buffer */ -}; - -/*! - * @brief I2S flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -typedef enum _i2s_flags -{ - kI2S_TxErrorFlag = I2S_FIFOINTENSET_TXERR_MASK, /*!< TX error interrupt */ - kI2S_TxLevelFlag = I2S_FIFOINTENSET_TXLVL_MASK, /*!< TX level interrupt */ - kI2S_RxErrorFlag = I2S_FIFOINTENSET_RXERR_MASK, /*!< RX error interrupt */ - kI2S_RxLevelFlag = I2S_FIFOINTENSET_RXLVL_MASK /*!< RX level interrupt */ -} i2s_flags_t; - -/*! @brief Master / slave mode. */ -typedef enum _i2s_master_slave -{ - kI2S_MasterSlaveNormalSlave = 0x0, /*!< Normal slave */ - kI2S_MasterSlaveWsSyncMaster = 0x1, /*!< WS synchronized master */ - kI2S_MasterSlaveExtSckMaster = 0x2, /*!< Master using existing SCK */ - kI2S_MasterSlaveNormalMaster = 0x3 /*!< Normal master */ -} i2s_master_slave_t; - -/*! @brief I2S mode. */ -typedef enum _i2s_mode -{ - kI2S_ModeI2sClassic = 0x0, /*!< I2S classic mode */ - kI2S_ModeDspWs50 = 0x1, /*!< DSP mode, WS having 50% duty cycle */ - kI2S_ModeDspWsShort = 0x2, /*!< DSP mode, WS having one clock long pulse */ - kI2S_ModeDspWsLong = 0x3 /*!< DSP mode, WS having one data slot long pulse */ -} i2s_mode_t; - -/*! @brief I2S configuration structure. */ -typedef struct _i2s_config -{ - i2s_master_slave_t masterSlave; /*!< Master / slave configuration */ - i2s_mode_t mode; /*!< I2S mode */ - bool rightLow; /*!< Right channel data in low portion of FIFO */ - bool leftJust; /*!< Left justify data in FIFO */ -#if defined(I2S_CFG1_PDMDATA) - bool pdmData; /*!< Data source is the D-Mic subsystem */ -#endif - bool sckPol; /*!< SCK polarity */ - bool wsPol; /*!< WS polarity */ - uint16_t divider; /*!< Flexcomm function clock divider (1 - 4096) */ - bool oneChannel; /*!< true mono, false stereo */ - uint8_t dataLength; /*!< Data length (4 - 32) */ - uint16_t frameLength; /*!< Frame width (4 - 512) */ - uint16_t position; /*!< Data position in the frame */ - uint8_t watermark; /*!< FIFO trigger level */ - bool txEmptyZero; /*!< Transmit zero when buffer becomes empty or last item */ - bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit - values) */ -} i2s_config_t; - -/*! @brief Buffer to transfer from or receive audio data into. */ -typedef struct _i2s_transfer -{ - volatile uint8_t *data; /*!< Pointer to data buffer. */ - volatile size_t dataSize; /*!< Buffer size in bytes. */ -} i2s_transfer_t; - -/*! @brief Transactional state of the intialized transfer or receive I2S operation. */ -typedef struct _i2s_handle i2s_handle_t; - -/*! - * @brief Callback function invoked from transactional API - * on completion of a single buffer transfer. - * - * @param base I2S base pointer. - * @param handle pointer to I2S transaction. - * @param completionStatus status of the transaction. - * @param userData optional pointer to user arguments data. - */ -typedef void (*i2s_transfer_callback_t)(I2S_Type *base, - i2s_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! @brief Members not to be accessed / modified outside of the driver. */ -struct _i2s_handle -{ - uint32_t state; /*!< State of transfer */ - i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */ - void *userData; /*!< Application data passed to callback */ - bool oneChannel; /*!< true mono, false stereo */ - uint8_t dataLength; /*!< Data length (4 - 32) */ - bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit - values) */ - bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */ - volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ - volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ - volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ - volatile uint32_t errorCount; /*!< Number of buffer underruns/overruns */ - volatile uint32_t transferCount; /*!< Number of bytes transferred */ - volatile uint8_t watermark; /*!< FIFO trigger level */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S transmission using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_TxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the I2S driver. - * - * @param base I2S base pointer. - * @param config pointer to I2S configuration structure. - */ -void I2S_TxInit(I2S_Type *base, const i2s_config_t *config); - -/*! - * @brief Initializes the FLEXCOMM peripheral for I2S receive functionality. - * - * Ungates the FLEXCOMM clock and configures the module - * for I2S receive using a configuration structure. - * The configuration structure can be custom filled or set with default values by - * I2S_RxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the I2S driver. - * - * @param base I2S base pointer. - * @param config pointer to I2S configuration structure. - */ -void I2S_RxInit(I2S_Type *base, const i2s_config_t *config); - -/*! - * @brief Sets the I2S Tx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_TxInit(). - * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified - * before calling I2S_TxInit(). - * Example: - @code - i2s_config_t config; - I2S_TxGetDefaultConfig(&config); - @endcode - * - * Default values: - * @code - * config->masterSlave = kI2S_MasterSlaveNormalMaster; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = true; - * config->pack48 = false; - * @endcode - * - * @param config pointer to I2S configuration structure. - */ -void I2S_TxGetDefaultConfig(i2s_config_t *config); - -/*! - * @brief Sets the I2S Rx configuration structure to default values. - * - * This API initializes the configuration structure for use in I2S_RxInit(). - * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified - * before calling I2S_RxInit(). - * Example: - @code - i2s_config_t config; - I2S_RxGetDefaultConfig(&config); - @endcode - * - * Default values: - * @code - * config->masterSlave = kI2S_MasterSlaveNormalSlave; - * config->mode = kI2S_ModeI2sClassic; - * config->rightLow = false; - * config->leftJust = false; - * config->pdmData = false; - * config->sckPol = false; - * config->wsPol = false; - * config->divider = 1; - * config->oneChannel = false; - * config->dataLength = 16; - * config->frameLength = 32; - * config->position = 0; - * config->watermark = 4; - * config->txEmptyZero = false; - * config->pack48 = false; - * @endcode - * - * @param config pointer to I2S configuration structure. - */ -void I2S_RxGetDefaultConfig(i2s_config_t *config); - -/*! - * @brief De-initializes the I2S peripheral. - * - * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit - * or I2S_RxInit is called to enable the clock. - * - * @param base I2S base pointer. - */ -void I2S_Deinit(I2S_Type *base); - -/*! @} */ - -/*! - * @name Non-blocking API - * @{ - */ - -/*! - * @brief Initializes handle for transfer of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); - -/*! - * @brief Begins or queue sending of the given data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts sending of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Initializes handle for reception of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); - -/*! - * @brief Begins or queue reception of data into given buffer. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. - */ -status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts receiving of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Returns number of bytes transferred so far. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param[out] count number of bytes transferred so far by the non-blocking transaction. - * - * @retval kStatus_Success - * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); - -/*! - * @brief Returns number of buffer underruns or overruns. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param[out] count number of transmit errors encountered so far by the non-blocking transaction. - * - * @retval kStatus_Success - * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. - */ -status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); - -/*! @} */ - -/*! - * @name Enable / disable - * @{ - */ - -/*! - * @brief Enables I2S operation. - * - * @param base I2S base pointer. - */ -static inline void I2S_Enable(I2S_Type *base) -{ - base->CFG1 |= I2S_CFG1_MAINENABLE(1U); -} - -/*! - * @brief Disables I2S operation. - * - * @param base I2S base pointer. - */ -static inline void I2S_Disable(I2S_Type *base) -{ - base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U)); -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables I2S FIFO interrupts. - * - * @param base I2S base pointer. - * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2S_EnableInterrupts(I2S_Type *base, uint32_t interruptMask) -{ - base->FIFOINTENSET = interruptMask; -} - -/*! - * @brief Disables I2S FIFO interrupts. - * - * @param base I2S base pointer. - * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void I2S_DisableInterrupts(I2S_Type *base, uint32_t interruptMask) -{ - base->FIFOINTENCLR = interruptMask; -} - -/*! - * @brief Returns the set of currently enabled I2S FIFO interrupts. - * - * @param base I2S base pointer. - * - * @return A bitmask composed of #i2s_flags_t enumerators OR'd together - * to indicate the set of enabled interrupts. - */ -static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base) -{ - return base->FIFOINTENSET; -} - -/*! - * @brief Invoked from interrupt handler when transmit FIFO level decreases. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); - -/*! - * @brief Invoked from interrupt handler when receive FIFO level decreases. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); - -/*! @} */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2S_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2s_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2s_dma.c deleted file mode 100644 index 3e137db39f..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2s_dma.c +++ /dev/null @@ -1,665 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dma.h" -#include "fsl_i2s_dma.h" -#include "fsl_flexcomm.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s_dma" -#endif - -#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t)) -#define DMA_DESCRIPTORS (2U) - -/*i2sQueue[handle->queueUser].dataSize) - { - /* Previously prepared buffers not processed yet, reject request */ - return kStatus_I2S_Busy; - } - - /* Enqueue data */ - privateHandle->descriptorQueue[handle->queueUser].data = transfer.data; - privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->i2sQueue[handle->queueUser].data = transfer.data; - handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; - handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; - - return kStatus_Success; -} - -static uint32_t I2S_GetInstance(I2S_Type *base) -{ - uint32_t i; - - for (i = 0U; i < ARRAY_SIZE(s_I2sBaseAddrs); i++) - { - if ((uint32_t)base == s_I2sBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0U; -} - -static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle) -{ - DMA_DisableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); -} - -static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle) -{ - if (handle->state != kI2S_DmaStateIdle) - { - DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); - } -} - -/*! - * brief Initializes handle for transfer of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param dmaHandle pointer to dma handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData) -{ - assert(handle); - assert(dmaHandle); - - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - - memset(handle, 0U, sizeof(*handle)); - handle->state = kI2S_DmaStateIdle; - handle->dmaHandle = dmaHandle; - handle->completionCallback = callback; - handle->userData = userData; - - memset(privateHandle, 0U, sizeof(*privateHandle)); - privateHandle->base = base; - privateHandle->handle = handle; - - DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle); -} - -/*! - * brief Begins or queue sending of the given data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) -{ - status_t status; - - I2S_DisableDMAInterrupts(handle); - - /* Enqueue transfer buffer */ - status = I2S_EnqueueUserBuffer(base, handle, transfer); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - - /* Initialize DMA transfer */ - if (handle->state == kI2S_DmaStateIdle) - { - handle->state = kI2S_DmaStateTx; - status = I2S_StartTransferDMA(base, handle); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - } - - I2S_AddTransferDMA(base, handle); - I2S_EnableDMAInterrupts(handle); - - return kStatus_Success; -} - -/*! - * brief Aborts transfer of data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - */ -void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - assert(handle); - assert(handle->dmaHandle); - - uint32_t instance = I2S_GetInstance(base); - i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - - I2S_DisableDMAInterrupts(handle); - - /* Abort operation */ - DMA_AbortTransfer(handle->dmaHandle); - - if (handle->state == kI2S_DmaStateTx) - { - /* Wait until all transmitted data get out of FIFO */ - while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) - { - } - /* The last piece of valid data can be still being transmitted from I2S at this moment */ - - /* Write additional data to FIFO */ - base->FIFOWR = 0U; - while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) - { - } - /* At this moment the additional data are out of FIFO, starting being transmitted. - * This means the preceding valid data has been just transmitted and we can stop I2S. */ - I2S_TxEnableDMA(base, false); - } - else - { - I2S_RxEnableDMA(base, false); - } - - I2S_Disable(base); - - /* Reset state */ - handle->state = kI2S_DmaStateIdle; - - /* Clear transfer queue */ - memset((void *)&(handle->i2sQueue), 0U, sizeof(handle->i2sQueue)); - handle->queueDriver = 0U; - handle->queueUser = 0U; - - /* Clear internal state */ - memset((void *)&(privateHandle->descriptorQueue), 0U, sizeof(privateHandle->descriptorQueue)); - memset((void *)&(privateHandle->enqueuedBytes), 0U, sizeof(privateHandle->enqueuedBytes)); - privateHandle->enqueuedBytesStart = 0U; - privateHandle->enqueuedBytesEnd = 0U; - privateHandle->dmaDescriptorsUsed = 0U; - privateHandle->descriptor = 0U; - privateHandle->queueDescriptor = 0U; - privateHandle->intA = false; -} - -/*! - * brief Initializes handle for reception of audio data. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param dmaHandle pointer to dma handle structure. - * param callback function to be called back when transfer is done or fails. - * param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData) -{ - I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData); -} - -/*! - * brief Begins or queue reception of data into given buffer. - * - * param base I2S base pointer. - * param handle pointer to handle structure. - * param transfer data buffer. - * - * retval kStatus_Success - * retval kStatus_I2S_Busy if all queue slots are occupied with buffers - * which are not full. - */ -status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) -{ - status_t status; - - I2S_DisableDMAInterrupts(handle); - - /* Enqueue transfer buffer */ - status = I2S_EnqueueUserBuffer(base, handle, transfer); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - - /* Initialize DMA transfer */ - if (handle->state == kI2S_DmaStateIdle) - { - handle->state = kI2S_DmaStateRx; - status = I2S_StartTransferDMA(base, handle); - if (status != kStatus_Success) - { - I2S_EnableDMAInterrupts(handle); - return status; - } - } - - I2S_AddTransferDMA(base, handle); - I2S_EnableDMAInterrupts(handle); - - return kStatus_Success; -} - -static void I2S_TxEnableDMA(I2S_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; - } -} - -static void I2S_RxEnableDMA(I2S_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK); - base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; - } -} - -static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer) -{ - assert(transfer); - - uint16_t transferBytes; - - if (transfer->dataSize >= (2 * DMA_MAX_TRANSFER_BYTES)) - { - transferBytes = DMA_MAX_TRANSFER_BYTES; - } - else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES) - { - transferBytes = transfer->dataSize / 2U; - if ((transferBytes % 4U) != 0U) - { - transferBytes -= (transferBytes % 4U); - } - } - else - { - transferBytes = transfer->dataSize; - } - - return transferBytes; -} - -static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - status_t status; - dma_transfer_config_t xferConfig = {0}; - i2s_dma_private_handle_t *privateHandle; - volatile i2s_transfer_t *transfer; - uint16_t transferBytes; - uint32_t instance; - int i; - dma_descriptor_t *descriptor; - dma_descriptor_t *nextDescriptor; - dma_xfercfg_t xfercfg; - - instance = I2S_GetInstance(base); - privateHandle = &(s_DmaPrivateHandle[instance]); - transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); - - transferBytes = I2S_GetTransferBytes(transfer); - - /* Prepare transfer of data via initial DMA transfer descriptor */ - DMA_PrepareTransfer( - &xferConfig, - (void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)transfer->data : (uint32_t)(&(base->FIFORD))), - (void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)(&(base->FIFOWR)) : (uint32_t)transfer->data), - sizeof(uint32_t), transferBytes, - (handle->state == kI2S_DmaStateTx) ? kDMA_MemoryToPeripheral : kDMA_PeripheralToMemory, - (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U])); - - /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */ - privateHandle->dmaDescriptorsUsed = 1U; - privateHandle->intA = false; - - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; - privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; - - transfer->dataSize -= transferBytes; - transfer->data += transferBytes; - - if (transfer->dataSize == 0U) - { - transfer->data = NULL; - privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; - } - - /* Link the DMA descriptors for the case when no additional transfer is queued before the initial one finishes */ - for (i = 0; i < DMA_DESCRIPTORS; i++) - { - descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]); - nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1) % DMA_DESCRIPTORS)]); - - xfercfg.valid = true; - xfercfg.reload = true; - xfercfg.swtrig = false; - xfercfg.clrtrig = false; - xfercfg.intA = false; - xfercfg.intB = false; - xfercfg.byteWidth = sizeof(uint32_t); - xfercfg.srcInc = 0U; - xfercfg.dstInc = 0U; - xfercfg.transferCount = 8U; - - DMA_CreateDescriptor( - descriptor, &xfercfg, - ((handle->state == kI2S_DmaStateTx) ? (void *)&s_DummyBufferTx : (void *)(uint32_t)(&(base->FIFORD))), - ((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t)(&(base->FIFOWR)) : (void *)&s_DummyBufferRx), - (void *)nextDescriptor); - } - - /* Submit and start initial DMA transfer */ - - if (handle->state == kI2S_DmaStateTx) - { - I2S_TxEnableDMA(base, true); - } - else - { - I2S_RxEnableDMA(base, true); - } - - status = DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); - if (status != kStatus_Success) - { - return status; - } - - DMA_StartTransfer(handle->dmaHandle); - - I2S_Enable(base); - return kStatus_Success; -} - -static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) -{ - dma_xfercfg_t xfercfg; - volatile i2s_transfer_t *transfer; - uint16_t transferBytes; - uint32_t instance; - i2s_dma_private_handle_t *privateHandle; - dma_descriptor_t *descriptor; - dma_descriptor_t *nextDescriptor; - uint32_t srcAddr = 0, destAddr = 0; - - instance = I2S_GetInstance(base); - privateHandle = &(s_DmaPrivateHandle[instance]); - - while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS) - { - transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); - - if (transfer->dataSize == 0U) - { - /* Nothing to be added */ - return; - } - - /* Determine currently configured descriptor and the other which it will link to */ - descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); - privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS; - nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); - - transferBytes = I2S_GetTransferBytes(transfer); - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; - privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; - - /* Configure descriptor */ - - xfercfg.valid = true; - xfercfg.reload = true; - xfercfg.swtrig = false; - xfercfg.clrtrig = false; - xfercfg.intA = privateHandle->intA; - xfercfg.intB = !privateHandle->intA; - xfercfg.byteWidth = sizeof(uint32_t); - xfercfg.srcInc = (handle->state == kI2S_DmaStateTx) ? 1U : 0U; - xfercfg.dstInc = (handle->state == kI2S_DmaStateTx) ? 0U : 1U; - xfercfg.transferCount = transferBytes / sizeof(uint32_t); - srcAddr = ((handle->state == kI2S_DmaStateTx) ? (uint32_t)transfer->data : (uint32_t) & (base->FIFORD)); - destAddr = ((handle->state == kI2S_DmaStateTx) ? (uint32_t) & (base->FIFOWR) : (uint32_t)transfer->data); - - DMA_CreateDescriptor(descriptor, &xfercfg, (void *)srcAddr, (void *)destAddr, (void *)nextDescriptor); - - /* Advance internal state */ - - privateHandle->dmaDescriptorsUsed++; - privateHandle->intA = !privateHandle->intA; - - transfer->dataSize -= transferBytes; - transfer->data += transferBytes; - if (transfer->dataSize == 0U) - { - transfer->data = NULL; - privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; - } - } -} - -/*! - * brief Invoked from DMA interrupt handler. - * - * param handle pointer to DMA handle structure. - * param userData argument for user callback. - * param transferDone if transfer was done. - * param tcds - */ -void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) -{ - i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData; - i2s_dma_handle_t *i2sHandle = privateHandle->handle; - I2S_Type *base = privateHandle->base; - - if ((!transferDone) || (i2sHandle->state == kI2S_DmaStateIdle)) - { - return; - } - - if (privateHandle->dmaDescriptorsUsed > 0U) - { - /* Finished descriptor, decrease amount of data to be processed */ - - i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize -= - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; - i2sHandle->i2sQueue[i2sHandle->queueDriver].data += - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U; - privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS; - - privateHandle->dmaDescriptorsUsed--; - - if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) - { - /* Entire user buffer sent or received - advance to next one */ - i2sHandle->i2sQueue[i2sHandle->queueDriver].data = NULL; - i2sHandle->queueDriver = (i2sHandle->queueDriver + 1U) % I2S_NUM_BUFFERS; - - /* Notify user about buffer completion */ - if (i2sHandle->completionCallback) - { - (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData); - } - } - } - - if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) - { - /* All user buffers processed */ - I2S_TransferAbortDMA(base, i2sHandle); - - /* Notify user about completion of the final buffer */ - if (i2sHandle->completionCallback) - { - (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_Done, i2sHandle->userData); - } - } - else - { - /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */ - I2S_AddTransferDMA(base, i2sHandle); - } -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2s_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2s_dma.h deleted file mode 100644 index 064b7f354f..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_i2s_dma.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_I2S_DMA_H_ -#define _FSL_I2S_DMA_H_ - -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -#include "fsl_dma.h" -#include "fsl_i2s.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup i2s_dma_driver - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2S DMA driver version 2.0.1. */ -#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! @brief Members not to be accessed / modified outside of the driver. */ -typedef struct _i2s_dma_handle i2s_dma_handle_t; - -/*! - * @brief Callback function invoked from DMA API on completion. - * - * @param base I2S base pointer. - * @param handle pointer to I2S transaction. - * @param completionStatus status of the transaction. - * @param userData optional pointer to user arguments data. - */ -typedef void (*i2s_dma_transfer_callback_t)(I2S_Type *base, - i2s_dma_handle_t *handle, - status_t completionStatus, - void *userData); - -struct _i2s_dma_handle -{ - uint32_t state; /*!< Internal state of I2S DMA transfer */ - i2s_dma_transfer_callback_t completionCallback; /*!< Callback function pointer */ - void *userData; /*!< Application data passed to callback */ - dma_handle_t *dmaHandle; /*!< DMA handle */ - volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ - volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ - volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! @} */ - -/*! - * @name DMA API - * @{ - */ - -/*! - * @brief Initializes handle for transfer of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param dmaHandle pointer to dma handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_TxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Begins or queue sending of the given data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. - */ -status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Aborts transfer of data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - */ -void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle); - -/*! - * @brief Initializes handle for reception of audio data. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param dmaHandle pointer to dma handle structure. - * @param callback function to be called back when transfer is done or fails. - * @param userData pointer to data passed to callback. - */ -void I2S_RxTransferCreateHandleDMA(I2S_Type *base, - i2s_dma_handle_t *handle, - dma_handle_t *dmaHandle, - i2s_dma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Begins or queue reception of data into given buffer. - * - * @param base I2S base pointer. - * @param handle pointer to handle structure. - * @param transfer data buffer. - * - * @retval kStatus_Success - * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers - * which are not full. - */ -status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); - -/*! - * @brief Invoked from DMA interrupt handler. - * - * @param handle pointer to DMA handle structure. - * @param userData argument for user callback. - * @param transferDone if transfer was done. - * @param tcds - */ -void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds); - -/*! @} */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_I2S_DMA_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_iap.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_iap.c deleted file mode 100644 index 4859aaa48a..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_iap.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "fsl_iap.h" -#include "fsl_iap_ffr.h" -#include "fsl_device_registers.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.iap1" -#endif - -/*! - * @addtogroup flash_driver_api - * @{ -*/ - -#define ROM_API_TREE ((uint32_t *)0x130010f0) -#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)ROM_API_TREE) - -static uint32_t S_Version_minor = 0; - -typedef status_t (*EraseCommend_t)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); -typedef status_t (*ProgramCommend_t)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); -typedef status_t (*VerifyProgramCommend_t)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); -typedef status_t (*FFR_CustomerPagesInit_t)(flash_config_t *config); -typedef status_t (*FFR_InfieldPageWrite_t)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); -typedef status_t (*FFR_GetManufactureData_t)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); -typedef status_t (*FFR_GetRompatchData_t)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - -/* -*!@brief Structure of version property. -* -*!@ingroup bl_core -*/ -typedef union BootloaderVersion -{ - struct - { - uint32_t bugfix : 8; /*!< bugfix version [7:0] */ - uint32_t minor : 8; /*!< minor version [15:8] */ - uint32_t major : 8; /*!< major version [23:16] */ - uint32_t name : 8; /*!< name [31:24] */ - } B; - uint32_t version; /*!< combined version numbers. */ -} standard_version_t; - -/*! @brief Interface for the flash driver.*/ -typedef struct FlashDriverInterface -{ - standard_version_t version; /*!< flash driver API version number.*/ - - /*!< Flash driver.*/ - status_t (*flash_init)(flash_config_t *config); - status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); - status_t (*flash_verify_program)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - /*!< Flash FFR driver*/ - status_t (*ffr_init)(flash_config_t *config); - status_t (*ffr_deinit)(flash_config_t *config); - status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); - status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); - status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); - status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); - status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); - status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); - status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); -} flash_driver_interface_t; - -/*! -* @brief Root of the bootloader API tree. -* -* An instance of this struct resides in read-only memory in the bootloader. It -* provides a user application access to APIs exported by the bootloader. -* -* @note The order of existing fields must not be changed. -*/ -typedef struct BootloaderTree -{ - void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing. */ - standard_version_t bootloader_version; /*!< Bootloader version number. */ - const char *copyright; /*!< Copyright string. */ - const uint32_t *reserved; /*!< Do NOT use. */ - const flash_driver_interface_t *flashDriver; /*!< Flash driver API. */ -} bootloader_tree_t; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Global pointer to the flash driver API table in ROM. */ -flash_driver_interface_t *FLASH_API_TREE; -/*! Get pointer to flash driver API table in ROM. */ -#define FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! See fsl_flash.h for documentation of this function. */ -status_t FLASH_Init(flash_config_t *config) -{ - assert(FLASH_API_TREE); - config->modeConfig.sysFreqInMHz = kSysToFlashFreq_defaultInMHz; - S_Version_minor = FLASH_API_TREE->version.B.minor; - return FLASH_API_TREE->flash_init(config); -} - -/*! See fsl_flash.h for documentation of this function. */ -status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) -{ - if (S_Version_minor == 0) - { - EraseCommend_t EraseCommand = - (EraseCommend_t)(0x1300413b); /*!< get the flash erase api location adress int rom */ - return EraseCommand(config, start, lengthInBytes, key); - } - else - { - assert(FLASH_API_TREE); - return FLASH_API_TREE->flash_erase(config, start, lengthInBytes, key); - } -} - -/*! See fsl_flash.h for documentation of this function. */ -status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) -{ - if (S_Version_minor == 0) - { - ProgramCommend_t ProgramCommend = - (ProgramCommend_t)(0x1300419d); /*!< get the flash program api location adress in rom*/ - return ProgramCommend(config, start, src, lengthInBytes); - } - else - { - assert(FLASH_API_TREE); - return FLASH_API_TREE->flash_program(config, start, src, lengthInBytes); - } -} - -/*! See fsl_flash.h for documentation of this function. */ -status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) -{ - assert(FLASH_API_TREE); - return FLASH_API_TREE->flash_verify_erase(config, start, lengthInBytes); -} - -/*! See fsl_flash.h for documentation of this function. */ -status_t FLASH_VerifyProgram(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData) -{ - if (S_Version_minor == 0) - { - VerifyProgramCommend_t VerifyProgramCommend = - (VerifyProgramCommend_t)(0x1300427d); /*!< get the flash verify program api location adress in rom*/ - return VerifyProgramCommend(config, start, lengthInBytes, expectedData, failedAddress, failedData); - } - else - { - assert(FLASH_API_TREE); - return FLASH_API_TREE->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress, - failedData); - } -} - -/*! See fsl_flash.h for documentation of this function.*/ -status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) -{ - assert(FLASH_API_TREE); - return FLASH_API_TREE->flash_get_property(config, whichProperty, value); -} -/******************************************************************************** - * fsl_flash_ffr CODE - *******************************************************************************/ - -/*! See fsl_flash_ffr.h for documentation of this function. */ -status_t FFR_Init(flash_config_t *config) -{ - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_init(config); -} - -/*! See fsl_flash_ffr.h for documentation of this function. */ -status_t FFR_Deinit(flash_config_t *config) -{ - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_deinit(config); -} - -status_t FFR_CustomerPagesInit(flash_config_t *config) -{ - assert(FLASH_API_TREE); - FFR_CustomerPagesInit_t FFR_CustomerPagesInit_cmd = (FFR_CustomerPagesInit_t)(0x13004951); - return FFR_CustomerPagesInit_cmd(config); -} - -status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len) -{ - FFR_InfieldPageWrite_t FFR_InfieldPageWrite_cmd = (FFR_InfieldPageWrite_t)(0x13004a0b); - return FFR_InfieldPageWrite_cmd(config, page_data, valid_len); -} - -/*! See fsl_flash_ffr.h for documentation of this function. */ -status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part) -{ - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); -} - -/*! See fsl_flash_ffr.h for documentation of this function. */ -status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) -{ - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); -} - -/*! See fsl_flash_ffr.h for documentation of this function. */ -status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore) -{ - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); -} - -/*! See fsl_flash_ffr.h for documentation of this function. */ -status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode) -{ - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); -} - -/*! See fsl_flash_ffr.h for documentation of this function. */ -status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex) -{ - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); -} - -status_t FFR_GetRompatchData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) -{ - FFR_GetRompatchData_t FFR_GetRompatchData_cmd = (FFR_GetRompatchData_t)(0x13004db3); - return FFR_GetRompatchData_cmd(config, pData, offset, len); -} - -/* APIs to access NMPA pages */ -status_t FFR_GetManufactureData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) -{ - FFR_GetManufactureData_t FFR_GetManufactureData_cmd = (FFR_GetManufactureData_t)(0x13004e15); - return FFR_GetManufactureData_cmd(config, pData, offset, len); -} - -/*! See fsl_flash_ffr.h for documentation of this function. */ -status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid) -{ - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_get_uuid(config, uuid); -} - -/*! See fsl_flash_ffr.h for documentation of this function. */ -status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) -{ - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); -} -/*! @}*/ - -/******************************************************************************** - * EOF - *******************************************************************************/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_iap.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_iap.h deleted file mode 100644 index dd69adfa0b..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_iap.h +++ /dev/null @@ -1,516 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_IAP_H_ -#define __FSL_IAP_H_ - -#include "fsl_common.h" -/*! - * @addtogroup iap_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! - * @name Flash version - * @{ - */ -/*! @brief Constructs the version number for drivers. */ -#if !defined(MAKE_VERSION) -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) -#endif - -/*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ - -/*! @brief Flash driver version for ROM*/ -enum _flash_driver_version_constants -{ - kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ - kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/ - kFLASH_DriverVersionMinor = 0, /*!< Minor flash driver version.*/ - kFLASH_DriverVersionBugfix = 0 /*!< Bugfix for flash driver version.*/ -}; - -/*@}*/ - -/*! - * @name Flash configuration - * @{ - */ -/*! @brief Flash IP Type. */ -#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC) -#define FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC (1) -#endif -#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_FC) -#define FSL_FEATURE_FLASH_IP_IS_C040HD_FC (0) -#endif - -/*@}*/ - -/*! - * @name Flash status - * @{ - */ -/*! @brief Flash driver status group. */ -#if defined(kStatusGroup_FlashDriver) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FlashDriver -#elif defined(kStatusGroup_FLASHIAP) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FLASH -#else -#define kStatusGroupGeneric 0 -#define kStatusGroupFlashDriver 1 -#endif - -/*! @brief Constructs a status code value from a group and a code number. */ -#if !defined(MAKE_STATUS) -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) -#endif - -/*! - * @brief Flash driver status codes. - */ -enum _flash_status -{ - kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ - kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ - kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ - kStatus_FLASH_AlignmentError = - MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ - kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ - kStatus_FLASH_AccessError = - MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ - kStatus_FLASH_ProtectionViolation = MAKE_STATUS( - kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ - kStatus_FLASH_CommandFailure = - MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ - kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ - kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ - kStatus_FLASH_RegionExecuteOnly = - MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ - kStatus_FLASH_ExecuteInRamFunctionNotReady = - MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ - - kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Flash API is not supported.*/ - kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< The flash property is read-only.*/ - kStatus_FLASH_InvalidPropertyValue = - MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< The flash property value is out of range.*/ - kStatus_FLASH_InvalidSpeculationOption = - MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< The option of flash prefetch speculation is invalid.*/ - kStatus_FLASH_EccError = MAKE_STATUS(kStatusGroupFlashDriver, - 0x10), /*!< A correctable or uncorrectable error during command execution. */ - kStatus_FLASH_CompareError = - MAKE_STATUS(kStatusGroupFlashDriver, 0x11), /*!< Destination and source memory contents do not match. */ - kStatus_FLASH_RegulationLoss = MAKE_STATUS(kStatusGroupFlashDriver, 0x12), /*!< A loss of regulation during read. */ - kStatus_FLASH_InvalidWaitStateCycles = - MAKE_STATUS(kStatusGroupFlashDriver, 0x13), /*!< The wait state cycle set to r/w mode is invalid. */ - - kStatus_FLASH_OutOfDateCfpaPage = - MAKE_STATUS(kStatusGroupFlashDriver, 0x20), /*!< CFPA page version is out of date. */ - kStatus_FLASH_BlankIfrPageData = MAKE_STATUS(kStatusGroupFlashDriver, 0x21), /*!< Blank page cannnot be read. */ - kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce = - MAKE_STATUS(kStatusGroupFlashDriver, 0x22), /*!< Encrypted flash subregions are not erased at once. */ - kStatus_FLASH_ProgramVerificationNotAllowed = MAKE_STATUS( - kStatusGroupFlashDriver, 0x23), /*!< Program verification is not allowed when the encryption is enabled. */ - kStatus_FLASH_HashCheckError = - MAKE_STATUS(kStatusGroupFlashDriver, 0x24), /*!< Hash check of page data is failed. */ - kStatus_FLASH_SealedFfrRegion = MAKE_STATUS(kStatusGroupFlashDriver, 0x25), /*!< The FFR region is sealed. */ - kStatus_FLASH_FfrRegionWriteBroken = MAKE_STATUS( - kStatusGroupFlashDriver, 0x26), /*!< The FFR Spec region is not allowed to be written discontinuously. */ - kStatus_FLASH_NmpaAccessNotAllowed = - MAKE_STATUS(kStatusGroupFlashDriver, 0x27), /*!< The NMPA region is not allowed to be read/written/erased. */ - kStatus_FLASH_CmpaCfgDirectEraseNotAllowed = - MAKE_STATUS(kStatusGroupFlashDriver, 0x28), /*!< The CMPA Cfg region is not allowed to be erased directly. */ - kStatus_FLASH_FfrBankIsLocked = MAKE_STATUS(kStatusGroupFlashDriver, 0x29), /*!< The FFR bank region is locked. */ -}; -/*@}*/ - -/*! - * @name Flash API key - * @{ - */ -/*! @brief Constructs the four character code for the Flash driver API key. */ -#if !defined(FOUR_CHAR_CODE) -#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) -#endif - -/*! - * @brief Enumeration for Flash driver API keys. - * - * @note The resulting value is built with a byte order such that the string - * being readable in expected order when viewed in a hex editor, if the value - * is treated as a 32-bit little endian value. - */ -enum _flash_driver_api_keys -{ - kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ -}; -/*@}*/ - -/*! - * @brief Enumeration for various flash properties. - */ -typedef enum _flash_property_tag -{ - kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ - kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ - kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ - kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ - kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ - - kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/ - kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency System Frequency.*/ - - kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/ - kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/ - kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/ - kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/ -} flash_property_tag_t; - -/*! - * @brief Enumeration for flash max pages to erase. - */ -enum _flash_max_erase_page_value -{ - kFLASH_MaxPagesToErase = 100U /*!< The max value in pages to erase. */ -}; - -enum _flash_freq_tag -{ - kSysToFlashFreq_lowInMHz = 12u, - kSysToFlashFreq_defaultInMHz = 96u, - kSysToFlashFreq_100MHz = 100u -}; - -/*! - * @brief Enumeration for flash alignment property. - */ -enum _flash_alignment_property -{ - kFLASH_AlignementUnitVerifyErase = 4, /*!< The alignment unit in bytes used for verify erase operation.*/ - kFLASH_AlignementUnitProgram = 512, /*!< The alignment unit in bytes used for program operation.*/ - /*kFLASH_AlignementUnitVerifyProgram = 4,*/ /*!< The alignment unit in bytes used for verify program operation.*/ - kFLASH_AlignementUnitSingleWordRead = 16 /*!< The alignment unit in bytes used for SingleWordRead command.*/ -}; - -/*! - * @brief Enumeration for flash read ecc option - */ -enum _flash_read_ecc_option -{ - kFLASH_ReadWithEccOn = 0, /*! ECC is on */ - kFLASH_ReadWithEccOff = 1, /*! ECC is off */ -}; - -/*! - * @brief Enumeration for flash read margin option - */ -enum _flash_read_margin_option -{ - kFLASH_ReadMarginNormal = 0, /*!< Normal read */ - kFLASH_ReadMarginVsProgram = 1, /*!< Margin vs. program */ - kFLASH_ReadMarginVsErase = 2, /*!< Margin vs. erase */ - kFLASH_ReadMarginIllegalBitCombination = 3 /*!< Illegal bit combination */ -}; - -/*! - * @brief Enumeration for flash read dmacc option - */ -enum _flash_read_dmacc_option -{ - kFLASH_ReadDmaccDisabled = 0, /*!< Memory word */ - kFLASH_ReadDmaccEnabled = 1, /*!< DMACC word */ -}; - -/*! - * @brief Enumeration for flash ramp control option - */ -enum _flash_ramp_control_option -{ - kFLASH_RampControlDivisionFactorReserved = 0, /*!< Reserved */ - kFLASH_RampControlDivisionFactor256 = 1, /*!< clk48mhz / 256 = 187.5KHz */ - kFLASH_RampControlDivisionFactor128 = 2, /*!< clk48mhz / 128 = 375KHz */ - kFLASH_RampControlDivisionFactor64 = 3 /*!< clk48mhz / 64 = 750KHz */ -}; - -/*! @brief Flash ECC log info. */ -typedef struct _flash_ecc_log -{ - uint32_t firstEccEventAddress; - uint32_t eccErrorCount; - uint32_t eccCorrectionCount; - uint32_t reserved; -} flash_ecc_log_t; - -/*! @brief Flash controller paramter config. */ -typedef struct _flash_mode_config -{ - uint32_t sysFreqInMHz; - /* ReadSingleWord parameter. */ - struct - { - uint8_t readWithEccOff : 1; - uint8_t readMarginLevel : 2; - uint8_t readDmaccWord : 1; - uint8_t reserved0 : 4; - uint8_t reserved1[3]; - } readSingleWord; - /* SetWriteMode parameter. */ - struct - { - uint8_t programRampControl; - uint8_t eraseRampControl; - uint8_t reserved[2]; - } setWriteMode; - /* SetReadMode parameter. */ - struct - { - uint16_t readInterfaceTimingTrim; - uint16_t readControllerTimingTrim; - uint8_t readWaitStates; - uint8_t reserved[3]; - } setReadMode; -} flash_mode_config_t; - -/*! @brief Flash controller paramter config. */ -typedef struct _flash_ffr_config -{ - uint32_t ffrBlockBase; - uint32_t ffrTotalSize; - uint32_t ffrPageSize; - uint32_t cfpaPageVersion; - uint32_t cfpaPageOffset; -} flash_ffr_config_t; - -/*! @brief Flash driver state information. - * - * An instance of this structure is allocated by the user of the flash driver and - * passed into each of the driver APIs. - */ -typedef struct _flash_config -{ - uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */ - uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */ - uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */ - uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */ - uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */ - flash_ffr_config_t ffrConfig; - flash_mode_config_t modeConfig; -} flash_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization - * @{ - */ - -/*! - * @brief Initializes the global flash properties structure members. - * - * This function checks and initializes the Flash module for the other Flash APIs. - * - * @param config Pointer to the storage for the driver runtime state. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Init(flash_config_t *config); - -/*@}*/ - -/*! - * @name Erasing - * @{ - */ - -/*! - * @brief Erases the flash sectors encompassed by parameters passed into function. - * - * This function erases the appropriate number of flash sectors based on the - * desired start address and length. - * - * @param config The pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be erased. - * The start address does not need to be sector-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words) - * to be erased. Must be word-aligned. - * @param key The value used to validate all flash erase APIs. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError The address is out of range. - * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - -/*@}*/ - -/*! - * @name Programming - * @{ - */ - -/*! - * @brief Programs flash with data at locations passed in through parameters. - * - * This function programs the flash memory with the desired data for a given - * flash area as determined by the start address and the length. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be programmed. Must be - * word-aligned. - * @param src A pointer to the source buffer of data that is to be programmed - * into the flash. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be programmed. Must be word-aligned. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); - -/*@}*/ - -/*! - * @name Verification - * @{ - */ - -/*! - * @brief Verifies an erasure of the desired flash area at a specified margin level. - * - * This function checks the appropriate number of flash sectors based on - * the desired start address and length to check whether the flash is erased - * to the specified read margin level. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be verified. - * The start address does not need to be sector-aligned but must be word-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be verified. Must be word-aligned. - * @param margin Read margin choice. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); - -/*! - * @brief Verifies programming of the desired flash area at a specified margin level. - * - * This function verifies the data programed in the flash memory using the - * Flash Program Check Command and compares it to the expected data for a given - * flash area as determined by the start address and length. - * - * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be verified. Must be word-aligned. - * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be verified. Must be word-aligned. - * @param expectedData A pointer to the expected data that is to be - * verified against. - * @param margin Read margin choice. - * @param failedAddress A pointer to the returned failing address. - * @param failedData A pointer to the returned failing data. Some derivatives do - * not include failed data as part of the FCCOBx registers. In this - * case, zeros are returned upon failure. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. - * @retval #kStatus_FLASH_AddressError Address is out of range. - * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. - * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. - * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. - */ -status_t FLASH_VerifyProgram(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); - -/*@}*/ - -/*! - * @name Properties - * @{ - */ - -/*! - * @brief Returns the desired flash property. - * - * @param config A pointer to the storage for the driver runtime state. - * @param whichProperty The desired property from the list of properties in - * enum flash_property_tag_t - * @param value A pointer to the value returned for the desired flash property. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_UnknownProperty An unknown property tag. - */ -status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - -/*! - * @brief Sets the desired flash property. - * - * @param config A pointer to the storage for the driver runtime state. - * @param whichProperty The desired property from the list of properties in - * enum flash_property_tag_t - * @param value A to set for the desired flash property. - * - * @retval #kStatus_FLASH_Success API was executed successfully. - * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. - * @retval #kStatus_FLASH_UnknownProperty An unknown property tag. - * @retval #kStatus_FLASH_ReadOnlyProperty An read-only property tag. - */ -status_t FLASH_SetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t value); - -/*@}*/ - -#ifdef __cplusplus -} -#endif -/*@}*/ - -#endif /* __FLASH_FLASH_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_iap_ffr.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_iap_ffr.h deleted file mode 100644 index 405dc05826..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_iap_ffr.h +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_IAP_FFR_H_ -#define __FSL_IAP_FFR_H_ - -#include "fsl_iap.h" - -/*! - * @addtogroup iap_ffr_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! - * @name Flash IFR version - * @{ - */ -/*! @brief Flash IFR driver version for SDK*/ -#define FSL_FLASH_IFR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ -/*@}*/ - -/*! @brief Alignment(down) utility. */ -#if !defined(ALIGN_DOWN) -#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) -#endif - -/*! @brief Alignment(up) utility. */ -#if !defined(ALIGN_UP) -#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) -#endif - -#define FLASH_FFR_MAX_PAGE_SIZE (512u) -#define FLASH_FFR_HASH_DIGEST_SIZE (32u) -#define FLASH_FFR_IV_CODE_SIZE (52u) - -enum _flash_ffr_page_offset -{ - kFfrPageOffset_CFPA = 0, /*!< Customer In-Field programmed area*/ - kFfrPageOffset_CFPA_Scratch = 0, /*!< CFPA Scratch page */ - kFfrPageOffset_CFPA_Cfg = 1, /*!< CFPA Configuration area (Ping page)*/ - kFfrPageOffset_CFPA_CfgPong = 2, /*!< Same as CFPA page (Pong page)*/ - - kFfrPageOffset_CMPA = 3, /*!< Customer Manufacturing programmed area*/ - kFfrPageOffset_CMPA_Cfg = 3, /*!< CMPA Configuration area (Part of CMPA)*/ - kFfrPageOffset_CMPA_Key = 4, /*!< Key Store area (Part of CMPA)*/ - - kFfrPageOffset_NMPA = 7, /*!< NXP Manufacturing programmed area*/ - kFfrPageOffset_NMPA_Romcp = 7, /*!< ROM patch area (Part of NMPA)*/ - kFfrPageOffset_NMPA_Repair = 9, /*!< Repair area (Part of NMPA)*/ - kFfrPageOffset_NMPA_Cfg = 15, /*!< NMPA configuration area (Part of NMPA)*/ - kFfrPageOffset_NMPA_End = 16, /*!< Reserved (Part of NMPA)*/ -}; - -enum _flash_ffr_page_num -{ - kFfrPageNum_CFPA = 3, /*!< Customer In-Field programmed area*/ - kFfrPageNum_CMPA = 4, /*!< Customer Manufacturing programmed area*/ - kFfrPageNum_NMPA = 10, /*!< NXP Manufacturing programmed area*/ - - kFfrPageNum_CMPA_Cfg = 1, - kFfrPageNum_CMPA_Key = 3, - kFfrPageNum_NMPA_Romcp = 2, - - kFfrPageNum_SpecArea = kFfrPageNum_CFPA + kFfrPageNum_CMPA, - kFfrPageNum_Total = (kFfrPageNum_CFPA + kFfrPageNum_CMPA + kFfrPageNum_NMPA), -}; - -enum _flash_ffr_block_size -{ - kFfrBlockSize_Key = 52u, - kFfrBlockSize_ActivationCode = 1192u, -}; - -typedef struct _cfpa_cfg_iv_code -{ - uint32_t keycodeHeader; - uint8_t reserved[FLASH_FFR_IV_CODE_SIZE]; -} cfpa_cfg_iv_code_t; - -typedef struct _cfpa_cfg_info -{ - uint32_t header; /*!< [0x000-0x003] */ - uint32_t version; /*!< [0x004-0x007 */ - uint32_t secureFwVersion; /*!< [0x008-0x00b */ - uint32_t nsFwVersion; /*!< [0x00c-0x00f] */ - uint32_t imageKeyRevoke; /*!< [0x010-0x013] */ - uint8_t reserved0[4]; /*!< [0x014-0x017] */ - uint32_t rotkhRevoke; /*!< [0x018-0x01b] */ - uint32_t vendorUsage; /*!< [0x01c-0x01f] */ - uint32_t dcfgNsPin; /*!< [0x020-0x013] */ - uint32_t dcfgNsDflt; /*!< [0x024-0x017] */ - uint32_t enableFaMode; /*!< [0x028-0x02b] */ - uint8_t reserved1[4]; /*!< [0x02c-0x02f] */ - cfpa_cfg_iv_code_t ivCodePrinceRegion[3]; /*!< [0x030-0x0d7] */ - uint8_t reserved2[264]; /*!< [0x0d8-0x1df] */ - uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ -} cfpa_cfg_info_t; - -#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) -#define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U) -#define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x0U) -#define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x1U) - -#define FFR_USBID_VENDORID_MASK (0xFFFFU) -#define FFR_USBID_VENDORID_SHIFT (0U) -#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) -#define FFR_USBID_PRODUCTID_SHIFT (16U) - -typedef struct _cmpa_cfg_info -{ - uint32_t bootCfg; /*!< [0x000-0x003] */ - uint32_t spiFlashCfg; /*!< [0x004-0x007] */ - struct - { - uint16_t vid; - uint16_t pid; - } usbId; /*!< [0x008-0x00b] */ - uint32_t sdioCfg; /*!< [0x00c-0x00f] */ - uint32_t dcfgPin; /*!< [0x010-0x013] */ - uint32_t dcfgDflt; /*!< [0x014-0x017] */ - uint32_t dapVendorUsage; /*!< [0x018-0x01b] */ - uint32_t secureBootCfg; /*!< [0x01c-0x01f] */ - uint32_t princeBaseAddr; /*!< [0x020-0x023] */ - uint32_t princeSr[3]; /*!< [0x024-0x02f] */ - uint8_t reserved0[32]; /*!< [0x030-0x04f] */ - uint32_t rotkh[8]; /*!< [0x050-0x06f] */ - uint8_t reserved1[368]; /*!< [0x070-0x1df] */ - uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ -} cmpa_cfg_info_t; - -typedef struct _cmpa_key_store_header -{ - uint32_t header; - uint8_t reserved[4]; -} cmpa_key_store_header_t; - -#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) -#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) -#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U) -#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U) - -#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) -#define FFR_PERIPHERALCFG_PERI_SHIFT (0U) -#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) -#define FFR_PERIPHERALCFG_COREEN_SHIFT (31U) - -typedef struct _nmpa_cfg_info -{ - uint16_t fro32kCfg; /*!< [0x000-0x001] */ - uint8_t reserved0[6]; /*!< [0x002-0x007] */ - uint8_t sysCfg; /*!< [0x008-0x008] */ - uint8_t reserved1[7]; /*!< [0x009-0x00f] */ - struct - { - uint32_t data; - uint32_t reserved[3]; - } GpoInitData[3]; /*!< [0x010-0x03f] */ - uint32_t GpoDataChecksum[4]; /*!< [0x040-0x04f] */ - uint32_t finalTestBatchId[4]; /*!< [0x050-0x05f] */ - uint32_t deviceType; /*!< [0x060-0x063] */ - uint32_t finalTestProgVersion; /*!< [0x064-0x067] */ - uint32_t finalTestDate; /*!< [0x068-0x06b] */ - uint32_t finalTestTime; /*!< [0x06c-0x06f] */ - uint32_t uuid[4]; /*!< [0x070-0x07f] */ - uint8_t reserved2[32]; /*!< [0x080-0x09f] */ - uint32_t peripheralCfg; /*!< [0x0a0-0x0a3] */ - uint32_t ramSizeCfg; /*!< [0x0a4-0x0a7] */ - uint32_t flashSizeCfg; /*!< [0x0a8-0x0ab] */ - uint8_t reserved3[36]; /*!< [0x0ac-0x0cf] */ - uint8_t fro1mCfg; /*!< [0x0d0-0x0d0] */ - uint8_t reserved4[15]; /*!< [0x0d1-0x0df] */ - uint32_t dcdc[4]; /*!< [0x0e0-0x0ef] */ - uint32_t bod; /*!< [0x0f0-0x0f3] */ - uint8_t reserved5[12]; /*!< [0x0f4-0x0ff] */ - uint8_t calcHashReserved[192]; /*!< [0x100-0x1bf] */ - uint8_t sha256[32]; /*!< [0x1c0-0x1df] */ - uint32_t ecidBackup[4]; /*!< [0x1e0-0x1ef] */ - uint32_t pageChecksum[4]; /*!< [0x1f0-0x1ff] */ -} nmpa_cfg_info_t; - -typedef struct _ffr_key_store -{ - uint8_t reserved[3][FLASH_FFR_MAX_PAGE_SIZE]; -} ffr_key_store_t; - -typedef enum _ffr_key_type -{ - kFFR_KeyTypeSbkek = 0x00U, - kFFR_KeyTypeUser = 0x01U, - kFFR_KeyTypeUds = 0x02U, - kFFR_KeyTypePrinceRegion0 = 0x03U, - kFFR_KeyTypePrinceRegion1 = 0x04U, - kFFR_KeyTypePrinceRegion2 = 0x05U, -} ffr_key_type_t; - -typedef enum _ffr_bank_type -{ - kFFR_BankTypeBank0_NMPA = 0x00U, - kFFR_BankTypeBank1_CMPA = 0x01U, - kFFR_BankTypeBank2_CFPA = 0x02U -} ffr_bank_type_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! Generic APIs for FFR */ -status_t FFR_Init(flash_config_t *config); -status_t FFR_Deinit(flash_config_t *config); - -/*! APIs to access CFPA pages */ -status_t FFR_CustomerPagesInit(flash_config_t *config); -status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); -/*! Read data stored in 'Customer In-field Page'. */ -status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); - -/*! APIs to access CMPA pages */ -status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part); -/*! Read data stored in 'Customer Factory CFG Page'. */ -status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); -status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); -status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode); -status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); - -/*! APIs to access NMPA pages */ -status_t FFR_NxpAreaCheckIntegrity(flash_config_t *config); -status_t FFR_GetRompatchData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); -/*! Read data stored in 'NXP Manufacuring Programmed CFG Page'. */ -status_t FFR_GetManufactureData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); -status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); - -#ifdef __cplusplus -} -#endif -/*@}*/ - -#endif /*! __FSL_FLASH_FFR_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_inputmux.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_inputmux.c deleted file mode 100644 index ff94a6abae..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_inputmux.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_inputmux.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.inputmux" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initialize INPUTMUX peripheral. - - * This function enables the INPUTMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * - * retval None. - */ -void INPUTMUX_Init(INPUTMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE - CLOCK_EnableClock(kCLOCK_Sct); - CLOCK_EnableClock(kCLOCK_Dma); -#else - CLOCK_EnableClock(kCLOCK_InputMux); -#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Attaches a signal - * - * This function gates the INPUTPMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * param index Destination peripheral to attach the signal to. - * param connection Selects connection. - * - * retval None. -*/ -void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection) -{ - uint32_t pmux_id; - uint32_t output_id; - - /* extract pmux to be used */ - pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT; - /* extract function number */ - output_id = ((uint32_t)(connection)) & 0xffffU; - /* programm signal */ - *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4)) = output_id; -} - -#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) -/*! - * brief Enable/disable a signal - * - * This function gates the INPUTPMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * param signal Enable signal register id and bit offset. - * param enable Selects enable or disable. - * - * retval None. -*/ -void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable) -{ - uint32_t ena_id; - uint32_t bit_offset; - - /* extract enable register to be used */ - ena_id = ((uint32_t)(signal)) >> ENA_SHIFT; - /* extract enable bit offset */ - bit_offset = ((uint32_t)(signal)) & 0xfU; - /* set signal */ - if (enable) - { - *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1U << bit_offset); - } - else - { - *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1U << bit_offset); - } -} -#endif - -/*! - * brief Deinitialize INPUTMUX peripheral. - - * This function disables the INPUTMUX clock. - * - * param base Base address of the INPUTMUX peripheral. - * - * retval None. - */ -void INPUTMUX_Deinit(INPUTMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE - CLOCK_DisableClock(kCLOCK_Sct); - CLOCK_DisableClock(kCLOCK_Dma); -#else - CLOCK_DisableClock(kCLOCK_InputMux); -#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_inputmux.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_inputmux.h deleted file mode 100644 index 4e6412e7ff..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_inputmux.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_INPUTMUX_H_ -#define _FSL_INPUTMUX_H_ - -#include "fsl_inputmux_connections.h" -#include "fsl_common.h" - -/*! - * @addtogroup inputmux_driver - * @{ - */ - -/*! @file */ -/*! @file fsl_inputmux_connections.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Group interrupt driver version for SDK */ -#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ - /*@}*/ - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @brief Initialize INPUTMUX peripheral. - - * This function enables the INPUTMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * - * @retval None. - */ -void INPUTMUX_Init(INPUTMUX_Type *base); - -/*! - * @brief Attaches a signal - * - * This function gates the INPUTPMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * @param index Destination peripheral to attach the signal to. - * @param connection Selects connection. - * - * @retval None. -*/ -void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection); - -#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) -/*! - * @brief Enable/disable a signal - * - * This function gates the INPUTPMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * @param signal Enable signal register id and bit offset. - * @param enable Selects enable or disable. - * - * @retval None. -*/ -void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable); -#endif - -/*! - * @brief Deinitialize INPUTMUX peripheral. - - * This function disables the INPUTMUX clock. - * - * @param base Base address of the INPUTMUX peripheral. - * - * @retval None. - */ -void INPUTMUX_Deinit(INPUTMUX_Type *base); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_INPUTMUX_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_inputmux_connections.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_inputmux_connections.h deleted file mode 100644 index bcdb277355..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_inputmux_connections.h +++ /dev/null @@ -1,410 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_INPUTMUX_CONNECTIONS_ -#define _FSL_INPUTMUX_CONNECTIONS_ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" -#endif - -/*! - * @addtogroup inputmux_driver - * @{ - */ - -/*! - * @name Input multiplexing connections - * @{ - */ - -/*! @brief Periphinmux IDs */ -#define SCT0_INMUX0 0x00U -#define TIMER0CAPTSEL0 0x20U -#define TIMER1CAPTSEL0 0x40U -#define TIMER2CAPTSEL0 0x60U -#define PINTSEL0 0xC0U -#define DMA0_ITRIG_INMUX0 0xE0U -#define DMA0_OTRIG_INMUX0 0x160U -#define FREQMEAS_REF_REG 0x180U -#define FREQMEAS_TARGET_REG 0x184U -#define TIMER3CAPTSEL0 0x1A0U -#define TIMER4CAPTSEL0 0x1C0U -#define PINTSECSEL0 0x1E0U -#define DMA1_ITRIG_INMUX0 0x200U -#define DMA1_OTRIG_INMUX0 0x240U -#define PMUX_SHIFT 20U - -/*! @brief INPUTMUX connections type */ -typedef enum _inputmux_connection_t -{ - /*!< SCT0 INMUX. */ - kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToSct0 = 8U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToSct0 = 9U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToSct0 = 10U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToSct0 = 11U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToSct0 = 12U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToSct0 = 14U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_CompOutToSct0 = 17U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedSck0ToSct0 = 18U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedSck1ToSct0 = 19U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToSct0 = 20U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToSct0 = 21U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_INMUX0 << PMUX_SHIFT), - - /*!< TIMER0 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - - /*!< TIMER1 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - - /*!< TIMER2 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - - /*!< Pin interrupt select. */ - kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT), - - /*!< DMA0 Input trigger. */ - kINPUTMUX_PinInt0ToDma0 = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToDma0 = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToDma0 = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDma0 = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_CompOutToDma0 = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig0ToDma0 = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig1ToDma0 = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig2ToDma0 = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig3ToDma0 = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq0ToDma0 = 19U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq1ToDma0 = 20U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_HashDmaRxToDma0 = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - - /*!< DMA0 output trigger. */ - kINPUTMUX_Dma0Hash0TxTrigoutToTriginChannels = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0HsLspiRxTrigoutToTriginChannels = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0HsLspiTxTrigoutToTriginChannels = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm2RxTrigoutToTriginChannels = 8U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm2TxTrigoutToTriginChannels = 9U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm3RxTrigoutToTriginChannels = 10U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm3TxTrigoutToTriginChannels = 11U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm4RxTrigoutToTriginChannels = 12U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm4TxTrigoutToTriginChannels = 13U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm5RxTrigoutToTriginChannels = 14U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm5TxTrigoutToTriginChannels = 15U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm6RxTrigoutToTriginChannels = 16U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm6TxTrigoutToTriginChannels = 17U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm7RxTrigoutToTriginChannels = 18U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Flexcomm7TxTrigoutToTriginChannels = 19U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Capt0TxTrigoutToTriginChannels = 20U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Adc0Ch0TrigoutToTriginChannels = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Adc0Ch1TrigoutToTriginChannels = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - - /*!< Selection for frequency measurement reference clock. */ - kINPUTMUX_ExternOscToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_Fro12MhzToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_Fro96MhzToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_WdtOscToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_32KhzOscToFreqmeasRef= 4u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_MainClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_aRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_bRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), - - /*!< Selection for frequency measurement target clock. */ - kINPUTMUX_ExternOscToFreqmeasTarget = 0U + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_Fro12MhzToFreqmeasTarget = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_Fro96MhzToFreqmeasTarget = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_WdtOscToFreqmeasTarget = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_32KhzOscToFreqmeasTarget= 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_MainClkToFreqmeasTarget = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_aTarget = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_bTarget = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - - /*!< TIMER3 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - - /*!< Timer4 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb0FrameToggleToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Usb1FrameToggleToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - - /*Pin interrupt secure select */ - kINPUTMUX_GpioPort0Pin0ToPintSecsel = 0U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin1ToPintSecsel = 1U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin2ToPintSecsel = 2U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin3ToPintSecsel = 3U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin4ToPintSecsel = 4U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin5ToPintSecsel = 5U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin6ToPintSecsel = 6U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin7ToPintSecsel = 7U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin8ToPintSecsel = 8U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin9ToPintSecsel = 9U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin10ToPintSecsel = 10U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin11ToPintSecsel = 11U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin12ToPintSecsel = 12U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin13ToPintSecsel = 13U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin14ToPintSecsel = 14U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin15ToPintSecsel = 15U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin16ToPintSecsel = 16U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin17ToPintSecsel = 17U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin18ToPintSecsel = 18U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin19ToPintSecsel = 19U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin20ToPintSecsel = 20U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin21ToPintSecsel = 21U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin22ToPintSecsel = 22U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin23ToPintSecsel = 23U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin24ToPintSecsel = 24U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin25ToPintSecsel = 25U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin26ToPintSecsel = 26U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin27ToPintSecsel = 27U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin28ToPintSecsel = 28U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin29ToPintSecsel = 29U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin30ToPintSecsel = 30U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin31ToPintSecsel = 31U + (PINTSECSEL0 << PMUX_SHIFT), - - /*!< DMA1 Input trigger. */ - kINPUTMUX_PinInt0ToDma1 = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToDma1 = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToDma1 = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDma1 = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDma1 = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToDma1 = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig0ToDma1 = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig1ToDma1 = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig2ToDma1 = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig3ToDma1 = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq0ToDma1 = 12U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Sct0DmaReq1ToDma1 = 13U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_HashDmaRxToDma1 = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - - /*!< DMA1 output trigger. */ - kINPUTMUX_Dma1Hash0TxTrigoutToTriginChannels = 0U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm2RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm2TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), -} inputmux_connection_t; - -/*@}*/ - -#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_iocon.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_iocon.h deleted file mode 100644 index b7bf0de17b..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_iocon.h +++ /dev/null @@ -1,288 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_IOCON_H_ -#define _FSL_IOCON_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_iocon - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" -#endif - -/*! @name Driver version */ -/*@{*/ -/*! @brief IOCON driver version 2.0.0. */ -#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/** - * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format - */ -typedef struct _iocon_group -{ - uint32_t port : 8; /* Pin port */ - uint32_t pin : 8; /* Pin number */ - uint32_t ionumber : 8; /* IO number */ - uint32_t modefunc : 16; /* Function and mode */ -} iocon_group_t; - -/** - * @brief IOCON function and mode selection definitions - * @note See the User Manual for specific modes and functions supported by the various pins. - */ -#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) -#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ -#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ -#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ -#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ -#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ -#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ -#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ -#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ -#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ -#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ -#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ -#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ -#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ -#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ -#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ -#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ -#if defined(IOCON_PIO_MODE_SHIFT) -#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ -#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ -#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ -#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ -#endif - -#if defined(IOCON_PIO_I2CSLEW_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_EGP_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_SLEW_SHIFT) -#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ -#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_INVERT_SHIFT) -#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ -#endif - -#if defined(IOCON_PIO_DIGIMODE_SHIFT) -#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ -#define IOCON_DIGITAL_EN \ - (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ -#endif - -#if defined(IOCON_PIO_FILTEROFF_SHIFT) -#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ -#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ -#endif - -#if defined(IOCON_PIO_I2CDRIVE_SHIFT) -#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ -#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ -#endif - -#if defined(IOCON_PIO_OD_SHIFT) -#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ -#endif - -#if defined(IOCON_PIO_I2CFILTER_SHIFT) -#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ -#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */ -#endif - -#if defined(IOCON_PIO_ASW_SHIFT) -#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */ -#endif - -#if defined(IOCON_PIO_SSEL_SHIFT) -#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */ -#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */ -#endif - -#if defined(IOCON_PIO_ECS_SHIFT) -#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */ -#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */ -#endif - -#if defined(IOCON_PIO_S_MODE_SHIFT) -#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ -#define IOCON_S_MODE_1CLK \ - (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_2CLK \ - (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_3CLK \ - (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ -#endif - -#if defined(IOCON_PIO_CLK_DIV_SHIFT) -#define IOCON_CLKDIV(div) \ - ((div) \ - << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ -#endif - -#else -#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ -#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ -#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ -#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ -#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ -#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ -#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ -#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ - -#if defined(IOCON_PIO_MODE_SHIFT) -#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ -#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ -#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ -#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ -#endif - -#if defined(IOCON_PIO_I2CSLEW_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_EGP_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_INVERT_SHIFT) -#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ -#endif - -#if defined(IOCON_PIO_DIGIMODE_SHIFT) -#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ -#define IOCON_DIGITAL_EN \ - (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ -#endif - -#if defined(IOCON_PIO_FILTEROFF_SHIFT) -#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ -#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ -#endif - -#if defined(IOCON_PIO_I2CDRIVE_SHIFT) -#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ -#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ -#endif - -#if defined(IOCON_PIO_OD_SHIFT) -#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ -#endif - -#if defined(IOCON_PIO_I2CFILTER_SHIFT) -#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ -#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled */ -#endif - -#if defined(IOCON_PIO_S_MODE_SHIFT) -#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ -#define IOCON_S_MODE_1CLK \ - (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_2CLK \ - (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_3CLK \ - (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ -#endif - -#if defined(IOCON_PIO_CLK_DIV_SHIFT) -#define IOCON_CLKDIV(div) \ - ((div) \ - << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ -#endif - -#endif -#if defined(__cplusplus) -extern "C" { -#endif - -#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) -/** - * @brief Sets I/O Control pin mux - * @param base : The base of IOCON peripheral on the chip - * @param ionumber : GPIO number to mux - * @param modefunc : OR'ed values of type IOCON_* - * @return Nothing - */ -__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc) -{ - base->PIO[ionumber] = modefunc; -} -#else -/** - * @brief Sets I/O Control pin mux - * @param base : The base of IOCON peripheral on the chip - * @param port : GPIO port to mux - * @param pin : GPIO pin to mux - * @param modefunc : OR'ed values of type IOCON_* - * @return Nothing - */ -__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) -{ - base->PIO[port][pin] = modefunc; -} -#endif - -/** - * @brief Set all I/O Control pin muxing - * @param base : The base of IOCON peripheral on the chip - * @param pinArray : Pointer to array of pin mux selections - * @param arrayLength : Number of entries in pinArray - * @return Nothing - */ -__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) -{ - uint32_t i; - - for (i = 0; i < arrayLength; i++) - { -#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) - IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc); -#else - IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); -#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ - } -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_IOCON_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_lpadc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_lpadc.c deleted file mode 100644 index 46a1309391..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_lpadc.c +++ /dev/null @@ -1,611 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_lpadc.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpadc" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for LPADC module. - * - * @param base LPADC peripheral base address - */ -static uint32_t LPADC_GetInstance(ADC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to LPADC bases for each instance. */ -static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to LPADC clocks for each instance. */ -static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t LPADC_GetInstance(ADC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++) - { - if (s_lpadcBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_lpadcBases)); - - return instance; -} - -/*! - * brief Initializes the LPADC module. - * - * param base LPADC peripheral base address. - * param config Pointer to configuration structure. See "lpadc_config_t". - */ -void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) -{ - /* Check if the pointer is available. */ - assert(config != NULL); - - uint32_t tmp32 = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock for LPADC instance. */ - CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module. */ - LPADC_DoResetConfig(base); -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - LPADC_DoResetFIFO0(base); - LPADC_DoResetFIFO1(base); -#else - LPADC_DoResetFIFO(base); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - - /* Disable the module before setting configuration. */ - LPADC_Enable(base, false); - - /* Configure the module generally. */ - if (config->enableInDozeMode) - { - base->CTRL &= ~ADC_CTRL_DOZEN_MASK; - } - else - { - base->CTRL |= ADC_CTRL_DOZEN_MASK; - } - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - /* Set calibration average mode. */ - base->CTRL |= ADC_CTRL_CAL_AVGS(config->conversionAverageMode); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - -/* ADCx_CFG. */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - if (config->enableInternalClock) - { - tmp32 |= ADC_CFG_ADCKEN_MASK; - } -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - if (config->enableVref1LowVoltage) - { - tmp32 |= ADC_CFG_VREF1RNG_MASK; - } -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - if (config->enableAnalogPreliminary) - { - tmp32 |= ADC_CFG_PWREN_MASK; - } - tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ - | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */ - | ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */ - | ADC_CFG_TPRICTRL(config->triggerPrioirtyPolicy); /* Trigger priority policy. */ - base->CFG = tmp32; - - /* ADCx_PAUSE. */ - if (config->enableConvPause) - { - base->PAUSE = ADC_PAUSE_PAUSEEN_MASK | ADC_PAUSE_PAUSEDLY(config->convPauseDelay); - } - else - { - base->PAUSE = 0U; - } - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - /* ADCx_FCTRL0. */ - base->FCTRL[0] = ADC_FCTRL_FWMARK(config->FIFO0Watermark); - /* ADCx_FCTRL1. */ - base->FCTRL[1] = ADC_FCTRL_FWMARK(config->FIFO1Watermark); -#else - /* ADCx_FCTRL. */ - base->FCTRL = ADC_FCTRL_FWMARK(config->FIFOWatermark); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - - /* Enable the module after setting configuration. */ - LPADC_Enable(base, true); -} - -/*! - * brief Gets an available pre-defined settings for initial configuration. - * - * This function initializes the converter configuration structure with an available settings. The default values are: - * code - * config->enableInDozeMode = true; - * config->conversionAverageMode = kLPADC_ConversionAverage1; - * config->enableAnalogPreliminary = false; - * config->powerUpDelay = 0x80; - * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - * config->powerLevelMode = kLPADC_PowerLevelAlt1; - * config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately; - * config->enableConvPause = false; - * config->convPauseDelay = 0U; - * config->FIFO0Watermark = 0U; - * config->FIFO1Watermark = 0U; - * config->FIFOWatermark = 0U; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConfig(lpadc_config_t *config) -{ - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - config->enableInternalClock = false; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - config->enableVref1LowVoltage = false; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - config->enableInDozeMode = true; -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - /* Set calibration average mode. */ - config->conversionAverageMode = kLPADC_ConversionAverage1; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - config->enableAnalogPreliminary = false; - config->powerUpDelay = 0x80; - config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - config->powerLevelMode = kLPADC_PowerLevelAlt1; - config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately; - config->enableConvPause = false; - config->convPauseDelay = 0U; -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - config->FIFO0Watermark = 0U; - config->FIFO1Watermark = 0U; -#else - config->FIFOWatermark = 0U; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ -} - -/*! - * brief De-initializes the LPADC module. - * - * param base LPADC peripheral base address. - */ -void LPADC_Deinit(ADC_Type *base) -{ - /* Disable the module. */ - LPADC_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the clock. */ - CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * brief Get the result in conversion FIFOn. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. - * param index Result FIFO index. - * - * return Status whether FIFOn entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index) -{ - assert(result != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = base->RESFIFO[index]; - - if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) - { - return false; /* FIFO is empty. Discard any read from RESFIFO. */ - } - - result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; - result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; - result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; - result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); - - return true; -} -#else -/*! - * brief Get the result in conversion FIFO. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFO. - * - * return Status whether FIFO entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result) -{ - assert(result != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = base->RESFIFO; - - if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) - { - return false; /* FIFO is empty. Discard any read from RESFIFO. */ - } - - result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; - result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; - result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; - result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); - - return true; -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * brief Configure the conversion trigger source. - * - * Each programmable trigger can launch the conversion command in command buffer. - * - * param base LPADC peripheral base address. - * param triggerId ID for each trigger. Typically, the available value range is from 0. - * param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. - */ -void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config) -{ - assert(triggerId < ADC_TCTRL_COUNT); /* Check if the triggerId is available in this device. */ - assert(config != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = ADC_TCTRL_TCMD(config->targetCommandId) /* Trigger command select. */ - | ADC_TCTRL_TDLY(config->delayPower) /* Trigger delay select. */ - | ADC_TCTRL_TPRI(config->priority) /* Trigger priority setting. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect) -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - ; - if (config->enableHardwareTrigger) - { - tmp32 |= ADC_TCTRL_HTEN_MASK; - } - - base->TCTRL[triggerId] = tmp32; -} - -/*! - * brief Gets an available pre-defined settings for trigger's configuration. - * - * This function initializes the trigger's configuration structure with an available settings. The default values are: - * code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; - * config->channelAFIFOSelect = 0U; - * config->channelBFIFOSelect = 0U; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config) -{ - assert(config != NULL); /* Check if the input pointer is available. */ - - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - - config->targetCommandId = 0U; - config->delayPower = 0U; - config->priority = 0U; -#if defined(FSL_FEATURE_LPADC_FIFO_COUNT) && FSL_FEATURE_LPADC_FIFO_COUNT - config->channelAFIFOSelect = 0U; - config->channelBFIFOSelect = 0U; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - config->enableHardwareTrigger = false; -} - -/*! - * brief Configure conversion command. - * - * param base LPADC peripheral base address. - * param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. - * param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. - */ -void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config) -{ - assert(commandId < (ADC_CMDL_COUNT + 1U)); /* Check if the commandId is available on this device. */ - assert(config != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32 = 0; - - commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */ - - /* ADCx_CMDL. */ - tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE - tmp32 |= ADC_CMDL_CTYPE(config->sampleChannelMode); -#else - switch (config->sampleChannelMode) /* Sample input. */ - { - case kLPADC_SampleChannelSingleEndSideB: - tmp32 |= ADC_CMDL_ABSEL_MASK; - break; -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - case kLPADC_SampleChannelDiffBothSideAB: - tmp32 |= ADC_CMDL_DIFF_MASK; - break; - case kLPADC_SampleChannelDiffBothSideBA: - tmp32 |= ADC_CMDL_ABSEL_MASK | ADC_CMDL_DIFF_MASK; - break; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ - default: /* kLPADC_SampleChannelSingleEndSideA. */ - break; - } -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - tmp32 |= ADC_CMDL_MODE(config->conversionResoultuionMode); -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ - base->CMD[commandId].CMDL = tmp32; - - /* ADCx_CMDH. */ - tmp32 = ADC_CMDH_NEXT(config->chainedNextCommandNumber) /* Next Command Select. */ - | ADC_CMDH_LOOP(config->loopCount) /* Loop Count Select. */ - | ADC_CMDH_AVGS(config->hardwareAverageMode) /* Hardware Average Select. */ - | ADC_CMDH_STS(config->sampleTimeMode) /* Sample Time Select. */ - | ADC_CMDH_CMPEN(config->hardwareCompareMode); /* Hardware compare enable. */ -#if (defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) - if (config->enableWaitTrigger) - { - tmp32 |= ADC_CMDH_WAIT_TRIG_MASK; /* Wait trigger enable. */ - } -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ - - if (config->enableAutoChannelIncrement) - { - tmp32 |= ADC_CMDH_LWI_MASK; - } - base->CMD[commandId].CMDH = tmp32; - - /* Hardware compare settings. - * Not all Command Buffers have an associated Compare Value register. The compare function is only available on - * Command Buffers that have a corresponding Compare Value register. - */ - if (kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) - { - /* Check if the hardware compare feature is available for indicated command buffer. */ - assert(commandId < ADC_CV_COUNT); - - /* Set CV register. */ - base->CV[commandId] = ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */ - | ADC_CV_CVL(config->hardwareCompareValueLow); /* Compare value low. */ - } -} - -/*! - * brief Gets an available pre-defined settings for conversion command's configuration. - * - * This function initializes the conversion command's configuration structure with an available settings. The default - * values are: - * code - * config->sampleScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; - * config->channelNumber = 0U; - * config->chainedNextCmdNumber = 0U; - * config->enableAutoChannelIncrement = false; - * config->loopCount = 0U; - * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - * config->sampleTimeMode = kLPADC_SampleTimeADCK3; - * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - * config->hardwareCompareValueHigh = 0U; - * config->hardwareCompareValueLow = 0U; - * config->conversionResoultuionMode = kLPADC_ConversionResolutionStandard; - * config->enableWaitTrigger = false; - * endcode - * param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) -{ - assert(config != NULL); /* Check if the input pointer is available. */ - - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - config->sampleScaleMode = kLPADC_SampleFullScale; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ - config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; - config->channelNumber = 0U; - config->chainedNextCommandNumber = 0U; /* No next command defined. */ - config->enableAutoChannelIncrement = false; - config->loopCount = 0U; - config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - config->sampleTimeMode = kLPADC_SampleTimeADCK3; - config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - config->hardwareCompareValueHigh = 0U; /* No used. */ - config->hardwareCompareValueLow = 0U; /* No used. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - config->conversionResoultuionMode = kLPADC_ConversionResolutionStandard; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG - config->enableWaitTrigger = false; -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ -} - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS -/*! - * brief Enable the calibration function. - * - * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes - * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value - * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- - * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the - * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. - * - * param base LPADC peripheral base address. - * bool enable switcher to the calibration function. - */ -void LPADC_EnableCalibration(ADC_Type *base, bool enable) -{ - LPADC_Enable(base, false); - if (enable) - { - base->CFG |= ADC_CFG_CALOFS_MASK; - } - else - { - base->CFG &= ~ADC_CFG_CALOFS_MASK; - } - LPADC_Enable(base, true); -} - -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! -* brief Do auto calibration. -* -* Calibration function should be executed before using converter in application. It used the software trigger and a -* dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API including: -* -LPADC_EnableCalibration(...) -* -LPADC_LPADC_SetOffsetValue(...) -* -LPADC_SetConvCommandConfig(...) -* -LPADC_SetConvTriggerConfig(...) -* -* param base LPADC peripheral base address. -*/ -void LPADC_DoAutoCalibration(ADC_Type *base) -{ - assert(0u == LPADC_GetConvResultCount(base)); - - uint32_t mLpadcCMDL; - uint32_t mLpadcCMDH; - uint32_t mLpadcTrigger; - lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct; - lpadc_conv_command_config_t mLpadcCommandConfigStruct; - lpadc_conv_result_t mLpadcResultConfigStruct; - - /* Enable the calibration function. */ - LPADC_EnableCalibration(base, true); - - /* Keep the CMD and TRG state here and restore it later if the calibration completes.*/ - mLpadcCMDL = base->CMD[0].CMDL; /* CMD1L. */ - mLpadcCMDH = base->CMD[0].CMDH; /* CMD1H. */ - mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ - - /* Set trigger0 configuration - for software trigger. */ - LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct); - mLpadcTriggerConfigStruct.targetCommandId = 1U; /* CMD1 is executed. */ - LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */ - - /* Set conversion CMD configuration. */ - LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct); - mLpadcCommandConfigStruct.hardwareAverageMode = kLPADC_HardwareAverageCount128; - LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); /* Set CMD1 configuration. */ - - /* Do calibration. */ - LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */ - while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct)) - { - } - /* The valid bits of data are bits 14:3 in the RESFIFO register. */ - LPADC_SetOffsetValue(base, (mLpadcResultConfigStruct.convValue) >> 3U); - /* Disable the calibration function. */ - LPADC_EnableCalibration(base, false); - - /* restore CMD and TRG registers. */ - base->CMD[0].CMDL = mLpadcCMDL; /* CMD1L. */ - base->CMD[0].CMDH = mLpadcCMDH; /* CMD1H. */ - base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ -} -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS -/*! - * brief Do offset calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoOffsetCalibration(ADC_Type *base) -{ - LPADC_EnableOffsetCalibration(base, true); - while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) - { - } -} - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ -/*! -* brief Do auto calibration. -* -* param base LPADC peripheral base address. -*/ -void LPADC_DoAutoCalibration(ADC_Type *base) -{ - assert((0u == LPADC_GetConvResultCount(base, 0)) && (0u == LPADC_GetConvResultCount(base, 1))); - - uint32_t GCCa; - uint32_t GCCb; - uint32_t GCRa; - uint32_t GCRb; - - /* Request gain calibration. */ - base->CTRL |= ADC_CTRL_CAL_REQ_MASK; - while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) || - (ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK))) - { - } - - /* Calculate gain offset. */ - GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); - GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); - GCRa = (uint16_t)((GCCa << 16U) / - (0xFFFFU - GCCa)); /* Gain_CalA = (65536 / (65536-(ADC_GCC_GAIN_CAL(ADC0->GCC[0])). */ - GCRb = (uint16_t)((GCCb << 16U) / - (0xFFFFU - GCCb)); /* Gain_CalB = (65536 / (65536-(ADC_GCC_GAIN_CAL(ADC0->GCC[1])). */ - base->GCR[0] = ADC_GCR_GCALR(GCRa); - base->GCR[1] = ADC_GCR_GCALR(GCRb); - - /* Indicate the values are valid. */ - base->GCR[0] |= ADC_GCR_RDY_MASK; - base->GCR[1] |= ADC_GCR_RDY_MASK; - - while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) - { - } -} -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_lpadc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_lpadc.h deleted file mode 100644 index 3507c08af8..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_lpadc.h +++ /dev/null @@ -1,844 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_LPADC_H_ -#define _FSL_LPADC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpadc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPADC driver version 2.0.3. */ -#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -/*! - * @brief Define the MACRO function to get command status from status value. - * - * The statusVal is the return value from LPADC_GetStatusFlags(). - */ -#define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT) - -/*! - * @brief Define the MACRO function to get trigger status from status value. - * - * The statusVal is the return value from LPADC_GetStatusFlags(). - */ -#define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT) - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Define hardware flags of the module. - */ -enum _lpadc_status_flags -{ - kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, /*!< Indicates that more data has been written to the Result - FIFO 0 than it can hold. */ - kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result - FIFO 0 is greater than the setting watermark level. */ - kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result - FIFO 1 than it can hold. */ - kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result - FIFO 1 is greater than the setting watermark level. */ -}; - -/*! - * @brief Define interrupt switchers of the module. - */ -enum _lpadc_interrupt_enable -{ - kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF0 flag is asserted. */ - kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY0 flag is asserted. */ - kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF1 flag is asserted. */ - kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY1 flag is asserted. */ -}; -#else -/*! - * @brief Define hardware flags of the module. - */ -enum _lpadc_status_flags -{ - kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO - than it can hold. */ - kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO - is greater than the setting watermark level. */ -}; - -/*! - * @brief Define interrupt switchers of the module. - */ -enum _lpadc_interrupt_enable -{ - kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF flag is asserted. */ - kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY flag is asserted. */ -}; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * @brief Define enumeration of sample scale mode. - * - * The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum - * possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the - * reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows - * conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode. - */ -typedef enum _lpadc_sample_scale_mode -{ - kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. (Factor of 30/64). */ - kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */ -} lpadc_sample_scale_mode_t; - -/*! - * @brief Define enumeration of channel sample mode. - * - * The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B. - */ -typedef enum _lpadc_sample_channel_mode -{ - kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */ - kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minue side. */ - kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minue side. */ -#elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE - kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */ - kLPADC_SampleChannelDualSingleEndBothSide = - 3U, /*!< Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */ -#endif -} lpadc_sample_channel_mode_t; - -/*! - * @brief Define enumeration of hardware average selection. - * - * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to - * capture temporary results while the averaging iterations are executed. - */ -typedef enum _lpadc_hardware_average_mode -{ - kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */ - kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */ - kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */ - kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */ - kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */ - kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */ - kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */ - kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */ -} lpadc_hardware_average_mode_t; - -/*! - * @brief Define enumeration of sample time selection. - * - * The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher - * impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption - * when command looping and sequencing is configured and high conversion rates are not required. - */ -typedef enum _lpadc_sample_time_mode -{ - kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */ -} lpadc_sample_time_mode_t; - -/*! - * @brief Define enumeration of hardware compare mode. - * - * After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting - * guides operation of the automatic compare function to optionally only store when the compare operation is true. - * When compare is enabled, the conversion result is compared to the compare values. - */ -typedef enum _lpadc_hardware_compare_mode -{ - kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */ - kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */ - kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */ -} lpadc_hardware_compare_mode_t; - -/*! - * @brief Define enumeration of conversion resolution mode. - * - * Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to - * #_lpadc_sample_channel_mode - */ -typedef enum _lpadc_conversion_resolution_mode -{ - kLPADC_ConversionResolutionStandard = 0U, /*!< Standard resolution. Single-ended 12-bit conversion, Differential - 13-bit conversion with 2’s complement output. */ - kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit - conversion with 2’s complement output. */ -} lpadc_conversion_resolution_mode_t; - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS -/*! - * @brief Define enumeration of conversion averages mode. - * - * Configure the converion average number for auto-calibration. - */ -typedef enum _lpadc_conversion_average_mode -{ - kLPADC_ConversionAverage1 = 0U, /*!< Single conversion. */ - kLPADC_ConversionAverage2 = 1U, /*!< 2 conversions averaged. */ - kLPADC_ConversionAverage4 = 2U, /*!< 4 conversions averaged. */ - kLPADC_ConversionAverage8 = 3U, /*!< 8 conversions averaged. */ - kLPADC_ConversionAverage16 = 4U, /*!< 16 conversions averaged. */ - kLPADC_ConversionAverage32 = 5U, /*!< 32 conversions averaged. */ - kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */ - kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */ -} lpadc_conversion_average_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - -/*! - * @brief Define enumeration of reference voltage source. - * - * For detail information, need to check the SoC's specification. - */ -typedef enum _lpadc_reference_voltage_mode -{ - kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */ - kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */ - kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */ -} lpadc_reference_voltage_source_t; - -/*! - * @brief Define enumeration of power configuration. - * - * Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be - * possible. Refer to the device data sheet for power and performance capabilities for each setting. - */ -typedef enum _lpadc_power_level_mode -{ - kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */ - kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */ - kLPADC_PowerLevelAlt3 = 2U, /*!< ... */ - kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */ -} lpadc_power_level_mode_t; - -/*! - * @brief Define enumeration of trigger priority policy. - * - * This selection controls how higher priority triggers are handled. - */ -typedef enum _lpadc_trigger_priority_policy -{ - kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command - processing, the current conversion is aborted and the new - command specified by the trigger is started. */ - kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing, - the current conversion is completed (including averaging iterations - and compare function if enabled) and stored to the result FIFO - before the higher priority trigger/command is initiated. */ - kLPADC_TriggerPriorityPreemptSubsequently = - 2U, /*!< If a higher priority trigger is received during command processing, the current - command will be completed (averaging, looping, compare) before servicing the - higher priority trigger. */ -} lpadc_trigger_priority_policy_t; - -/*! - * @beief LPADC global configuration. - * - * This structure would used to keep the settings for initialization. - */ -typedef struct -{ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock - selection logic at the chip level and is optionally used for the ADC clock source. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true". - If voltage reference option1 input is above 1.8V, it should be "false". */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When - enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the - ADC will wait for the current averaging iteration/FIFO storage to complete before - acknowledging stop or wait mode entry. */ -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - lpadc_conversion_average_mode_t conversionAverageMode; /*!< Auto-Calibration Averages. */ -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without - startup delays(at the cost of higher DC current consumption). */ - uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered - while the ADC is active and there is a counted delay defined by this field after an - initial trigger transitions the ADC from its Idle state to allow time for the analog - circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must - result in a longer delay than the analog startup time. */ - lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for - conversions.*/ - lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ - lpadc_trigger_priority_policy_t triggerPrioirtyPolicy; /*!< Control how higher priority triggers are handled, see to - #lpadc_trigger_priority_policy_mode_t. */ - bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during - command execution sequencing between LOOP iterations, between commands in a sequence, and - between conversions when command is executing in "Compare Until True" configuration. */ - uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay - is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing - function is enabled. The available value range is in 9-bit. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - /* for FIFO0. */ - uint32_t - FIFO0Watermark; /*!< FIFO0Watermark is a programmable threshold setting. When the number of datawords stored - in the ADC Result FIFO0 is greater than the value in this field, the ready flag would be - asserted to indicate stored data has reached the programmable threshold. */ - /* for FIFO1. */ - uint32_t - FIFO1Watermark; /*!< FIFO1Watermark is a programmable threshold setting. When the number of datawords stored - in the ADC Result FIFO1 is greater than the value in this field, the ready flag would be - asserted to indicate stored data has reached the programmable threshold. */ -#else - /* for FIFO. */ - uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored - in the ADC Result FIFO is greater than the value in this field, the ready flag would be - asserted to indicate stored data has reached the programmable threshold. */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ -} lpadc_config_t; - -/*! - * @brief Define structure to keep the configuration for conversion command. - */ -typedef struct -{ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ - lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */ - uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */ - uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes. - 1-15 is available, 0 is to terminate the chain after this command. */ - bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number - of times the selected channel is converted consecutively; when enabled, the - "loopCount" field defines how many consecutive channels are converted as part - of the command execution. */ - uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next - command or Idle state. Command executes LOOP+1 times. 0-15 is available. */ - lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */ - lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */ - - lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */ - uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */ - uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - lpadc_conversion_resolution_mode_t conversionResoultuionMode; /*!< Conversion resolution mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG - bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be - automatically executed; when enabled, the active trigger must be asserted again before - executing this command. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ -} lpadc_conv_command_config_t; - -/*! - * @brief Define structure to keep the configuration for conversion trigger. - */ -typedef struct -{ - uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated - trigger event. */ - uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event. - When this field is clear, then no delay is incurred. When this field is set to a non-zero - value, the duration for the delay is 2^delayPower ADCK cycles. The available value range - is 4-bit. */ - uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same - priority level setting, the lower order trigger event has the higher priority. The lower - value for this field is for the higher priority, the available value range is 1-bit. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */ - uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the - input trigger source or not. THe software trigger is always available. */ -} lpadc_conv_trigger_config_t; - -/*! - * @brief Define the structure to keep the conversion result. - */ -typedef struct -{ - uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */ - uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */ - uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */ - uint16_t convValue; /*!< Data result. */ -} lpadc_conv_result_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ -/*! - * @name Initialization & de-initialization. - * @{ - */ - -/*! - * @brief Initializes the LPADC module. - * - * @param base LPADC peripheral base address. - * @param config Pointer to configuration structure. See "lpadc_config_t". - */ -void LPADC_Init(ADC_Type *base, const lpadc_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for initial configuration. - * - * This function initializes the converter configuration structure with an available settings. The default values are: - * @code - * config->enableInDozeMode = true; - * config->enableAnalogPreliminary = false; - * config->powerUpDelay = 0x80; - * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - * config->powerLevelMode = kLPADC_PowerLevelAlt1; - * config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately; - * config->enableConvPause = false; - * config->convPauseDelay = 0U; - * config->FIFOWatermark = 0U; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConfig(lpadc_config_t *config); - -/*! - * @brief De-initializes the LPADC module. - * - * @param base LPADC peripheral base address. - */ -void LPADC_Deinit(ADC_Type *base); - -/*! - * @brief Switch on/off the LPADC module. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the module. - */ -static inline void LPADC_Enable(ADC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= ADC_CTRL_ADCEN_MASK; - } - else - { - base->CTRL &= ~ADC_CTRL_ADCEN_MASK; - } -} - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Do reset the conversion FIFO0. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO0(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO0_MASK; -} - -/*! - * @brief Do reset the conversion FIFO1. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO1(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO1_MASK; -} -#else -/*! - * @brief Do reset the conversion FIFO. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO_MASK; -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * @brief Do reset the module's configuration. - * - * Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL). - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetConfig(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RST_MASK; - base->CTRL &= ~ADC_CTRL_RST_MASK; -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get status flags. - * - * @param base LPADC peripheral base address. - * @return status flags' mask. See to #_lpadc_status_flags. - */ -static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base) -{ - return base->STAT; -} - -/*! - * @brief Clear status flags. - * - * Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags. - */ -static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) -{ - base->STAT = mask; -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enable interrupts. - * - * @param base LPADC peripheral base address. - * @mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. - */ -static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->IE |= mask; -} - -/*! - * @brief Disable interrupts. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. - */ -static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->IE &= ~mask; -} - -/*! - * @name DMA Control - * @{ - */ - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Switch on/off the DMA trigger for FIFO0 watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE0_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE0_MASK; - } -} - -/*! - * @brief Switch on/off the DMA trigger for FIFO1 watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE1_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE1_MASK; - } -} -#else -/*! - * @brief Switch on/off the DMA trigger for FIFO watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE_MASK; - } -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - /* @} */ - -/*! - * @name Trigger and conversion with FIFO. - * @{ - */ - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Get the count of result kept in conversion FIFOn. - * - * @param base LPADC peripheral base address. - * @param index Result FIFO index. - * @return The count of result kept in conversion FIFOn. - */ -static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index) -{ - return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT; -} - -/*! - * brief Get the result in conversion FIFOn. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. - * param index Result FIFO index. - * - * return Status whether FIFOn entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); -#else -/*! - * @brief Get the count of result kept in conversion FIFO. - * - * @param base LPADC peripheral base address. - * @return The count of result kept in conversion FIFO. - */ -static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base) -{ - return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT; -} - -/*! - * @brief Get the result in conversion FIFO. - * - * @param base LPADC peripheral base address. - * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. - * - * @return Status whether FIFO entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * @brief Configure the conversion trigger source. - * - * Each programmable trigger can launch the conversion command in command buffer. - * - * @param base LPADC peripheral base address. - * @param triggerId ID for each trigger. Typically, the available value range is from 0. - * @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. - */ -void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for trigger's configuration. - * - * This function initializes the trigger's configuration structure with an available settings. The default values are: - * @code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config); - -/*! - * @brief Do software trigger to conversion command. - * - * @param base LPADC peripheral base address. - * @param triggerIdMask Mask value for software trigger indexes, which count from zero. - */ -static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask) -{ - /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */ - base->SWTRIG = triggerIdMask; -} - -/*! - * @brief Configure conversion command. - * - * @param base LPADC peripheral base address. - * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. - * @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. - */ -void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for conversion command's configuration. - * - * This function initializes the conversion command's configuration structure with an available settings. The default - * values are: - * @code - * config->sampleScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; - * config->channelNumber = 0U; - * config->chainedNextCmdNumber = 0U; - * config->enableAutoChannelIncrement = false; - * config->loopCount = 0U; - * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - * config->sampleTimeMode = kLPADC_SampleTimeADCK3; - * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - * config->hardwareCompareValueHigh = 0U; - * config->hardwareCompareValueLow = 0U; - * config->conversionResoultuionMode = kLPADC_ConversionResolutionStandard; - * config->enableWaitTrigger = false; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config); - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS -/*! - * @brief Enable the calibration function. - * - * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes - * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value - * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- - * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the - * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. - * - * @param base LPADC peripheral base address. - * @bool enable switcher to the calibration function. - */ -void LPADC_EnableCalibration(ADC_Type *base, bool enable); -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * @brief Set proper offset value to trim ADC. - * - * To minimize the offset during normal operation, software should read the conversion result from - * the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register. - * - * @param base LPADC peripheral base address. - * @param value Setting offset value. - */ -static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) -{ - base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT; -} - -/*! -* @brief Do auto calibration. -* -* Calibration function should be executed before using converter in application. It used the software trigger and a -* dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API including: -* -LPADC_EnableCalibration(...) -* -LPADC_LPADC_SetOffsetValue(...) -* -LPADC_SetConvCommandConfig(...) -* -LPADC_SetConvTriggerConfig(...) -* -* @param base LPADC peripheral base address. -*/ -void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * @brief Set proper offset value to trim ADC. - * - * Set the offset trim value for offset calibration manually. - * - * @param base LPADC peripheral base address. - * @param valueA Setting offset value A. - * @param valueB Setting offset value B. - * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. - */ -static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) -{ - base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB); -} -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ - -/*! - * @brief Enable the offset calibration function. - * - * @param base LPADC peripheral base address. - * @bool enable switcher to the calibration function. - */ -static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= ADC_CTRL_CALOFS_MASK; - } - else - { - base->CTRL &= ~ADC_CTRL_CALOFS_MASK; - } -} - -/*! - * @brief Do offset calibration. - * - * @param base LPADC peripheral base address. - */ -void LPADC_DoOffsetCalibration(ADC_Type *base); - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ -/*! - * brief Do auto calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_LPADC_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_mailbox.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_mailbox.h deleted file mode 100644 index e2f9ece7d5..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_mailbox.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright(C) NXP Semiconductors, 2014 - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_MAILBOX_H_ -#define _FSL_MAILBOX_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup mailbox - * @{ - */ - -/*! @file */ - -/****************************************************************************** - * Definitions - *****************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.mailbox" -#endif - -/*! @name Driver version */ -/*@{*/ -/*! @brief MAILBOX driver version 2.1.0. */ -#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) -/*@}*/ - -/*! - * @brief CPU ID. - */ -#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) -typedef enum _mailbox_cpu_id -{ - kMAILBOX_CM33_Core1 = 0, - kMAILBOX_CM33_Core0 -} mailbox_cpu_id_t; -#else -typedef enum _mailbox_cpu_id -{ - kMAILBOX_CM0Plus = 0, - kMAILBOX_CM4 -} mailbox_cpu_id_t; -#endif -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @name MAILBOX initialization - * @{ - */ - -/*! - * @brief Initializes the MAILBOX module. - * - * This function enables the MAILBOX clock only. - * - * @param base MAILBOX peripheral base address. - */ -static inline void MAILBOX_Init(MAILBOX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Mailbox); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_FEATURE_MAILBOX_HAS_NO_RESET) && FSL_FEATURE_MAILBOX_HAS_NO_RESET) - /* Reset the MAILBOX module */ - RESET_PeripheralReset(kMAILBOX_RST_SHIFT_RSTn); -#endif -} - -/*! - * @brief De-initializes the MAILBOX module. - * - * This function disables the MAILBOX clock only. - * - * @param base MAILBOX peripheral base address. - */ -static inline void MAILBOX_Deinit(MAILBOX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Mailbox); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/* @} */ - -/*! - * @brief Set data value in the mailbox based on the CPU ID. - * - * @param base MAILBOX peripheral base address. - * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices, - * kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices. - * @param mboxData Data to send in the mailbox. - * - * @note Sets a data value to send via the MAILBOX to the other core. - */ -static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxData) -{ -#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) - assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); -#else - assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); -#endif - base->MBOXIRQ[cpu_id].IRQ = mboxData; -} - -/*! - * @brief Get data in the mailbox based on the CPU ID. - * - * @param base MAILBOX peripheral base address. - * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices, - * kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices. - * - * @return Current mailbox data. - */ -static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id) -{ -#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) - assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); -#else - assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); -#endif - return base->MBOXIRQ[cpu_id].IRQ; -} - -/*! - * @brief Set data bits in the mailbox based on the CPU ID. - * - * @param base MAILBOX peripheral base address. - * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices, - * kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices. - * @param mboxSetBits Data bits to set in the mailbox. - * - * @note Sets data bits to send via the MAILBOX to the other core. A value of 0 will - * do nothing. Only sets bits selected with a 1 in it's bit position. - */ -static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxSetBits) -{ -#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) - assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); -#else - assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); -#endif - base->MBOXIRQ[cpu_id].IRQSET = mboxSetBits; -} - -/*! - * @brief Clear data bits in the mailbox based on the CPU ID. - * - * @param base MAILBOX peripheral base address. - * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices, - * kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices. - * @param mboxClrBits Data bits to clear in the mailbox. - * - * @note Clear data bits to send via the MAILBOX to the other core. A value of 0 will - * do nothing. Only clears bits selected with a 1 in it's bit position. - */ -static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxClrBits) -{ -#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) - assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); -#else - assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); -#endif - base->MBOXIRQ[cpu_id].IRQCLR = mboxClrBits; -} - -/*! - * @brief Get MUTEX state and lock mutex - * - * @param base MAILBOX peripheral base address. - * - * @return See note - * - * @note Returns '1' if the mutex was taken or '0' if another resources has the - * mutex locked. Once a mutex is taken, it can be returned with the MAILBOX_SetMutex() - * function. - */ -static inline uint32_t MAILBOX_GetMutex(MAILBOX_Type *base) -{ - return (base->MUTEX & MAILBOX_MUTEX_EX_MASK); -} - -/*! - * @brief Set MUTEX state - * - * @param base MAILBOX peripheral base address. - * - * @note Sets mutex state to '1' and allows other resources to get the mutex. - */ -static inline void MAILBOX_SetMutex(MAILBOX_Type *base) -{ - base->MUTEX = MAILBOX_MUTEX_EX_MASK; -} - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ -/*@}*/ - -#endif /* _FSL_MAILBOX_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_mrt.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_mrt.c deleted file mode 100644 index 8306b33e76..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_mrt.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_mrt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.mrt" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base Multi-Rate timer peripheral base address - * - * @return The MRT instance - */ -static uint32_t MRT_GetInstance(MRT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to MRT bases for each instance. */ -static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to MRT clocks for each instance. */ -static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N; -#else -/*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_mrtResets[] = MRT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t MRT_GetInstance(MRT_Type *base) -{ - uint32_t instance; - uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < mrtArrayCount; instance++) - { - if (s_mrtBases[instance] == base) - { - break; - } - } - - assert(instance < mrtArrayCount); - - return instance; -} - -/*! - * brief Ungates the MRT clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application using the MRT driver. - * - * param base Multi-Rate timer peripheral base address - * param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in - * MODCFG reigster, param config is useless. - */ -void MRT_Init(MRT_Type *base, const mrt_config_t *config) -{ - assert(config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate the MRT clock */ - CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) - /* Set timer operating mode */ - base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask); -#endif -} - -/*! - * brief Gate the MRT clock - * - * param base Multi-Rate timer peripheral base address - */ -void MRT_Deinit(MRT_Type *base) -{ - /* Stop all the timers */ - MRT_StopTimer(base, kMRT_Channel_0); - MRT_StopTimer(base, kMRT_Channel_1); -#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 2U) - MRT_StopTimer(base, kMRT_Channel_2); -#endif -#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 3U) - MRT_StopTimer(base, kMRT_Channel_3); -#endif - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the MRT clock*/ - CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Used to update the timer period in units of count. - * - * The new value will be immediately loaded or will be loaded at the end of the current time - * interval. For one-shot interrupt mode the new value will be immediately loaded. - * - * note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * param base Multi-Rate timer peripheral base address - * param channel Timer channel number - * param count Timer period in units of ticks - * param immediateLoad true: Load the new value immediately into the TIMER register; - * false: Load the new value at the end of current timer interval - */ -void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t newValue = count; - if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == kMRT_OneShotMode) || (immediateLoad)) - { - /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */ - newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK; - } - - /* Update the timer interval value */ - base->CHANNEL[channel].INTVAL = newValue; -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_mrt.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_mrt.h deleted file mode 100644 index ea82599ba1..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_mrt.h +++ /dev/null @@ -1,365 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_MRT_H_ -#define _FSL_MRT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup mrt - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ -/*@}*/ - -/*! @brief List of MRT channels */ -typedef enum _mrt_chnl -{ - kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/ - kMRT_Channel_1, /*!< MRT channel number 1 */ - kMRT_Channel_2, /*!< MRT channel number 2 */ - kMRT_Channel_3 /*!< MRT channel number 3 */ -} mrt_chnl_t; - -/*! @brief List of MRT timer modes */ -typedef enum _mrt_timer_mode -{ - kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< Repeat Interrupt mode */ - kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< One-shot Interrupt mode */ - kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */ -} mrt_timer_mode_t; - -/*! @brief List of MRT interrupts */ -typedef enum _mrt_interrupt_enable -{ - kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/ -} mrt_interrupt_enable_t; - -/*! @brief List of MRT status flags */ -typedef enum _mrt_status_flags -{ - kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */ - kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK, /*!< Indicates state of the timer */ -} mrt_status_flags_t; - -/*! - * @brief MRT configuration structure - * - * This structure holds the configuration settings for the MRT peripheral. To initialize this - * structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _mrt_config -{ - bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */ -} mrt_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the MRT clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the MRT driver. - * - * @param base Multi-Rate timer peripheral base address - * @param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in - * MODCFG reigster, param config is useless. - */ -void MRT_Init(MRT_Type *base, const mrt_config_t *config); - -/*! - * @brief Gate the MRT clock - * - * @param base Multi-Rate timer peripheral base address - */ -void MRT_Deinit(MRT_Type *base); - -/*! - * @brief Fill in the MRT config struct with the default settings - * - * The default values are: - * @code - * config->enableMultiTask = false; - * @endcode - * @param config Pointer to user's MRT config structure. - */ -static inline void MRT_GetDefaultConfig(mrt_config_t *config) -{ - assert(config); -#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) - /* Use hardware status operating mode */ - config->enableMultiTask = false; -#endif -} - -/*! - * @brief Sets up an MRT channel mode. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Channel that is being configured. - * @param mode Timer mode to use for the channel. - */ -static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t reg = base->CHANNEL[channel].CTRL; - - /* Clear old value */ - reg &= ~MRT_CHANNEL_CTRL_MODE_MASK; - /* Add the new mode */ - reg |= mode; - - base->CHANNEL[channel].CTRL = reg; -} - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the MRT interrupt. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CTRL |= mask; -} - -/*! - * @brief Disables the selected MRT interrupt. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to disable. This is a logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].CTRL &= ~mask; -} - -/*! - * @brief Gets the enabled MRT interrupts. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::mrt_interrupt_enable_t - */ -static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the MRT status flags - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::mrt_status_flags_t - */ -static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK)); -} - -/*! - * @brief Clears the MRT status flags. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::mrt_status_flags_t - */ -static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK); -} - -/*! @}*/ - -/*! - * @name Read and Write the timer period - * @{ - */ - -/*! - * @brief Used to update the timer period in units of count. - * - * The new value will be immediately loaded or will be loaded at the end of the current time - * interval. For one-shot interrupt mode the new value will be immediately loaded. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * @param count Timer period in units of ticks - * @param immediateLoad true: Load the new value immediately into the TIMER register; - * false: Load the new value at the end of current timer interval - */ -void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad); - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number - * - * @return Current timer counting value in ticks - */ -static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - return base->CHANNEL[channel].TIMER; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer counting. - * - * After calling this function, timers load period value, counts down to 0 and - * depending on the timer mode it will either load the respective start value again or stop. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - * @param count Timer period in units of ticks - */ -static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - /* Write the timer interval value */ - base->CHANNEL[channel].INTVAL = count; -} - -/*! - * @brief Stops the timer counting. - * - * This function stops the timer from counting. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - */ -static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - /* Stop the timer immediately */ - base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK; -} - -/*! @}*/ - -/*! - * @name Get & release channel - * @{ - */ - -/*! - * @brief Find the available channel. - * - * This function returns the lowest available channel number. - * - * @param base Multi-Rate timer peripheral base address - */ -static inline uint32_t MRT_GetIdleChannel(MRT_Type *base) -{ - return base->IDLE_CH; -} - -#if !(defined(FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) && FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) -/*! - * @brief Release the channel when the timer is using the multi-task mode. - * - * In multi-task mode, the INUSE flags allow more control over when MRT channels are released for - * further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as - * long as it is needed and release it by calling this function. This removes the need to ask for - * an available channel for every use. - * - * @param base Multi-Rate timer peripheral base address - * @param channel Timer channel number. - */ -static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel) -{ - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - - uint32_t reg = base->CHANNEL[channel].STAT; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK; - reg |= MRT_CHANNEL_STAT_INUSE_MASK; - - base->CHANNEL[channel].STAT = reg; -} -#endif - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_MRT_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_ostimer.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_ostimer.c deleted file mode 100644 index 34291559cb..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_ostimer.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_ostimer.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.ostimer" -#endif - -/* Typedef for interrupt handler. */ -typedef void (*ostimer_isr_t)(OSTIMER_Type *base, ostimer_callback_t cb); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base OSTIMER peripheral base address - * - * @return The OSTIMER instance - */ -static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of OSTIMER handle. */ -static ostimer_callback_t s_ostimerHandle[FSL_FEATURE_SOC_OSTIMER_COUNT]; -/* Array of OSTIMER peripheral base address. */ -static OSTIMER_Type *const s_ostimerBases[] = OSTIMER_BASE_PTRS; -/* Array of OSTIMER IRQ number. */ -static const IRQn_Type s_ostimerIRQ[] = OSTIMER_IRQS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of OSTIMER clock name. */ -static const clock_ip_name_t s_ostimerClock[] = OSTIMER_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/* Array of OSTIMER reset name. */ -static const reset_ip_name_t s_ostimerReset[] = OSTIMER_RSTS; - -/* OSTIMER ISR for transactional APIs. */ -static ostimer_isr_t s_ostimerIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* @brief Function for getting the instance number of OS timer. */ -static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_ostimerBases); instance++) - { - if (s_ostimerBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_ostimerBases)); - - return instance; -} - -/* @brief Translate the value from gray-code to decimal. */ -static uint64_t OSTIMER_GrayToDecimal(uint64_t gray) -{ - uint64_t temp = gray; - while (temp) - { - temp >>= 1U; - gray ^= temp; - } - - return gray; -} - -/* @brief Translate the value from decimal to gray-code. */ -static uint64_t OSTIMER_DecimalToGray(uint64_t dec) -{ - return (dec ^ (dec >> 1U)); -} - -/*! -* @brief Initializes an OSTIMER by turning it's clock on. -* -*/ -void OSTIMER_Init(OSTIMER_Type *base) -{ - assert(base); - - uint32_t instance = OSTIMER_GetInstance(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the OSTIMER 32k clock in PMC module. */ - PMC->OSTIMERr |= PMC_OSTIMER_CLOCKENABLE_MASK; - PMC->OSTIMERr &= ~PMC_OSTIMER_OSC32KPD_MASK; - /* Enable clock for OSTIMER. */ - CLOCK_EnableClock(s_ostimerClock[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_OSTIMER_HAS_NO_RESET) && FSL_FEATURE_OSTIMER_HAS_NO_RESET) - /* Reset the OSTIMER. */ - RESET_PeripheralReset(s_ostimerReset[instance]); -#endif -} - -/*! - * @brief Deinitializes a OSTIMER instance. - * - * This function shuts down OSTIMER clock - * - * @param base OSTIMER peripheral base address. - */ -void OSTIMER_Deinit(OSTIMER_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable clock for OSTIMER. */ - CLOCK_DisableClock(s_ostimerClock[OSTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Get OSTIMER status Flags. - * - * This returns the status flag. - * Currently, only match interrupt flag can be got. - * - * @param base OSTIMER peripheral base address. - * @return status register value - */ -uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base) -{ - return base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK; -} - -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intr status flag. - * Currently, only match interrupt flag can be cleared. - * - * @param base OSTIMER peripheral base address. - * @return none - */ -void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask) -{ - base->OSEVENT_CTRL |= mask; -} - -/*! - * @brief Set the match raw value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is gray-code format) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @return none - */ -void OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) -{ - uint64_t tmp = count; - uint32_t instance = OSTIMER_GetInstance(base); - - s_ostimerIsr = OSTIMER_HandleIRQ; - s_ostimerHandle[instance] = cb; - - /* Set the match value. */ - base->MATCHN_L = tmp; - base->MATCHN_H = tmp >> 32U; - - /* - * Enable deep sleep IRQ directly for some times the OS timer may run in deep sleep mode. - * Please note that while enabling deep sleep IRQ, the NVIC will be also enabled. - */ - base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; - PMC->OSTIMERr |= PMC_OSTIMER_DPDWAKEUPENABLE_MASK; - EnableDeepSleepIRQ(s_ostimerIRQ[instance]); -} - -/*! - * @brief Set the match value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code in - * API. ) - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @return none - */ -void OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) -{ - uint64_t tmp = OSTIMER_DecimalToGray(count); - - OSTIMER_SetMatchRawValue(base, tmp, cb); -} - -/*! - * @brief Get current timer count value from OSTIMER. - * - * This function will get a decimal timer count value. - * The RAW value of timer count is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of OSTIMER which will formated to decimal value. - */ -uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = OSTIMER_GetCurrentTimerRawValue(base); - - return OSTIMER_GrayToDecimal(tmp); -} - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a capture decimal-value from OSTIMER. - * The RAW value of timer capture is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of capture register, data format is decimal. - */ -uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = OSTIMER_GetCaptureRawValue(base); - - return OSTIMER_GrayToDecimal(tmp); -} - -void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb) -{ - /* Clear the match interrupt flag. */ - OSTIMER_ClearStatusFlags(base, kOSTIMER_MatchInterruptFlag); - - if (cb) - { - cb(); - } -} - -#if defined(OSTIMER) -void OS_EVENT_DriverIRQHandler(void) -{ - s_ostimerIsr(OSTIMER, s_ostimerHandle[0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_ostimer.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_ostimer.h deleted file mode 100644 index a65848089a..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_ostimer.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_OSTIMER_H_ -#define _FSL_OSTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ostimer - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief OSTIMER driver version 2.0.0. */ -#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! - * @brief OSTIMER status flags. - */ -enum _ostimer_flags -{ - kOSTIMER_MatchInterruptFlag = (OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK), /*!< Match interrupt flag bit, sets if - the match value was reached. */ -}; - -/*! @brief ostimer callback function. */ -typedef void (*ostimer_callback_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! -* @brief Initializes an OSTIMER by turning its bus clock on -* -*/ -void OSTIMER_Init(OSTIMER_Type *base); - -/*! - * @brief Deinitializes a OSTIMER instance. - * - * This function shuts down OSTIMER bus clock - * - * @param base OSTIMER peripheral base address. - */ -void OSTIMER_Deinit(OSTIMER_Type *base); - -/*! - * @brief OSTIMER software reset. - * - * This function will use software to trigger an OSTIMER reset. - * Please note that, the OS timer reset bit was in PMC->OSTIMERr register. - * - * @param base OSTIMER peripheral base address. - */ -static inline void OSTIMER_SoftwareReset(OSTIMER_Type *base) -{ - PMC->OSTIMERr |= PMC_OSTIMER_SOFTRESET_MASK; - PMC->OSTIMERr &= ~PMC_OSTIMER_SOFTRESET_MASK; -} - -/*! - * @brief Get OSTIMER status Flags. - * - * This returns the status flag. - * Currently, only match interrupt flag can be got. - * - * @param base OSTIMER peripheral base address. - * @return status register value - */ -uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base); - -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intrrupt status flag. - * Currently, only match interrupt flag can be cleared. - * - * @param base OSTIMER peripheral base address. - * @return none - */ -void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask); - -/*! - * @brief Set the match raw value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. - * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is gray-code format) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @return none - */ -void OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); - -/*! - * @brief Set the match value for OSTIMER. - * - * This function will set a match value for OSTIMER with an optional callback. And this callback - * will be called while the data in dedicated pair match register is equals to the value of central OS TIMER. - * - * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code - * internally.) - * - * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @return none - */ -void OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); - -/*! - * @brief Get current timer raw count value from OSTIMER. - * - * This function will get a gray code type timer count value from OS timer register. - * The raw value of timer count is gray code format. - * - * @param base OSTIMER peripheral base address. - * @return Raw value of OSTIMER, gray code format. - */ -static inline uint64_t OSTIMER_GetCurrentTimerRawValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = base->EVTIMERL; - tmp |= (uint64_t)(base->EVTIMERH) << 32U; - - return tmp; -} - -/*! - * @brief Get current timer count value from OSTIMER. - * - * This function will get a decimal timer count value. - * The RAW value of timer count is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of OSTIMER which will be formated to decimal value. - */ -uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base); - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a captured gray-code value from OSTIMER. - * The Raw value of timer capture is gray code format. - * - * @param base OSTIMER peripheral base address. - * @return Raw value of capture register, data format is gray code. - */ -static inline uint64_t OSTIMER_GetCaptureRawValue(OSTIMER_Type *base) -{ - uint64_t tmp = 0U; - - tmp = base->CAPTUREN_L; - tmp |= (uint64_t)(base->CAPTUREN_H) << 32U; - - return tmp; -} - -/*! - * @brief Get the capture value from OSTIMER. - * - * This function will get a capture decimal-value from OSTIMER. - * The RAW value of timer capture is gray code format, will be translated to decimal data internally. - * - * @param base OSTIMER peripheral base address. - * @return Value of capture register, data format is decimal. - */ -uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base); - -/*! - * @brief OS timer interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in OSTIMER_SetMatchValue()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * @param base OS timer peripheral base address. - * @param cb callback scheduled for this instance of OS timer - * @return none - */ -void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb); -/*! - * @} - */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* _FSL_OSTIMER_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_pint.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_pint.c deleted file mode 100644 index 9dde3ab779..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_pint.c +++ /dev/null @@ -1,805 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_pint.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.pint" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Irq number array */ -static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; -/*! @brief Callback function array for PINT(s). */ -static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initialize PINT peripheral. - - * This function initializes the PINT peripheral and enables the clock. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_Init(PINT_Type *base) -{ - uint32_t i; - uint32_t pmcfg; - - assert(base); - - pmcfg = 0; - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - - if (base == SECPINT) - { - /* Disable all bit slices for secure pint*/ - for (i = 0; i < SEC_PINT_PIN_INT_COUNT; i++) - { - pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); - } - } - else - { - /* Disable all bit slices for pint*/ - for (i = 0; i < PINT_PIN_INT_COUNT; i++) - { - pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); - } - } -#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_GpioInt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio_Sec); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#else - /* if need config SECURE PINT device,then enable secure pint interrupt clock */ - if (base == SECPINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio_sec_Int); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } - else - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Pint); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } -#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE && FSL_FEATURE_CLOCK_HAS_NO_GPIOINT_CLOCK_SOURCE*/ - - /* Disable all pattern match bit slices */ - base->PMCFG = pmcfg; -} - -/*! - * brief Configure PINT peripheral pin interrupt. - - * This function configures a given pin interrupt. - * - * param base Base address of the PINT peripheral. - * param intr Pin interrupt. - * param enable Selects detection logic. - * param callback Callback. - * - * retval None. - */ -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) -{ - assert(base); - - /* Clear Rise and Fall flags first */ - PINT_PinInterruptClrRiseFlag(base, intr); - PINT_PinInterruptClrFallFlag(base, intr); - - /* select level or edge sensitive */ - base->ISEL = (base->ISEL & ~(1U << intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1U << intr) : 0U); - - /* enable rising or level interrupt */ - if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) - { - base->SIENR = 1U << intr; - } - else - { - base->CIENR = 1U << intr; - } - - /* Enable falling or select high level */ - if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) - { - base->SIENF = 1U << intr; - } - else - { - base->CIENF = 1U << intr; - } - /* Handle secure pint interrupt*/ - if ((base == SECPINT) && (intr == kPINT_PinInt0)) - { - intr = kPINT_SecPinInt0; - } - else if ((base == SECPINT) && (intr == kPINT_PinInt1)) - { - intr = kPINT_SecPinInt1; - } - s_pintCallback[intr] = callback; -} - -/*! - * brief Get PINT peripheral pin interrupt configuration. - - * This function returns the configuration of a given pin interrupt. - * - * param base Base address of the PINT peripheral. - * param pintr Pin interrupt. - * param enable Pointer to store the detection logic. - * param callback Callback. - * - * retval None. - */ -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) -{ - uint32_t mask; - bool level; - - assert(base); - - *enable = kPINT_PinIntEnableNone; - level = false; - - mask = 1U << pintr; - if (base->ISEL & mask) - { - /* Pin interrupt is level sensitive */ - level = true; - } - - if (base->IENR & mask) - { - if (level) - { - /* Level interrupt is enabled */ - *enable = kPINT_PinIntEnableLowLevel; - } - else - { - /* Rising edge interrupt */ - *enable = kPINT_PinIntEnableRiseEdge; - } - } - - if (base->IENF & mask) - { - if (level) - { - /* Level interrupt is active high */ - *enable = kPINT_PinIntEnableHighLevel; - } - else - { - /* Either falling or both edge */ - if (*enable == kPINT_PinIntEnableRiseEdge) - { - /* Rising and faling edge */ - *enable = kPINT_PinIntEnableBothEdges; - } - else - { - /* Falling edge */ - *enable = kPINT_PinIntEnableFallEdge; - } - } - } - - *callback = s_pintCallback[pintr]; -} - -/*! - * brief Configure PINT pattern match. - - * This function configures a given pattern match bit slice. - * - * param base Base address of the PINT peripheral. - * param bslice Pattern match bit slice number. - * param cfg Pointer to bit slice configuration. - * - * retval None. - */ -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - uint32_t pmcfg; - - assert(base); - - src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U); - cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U); - - /* Input source selection for selected bit slice */ - base->PMSRC = (base->PMSRC & ~(PININT_BITSLICE_SRC_MASK << src_shift)) | (cfg->bs_src << src_shift); - - /* Bit slice configuration */ - pmcfg = base->PMCFG; - pmcfg = (pmcfg & ~(PININT_BITSLICE_CFG_MASK << cfg_shift)) | (cfg->bs_cfg << cfg_shift); - - /* If end point is true, enable the bits */ - if (bslice != 7U) - { - if (cfg->end_point) - { - pmcfg |= (0x1U << bslice); - } - else - { - pmcfg &= ~(0x1U << bslice); - } - } - - base->PMCFG = pmcfg; - /* Handle secure pint pattern match*/ - if ((base == SECPINT) && (bslice == kPINT_PatternMatchBSlice0)) - { - bslice = kSECPINT_PatternMatchBSlice0; - } - else if ((base == SECPINT) && (bslice == kPINT_PatternMatchBSlice1)) - { - bslice = kSECPINT_PatternMatchBSlice1; - } - /* Save callback pointer */ - s_pintCallback[bslice] = cfg->callback; -} - -/*! - * brief Get PINT pattern match configuration. - - * This function returns the configuration of a given pattern match bit slice. - * - * param base Base address of the PINT peripheral. - * param bslice Pattern match bit slice number. - * param cfg Pointer to bit slice configuration. - * - * retval None. - */ -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - - assert(base); - - src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U); - cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U); - - cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (PININT_BITSLICE_SRC_MASK << src_shift)) >> src_shift); - cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (PININT_BITSLICE_CFG_MASK << cfg_shift)) >> cfg_shift); - - if (bslice == 7U) - { - cfg->end_point = true; - } - else - { - cfg->end_point = (base->PMCFG & (0x1U << bslice)) >> bslice; - } - cfg->callback = s_pintCallback[bslice]; -} - -/*! - * brief Reset pattern match detection logic. - - * This function resets the pattern match detection logic if any of the product term is matching. - * - * param base Base address of the PINT peripheral. - * - * retval pmstatus Each bit position indicates the match status of corresponding bit slice. - * = 0 Match was detected. = 1 Match was not detected. - */ -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) -{ - uint32_t pmctrl; - uint32_t pmstatus; - uint32_t pmsrc; - - pmctrl = base->PMCTRL; - pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT; - if (pmstatus) - { - /* Reset Pattern match engine detection logic */ - pmsrc = base->PMSRC; - base->PMSRC = pmsrc; - } - return (pmstatus); -} - -/*! - * brief Enable callback. - - * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_EnableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base); - - PINT_PinInterruptClrStatusAll(base); - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - EnableIRQ(s_pintIRQ[i]); - } -} - -/*! - * brief enable callback by pin index. - - * This function enables callback by pin index instead of enabling all pins. - * - * param base Base address of the peripheral. - * param pinIdx pin index. - * - * retval None. - */ -void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) -{ - assert(base); - - if (base == SECPINT) - { - pintIdx += 8; - } - NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - EnableIRQ(s_pintIRQ[pintIdx]); -} - -/*! - * brief Disable callback. - - * This function disables the interrupt for the selected PINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * param base Base address of the peripheral. - * - * retval None. - */ -void PINT_DisableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base); - - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - DisableIRQ(s_pintIRQ[i]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - } -} - -/*! - * brief disable callback by pin index. - - * This function disables callback by pin index instead of disabling all pins. - * - * param base Base address of the peripheral. - * param pinIdx pin index. - * - * retval None. - */ -void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) -{ - assert(base); - - if (base == SECPINT) - { - pintIdx += 8; - } - DisableIRQ(s_pintIRQ[pintIdx]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); -} -/*! - * brief Deinitialize PINT peripheral. - - * This function disables the PINT clock. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_Deinit(PINT_Type *base) -{ - uint32_t i; - - assert(base); - - /* Cleanup */ - PINT_DisableCallback(base); - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - -#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_GpioInt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio_Sec); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#else - if (base == SECPINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio_sec_Int); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - } - else - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_Pint); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - } -#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ -} - -/* IRQ handler functions overloading weak symbols in the startup */ -void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) -{ - uint32_t pmstatus = 0; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); - /* Call user function */ - if (s_pintCallback[kPINT_SecPinInt0] != NULL) - { - s_pintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus); - } - if ((SECPINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) -/* IRQ handler functions overloading weak symbols in the startup */ -void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); - /* Call user function */ - if (s_pintCallback[kPINT_SecPinInt1] != NULL) - { - s_pintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus); - } - if ((SECPINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -/* IRQ handler functions overloading weak symbols in the startup */ -void PIN_INT0_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt0] != NULL) - { - s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); - } - if ((PINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) -void PIN_INT1_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt1] != NULL) - { - s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); - } - if ((PINT->ISEL & 0x2U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) -void PIN_INT2_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt2] != NULL) - { - s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); - } - if ((PINT->ISEL & 0x4U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) -void PIN_INT3_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt3] != NULL) - { - s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); - } - if ((PINT->ISEL & 0x8U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) -void PIN_INT4_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt4] != NULL) - { - s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); - } - if ((PINT->ISEL & 0x10U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT5_DAC1_IRQHandler(void) -#else -void PIN_INT5_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt5] != NULL) - { - s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); - } - if ((PINT->ISEL & 0x20U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT6_USART3_IRQHandler(void) -#else -void PIN_INT6_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt6] != NULL) - { - s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); - } - if ((PINT->ISEL & 0x40U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT7_USART4_IRQHandler(void) -#else -void PIN_INT7_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt7] != NULL) - { - s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); - } - if ((PINT->ISEL & 0x80U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_pint.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_pint.h deleted file mode 100644 index b8f5692508..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_pint.h +++ /dev/null @@ -1,585 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_PINT_H_ -#define _FSL_PINT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup pint_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) /*!< Version 2.0.4 */ -/*@}*/ - -/* Number of interrupt line supported by PINT */ -#define PINT_PIN_INT_COUNT 8U - -/* Number of interrupt line supported by SECURE PINT */ -#define SEC_PINT_PIN_INT_COUNT 2U - -/* Number of input sources supported by PINT */ -#define PINT_INPUT_COUNT 8U - -/* PININT Bit slice source register bits */ -#define PININT_BITSLICE_SRC_START 8U -#define PININT_BITSLICE_SRC_MASK 7U - -/* PININT Bit slice configuration register bits */ -#define PININT_BITSLICE_CFG_START 8U -#define PININT_BITSLICE_CFG_MASK 7U -#define PININT_BITSLICE_ENDP_MASK 7U - -#define PINT_PIN_INT_LEVEL 0x10U -#define PINT_PIN_INT_EDGE 0x00U -#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U -#define PINT_PIN_INT_RISE 0x01U -#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) -#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) -#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) - -/*! @brief PINT Pin Interrupt enable type */ -typedef enum _pint_pin_enable -{ - kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ - kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ - kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ - kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */ - kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ - kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */ -} pint_pin_enable_t; - -/*! @brief PINT Pin Interrupt type */ -typedef enum _pint_int -{ - kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */ -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ -#endif -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) - kPINT_SecPinInt0 = 8U, /*!< Secure Pin Interrupt 0 */ -#endif -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_SecPinInt1 = 9U, /*!< Secure Pin Interrupt 1 */ -#endif -} pint_pin_int_t; - -/*! @brief PINT Pattern Match bit slice input source type */ -typedef enum _pint_pmatch_input_src -{ - kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ - kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ - kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ - kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ - kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ - kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ - kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ - kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ -} pint_pmatch_input_src_t; - -/*! @brief PINT Pattern Match bit slice type */ -typedef enum _pint_pmatch_bslice -{ - kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ -#endif -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) - kSECPINT_PatternMatchBSlice0 = 8U, /*!< Bit slice 0 */ -#endif -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kSECPINT_PatternMatchBSlice1 = 9U, /*!< Bit slice 1 */ -#endif -} pint_pmatch_bslice_t; - -/*! @brief PINT Pattern Match configuration type */ -typedef enum _pint_pmatch_bslice_cfg -{ - kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ - kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ - kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ - kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */ - kPINT_PatternMatchHigh = 4U, /*!< High level */ - kPINT_PatternMatchLow = 5U, /*!< Low level */ - kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ - kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ -} pint_pmatch_bslice_cfg_t; - -/*! @brief PINT Callback function. */ -typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status); - -typedef struct _pint_pmatch_cfg -{ - pint_pmatch_input_src_t bs_src; - pint_pmatch_bslice_cfg_t bs_cfg; - bool end_point; - pint_cb_t callback; -} pint_pmatch_cfg_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize PINT peripheral. - - * This function initializes the PINT peripheral and enables the clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Init(PINT_Type *base); - -/*! - * @brief Configure PINT peripheral pin interrupt. - - * This function configures a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param intr Pin interrupt. - * @param enable Selects detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback); - -/*! - * @brief Get PINT peripheral pin interrupt configuration. - - * This function returns the configuration of a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * @param enable Pointer to store the detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback); - -/*! - * @brief Clear Selected pin interrupt status. - - * This function clears the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - base->IST = (1U << pintr); -} - -/*! - * @brief Get Selected pin interrupt status. - - * This function returns the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval status = 0 No pin interrupt request. = 1 Selected Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->IST & (1U << pintr)) ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupts status. - - * This function clears the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrStatusAll(PINT_Type *base) -{ - base->IST = PINT_IST_PSTAT_MASK; -} - -/*! - * @brief Get all pin interrupts status. - - * This function returns the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the status of corresponding pin interrupt. - * = 0 No pin interrupt request. = 1 Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base) -{ - return (base->IST); -} - -/*! - * @brief Clear Selected pin interrupt fall flag. - - * This function clears the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->FALL = (1U << pintr); -} - -/*! - * @brief Get selected pin interrupt fall flag. - - * This function returns the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->FALL & (1U << pintr)) ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt fall flags. - - * This function clears the fall flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base) -{ - base->FALL = PINT_FALL_FDET_MASK; -} - -/*! - * @brief Get all pin interrupt fall flags. - - * This function returns the fall flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt. - * 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base) -{ - return (base->FALL); -} - -/*! - * @brief Clear Selected pin interrupt rise flag. - - * This function clears the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->RISE = (1U << pintr); -} - -/*! - * @brief Get selected pin interrupt rise flag. - - * This function returns the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->RISE & (1U << pintr)) ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt rise flags. - - * This function clears the rise flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base) -{ - base->RISE = PINT_RISE_RDET_MASK; -} - -/*! - * @brief Get all pin interrupt rise flags. - - * This function returns the rise flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt. - * 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) -{ - return (base->RISE); -} - -/*! - * @brief Configure PINT pattern match. - - * This function configures a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get PINT pattern match configuration. - - * This function returns the configuration of a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get pattern match bit slice status. - - * This function returns the status of selected bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * - * @retval status = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice) -{ - return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (0x1U << bslice)) >> bslice; -} - -/*! - * @brief Get status of all pattern match bit slices. - - * This function returns the status of all bit slices. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the match status of corresponding bit slice. - * = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) -{ - return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT; -} - -/*! - * @brief Reset pattern match detection logic. - - * This function resets the pattern match detection logic if any of the product term is matching. - * - * @param base Base address of the PINT peripheral. - * - * @retval pmstatus Each bit position indicates the match status of corresponding bit slice. - * = 0 Match was detected. = 1 Match was not detected. - */ -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base); - -/*! - * @brief Enable pattern match function. - - * This function enables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Disable pattern match function. - - * This function disables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Enable RXEV output. - - * This function enables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Disable RXEV output. - - * This function disables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_EnableCallback(PINT_Type *base); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected PINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * @param base Base address of the peripheral. - * - * @retval None. - */ -void PINT_DisableCallback(PINT_Type *base); - -/*! - * @brief Deinitialize PINT peripheral. - - * This function disables the PINT clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Deinit(PINT_Type *base); - -/*! - * @brief enable callback by pin index. - - * This function enables callback by pin index instead of enabling all pins. - * - * @param base Base address of the peripheral. - * @param pinIdx pin index. - * - * @retval None. - */ -void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); - -/*! - * @brief disable callback by pin index. - - * This function disables callback by pin index instead of disabling all pins. - * - * @param base Base address of the peripheral. - * @param pinIdx pin index. - * - * @retval None. - */ -void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_PINT_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_plu.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_plu.c deleted file mode 100644 index ef65b4e5a2..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_plu.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2018, NXP Semiconductors, Inc. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_plu.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.plu" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Gets the instance from the base address - * - * @param base PLU peripheral base address - * - * @return The PLU instance - */ -static uint32_t PLU_GetInstance(PLU_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to PLU bases for each instance. */ -static PLU_Type *const s_pluBases[] = PLU_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to PLU clocks for each instance. */ -static const clock_ip_name_t s_pluClocks[] = PLU_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/*! @brief Pointers to PLU resets for each instance. */ -static const reset_ip_name_t s_lpuResets[] = PLU_RSTS_N; -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t PLU_GetInstance(PLU_Type *base) -{ - uint32_t instance; - uint32_t pluArrayCount = (sizeof(s_pluBases) / sizeof(s_pluBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < pluArrayCount; instance++) - { - if (s_pluBases[instance] == base) - { - break; - } - } - - assert(instance < pluArrayCount); - - return instance; -} - -/*! - * brief Ungates the PLU clock and reset the module. - * - * note This API should be called at the beginning of the application using the PLU driver. - * - * param base PLU peripheral base address - */ -void PLU_Init(PLU_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the PLU peripheral clock */ - CLOCK_EnableClock(s_pluClocks[PLU_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_lpuResets[PLU_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -} - -/*! - * brief Gate the PLU clock - * - * param base PLU peripheral base address - */ -void PLU_Deinit(PLU_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the module clock */ - CLOCK_DisableClock((s_pluClocks[PLU_GetInstance(base)])); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_plu.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_plu.h deleted file mode 100644 index 7be1d53062..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_plu.h +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Copyright (c) 2018, NXP Semiconductors, Inc. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_PLU_H_ -#define _FSL_PLU_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup plu - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PLU_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ - /*@}*/ - -/*! @brief Index of LUT */ -typedef enum _plu_lut_index -{ - kPLU_LUT_0 = 0U, /*!< 5-input Look-up Table 0 */ - kPLU_LUT_1 = 1U, /*!< 5-input Look-up Table 1 */ - kPLU_LUT_2 = 2U, /*!< 5-input Look-up Table 2 */ - kPLU_LUT_3 = 3U, /*!< 5-input Look-up Table 3 */ - kPLU_LUT_4 = 4U, /*!< 5-input Look-up Table 4 */ - kPLU_LUT_5 = 5U, /*!< 5-input Look-up Table 5 */ - kPLU_LUT_6 = 6U, /*!< 5-input Look-up Table 6 */ - kPLU_LUT_7 = 7U, /*!< 5-input Look-up Table 7 */ - kPLU_LUT_8 = 8U, /*!< 5-input Look-up Table 8 */ - kPLU_LUT_9 = 9U, /*!< 5-input Look-up Table 9 */ - kPLU_LUT_10 = 10U, /*!< 5-input Look-up Table 10 */ - kPLU_LUT_11 = 11U, /*!< 5-input Look-up Table 11 */ - kPLU_LUT_12 = 12U, /*!< 5-input Look-up Table 12 */ - kPLU_LUT_13 = 13U, /*!< 5-input Look-up Table 13 */ - kPLU_LUT_14 = 14U, /*!< 5-input Look-up Table 14 */ - kPLU_LUT_15 = 15U, /*!< 5-input Look-up Table 15 */ - kPLU_LUT_16 = 16U, /*!< 5-input Look-up Table 16 */ - kPLU_LUT_17 = 17U, /*!< 5-input Look-up Table 17 */ - kPLU_LUT_18 = 18U, /*!< 5-input Look-up Table 18 */ - kPLU_LUT_19 = 19U, /*!< 5-input Look-up Table 19 */ - kPLU_LUT_20 = 20U, /*!< 5-input Look-up Table 20 */ - kPLU_LUT_21 = 21U, /*!< 5-input Look-up Table 21 */ - kPLU_LUT_22 = 22U, /*!< 5-input Look-up Table 22 */ - kPLU_LUT_23 = 23U, /*!< 5-input Look-up Table 23 */ - kPLU_LUT_24 = 24U, /*!< 5-input Look-up Table 24 */ - kPLU_LUT_25 = 25U /*!< 5-input Look-up Table 25 */ -} plu_lut_index_t; - -/*! @brief Inputs of LUT. 5 input present for each LUT. */ -typedef enum _plu_lut_in_index -{ - kPLU_LUT_IN_0 = 0U, /*!< LUT input 0 */ - kPLU_LUT_IN_1 = 1U, /*!< LUT input 1 */ - kPLU_LUT_IN_2 = 2U, /*!< LUT input 2 */ - kPLU_LUT_IN_3 = 3U, /*!< LUT input 3 */ - kPLU_LUT_IN_4 = 4U /*!< LUT input 4 */ -} plu_lut_in_index_t; - -/*! @brief Available sources of LUT input */ -typedef enum _plu_lut_input_source -{ - kPLU_LUT_IN_SRC_PLU_IN_0 = 0U, /*!< Select PLU input 0 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_1 = 1U, /*!< Select PLU input 1 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_2 = 2U, /*!< Select PLU input 2 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_3 = 3U, /*!< Select PLU input 3 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_4 = 4U, /*!< Select PLU input 4 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_PLU_IN_5 = 5U, /*!< Select PLU input 5 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_0 = 6U, /*!< Select LUT output 0 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_1 = 7U, /*!< Select LUT output 1 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_2 = 8U, /*!< Select LUT output 2 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_3 = 9U, /*!< Select LUT output 3 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_4 = 10U, /*!< Select LUT output 4 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_5 = 11U, /*!< Select LUT output 5 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_6 = 12U, /*!< Select LUT output 6 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_7 = 13U, /*!< Select LUT output 7 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_8 = 14U, /*!< Select LUT output 8 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_9 = 15U, /*!< Select LUT output 9 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_10 = 16U, /*!< Select LUT output 10 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_11 = 17U, /*!< Select LUT output 11 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_12 = 18U, /*!< Select LUT output 12 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_13 = 19U, /*!< Select LUT output 13 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_14 = 20U, /*!< Select LUT output 14 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_15 = 21U, /*!< Select LUT output 15 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_16 = 22U, /*!< Select LUT output 16 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_17 = 23U, /*!< Select LUT output 17 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_18 = 24U, /*!< Select LUT output 18 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_19 = 25U, /*!< Select LUT output 19 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_20 = 26U, /*!< Select LUT output 20 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_21 = 27U, /*!< Select LUT output 21 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_22 = 28U, /*!< Select LUT output 22 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_23 = 29U, /*!< Select LUT output 23 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_24 = 30U, /*!< Select LUT output 24 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_LUT_OUT_25 = 31U, /*!< Select LUT output 25 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_0 = 32U, /*!< Select Flip-Flops state 0 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_1 = 33U, /*!< Select Flip-Flops state 1 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_2 = 34U, /*!< Select Flip-Flops state 2 to be connected to LUTn Input x */ - kPLU_LUT_IN_SRC_FLIPFLOP_3 = 35U /*!< Select Flip-Flops state 3 to be connected to LUTn Input x */ -} plu_lut_input_source_t; - -/*! @brief PLU output multiplexer registers */ -typedef enum _plu_output_index -{ - kPLU_OUTPUT_0 = 0U, /*!< PLU OUTPUT 0 */ - kPLU_OUTPUT_1 = 1U, /*!< PLU OUTPUT 1 */ - kPLU_OUTPUT_2 = 2U, /*!< PLU OUTPUT 2 */ - kPLU_OUTPUT_3 = 3U, /*!< PLU OUTPUT 3 */ - kPLU_OUTPUT_4 = 4U, /*!< PLU OUTPUT 4 */ - kPLU_OUTPUT_5 = 5U, /*!< PLU OUTPUT 5 */ - kPLU_OUTPUT_6 = 6U, /*!< PLU OUTPUT 6 */ - kPLU_OUTPUT_7 = 7U /*!< PLU OUTPUT 7 */ -} plu_output_index_t; - -/*! @brief Available sources of PLU output */ -typedef enum _plu_output_source -{ - kPLU_OUT_SRC_LUT_0 = 0U, /*!< Select LUT0 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_1 = 1U, /*!< Select LUT1 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_2 = 2U, /*!< Select LUT2 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_3 = 3U, /*!< Select LUT3 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_4 = 4U, /*!< Select LUT4 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_5 = 5U, /*!< Select LUT5 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_6 = 6U, /*!< Select LUT6 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_7 = 7U, /*!< Select LUT7 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_8 = 8U, /*!< Select LUT8 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_9 = 9U, /*!< Select LUT9 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_10 = 10U, /*!< Select LUT10 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_11 = 11U, /*!< Select LUT11 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_12 = 12U, /*!< Select LUT12 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_13 = 13U, /*!< Select LUT13 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_14 = 14U, /*!< Select LUT14 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_15 = 15U, /*!< Select LUT15 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_16 = 16U, /*!< Select LUT16 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_17 = 17U, /*!< Select LUT17 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_18 = 18U, /*!< Select LUT18 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_19 = 19U, /*!< Select LUT19 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_20 = 20U, /*!< Select LUT20 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_21 = 21U, /*!< Select LUT21 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_22 = 22U, /*!< Select LUT22 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_23 = 23U, /*!< Select LUT23 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_24 = 24U, /*!< Select LUT24 output to be connected to PLU output */ - kPLU_OUT_SRC_LUT_25 = 25U, /*!< Select LUT25 output to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_0 = 26U, /*!< Select Flip-Flops state(0) to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_1 = 27U, /*!< Select Flip-Flops state(1) to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_2 = 28U, /*!< Select Flip-Flops state(2) to be connected to PLU output */ - kPLU_OUT_SRC_FLIPFLOP_3 = 29U /*!< Select Flip-Flops state(3) to be connected to PLU output */ -} plu_output_source_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the PLU clock and reset the module. - * - * @note This API should be called at the beginning of the application using the PLU driver. - * - * @param base PLU peripheral base address - */ -void PLU_Init(PLU_Type *base); - -/*! - * @brief Gate the PLU clock - * - * @param base PLU peripheral base address - */ -void PLU_Deinit(PLU_Type *base); - -/*! @}*/ - -/*! - * @name Set input/output source and Truth Table - * @{ - */ - -/*! - * @brief Set Input source of LUT. - * - * Note: An external clock must be applied to the PLU_CLKIN input when using FFs. - * For each LUT, the slot associated with the output from LUTn itself is tied low. - * - * @param base PLU peripheral base address. - * @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration). - * @param lutInIndex LUT input index (see @ref plu_lut_in_index_t typedef enumeration). - * @param inputSrc LUT input source (see @ref plu_lut_input_source_t typedef enumeration). - */ -static inline void PLU_SetLutInputSource(PLU_Type *base, - plu_lut_index_t lutIndex, - plu_lut_in_index_t lutInIndex, - plu_lut_input_source_t inputSrc) -{ - PLU->LUT[lutIndex].INP[lutInIndex] = inputSrc; -} - -/*! - * @brief Set Output source of PLU. - * - * Note: An external clock must be applied to the PLU_CLKIN input when using FFs. - * - * @param base PLU peripheral base address. - * @param outputIndex PLU output index (see @ref plu_output_index_t typedef enumeration). - * @param outputSrc PLU output source (see @ref plu_output_source_t typedef enumeration). - */ -static inline void PLU_SetOutputSource(PLU_Type *base, plu_output_index_t outputIndex, plu_output_source_t outputSrc) -{ - base->OUTPUT_MUX[outputIndex] = outputSrc; -} - -/*! - * @brief Set Truth Table of LUT. - * - * @param base PLU peripheral base address. - * @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration). - * @param truthTable Truth Table value. - */ -static inline void PLU_SetLutTruthTable(PLU_Type *base, plu_lut_index_t lutIndex, uint32_t truthTable) -{ - base->LUT_TRUTH[lutIndex] = truthTable; -} - -/*! @}*/ - -/*! - * @name Read current Output State - * @{ - */ - -/*! - * @brief Read the current state of the 8 designated PLU Outputs. - * - * Note: The PLU bus clock must be re-enabled prior to reading the Outpus Register if PLU bus clock is - * shut-off. - * - * @param base PLU peripheral base address. - * @return Current PLU output state value. - */ -static inline uint32_t PLU_ReadOutputState(PLU_Type *base) -{ - return (base->OUTPUTS & PLU_OUTPUTS_OUTPUT_STATE_MASK); -} - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_PLU_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_power.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_power.c deleted file mode 100644 index b56f4afd7b..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_power.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_common.h" -#include "fsl_power.h" -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.power" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Empty file since implementation is in header file and power library */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_power.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_power.h deleted file mode 100644 index 68cc23bcb2..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_power.h +++ /dev/null @@ -1,724 +0,0 @@ -/* - * Copyright (c) 2017, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_POWER_H_ -#define _FSL_POWER_H_ - -#include "fsl_common.h" -#include "fsl_device_registers.h" -#include - -/*! - * @addtogroup power - * @{ - */ -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief power driver version 1.0.0. */ -#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) -/*@}*/ - - -/** @brief Low Power main structure */ -typedef enum -{ - VD_AON = 0x0, /*!< Digital Always On power domain */ - VD_MEM = 0x1, /*!< Memories (SRAM) power domain */ - VD_DCDC = 0x2, /*!< Core logic power domain */ - VD_DEEPSLEEP = 0x3 /*!< Core logic power domain */ -} LPC_POWER_DOMAIN_T; - -/** @brief Low Power main structure */ -typedef struct -{ /* */ - __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ - __IO uint32_t PDCTRL0; /*!< Power Down control : controls power of various modules - in the different Low power modes, including ROM */ - __IO uint32_t SRAMRETCTRL; /*!< Power Down control : controls power SRAM instances - in the different Low power modes */ - __IO uint32_t CPURETCTRL; /*!< CPU0 retention control : controls CPU retention parameters in POWER DOWN modes */ - __IO uint64_t VOLTAGE; /*!< Voltage control in Low Power Modes */ - __IO uint64_t WAKEUPSRC; /*!< Wake up sources control for sleepcon */ - __IO uint64_t WAKEUPINT; /*!< Wake up sources control for ARM */ - __IO uint32_t HWWAKE; /*!< Interrupt that can postpone power down modes - in case an interrupt is pending when the processor request deepsleep */ - __IO uint32_t WAKEUPIOSRC; /*!< Wake up I/O sources in DEEP POWER DOWN mode */ - __IO uint32_t TIMERCFG; /*!< Wake up timers configuration */ - __IO uint32_t TIMERCOUNT; /*!< Wake up Timer count*/ - __IO uint32_t POWERCYCLE; /*!< Cancels entry in Low Power mode if set with 0xDEADABBA (might be used by some - interrupt handlers)*/ -} LPC_LOWPOWER_T; - -/* */ -#define LOWPOWER_POWERCYCLE_CANCELLED 0xDEADABBA /*!< */ - -/* Low Power modes */ -#define LOWPOWER_CFG_LPMODE_INDEX 0 -#define LOWPOWER_CFG_LPMODE_MASK (0x3UL << LOWPOWER_CFG_LPMODE_INDEX) -#define LOWPOWER_CFG_SELCLOCK_INDEX 2 -#define LOWPOWER_CFG_SELCLOCK_MASK (0x1UL << LOWPOWER_CFG_SELCLOCK_INDEX) -#define LOWPOWER_CFG_SELMEMSUPPLY_INDEX 3 -#define LOWPOWER_CFG_SELMEMSUPPLY_MASK (0x1UL << LOWPOWER_CFG_SELMEMSUPPLY_INDEX) -#define LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX 4 -#define LOWPOWER_CFG_MEMLOWPOWERMODE_MASK (0x1UL << LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX) -#define LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX 5 -#define LOWPOWER_CFG_LDODEEPSLEEPREF_MASK (0x1UL << LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX) - -#define LOWPOWER_CFG_LPMODE_ACTIVE 0 /*!< ACTIVE mode */ -#define LOWPOWER_CFG_LPMODE_DEEPSLEEP 1 /*!< DEEP SLEEP mode */ -#define LOWPOWER_CFG_LPMODE_POWERDOWN 2 /*!< POWER DOWN mode */ -#define LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN 3 /*!< DEEP POWER DOWN mode */ -#define LOWPOWER_CFG_LPMODE_SLEEP 4 /*!< SLEEP mode */ - -#define LOWPOWER_CFG_SELCLOCK_1MHZ 0 /*!< The 1 MHz clock is used during the configuration of the PMC */ -#define LOWPOWER_CFG_SELCLOCK_12MHZ 1 /*!< The 12 MHz clock is used during the configuration of the PMC (to speed up PMC configuration process)*/ - -#define LOWPOWER_CFG_SELMEMSUPPLY_LDOMEM 0 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_MEM */ -#define LOWPOWER_CFG_SELMEMSUPPLY_LDODEEPSLEEP 1 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_DEEP_SLEEP (or DCDC) */ - -#define LOWPOWER_CFG_MEMLOWPOWERMODE_SOURCEBIASING 0 /*!< All SRAM instances use "Source Biasing" as low power mode technic (it is recommended to set LDO_MEM as high as possible -- 1.1V typical -- during low power mode) */ -#define LOWPOWER_CFG_MEMLOWPOWERMODE_VOLTAGESCALING 1 /*!< All SRAM instances use "Voltage Scaling" as low power mode technic (it is recommended to set LDO_MEM as low as possible -- down to 0.7V -- during low power mode) */ - -#define LOWPOWER_CFG_LDODEEPSLEEPREF_FLASHBUFFER 0 /*!< LDO DEEP SLEEP uses Flash Buffer as reference */ -#define LOWPOWER_CFG_LDODEEPSLEEPREF_BANDGAG0P8V 1 /*!< LDO DEEP SLEEP uses Band Gap 0.8V as reference */ - -/* CPU Retention Control*/ -#define LOWPOWER_CPURETCTRL_ENA_INDEX 0 -#define LOWPOWER_CPURETCTRL_ENA_MASK (0x1UL << LOWPOWER_CPURETCTRL_ENA_INDEX) -#define LOWPOWER_CPURETCTRL_MEMBASE_INDEX 1 -#define LOWPOWER_CPURETCTRL_MEMBASE_MASK (0x1FFF << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) -#define LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX 14 -#define LOWPOWER_CPURETCTRL_RETDATALENGTH_MASK (0x3FFUL << LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX) - -#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */ -#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */ - -/** - * @brief Analog components power modes control during low power modes - */ -typedef enum pd_bits -{ - kPDRUNCFG_PD_DCDC = (1UL << 0), - kPDRUNCFG_PD_BIAS = (1UL << 1), - kPDRUNCFG_PD_BODCORE = (1UL << 2), - kPDRUNCFG_PD_BODVBAT = (1UL << 3), - kPDRUNCFG_PD_FRO1M = (1UL << 4), - kPDRUNCFG_PD_FRO192M = (1UL << 5), - kPDRUNCFG_PD_FRO32K = (1UL << 6), - kPDRUNCFG_PD_XTAL32K = (1UL << 7), - kPDRUNCFG_PD_XTAL32M = (1UL << 8), - kPDRUNCFG_PD_PLL0 = (1UL << 9), - kPDRUNCFG_PD_PLL1 = (1UL << 10), - kPDRUNCFG_PD_USB0_PHY = (1UL << 11), - kPDRUNCFG_PD_USB1_PHY = (1UL << 12), - kPDRUNCFG_PD_COMP = (1UL << 13), - kPDRUNCFG_PD_TEMPSENS = (1UL << 14), - kPDRUNCFG_PD_GPADC = (1UL << 15), - kPDRUNCFG_PD_LDOMEM = (1UL << 16), - kPDRUNCFG_PD_LDODEEPSLEEP = (1UL << 17), - kPDRUNCFG_PD_LDOUSBHS = (1UL << 18), - kPDRUNCFG_PD_LDOGPADC = (1UL << 19), - kPDRUNCFG_PD_LDOXO32M = (1UL << 20), - kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21), - kPDRUNCFG_PD_RNG = (1UL << 22), - kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23), - kPDRUNCFG_PD_ROM = (1UL << 24), - - /* - This enum member has no practical meaning,it is used to avoid MISRA issue, - user should not trying to use it. - */ - kPDRUNCFG_ForceUnsigned = 0x80000000U, -} pd_bit_t; - -/** - * @brief SRAM instances retention control during low power modes - */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM01 (1UL << 5) /*!< Enable SRAM0_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM30 (1UL << 8) /*!< Enable SRAM3_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM31 (1UL << 9) /*!< Enable SRAM3_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM40 (1UL << 10) /*!< Enable SRAM4_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM41 (1UL << 11) /*!< Enable SRAM4_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM42 (1UL << 12) /*!< Enable SRAM4_2 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM43 (1UL << 13) /*!< Enable SRAM4_3 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_PUF (1UL << 15) /*!< Enable SRAM PUFF retention when entering in Low power modes */ - -/** - * @brief SRAM Low Power Modes - */ - -#define LOWPOWER_SRAM_LPMODE_MASK (0xFUL) -#define LOWPOWER_SRAM_LPMODE_ACTIVE (0x6UL) /*!< SRAM functional mode */ -#define LOWPOWER_SRAM_LPMODE_SLEEP (0xFUL) /*!< SRAM Sleep mode (Data retention, fast wake up) */ -#define LOWPOWER_SRAM_LPMODE_DEEPSLEEP (0x8UL) /*!< SRAM Deep Sleep mode (Data retention, slow wake up) */ -#define LOWPOWER_SRAM_LPMODE_SHUTDOWN (0x9UL) /*!< SRAM Shut Down mode (no data retention) */ -#define LOWPOWER_SRAM_LPMODE_POWERUP (0xAUL) /*!< SRAM is powering up */ - -/*@brief BOD VBAT level */ -typedef enum _power_bod_vbat_level -{ - kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */ - kPOWER_BodVbatLevel1100mv = 1, /*!< Brown out detector VBAT level 1.1V */ - kPOWER_BodVbatLevel1200mv = 2, /*!< Brown out detector VBAT level 1.2V */ - kPOWER_BodVbatLevel1300mv = 3, /*!< Brown out detector VBAT level 1.3V */ - kPOWER_BodVbatLevel1400mv = 4, /*!< Brown out detector VBAT level 1.4V */ - kPOWER_BodVbatLevel1500mv = 5, /*!< Brown out detector VBAT level 1.5V */ - kPOWER_BodVbatLevel1600mv = 6, /*!< Brown out detector VBAT level 1.6V */ - kPOWER_BodVbatLevel1650mv = 7, /*!< Brown out detector VBAT level 1.65V */ - kPOWER_BodVbatLevel1700mv = 8, /*!< Brown out detector VBAT level 1.7V */ - kPOWER_BodVbatLevel1750mv = 9, /*!< Brown out detector VBAT level 1.75V */ - kPOWER_BodVbatLevel1800mv = 10, /*!< Brown out detector VBAT level 1.8V */ - kPOWER_BodVbatLevel1900mv = 11, /*!< Brown out detector VBAT level 1.9V */ - kPOWER_BodVbatLevel2000mv = 12, /*!< Brown out detector VBAT level 2V */ - kPOWER_BodVbatLevel2100mv = 13, /*!< Brown out detector VBAT level 2.1V */ - kPOWER_BodVbatLevel2200mv = 14, /*!< Brown out detector VBAT level 2.2V */ - kPOWER_BodVbatLevel2300mv = 15, /*!< Brown out detector VBAT level 2.3V */ - kPOWER_BodVbatLevel2400mv = 16, /*!< Brown out detector VBAT level 2.4V */ - kPOWER_BodVbatLevel2500mv = 17, /*!< Brown out detector VBAT level 2.5V */ - kPOWER_BodVbatLevel2600mv = 18, /*!< Brown out detector VBAT level 2.6V */ - kPOWER_BodVbatLevel2700mv = 19, /*!< Brown out detector VBAT level 2.7V */ - kPOWER_BodVbatLevel2806mv = 20, /*!< Brown out detector VBAT level 2.806V */ - kPOWER_BodVbatLevel2900mv = 21, /*!< Brown out detector VBAT level 2.9V */ - kPOWER_BodVbatLevel3000mv = 22, /*!< Brown out detector VBAT level 3.0V */ - kPOWER_BodVbatLevel3100mv = 23, /*!< Brown out detector VBAT level 3.1V */ - kPOWER_BodVbatLevel3200mv = 24, /*!< Brown out detector VBAT level 3.2V */ - kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */ -} power_bod_vbat_level_t; - -/*@brief BOD core level */ -typedef enum _power_bod_core_level -{ - kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */ - kPOWER_BodCoreLevel650mv = 1, /*!< Brown out detector core level 650mV */ - kPOWER_BodCoreLevel700mv = 2, /*!< Brown out detector core level 700mV */ - kPOWER_BodCoreLevel750mv = 3, /*!< Brown out detector core level 750mV */ - kPOWER_BodCoreLevel800mv = 4, /*!< Brown out detector core level 800mV */ - kPOWER_BodCoreLevel850mv = 5, /*!< Brown out detector core level 850mV */ - kPOWER_BodCoreLevel900mv = 6, /*!< Brown out detector core level 900mV */ - kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */ -} power_bod_core_level_t; - -/*@brief BOD Hysteresis control */ -typedef enum _power_bod_hyst -{ - kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */ - kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */ - kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */ - kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */ -} power_bod_hyst_t; - -/** - * @brief LDO Voltage control in Low Power Modes - */ -#define LOWPOWER_VOLTAGE_LDO_PMU_INDEX 0 -#define LOWPOWER_VOLTAGE_LDO_PMU_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) -#define LOWPOWER_VOLTAGE_LDO_MEM_INDEX 5 -#define LOWPOWER_VOLTAGE_LDO_MEM_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) -#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX 10 -#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_MASK (0x7ULL << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) -#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX 19 -#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) -#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX 24 -#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) -#define LOWPOWER_VOLTAGE_DCDC_INDEX 29 -#define LOWPOWER_VOLTAGE_DCDC_MASK (0xFULL << LOWPOWER_VOLTAGE_DCDC_INDEX) - -/** - * @brief Always On and Memories LDO voltage settings - */ - -typedef enum _v_ao -{ - // V_AO_1P220 1.22 = 0, /*!< 1.22 V */ - V_AO_0P700 = 1, /*!< 0.7 V */ - V_AO_0P725 = 2, /*!< 0.725 V */ - V_AO_0P750 = 3, /*!< 0.75 V */ - V_AO_0P775 = 4, /*!< 0.775 V */ - V_AO_0P800 = 5, /*!< 0.8 V */ - V_AO_0P825 = 6, /*!< 0.825 V */ - V_AO_0P850 = 7, /*!< 0.85 V */ - V_AO_0P875 = 8, /*!< 0.875 V */ - V_AO_0P900 = 9, /*!< 0.9 V */ - V_AO_0P960 = 10, /*!< 0.96 V */ - V_AO_0P970 = 11, /*!< 0.97 V */ - V_AO_0P980 = 12, /*!< 0.98 V */ - V_AO_0P990 = 13, /*!< 0.99 V */ - V_AO_1P000 = 14, /*!< 1 V */ - V_AO_1P010 = 15, /*!< 1.01 V */ - V_AO_1P020 = 16, /*!< 1.02 V */ - V_AO_1P030 = 17, /*!< 1.03 V */ - V_AO_1P040 = 18, /*!< 1.04 V */ - V_AO_1P050 = 19, /*!< 1.05 V */ - V_AO_1P060 = 20, /*!< 1.06 V */ - V_AO_1P070 = 21, /*!< 1.07 V */ - V_AO_1P080 = 22, /*!< 1.08 V */ - V_AO_1P090 = 23, /*!< 1.09 V */ - V_AO_1P100 = 24, /*!< 1.1 V */ - V_AO_1P110 = 25, /*!< 1.11 V */ - V_AO_1P120 = 26, /*!< 1.12 V */ - V_AO_1P130 = 27, /*!< 1.13 V */ - V_AO_1P140 = 28, /*!< 1.14 V */ - V_AO_1P150 = 29, /*!< 1.15 V */ - V_AO_1P160 = 30, /*!< 1.16 V */ - V_AO_1P220 = 31 /*!< 1.22 V */ -} v_ao_t; - -/** - * @brief Deep Sleep LDO voltage settings - */ -typedef enum _v_deepsleep -{ - V_DEEPSLEEP_0P900 = 0, /*!< 0.9 V */ - V_DEEPSLEEP_0P925 = 1, /*!< 0.925 V */ - V_DEEPSLEEP_0P950 = 2, /*!< 0.95 V */ - V_DEEPSLEEP_0P975 = 3, /*!< 0.975 V */ - V_DEEPSLEEP_1P000 = 4, /*!< 1.000 V */ - V_DEEPSLEEP_1P025 = 5, /*!< 1.025 V */ - V_DEEPSLEEP_1P050 = 6, /*!< 1.050 V */ - V_DEEPSLEEP_1P075 = 7 /*!< 1.075 V */ -} v_deepsleep_t; - -/** - * @brief DCDC voltage settings - */ -typedef enum _v_dcdc -{ - V_DCDC_0P950 = 0, /*!< 0.95 V */ - V_DCDC_0P975 = 1, /*!< 0.975 V */ - V_DCDC_1P000 = 2, /*!< 1 V */ - V_DCDC_1P025 = 3, /*!< 1.025 V */ - V_DCDC_1P050 = 4, /*!< 1.050 V */ - V_DCDC_1P075 = 5, /*!< 1.075 V */ - V_DCDC_1P100 = 6, /*!< 1.1 V */ - V_DCDC_1P125 = 7, /*!< 1.125 V */ - V_DCDC_1P150 = 8, /*!< 1.150 V */ - V_DCDC_1P175 = 9, /*!< 1.175 V */ - V_DCDC_1P200 = 10 /*!< 1.2 V */ -} v_dcdc_t; -/** - * @brief LDO_FLASH_NV & LDO_USB voltage settings - */ -typedef enum _v_flashnv -{ - V_LDOFLASHNV_1P650 = 0, /*!< 0.95 V */ - V_LDOFLASHNV_1P700 = 1, /*!< 0.975 V */ - V_LDOFLASHNV_1P750 = 2, /*!< 1 V */ - V_LDOFLASHNV_0P800 = 3, /*!< 1.025 V */ - V_LDOFLASHNV_1P850 = 4, /*!< 1.050 V */ - V_LDOFLASHNV_1P900 = 5, /*!< 1.075 V */ - V_LDOFLASHNV_1P950 = 6, /*!< 1.1 V */ - V_LDOFLASHNV_2P000 = 7 /*!< 1.125 V */ -} v_flashnv_t; - -/** - * @brief Low Power Modes Wake up sources - */ - -#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/ -#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */ -#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */ -#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */ -#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */ -// reserved (1ULL << 23) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_ACMP_CAPT (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -// reserved (1ULL << 25) -// reserved (1ULL << 26) -#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ -#define WAKEUP_EZH_ARCH_B (1ULL << 30) /*!< [SLEEP, ] */ -#define WAKEUP_WAKEUP_MAILBOX (1ULL << 31) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ -// reserved (1ULL << 39) -// reserved (1ULL << 40) -// reserved (1ULL << 41) -#define WAKEUP_SDIO (1ULL << 42) /*!< [SLEEP, ] */ -// reserved (1ULL << 43) -// reserved (1ULL << 44) -// reserved (1ULL << 45) -// reserved (1ULL << 46) -#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */ -#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_VIO (1ULL << 53) -#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */ -#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */ -#define WAKEUP_PUFF (1ULL << 56) /*!< [SLEEP, ] */ -#define WAKEUP_PQ (1ULL << 57) /*!< [SLEEP, ] */ -#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */ -// reserved WAKEUP_PVTVF0_AMBER (1ULL << 60) -// reserved WAKEUP_PVTVF0_RED (1ULL << 61) -// reserved WAKEUP_PVTVF1_AMBER (1ULL << 62) -#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */ - - -/** - * @brief Sleep Postpone - */ -#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */ -#define LOWPOWER_HWWAKE_PERIPHERALS (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted */ -#define LOWPOWER_HWWAKE_SDMA0 (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ -#define LOWPOWER_HWWAKE_SDMA1 (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ -#define LOWPOWER_HWWAKE_ENABLE_FRO192M (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */ - -/** - * @brief Wake up I/O sources - */ -#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */ -#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */ -#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */ -#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */ - -#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */ -#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */ -#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */ -#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */ - -/** - * @brief Wake up timers configuration in Low Power Modes - */ -#define LOWPOWER_TIMERCFG_CTRL_INDEX 0 -#define LOWPOWER_TIMERCFG_CTRL_MASK (0x1UL << LOWPOWER_TIMERCFG_CTRL_INDEX) -#define LOWPOWER_TIMERCFG_TIMER_INDEX 1 -#define LOWPOWER_TIMERCFG_TIMER_MASK (0x7UL << LOWPOWER_TIMERCFG_TIMER_INDEX) -#define LOWPOWER_TIMERCFG_OSC32K_INDEX 4 -#define LOWPOWER_TIMERCFG_OSC32K_MASK (0x1UL << LOWPOWER_TIMERCFG_OSC32K_INDEX) - -#define LOWPOWER_TIMERCFG_CTRL_DISABLE 0 /*!< Wake Timer Disable */ -#define LOWPOWER_TIMERCFG_CTRL_ENABLE 1 /*!< Wake Timer Enable */ - -/** - * @brief Primary Wake up timers configuration in Low Power Modes - */ -#define LOWPOWER_TIMERCFG_TIMER_RTC1KHZ 0 /*!< 1 KHz Real Time Counter (RTC) used as wake up source */ -#define LOWPOWER_TIMERCFG_TIMER_RTC1HZ 1 /*!< 1 Hz Real Time Counter (RTC) used as wake up source */ -#define LOWPOWER_TIMERCFG_TIMER_OSTIMER 2 /*!< OS Event Timer used as wake up source */ - -#define LOWPOWER_TIMERCFG_OSC32K_FRO32KHZ 0 /*!< Wake up Timers uses FRO 32 KHz as clock source */ -#define LOWPOWER_TIMERCFG_OSC32K_XTAL32KHZ 1 /*!< Wake up Timers uses Chrystal 32 KHz as clock source */ - -//! @brief Interface for lowpower functions -typedef struct LowpowerDriverInterface -{ - void (*power_cycle_cpu_and_flash)(void); - void (*set_lowpower_mode)(LPC_LOWPOWER_T *p_lowpower_cfg); -} lowpower_driver_interface_t; - -/* Power mode configuration API parameter */ -typedef enum _power_mode_config -{ - kPmu_Sleep = 0U, - kPmu_Deep_Sleep = 1U, - kPmu_PowerDown = 2U, - kPmu_Deep_PowerDown = 3U, -} power_mode_cfg_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral - * - * @param en peripheral for which to enable the PDRUNCFG bit - * @return none - */ -static inline void POWER_EnablePD(pd_bit_t en) -{ - /* PDRUNCFGSET */ - PMC->PDRUNCFGSET0 = en; -} - -/*! - * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral - * - * @param en peripheral for which to disable the PDRUNCFG bit - * @return none - */ -static inline void POWER_DisablePD(pd_bit_t en) -{ - /* PDRUNCFGCLR */ - PMC->PDRUNCFGCLR0 = en; -} - -/*! - * @brief set BOD VBAT level. - * - * @param level BOD detect level - * @param hyst BoD Hysteresis control - * @param enBodVbatReset VBAT brown out detect reset - */ -static inline void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset) -{ - PMC->BODVBAT = (PMC->BODVBAT & (~(PMC_BODVBAT_TRIGLVL_MASK | PMC_BODVBAT_HYST_MASK))) | PMC_BODVBAT_TRIGLVL(level) | - PMC_BODVBAT_HYST(hyst); - PMC->RESETCTRL = - (PMC->RESETCTRL & (~PMC_RESETCTRL_BODVBATRESETENABLE_MASK)) | PMC_RESETCTRL_BODVBATRESETENABLE(enBodVbatReset); -} - -/*! - * @brief set BOD core level. - * - * @param level BOD detect level - * @param hyst BoD Hysteresis control - * @param enBodCoreReset core brown out detect reset - */ -static inline void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset) -{ - PMC->BODCORE = (PMC->BODCORE & (~(PMC_BODCORE_TRIGLVL_MASK | PMC_BODCORE_HYST_MASK))) | PMC_BODCORE_TRIGLVL(level) | - PMC_BODCORE_HYST(hyst); - PMC->RESETCTRL = - (PMC->RESETCTRL & (~PMC_RESETCTRL_BODCORERESETENABLE_MASK)) | PMC_RESETCTRL_BODCORERESETENABLE(enBodCoreReset); -} - -/*! - * @brief API to enable deep sleep bit in the ARM Core. - * - * @param none - * @return none - */ -static inline void POWER_EnableDeepSleep(void) -{ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; -} - -/*! - * @brief API to disable deep sleep bit in the ARM Core. - * - * @param none - * @return none - */ -static inline void POWER_DisableDeepSleep(void) -{ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; -} - -/*! - * @brief API to power down flash controller. - * - * @param none - * @return none - */ -static inline void POWER_PowerDownFlash(void) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */ - CLOCK_DisableClock(kCLOCK_Flash); - - /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */ - CLOCK_DisableClock(kCLOCK_Fmc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief API to power up flash controller. - * - * @param none - * @return none - */ -static inline void POWER_PowerUpFlash(void) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */ - CLOCK_EnableClock(kCLOCK_Fmc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/** - * @brief Configures and enters in low power mode - * @param p_lowpower_cfg: pointer to a structure that contains all low power mode parameters - * @return Nothing - * - * !!! IMPORTANT NOTES : - * 1 - CPU Interrupt Enable registers are updated with p_lowpower_cfg->WAKEUPINT. They are NOT restored by the - * API. - * 2 - The Non Maskable Interrupt (NMI) should be disable before calling this API (otherwise, there is a risk - * of Dead Lock). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip - * reset) - */ -void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg); - -/** - * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event - * This MUST BE EXECUTED outside the Flash: - * either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is - * preferable to have all functions defined in this file implemented in ROM. - * @param None - * @return Nothing - */ -void POWER_CycleCpuAndFlash(void); - -/** - * @brief Configures and enters in DEEP-SLEEP low power mode - * @param exclude_from_pd: - * @param sram_retention_ctrl: - * @param wakeup_interrupts: - * @param hardware_wake_ctrl: - - * @return Nothing - * - * !!! IMPORTANT NOTES : - 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset) - reset) - */ -void POWER_EnterDeepSleep(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts,uint32_t hardware_wake_ctrl); - -/** - * @brief Configures and enters in POWERDOWN low power mode - * @param exclude_from_pd: - * @param sram_retention_ctrl: - * @param wakeup_interrupts: - * @param cpu_retention_ctrl: 0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are - RESERVED. - - * @return Nothing - * - * !!! IMPORTANT NOTES : - 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance containing the stack used to call this function WILL BE preserved during low power (via parameter "sram_retention_ctrl") - * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset) - reset) - */ -void POWER_EnterPowerDown(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t cpu_retention_ctrl); - -/** - * @brief Configures and enters in DEEPPOWERDOWN low power mode - * @param exclude_from_pd: - * @param sram_retention_ctrl: - * @param wakeup_interrupts: - * @param wakeup_io_ctrl: - - * @return Nothing - * - * !!! IMPORTANT NOTES : - 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset) - */ -void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t wakeup_io_ctrl); - -/** - * @brief Configures and enters in SLEEP low power mode - * @param : - * @return Nothing - */ -void POWER_EnterSleep(void); - -/*! - * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. - * - * @param system_freq_hz - The desired frequency (in Hertz) at which the part would like to operate, - * note that the voltage and flash wait states should be set before changing frequency - * @return none - */ -void POWER_SetVoltageForFreq(uint32_t system_freq_hz); - -/*! - * @brief Power Library API to return the library version. - * - * @param none - * @return version number of the power library - */ -uint32_t POWER_GetLibVersion(void); - -/** - * @brief Sets board-specific trim values for 16MHz XTAL - * @param pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * @param pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * @param pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * @return none - * @note Following default Values can be used: - * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 - * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20 - * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 - */ -extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, int32_t pi32_16MfXtalPPcbParCappF_x100, int32_t pi32_16MfXtalNPcbParCappF_x100); -/** - * @brief Sets board-specific trim values for 32kHz XTAL - * @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - - * @return none - * @note Following default Values can be used: - * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 - * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40 - * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 - */ -extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, int32_t pi32_32kfXtalPPcbParCappF_x100, int32_t pi32_32kfXtalNPcbParCappF_x100); -/** - * @brief Enables and sets LDO for 16MHz XTAL - * @param none - * @return none - */ -extern void POWER_SetXtal16mhzLdo(void); -/** - * @brief Set up 16-MHz XTAL Trimmings - * @param amp Amplitude - * @param gm Transconductance - * @return none - */ -extern void POWER_SetXtal16mhzTrim(uint32_t amp, uint32_t gm); -#ifdef __cplusplus - } -#endif - -/** - * @} - */ - -#endif /* _FSL_POWER_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad.h deleted file mode 100644 index 92a63ac5b7..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad.h +++ /dev/null @@ -1,2764 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_POWERQUAD_H_ -#define _FSL_POWERQUAD_H_ - -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) -#include -#elif defined(__ICCARM__) -#include -#elif defined(__GNUC__) -#include -#endif /* defined(__CC_ARM) */ - -#include "fsl_common.h" -#include "fsl_powerquad_data.h" - -/*! - * @addtogroup powerquad - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_POWERQUAD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ -/*@}*/ - -#define PQ_FLOAT32 0U -#define PQ_FIXEDPT 1U - -#define CP_PQ 0U -#define CP_MTX 1U -#define CP_FFT 2U -#define CP_FIR 3U -#define CP_CORDIC 5U - -#define PQ_TRANS 0U -#define PQ_TRIG 1U -#define PQ_BIQUAD 2U - -#define PQ_TRANS_FIXED 4U -#define PQ_TRIG_FIXED 5U -#define PQ_BIQUAD_FIXED 6U - -#define PQ_INV 0U -#define PQ_LN 1U -#define PQ_SQRT 2U -#define PQ_INVSQRT 3U -#define PQ_ETOX 4U -#define PQ_ETONX 5U -#define PQ_DIV 6U - -#define PQ_SIN 0U -#define PQ_COS 1U - -#define PQ_BIQ0_CALC 1U -#define PQ_BIQ1_CALC 1U - -#define PQ_COMP0_ONLY (0U << 1) -#define PQ_COMP1_ONLY (1U << 1) - -#define CORDIC_ITER(x) (x << 2) -#define CORDIC_MIU(x) (x << 1) -#define CORDIC_T(x) (x << 0) -#define CORDIC_ARCTAN CORDIC_T(1) | CORDIC_MIU(0) -#define CORDIC_ARCTANH CORDIC_T(1) | CORDIC_MIU(1) - -#define INST_BUSY 0x80000000U - -#define PQ_ERRSTAT_OVERFLOW 0U -#define PQ_ERRSTAT_NAN 1U -#define PQ_ERRSTAT_FIXEDOVERFLOW 2U -#define PQ_ERRSTAT_UNDERFLOW 3U - -#define PQ_TRANS_CFFT 0U -#define PQ_TRANS_IFFT 1U -#define PQ_TRANS_CDCT 2U -#define PQ_TRANS_IDCT 3U -#define PQ_TRANS_RFFT 4U -#define PQ_TRANS_RDCT 6U - -#define PQ_MTX_SCALE 1U -#define PQ_MTX_MULT 2U -#define PQ_MTX_ADD 3U -#define PQ_MTX_INV 4U -#define PQ_MTX_PROD 5U -#define PQ_MTX_SUB 7U -#define PQ_VEC_DOTP 9U -#define PQ_MTX_TRAN 10U - -/* FIR engine operation type */ -#define PQ_FIR_FIR 0U -#define PQ_FIR_CONVOLUTION 1U -#define PQ_FIR_CORRELATION 2U -#define PQ_FIR_INCREMENTAL 4U - -#define _pq_ln0(x) __arm_mcr(CP_PQ, PQ_LN, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_inv0(x) __arm_mcr(CP_PQ, PQ_INV, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_sqrt0(x) __arm_mcr(CP_PQ, PQ_SQRT, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_invsqrt0(x) __arm_mcr(CP_PQ, PQ_INVSQRT, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_etox0(x) __arm_mcr(CP_PQ, PQ_ETOX, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_etonx0(x) __arm_mcr(CP_PQ, PQ_ETONX, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_sin0(x) __arm_mcr(CP_PQ, PQ_SIN, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRIG) -#define _pq_cos0(x) __arm_mcr(CP_PQ, PQ_COS, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRIG) -#define _pq_biquad0(x) __arm_mcr(CP_PQ, PQ_BIQ0_CALC, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_BIQUAD) - -#define _pq_ln_fx0(x) __arm_mcr(CP_PQ, PQ_LN, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_inv_fx0(x) __arm_mcr(CP_PQ, PQ_INV, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_sqrt_fx0(x) __arm_mcr(CP_PQ, PQ_SQRT, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_invsqrt_fx0(x) __arm_mcr(CP_PQ, PQ_INVSQRT, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_etox_fx0(x) __arm_mcr(CP_PQ, PQ_ETOX, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_etonx_fx0(x) __arm_mcr(CP_PQ, PQ_ETONX, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_sin_fx0(x) __arm_mcr(CP_PQ, PQ_SIN, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRIG_FIXED) -#define _pq_cos_fx0(x) __arm_mcr(CP_PQ, PQ_COS, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRIG_FIXED) -#define _pq_biquad0_fx(x) __arm_mcr(CP_PQ, PQ_BIQ0_CALC, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_BIQUAD_FIXED) - -#define _pq_div0(x) __arm_mcrr(CP_PQ, PQ_FLOAT32 | PQ_COMP0_ONLY, x, PQ_DIV) -#define _pq_div1(x) __arm_mcrr(CP_PQ, PQ_FLOAT32 | PQ_COMP1_ONLY, x, PQ_DIV) - -#define _pq_ln1(x) __arm_mcr(CP_PQ, PQ_LN, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_inv1(x) __arm_mcr(CP_PQ, PQ_INV, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_sqrt1(x) __arm_mcr(CP_PQ, PQ_SQRT, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_invsqrt1(x) __arm_mcr(CP_PQ, PQ_INVSQRT, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_etox1(x) __arm_mcr(CP_PQ, PQ_ETOX, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_etonx1(x) __arm_mcr(CP_PQ, PQ_ETONX, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_sin1(x) __arm_mcr(CP_PQ, PQ_SIN, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRIG) -#define _pq_cos1(x) __arm_mcr(CP_PQ, PQ_COS, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRIG) -#define _pq_biquad1(x) __arm_mcr(CP_PQ, PQ_BIQ1_CALC, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_BIQUAD) - -#define _pq_ln_fx1(x) __arm_mcr(CP_PQ, PQ_LN, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_inv_fx1(x) __arm_mcr(CP_PQ, PQ_INV, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_sqrt_fx1(x) __arm_mcr(CP_PQ, PQ_SQRT, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_invsqrt_fx1(x) __arm_mcr(CP_PQ, PQ_INVSQRT, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_etox_fx1(x) __arm_mcr(CP_PQ, PQ_ETOX, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_etonx_fx1(x) __arm_mcr(CP_PQ, PQ_ETONX, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_sin_fx1(x) __arm_mcr(CP_PQ, PQ_SIN, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRIG_FIXED) -#define _pq_cos_fx1(x) __arm_mcr(CP_PQ, PQ_COS, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRIG_FIXED) -#define _pq_biquad1_fx(x) __arm_mcr(CP_PQ, PQ_BIQ1_CALC, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_BIQUAD_FIXED) - -#define _pq_readMult0() __arm_mrc(CP_PQ, 0, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, 0) -#define _pq_readAdd0() __arm_mrc(CP_PQ, 1, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, 0) -#define _pq_readMult1() __arm_mrc(CP_PQ, 0, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, 0) -#define _pq_readAdd1() __arm_mrc(CP_PQ, 1, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, 0) -#define _pq_readMult0_fx() __arm_mrc(CP_PQ, 0, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, 0) -#define _pq_readAdd0_fx() __arm_mrc(CP_PQ, 1, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, 0) -#define _pq_readMult1_fx() __arm_mrc(CP_PQ, 0, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, 0) -#define _pq_readAdd1_fx() __arm_mrc(CP_PQ, 1, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, 0) - -/*! Parameter used for vector ln(x) */ -#define PQ_LN_INF PQ_LN, 1, PQ_TRANS -/*! Parameter used for vector 1/x */ -#define PQ_INV_INF PQ_INV, 0, PQ_TRANS -/*! Parameter used for vector sqrt(x) */ -#define PQ_SQRT_INF PQ_SQRT, 0, PQ_TRANS -/*! Parameter used for vector 1/sqrt(x) */ -#define PQ_ISQRT_INF PQ_INVSQRT, 0, PQ_TRANS -/*! Parameter used for vector e^x */ -#define PQ_ETOX_INF PQ_ETOX, 0, PQ_TRANS -/*! Parameter used for vector e^(-x) */ -#define PQ_ETONX_INF PQ_ETONX, 0, PQ_TRANS -/*! Parameter used for vector sin(x) */ -#define PQ_SIN_INF PQ_SIN, 1, PQ_TRIG -/*! Parameter used for vector cos(x) */ -#define PQ_COS_INF PQ_COS, 1, PQ_TRIG - -/* - * Register assignment for the vector calculation assembly. - * r0: pSrc, r1: pDest, r2-r7: Data - */ - -#define _PQ_RUN_FLOAT_OPCODE_R3_R2(BATCH_OPCODE, BATCH_MACHINE) \ - __asm volatile( \ - " MCR p0,%[opcode],r3,c2,c0,%[machine] \n" \ - " MCR p0,%[opcode],r2,c0,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ - [machine] "i"(BATCH_MACHINE)) - -#define _PQ_RUN_FLOAT_OPCODE_R5_R4(BATCH_OPCODE, BATCH_MACHINE) \ - __asm volatile( \ - " MCR p0,%[opcode],r5,c2,c0,%[machine] \n" \ - " MCR p0,%[opcode],r4,c0,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ - [machine] "i"(BATCH_MACHINE)) - -#define _PQ_RUN_FLOAT_OPCODE_R7_R6(BATCH_OPCODE, BATCH_MACHINE) \ - __asm volatile( \ - " MCR p0,%[opcode],r7,c2,c0,%[machine] \n" \ - " MCR p0,%[opcode],r6,c0,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ - [machine] "i"(BATCH_MACHINE)) - -/*! - * @brief Float data vector calculation. - * - * Float data vector calculation, the input data should be Float and must be 8 bytes. - * - * @param middle Determine if it is the first set of data, true if not. - * @param last Determine if it is the last set of data, true if yes. - * - * The last three parameters could be PQ_LN_INF, PQ_INV_INF, PQ_SQRT_INF, PQ_ISQRT_INF, PQ_ETOX_INF, PQ_ETONX_INF. - * For example, to calculate sqrt of a vector, use like this: - * @code - #define VECTOR_LEN 16 - Float input[VECTOR_LEN] = {1.0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - Float output[VECTOR_LEN]; - - PQ_Initiate_Vector_Func(pSrc,pDst); - PQ_Vector8_FP(false,false,PQ_SQRT_INF); - PQ_Vector8_FP(true,true,PQ_SQRT_INF); - PQ_End_Vector_Func(); - @endcode - * - */ - -#define PQ_Vector8_FP(middle, last, BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ - _PQ_RUN_FLOAT_OPCODE_R3_R2(BATCH_OPCODE, BATCH_MACHINE); \ - if (middle) \ - { \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ - } \ - __asm volatile("LDMIA r0!,{r4-r5}"); /* load next 2 datas */ \ - if (DOUBLE_READ_ADDERS) \ - { \ - __asm volatile("MRRC p0,#0,r2,r3,c1"); \ - } \ - else \ - { \ - __asm volatile("MRRC p0,#0,r2,r3,c0"); \ - } \ - _PQ_RUN_FLOAT_OPCODE_R5_R4(BATCH_OPCODE, BATCH_MACHINE); \ - __asm volatile("STRD r2,r3,[r1],#8"); /* store first two results */ \ - __asm volatile("LDMIA r0!,{r6-r7}"); /* load next 2 datas */ \ - if (DOUBLE_READ_ADDERS) \ - { \ - __asm volatile("MRRC p0,#0,r4,r5,c1"); \ - } \ - else \ - { \ - __asm volatile("MRRC p0,#0,r4,r5,c0"); \ - } \ - _PQ_RUN_FLOAT_OPCODE_R7_R6(BATCH_OPCODE, BATCH_MACHINE); \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store second two results */ \ - __asm volatile("LDRD r4,r5,[r0],#8"); /* load last 2 of the 8 */ \ - if (DOUBLE_READ_ADDERS) \ - { \ - __asm volatile("MRRC p0,#0,r6,r7,c1"); \ - } \ - else \ - { \ - __asm volatile("MRRC p0,#0,r6,r7,c0"); \ - } \ - _PQ_RUN_FLOAT_OPCODE_R5_R4(BATCH_OPCODE, BATCH_MACHINE); \ - __asm volatile("STRD r6,r7,[r1],#8"); /* store third two results */ \ - if (!last) \ - { \ - __asm volatile("LDRD r2,r3,[r0],#8"); /* load first two of next 8 */ \ - } \ - else \ - { \ - __asm volatile("NOP"); \ - } \ - if (DOUBLE_READ_ADDERS) \ - { \ - __asm volatile("MRRC p0,#0,r4,r5,c1"); \ - } \ - else \ - { \ - __asm volatile("MRRC p0,#0,r4,r5,c0"); \ - } \ - if (last) \ - { \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ - } - -#define _PQ_RUN_FIXED32_OPCODE_R2_R3(BATCH_OPCODE, BATCH_MACHINE) \ - __asm volatile( \ - " MCR p0,%[opcode],r2,c1,c0,%[machine] \n" \ - " MCR p0,%[opcode],r3,c3,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ - [machine] "i"(BATCH_MACHINE)) - -#define _PQ_RUN_FIXED32_OPCODE_R4_R5(BATCH_OPCODE, BATCH_MACHINE) \ - __asm volatile( \ - " MCR p0,%[opcode],r4,c1,c0,%[machine] \n" \ - " MCR p0,%[opcode],r5,c3,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ - [machine] "i"(BATCH_MACHINE)) - -#define _PQ_RUN_FIXED32_OPCODE_R6_R7(BATCH_OPCODE, BATCH_MACHINE) \ - __asm volatile( \ - " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ - [machine] "i"(BATCH_MACHINE)) - -/*! - * @brief Fixed data vector calculation. - * - * Fixed data vector calculation, the input data should be Fixed and must be 8 bytes. - * - * @param middle Determine if it is the first set of data, true if not. - * @param last Determine if it is the last set of data, true if yes. - * - * The last three parameters could be PQ_LN_INF, PQ_INV_INF, PQ_SQRT_INF, PQ_ISQRT_INF, PQ_ETOX_INF, PQ_ETONX_INF. - * For example, to calculate sqrt of a vector, use like this: - * @code - #define VECTOR_LEN 16 - uint32_t input[VECTOR_LEN] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - uint32_t output[VECTOR_LEN]; - - PQ_Initiate_Vector_Func(pSrc,pDst); - PQ_Vector8_FX(false,false,PQ_SQRT_INF); - PQ_Vector8_FX(true,true,PQ_SQRT_INF); - PQ_End_Vector_Func(); - @endcode - * - */ - -#define PQ_Vector8_FX(middle, last, BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ - _PQ_RUN_FIXED32_OPCODE_R2_R3(BATCH_OPCODE, BATCH_MACHINE); \ - if (middle) \ - { \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ - } \ - __asm volatile("LDMIA r0!,{r4-r7}"); /* load next 4 datas */ \ - if (DOUBLE_READ_ADDERS) \ - { \ - __asm volatile("MRC p0,#0x1,r2,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r3,c3,c0,#0"); \ - } \ - else \ - { \ - __asm volatile("MRC p0,#0,r2,c1,c0,#0"); \ - __asm volatile("MRC p0,#0,r3,c3,c0,#0"); \ - } \ - _PQ_RUN_FIXED32_OPCODE_R4_R5(BATCH_OPCODE, BATCH_MACHINE); \ - __asm volatile("STRD r2,r3,[r1],#8"); /* store first two results */ \ - if (DOUBLE_READ_ADDERS) \ - { \ - __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r5,c3,c0,#0"); \ - } \ - else \ - { \ - __asm volatile("MRC p0,#0,r4,c1,c0,#0"); \ - __asm volatile("MRC p0,#0,r5,c3,c0,#0"); \ - } \ - _PQ_RUN_FIXED32_OPCODE_R6_R7(BATCH_OPCODE, BATCH_MACHINE); \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store second two results */ \ - __asm volatile("LDRD r4,r5,[r0],#8"); /* load last 2 of the 8 */ \ - if (DOUBLE_READ_ADDERS) \ - { \ - __asm volatile("MRC p0,#0x1,r6,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r7,c3,c0,#0"); \ - } \ - else \ - { \ - __asm volatile("MRC p0,#0,r6,c1,c0,#0"); \ - __asm volatile("MRC p0,#0,r7,c3,c0,#0"); \ - } \ - _PQ_RUN_FIXED32_OPCODE_R4_R5(BATCH_OPCODE, BATCH_MACHINE); \ - __asm volatile("STRD r6,r7,[r1],#8"); /* store third two results */ \ - if (!last) \ - __asm volatile("LDRD r2,r3,[r0],#8"); /* load first two of next 8 */ \ - if (DOUBLE_READ_ADDERS) \ - { \ - __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r5,c3,c0,#0"); \ - } \ - else \ - { \ - __asm volatile("MRC p0,#0,r4,c1,c0,#0"); \ - __asm volatile("MRC p0,#0,r5,c3,c0,#0"); \ - } \ - if (last) \ - { \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ - } - -/*! - * @brief Start 32-bit data vector calculation. - * - * Start the vector calculation, the input data could be float, int32_t or Q31. - * - * @param PSRC Pointer to the source data. - * @param PDST Pointer to the destination data. - */ -#define PQ_Initiate_Vector_Func(pSrc, pDst) \ - __asm volatile( \ - "MOV r0, %[psrc] \n" \ - "MOV r1, %[pdst] \n" \ - "PUSH {r2-r7} \n" \ - "LDRD r2,r3,[r0],#8 \n" ::[psrc] "r"(pSrc), \ - [pdst] "r"(pDst) \ - : "r0", "r1") - -/*! - * @brief End vector calculation. - * - * This function should be called after vector calculation. - */ -#define PQ_End_Vector_Func() __asm volatile("POP {r2-r7}") - -/* - * Register assignment for the vector calculation assembly. - * r0: pSrc, r1: pDest, r2: length, r3: middle, r4-r9: Data, r10:dra - */ - -/*! - * @brief Start 32-bit data vector calculation. - * - * Start the vector calculation, the input data could be float, int32_t or Q31. - * - * @param PSRC Pointer to the source data. - * @param PDST Pointer to the destination data. - * @param LENGTH Number of the data, must be multiple of 8. - */ -#define PQ_StartVector(PSRC, PDST, LENGTH) \ - __asm volatile( \ - "MOV r0, %[psrc] \n" \ - "MOV r1, %[pdst] \n" \ - "MOV r2, %[length] \n" \ - "PUSH {r3-r10} \n" \ - "MOV r3, #0 \n" \ - "MOV r10, #0 \n" \ - "LDRD r4,r5,[r0],#8 \n" ::[psrc] "r"(PSRC), \ - [pdst] "r"(PDST), [length] "r"(LENGTH) \ - : "r0", "r1", "r2") - -/*! - * @brief Start 16-bit data vector calculation. - * - * Start the vector calculation, the input data could be int16_t. This function - * should be use with @ref PQ_Vector8Fixed16. - * - * @param PSRC Pointer to the source data. - * @param PDST Pointer to the destination data. - * @param LENGTH Number of the data, must be multiple of 8. - */ -#define PQ_StartVectorFixed16(PSRC, PDST, LENGTH) \ - __asm volatile( \ - "MOV r0, %[psrc] \n" \ - "MOV r1, %[pdst] \n" \ - "MOV r2, %[length] \n" \ - "PUSH {r3-r10} \n" \ - "MOV r3, #0 \n" \ - "LDRSH r4,[r0],#2 \n" \ - "LDRSH r5,[r0],#2 \n" ::[psrc] "r"(PSRC), \ - [pdst] "r"(PDST), [length] "r"(LENGTH) \ - : "r0", "r1", "r2") - -/*! - * @brief Start Q15-bit data vector calculation. - * - * Start the vector calculation, the input data could be Q15. This function - * should be use with @ref PQ_Vector8Q15. This function is dedicate for - * SinQ15/CosQ15 vector calculation. Because PowerQuad only supports Q31 Sin/Cos - * fixed function, so the input Q15 data is left shift 16 bits first, after - * Q31 calculation, the output data is right shift 16 bits. - * - * @param PSRC Pointer to the source data. - * @param PDST Pointer to the destination data. - * @param LENGTH Number of the data, must be multiple of 8. - */ -#define PQ_StartVectorQ15(PSRC, PDST, LENGTH) \ - __asm volatile( \ - "MOV r0, %[psrc] \n" \ - "MOV r1, %[pdst] \n" \ - "MOV r2, %[length] \n" \ - "PUSH {r3-r10} \n" \ - "MOV r3, #0 \n" \ - "LDR r5,[r0],#4 \n" \ - "LSL r4,r5,#16 \n" \ - "BFC r5,#0,#16 \n" ::[psrc] "r"(PSRC), \ - [pdst] "r"(PDST), [length] "r"(LENGTH) \ - : "r0", "r1", "r2") - -/*! - * @brief End vector calculation. - * - * This function should be called after vector calculation. - */ -#define PQ_EndVector() __asm volatile("POP {r3-r10} \n") - -/*! - * @brief Float data vector calculation. - * - * Float data vector calculation, the input data should be float. The parameter - * could be PQ_LN_INF, PQ_INV_INF, PQ_SQRT_INF, PQ_ISQRT_INF, PQ_ETOX_INF, PQ_ETONX_INF. - * For example, to calculate sqrt of a vector, use like this: - * @code - #define VECTOR_LEN 8 - float input[VECTOR_LEN] = {1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0}; - float output[VECTOR_LEN]; - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8F32(PQ_SQRT_INF); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8F32(BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ - __asm volatile( \ - "1: \n" \ - " MCR p0,%[opcode],r5,c2,c0,%[machine] \n" \ - " MCR p0,%[opcode],r4,c0,c0,%[machine] \n" \ - " CMP r3, #0 \n" \ - " ITE NE \n" \ - " STRDNE r6,r7,[r1],#8 \n" /* store fourth two results */ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ - " MOV r10,%[dra] \n" \ - " CMP r10, #0 \n" \ - " ITE NE \n" \ - " MRRCNE p0,#0,r4,r5,c1 \n" \ - " MRRCEQ p0,#0,r4,r5,c0 \n" \ - " MCR p0,%[opcode],r7,c2,c0,%[machine] \n" \ - " MCR p0,%[opcode],r6,c0,c0,%[machine] \n" \ - " STRD r4,r5,[r1],#8 \n" /* store first two results */ \ - " MOV r10,%[dra] \n" \ - " CMP r10, #0 \n" \ - " ITE NE \n" \ - " MRRCNE p0,#0,r6,r7,c1 \n" \ - " MRRCEQ p0,#0,r6,r7,c0 \n" \ - " MCR p0,%[opcode],r9,c2,c0,%[machine] \n" \ - " MCR p0,%[opcode],r8,c0,c0,%[machine] \n" \ - " STRD r6,r7,[r1],#8 \n" /* store second two results */ \ - " LDRD r6,r7,[r0],#8 \n" /* load last 2 of the 8 */ \ - " CMP r10, #0 \n" \ - " ITE NE \n" \ - " MRRCNE p0,#0,r8,r9,c1 \n" \ - " MRRCEQ p0,#0,r8,r9,c0 \n" \ - " MCR p0,%[opcode],r7,c2,c0,%[machine] \n" \ - " MCR p0,%[opcode],r6,c0,c0,%[machine] \n" \ - " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " IT NE \n" \ - " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ - " CMP r10, #0 \n" \ - " ITE NE \n" \ - " MRRCNE p0,#0,r6,r7,c1 \n" \ - " MRRCEQ p0,#0,r6,r7,c0 \n" \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " STRD r6,r7,[r1],#8 \n" /* store fourth two results */ \ - ::[opcode] "i"(BATCH_OPCODE), \ - [dra] "i"(DOUBLE_READ_ADDERS), [machine] "i"(BATCH_MACHINE)) - -/*! - * @brief Fixed 32bits data vector calculation. - * - * Float data vector calculation, the input data should be 32-bit integer. The parameter - * could be PQ_LN_INF, PQ_INV_INF, PQ_SQRT_INF, PQ_ISQRT_INF, PQ_ETOX_INF, PQ_ETONX_INF. - * PQ_SIN_INF, PQ_COS_INF. When this function is used for sin/cos calculation, the input - * data should be in the format Q1.31. - * For example, to calculate sqrt of a vector, use like this: - * @code - #define VECTOR_LEN 8 - int32_t input[VECTOR_LEN] = {1, 4, 9, 16, 25, 36, 49, 64}; - int32_t output[VECTOR_LEN]; - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8F32(PQ_SQRT_INF); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8Fixed32(BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ - __asm volatile( \ - "1: \n" \ - " MCR p0,%[opcode],r4,c1,c0,%[machine] \n" \ - " ISB \n" \ - " MCR p0,%[opcode],r5,c3,c0,%[machine] \n" \ - " CMP r3, #0 \n" \ - " ITE NE \n" \ - " STRDNE r6,r7,[r1],#8 \n" /* store fourth two results */ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ - " MRC p0,%[dra],r4,c1,c0,#0 \n" \ - " MRC p0,%[dra],r5,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " ISB \n" \ - " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ - " STRD r4,r5,[r1],#8 \n" /* store first two results */ \ - " MRC p0,%[dra],r6,c1,c0,#0 \n" \ - " MRC p0,%[dra],r7,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r8,c1,c0,%[machine] \n" \ - " ISB \n" \ - " MCR p0,%[opcode],r9,c3,c0,%[machine] \n" \ - " STRD r6,r7,[r1],#8 \n" /* store second two results */ \ - " LDRD r6,r7,[r0],#8 \n" /* load last 2 of the 8 */ \ - " MRC p0,%[dra],r8,c1,c0,#0 \n" \ - " MRC p0,%[dra],r9,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " ISB \n" \ - " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ - " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " IT NE \n" \ - " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ - " MRC p0,%[dra],r6,c1,c0,#0 \n" \ - " MRC p0,%[dra],r7,c3,c0,#0 \n" \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " STRD r6,r7,[r1],#8 \n" /* store fourth two results */ \ - ::[opcode] "i"(BATCH_OPCODE), \ - [dra] "i"(DOUBLE_READ_ADDERS), [machine] "i"(BATCH_MACHINE)) - -/*! - * @brief Fixed 32bits data vector calculation. - * - * Float data vector calculation, the input data should be 16-bit integer. The parameter - * could be PQ_LN_INF, PQ_INV_INF, PQ_SQRT_INF, PQ_ISQRT_INF, PQ_ETOX_INF, PQ_ETONX_INF. - * For example, to calculate sqrt of a vector, use like this: - * @code - #define VECTOR_LEN 8 - int16_t input[VECTOR_LEN] = {1, 4, 9, 16, 25, 36, 49, 64}; - int16_t output[VECTOR_LEN]; - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8F32(PQ_SQRT_INF); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8Fixed16(BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ - __asm volatile( \ - "1: \n" \ - " MCR p0,%[opcode],r4,c1,c0,%[machine] \n" \ - " MCR p0,%[opcode],r5,c3,c0,%[machine] \n" \ - " CMP r3, #0 \n" \ - " ITTE NE \n" \ - " STRHNE r6,[r1],#2 \n" /* store fourth two results */ \ - " STRHNE r7,[r1],#2 \n" /* store fourth two results */ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDRSH r6,[r0],#2 \n" /* load next 2 of the 8 */ \ - " LDRSH r7,[r0],#2 \n" /* load next 2 of the 8 */ \ - " MRC p0,%[dra],r4,c1,c0,#0 \n" \ - " MRC p0,%[dra],r5,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ - " STRH r4,[r1],#2 \n" /* store first two results */ \ - " STRH r5,[r1],#2 \n" /* store first two results */ \ - " LDRSH r8,[r0],#2 \n" /* load next 2 of the 8 */ \ - " LDRSH r9,[r0],#2 \n" /* load next 2 of the 8 */ \ - " MRC p0,%[dra],r6,c1,c0,#0 \n" \ - " MRC p0,%[dra],r7,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r8,c1,c0,%[machine] \n" \ - " MCR p0,%[opcode],r9,c3,c0,%[machine] \n" \ - " STRH r6,[r1],#2 \n" /* store second two results */ \ - " STRH r7,[r1],#2 \n" /* store second two results */ \ - " LDRSH r6,[r0],#2 \n" /* load last 2 of the 8 */ \ - " LDRSH r7,[r0],#2 \n" /* load last 2 of the 8 */ \ - " MRC p0,%[dra],r8,c1,c0,#0 \n" \ - " MRC p0,%[dra],r9,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ - " STRH r8,[r1],#2 \n" /* store third two results */ \ - " STRH r9,[r1],#2 \n" /* store third two results */ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " ITT NE \n" \ - " LDRSHNE r4,[r0],#2 \n" /* load first two of next 8 */ \ - " LDRSHNE r5,[r0],#2 \n" /* load first two of next 8 */ \ - " MRC p0,%[dra],r6,c1,c0,#0 \n" \ - " MRC p0,%[dra],r7,c3,c0,#0 \n" \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " STRH r6,[r1],#2 \n" /* store fourth two results */ \ - " STRH r7,[r1],#2 \n" /* store fourth two results */ \ - ::[opcode] "i"(BATCH_OPCODE), \ - [dra] "i"(DOUBLE_READ_ADDERS), [machine] "i"(BATCH_MACHINE)) - -/*! - * @brief Q15 data vector calculation. - * - * Q15 data vector calculation, this function should only be used for sin/cos Q15 calculation, - * and the coprocessor output prescaler must be set to 31 before this function. This function - * loads Q15 data and left shift 16 bits, calculate and right shift 16 bits, then stores to - * the output array. The input range -1 to 1 means -pi to pi. - * For example, to calculate sin of a vector, use like this: - * @code - #define VECTOR_LEN 8 - int16_t input[VECTOR_LEN] = {...} - int16_t output[VECTOR_LEN]; - const pq_prescale_t prescale = - { - .inputPrescale = 0, - .outputPrescale = 31, - .outputSaturate = 0 - }; - - PQ_SetCoprocessorScaler(POWERQUAD, const pq_prescale_t *prescale); - - PQ_StartVectorQ15(pSrc, pDst, length); - PQ_Vector8Q15(PQ_SQRT_INF); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8Q15(BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ - __asm volatile( \ - "1: \n" \ - " MCR p0,%[opcode],r4,c1,c0,%[machine] \n" \ - " ISB \n" \ - " MCR p0,%[opcode],r5,c3,c0,%[machine] \n" \ - " CMP r3, #0 \n" \ - " ITTTE NE \n" \ - " LSRNE r6,r6,#16 \n" /* store fourth two results */ \ - " BFINE r7,r6,#0,#16 \n" /* store fourth two results */ \ - " STRNE r7,[r1],#4 \n" /* store fourth two results */ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDR r7,[r0],#4 \n" /* load next 2 of the 8 */ \ - " LSL r6,r7,#16 \n" /* load next 2 of the 8 */ \ - " BFC r7,#0,#16 \n" /* load next 2 of the 8 */ \ - " MRC p0,%[dra],r4,c1,c0,#0 \n" \ - " MRC p0,%[dra],r5,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " ISB \n" \ - " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ - " LSR r4,r4,#16 \n" /* store first two results */ \ - " BFI r5,r4,#0,#16 \n" /* store first two results */ \ - " STR r5,[r1],#4 \n" /* store first two results */ \ - " LDR r9,[r0],#4 \n" /* load next 2 of the 8 */ \ - " LSL r8,r9,#16 \n" /* load next 2 of the 8 */ \ - " BFC r9,#0,#16 \n" /* load next 2 of the 8 */ \ - " MRC p0,%[dra],r6,c1,c0,#0 \n" \ - " MRC p0,%[dra],r7,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r8,c1,c0,%[machine] \n" \ - " ISB \n" \ - " MCR p0,%[opcode],r9,c3,c0,%[machine] \n" \ - " LSR r6,r6,#16 \n" /* store second two results */ \ - " BFI r7,r6,#0,#16 \n" /* store second two results */ \ - " STR r7,[r1],#4 \n" /* store second two results */ \ - " LDR r7,[r0],#4 \n" /* load next 2 of the 8 */ \ - " LSL r6,r7,#16 \n" /* load next 2 of the 8 */ \ - " BFC r7,#0,#16 \n" /* load next 2 of the 8 */ \ - " MRC p0,%[dra],r8,c1,c0,#0 \n" \ - " MRC p0,%[dra],r9,c3,c0,#0 \n" \ - " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " ISB \n" \ - " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ - " LSR r8,r8,#16 \n" /* store third two results */ \ - " BFI r9,r8,#0,#16 \n" /* store third two results */ \ - " STR r9,[r1],#4 \n" /* store third two results */ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " ITTT NE \n" \ - " LDRNE r5,[r0],#4 \n" /* load next 2 of the 8 */ \ - " LSLNE r4,r5,#16 \n" /* load next 2 of the 8 */ \ - " BFCNE r5,#0,#16 \n" /* load next 2 of the 8 */ \ - " MRC p0,%[dra],r6,c1,c0,#0 \n" \ - " MRC p0,%[dra],r7,c3,c0,#0 \n" \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " LSR r6,r6,#16 \n" /* store fourth two results */ \ - " BFI r7,r6,#0,#16 \n" /* store fourth two results */ \ - " STR r7,[r1],#4 \n" /* store fourth two results */ \ - ::[opcode] "i"(BATCH_OPCODE), \ - [dra] "i"(DOUBLE_READ_ADDERS), [machine] "i"(BATCH_MACHINE)) - -/*! - * @brief Float data vector biquad direct form II calculation. - * - * Biquad filter, the input and output data are float data. Biquad side 0 is used. Example: - * @code - #define VECTOR_LEN 16 - float input[VECTOR_LEN] = {1024.0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - float output[VECTOR_LEN]; - pq_biquad_state_t state = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state); - - PQ_Initiate_Vector_Func(pSrc,pDst); - PQ_DF2_Vector8_FP(false,false); - PQ_DF2_Vector8_FP(true,true); - PQ_End_Vector_Func(); - @endcode - * - */ -#define PQ_DF2_Vector8_FP(middle, last) \ - __asm volatile("MCR p0,#0x1,r2,c0,c0,#6"); /* write biquad0*/ \ - if (middle) \ - { \ - __asm volatile("STR r5,[r1],#4"); /* store last result*/ \ - } \ - __asm volatile("LDRD r4,r5,[r0],#8"); /* load next 2 datas */ \ - __asm volatile("MRC p0,#0x1,r2,c0,c0,#0"); /* read biquad0*/ \ - __asm volatile("MCR p0,#0x1,r3,c0,c0,#6"); /* write biquad0 */ \ - __asm volatile("MRC p0,#0x1,r3,c0,c0,#0"); /* read biquad0*/ \ - __asm volatile("MCR p0,#0x1,r4,c0,c0,#6"); /* write biquad0 */ \ - __asm volatile("STRD r2,r3,[r1],#8"); /* store first 2 results */ \ - __asm volatile("MRC p0,#0x1,r4,c0,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r5,c0,c0,#6"); \ - __asm volatile("LDRD r6,r7,[r0],#8"); /* load next 2 datas */ \ - __asm volatile("MRC p0,#0x1,r5,c0,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r6,c0,c0,#6"); \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store next 2 results */ \ - __asm volatile("MRC p0,#0x1,r6,c0,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r7,c0,c0,#6"); \ - __asm volatile("LDRD r4,r5,[r0],#8"); /* load next 2 datas */ \ - __asm volatile("MRC p0,#0x1,r7,c0,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r4,c0,c0,#6"); \ - __asm volatile("STRD r6,r7,[r1],#8"); /* store next 2 results */ \ - __asm volatile("MRC p0,#0x1,r4,c0,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r5,c0,c0,#6"); \ - if (!last) \ - { \ - __asm volatile("LDRD r2,r3,[r0],#8"); /* load first two of next 8 */ \ - } \ - __asm volatile("STR r4,[r1],#4"); \ - __asm volatile("MRC p0,#0x1,r5,c0,c0,#0"); \ - if (last) \ - { \ - __asm volatile("STR r5,[r1],#4"); /* store last result */ \ - } - -/*! - * @brief Fixed data vector biquad direct form II calculation. - * - * Biquad filter, the input and output data are fixed data. Biquad side 0 is used. Example: - * @code - #define VECTOR_LEN 16 - int32_t input[VECTOR_LEN] = {1024, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - int32_t output[VECTOR_LEN]; - pq_biquad_state_t state = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state); - - PQ_Initiate_Vector_Func(pSrc,pDst); - PQ_DF2_Vector8_FX(false,false); - PQ_DF2_Vector8_FX(true,true); - PQ_End_Vector_Func(); - @endcode - * - */ -#define PQ_DF2_Vector8_FX(middle, last) \ - __asm volatile("MCR p0,#0x1,r2,c1,c0,#6"); /* write biquad0*/ \ - if (middle) \ - { \ - __asm volatile("STR r5,[r1],#4"); /* store last result*/ \ - } \ - __asm volatile("LDRD r4,r5,[r0],#8"); /* load next 2 datas */ \ - __asm volatile("MRC p0,#0x1,r2,c1,c0,#0"); /* read biquad0*/ \ - __asm volatile("MCR p0,#0x1,r3,c1,c0,#6"); /* write biquad0 */ \ - __asm volatile("MRC p0,#0x1,r3,c1,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r4,c1,c0,#6"); \ - __asm volatile("STRD r2,r3,[r1],#8"); /* store first 2 results */ \ - __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r5,c1,c0,#6"); \ - __asm volatile("LDRD r6,r7,[r0],#8"); \ - __asm volatile("MRC p0,#0x1,r5,c1,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r6,c1,c0,#6"); \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store next 2 results */ \ - __asm volatile("MRC p0,#0x1,r6,c1,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r7,c1,c0,#6"); \ - __asm volatile("LDRD r4,r5,[r0],#8"); \ - __asm volatile("MRC p0,#0x1,r7,c1,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r4,c1,c0,#6"); \ - __asm volatile("STRD r6,r7,[r1],#8"); /* store next 2 results */ \ - __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r5,c1,c0,#6"); \ - if (!last) \ - { \ - __asm volatile("LDRD r2,r3,[r0],#8"); /* load two of next 8 */ \ - } \ - __asm volatile("STR r4,[r1],#4"); /* store 7th results */ \ - __asm volatile("MRC p0,#0x1,r5,c1,c0,#0"); \ - if (last) \ - { \ - __asm volatile("STR r5,[r1],#4"); /* store last result */ \ - } - -/*! - * @brief Float data vector biquad direct form II calculation. - * - * Biquad filter, the input and output data are float data. Biquad side 0 is used. Example: - * @code - #define VECTOR_LEN 8 - float input[VECTOR_LEN] = {1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0}; - float output[VECTOR_LEN]; - pq_biquad_state_t state = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state); - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8BiquadDf2F32(); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8BiquadDf2F32() \ - __asm volatile( \ - "1: \n" \ - " MCR p0,#0x1,r4,c0,c0,#6 \n" /* write biquad0*/ \ - " CMP r3, #0 \n" \ - " ITE NE \n" \ - " STRNE r7,[r1],#4 \n" /* store last result*/ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ - " MRC p0,#0x1,r4,c0,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r5,c0,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r5,c0,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r6,c0,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r6,c0,c0,#0 \n" /* read biquad0 */ \ - " MCR p0,#0x1,r7,c0,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r7,c0,c0,#0 \n" /* read biquad0 */ \ - " MCR p0,#0x1,r8,c0,c0,#6 \n" /* write biquad0*/ \ - " STMIA r1!,{r4-r7} \n" /* store first four results */ \ - " MRC p0,#0x1,r8,c0,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r9,c0,c0,#6 \n" /* write biquad0*/ \ - " LDRD r6,r7,[r0],#8 \n" /* load next 2 items*/ \ - " MRC p0,#0x1,r9,c0,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r6,c0,c0,#6 \n" /* write biquad0*/ \ - " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ - " MRC p0,#0x1,r6,c0,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r7,c0,c0,#6 \n" /* write biquad0*/ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " IT NE \n" \ - " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ - " STR r6,[r1],#4 \n" /* store 7th results */ \ - " MRC p0,#0x1,r7,c0,c0,#0 \n" /* read biquad0*/ \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " STR r7,[r1],#4 \n" /* store last result */ \ - ) - -/*! - * @brief Fixed 32-bit data vector biquad direct form II calculation. - * - * Biquad filter, the input and output data are Q31 or 32-bit integer. Biquad side 0 is used. Example: - * @code - #define VECTOR_LEN 8 - int32_t input[VECTOR_LEN] = {1, 2, 3, 4, 5, 6, 7, 8}; - int32_t output[VECTOR_LEN]; - pq_biquad_state_t state = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state); - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8BiquadDf2Fixed32(); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8BiquadDf2Fixed32() \ - __asm volatile( \ - "1: \n" \ - " MCR p0,#0x1,r4,c1,c0,#6 \n" /* write biquad0*/ \ - " CMP r3, #0 \n" \ - " ITE NE \n" \ - " STRNE r7,[r1],#4 \n" /* store last result*/ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ - " MRC p0,#0x1,r4,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r5,c1,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r5,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0 */ \ - " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0 */ \ - " MCR p0,#0x1,r8,c1,c0,#6 \n" /* write biquad0*/ \ - " STMIA r1!,{r4-r7} \n" /* store first four results */ \ - " MRC p0,#0x1,r8,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r9,c1,c0,#6 \n" /* write biquad0*/ \ - " LDRD r6,r7,[r0],#8 \n" /* load next 2 items*/ \ - " MRC p0,#0x1,r9,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ - " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ - " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " IT NE \n" \ - " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ - " STR r6,[r1],#4 \n" /* store 7th results */ \ - " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " STR r7,[r1],#4 \n" /* store last result */ \ - ) - -/*! - * @brief Fixed 16-bit data vector biquad direct form II calculation. - * - * Biquad filter, the input and output data are Q15 or 16-bit integer. Biquad side 0 is used. Example: - * @code - #define VECTOR_LEN 8 - int16_t input[VECTOR_LEN] = {1, 2, 3, 4, 5, 6, 7, 8}; - int16_t output[VECTOR_LEN]; - pq_biquad_state_t state = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state); - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8BiquadDf2Fixed16(); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8BiquadDf2Fixed16() \ - __asm volatile( \ - "1: \n" \ - " MCR p0,#0x1,r4,c1,c0,#6 \n" /* write biquad0*/ \ - " CMP r3, #0 \n" \ - " ITE NE \n" \ - " STRHNE r7,[r1],#2 \n" /* store last result*/ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDRSH r6,[r0],#2 \n" /* load next 2 of the 8*/ \ - " LDRSH r7,[r0],#2 \n" /* load next 2 of the 8*/ \ - " MRC p0,#0x1,r4,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r5,c1,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r5,c1,c0,#0 \n" /* read biquad0*/ \ - " LDRSH r8,[r0],#2 \n" /* load next 2 of the 8*/ \ - " LDRSH r9,[r0],#2 \n" /* load next 2 of the 8*/ \ - " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0 */ \ - " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0 */ \ - " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0 */ \ - " STRH r4,[r1],#2 \n" /* store first 4 results */ \ - " STRH r5,[r1],#2 \n" /* store first 4 results */ \ - " MCR p0,#0x1,r8,c1,c0,#6 \n" /* write biquad0*/ \ - " STRH r6,[r1],#2 \n" /* store first 4 results */ \ - " STRH r7,[r1],#2 \n" /* store first 4 results */ \ - " MRC p0,#0x1,r8,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r9,c1,c0,#6 \n" /* write biquad0*/ \ - " LDRSH r6,[r0],#2 \n" /* load next 1 of the 8*/ \ - " LDRSH r7,[r0],#2 \n" /* load next 1 of the 8*/ \ - " MRC p0,#0x1,r9,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ - " STRH r8,[r1],#2 \n" /* store next two results */ \ - " STRH r9,[r1],#2 \n" /* store next two results */ \ - " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ - " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " ITT NE \n" \ - " LDRSHNE r4,[r0],#2 \n" /* load first two of next 8*/ \ - " LDRSHNE r5,[r0],#2 \n" /* load first two of next 8*/ \ - " STRH r6,[r1],#2 \n" /* store 7th results */ \ - " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " STRH r7,[r1],#2 \n" /* store last result */ \ - ) - -/*! - * @brief Float data vector direct form II biquad cascade filter. - * - * The input and output data are float data. The data flow is - * input -> biquad side 1 -> biquad side 0 -> output. - * - * @code - #define VECTOR_LEN 16 - float input[VECTOR_LEN] = {1024.0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - float output[VECTOR_LEN]; - pq_biquad_state_t state0 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - pq_biquad_state_t state1 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state0); - PQ_BiquadRestoreInternalState(POWERQUAD, 1, &state1); - - PQ_Initiate_Vector_Func(pSrc, pDst); - PQ_DF2_Cascade_Vector8_FP(false, false); - PQ_DF2_Cascade_Vector8_FP(true, true); - PQ_End_Vector_Func(); - @endcode - * - */ -#define PQ_DF2_Cascade_Vector8_FP(middle, last) \ - __asm volatile("MCR p0,#0x1,r2,c2,c0,#6"); /* write biquad1*/ \ - if (middle) \ - { \ - __asm volatile("MCR p0,#0x1,r5,c0,c0,#6"); /* write biquad0*/ \ - __asm volatile("MRRC p0,#0,r5,r2,c1"); /* read both biquad*/ \ - } \ - else \ - { \ - __asm volatile("MRC p0,#0x1,r2,c2,c0,#0"); /* read biquad1*/ \ - } \ - __asm volatile("MCR p0,#0x1,r3,c2,c0,#6"); /* write biquad1*/ \ - __asm volatile("MCR p0,#0x1,r2,c0,c0,#6"); /* write biquad0*/ \ - if (middle) \ - { \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store last two results*/ \ - } \ - __asm volatile("LDRD r4,r5,[r0],#8"); /* load next 2 datas */ \ - __asm volatile("MRRC p0,#0,r2,r3,c1"); /* read both biquad*/ \ - __asm volatile("MCR p0,#0x1,r4,c2,c0,#6"); /* write biquad1*/ \ - __asm volatile("MCR p0,#0x1,r3,c0,c0,#6"); /* write biquad0*/ \ - __asm volatile("LDRD r6,r7,[r0],#8"); \ - __asm volatile("MRRC p0,#0,r3,r4,c1"); \ - __asm volatile("MCR p0,#0x1,r5,c2,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r4,c0,c0,#6"); \ - __asm volatile("STRD r2,r3,[r1],#8"); /* store first two results */ \ - __asm volatile("MRRC p0,#0,r4,r5,c1"); \ - __asm volatile("MCR p0,#0x1,r6,c2,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r5,c0,c0,#6"); \ - __asm volatile("STR r4,[r1],#4"); \ - __asm volatile("MRRC p0,#0,r5,r6,c1"); \ - __asm volatile("MCR p0,#0x1,r7,c2,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r6,c0,c0,#6"); \ - __asm volatile("STR r5,[r1],#4"); \ - __asm volatile("LDRD r4,r5,[r0],#8"); \ - __asm volatile("MRRC p0,#0,r6,r7,c1"); \ - __asm volatile("MCR p0,#0x1,r4,c2,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r7,c0,c0,#6"); \ - if (!last) \ - { \ - __asm volatile("LDRD r2,r3,[r0],#8"); /* load first two of next 8 */ \ - } \ - __asm volatile("MRRC p0,#0,r7,r4,c1"); \ - __asm volatile("MCR p0,#0x1,r5,c2,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r4,c0,c0,#6"); \ - __asm volatile("STRD r6,r7,[r1],#8"); /* store third two results */ \ - __asm volatile("MRRC p0,#0,r4,r5,c1"); \ - if (last) \ - { \ - __asm volatile("MCR p0,#0x1,r5,c0,c0,#6"); /* write biquad0*/ \ - __asm volatile("MRC p0,#0x1,r5,c0,c0,#0"); /* read biquad0*/ \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ - } - -/*! - * @brief Fixed data vector direct form II biquad cascade filter. - * - * The input and output data are fixed data. The data flow is - * input -> biquad side 1 -> biquad side 0 -> output. - * - * @code - #define VECTOR_LEN 16 - int32_t input[VECTOR_LEN] = {1024.0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - int32_t output[VECTOR_LEN]; - pq_biquad_state_t state0 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - pq_biquad_state_t state1 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state0); - PQ_BiquadRestoreInternalState(POWERQUAD, 1, &state1); - - PQ_Initiate_Vector_Func(pSrc, pDst); - PQ_DF2_Cascade_Vector8_FX(false, false); - PQ_DF2_Cascade_Vector8_FX(true, true); - PQ_End_Vector_Func(); - @endcode - * - */ -#define PQ_DF2_Cascade_Vector8_FX(middle, last) \ - __asm volatile("MCR p0,#0x1,r2,c3,c0,#6"); /* write biquad1*/ \ - if (middle) \ - { \ - __asm volatile("MCR p0,#0x1,r5,c1,c0,#6"); /* write biquad0*/ \ - __asm volatile("MRC p0,#0x1,r5,c1,c0,#0"); /* read biquad0*/ \ - __asm volatile("MRC p0,#0x1,r2,c3,c0,#0"); /* read biquad1*/ \ - } \ - else \ - { \ - __asm volatile("MRC p0,#0x1,r2,c3,c0,#0"); /* read biquad1*/ \ - } \ - __asm volatile("MCR p0,#0x1,r3,c3,c0,#6"); /* write biquad1*/ \ - __asm volatile("MCR p0,#0x1,r2,c1,c0,#6"); /* write biquad0*/ \ - if (middle) \ - { \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store last two results*/ \ - } \ - __asm volatile("LDRD r4,r5,[r0],#8"); /* load next 2 datas */ \ - __asm volatile("MRC p0,#0x1,r2,c1,c0,#0"); /* read biquad0*/ \ - __asm volatile("MRC p0,#0x1,r3,c3,c0,#0"); /* read biquad1*/ \ - __asm volatile("MCR p0,#0x1,r4,c3,c0,#6"); /* write biquad1*/ \ - __asm volatile("MCR p0,#0x1,r3,c1,c0,#6"); /* write biquad0*/ \ - __asm volatile("LDRD r6,r7,[r0],#8"); \ - __asm volatile("MRC p0,#0x1,r3,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r4,c3,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r5,c3,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r4,c1,c0,#6"); \ - __asm volatile("STRD r2,r3,[r1],#8"); \ - __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r5,c3,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r6,c3,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r5,c1,c0,#6"); \ - __asm volatile("STR r4,[r1],#4"); \ - __asm volatile("MRC p0,#0x1,r5,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r6,c3,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r7,c3,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r6,c1,c0,#6"); \ - __asm volatile("STR r5,[r1],#4"); \ - __asm volatile("LDRD r4,r5,[r0],#8"); \ - __asm volatile("MRC p0,#0x1,r6,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r7,c3,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r4,c3,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r7,c1,c0,#6"); \ - if (!last) \ - { \ - __asm volatile("LDRD r2,r3,[r0],#8"); /* load first two of next 8 */ \ - } \ - __asm volatile("MRC p0,#0x1,r7,c1,c0,#0"); \ - __asm volatile("MRC p0,#0x1,r4,c3,c0,#0"); \ - __asm volatile("MCR p0,#0x1,r5,c3,c0,#6"); \ - __asm volatile("MCR p0,#0x1,r4,c1,c0,#6"); \ - __asm volatile("STRD r6,r7,[r1],#8"); /* store third two results */ \ - __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); /* read biquad0*/ \ - __asm volatile("MRC p0,#0x1,r5,c3,c0,#0"); /* read biquad1*/ \ - if (last) \ - { \ - __asm volatile("MCR p0,#0x1,r5,c1,c0,#6"); /* write biquad0*/ \ - __asm volatile("MRC p0,#0x1,r5,c1,c0,#0"); /* read biquad0*/ \ - __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ - } - -/*! - * @brief Float data vector direct form II biquad cascade filter. - * - * The input and output data are float data. The data flow is - * input -> biquad side 1 -> biquad side 0 -> output. - * - * @code - #define VECTOR_LEN 8 - float input[VECTOR_LEN] = {1, 2, 3, 4, 5, 6, 7, 8}; - float output[VECTOR_LEN]; - pq_biquad_state_t state0 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - pq_biquad_state_t state1 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state0); - PQ_BiquadRestoreInternalState(POWERQUAD, 1, &state1); - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8BiqaudDf2CascadeF32(); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8BiqaudDf2CascadeF32() \ - __asm volatile( \ - "1: \n" \ - " MCR p0,#0x1,r4,c2,c0,#2 \n" /* write biquad1*/ \ - " CMP r3, #0 \n" \ - " ITTE NE \n" \ - " MCRNE p0,#0x1,r7,c0,c0,#2 \n" /* write biquad0*/ \ - " MRRCNE p0,#0,r7,r4,c1 \n" /* read both biquad*/ \ - " MRCEQ p0,#0x1,r4,c2,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r5,c2,c0,#2 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r4,c0,c0,#2 \n" /* write biquad0*/ \ - " CMP r3, #0 \n" \ - " ITE NE \n" \ - " STRDNE r6,r7,[r1],#8 \n" /* store last two results*/ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ - " MRRC p0,#0,r4,r5,c1 \n" /* read both biquad*/ \ - " MCR p0,#0x1,r6,c2,c0,#2 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r5,c0,c0,#2 \n" /* write biquad0*/ \ - " MRRC p0,#0,r5,r6,c1 \n" /* read both biquad*/ \ - " MCR p0,#0x1,r7,c2,c0,#2 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r6,c0,c0,#2 \n" /* write biquad0*/ \ - " MRRC p0,#0,r6,r7,c1 \n" /* read both biquad*/ \ - " MCR p0,#0x1,r8,c2,c0,#2 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r7,c0,c0,#2 \n" /* write biquad0*/ \ - " MRRC p0,#0,r7,r8,c1 \n" /* read both biquad*/ \ - " MCR p0,#0x1,r9,c2,c0,#2 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r8,c0,c0,#2 \n" /* write biquad0*/ \ - " STMIA r1!,{R4-R7} \n" /* store first and second two results */ \ - " LDRD r6,r7,[r0],#8 \n" /* load last 2 of the 8 */ \ - " MRRC p0,#0,r8,r9,c1 \n" /* read both biquad*/ \ - " MCR p0,#0x1,r6,c2,c0,#2 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r9,c0,c0,#2 \n" /* write biquad0*/ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " IT NE \n" \ - " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ - " MRRC p0,#0,r9,r6,c1 \n" /* read both biquad*/ \ - " MCR p0,#0x1,r7,c2,c0,#2 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r6,c0,c0,#2 \n" /* write biquad0*/ \ - " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ - " MRRC p0,#0,r6,r7,c1 \n" /* read both biquad*/ \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " MCR p0,#0x1,r7,c0,c0,#2 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r7,c0,c0,#0 \n" /* read biquad0*/ \ - " STRD r6,r7,[r1],#8 \n" /* store fourth two results */ \ - ) - -/*! - * @brief Fixed 32-bit data vector direct form II biquad cascade filter. - * - * The input and output data are fixed 32-bit data. The data flow is - * input -> biquad side 1 -> biquad side 0 -> output. - * - * @code - #define VECTOR_LEN 8 - int32_t input[VECTOR_LEN] = {1, 2, 3, 4, 5, 6, 7, 8}; - int32_t output[VECTOR_LEN]; - pq_biquad_state_t state0 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - pq_biquad_state_t state1 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state0); - PQ_BiquadRestoreInternalState(POWERQUAD, 1, &state1); - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8BiqaudDf2CascadeFixed32(); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8BiqaudDf2CascadeFixed32() \ - __asm volatile( \ - "1: \n" \ - " MCR p0,#0x1,r4,c3,c0,#6 \n" /* write biquad1*/ \ - " CMP r3, #0 \n" \ - " ITTTE NE \n" \ - " MCRNE p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ - " MRCNE p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ - " MRCNE p0,#0x1,r4,c3,c0,#0 \n" /* read biquad1*/ \ - " MRCEQ p0,#0x1,r4,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r5,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r4,c1,c0,#6 \n" /* write biquad0*/ \ - " CMP r3, #0 \n" \ - " ITE NE \n" \ - " STRDNE r6,r7,[r1],#8 \n" /* store last two results*/ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ - " MRC p0,#0x1,r4,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r5,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r6,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r5,c1,c0,#6 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r5,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r6,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r7,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r7,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r8,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r8,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r9,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r8,c1,c0,#6 \n" /* write biquad0*/ \ - " STMIA r1!,{R4-R7} \n" /* store first and second two results */ \ - " LDRD r6,r7,[r0],#8 \n" /* load last 2 of the 8 */ \ - " MRC p0,#0x1,r8,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r9,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r6,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r9,c1,c0,#6 \n" /* write biquad0*/ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " IT NE \n" \ - " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ - " MRC p0,#0x1,r9,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r6,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r7,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ - " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ - " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r7,c3,c0,#0 \n" /* read biquad1*/ \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ - " STRD r6,r7,[r1],#8 \n" /* store fourth two results */ \ - ) - -/*! - * @brief Fixed 16-bit data vector direct form II biquad cascade filter. - * - * The input and output data are fixed 16-bit data. The data flow is - * input -> biquad side 1 -> biquad side 0 -> output. - * - * @code - #define VECTOR_LEN 8 - int32_t input[VECTOR_LEN] = {1, 2, 3, 4, 5, 6, 7, 8}; - int32_t output[VECTOR_LEN]; - pq_biquad_state_t state0 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - pq_biquad_state_t state1 = - { - .param = - { - .a_1 = xxx, - .a_2 = xxx, - .b_0 = xxx, - .b_1 = xxx, - .b_2 = xxx, - }, - }; - - PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state0); - PQ_BiquadRestoreInternalState(POWERQUAD, 1, &state1); - - PQ_StartVector(input, output, VECTOR_LEN); - PQ_Vector8BiqaudDf2CascadeFixed16(); - PQ_EndVector(); - @endcode - * - */ -#define PQ_Vector8BiqaudDf2CascadeFixed16() \ - __asm volatile( \ - "1: \n" \ - " MCR p0,#0x1,r4,c3,c0,#6 \n" /* write biquad1*/ \ - " CMP r3, #0 \n" \ - " ITTTE NE \n" \ - " MCRNE p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ - " MRCNE p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ - " MRCNE p0,#0x1,r4,c3,c0,#0 \n" /* read biquad1*/ \ - " MRCEQ p0,#0x1,r4,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r5,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r4,c1,c0,#6 \n" /* write biquad0*/ \ - " CMP r3, #0 \n" \ - " ITTE NE \n" \ - " STRHNE r6,[r1],#2 \n" /* store last two results*/ \ - " STRHNE r7,[r1],#2 \n" /* store last two results*/ \ - " MOVEQ r3, #1 \n" /* middle = 1 */ \ - " LDRSH r6,[r0],#2 \n" /* load next 2 of the 8*/ \ - " LDRSH r7,[r0],#2 \n" /* load next 2 of the 8*/ \ - " MRC p0,#0x1,r4,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r5,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r6,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r5,c1,c0,#6 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r5,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r6,c3,c0,#0 \n" /* read biquad1*/ \ - " LDRSH r8,[r0],#2 \n" /* load next 2 of the 8*/ \ - " LDRSH r9,[r0],#2 \n" /* load next 2 of the 8*/ \ - " MCR p0,#0x1,r7,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r7,c3,c0,#0 \n" /* read biquad1*/ \ - " STRH r4,[r1],#2 \n" /* store first 4 results */ \ - " STRH r5,[r1],#2 \n" /* store first 4 results */ \ - " MCR p0,#0x1,r8,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r8,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r9,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r8,c1,c0,#6 \n" /* write biquad0*/ \ - " STRH r6,[r1],#2 \n" /* store first 4 results */ \ - " STRH r7,[r1],#2 \n" /* store first 4 results */ \ - " LDRSH r6,[r0],#2 \n" /* load last 2 of the 8*/ \ - " LDRSH r7,[r0],#2 \n" /* load last 2 of the 8*/ \ - " MRC p0,#0x1,r8,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r9,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r6,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r9,c1,c0,#6 \n" /* write biquad0*/ \ - " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ - " ITT NE \n" \ - " LDRSHNE r4,[r0],#2 \n" /* load first two of next 8*/ \ - " LDRSHNE r5,[r0],#2 \n" /* load first two of next 8*/ \ - " MRC p0,#0x1,r9,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r6,c3,c0,#0 \n" /* read biquad1*/ \ - " MCR p0,#0x1,r7,c3,c0,#6 \n" /* write biquad1*/ \ - " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ - " STRH r8,[r1],#2 \n" /* store third two results */ \ - " STRH r9,[r1],#2 \n" /* store third two results */ \ - " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ - " MRC p0,#0x1,r7,c3,c0,#0 \n" /* read biquad1*/ \ - " CMP r2, #0 \n" /* if (length == 0) */ \ - " BNE 1b \n" \ - " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ - " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ - " STRH r6,[r1],#2 \n" /* store fourth two results */ \ - " STRH r7,[r1],#2 \n" /* store fourth two results */ \ - ) - -/*! @brief Make the length used for matrix functions. */ -#define POWERQUAD_MAKE_MATRIX_LEN(mat1Row, mat1Col, mat2Col) \ - (((uint32_t)(mat1Row) << 0U) | ((uint32_t)(mat1Col) << 8U) | ((uint32_t)(mat2Col) << 16U)) - -/*! @brief Convert Q31 to float. */ -#define PQ_Q31_2_FLOAT(x) (((float)(x)) / 2147483648.0f) - -/*! @brief Convert Q15 to float. */ -#define PQ_Q15_2_FLOAT(x) (((float)(x)) / 32768.0f) - -/*! @brief powerquad computation engine */ -typedef enum -{ - kPQ_CP_PQ = 0, /*!< Math engine.*/ - kPQ_CP_MTX = 1, /*!< Matrix engine.*/ - kPQ_CP_FFT = 2, /*!< FFT engine.*/ - kPQ_CP_FIR = 3, /*!< FIR engine.*/ - kPQ_CP_CORDIC = 5 /*!< CORDIC engine.*/ -} pq_computationengine_t; - -/*! @brief powerquad data structure format type */ -typedef enum -{ - kPQ_16Bit = 0, /*!< Int16 Fixed point.*/ - kPQ_32Bit = 1, /*!< Int32 Fixed point.*/ - kPQ_Float = 2 /*!< Float point.*/ -} pq_format_t; - -/*! @brief Coprocessor prescale */ -typedef struct -{ - int8_t inputPrescale; /*!< Input prescale.*/ - int8_t outputPrescale; /*!< Output prescale.*/ - int8_t outputSaturate; /*!< Output saturate at n bits, for example 0x11 is 8 bit space, - the value will be truncated at +127 or -128.*/ -} pq_prescale_t; - -/*! @brief powerquad data structure format */ -typedef struct -{ - pq_format_t inputAFormat; /*!< Input A format.*/ - int8_t inputAPrescale; /*!< Input A prescale, for example 1.5 can be 1.5*2^n if you scale by 'shifting' - ('scaling' by a factor of n).*/ - pq_format_t inputBFormat; /*!< Input B format.*/ - int8_t inputBPrescale; /*!< Input B prescale.*/ - pq_format_t outputFormat; /*!< Out format.*/ - int8_t outputPrescale; /*!< Out prescale.*/ - pq_format_t tmpFormat; /*!< Temp format.*/ - int8_t tmpPrescale; /*!< Temp prescale.*/ - pq_format_t machineFormat; /*!< Machine format.*/ - uint32_t *tmpBase; /*!< Tmp base address.*/ -} pq_config_t; - -/*! @brief Struct to save biquad parameters. */ -typedef struct _pq_biquad_param -{ - float v_n_1; /*!< v[n-1], set to 0 when initialization. */ - float v_n; /*!< v[n], set to 0 when initialization. */ - float a_1; /*!< a[1] */ - float a_2; /*!< a[2] */ - float b_0; /*!< b[0] */ - float b_1; /*!< b[1] */ - float b_2; /*!< b[2] */ -} pq_biquad_param_t; - -/*! @brief Struct to save biquad state. */ -typedef struct _pq_biquad_state -{ - pq_biquad_param_t param; /*!< Filter parameter. */ - uint32_t compreg; /*!< Internal register, set to 0 when initialization. */ -} pq_biquad_state_t; - -/*! @brief Instance structure for the direct form II Biquad cascade filter */ -typedef struct -{ - uint8_t numStages; /**< Number of 2nd order stages in the filter.*/ - pq_biquad_state_t *pState; /**< Points to the array of state coefficients.*/ -} pq_biquad_cascade_df2_instance; - -/*! @brief CORDIC iteration */ -typedef enum -{ - kPQ_Iteration_8 = 0, /*!< Iterate 8 times.*/ - kPQ_Iteration_16, /*!< Iterate 16 times.*/ - kPQ_Iteration_24 /*!< Iterate 24 times.*/ -} pq_cordic_iter_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name POWERQUAD functional Operation - * @{ - */ - -/*! - * @brief Get default configuration. - * - * This function initializes the POWERQUAD configuration structure to a default value. - * FORMAT register field definitions - * Bits[15:8] scaler (for scaled 'q31' formats) - * Bits[5:4] external format. 00b=q15, 01b=q31, 10b=float - * Bits[1:0] internal format. 00b=q15, 01b=q31, 10b=float - * POWERQUAD->INAFORMAT = (config->inputAPrescale << 8) | (config->inputAFormat << 4) | config->machineFormat - * - * For all Powerquad operations internal format must be float (with the only exception being - * the FFT related functions, ie FFT/IFFT/DCT/IDCT which must be set to q31). - * The default values are: - * config->inputAFormat = kPQ_Float; - * config->inputAPrescale = 0; - * config->inputBFormat = kPQ_Float; - * config->inputBPrescale = 0; - * config->outputFormat = kPQ_Float; - * config->outputPrescale = 0; - * config->tmpFormat = kPQ_Float; - * config->tmpPrescale = 0; - * config->machineFormat = kPQ_Float; - * config->tmpBase = 0xE0000000; - * - * @param config Pointer to "pq_config_t" structure. - */ -void PQ_GetDefaultConfig(pq_config_t *config); - -/*! - * @brief Set configuration with format/prescale. - * - * @param base POWERQUAD peripheral base address - * @param config Pointer to "pq_config_t" structure. - */ -void PQ_SetConfig(POWERQUAD_Type *base, const pq_config_t *config); - -/*! - * @brief set coprocessor scaler for coprocessor instructions, this function is used to - * set output saturation and scaleing for input/output. - * - * @param base POWERQUAD peripheral base address - * @param prescale Pointer to "pq_prescale_t" structure. - */ -static inline void PQ_SetCoprocessorScaler(POWERQUAD_Type *base, const pq_prescale_t *prescale) -{ - assert(prescale); - - base->CPPRE = POWERQUAD_CPPRE_CPPRE_IN(prescale->inputPrescale) | - POWERQUAD_CPPRE_CPPRE_OUT(prescale->outputPrescale) | - ((uint32_t)prescale->outputSaturate << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT); -} - -/*! - * @brief Initializes the POWERQUAD module. - * - * @param base POWERQUAD peripheral base address. - */ -void PQ_Init(POWERQUAD_Type *base); - -/*! - * @brief De-initializes the POWERQUAD module. - * - * @param base POWERQUAD peripheral base address. - */ -void PQ_Deinit(POWERQUAD_Type *base); - -/*! - * @brief Set format for non-coprecessor instructions. - * - * @param base POWERQUAD peripheral base address - * @param engine Computation engine - * @param format Data format - */ -void PQ_SetFormat(POWERQUAD_Type *base, pq_computationengine_t engine, pq_format_t format); - -/*! - * @brief Wait for the completion. - * - * @param base POWERQUAD peripheral base address - */ -static inline void PQ_WaitDone(POWERQUAD_Type *base) -{ - /* wait for the completion */ - while ((base->CONTROL & INST_BUSY) == INST_BUSY) - { - __WFE(); - } -} - -/*! - * @brief Processing function for the floating-point natural log. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - */ -static inline void PQ_LnF32(float *pSrc, float *pDst) -{ - _pq_ln0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readAdd0(); -} - -/*! - * @brief Processing function for the floating-point reciprocal. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - */ -static inline void PQ_InvF32(float *pSrc, float *pDst) -{ - _pq_inv0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readMult0(); -} - -/*! - * @brief Processing function for the floating-point square-root. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - */ -static inline void PQ_SqrtF32(float *pSrc, float *pDst) -{ - _pq_sqrt0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readMult0(); -} - -/*! - * @brief Processing function for the floating-point inverse square-root. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - */ -static inline void PQ_InvSqrtF32(float *pSrc, float *pDst) -{ - _pq_invsqrt0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readMult0(); -} - -/*! - * @brief Processing function for the floating-point natural exponent. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - */ -static inline void PQ_EtoxF32(float *pSrc, float *pDst) -{ - _pq_etox0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readMult0(); -} - -/*! - * @brief Processing function for the floating-point natural exponent with negative parameter. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - */ -static inline void PQ_EtonxF32(float *pSrc, float *pDst) -{ - _pq_etonx0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readMult0(); -} - -/*! - * @brief Processing function for the floating-point sine. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - */ -static inline void PQ_SinF32(float *pSrc, float *pDst) -{ - _pq_sin0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readAdd0(); -} - -/*! - * @brief Processing function for the floating-point cosine. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - */ -static inline void PQ_CosF32(float *pSrc, float *pDst) -{ - _pq_cos0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readAdd0(); -} - -/*! - * @brief Processing function for the floating-point biquad. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - */ -static inline void PQ_BiquadF32(float *pSrc, float *pDst) -{ - _pq_biquad0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readAdd0(); -} - -/*! - * @brief Processing function for the floating-point division. - * - * Get x1 / x2. - * - * @param x1 x1 - * @param x2 x2 - * @param *pDst points to the block of output data - */ -static inline void PQ_DivF32(float *x1, float *x2, float *pDst) -{ - uint32_t X1 = *(uint32_t *)x1; - uint32_t X2 = *(uint32_t *)x2; - uint64_t input = (uint64_t)(X2) | ((uint64_t)(X1) << 32U); - - _pq_div0(input); - *(int32_t *)pDst = _pq_readMult0(); -} - -/*! - * @brief Processing function for the floating-point biquad. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - */ -static inline void PQ_Biquad1F32(float *pSrc, float *pDst) -{ - _pq_biquad1(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readAdd1(); -} - -/*! - * @brief Processing function for the fixed natural log. - * - * @param val value to be calculated - * @return returns ln(val). - */ -static inline int32_t PQ_LnFixed(int32_t val) -{ - _pq_ln_fx0(val); - return _pq_readAdd0_fx(); -} - -/*! - * @brief Processing function for the fixed reciprocal. - * - * @param val value to be calculated - * @return returns inv(val). - */ -static inline int32_t PQ_InvFixed(int32_t val) -{ - _pq_inv_fx0(val); - return _pq_readMult0_fx(); -} - -/*! - * @brief Processing function for the fixed square-root. - * - * @param val value to be calculated - * @return returns sqrt(val). - */ -static inline uint32_t PQ_SqrtFixed(uint32_t val) -{ - _pq_sqrt_fx0(val); - return _pq_readMult0_fx(); -} - -/*! - * @brief Processing function for the fixed inverse square-root. - * - * @param val value to be calculated - * @return returns 1/sqrt(val). - */ -static inline int32_t PQ_InvSqrtFixed(int32_t val) -{ - _pq_invsqrt_fx0(val); - return _pq_readMult0_fx(); -} - -/*! - * @brief Processing function for the Fixed natural exponent. - * - * @param val value to be calculated - * @return returns etox^(val). - */ -static inline int32_t PQ_EtoxFixed(int32_t val) -{ - _pq_etox_fx0(val); - return _pq_readMult0_fx(); -} - -/*! - * @brief Processing function for the fixed natural exponent with negative parameter. - * - * @param val value to be calculated - * @return returns etonx^(val). - */ -static inline int32_t PQ_EtonxFixed(int32_t val) -{ - _pq_etonx_fx0(val); - return _pq_readMult0_fx(); -} - -/*! - * @brief Processing function for the fixed sine. - * - * @param val value to be calculated - * @return returns sin(val). - */ -static inline int32_t PQ_SinQ31(int32_t val) -{ - int32_t ret; - uint32_t cppre; -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-aliasing" -#endif - const int32_t magic = 0x30c90fdb; - float valFloat = *(const float *)(&magic) * (float)val; - val = *(int32_t *)(&valFloat); -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif -#endif - - cppre = POWERQUAD->CPPRE; - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); - -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - _pq_sin0(val); - - ret = _pq_readAdd0(); - ret = _pq_readAdd0_fx(); -#else - _pq_sin_fx0(val); - ret = _pq_readAdd0_fx(); -#endif - - POWERQUAD->CPPRE = cppre; - - return ret; -} - -/*! - * @brief Processing function for the fixed sine. - * - * @param val value to be calculated - * @return returns sin(val). - */ -static inline int16_t PQ_SinQ15(int16_t val) -{ - int32_t ret; - uint32_t cppre; -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-aliasing" -#endif - int32_t val32 = val; - const int32_t magic = 0x30c90fdb; - float valFloat = *(const float *)(&magic) * (float)(val32 << 16); - val32 = *(int32_t *)(&valFloat); -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif -#endif - - cppre = POWERQUAD->CPPRE; - /* Don't use 15 here, it is wrong then val is 0x4000 */ - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); - -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - _pq_sin0(val32); - - ret = _pq_readAdd0(); - ret = _pq_readAdd0_fx() >> 16; -#else - _pq_sin_fx0((uint32_t)val << 16); - ret = (_pq_readAdd0_fx()) >> 16; -#endif - - POWERQUAD->CPPRE = cppre; - - return (int16_t)ret; -} - -/*! - * @brief Processing function for the fixed cosine. - * - * @param val value to be calculated - * @return returns cos(val). - */ -static inline int32_t PQ_CosQ31(int32_t val) -{ - int32_t ret; - uint32_t cppre; -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-aliasing" -#endif - const int32_t magic = 0x30c90fdb; - float valFloat = *(const float *)(&magic) * (float)val; - val = *(int32_t *)(&valFloat); -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif -#endif - - cppre = POWERQUAD->CPPRE; - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); - -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - _pq_cos0(val); - - ret = _pq_readAdd0(); - ret = _pq_readAdd0_fx(); -#else - _pq_cos_fx0(val); - ret = _pq_readAdd0_fx(); -#endif - - POWERQUAD->CPPRE = cppre; - - return ret; -} - -/*! - * @brief Processing function for the fixed sine. - * - * @param val value to be calculated - * @return returns sin(val). - */ -static inline int16_t PQ_CosQ15(int16_t val) -{ - int32_t ret; - uint32_t cppre; -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-aliasing" -#endif - int32_t val32 = val; - const int32_t magic = 0x30c90fdb; - float valFloat = *(const float *)(&magic) * (float)(val32 << 16); - val32 = *(int32_t *)(&valFloat); -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif -#endif - - cppre = POWERQUAD->CPPRE; - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); - -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - _pq_cos0(val32); - - ret = _pq_readAdd0(); - ret = _pq_readAdd0_fx() >> 16; -#else - _pq_cos_fx0((uint32_t)val << 16); - ret = (_pq_readAdd0_fx()) >> 16; -#endif - - POWERQUAD->CPPRE = cppre; - - return (int16_t)ret; -} - -/*! - * @brief Processing function for the fixed biquad. - * - * @param val value to be calculated - * @return returns biquad(val). - */ -static inline int32_t PQ_BiquadFixed(int32_t val) -{ - _pq_biquad0_fx(val); - return _pq_readAdd0_fx(); -} - -/*! - * @brief Processing function for the floating-point vectorised natural log. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorLnF32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised reciprocal. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorInvF32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised square-root. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorSqrtF32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised inverse square-root. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorInvSqrtF32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised natural exponent. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorEtoxF32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised natural exponent with negative parameter. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorEtonxF32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised sine - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorSinF32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised cosine. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorCosF32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the Q31 vectorised natural log. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorLnFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the Q31 vectorised reciprocal. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorInvFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 32-bit integer vectorised square-root. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorSqrtFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 32-bit integer vectorised inverse square-root. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorInvSqrtFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 32-bit integer vectorised natural exponent. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorEtoxFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 32-bit integer vectorised natural exponent with negative parameter. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorEtonxFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the Q15 vectorised sine - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorSinQ15(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the Q15 vectorised cosine. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorCosQ15(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the Q31 vectorised sine - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorSinQ31(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the Q31 vectorised cosine. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorCosQ31(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 16-bit integer vectorised natural log. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorLnFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 16-bit integer vectorised reciprocal. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorInvFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 16-bit integer vectorised square-root. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorSqrtFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 16-bit integer vectorised inverse square-root. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorInvSqrtFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 16-bit integer vectorised natural exponent. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorEtoxFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 16-bit integer vectorised natural exponent with negative parameter. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block of input data. - */ -void PQ_VectorEtonxFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised biquad direct form II. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param length the block size of input data. - */ -void PQ_VectorBiqaudDf2F32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the 32-bit integer vectorised biquad direct form II. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param blocksSize the block size of input data - */ -void PQ_VectorBiqaudDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 16-bit integer vectorised biquad direct form II. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param blocksSize the block size of input data - */ -void PQ_VectorBiqaudDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the floating-point vectorised biquad direct form II. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param blocksSize the block size of input data - */ -void PQ_VectorBiqaudCascadeDf2F32(float *pSrc, float *pDst, int32_t length); - -/*! - * @brief Processing function for the 32-bit integer vectorised biquad direct form II. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param blocksSize the block size of input data - */ -void PQ_VectorBiqaudCascadeDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length); - -/*! - * @brief Processing function for the 16-bit integer vectorised biquad direct form II. - * - * @param *pSrc points to the block of input data - * @param *pDst points to the block of output data - * @param blocksSize the block size of input data - */ -void PQ_VectorBiqaudCascadeDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length); - -/*! - * @brief Processing function for the fixed inverse trigonometric. - * - * @param base POWERQUAD peripheral base address - * @param x value of opposite - * @param y value of adjacent - * @param iteration iteration times - * @return The return value is in the range of -2^27 to 2^27, which means -pi to pi. - * @note The sum of x and y should not exceed the range of int32_t. - * @note Larger input number gets higher output accuracy, for example the arctan(0.5), - * the result of PQ_ArctanFixed(POWERQUAD, 100000, 200000, kPQ_Iteration_24) is more - * accurate than PQ_ArctanFixed(POWERQUAD, 1, 2, kPQ_Iteration_24). - */ -int32_t PQ_ArctanFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration); - -/*! - * @brief Processing function for the fixed inverse trigonometric. - * - * @param base POWERQUAD peripheral base address - * @param x value of opposite - * @param y value of adjacent - * @param iteration iteration times - * @return The return value is in the range of -2^27 to 2^27, which means -1 to 1. - * @note The sum of x and y should not exceed the range of int32_t. - * @note Larger input number gets higher output accuracy, for example the arctanh(0.5), - * the result of PQ_ArctanhFixed(POWERQUAD, 100000, 200000, kPQ_Iteration_24) is more - * accurate than PQ_ArctanhFixed(POWERQUAD, 1, 2, kPQ_Iteration_24). - */ -int32_t PQ_ArctanhFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration); - -/*! - * @brief Processing function for the fixed biquad. - * - * @param val value to be calculated - * @return returns biquad(val). - */ -static inline int32_t PQ_Biquad1Fixed(int32_t val) -{ - _pq_biquad1_fx(val); - return _pq_readAdd1_fx(); -} - -/*! - * @brief Processing function for the complex FFT. - * - * @param base POWERQUAD peripheral base address - * @param length number of input samples - * @param pData input data - * @param pResult output data. - */ -void PQ_TransformCFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); - -/*! - * @brief Processing function for the real FFT. - * - * @param base POWERQUAD peripheral base address - * @param length number of input samples - * @param pData input data - * @param pResult output data. - */ -void PQ_TransformRFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); - -/*! - * @brief Processing function for the inverse complex FFT. - * - * @param base POWERQUAD peripheral base address - * @param length number of input samples - * @param pData input data - * @param pResult output data. - */ -void PQ_TransformIFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); - -/*! - * @brief Processing function for the complex DCT. - * - * @param base POWERQUAD peripheral base address - * @param length number of input samples - * @param pData input data - * @param pResult output data. - */ -void PQ_TransformCDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); - -/*! - * @brief Processing function for the real DCT. - * - * @param base POWERQUAD peripheral base address - * @param length number of input samples - * @param pData input data - * @param pResult output data. - */ -void PQ_TransformRDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); - -/*! - * @brief Processing function for the inverse complex DCT. - * - * @param base POWERQUAD peripheral base address - * @param length number of input samples - * @param pData input data - * @param pResult output data. - */ -void PQ_TransformIDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); - -/*! - * @brief Processing function for backup biquad context. - * - * @param base POWERQUAD peripheral base address - * @param biquad_num biquad side - * @param state point to states. - */ -void PQ_BiquadBackUpInternalState(POWERQUAD_Type *base, int32_t biquad_num, pq_biquad_state_t *state); - -/*! - * @brief Processing function for restore biquad context. - * - * @param base POWERQUAD peripheral base address - * @param biquad_num biquad side - * @param state point to states. - */ -void PQ_BiquadRestoreInternalState(POWERQUAD_Type *base, int32_t biquad_num, pq_biquad_state_t *state); - -/*! - * @brief Initialization function for the direct form II Biquad cascade filter. - * - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pState points to the state buffer. - */ -void PQ_BiquadCascadeDf2Init(pq_biquad_cascade_df2_instance *S, uint8_t numStages, pq_biquad_state_t *pState); - -/*! - * @brief Processing function for the floating-point direct form II Biquad cascade filter. - * - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void PQ_BiquadCascadeDf2F32(const pq_biquad_cascade_df2_instance *S, float *pSrc, float *pDst, uint32_t blockSize); - -/*! - * @brief Processing function for the Q31 direct form II Biquad cascade filter. - * - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void PQ_BiquadCascadeDf2Fixed32(const pq_biquad_cascade_df2_instance *S, - int32_t *pSrc, - int32_t *pDst, - uint32_t blockSize); - -/*! - * @brief Processing function for the Q15 direct form II Biquad cascade filter. - * - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void PQ_BiquadCascadeDf2Fixed16(const pq_biquad_cascade_df2_instance *S, - int16_t *pSrc, - int16_t *pDst, - uint32_t blockSize); - -/*! - * @brief Processing function for the FIR. - * - * @param base POWERQUAD peripheral base address - * @param pAData the first input sequence - * @param ALength number of the first input sequence - * @param pBData the second input sequence - * @param BLength number of the second input sequence - * @param pResult array for the output data - * @param opType operation type, could be PQ_FIR_FIR, PQ_FIR_CONVOLUTION, PQ_FIR_CORRELATION. - */ -void PQ_FIR( - POWERQUAD_Type *base, void *pAData, int32_t ALength, void *pBData, int32_t BLength, void *pResult, uint32_t opType); - -/*! - * @brief Processing function for the incremental FIR. - * This function can be used after pq_fir() for incremental FIR - * operation when new x data are available - * - * @param base POWERQUAD peripheral base address - * @param ALength number of input samples - * @param BLength number of taps - * @param xoffset offset for number of input samples - */ -void PQ_FIRIncrement(POWERQUAD_Type *base, int32_t ALength, int32_t BLength, int32_t xOffset); - -/*! - * @brief Processing function for the matrix addition. - * - * @param base POWERQUAD peripheral base address - * @param length rows and cols for matrix. LENGTH register configuration: - * LENGTH[23:16] = M2 cols - * LENGTH[15:8] = M1 cols - * LENGTH[7:0] = M1 rows - * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. - * @param pAData input matrix A - * @param pBData input matrix B - * @param pResult array for the output data. - */ -void PQ_MatrixAddition(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult); - -/*! - * @brief Processing function for the matrix subtraction. - * - * @param base POWERQUAD peripheral base address - * @param length rows and cols for matrix. LENGTH register configuration: - * LENGTH[23:16] = M2 cols - * LENGTH[15:8] = M1 cols - * LENGTH[7:0] = M1 rows - * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. - * @param pAData input matrix A - * @param pBData input matrix B - * @param pResult array for the output data. - */ -void PQ_MatrixSubtraction(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult); - -/*! - * @brief Processing function for the matrix multiplication. - * - * @param base POWERQUAD peripheral base address - * @param length rows and cols for matrix. LENGTH register configuration: - * LENGTH[23:16] = M2 cols - * LENGTH[15:8] = M1 cols - * LENGTH[7:0] = M1 rows - * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. - * @param pAData input matrix A - * @param pBData input matrix B - * @param pResult array for the output data. - */ -void PQ_MatrixMultiplication(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult); - -/*! - * @brief Processing function for the matrix product. - * - * @param base POWERQUAD peripheral base address - * @param length rows and cols for matrix. LENGTH register configuration: - * LENGTH[23:16] = M2 cols - * LENGTH[15:8] = M1 cols - * LENGTH[7:0] = M1 rows - * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. - * @param pAData input matrix A - * @param pBData input matrix B - * @param pResult array for the output data. - */ -void PQ_MatrixProduct(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult); - -/*! - * @brief Processing function for the vector dot product. - * - * @param base POWERQUAD peripheral base address - * @param length length of vector - * @param pAData input vector A - * @param pBData input vector B - * @param pResult array for the output data. - */ -void PQ_VectorDotProduct(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult); - -/*! - * @brief Processing function for the matrix inverse. - * - * @param base POWERQUAD peripheral base address - * @param length rows and cols for matrix. LENGTH register configuration: - * LENGTH[23:16] = M2 cols - * LENGTH[15:8] = M1 cols - * LENGTH[7:0] = M1 rows - * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. - * @param pData input matrix - * @param pTmpData input temporary matrix, pTmpData length not less than pData lenght and 1024 words is sufficient for - * the largest supported matrix. - * @param pResult array for the output data, round down for fixed point. - */ -void PQ_MatrixInversion(POWERQUAD_Type *base, uint32_t length, void *pData, void *pTmpData, void *pResult); - -/*! - * @brief Processing function for the matrix transpose. - * - * @param base POWERQUAD peripheral base address - * @param length rows and cols for matrix. LENGTH register configuration: - * LENGTH[23:16] = M2 cols - * LENGTH[15:8] = M1 cols - * LENGTH[7:0] = M1 rows - * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. - * @param pData input matrix - * @param pResult array for the output data. - */ -void PQ_MatrixTranspose(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); - -/*! - * @brief Processing function for the matrix scale. - * - * @param base POWERQUAD peripheral base address - * @param length rows and cols for matrix. LENGTH register configuration: - * LENGTH[23:16] = M2 cols - * LENGTH[15:8] = M1 cols - * LENGTH[7:0] = M1 rows - * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. - * @param misc scaling parameters - * @param pData input matrix - * @param pResult array for the output data. - */ -void PQ_MatrixScale(POWERQUAD_Type *base, uint32_t length, float misc, void *pData, void *pResult); - -/* @} */ - -#if defined(__cplusplus) -} - -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_POWERQUAD_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_basic.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_basic.c deleted file mode 100644 index 207527fe61..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_basic.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_powerquad.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.powerquad_basic" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -void PQ_GetDefaultConfig(pq_config_t *config) -{ - config->inputAFormat = kPQ_Float; - config->inputAPrescale = 0; - config->inputBFormat = kPQ_Float; - config->inputBPrescale = 0; - config->outputFormat = kPQ_Float; - config->outputPrescale = 0; - config->tmpFormat = kPQ_Float; - config->tmpPrescale = 0; - config->machineFormat = kPQ_Float; - config->tmpBase = (void *)0xE0000000U; -} - -void PQ_SetConfig(POWERQUAD_Type *base, const pq_config_t *config) -{ - assert(config); - - base->TMPBASE = (uint32_t)config->tmpBase; - base->INAFORMAT = - ((uint32_t)config->inputAPrescale << 8U) | ((uint32_t)config->inputAFormat << 4U) | config->machineFormat; - base->INBFORMAT = - ((uint32_t)config->inputBPrescale << 8U) | ((uint32_t)config->inputBFormat << 4U) | config->machineFormat; - base->TMPFORMAT = - ((uint32_t)config->tmpPrescale << 8U) | ((uint32_t)config->tmpFormat << 4U) | config->machineFormat; - base->OUTFORMAT = - ((uint32_t)config->outputPrescale << 8U) | ((uint32_t)config->outputFormat << 4U) | config->machineFormat; -} - -void PQ_Init(POWERQUAD_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_PowerQuad); -#endif -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - RESET_PeripheralReset(kPOWERQUAD_RST_SHIFT_RSTn); -#endif - - /* Enable event used for WFE. */ - base->EVENTEN = POWERQUAD_EVENTEN_EVENT_OFLOW_MASK | POWERQUAD_EVENTEN_EVENT_NAN_MASK | - POWERQUAD_EVENTEN_EVENT_FIXED_MASK | POWERQUAD_EVENTEN_EVENT_UFLOW_MASK | - POWERQUAD_EVENTEN_EVENT_BERR_MASK | POWERQUAD_EVENTEN_EVENT_COMP_MASK; -} - -void PQ_Deinit(POWERQUAD_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_PowerQuad); -#endif -} - -void PQ_SetFormat(POWERQUAD_Type *base, pq_computationengine_t engine, pq_format_t format) -{ - pq_config_t config; - - PQ_GetDefaultConfig(&config); - - /* 32-bit Float point */ - if (kPQ_Float == format) - { - config.inputAFormat = kPQ_Float; - config.inputAPrescale = 0; - config.inputBFormat = kPQ_Float; - config.inputBPrescale = 0; - config.outputFormat = kPQ_Float; - config.outputPrescale = 0; - config.tmpFormat = kPQ_Float; - config.tmpPrescale = 0; - } - /* 32-bit Fixed point */ - if (kPQ_32Bit == format) - { - config.inputAFormat = kPQ_32Bit; - config.inputAPrescale = 0; - config.inputBFormat = kPQ_32Bit; - config.inputBPrescale = 0; - config.outputFormat = kPQ_32Bit; - config.outputPrescale = 0; - config.tmpFormat = kPQ_Float; - config.tmpPrescale = 0; - } - /* 16-bit Fixed point */ - if (kPQ_16Bit == format) - { - config.inputAFormat = kPQ_16Bit; - config.inputAPrescale = 0; - config.inputBFormat = kPQ_16Bit; - config.inputBPrescale = 0; - config.outputFormat = kPQ_16Bit; - config.outputPrescale = 0; - config.tmpFormat = kPQ_Float; - config.tmpPrescale = 0; - } - - if (CP_FFT == engine) - { - config.machineFormat = kPQ_32Bit; - } - else - { - config.machineFormat = kPQ_Float; - } - - PQ_SetConfig(base, &config); -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_data.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_data.c deleted file mode 100644 index 9cee85b24e..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_data.c +++ /dev/null @@ -1,584 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.powerquad" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * @brief MATLAB script for calculating twiddle factor table for DCT is below,this gives phasor for FFTs twiddle at end - * of DCT, - * note that y is raw, scaled y is for fixed point multiplication. - * - * N=32; - * n=0; - * while(n - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -extern int32_t dct16_twiddle[32]; -extern int32_t dct32_twiddle[64]; -extern int32_t dct64_twiddle[128]; -extern int32_t dct128_twiddle[256]; -extern int32_t dct256_twiddle[512]; -extern int32_t dct512_twiddle[1024]; -extern int32_t idct16_twiddle[32]; -extern int32_t idct32_twiddle[64]; -extern int32_t idct64_twiddle[128]; -extern int32_t idct128_twiddle[256]; -extern int32_t idct256_twiddle[512]; -extern int32_t idct512_twiddle[1024]; -extern int32_t dct16_cosFactor[16]; -extern int32_t dct32_cosFactor[32]; -extern int32_t dct64_cosFactor[64]; -extern int32_t dct128_cosFactor[128]; -extern int32_t dct256_cosFactor[256]; -extern int32_t dct512_cosFactor[512]; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -#if defined(__cplusplus) -} - -#endif /* __cplusplus */ - -#endif /* _FSL_POWERQUAD_DATA_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_filter.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_filter.c deleted file mode 100644 index c0b5f44f37..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_filter.c +++ /dev/null @@ -1,373 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_powerquad.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.powerquad_filter" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -void PQ_VectorBiqaudDf2F32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_biquad0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readAdd0(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8BiquadDf2F32(); - PQ_EndVector(); - } -} - -void PQ_VectorBiqaudDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_biquad0_fx(*pSrc++); - *pDst++ = _pq_readAdd0_fx(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8BiquadDf2Fixed32(); - PQ_EndVector(); - } -} - -void PQ_VectorBiqaudDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_biquad0_fx(*pSrc++); - *pDst++ = _pq_readAdd0_fx(); - } - } - - if (length) - { - PQ_StartVectorFixed16(pSrc, pDst, length); - PQ_Vector8BiquadDf2Fixed16(); - PQ_EndVector(); - } -} - -void PQ_VectorBiqaudCascadeDf2F32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - - PQ_Biquad1F32(&pSrc[0], &pDst[0]); - - for (int i = 1; i < remainderBy8; i++) - { - _pq_biquad0(*(int32_t *)&pSrc[i - 1]); - _pq_biquad1(*(int32_t *)&pSrc[i]); - *(int32_t *)&pDst[i - 1] = _pq_readAdd0(); - *(int32_t *)&pDst[i] = _pq_readAdd1(); - } - - PQ_BiquadF32(&pSrc[remainderBy8 - 1], &pDst[remainderBy8 - 1]); - } - - if (length) - { - PQ_StartVector(&pSrc[remainderBy8], &pDst[remainderBy8], length); - PQ_Vector8BiqaudDf2CascadeF32(); - PQ_EndVector(); - } -} - -void PQ_VectorBiqaudCascadeDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - - _pq_biquad1_fx(pSrc[0]); - pDst[0] = _pq_readAdd1_fx(); - - for (int i = 1; i < remainderBy8; i++) - { - _pq_biquad0_fx(pSrc[i - 1]); - _pq_biquad1_fx(pSrc[i]); - pDst[i - 1] = _pq_readAdd0_fx(); - pDst[i] = _pq_readAdd1_fx(); - } - - _pq_biquad0_fx(pSrc[remainderBy8 - 1]); - pDst[remainderBy8 - 1] = _pq_readAdd0_fx(); - } - - if (length) - { - PQ_StartVector(&pSrc[remainderBy8], &pDst[remainderBy8], length); - PQ_Vector8BiqaudDf2CascadeFixed32(); - PQ_EndVector(); - } -} - -void PQ_VectorBiqaudCascadeDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - - _pq_biquad1_fx(pSrc[0]); - pDst[0] = _pq_readAdd1_fx(); - - for (int i = 1; i < remainderBy8; i++) - { - _pq_biquad0_fx(pSrc[i - 1]); - _pq_biquad1_fx(pSrc[i]); - pDst[i - 1] = _pq_readAdd0_fx(); - pDst[i] = _pq_readAdd1_fx(); - } - - _pq_biquad0_fx(pSrc[remainderBy8 - 1]); - pDst[remainderBy8 - 1] = _pq_readAdd0_fx(); - } - - if (length) - { - PQ_StartVectorFixed16(&pSrc[remainderBy8], &pDst[remainderBy8], length); - PQ_Vector8BiqaudDf2CascadeFixed16(); - PQ_EndVector(); - } -} - -void PQ_BiquadBackUpInternalState(POWERQUAD_Type *base, int32_t biquad_num, pq_biquad_state_t *state) -{ -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-aliasing" -#endif - if (0 == biquad_num) - { - state->param = *(volatile pq_biquad_param_t *)&base->GPREG[0]; - state->compreg = base->COMPREG[1]; - } - else - { - state->param = *(volatile pq_biquad_param_t *)&base->GPREG[8]; - state->compreg = base->COMPREG[3]; - } -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif -} - -void PQ_BiquadRestoreInternalState(POWERQUAD_Type *base, int32_t biquad_num, pq_biquad_state_t *state) -{ -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-aliasing" -#endif - if (0 == biquad_num) - { - *(volatile pq_biquad_param_t *)&base->GPREG[0] = state->param; - base->COMPREG[1] = state->compreg; - } - else - { - *(volatile pq_biquad_param_t *)&base->GPREG[8] = state->param; - base->COMPREG[3] = state->compreg; - } -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif -} - -void PQ_FIR( - POWERQUAD_Type *base, void *pAData, int32_t ALength, void *pBData, int32_t BLength, void *pResult, uint32_t opType) -{ - assert(pAData); - assert(pBData); - assert(pResult); - - base->INABASE = (uint32_t)pAData; - base->INBBASE = (uint32_t)pBData; - base->LENGTH = ((uint32_t)BLength << 16U) + (uint32_t)ALength; - base->OUTBASE = (uint32_t)pResult; - base->CONTROL = (CP_FIR << 4U) | opType; -} - -void PQ_FIRIncrement(POWERQUAD_Type *base, int32_t ALength, int32_t BLength, int32_t xOffset) -{ - base->MISC = xOffset; - base->LENGTH = ((uint32_t)BLength << 16) + (uint32_t)ALength; - base->CONTROL = (CP_FIR << 4) | PQ_FIR_INCREMENTAL; -} - -void PQ_BiquadCascadeDf2Init(pq_biquad_cascade_df2_instance *S, uint8_t numStages, pq_biquad_state_t *pState) -{ - S->numStages = numStages; - S->pState = pState; -} - -void PQ_BiquadCascadeDf2F32(const pq_biquad_cascade_df2_instance *S, float *pSrc, float *pDst, uint32_t blockSize) -{ - uint32_t stage = S->numStages; - pq_biquad_state_t *states = S->pState; - - if (pDst != pSrc) - { - memcpy(pDst, pSrc, 4 * blockSize); - } - - if (stage % 2 != 0) - { - PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); - - PQ_VectorBiqaudDf2F32(pSrc, pDst, blockSize); - - PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); - - states++; - stage--; - } - - do - { - PQ_BiquadRestoreInternalState(POWERQUAD, 1, states); - states++; - PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); - - PQ_VectorBiqaudCascadeDf2F32(pDst, pDst, blockSize); - - states--; - PQ_BiquadBackUpInternalState(POWERQUAD, 1, states); - states++; - PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); - - states++; - stage -= 2U; - - } while (stage > 0U); -} - -void PQ_BiquadCascadeDf2Fixed32(const pq_biquad_cascade_df2_instance *S, - int32_t *pSrc, - int32_t *pDst, - uint32_t blockSize) -{ - uint32_t stage = S->numStages; - pq_biquad_state_t *states = S->pState; - - if (pDst != pSrc) - { - memcpy(pDst, pSrc, 4 * blockSize); - } - - if (stage % 2 != 0) - { - PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); - - PQ_VectorBiqaudDf2Fixed32(pSrc, pDst, blockSize); - - PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); - - states++; - stage--; - } - - do - { - PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); - states++; - PQ_BiquadRestoreInternalState(POWERQUAD, 1, states); - - PQ_VectorBiqaudCascadeDf2Fixed32(pDst, pDst, blockSize); - - states--; - PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); - states++; - PQ_BiquadBackUpInternalState(POWERQUAD, 1, states); - - states++; - stage -= 2U; - } while (stage > 0U); -} - -void PQ_BiquadCascadeDf2Fixed16(const pq_biquad_cascade_df2_instance *S, - int16_t *pSrc, - int16_t *pDst, - uint32_t blockSize) -{ - uint32_t stage = S->numStages; - pq_biquad_state_t *states = S->pState; - - if (pDst != pSrc) - { - memcpy(pDst, pSrc, 2 * blockSize); - } - - if (stage % 2 != 0) - { - PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); - - PQ_VectorBiqaudDf2Fixed16(pSrc, pDst, blockSize); - - PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); - - states++; - stage--; - } - - do - { - PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); - states++; - PQ_BiquadRestoreInternalState(POWERQUAD, 1, states); - - PQ_VectorBiqaudCascadeDf2Fixed16(pDst, pDst, blockSize); - - states--; - PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); - states++; - PQ_BiquadBackUpInternalState(POWERQUAD, 1, states); - - states++; - stage -= 2U; - } while (stage > 0U); -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_math.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_math.c deleted file mode 100644 index 6e6877fc03..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_math.c +++ /dev/null @@ -1,887 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_powerquad.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.powerquad_math" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -void PQ_VectorLnF32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_ln0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readAdd0(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8F32(PQ_LN, 1, PQ_TRANS); - PQ_EndVector(); - } -} - -void PQ_VectorInvF32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_inv0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readMult0(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8F32(PQ_INV, 0, PQ_TRANS); - PQ_EndVector(); - } -} - -void PQ_VectorSqrtF32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_sqrt0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readMult0(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8F32(PQ_SQRT, 0, PQ_TRANS); - PQ_EndVector(); - } -} - -void PQ_VectorInvSqrtF32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_invsqrt0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readMult0(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8F32(PQ_INVSQRT, 0, PQ_TRANS); - PQ_EndVector(); - } -} - -void PQ_VectorEtoxF32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_etox0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readMult0(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8F32(PQ_ETOX, 0, PQ_TRANS); - PQ_EndVector(); - } -} - -void PQ_VectorEtonxF32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_etonx0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readMult0(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8F32(PQ_ETONX, 0, PQ_TRANS); - PQ_EndVector(); - } -} - -void PQ_VectorSinF32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_sin0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readAdd0(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8F32(PQ_SIN, 1, PQ_TRIG); - PQ_EndVector(); - } -} - -void PQ_VectorCosF32(float *pSrc, float *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_cos0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readAdd0(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8F32(PQ_COS, 1, PQ_TRIG); - PQ_EndVector(); - } -} - -void PQ_VectorLnFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_ln_fx0(*pSrc++); - *pDst++ = _pq_readAdd0_fx(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8Fixed32(PQ_LN, 1, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorInvFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_inv_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8Fixed32(PQ_INV, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorSqrtFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_sqrt_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8Fixed32(PQ_SQRT, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorInvSqrtFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_invsqrt_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8Fixed32(PQ_INVSQRT, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorEtoxFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_etox_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8Fixed32(PQ_ETOX, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorEtonxFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_etonx_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8Fixed32(PQ_ETONX, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorSinQ31(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - uint32_t cppre; -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - const int32_t magic = 0x30c90fdb; - float valFloat; -#endif - - cppre = POWERQUAD->CPPRE; - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); - -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-aliasing" -#endif - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - } - } - - while (length > 0) - { - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - - length -= 8; - } -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif - -#else - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_sin_fx0(*pSrc++); - *pDst++ = _pq_readAdd0_fx(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8Fixed32(PQ_SIN, 1, PQ_TRIG_FIXED); - PQ_EndVector(); - } -#endif - - POWERQUAD->CPPRE = cppre; -} - -void PQ_VectorCosQ31(int32_t *pSrc, int32_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - uint32_t cppre; -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - const int32_t magic = 0x30c90fdb; - float valFloat; -#endif - - cppre = POWERQUAD->CPPRE; - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); - -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-aliasing" -#endif - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - } - } - - while (length > 0) - { - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - - valFloat = *(const float *)(&magic) * (float)(*pSrc++); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); - - length -= 8; - } - -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif - -#else - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_cos_fx0(*pSrc++); - *pDst++ = _pq_readAdd0_fx(); - } - } - - if (length) - { - PQ_StartVector(pSrc, pDst, length); - PQ_Vector8Fixed32(PQ_COS, 1, PQ_TRIG_FIXED); - PQ_EndVector(); - } -#endif - - POWERQUAD->CPPRE = cppre; -} - -void PQ_VectorLnFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_ln_fx0(*pSrc++); - *pDst++ = _pq_readAdd0_fx(); - } - } - - if (length) - { - PQ_StartVectorFixed16(pSrc, pDst, length); - PQ_Vector8Fixed16(PQ_LN, 1, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorInvFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_inv_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); - } - } - - if (length) - { - PQ_StartVectorFixed16(pSrc, pDst, length); - PQ_Vector8Fixed16(PQ_INV, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorSqrtFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_sqrt_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); - } - } - - if (length) - { - PQ_StartVectorFixed16(pSrc, pDst, length); - PQ_Vector8Fixed16(PQ_SQRT, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorInvSqrtFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_invsqrt_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); - } - } - - if (length) - { - PQ_StartVectorFixed16(pSrc, pDst, length); - PQ_Vector8Fixed16(PQ_INVSQRT, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorEtoxFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_etox_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); - } - } - - if (length) - { - PQ_StartVectorFixed16(pSrc, pDst, length); - PQ_Vector8Fixed16(PQ_ETOX, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorEtonxFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - int32_t remainderBy8 = length % 8; - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_etonx_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); - } - } - - if (length) - { - PQ_StartVectorFixed16(pSrc, pDst, length); - PQ_Vector8Fixed16(PQ_ETONX, 0, PQ_TRANS_FIXED); - PQ_EndVector(); - } -} - -void PQ_VectorSinQ15(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - uint32_t cppre; -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - const int32_t magic = 0x30c90fdb; - float valFloat; -#endif - - cppre = POWERQUAD->CPPRE; - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); - - int32_t remainderBy8 = length % 8; - -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-aliasing" -#endif - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - } - } - - while (length > 0) - { - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - - length -= 8; - } - -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif - -#else - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_sin_fx0((uint32_t)(*pSrc++) << 16); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - } - } - - if (length) - { - PQ_StartVectorQ15(pSrc, pDst, length); - PQ_Vector8Q15(PQ_SIN, 1, PQ_TRIG_FIXED); - PQ_EndVector(); - } -#endif - - POWERQUAD->CPPRE = cppre; -} - -void PQ_VectorCosQ15(int16_t *pSrc, int16_t *pDst, int32_t length) -{ - uint32_t cppre; -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - const int32_t magic = 0x30c90fdb; - float valFloat; -#endif - - cppre = POWERQUAD->CPPRE; - POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); - - int32_t remainderBy8 = length % 8; - -#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-aliasing" -#endif - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - } - } - - while (length > 0) - { - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - - valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16); - _pq_cos0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - - length -= 8; - } - -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif - -#else - - if (remainderBy8) - { - length -= remainderBy8; - while (remainderBy8--) - { - _pq_cos_fx0((uint32_t)(*pSrc++) << 16); - *pDst++ = (_pq_readAdd0_fx()) >> 16; - } - } - - if (length) - { - PQ_StartVectorQ15(pSrc, pDst, length); - PQ_Vector8Q15(PQ_COS, 1, PQ_TRIG_FIXED); - PQ_EndVector(); - } -#endif - - POWERQUAD->CPPRE = cppre; -} - -int32_t PQ_ArctanFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration) -{ - base->CORDIC_X = x; - base->CORDIC_Y = y; - base->CORDIC_Z = 0; - base->CONTROL = (CP_CORDIC << 4) | CORDIC_ARCTAN | CORDIC_ITER(iteration); - - PQ_WaitDone(base); - return base->CORDIC_Z; -} - -int32_t PQ_ArctanhFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration) -{ - base->CORDIC_X = x; - base->CORDIC_Y = y; - base->CORDIC_Z = 0; - base->CONTROL = (CP_CORDIC << 4) | CORDIC_ARCTANH | CORDIC_ITER(iteration); - - PQ_WaitDone(base); - return base->CORDIC_Z; -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_matrix.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_matrix.c deleted file mode 100644 index 7323b408d1..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_matrix.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_powerquad.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.powerquad_matrix" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -void PQ_MatrixAddition(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) -{ - assert(pAData); - assert(pBData); - assert(pResult); - - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pAData; - base->INBBASE = (int32_t)pBData; - base->LENGTH = length; - base->CONTROL = (CP_MTX << 4) | PQ_MTX_ADD; -} - -void PQ_MatrixSubtraction(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) -{ - assert(pAData); - assert(pBData); - assert(pResult); - - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pAData; - base->INBBASE = (int32_t)pBData; - base->LENGTH = length; - base->CONTROL = (CP_MTX << 4) | PQ_MTX_SUB; -} - -void PQ_MatrixMultiplication(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) -{ - assert(pAData); - assert(pBData); - assert(pResult); - - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pAData; - base->INBBASE = (int32_t)pBData; - base->LENGTH = length; - base->CONTROL = (CP_MTX << 4) | PQ_MTX_MULT; -} - -void PQ_MatrixProduct(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) -{ - assert(pAData); - assert(pBData); - assert(pResult); - - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pAData; - base->INBBASE = (int32_t)pBData; - base->LENGTH = length; - base->CONTROL = (CP_MTX << 4) | PQ_MTX_PROD; -} - -void PQ_VectorDotProduct(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) -{ - assert(pAData); - assert(pBData); - assert(pResult); - - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pAData; - base->INBBASE = (int32_t)pBData; - base->LENGTH = length; - base->CONTROL = (CP_MTX << 4) | PQ_VEC_DOTP; -} - -void PQ_MatrixInversion(POWERQUAD_Type *base, uint32_t length, void *pData, void *pTmpData, void *pResult) -{ - assert(pData); - assert(pTmpData); - assert(pResult); - - /* Workaround: - * - * Matrix inv depends on the coproc 1/x function, this puts coproc to right state. - */ - _pq_inv0(1.0); - - base->INABASE = (uint32_t)pData; - base->TMPBASE = (uint32_t)pTmpData; - base->OUTBASE = (uint32_t)pResult; - base->LENGTH = length; - base->CONTROL = (CP_MTX << 4) | PQ_MTX_INV; -} - -void PQ_MatrixTranspose(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) -{ - assert(pData); - assert(pResult); - - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pData; - base->LENGTH = length; - base->CONTROL = (CP_MTX << 4) | PQ_MTX_TRAN; -} - -void PQ_MatrixScale(POWERQUAD_Type *base, uint32_t length, float misc, void *pData, void *pResult) -{ - assert(pData); - assert(pResult); - - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pData; - base->LENGTH = length; -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-aliasing" -#endif - base->MISC = *(uint32_t *)&misc; -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif - base->CONTROL = (CP_MTX << 4) | PQ_MTX_SCALE; -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_transform.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_transform.c deleted file mode 100644 index 6f1c387f14..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_powerquad_transform.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_powerquad.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.powerquad_transform" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -void PQ_TransformCFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) -{ - assert(pData); - assert(pResult); - - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pData; - base->LENGTH = length; - base->CONTROL = (CP_FFT << 4) | PQ_TRANS_CFFT; -} - -void PQ_TransformRFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) -{ - assert(pData); - assert(pResult); - - /* Set 0's for imaginary inputs as not be reading them in by the machine */ - base->GPREG[1] = 0; - base->GPREG[3] = 0; - base->GPREG[5] = 0; - base->GPREG[7] = 0; - base->GPREG[9] = 0; - base->GPREG[11] = 0; - base->GPREG[13] = 0; - base->GPREG[15] = 0; - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pData; - base->LENGTH = length; - base->CONTROL = (CP_FFT << 4) | PQ_TRANS_RFFT; -} - -void PQ_TransformIFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) -{ - assert(pData); - assert(pResult); - - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pData; - base->LENGTH = length; - base->CONTROL = (CP_FFT << 4) | PQ_TRANS_IFFT; -} - -void PQ_TransformCDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) -{ - assert(pData); - assert(pResult); - - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pData; - base->LENGTH = length; - base->CONTROL = (CP_FFT << 4) | PQ_TRANS_CDCT; -} - -void PQ_TransformRDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) -{ - assert(pData); - assert(pResult); - - base->GPREG[1] = 0; - base->GPREG[3] = 0; - base->GPREG[5] = 0; - base->GPREG[7] = 0; - base->GPREG[9] = 0; - base->GPREG[11] = 0; - base->GPREG[13] = 0; - base->GPREG[15] = 0; - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pData; - base->LENGTH = length; - base->CONTROL = (CP_FFT << 4) | PQ_TRANS_RDCT; -} - -void PQ_TransformIDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) -{ - assert(pData); - assert(pResult); - - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pData; - base->LENGTH = length; - base->CONTROL = (CP_FFT << 4) | PQ_TRANS_IDCT; -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_prince.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_prince.c deleted file mode 100644 index e312282352..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_prince.c +++ /dev/null @@ -1,454 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_prince.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ - -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.prince" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * brief Generate new IV code. - * - * This function generates new IV code and stores it into the persistent memory. - * Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true! - * - * param region PRINCE region index. - * param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code. - * param store flag to allow storing the newly generated IV code into the persistent memory (FFR). - * param flash_context pointer to the flash driver context structure. - * - * return kStatus_Success upon success - * return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular - * PRINCE region is not present in the keystore (though new IV code has been provided) - */ -status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context) -{ - status_t retVal = kStatus_Fail; - uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; - uint8_t tempBuffer[FLASH_FFR_MAX_PAGE_SIZE] = {0}; - - if (((SYSCON->PERIPHENCFG & SYSCON_PERIPHENCFG_PRINCEEN_MASK) ? true : false) == false) - { - return retVal; /* PRINCE peripheral not enabled, return kStatus_Fail. */ - } - - /* Make sure PUF is started to allow key and IV code decryption and generation */ - if (true != PUF_IsGetKeyAllowed(PUF)) - { - return retVal; - } - - /* Generate new IV code for the PRINCE region */ - retVal = PUF_SetIntrinsicKey(PUF, (puf_key_index_register_t)(kPUF_KeyIndex_02 + (puf_key_index_register_t)region), - 8, &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); - if ((kStatus_Success == retVal) && (true == store)) - { - /* Store the new IV code for the PRINCE region into the respective FFRs. */ - /* Create a new version of "Customer Field Programmable" (CFP) page. */ - if (kStatus_FLASH_Success == - FFR_GetCustomerInfieldData(flash_context, (uint8_t *)tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE)) - { - /* Set the IV code in the page */ - memcpy(&tempBuffer[offsetof(cfpa_cfg_info_t, ivCodePrinceRegion) + ((region * sizeof(cfpa_cfg_iv_code_t))) + - 4], - &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); - - uint32_t *p32 = (uint32_t *)tempBuffer; - uint32_t version = p32[1]; - if (version == 0xFFFFFFFFu) - { - return kStatus_Fail; - } - version++; - p32[1] = version; - - /* Program the page and enable firewall for "Customer field area" */ - if (kStatus_FLASH_Success == - FFR_InfieldPageWrite(flash_context, (uint8_t *)tempBuffer, FLASH_FFR_MAX_PAGE_SIZE)) - { - retVal = kStatus_Success; - } - else - { - retVal = kStatus_Fail; - } - } - } - if (retVal == kStatus_Success) - { - /* Pass the new IV code */ - memcpy(iv_code, &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); - } - return retVal; -} - -/*! - * brief Load IV code. - * - * This function enables IV code loading into the PRINCE bus encryption engine. - * - * param region PRINCE region index. - * param iv_code IV code pointer used for passing the IV code. - * - * return kStatus_Success upon success - * return kStatus_Fail otherwise - */ -status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code) -{ - status_t retVal = kStatus_Fail; - uint32_t keyIndex = 0x0Fu & iv_code[1]; - uint8_t prince_iv[8] = {0}; - - if (((SYSCON->PERIPHENCFG & SYSCON_PERIPHENCFG_PRINCEEN_MASK) ? true : false) == false) - { - return retVal; /* PRINCE peripheral not enabled, return kStatus_Fail. */ - } - - /* Make sure PUF is started to allow key and IV code decryption and generation */ - if (true != PUF_IsGetKeyAllowed(PUF)) - { - return retVal; - } - - /* Check if region number matches the PUF index value */ - if ((kPUF_KeyIndex_02 + (puf_key_index_register_t)region) == (puf_key_index_register_t)keyIndex) - { - /* Decrypt the IV */ - if (kStatus_Success == PUF_GetKey(PUF, iv_code, FLASH_FFR_IV_CODE_SIZE, &prince_iv[0], 8)) - { - /* Store the new IV for the PRINCE region into PRINCE registers. */ - PRINCE_SetRegionIV(PRINCE, (prince_region_t)region, prince_iv); - retVal = kStatus_Success; - } - } - return retVal; -} - -/*! - * brief Allow encryption/decryption for specified address range. - * - * This function sets the encryption/decryption for specified address range. - * Ensure about 800 bytes free space on the stack when calling this routine! - * - * param region PRINCE region index. - * param start_address start address of the area to be encrypted/decrypted. - * param length length of the area to be encrypted/decrypted. - * param flash_context pointer to the flash driver context structure. - * - * return kStatus_Success upon success - * return kStatus_Fail otherwise - */ -status_t PRINCE_SetEncryptForAddressRange(prince_region_t region, - uint32_t start_address, - uint32_t length, - flash_config_t *flash_context) -{ - status_t retVal = kStatus_Fail; - uint32_t srEnableRegister = 0; - uint32_t alignedStartAddress; - uint32_t end_address = start_address + length; - uint32_t prince_region_base_address = 0; - uint8_t my_prince_iv_code[52] = {0}; - uint8_t tempBuffer[512] = {0}; - uint32_t prince_base_addr_ffr_word = 0; - - /* Check the address range, regions overlaping. */ - if ((start_address > 0xA0000) || ((start_address < 0x40000) && (end_address > 0x40000)) || - ((start_address < 0x80000) && (end_address > 0x80000)) || - ((start_address < 0xA0000) && (end_address > 0xA0000))) - { - return kStatus_Fail; - } - - /* Generate new IV code for the PRINCE region and store the new IV into the respective FFRs */ - retVal = PRINCE_GenNewIV((prince_region_t)region, &my_prince_iv_code[0], true, flash_context); - if (kStatus_Success != retVal) - { - return kStatus_Fail; - } - - /* Store the new IV for the PRINCE region into PRINCE registers. */ - retVal = PRINCE_LoadIV((prince_region_t)region, &my_prince_iv_code[0]); - if (kStatus_Success != retVal) - { - return kStatus_Fail; - } - - alignedStartAddress = ALIGN_DOWN(start_address, FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); - - uint32_t subregion = alignedStartAddress / (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); - if (subregion < (32)) - { - /* PRINCE_Region0 */ - prince_region_base_address = 0; - } - else if (subregion < (64)) - { - /* PRINCE_Region1 */ - subregion = subregion - 32; - prince_region_base_address = 0x40000; - } - else - { - /* PRINCE_Region2 */ - subregion = subregion - 64; - prince_region_base_address = 0x80000; - } - - srEnableRegister = (1 << subregion); - alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); - - while (alignedStartAddress < (start_address + length)) - { - subregion++; - srEnableRegister |= (1 << subregion); - alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); - } - - /* Store BASE_ADDR into PRINCE register before storing the SR to avoid en/decryption triggering - from addresses being defined by current BASE_ADDR register content (could be 0 and the decryption - of actually executed code can be started causing the hardfault then). */ - retVal = PRINCE_SetRegionBaseAddress(PRINCE, (prince_region_t)region, prince_region_base_address); - if (kStatus_Success != retVal) - { - return retVal; - } - - /* Store SR into PRINCE register */ - retVal = PRINCE_SetRegionSREnable(PRINCE, (prince_region_t)region, srEnableRegister); - if (kStatus_Success != retVal) - { - return retVal; - } - - /* Store SR and BASE_ADDR into CMPA FFR */ - if (kStatus_Success == FFR_GetCustomerData(flash_context, (uint8_t *)&tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE)) - { - /* Set the PRINCE_SR_X in the page */ - memcpy(&tempBuffer[offsetof(cmpa_cfg_info_t, princeSr) + (region * sizeof(uint32_t))], &srEnableRegister, - sizeof(uint32_t)); - - /* Set the ADDRX_PRG in the page */ - memcpy(&prince_base_addr_ffr_word, &tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], sizeof(uint32_t)); - prince_base_addr_ffr_word &= ~((FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) << (region * 4)); - prince_base_addr_ffr_word |= - (((prince_region_base_address >> 18) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) << (region * 4)); - memcpy(&tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], &prince_base_addr_ffr_word, sizeof(uint32_t)); - - /* Program the CMPA page, set seal_part parameter to false (used during development to avoid sealing the part) - */ - retVal = FFR_CustFactoryPageWrite(flash_context, (uint8_t *)tempBuffer, false); - } - - return retVal; -} - -/*! - * brief Gets the PRINCE Sub-Region Enable register. - * - * This function gets PRINCE SR_ENABLE register. - * - * param base PRINCE peripheral address. - * param region PRINCE region index. - * param sr_enable Sub-Region Enable register pointer. - * - * return kStatus_Success upon success - * return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t *sr_enable) -{ - status_t status = kStatus_Success; - - switch (region) - { - case kPRINCE_Region0: - *sr_enable = base->SR_ENABLE0; - break; - - case kPRINCE_Region1: - *sr_enable = base->SR_ENABLE1; - break; - - case kPRINCE_Region2: - *sr_enable = base->SR_ENABLE2; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -/*! - * brief Gets the PRINCE region base address register. - * - * This function gets PRINCE BASE_ADDR register. - * - * param base PRINCE peripheral address. - * param region PRINCE region index. - * param region_base_addr Region base address pointer. - * - * return kStatus_Success upon success - * return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t *region_base_addr) -{ - status_t status = kStatus_Success; - - switch (region) - { - case kPRINCE_Region0: - *region_base_addr = base->BASE_ADDR0; - break; - - case kPRINCE_Region1: - *region_base_addr = base->BASE_ADDR1; - break; - - case kPRINCE_Region2: - *region_base_addr = base->BASE_ADDR2; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -/*! - * @brief Sets the PRINCE region IV. - * - * This function sets specified AES IV for the given region. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param iv 64-bit AES IV in little-endian byte order. - */ -status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uint8_t iv[8]) -{ - status_t status = kStatus_Fail; - volatile uint32_t *IVMsb_reg = NULL; - volatile uint32_t *IVLsb_reg = NULL; - - switch (region) - { - case kPRINCE_Region0: - IVLsb_reg = &base->IV_LSB0; - IVMsb_reg = &base->IV_MSB0; - break; - - case kPRINCE_Region1: - IVLsb_reg = &base->IV_LSB1; - IVMsb_reg = &base->IV_MSB1; - break; - - case kPRINCE_Region2: - IVLsb_reg = &base->IV_LSB2; - IVMsb_reg = &base->IV_MSB2; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - if (status != kStatus_InvalidArgument) - { - *IVLsb_reg = ((uint32_t *)(uintptr_t)iv)[0]; - *IVMsb_reg = ((uint32_t *)(uintptr_t)iv)[1]; - status = kStatus_Success; - } - - return status; -} - -/*! - * @brief Sets the PRINCE region base address. - * - * This function configures PRINCE region base address. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param region_base_addr Base Address for region. - */ -status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t region_base_addr) -{ - status_t status = kStatus_Success; - - switch (region) - { - case kPRINCE_Region0: - base->BASE_ADDR0 = region_base_addr; - break; - - case kPRINCE_Region1: - base->BASE_ADDR1 = region_base_addr; - break; - - case kPRINCE_Region2: - base->BASE_ADDR2 = region_base_addr; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} - -/*! - * @brief Sets the PRINCE Sub-Region Enable register. - * - * This function configures PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param sr_enable Sub-Region Enable register value. - */ -status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable) -{ - status_t status = kStatus_Success; - - switch (region) - { - case kPRINCE_Region0: - base->SR_ENABLE0 = sr_enable; - break; - - case kPRINCE_Region1: - base->SR_ENABLE1 = sr_enable; - break; - - case kPRINCE_Region2: - base->SR_ENABLE2 = sr_enable; - break; - - default: - status = kStatus_InvalidArgument; - break; - } - - return status; -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_prince.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_prince.h deleted file mode 100644 index 04e37a48ac..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_prince.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_PRINCE_H_ -#define _FSL_PRINCE_H_ - -#include "fsl_common.h" -#include "fsl_iap_ffr.h" -#include "fsl_puf.h" - -/*! - * @addtogroup prince - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief PRINCE driver version 2.0.0. - * - * Current version: 2.0.0 - * - * Change log: - * - Version 2.0.0 - * - Initial version. - */ -#define FSL_PRINCE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -#define FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB (8) - -#if !defined(ALIGN_DOWN) -#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) -#endif - -typedef enum _prince_region -{ - kPRINCE_Region0 = 0U, /*!< PRINCE region 0 */ - kPRINCE_Region1 = 1U, /*!< PRINCE region 1 */ - kPRINCE_Region2 = 2U, /*!< PRINCE region 2 */ -} prince_region_t; - -typedef enum _prince_lock -{ - kPRINCE_Region0Lock = 1U, /*!< PRINCE region 0 lock */ - kPRINCE_Region1Lock = 2U, /*!< PRINCE region 1 lock */ - kPRINCE_Region2Lock = 4U, /*!< PRINCE region 2 lock */ - kPRINCE_MaskLock = 256U, /*!< PRINCE mask register lock */ -} prince_lock_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enable data encryption. - * - * This function enables PRINCE on-the-fly data encryption. - * - * @param base PRINCE peripheral address. - */ -static inline void PRINCE_EncryptEnable(PRINCE_Type *base) -{ - base->ENC_ENABLE = 1; -} - -/*! - * @brief Disable data encryption. - * - * This function disables PRINCE on-the-fly data encryption. - * - * @param base PRINCE peripheral address. - */ -static inline void PRINCE_EncryptDisable(PRINCE_Type *base) -{ - base->ENC_ENABLE = 0; -} - -/*! - * @brief Sets PRINCE data mask. - * - * This function sets the PRINCE mask that is used to mask decrypted data. - * - * @param base PRINCE peripheral address. - * @param mask 64-bit data mask value. - */ -static inline void PRINCE_SetMask(PRINCE_Type *base, uint64_t mask) -{ - base->MASK_LSB = mask & 0xffffffffu; - base->MASK_MSB = mask >> 32u; -} - -/*! - * @brief Locks access for specified region registers or data mask register. - * - * This function sets lock on specified region registers or mask register. - * - * @param base PRINCE peripheral address. - * @param lock registers to lock. This is a logical OR of members of the - * enumeration ::prince_lock_t - */ -static inline void PRINCE_SetLock(PRINCE_Type *base, uint32_t lock) -{ - base->LOCK = lock & 0x1ffu; -} - -/*! - * @brief Generate new IV code. - * - * This function generates new IV code and stores it into the persistent memory. - * This function is implemented as a wrapper of the exported ROM bootloader API. - * Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true! - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code. - * @param store flag to allow storing the newly generated IV code into the persistent memory (FFR). - * param flash_context pointer to the flash driver context structure. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular - * PRINCE region is not present in the keystore (though new IV code has been provided) - */ -status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context); - -/*! - * @brief Load IV code. - * - * This function enables IV code loading into the PRINCE bus encryption engine. - * This function is implemented as a wrapper of the exported ROM bootloader API. - * - * @param region PRINCE region index. - * @param iv_code IV code pointer used for passing the IV code. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code); - -/*! - * @brief Allow encryption/decryption for specified address range. - * - * This function sets the encryption/decryption for specified address range. - * This function is implemented as a wrapper of the exported ROM bootloader API. - * Ensure about 800 bytes free space on the stack when calling this routine! - * - * @param region PRINCE region index. - * @param start_address start address of the area to be encrypted/decrypted. - * @param length length of the area to be encrypted/decrypted. - * param flash_context pointer to the flash driver context structure. - * - * @return kStatus_Success upon success - * @return kStatus_Fail otherwise - */ -status_t PRINCE_SetEncryptForAddressRange(prince_region_t region, - uint32_t start_address, - uint32_t length, - flash_config_t *flash_context); - -/*! - * @brief Gets the PRINCE Sub-Region Enable register. - * - * This function gets PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param sr_enable Sub-Region Enable register pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t *sr_enable); - -/*! - * @brief Gets the PRINCE region base address register. - * - * This function gets PRINCE BASE_ADDR register. - * - * @param base PRINCE peripheral address. - * @param region PRINCE region index. - * @param region_base_addr Region base address pointer. - * - * @return kStatus_Success upon success - * @return kStatus_InvalidArgument - */ -status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t *region_base_addr); - -/*! - * @brief Sets the PRINCE region IV. - * - * This function sets specified AES IV for the given region. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param iv 64-bit AES IV in little-endian byte order. - */ -status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uint8_t iv[8]); - -/*! - * @brief Sets the PRINCE region base address. - * - * This function configures PRINCE region base address. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param region_base_addr Base Address for region. - */ -status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t region_base_addr); - -/*! - * @brief Sets the PRINCE Sub-Region Enable register. - * - * This function configures PRINCE SR_ENABLE register. - * - * @param base PRINCE peripheral address. - * @param region Selection of the PRINCE region to be configured. - * @param sr_enable Sub-Region Enable register value. - */ -status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable); - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_PRINCE_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_puf.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_puf.c deleted file mode 100644 index 35da58e7b1..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_puf.c +++ /dev/null @@ -1,815 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_puf.h" -#include "fsl_clock.h" -#include "fsl_reset.h" -#include "fsl_common.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.puf" -#endif - -static void puf_wait_usec(volatile uint32_t usec, uint32_t coreClockFrequencyMHz) -{ - while (usec > 0) - { - usec--; - - /* number of MHz is directly number of core clocks to wait 1 usec. */ - /* the while loop below is actually 4 clocks so divide by 4 for ~1 usec */ - register uint32_t ticksCount = coreClockFrequencyMHz / 4u + 1u; - while (ticksCount--) - { - } - } -} - -static status_t puf_waitForInit(PUF_Type *base) -{ - status_t status = kStatus_Fail; - - /* wait until status register reads non-zero. All zero is not valid. It should be BUSY or OK or ERROR */ - while (0 == base->STAT) - { - } - - /* wait if busy */ - while ((base->STAT & PUF_STAT_BUSY_MASK) != 0) - { - } - - /* return status */ - if (PUF_STAT_SUCCESS_MASK == (base->STAT & (PUF_STAT_SUCCESS_MASK | PUF_STAT_ERROR_MASK))) - { - status = kStatus_Success; - } - - return status; -} - -static void puf_powerOn(PUF_Type *base) -{ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) - /* RT6xxs */ - base->PWRCTRL = 0x5u; - base->PWRCTRL = 0xDu; - base->PWRCTRL = 0x9u; -#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ - /* Niobe4 & Aruba FL */ - base->PWRCTRL = PUF_PWRCTRL_RAMON_MASK; - while (0 == (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)) - { - } -#endif /* FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ -} - -static status_t puf_powerCycle(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz) -{ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) - /* RT6xxs */ - uint32_t coreClockFrequencyMHz = coreClockFrequencyHz / 1000000u; - - /* exit ASPS mode */ - - /* write PWRCTRL=0x38. wait time > 1 us */ - base->PWRCTRL = 0x38u; /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=1. */ - puf_wait_usec(1, coreClockFrequencyMHz); - - /* write PWRCTRL=0x8. wait time > 1 us */ - base->PWRCTRL = 0x08u; /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=0 */ - puf_wait_usec(1, coreClockFrequencyMHz); - - base->PWRCTRL = 0xCu; - base->PWRCTRL = 0xDu; - base->PWRCTRL = 0x9u; - - /* Generate INITN low pulse */ - base->PWRCTRL = 0xDu; - base->PWRCTRL = 0x5u; - base->PWRCTRL = 0x1u; -#else - /* Niobe4 & Aruba FL */ - base->PWRCTRL = 0x0u; - while (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL) - { - } -#endif - - /* Wait enough time to discharge fully */ - puf_wait_usec(dischargeTimeMsec * 1000u, coreClockFrequencyHz / 1000000u); - - /* Reset PUF and reenable power to PUF SRAM */ - RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); - puf_powerOn(base); - - return kStatus_Success; -} - -/*! - * brief Initialize PUF - * - * This function enables power to PUF block and waits until the block initializes. - * - * param base PUF peripheral base address - * param dischargeTimeMsec time in ms to wait for PUF SRAM to fully discharge - * param coreClockFrequencyHz core clock frequency in Hz - * return Status of the init operation - */ -status_t PUF_Init(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz) -{ - status_t status = kStatus_Fail; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Puf); -#endif - /* Reset PUF */ - RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); - - /* Enable power to PUF SRAM */ - puf_powerOn(base); - - /* Wait for peripheral to become ready */ - status = puf_waitForInit(base); - - /* In case of error or enroll & start not allowed, do power-cycle */ - if ((status != kStatus_Success) || ((PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK) != - (base->ALLOW & (PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK)))) - { - puf_powerCycle(base, dischargeTimeMsec, coreClockFrequencyHz); - status = puf_waitForInit(base); - } - - return status; -} - -/*! - * brief Denitialize PUF - * - * This function disables power to PUF SRAM and peripheral clock. - * - * param base PUF peripheral base address - */ -void PUF_Deinit(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz) -{ -#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) - /* RT6xxs */ - base->PWRCTRL = 0xDu; /* disable RAM CK */ - - /* enter ASPS mode */ - base->PWRCTRL = 0xCu; /* SLEEP = 1 */ - base->PWRCTRL = 0x8u; /* enable RAM CK */ - base->PWRCTRL = 0xF8u; /* SLEEP=1, PSW*=1 */ -#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ - /* Niobe4 & Aruba FL */ - base->PWRCTRL = 0x00u; -#endif - - /* Wait enough time to discharge fully */ - puf_wait_usec(dischargeTimeMsec * 1000u, coreClockFrequencyHz / 1000000u); - - RESET_SetPeripheralReset(kPUF_RST_SHIFT_RSTn); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Puf); -#endif -} - -/*! - * brief Enroll PUF - * - * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) - * and returns it to be stored in an NVM or a file. This step needs to be - * performed only once for each device. This function may be permanently disallowed by a fuse. - * - * param base PUF peripheral base address - * param[out] activationCode Word aligned address of the resulting activation code. - * param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * return Status of enroll operation. - */ -status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *activationCodeAligned = NULL; - register uint32_t temp32 = 0; - - /* check that activation code buffer size is at least 1192 bytes */ - if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE) - { - return kStatus_InvalidArgument; - } - - /* only work with aligned activationCode */ - if (0x3u & (uintptr_t)activationCode) - { - return kStatus_InvalidArgument; - } - - activationCodeAligned = (uint32_t *)(uintptr_t)activationCode; - - /* check if ENROLL is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWENROLL_MASK)) - { - return kStatus_Fail; - } - - /* begin */ - base->CTRL = PUF_CTRL_ENROLL_MASK; - - /* check status */ - while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* read out AC */ - while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0 != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) - { - temp32 = base->CODEOUTPUT; - if (activationCodeSize >= sizeof(uint32_t)) - { - *activationCodeAligned = temp32; - activationCodeAligned++; - activationCodeSize -= sizeof(uint32_t); - } - } - } - - if ((base->STAT & PUF_STAT_SUCCESS_MASK) && (activationCodeSize == 0)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Start PUF - * - * The Activation Code generated during the Enroll operation is used to - * reconstruct the digital fingerprint. This needs to be done after every power-up - * and reset. - * - * param base PUF peripheral base address - * param activationCode Word aligned address of the input activation code. - * param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * return Status of start operation. - */ -status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize) -{ - status_t status = kStatus_Fail; - const uint32_t *activationCodeAligned = NULL; - register uint32_t temp32 = 0; - - /* check that activation code size is at least 1192 bytes */ - if (activationCodeSize < 1192) - { - return kStatus_InvalidArgument; - } - - /* only work with aligned activationCode */ - if (0x3u & (uintptr_t)activationCode) - { - return kStatus_InvalidArgument; - } - - activationCodeAligned = (const uint32_t *)(uintptr_t)activationCode; - - /* check if START is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSTART_MASK)) - { - return kStatus_Fail; - } - - /* begin */ - base->CTRL = PUF_CTRL_START_MASK; - - /* check status */ - while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy send AC */ - while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0 != (PUF_STAT_CODEINREQ_MASK & base->STAT)) - { - if (activationCodeSize >= sizeof(uint32_t)) - { - temp32 = *activationCodeAligned; - activationCodeAligned++; - activationCodeSize -= sizeof(uint32_t); - } - base->CODEINPUT = temp32; - } - } - - /* get status */ - if (0 != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Set intrinsic key - * - * The digital fingerprint generated during the Enroll/Start - * operations is used to generate a Key Code (KC) that defines a unique intrinsic - * key. This KC is returned to be stored in an NVM or a file. This operation - * needs to be done only once for each intrinsic key. - * Each time a Set Intrinsic Key operation is executed a new unique key is - * generated. - * - * param base PUF peripheral base address - * param keyIndex PUF key index register - * param keySize Size of the intrinsic key to generate in bytes. - * param[out] keyCode Word aligned address of the resulting key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * return Status of set intrinsic key operation. - */ -status_t PUF_SetIntrinsicKey( - PUF_Type *base, puf_key_index_register_t keyIndex, size_t keySize, uint8_t *keyCode, size_t keyCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - register uint32_t temp32 = 0; - - /* check if SET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0x3u & (uintptr_t)keyCode) - { - return kStatus_InvalidArgument; - } - - /* Check that keySize is in the correct range and that it is multiple of 8 */ - if ((keySize < kPUF_KeySizeMin) || (keySize > kPUF_KeySizeMax) || (keySize & 0x7)) - { - return kStatus_InvalidArgument; - } - - /* check that keyCodeSize is correct for given keySize */ - if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize)) - { - return kStatus_InvalidArgument; - } - - if ((uint32_t)keyIndex > kPUF_KeyIndexMax) - { - return kStatus_InvalidArgument; - } - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - - /* program the key size and index */ - base->KEYSIZE = keySize >> 3; - base->KEYINDEX = (uint32_t)keyIndex; - - /* begin */ - base->CTRL = PUF_CTRL_GENERATEKEY_MASK; - - /* wait till command is accepted */ - while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy read KC */ - while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0 != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) - { - temp32 = base->CODEOUTPUT; - if (keyCodeSize >= sizeof(uint32_t)) - { - *keyCodeAligned = temp32; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - } - } - - /* get status */ - if (0 != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Set user key - * - * The digital fingerprint generated during the Enroll/Start - * operations and a user key (UK) provided as input are used to - * generate a Key Code (KC). This KC is sent returned to be stored - * in an NVM or a file. This operation needs to be done only once for each user key. - * - * param base PUF peripheral base address - * param keyIndex PUF key index register - * param userKey Word aligned address of input user key. - * param userKeySize Size of the input user key in bytes. - * param[out] keyCode Word aligned address of the resulting key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize). - * return Status of set user key operation. - */ -status_t PUF_SetUserKey(PUF_Type *base, - puf_key_index_register_t keyIndex, - const uint8_t *userKey, - size_t userKeySize, - uint8_t *keyCode, - size_t keyCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - const uint32_t *userKeyAligned = NULL; - register uint32_t temp32 = 0; - - /* check if SET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0x3u & (uintptr_t)keyCode) - { - return kStatus_InvalidArgument; - } - - /* Check that userKeySize is in the correct range and that it is multiple of 8 */ - if ((userKeySize < kPUF_KeySizeMin) || (userKeySize > kPUF_KeySizeMax) || (userKeySize & 0x7)) - { - return kStatus_InvalidArgument; - } - - /* check that keyCodeSize is correct for given userKeySize */ - if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize)) - { - return kStatus_InvalidArgument; - } - - if ((uint32_t)keyIndex > kPUF_KeyIndexMax) - { - return kStatus_InvalidArgument; - } - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - userKeyAligned = (const uint32_t *)(uintptr_t)userKey; - - /* program the key size and index */ - base->KEYSIZE = userKeySize >> 3; /* convert to 64-bit blocks */ - base->KEYINDEX = (uint32_t)keyIndex; - - /* begin */ - base->CTRL = PUF_CTRL_SETKEY_MASK; - - /* wait till command is accepted */ - while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy write UK and read KC */ - while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0 != (PUF_STAT_KEYINREQ_MASK & base->STAT)) - { - if (userKeySize >= sizeof(uint32_t)) - { - temp32 = *userKeyAligned; - userKeyAligned++; - userKeySize -= sizeof(uint32_t); - } - base->KEYINPUT = temp32; - } - - if (0 != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) - { - temp32 = base->CODEOUTPUT; - if (keyCodeSize >= sizeof(uint32_t)) - { - *keyCodeAligned = temp32; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - } - } - - /* get status */ - if (0 != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -static status_t puf_getHwKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - register uint32_t temp32 = 0; - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - - /* begin */ - base->CTRL = PUF_CTRL_GETKEY_MASK; - - /* wait till command is accepted */ - while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy send KC, key is reconstructed to HW bus */ - while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0 != (PUF_STAT_CODEINREQ_MASK & base->STAT)) - { - if (keyCodeSize >= sizeof(uint32_t)) - { - temp32 = *keyCodeAligned; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - base->CODEINPUT = temp32; - } - } - - /* get status */ - if (0 != (base->STAT & PUF_STAT_SUCCESS_MASK)) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Reconstruct hw bus key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index register kPUF_KeyIndex_00. - * Such a key is output directly to a dedicated hardware bus. The reconstructed key is not exposed to system memory. - * - * param base PUF peripheral base address - * param keyCode Word aligned address of the input key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * param keySlot key slot to output on hw bus. Parameter is ignored on devices with less than two key slots. - * param keyMask key masking value. Shall be random for each POR/reset. Value does not have to be cryptographicaly - * secure. - * return Status of get key operation. - */ -status_t PUF_GetHwKey( - PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, puf_key_slot_t keySlot, uint32_t keyMask) -{ - status_t status = kStatus_Fail; - uint32_t keyIndex; - - /* check if GET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0x3u & (uintptr_t)keyCode) - { - return kStatus_Fail; - } - - /* check that keyCodeSize is at least PUF_MIN_KEY_CODE_SIZE */ - if (keyCodeSize < PUF_MIN_KEY_CODE_SIZE) - { - return kStatus_InvalidArgument; - } - - keyIndex = 0x0Fu & keyCode[1]; - - /* check the Key Code header byte 1. index must be zero for the hw key. */ - if (kPUF_KeyIndex_00 != (puf_key_index_register_t)keyIndex) - { - return kStatus_Fail; - } - -#if defined(FSL_FEATURE_PUF_HAS_KEYSLOTS) && (FSL_FEATURE_PUF_HAS_KEYSLOTS > 0) - volatile uint32_t *keyMask_reg = NULL; - uint32_t regVal = (2 << (2 * keySlot)); - - switch (keySlot) - { - case kPUF_KeySlot0: - keyMask_reg = &base->KEYMASK[0]; - break; - - case kPUF_KeySlot1: - keyMask_reg = &base->KEYMASK[1]; - break; -#if (FSL_FEATURE_PUF_HAS_KEYSLOTS > 2) - case kPUF_KeySlot2: - keyMask_reg = &base->KEYMASK[2]; - break; - - case kPUF_KeySlot3: - keyMask_reg = &base->KEYMASK[3]; - break; -#endif /* FSL_FEATURE_PUF_HAS_KEYSLOTS > 2 */ - default: - status = kStatus_InvalidArgument; - break; - } -#endif /* FSL_FEATURE_PUF_HAS_KEYSLOTS */ - - if (status != kStatus_InvalidArgument) - { -#if defined(FSL_FEATURE_PUF_HAS_KEYSLOTS) && (FSL_FEATURE_PUF_HAS_KEYSLOTS > 0) - base->KEYRESET = regVal; - base->KEYENABLE = regVal; - *keyMask_reg = keyMask; -#endif /* FSL_FEATURE_PUF_HAS_KEYSLOTS */ - - status = puf_getHwKey(base, keyCode, keyCodeSize); - -#if defined(FSL_FEATURE_PUF_HAS_SHIFT_STATUS) && (FSL_FEATURE_PUF_HAS_SHIFT_STATUS > 0) - size_t keyWords = 0; - - if (status == kStatus_Success) - { - /* if the corresponding shift count does not match, return fail anyway */ - keyWords = ((((size_t)keyCode[3]) * 2) - 1u) << (keySlot << 2); - if (keyWords != ((0x0Fu << (keySlot << 2)) & base->SHIFT_STATUS)) - { - status = kStatus_Fail; - } - } -#endif /* FSL_FEATURE_PUF_HAS_SHIFT_STATUS */ - } - - return status; -} - -/*! - * brief Checks if Get Key operation is allowed. - * - * This function returns true if get key operation is allowed. - * - * param base PUF peripheral base address - * return true if get key operation is allowed - */ -bool PUF_IsGetKeyAllowed(PUF_Type *base) -{ - if (0 == (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)) - { - return false; - } - - /* check if GET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) - { - return false; - } - - return true; -} - -/*! - * brief Reconstruct key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index registers kPUF_KeyIndex_01 to kPUF_KeyIndex_15. - * - * param base PUF peripheral base address - * param keyCode Word aligned address of the input key code. - * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * param[out] key Word aligned address of output key. - * param keySize Size of the output key in bytes. - * return Status of get key operation. - */ -status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize) -{ - status_t status = kStatus_Fail; - uint32_t *keyCodeAligned = NULL; - uint32_t *keyAligned = NULL; - uint32_t keyIndex; - register uint32_t temp32 = 0; - - /* check if GET KEY is allowed */ - if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) - { - return kStatus_Fail; - } - - /* only work with aligned keyCode */ - if (0x3u & (uintptr_t)keyCode) - { - return kStatus_Fail; - } - - /* only work with aligned key */ - if (0x3u & (uintptr_t)key) - { - return kStatus_Fail; - } - - /* check that keyCodeSize is correct for given keySize */ - if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize)) - { - return kStatus_InvalidArgument; - } - - keyIndex = 0x0Fu & keyCode[1]; - - /* check the Key Code header byte 1. index must be non-zero for the register key. */ - if (kPUF_KeyIndex_00 == (puf_key_index_register_t)keyIndex) - { - return kStatus_Fail; - } - - keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; - keyAligned = (uint32_t *)(uintptr_t)key; - - /* begin */ - base->CTRL = PUF_CTRL_GETKEY_MASK; - - /* wait till command is accepted */ - while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) - { - } - - /* while busy send KC, read key */ - while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) - { - if (0 != (PUF_STAT_CODEINREQ_MASK & base->STAT)) - { - temp32 = 0; - if (keyCodeSize >= sizeof(uint32_t)) - { - temp32 = *keyCodeAligned; - keyCodeAligned++; - keyCodeSize -= sizeof(uint32_t); - } - base->CODEINPUT = temp32; - } - - if (0 != (PUF_STAT_KEYOUTAVAIL_MASK & base->STAT)) - { - keyIndex = base->KEYOUTINDEX; - temp32 = base->KEYOUTPUT; - if (keySize >= sizeof(uint32_t)) - { - *keyAligned = temp32; - keyAligned++; - keySize -= sizeof(uint32_t); - } - } - } - - /* get status */ - if ((keyIndex) && (0 != (base->STAT & PUF_STAT_SUCCESS_MASK))) - { - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Zeroize PUF - * - * This function clears all PUF internal logic and puts the PUF to error state. - * - * param base PUF peripheral base address - * return Status of the zeroize operation. - */ -status_t PUF_Zeroize(PUF_Type *base) -{ - status_t status = kStatus_Fail; - - /* zeroize command is always allowed */ - base->CTRL = PUF_CTRL_ZEROIZE_MASK; - - /* check that command is accepted */ - if ((0 != (base->STAT & PUF_STAT_ERROR_MASK)) && (0 == base->ALLOW)) - { - status = kStatus_Success; - } - - return status; -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_puf.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_puf.h deleted file mode 100644 index a93b351d61..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_puf.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PUF_H_ -#define _PUF_H_ - -#include -#include - -#include "fsl_common.h" - -typedef enum _puf_key_index_register -{ - kPUF_KeyIndex_00 = 0x00U, - kPUF_KeyIndex_01 = 0x01U, - kPUF_KeyIndex_02 = 0x02U, - kPUF_KeyIndex_03 = 0x03U, - kPUF_KeyIndex_04 = 0x04U, - kPUF_KeyIndex_05 = 0x05U, - kPUF_KeyIndex_06 = 0x06U, - kPUF_KeyIndex_07 = 0x07U, - kPUF_KeyIndex_08 = 0x08U, - kPUF_KeyIndex_09 = 0x09U, - kPUF_KeyIndex_10 = 0x0AU, - kPUF_KeyIndex_11 = 0x0BU, - kPUF_KeyIndex_12 = 0x0CU, - kPUF_KeyIndex_13 = 0x0DU, - kPUF_KeyIndex_14 = 0x0EU, - kPUF_KeyIndex_15 = 0x0FU, -} puf_key_index_register_t; - -typedef enum _puf_min_max -{ - kPUF_KeySizeMin = 8u, - kPUF_KeySizeMax = 512u, - kPUF_KeyIndexMax = kPUF_KeyIndex_15, -} puf_min_max_t; - -typedef enum _puf_key_slot -{ - kPUF_KeySlot0 = 0U, /*!< PUF key slot 0 */ - kPUF_KeySlot1 = 1U, /*!< PUF key slot 1 */ -#if defined(FSL_FEATURE_PUF_HAS_KEYSLOTS) && (FSL_FEATURE_PUF_HAS_KEYSLOTS > 2) - kPUF_KeySlot2 = 2U, /*!< PUF key slot 2 */ - kPUF_KeySlot3 = 3U, /*!< PUF key slot 3 */ -#endif -} puf_key_slot_t; - -/*! @brief Get Key Code size in bytes from key size in bytes at compile time. */ -#define PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(x) ((160u + ((((x << 3) + 255u) >> 8) << 8)) >> 3) -#define PUF_MIN_KEY_CODE_SIZE PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(8) -#define PUF_ACTIVATION_CODE_SIZE 1192 -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @brief Initialize PUF - * - * This function enables power to PUF block and waits until the block initializes. - * - * @param base PUF peripheral base address - * @param dischargeTimeMsec time in ms to wait for PUF SRAM to fully discharge - * @param coreClockFrequencyHz core clock frequency in Hz - * @return Status of the init operation - */ -status_t PUF_Init(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz); - -/*! - * @brief Denitialize PUF - * - * This function disables power to PUF SRAM and peripheral clock. - * - * @param base PUF peripheral base address - * @param dischargeTimeMsec time in ms to wait for PUF SRAM to fully discharge - * @param coreClockFrequencyHz core clock frequency in Hz - */ -void PUF_Deinit(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz); - -/*! - * @brief Enroll PUF - * - * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) - * and returns it to be stored in an NVM or a file. This step needs to be - * performed only once for each device. This function may be permanently disallowed by a fuse. - * - * @param base PUF peripheral base address - * @param[out] activationCode Word aligned address of the resulting activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * @return Status of enroll operation. - */ -status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize); - -/*! - * @brief Start PUF - * - * The Activation Code generated during the Enroll operation is used to - * reconstruct the digital fingerprint. This needs to be done after every power-up - * and reset. - * - * @param base PUF peripheral base address - * @param activationCode Word aligned address of the input activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. - * @return Status of start operation. - */ -status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize); - -/*! - * @brief Set intrinsic key - * - * The digital fingerprint generated during the Enroll/Start - * operations is used to generate a Key Code (KC) that defines a unique intrinsic - * key. This KC is returned to be stored in an NVM or a file. This operation - * needs to be done only once for each intrinsic key. - * Each time a Set Intrinsic Key operation is executed a new unique key is - * generated. - * - * @param base PUF peripheral base address - * @param keyIndex PUF key index register - * @param keySize Size of the intrinsic key to generate in bytes. - * @param[out] keyCode Word aligned address of the resulting key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * @return Status of set intrinsic key operation. - */ -status_t PUF_SetIntrinsicKey( - PUF_Type *base, puf_key_index_register_t keyIndex, size_t keySize, uint8_t *keyCode, size_t keyCodeSize); - -/*! - * @brief Set user key - * - * The digital fingerprint generated during the Enroll/Start - * operations and a user key (UK) provided as input are used to - * generate a Key Code (KC). This KC is sent returned to be stored - * in an NVM or a file. This operation needs to be done only once for each user key. - * - * @param base PUF peripheral base address - * @param keyIndex PUF key index register - * @param userKey Word aligned address of input user key. - * @param userKeySize Size of the input user key in bytes. - * @param[out] keyCode Word aligned address of the resulting key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize). - * @return Status of set user key operation. - */ -status_t PUF_SetUserKey(PUF_Type *base, - puf_key_index_register_t keyIndex, - const uint8_t *userKey, - size_t userKeySize, - uint8_t *keyCode, - size_t keyCodeSize); - -/*! - * @brief Reconstruct key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index registers kPUF_KeyIndex_01 to kPUF_KeyIndex_15. - * - * @param base PUF peripheral base address - * @param keyCode Word aligned address of the input key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * @param[out] key Word aligned address of output key. - * @param keySize Size of the output key in bytes. - * @return Status of get key operation. - */ -status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize); - -/*! - * @brief Reconstruct hw bus key from a key code - * - * The digital fingerprint generated during the Start operation and the KC - * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This - * operation needs to be done every time a key is needed. - * This function accepts only Key Codes created for PUF index register kPUF_KeyIndex_00. - * Such a key is output directly to a dedicated hardware bus. The reconstructed key is not exposed to system memory. - * - * @param base PUF peripheral base address - * @param keyCode Word aligned address of the input key code. - * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). - * @param keySlot key slot to output on hw bus. Parameter is ignored on devices with less than two key slots. - * @param keyMask key masking value. Shall be random for each POR/reset. Value does not have to be cryptographicaly - * secure. - * @return Status of get key operation. - */ -status_t PUF_GetHwKey( - PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, puf_key_slot_t keySlot, uint32_t keyMask); - -/*! - * @brief Zeroize PUF - * - * This function clears all PUF internal logic and puts the PUF to error state. - * - * @param base PUF peripheral base address - * @return Status of the zeroize operation. - */ -status_t PUF_Zeroize(PUF_Type *base); - -/*! - * @brief Checks if Get Key operation is allowed. - * - * This function returns true if get key operation is allowed. - * - * @param base PUF peripheral base address - * @return true if get key operation is allowed - */ -bool PUF_IsGetKeyAllowed(PUF_Type *base); - -static inline void PUF_BlockSetKey(PUF_Type *base) -{ - base->CFG |= PUF_CFG_BLOCKKEYOUTPUT_MASK; /* block set key */ -} - -static inline void PUF_BlockEnroll(PUF_Type *base) -{ - base->CFG |= PUF_CFG_BLOCKENROLL_SETKEY_MASK; /* block enroll */ -} - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -#endif /* _PUF_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_reset.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_reset.c deleted file mode 100644 index 2135e12119..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_reset.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_reset.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.reset" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -/*! - * brief Assert reset to peripheral. - * - * Asserts reset signal to specified peripheral module. - * - * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_SetPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1u << bitPos; - - assert(bitPos < 32u); - - /* reset register is in SYSCON */ - /* set bit */ - SYSCON->PRESETCTRLSET[regIndex] = bitMask; - /* wait until it reads 0b1 */ - while (0u == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) - { - } -} - -/*! - * brief Clear reset to peripheral. - * - * Clears reset signal to specified peripheral module, allows it to operate. - * - * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1u << bitPos; - - assert(bitPos < 32u); - - /* reset register is in SYSCON */ - - /* clear bit */ - SYSCON->PRESETCTRLCLR[regIndex] = bitMask; - /* wait until it reads 0b0 */ - while (bitMask == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) - { - } -} - -/*! - * brief Reset peripheral module. - * - * Reset peripheral module. - * - * param peripheral Peripheral to reset. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_PeripheralReset(reset_ip_name_t peripheral) -{ - RESET_SetPeripheralReset(peripheral); - RESET_ClearPeripheralReset(peripheral); -} - -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_reset.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_reset.h deleted file mode 100644 index 0b98f18c0c..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_reset.h +++ /dev/null @@ -1,281 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_RESET_H_ -#define _FSL_RESET_H_ - -#include -#include -#include -#include -#include "fsl_device_registers.h" - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief reset driver version 2.0.0. */ -#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! - * @brief Enumeration for peripheral reset control bits - * - * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers - */ -typedef enum _SYSCON_RSTn -{ - kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */ - kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */ - kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */ - kSRAM3_RST_SHIFT_RSTn = 0 | 5U, /**< SRAM3 reset control */ - kSRAM4_RST_SHIFT_RSTn = 0 | 6U, /**< SRAM4 reset control */ - kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ - kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ - kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */ - kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */ - kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ - kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ - kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ - kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */ - kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */ - kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ - kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ - kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ - kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ - kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ - kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */ - kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */ - kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ - - kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ - kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */ - kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ - kSCTIPU_RST_SHIFT_RSTn = 65536 | 6U, /**< SCTIPU reset control */ - kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ - kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ - kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ - kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ - kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ - kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ - kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ - kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ - kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ - kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ - kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */ - kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ - kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ - kPVT_RST_SHIFT_RSTn = 65536 | 28U, /**< PVT reset control */ - kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */ - kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */ - - kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ - kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */ - kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */ - kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */ - kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */ - kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */ - kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */ - kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ - kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */ - kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */ - kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */ - kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */ - kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ - kMUX1_RST_SHIFT_RSTn = 131072 | 14U, /**< Input mux1 reset control */ - kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */ - kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */ - kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */ - kPOWERQUAD_RST_SHIFT_RSTn = 131072 | 19U, /**< PowerQuad reset control */ - kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */ - kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ - kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ - kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ - kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */ - kCAP0_RST_SHIFT_RSTn = 131072 | 25U, /**< CASPER reset control */ - kOSTIMER1_RST_SHIFT_RSTn = 131072 | 26U, /**< OSTIMER1 reset control */ - kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */ - kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */ - kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */ - kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */ -} SYSCON_RSTn_t; - -/** Array initializers with peripheral reset bits **/ -#define ADC_RSTS \ - { \ - kADC0_RST_SHIFT_RSTn \ - } /* Reset bits for ADC peripheral */ -#define AES_RSTS \ - { \ - kAES_RST_SHIFT_RSTn \ - } /* Reset bits for AES peripheral */ -#define CRC_RSTS \ - { \ - kCRC_RST_SHIFT_RSTn \ - } /* Reset bits for CRC peripheral */ -#define CTIMER_RSTS \ - { \ - kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ - kCTIMER4_RST_SHIFT_RSTn \ - } /* Reset bits for CTIMER peripheral */ -#define DMA_RSTS_N \ - { \ - kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \ - } /* Reset bits for DMA peripheral */ - -#define FLEXCOMM_RSTS \ - { \ - kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ - kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \ - } /* Reset bits for FLEXCOMM peripheral */ -#define GINT_RSTS \ - { \ - kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ - } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ -#define GPIO_RSTS_N \ - { \ - kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ - kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \ - } /* Reset bits for GPIO peripheral */ -#define INPUTMUX_RSTS \ - { \ - kMUX0_RST_SHIFT_RSTn, kMUX1_RST_SHIFT_RSTn \ - } /* Reset bits for INPUTMUX peripheral */ -#define IOCON_RSTS \ - { \ - kIOCON_RST_SHIFT_RSTn \ - } /* Reset bits for IOCON peripheral */ -#define FLASH_RSTS \ - { \ - kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ - } /* Reset bits for Flash peripheral */ -#define MRT_RSTS \ - { \ - kMRT_RST_SHIFT_RSTn \ - } /* Reset bits for MRT peripheral */ -#define OTP_RSTS \ - { \ - kOTP_RST_SHIFT_RSTn \ - } /* Reset bits for OTP peripheral */ -#define PINT_RSTS \ - { \ - kPINT_RST_SHIFT_RSTn \ - } /* Reset bits for PINT peripheral */ -#define RNG_RSTS \ - { \ - kRNG_RST_SHIFT_RSTn \ - } /* Reset bits for RNG peripheral */ -#define SDIO_RST \ - { \ - kSDIO_RST_SHIFT_RSTn \ - } /* Reset bits for SDIO peripheral */ -#define SCT_RSTS \ - { \ - kSCT0_RST_SHIFT_RSTn \ - } /* Reset bits for SCT peripheral */ -#define SPIFI_RSTS \ - { \ - kSPIFI_RST_SHIFT_RSTn \ - } /* Reset bits for SPIFI peripheral */ -#define USB0D_RST \ - { \ - kUSB0D_RST_SHIFT_RSTn \ - } /* Reset bits for USB0D peripheral */ -#define USB0HMR_RST \ - { \ - kUSB0HMR_RST_SHIFT_RSTn \ - } /* Reset bits for USB0HMR peripheral */ -#define USB0HSL_RST \ - { \ - kUSB0HSL_RST_SHIFT_RSTn \ - } /* Reset bits for USB0HSL peripheral */ -#define USB1H_RST \ - { \ - kUSB1H_RST_SHIFT_RSTn \ - } /* Reset bits for USB1H peripheral */ -#define USB1D_RST \ - { \ - kUSB1D_RST_SHIFT_RSTn \ - } /* Reset bits for USB1D peripheral */ -#define USB1RAM_RST \ - { \ - kUSB1RAM_RST_SHIFT_RSTn \ - } /* Reset bits for USB1RAM peripheral */ -#define UTICK_RSTS \ - { \ - kUTICK_RST_SHIFT_RSTn \ - } /* Reset bits for UTICK peripheral */ -#define WWDT_RSTS \ - { \ - kWWDT_RST_SHIFT_RSTn \ - } /* Reset bits for WWDT peripheral */ -#define CAPT_RSTS_N \ - { \ - kCAP0_RST_SHIFT_RSTn \ - } /* Reset bits for CAPT peripheral */ -#define PLU_RSTS_N \ - { \ - kPLULUT_RST_SHIFT_RSTn \ - } /* Reset bits for PLU peripheral */ -#define OSTIMER_RSTS \ - { \ - kOSTIMER0_RST_SHIFT_RSTn \ - } /* Reset bits for OSTIMER peripheral */ -typedef SYSCON_RSTn_t reset_ip_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Assert reset to peripheral. - * - * Asserts reset signal to specified peripheral module. - * - * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_SetPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Clear reset to peripheral. - * - * Clears reset signal to specified peripheral module, allows it to operate. - * - * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Reset peripheral module. - * - * Reset peripheral module. - * - * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_PeripheralReset(reset_ip_name_t peripheral); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_RESET_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_rng.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_rng.c deleted file mode 100644 index 5da5be4104..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_rng.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright 2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_rng.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.rng_1" -#endif - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/******************************************************************************* - * Prototypes - *******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -void RNG_Init(RNG_Type *base) -{ - /* Clear ring oscilator disable bit*/ - PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_RNG_MASK; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Rng); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Clear POWERDOWN bit to enable RNG */ - base->POWERDOWN &= ~RNG_POWERDOWN_POWERDOWN_MASK; -} - -void RNG_Deinit(RNG_Type *base) -{ - /* Set ring oscilator disable bit*/ - PMC->PDRUNCFGSET0 = PMC_PDRUNCFG0_PDEN_RNG_MASK; - /* Set POWERDOWN bit to disable RNG */ - base->POWERDOWN |= RNG_POWERDOWN_POWERDOWN_MASK; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Rng); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t dataSize) -{ - status_t result = kStatus_Fail; - uint32_t random32; - uint32_t randomSize; - uint8_t *pRandom; - uint8_t *pData = (uint8_t *)data; - uint32_t i; - - /* Check input parameters.*/ - if (!(base && data && dataSize)) - { - result = kStatus_InvalidArgument; - } - else - { - /* Check that ring oscilator is enabled */ - if (!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_RNG_MASK)) - { - do - { - /* Read Entropy.*/ - random32 = base->RANDOM_NUMBER; - pRandom = (uint8_t *)&random32; - - if (dataSize < sizeof(random32)) - { - randomSize = dataSize; - } - else - { - randomSize = sizeof(random32); - } - - for (i = 0; i < randomSize; i++) - { - *pData++ = *pRandom++; - } - - dataSize -= randomSize; - } while (dataSize > 0); - - result = kStatus_Success; - } - } - - return result; -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_rng.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_rng.h deleted file mode 100644 index e5a7e90c48..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_rng.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_RNG_DRIVER_H_ -#define _FSL_RNG_DRIVER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup rng - * @{ - */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief RNG driver version. Version 2.0.0. - * - * Current version: 2.0.0 - * - * Change log: - * - Version 2.0.0 - * - Initial version - */ -#define FSL_RNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initializes the RNG. - * - * This function initializes the RNG. - * When called, the RNG module and ring oscillator is enabled. - * - * @param base RNG base address - * @param userConfig Pointer to the initialization configuration structure. - * @return If successful, returns the kStatus_RNG_Success. Otherwise, it returns an error. - */ -void RNG_Init(RNG_Type *base); - -/*! - * @brief Shuts down the RNG. - * - * This function shuts down the RNG. - * - * @param base RNG base address. - */ -void RNG_Deinit(RNG_Type *base); - -/*! - * @brief Gets random data. - * - * This function gets random data from the RNG. - * - * @param base RNG base address. - * @param data Pointer address used to store random data. - * @param dataSize Size of the buffer pointed by the data parameter. - * @return random data - */ -status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t data_size); - -/*! - * @brief Returns random 32-bit number. - * - * This function gets random number from the RNG. - * - * @param base RNG base address. - * @return random number - */ -static inline uint32_t RNG_GetRandomWord(RNG_Type *base) -{ - return base->RANDOM_NUMBER; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /*_FSL_RNG_H_*/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_rtc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_rtc.c deleted file mode 100644 index b9eedeec6c..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_rtc.c +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_rtc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_rtc" -#endif - -#define SECONDS_IN_A_DAY (86400U) -#define SECONDS_IN_A_HOUR (3600U) -#define SECONDS_IN_A_MINUTE (60U) -#define DAYS_IN_A_YEAR (365U) -#define YEAR_RANGE_START (1970U) -#define YEAR_RANGE_END (2099U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Checks whether the date and time passed in is valid - * - * @param datetime Pointer to structure where the date and time details are stored - * - * @return Returns false if the date & time details are out of range; true if in range - */ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); - -/*! - * @brief Converts time data from datetime to seconds - * - * @param datetime Pointer to datetime structure where the date and time details are stored - * - * @return The result of the conversion in seconds - */ -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); - -/*! - * @brief Converts time data from seconds to a datetime structure - * - * @param seconds Seconds value that needs to be converted to datetime format - * @param datetime Pointer to the datetime structure where the result of the conversion is stored - */ -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime); - -/******************************************************************************* - * Code - ******************************************************************************/ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Check year, month, hour, minute, seconds */ - if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || - (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) - { - /* If not correct then error*/ - return false; - } - - /* Adjust the days in February for a leap year */ - if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) - { - daysPerMonth[2] = 29U; - } - - /* Check the validity of the day */ - if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) - { - return false; - } - - return true; -} - -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Number of days from begin of the non Leap-year*/ - /* Number of days from begin of the non Leap-year*/ - uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; - uint32_t seconds; - - /* Compute number of days from 1970 till given year*/ - seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; - /* Add leap year days */ - seconds += ((datetime->year / 4) - (1970U / 4)); - /* Add number of days till given month*/ - seconds += monthDays[datetime->month]; - /* Add days in given month. We subtract the current day as it is - * represented in the hours, minutes and seconds field*/ - seconds += (datetime->day - 1); - /* For leap year if month less than or equal to Febraury, decrement day counter*/ - if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) - { - seconds--; - } - - seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + - (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; - - return seconds; -} - -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t x; - uint32_t secondsRemaining, days; - uint16_t daysInYear; - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Start with the seconds value that is passed in to be converted to date time format */ - secondsRemaining = seconds; - - /* Calcuate the number of days, we add 1 for the current day which is represented in the - * hours and seconds field - */ - days = secondsRemaining / SECONDS_IN_A_DAY + 1; - - /* Update seconds left*/ - secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; - - /* Calculate the datetime hour, minute and second fields */ - datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; - secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; - datetime->minute = secondsRemaining / 60U; - datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; - - /* Calculate year */ - daysInYear = DAYS_IN_A_YEAR; - datetime->year = YEAR_RANGE_START; - while (days > daysInYear) - { - /* Decrease day count by a year and increment year by 1 */ - days -= daysInYear; - datetime->year++; - - /* Adjust the number of days for a leap year */ - if (datetime->year & 3U) - { - daysInYear = DAYS_IN_A_YEAR; - } - else - { - daysInYear = DAYS_IN_A_YEAR + 1; - } - } - - /* Adjust the days in February for a leap year */ - if (!(datetime->year & 3U)) - { - daysPerMonth[2] = 29U; - } - - for (x = 1U; x <= 12U; x++) - { - if (days <= daysPerMonth[x]) - { - datetime->month = x; - break; - } - else - { - days -= daysPerMonth[x]; - } - } - - datetime->day = days; -} - -/*! - * brief Ungates the RTC clock and enables the RTC oscillator. - * - * note This API should be called at the beginning of the application using the RTC driver. - * - * param base RTC peripheral base address - */ -void RTC_Init(RTC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the RTC peripheral clock */ - CLOCK_EnableClock(kCLOCK_Rtc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_RTC_HAS_NO_RESET) && FSL_FEATURE_RTC_HAS_NO_RESET) - RESET_PeripheralReset(kRTC_RST_SHIFT_RSTn); -#endif - /* Make sure the reset bit is cleared */ - base->CTRL &= ~RTC_CTRL_SWRESET_MASK; - -#if !(defined(FSL_FEATURE_RTC_HAS_NO_OSC_PD) && FSL_FEATURE_RTC_HAS_NO_OSC_PD) - /* Make sure the RTC OSC is powered up */ - base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK; -#endif -} - -/*! - * brief Sets the RTC date and time according to the given time structure. - * - * The RTC counter must be stopped prior to calling this function as writes to the RTC - * seconds register will fail if the RTC counter is running. - * - * param base RTC peripheral base address - * param datetime Pointer to structure where the date and time details to set are stored - * - * return kStatus_Success: Success in setting the time and starting the RTC - * kStatus_InvalidArgument: Error because the datetime format is incorrect - */ -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Return error if the time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(datetime))) - { - return kStatus_InvalidArgument; - } - - /* Set time in seconds */ - base->COUNT = RTC_ConvertDatetimeToSeconds(datetime); - - return kStatus_Success; -} - -/*! - * brief Gets the RTC time and stores it in the given time structure. - * - * param base RTC peripheral base address - * param datetime Pointer to structure where the date and time details are stored. - */ -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t seconds = 0; - - seconds = base->COUNT; - RTC_ConvertSecondsToDatetime(seconds, datetime); -} - -/*! - * brief Sets the RTC alarm time - * - * The function checks whether the specified alarm time is greater than the present - * time. If not, the function does not set the alarm and returns an error. - * - * param base RTC peripheral base address - * param alarmTime Pointer to structure where the alarm time is stored. - * - * return kStatus_Success: success in setting the RTC alarm - * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect - * kStatus_Fail: Error because the alarm time has already passed - */ -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) -{ - assert(alarmTime); - - uint32_t alarmSeconds = 0; - uint32_t currSeconds = 0; - - /* Return error if the alarm time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(alarmTime))) - { - return kStatus_InvalidArgument; - } - - alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); - - /* Get the current time */ - currSeconds = base->COUNT; - - /* Return error if the alarm time has passed */ - if (alarmSeconds < currSeconds) - { - return kStatus_Fail; - } - - /* Set alarm in seconds*/ - base->MATCH = alarmSeconds; - - return kStatus_Success; -} - -/*! - * brief Returns the RTC alarm time. - * - * param base RTC peripheral base address - * param datetime Pointer to structure where the alarm date and time details are stored. - */ -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t alarmSeconds = 0; - - /* Get alarm in seconds */ - alarmSeconds = base->MATCH; - - RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_rtc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_rtc.h deleted file mode 100644 index fb9f850928..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_rtc.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_RTC_H_ -#define _FSL_RTC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup rtc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief List of RTC interrupts */ -typedef enum _rtc_interrupt_enable -{ - kRTC_AlarmInterruptEnable = RTC_CTRL_ALARMDPD_EN_MASK, /*!< Alarm interrupt.*/ - kRTC_WakeupInterruptEnable = RTC_CTRL_WAKEDPD_EN_MASK /*!< Wake-up interrupt.*/ -} rtc_interrupt_enable_t; - -/*! @brief List of RTC flags */ -typedef enum _rtc_status_flags -{ - kRTC_AlarmFlag = RTC_CTRL_ALARM1HZ_MASK, /*!< Alarm flag*/ - kRTC_WakeupFlag = RTC_CTRL_WAKE1KHZ_MASK /*!< 1kHz wake-up timer flag*/ -} rtc_status_flags_t; - -/*! @brief Structure is used to hold the date and time */ -typedef struct _rtc_datetime -{ - uint16_t year; /*!< Range from 1970 to 2099.*/ - uint8_t month; /*!< Range from 1 to 12.*/ - uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ - uint8_t hour; /*!< Range from 0 to 23.*/ - uint8_t minute; /*!< Range from 0 to 59.*/ - uint8_t second; /*!< Range from 0 to 59.*/ -} rtc_datetime_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the RTC clock and enables the RTC oscillator. - * - * @note This API should be called at the beginning of the application using the RTC driver. - * - * @param base RTC peripheral base address - */ -void RTC_Init(RTC_Type *base); - -/*! - * @brief Stop the timer and gate the RTC clock - * - * @param base RTC peripheral base address - */ -static inline void RTC_Deinit(RTC_Type *base) -{ - /* Stop the RTC timer */ - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the module clock */ - CLOCK_DisableClock(kCLOCK_Rtc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! @}*/ - -/*! - * @name Current Time & Alarm - * @{ - */ - -/*! - * @brief Sets the RTC date and time according to the given time structure. - * - * The RTC counter must be stopped prior to calling this function as writes to the RTC - * seconds register will fail if the RTC counter is running. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the date and time details to set are stored - * - * @return kStatus_Success: Success in setting the time and starting the RTC - * kStatus_InvalidArgument: Error because the datetime format is incorrect - */ -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); - -/*! - * @brief Gets the RTC time and stores it in the given time structure. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the date and time details are stored. - */ -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); - -/*! - * @brief Sets the RTC alarm time - * - * The function checks whether the specified alarm time is greater than the present - * time. If not, the function does not set the alarm and returns an error. - * - * @param base RTC peripheral base address - * @param alarmTime Pointer to structure where the alarm time is stored. - * - * @return kStatus_Success: success in setting the RTC alarm - * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect - * kStatus_Fail: Error because the alarm time has already passed - */ -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); - -/*! - * @brief Returns the RTC alarm time. - * - * @param base RTC peripheral base address - * @param datetime Pointer to structure where the alarm date and time details are stored. - */ -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); - -/*! @}*/ - -/*! - * @brief Enable the RTC high resolution timer and set the wake-up time. - * - * @param base RTC peripheral base address - * @param wakeupValue The value to be loaded into the RTC WAKE register - */ -static inline void RTC_SetWakeupCount(RTC_Type *base, uint16_t wakeupValue) -{ - /* Enable the 1kHz RTC timer */ - base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; - - /* Set the start count value into the wake-up timer */ - base->WAKE = wakeupValue; -} - -/*! - * @brief Read actual RTC counter value. - * - * @param base RTC peripheral base address - */ -static inline uint16_t RTC_GetWakeupCount(RTC_Type *base) -{ - /* Read wake-up counter */ - return RTC_WAKE_VAL(base->WAKE); -} - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected RTC interrupts. - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); - reg |= mask; - - base->CTRL = reg; -} - -/*! - * @brief Disables the selected RTC interrupts. - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK | mask); - - base->CTRL = reg; -} - -/*! - * @brief Gets the enabled RTC interrupts. - * - * @param base RTC peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) -{ - return (base->CTRL & (RTC_CTRL_ALARMDPD_EN_MASK | RTC_CTRL_WAKEDPD_EN_MASK)); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the RTC status flags - * - * @param base RTC peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) -{ - return (base->CTRL & (RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK)); -} - -/*! - * @brief Clears the RTC status flags. - * - * @param base RTC peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -static inline void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) -{ - uint32_t reg = base->CTRL; - - /* Clear flag bits to prevent accidentally clearing anything when writing back */ - reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); - - /* Write 1 to the flags we wish to clear */ - reg |= mask; - - base->CTRL = reg; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the RTC time counter. - * - * After calling this function, the timer counter increments once a second provided SR[TOF] or - * SR[TIF] are not set. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StartTimer(RTC_Type *base) -{ - base->CTRL |= RTC_CTRL_RTC_EN_MASK; -} - -/*! - * @brief Stops the RTC time counter. - * - * RTC's seconds register can be written to only when the timer is stopped. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StopTimer(RTC_Type *base) -{ - base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; -} - -/*! @}*/ - -/*! - * @brief Performs a software reset on the RTC module. - * - * This resets all RTC registers to their reset value. The bit is cleared by software explicitly clearing it. - * - * @param base RTC peripheral base address - */ -static inline void RTC_Reset(RTC_Type *base) -{ - base->CTRL |= RTC_CTRL_SWRESET_MASK; - base->CTRL &= ~RTC_CTRL_SWRESET_MASK; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_RTC_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sctimer.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sctimer.c deleted file mode 100644 index 373402b590..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sctimer.c +++ /dev/null @@ -1,702 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sctimer.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sctimer" -#endif - -/*! @brief Typedef for interrupt handler. */ -typedef void (*sctimer_isr_t)(SCT_Type *base); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base SCTimer peripheral base address - * - * @return The SCTimer instance - */ -static uint32_t SCTIMER_GetInstance(SCT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to SCT bases for each instance. */ -static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to SCT clocks for each instance. */ -static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to SCT resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_sctResets[] = SCT_RSTS_N; -#else -/*! @brief Pointers to SCT resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_sctResets[] = SCT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/*!< @brief SCTimer event Callback function. */ -static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS]; - -/*!< @brief Keep track of SCTimer event number */ -static uint32_t s_currentEvent; - -/*!< @brief Keep track of SCTimer state number */ -static uint32_t s_currentState; - -/*!< @brief Keep track of SCTimer match/capture register number */ -static uint32_t s_currentMatch; - -/*! @brief Pointer to SCTimer IRQ handler */ -static sctimer_isr_t s_sctimerIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t SCTIMER_GetInstance(SCT_Type *base) -{ - uint32_t instance; - uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < sctArrayCount; instance++) - { - if (s_sctBases[instance] == base) - { - break; - } - } - - assert(instance < sctArrayCount); - - return instance; -} - -/*! - * brief Ungates the SCTimer clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application using the SCTimer driver. - * - * param base SCTimer peripheral base address - * param config Pointer to the user configuration structure. - * - * return kStatus_Success indicates success; Else indicates failure. - */ -status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) -{ - assert(config); - uint32_t i; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the SCTimer clock*/ - CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - - /* Setup the counter operation */ - base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) | - SCT_CONFIG_UNIFY(config->enableCounterUnify); - - /* Write to the control register, clear the counter and keep the counters halted */ - base->CTRL = SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) | - SCT_CTRL_CLRCTR_L_MASK | SCT_CTRL_HALT_L_MASK; - - if (!(config->enableCounterUnify)) - { - base->CTRL |= SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) | - SCT_CTRL_CLRCTR_H_MASK | SCT_CTRL_HALT_H_MASK; - } - - /* Initial state of channel output */ - base->OUTPUT = config->outInitState; - - /* Clear the global variables */ - s_currentEvent = 0; - s_currentState = 0; - s_currentMatch = 0; - - /* Clear the callback array */ - for (i = 0; i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) - { - s_eventCallback[i] = NULL; - } - - /* Save interrupt handler */ - s_sctimerIsr = SCTIMER_EventHandleIRQ; - - return kStatus_Success; -} - -/*! - * brief Gates the SCTimer clock. - * - * param base SCTimer peripheral base address - */ -void SCTIMER_Deinit(SCT_Type *base) -{ - /* Halt the counters */ - base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the SCTimer clock*/ - CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Fills in the SCTimer configuration structure with the default settings. - * - * The default values are: - * code - * config->enableCounterUnify = true; - * config->clockMode = kSCTIMER_System_ClockMode; - * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - * config->enableBidirection_l = false; - * config->enableBidirection_h = false; - * config->prescale_l = 0; - * config->prescale_h = 0; - * config->outInitState = 0; - * endcode - * param config Pointer to the user configuration structure. - */ -void SCTIMER_GetDefaultConfig(sctimer_config_t *config) -{ - assert(config); - - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - - /* SCT operates as a unified 32-bit counter */ - config->enableCounterUnify = true; - /* System clock clocks the entire SCT module */ - config->clockMode = kSCTIMER_System_ClockMode; - /* This is used only by certain clock modes */ - config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - /* Up count mode only for the unified counter */ - config->enableBidirection_l = false; - /* Up count mode only for Counte_H */ - config->enableBidirection_h = false; - /* Prescale factor of 1 */ - config->prescale_l = 0; - /* Prescale factor of 1 for Counter_H*/ - config->prescale_h = 0; - /* Clear outputs */ - config->outInitState = 0; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This - * function will create 2 events; one of the events will trigger on match with the pulse value - * and the other will trigger when the counter matches the PWM period. The PWM period event is - * also used as a limit event to reset the counter or change direction. Both events are enabled - * for the same state. The state number can be retrieved by calling the function - * SCTIMER_GetCurrentStateNumber(). - * The counter is set to operate as one 32-bit counter (unify bit is set to 1). - * The counter operates in bi-directional mode when generating a center-aligned PWM. - * - * note When setting PWM output from multiple output pins, they all should use the same PWM mode - * i.e all PWM's should be either edge-aligned or center-aligned. - * When using this API, the PWM signal frequency of all the initialized channels must be the same. - * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the - * API's pwmFreq_Hz. - * - * param base SCTimer peripheral base address - * param pwmParams PWM parameters to configure the output - * param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t - * param pwmFreq_Hz PWM signal frequency in Hz - * param srcClock_Hz SCTimer counter clock in Hz - * param event Pointer to a variable where the PWM period event number is stored - * - * return kStatus_Success on success - * kStatus_Fail If we have hit the limit in terms of number of events created or if - * an incorrect PWM dutycylce is passed in. - */ -status_t SCTIMER_SetupPwm(SCT_Type *base, - const sctimer_pwm_signal_param_t *pwmParams, - sctimer_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - uint32_t *event) -{ - assert(pwmParams); - assert(srcClock_Hz); - assert(pwmFreq_Hz); - assert(pwmParams->output < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - uint32_t period, pulsePeriod = 0; - uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1); - uint32_t periodEvent = 0, pulseEvent = 0; - uint32_t reg; - - /* This function will create 2 events, return an error if we do not have enough events available */ - if ((s_currentEvent + 2) > FSL_FEATURE_SCT_NUMBER_OF_EVENTS) - { - return kStatus_Fail; - } - - if (pwmParams->dutyCyclePercent == 0) - { - return kStatus_Fail; - } - - /* Set unify bit to operate in 32-bit counter mode */ - base->CONFIG |= SCT_CONFIG_UNIFY_MASK; - - /* Use bi-directional mode for center-aligned PWM */ - if (mode == kSCTIMER_CenterAlignedPwm) - { - base->CTRL |= SCT_CTRL_BIDIR_L_MASK; - } - - /* Calculate PWM period match value */ - if (mode == kSCTIMER_EdgeAlignedPwm) - { - period = (sctClock / pwmFreq_Hz) - 1; - } - else - { - period = sctClock / (pwmFreq_Hz * 2); - } - - /* Calculate pulse width match value */ - pulsePeriod = (period * pwmParams->dutyCyclePercent) / 100; - - /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ - if (pwmParams->dutyCyclePercent >= 100) - { - pulsePeriod = period + 2; - } - - /* Schedule an event when we reach the PWM period */ - SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_L, &periodEvent); - - /* Schedule an event when we reach the pulse width */ - SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_L, &pulseEvent); - - /* Reset the counter when we reach the PWM period */ - SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_L, periodEvent); - - /* Return the period event to the user */ - *event = periodEvent; - - /* For high-true level */ - if (pwmParams->level == kSCTIMER_HighTrue) - { - /* Set the initial output level to low which is the inactive state */ - base->OUTPUT &= ~(1U << pwmParams->output); - - if (mode == kSCTIMER_EdgeAlignedPwm) - { - /* Set the output when we reach the PWM period */ - SCTIMER_SetupOutputSetAction(base, pwmParams->output, periodEvent); - /* Clear the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent); - } - else - { - /* Clear the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output)); - reg |= (1U << (2 * pwmParams->output)); - base->OUTPUTDIRCTRL = reg; - } - } - /* For low-true level */ - else - { - /* Set the initial output level to high which is the inactive state */ - base->OUTPUT |= (1U << pwmParams->output); - - if (mode == kSCTIMER_EdgeAlignedPwm) - { - /* Clear the output when we reach the PWM period */ - SCTIMER_SetupOutputClearAction(base, pwmParams->output, periodEvent); - /* Set the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent); - } - else - { - /* Set the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output)); - reg |= (1U << (2 * pwmParams->output)); - base->OUTPUTDIRCTRL = reg; - } - } - - return kStatus_Success; -} - -/*! - * brief Updates the duty cycle of an active PWM signal. - * - * param base SCTimer peripheral base address - * param output The output to configure - * param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100 - * param event Event number associated with this PWM signal. This was returned to the user by the - * function SCTIMER_SetupPwm(). - */ -void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event) - -{ - assert(dutyCyclePercent > 0); - assert(output < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - uint32_t periodMatchReg, pulseMatchReg; - uint32_t pulsePeriod = 0, period; - - /* Retrieve the match register number for the PWM period */ - periodMatchReg = base->EVENT[event].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK; - - /* Retrieve the match register number for the PWM pulse period */ - pulseMatchReg = base->EVENT[event + 1].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK; - - period = base->SCTMATCH[periodMatchReg]; - - /* Calculate pulse width match value */ - pulsePeriod = (period * dutyCyclePercent) / 100; - - /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent >= 100) - { - pulsePeriod = period + 2; - } - - /* Stop the counter before updating match register */ - SCTIMER_StopTimer(base, kSCTIMER_Counter_L); - - /* Update dutycycle */ - base->SCTMATCH[pulseMatchReg] = SCT_SCTMATCH_MATCHn_L(pulsePeriod); - base->SCTMATCHREL[pulseMatchReg] = SCT_SCTMATCHREL_RELOADn_L(pulsePeriod); - - /* Restart the counter */ - SCTIMER_StartTimer(base, kSCTIMER_Counter_L); -} - -/*! - * brief Create an event that is triggered on a match or IO and schedule in current state. - * - * This function will configure an event using the options provided by the user. If the event type uses - * the counter match, then the function will set the user provided match value into a match register - * and put this match register number into the event control register. - * The event is enabled for the current state and the event number is increased by one at the end. - * The function returns the event number; this event number can be used to configure actions to be - * done when this event is triggered. - * - * param base SCTimer peripheral base address - * param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t - * param matchValue The match value that will be programmed to a match register - * param whichIO The input or output that will be involved in event triggering. This field - * is ignored if the event type is "match only" - * param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as we have only 1 unified counter; hence ignored. - * param event Pointer to a variable where the new event number is stored - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of events created or - if we have reached the limit in terms of number of match registers - */ -status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, - sctimer_event_t howToMonitor, - uint32_t matchValue, - uint32_t whichIO, - sctimer_counter_t whichCounter, - uint32_t *event) -{ - uint32_t combMode = (((uint32_t)howToMonitor & SCT_EVENT_CTRL_COMBMODE_MASK) >> SCT_EVENT_CTRL_COMBMODE_SHIFT); - uint32_t currentCtrlVal = howToMonitor; - - /* Return an error if we have hit the limit in terms of number of events created */ - if (s_currentEvent >= FSL_FEATURE_SCT_NUMBER_OF_EVENTS) - { - return kStatus_Fail; - } - - /* IO only mode */ - if (combMode == 0x2U) - { - base->EVENT[s_currentEvent].CTRL = currentCtrlVal | SCT_EVENT_CTRL_IOSEL(whichIO); - } - /* Match mode only */ - else if (combMode == 0x1U) - { - /* Return an error if we have hit the limit in terms of number of number of match registers */ - if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - return kStatus_Fail; - } - - currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch); - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue); - base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue); - } - else - { - /* Select the counter, no need for this if operating in 32-bit mode */ - currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter); - base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue); - base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue); - } - base->EVENT[s_currentEvent].CTRL = currentCtrlVal; - /* Increment the match register number */ - s_currentMatch++; - } - /* Use both Match & IO */ - else - { - /* Return an error if we have hit the limit in terms of number of number of match registers */ - if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - return kStatus_Fail; - } - - currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch) | SCT_EVENT_CTRL_IOSEL(whichIO); - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue); - base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue); - } - else - { - /* Select the counter, no need for this if operating in 32-bit mode */ - currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter); - base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue); - base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue); - } - base->EVENT[s_currentEvent].CTRL = currentCtrlVal; - /* Increment the match register number */ - s_currentMatch++; - } - - /* Enable the event in the current state */ - base->EVENT[s_currentEvent].STATE = (1U << s_currentState); - - /* Return the event number */ - *event = s_currentEvent; - - /* Increment the event number */ - s_currentEvent++; - - return kStatus_Success; -} - -/*! - * brief Enable an event in the current state. - * - * This function will allow the event passed in to trigger in the current state. The event must - * be created earlier by either calling the function SCTIMER_SetupPwm() or function - * SCTIMER_CreateAndScheduleEvent() . - * - * param base SCTimer peripheral base address - * param event Event number to enable in the current state - * - */ -void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event) -{ - /* Enable event in the current state */ - base->EVENT[event].STATE |= (1U << s_currentState); -} - -/*! - * brief Increase the state by 1 - * - * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new - * state. - * - * param base SCTimer peripheral base address - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of states used - - */ -status_t SCTIMER_IncreaseState(SCT_Type *base) -{ - /* Return an error if we have hit the limit in terms of states used */ - if (s_currentState >= FSL_FEATURE_SCT_NUMBER_OF_STATES) - { - return kStatus_Fail; - } - - s_currentState++; - - return kStatus_Success; -} - -/*! - * brief Provides the current state - * - * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). - * - * param base SCTimer peripheral base address - * - * return The current state - */ -uint32_t SCTIMER_GetCurrentState(SCT_Type *base) -{ - return s_currentState; -} - -/*! - * brief Toggle the output level. - * - * This change in the output level is triggered by the event number that is passed in by the user. - * - * param base SCTimer peripheral base address - * param whichIO The output to toggle - * param event Event number that will trigger the output change - */ -void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - uint32_t reg; - - /* Set the same event to set and clear the output */ - base->OUT[whichIO].CLR |= (1U << event); - base->OUT[whichIO].SET |= (1U << event); - - /* Set the conflict resolution to toggle output */ - reg = base->RES; - reg &= ~(SCT_RES_O0RES_MASK << (2 * whichIO)); - reg |= (uint32_t)(kSCTIMER_ResolveToggle << (2 * whichIO)); - base->RES = reg; -} - -/*! - * brief Setup capture of the counter value on trigger of a selected event - * - * param base SCTimer peripheral base address - * param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. - * param captureRegister Pointer to a variable where the capture register number will be returned. User - * can read the captured value from this register when the specified event is triggered. - * param event Event number that will trigger the capture - * - * return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of match/capture registers available - */ -status_t SCTIMER_SetupCaptureAction(SCT_Type *base, - sctimer_counter_t whichCounter, - uint32_t *captureRegister, - uint32_t event) -{ - /* Return an error if we have hit the limit in terms of number of capture/match registers used */ - if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - return kStatus_Fail; - } - - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - /* Set the bit to enable event */ - base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_L(1 << event); - - /* Set this resource to be a capture rather than match */ - base->REGMODE |= SCT_REGMODE_REGMOD_L(1 << s_currentMatch); - } - else - { - /* Set bit to enable event */ - base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_H(1 << event); - - /* Set this resource to be a capture rather than match */ - base->REGMODE |= SCT_REGMODE_REGMOD_H(1 << s_currentMatch); - } - - /* Return the match register number */ - *captureRegister = s_currentMatch; - - /* Increase the match register number */ - s_currentMatch++; - - return kStatus_Success; -} - -/*! - * brief Receive noticification when the event trigger an interrupt. - * - * If the interrupt for the event is enabled by the user, then a callback can be registered - * which will be invoked when the event is triggered - * - * param base SCTimer peripheral base address - * param event Event number that will trigger the interrupt - * param callback Function to invoke when the event is triggered - */ - -void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event) -{ - s_eventCallback[event] = callback; -} - -/*! - * brief SCTimer interrupt handler. - * - * param base SCTimer peripheral base address. - */ -void SCTIMER_EventHandleIRQ(SCT_Type *base) -{ - uint32_t eventFlag = SCT0->EVFLAG; - /* Only clear the flags whose interrupt field is enabled */ - uint32_t clearFlag = (eventFlag & SCT0->EVEN); - uint32_t mask = eventFlag; - int i = 0; - - /* Invoke the callback for certain events */ - for (i = 0; (i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS) && (mask != 0); i++) - { - if (mask & 0x1) - { - if (s_eventCallback[i] != NULL) - { - s_eventCallback[i](); - } - } - mask >>= 1; - } - - /* Clear event interrupt flag */ - SCT0->EVFLAG = clearFlag; -} - -void SCT0_IRQHandler(void) -{ - s_sctimerIsr(SCT0); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sctimer.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sctimer.h deleted file mode 100644 index c27e8587c4..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sctimer.h +++ /dev/null @@ -1,808 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SCTIMER_H_ -#define _FSL_SCTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup sctimer - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ -/*@}*/ - -/*! @brief SCTimer PWM operation modes */ -typedef enum _sctimer_pwm_mode -{ - kSCTIMER_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */ - kSCTIMER_CenterAlignedPwm /*!< Center-aligned PWM */ -} sctimer_pwm_mode_t; - -/*! @brief SCTimer counters when working as two independent 16-bit counters */ -typedef enum _sctimer_counter -{ - kSCTIMER_Counter_L = 0U, /*!< Counter L */ - kSCTIMER_Counter_H /*!< Counter H */ -} sctimer_counter_t; - -/*! @brief List of SCTimer input pins */ -typedef enum _sctimer_input -{ - kSCTIMER_Input_0 = 0U, /*!< SCTIMER input 0 */ - kSCTIMER_Input_1, /*!< SCTIMER input 1 */ - kSCTIMER_Input_2, /*!< SCTIMER input 2 */ - kSCTIMER_Input_3, /*!< SCTIMER input 3 */ - kSCTIMER_Input_4, /*!< SCTIMER input 4 */ - kSCTIMER_Input_5, /*!< SCTIMER input 5 */ - kSCTIMER_Input_6, /*!< SCTIMER input 6 */ - kSCTIMER_Input_7 /*!< SCTIMER input 7 */ -} sctimer_input_t; - -/*! @brief List of SCTimer output pins */ -typedef enum _sctimer_out -{ - kSCTIMER_Out_0 = 0U, /*!< SCTIMER output 0*/ - kSCTIMER_Out_1, /*!< SCTIMER output 1 */ - kSCTIMER_Out_2, /*!< SCTIMER output 2 */ - kSCTIMER_Out_3, /*!< SCTIMER output 3 */ - kSCTIMER_Out_4, /*!< SCTIMER output 4 */ - kSCTIMER_Out_5, /*!< SCTIMER output 5 */ - kSCTIMER_Out_6, /*!< SCTIMER output 6 */ - kSCTIMER_Out_7, /*!< SCTIMER output 7 */ - kSCTIMER_Out_8, /*!< SCTIMER output 8 */ - kSCTIMER_Out_9 /*!< SCTIMER output 9 */ -} sctimer_out_t; - -/*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */ -typedef enum _sctimer_pwm_level_select -{ - kSCTIMER_LowTrue = 0U, /*!< Low true pulses */ - kSCTIMER_HighTrue /*!< High true pulses */ -} sctimer_pwm_level_select_t; - -/*! @brief Options to configure a SCTimer PWM signal */ -typedef struct _sctimer_pwm_signal_param -{ - sctimer_out_t output; /*!< The output pin to use to generate the PWM signal */ - sctimer_pwm_level_select_t level; /*!< PWM output active level select. */ - uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 1 to 100 - 100 = always active signal (100% duty cycle).*/ -} sctimer_pwm_signal_param_t; - -/*! @brief SCTimer clock mode options */ -typedef enum _sctimer_clock_mode -{ - kSCTIMER_System_ClockMode = 0U, /*!< System Clock Mode */ - kSCTIMER_Sampled_ClockMode, /*!< Sampled System Clock Mode */ - kSCTIMER_Input_ClockMode, /*!< SCT Input Clock Mode */ - kSCTIMER_Asynchronous_ClockMode /*!< Asynchronous Mode */ -} sctimer_clock_mode_t; - -/*! @brief SCTimer clock select options */ -typedef enum _sctimer_clock_select -{ - kSCTIMER_Clock_On_Rise_Input_0 = 0U, /*!< Rising edges on input 0 */ - kSCTIMER_Clock_On_Fall_Input_0, /*!< Falling edges on input 0 */ - kSCTIMER_Clock_On_Rise_Input_1, /*!< Rising edges on input 1 */ - kSCTIMER_Clock_On_Fall_Input_1, /*!< Falling edges on input 1 */ - kSCTIMER_Clock_On_Rise_Input_2, /*!< Rising edges on input 2 */ - kSCTIMER_Clock_On_Fall_Input_2, /*!< Falling edges on input 2 */ - kSCTIMER_Clock_On_Rise_Input_3, /*!< Rising edges on input 3 */ - kSCTIMER_Clock_On_Fall_Input_3, /*!< Falling edges on input 3 */ - kSCTIMER_Clock_On_Rise_Input_4, /*!< Rising edges on input 4 */ - kSCTIMER_Clock_On_Fall_Input_4, /*!< Falling edges on input 4 */ - kSCTIMER_Clock_On_Rise_Input_5, /*!< Rising edges on input 5 */ - kSCTIMER_Clock_On_Fall_Input_5, /*!< Falling edges on input 5 */ - kSCTIMER_Clock_On_Rise_Input_6, /*!< Rising edges on input 6 */ - kSCTIMER_Clock_On_Fall_Input_6, /*!< Falling edges on input 6 */ - kSCTIMER_Clock_On_Rise_Input_7, /*!< Rising edges on input 7 */ - kSCTIMER_Clock_On_Fall_Input_7 /*!< Falling edges on input 7 */ -} sctimer_clock_select_t; - -/*! - * @brief SCTimer output conflict resolution options. - * - * Specifies what action should be taken if multiple events dictate that a given output should be - * both set and cleared at the same time - */ -typedef enum _sctimer_conflict_resolution -{ - kSCTIMER_ResolveNone = 0U, /*!< No change */ - kSCTIMER_ResolveSet, /*!< Set output */ - kSCTIMER_ResolveClear, /*!< Clear output */ - kSCTIMER_ResolveToggle /*!< Toggle output */ -} sctimer_conflict_resolution_t; - -/*! @brief List of SCTimer event types */ -typedef enum _sctimer_event -{ - kSCTIMER_InputLowOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_MatchEventOnly = - (1 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_InputLowEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_InputLowAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputRiseAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputFallAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_InputHighAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - - kSCTIMER_OutputLowAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputRiseAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputFallAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), - kSCTIMER_OutputHighAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT) -} sctimer_event_t; - -/*! @brief SCTimer callback typedef. */ -typedef void (*sctimer_event_callback_t)(void); - -/*! @brief List of SCTimer interrupts */ -typedef enum _sctimer_interrupt_enable -{ - kSCTIMER_Event0InterruptEnable = (1U << 0), /*!< Event 0 interrupt */ - kSCTIMER_Event1InterruptEnable = (1U << 1), /*!< Event 1 interrupt */ - kSCTIMER_Event2InterruptEnable = (1U << 2), /*!< Event 2 interrupt */ - kSCTIMER_Event3InterruptEnable = (1U << 3), /*!< Event 3 interrupt */ - kSCTIMER_Event4InterruptEnable = (1U << 4), /*!< Event 4 interrupt */ - kSCTIMER_Event5InterruptEnable = (1U << 5), /*!< Event 5 interrupt */ - kSCTIMER_Event6InterruptEnable = (1U << 6), /*!< Event 6 interrupt */ - kSCTIMER_Event7InterruptEnable = (1U << 7), /*!< Event 7 interrupt */ - kSCTIMER_Event8InterruptEnable = (1U << 8), /*!< Event 8 interrupt */ - kSCTIMER_Event9InterruptEnable = (1U << 9), /*!< Event 9 interrupt */ - kSCTIMER_Event10InterruptEnable = (1U << 10), /*!< Event 10 interrupt */ - kSCTIMER_Event11InterruptEnable = (1U << 11), /*!< Event 11 interrupt */ - kSCTIMER_Event12InterruptEnable = (1U << 12), /*!< Event 12 interrupt */ -} sctimer_interrupt_enable_t; - -/*! @brief List of SCTimer flags */ -typedef enum _sctimer_status_flags -{ - kSCTIMER_Event0Flag = (1U << 0), /*!< Event 0 Flag */ - kSCTIMER_Event1Flag = (1U << 1), /*!< Event 1 Flag */ - kSCTIMER_Event2Flag = (1U << 2), /*!< Event 2 Flag */ - kSCTIMER_Event3Flag = (1U << 3), /*!< Event 3 Flag */ - kSCTIMER_Event4Flag = (1U << 4), /*!< Event 4 Flag */ - kSCTIMER_Event5Flag = (1U << 5), /*!< Event 5 Flag */ - kSCTIMER_Event6Flag = (1U << 6), /*!< Event 6 Flag */ - kSCTIMER_Event7Flag = (1U << 7), /*!< Event 7 Flag */ - kSCTIMER_Event8Flag = (1U << 8), /*!< Event 8 Flag */ - kSCTIMER_Event9Flag = (1U << 9), /*!< Event 9 Flag */ - kSCTIMER_Event10Flag = (1U << 10), /*!< Event 10 Flag */ - kSCTIMER_Event11Flag = (1U << 11), /*!< Event 11 Flag */ - kSCTIMER_Event12Flag = (1U << 12), /*!< Event 12 Flag */ - kSCTIMER_BusErrorLFlag = - (1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */ - kSCTIMER_BusErrorHFlag = - (int)(1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */ -} sctimer_status_flags_t; - -/*! - * @brief SCTimer configuration structure - * - * This structure holds the configuration settings for the SCTimer peripheral. To initialize this - * structure to reasonable defaults, call the SCTMR_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _sctimer_config -{ - bool enableCounterUnify; /*!< true: SCT operates as a unified 32-bit counter; - false: SCT operates as two 16-bit counters */ - sctimer_clock_mode_t clockMode; /*!< SCT clock mode value */ - sctimer_clock_select_t clockSelect; /*!< SCT clock select value */ - bool enableBidirection_l; /*!< true: Up-down count mode for the L or unified counter - false: Up count mode only for the L or unified counter */ - bool enableBidirection_h; /*!< true: Up-down count mode for the H or unified counter - false: Up count mode only for the H or unified counter. - This field is used only if the enableCounterUnify is set - to false */ - uint8_t prescale_l; /*!< Prescale value to produce the L or unified counter clock */ - uint8_t prescale_h; /*!< Prescale value to produce the H counter clock. - This field is used only if the enableCounterUnify is set - to false */ - uint8_t outInitState; /*!< Defines the initial output value */ -} sctimer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the SCTimer clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the SCTimer driver. - * - * @param base SCTimer peripheral base address - * @param config Pointer to the user configuration structure. - * - * @return kStatus_Success indicates success; Else indicates failure. - */ -status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config); - -/*! - * @brief Gates the SCTimer clock. - * - * @param base SCTimer peripheral base address - */ -void SCTIMER_Deinit(SCT_Type *base); - -/*! - * @brief Fills in the SCTimer configuration structure with the default settings. - * - * The default values are: - * @code - * config->enableCounterUnify = true; - * config->clockMode = kSCTIMER_System_ClockMode; - * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; - * config->enableBidirection_l = false; - * config->enableBidirection_h = false; - * config->prescale_l = 0; - * config->prescale_h = 0; - * config->outInitState = 0; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void SCTIMER_GetDefaultConfig(sctimer_config_t *config); - -/*! @}*/ - -/*! - * @name PWM setup operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This - * function will create 2 events; one of the events will trigger on match with the pulse value - * and the other will trigger when the counter matches the PWM period. The PWM period event is - * also used as a limit event to reset the counter or change direction. Both events are enabled - * for the same state. The state number can be retrieved by calling the function - * SCTIMER_GetCurrentStateNumber(). - * The counter is set to operate as one 32-bit counter (unify bit is set to 1). - * The counter operates in bi-directional mode when generating a center-aligned PWM. - * - * @note When setting PWM output from multiple output pins, they all should use the same PWM mode - * i.e all PWM's should be either edge-aligned or center-aligned. - * When using this API, the PWM signal frequency of all the initialized channels must be the same. - * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the - * API's pwmFreq_Hz. - * - * @param base SCTimer peripheral base address - * @param pwmParams PWM parameters to configure the output - * @param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz SCTimer counter clock in Hz - * @param event Pointer to a variable where the PWM period event number is stored - * - * @return kStatus_Success on success - * kStatus_Fail If we have hit the limit in terms of number of events created or if - * an incorrect PWM dutycylce is passed in. - */ -status_t SCTIMER_SetupPwm(SCT_Type *base, - const sctimer_pwm_signal_param_t *pwmParams, - sctimer_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - uint32_t *event); - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * @param base SCTimer peripheral base address - * @param output The output to configure - * @param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100 - * @param event Event number associated with this PWM signal. This was returned to the user by the - * function SCTIMER_SetupPwm(). - */ -void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline void SCTIMER_EnableInterrupts(SCT_Type *base, uint32_t mask) -{ - base->EVEN |= mask; -} - -/*! - * @brief Disables the selected SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline void SCTIMER_DisableInterrupts(SCT_Type *base, uint32_t mask) -{ - base->EVEN &= ~mask; -} - -/*! - * @brief Gets the enabled SCTimer interrupts. - * - * @param base SCTimer peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::sctimer_interrupt_enable_t - */ -static inline uint32_t SCTIMER_GetEnabledInterrupts(SCT_Type *base) -{ - return (base->EVEN & 0xFFFFU); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the SCTimer status flags. - * - * @param base SCTimer peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::sctimer_status_flags_t - */ -static inline uint32_t SCTIMER_GetStatusFlags(SCT_Type *base) -{ - uint32_t statusFlags = 0; - - /* Add the recorded events */ - statusFlags = (base->EVFLAG & 0xFFFFU); - - /* Add bus error flags */ - statusFlags |= (base->CONFLAG & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); - - return statusFlags; -} - -/*! - * @brief Clears the SCTimer status flags. - * - * @param base SCTimer peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::sctimer_status_flags_t - */ -static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask) -{ - /* Write to the flag registers */ - base->EVFLAG = (mask & 0xFFFFU); - base->CONFLAG = (mask & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); -} - -/*! @}*/ - -/*! - * @name Counter Start and Stop - * @{ - */ - -/*! - * @brief Starts the SCTimer counter. - * - * @param base SCTimer peripheral base address - * @param countertoStart SCTimer counter to start; if unify mode is set then function always - * writes to HALT_L bit - */ -static inline void SCTIMER_StartTimer(SCT_Type *base, sctimer_counter_t countertoStart) -{ - /* Clear HALT_L bit if counter is operating in 32-bit mode or user wants to start L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStart == kSCTIMER_Counter_L)) - { - base->CTRL &= ~(SCT_CTRL_HALT_L_MASK); - } - else - { - /* Start H counter */ - base->CTRL &= ~(SCT_CTRL_HALT_H_MASK); - } -} - -/*! - * @brief Halts the SCTimer counter. - * - * @param base SCTimer peripheral base address - * @param countertoStop SCTimer counter to stop; if unify mode is set then function always - * writes to HALT_L bit - */ -static inline void SCTIMER_StopTimer(SCT_Type *base, sctimer_counter_t countertoStop) -{ - /* Set HALT_L bit if counter is operating in 32-bit mode or user wants to stop L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStop == kSCTIMER_Counter_L)) - { - base->CTRL |= (SCT_CTRL_HALT_L_MASK); - } - else - { - /* Stop H counter */ - base->CTRL |= (SCT_CTRL_HALT_H_MASK); - } -} - -/*! @}*/ - -/*! - * @name Functions to create a new event and manage the state logic - * @{ - */ - -/*! - * @brief Create an event that is triggered on a match or IO and schedule in current state. - * - * This function will configure an event using the options provided by the user. If the event type uses - * the counter match, then the function will set the user provided match value into a match register - * and put this match register number into the event control register. - * The event is enabled for the current state and the event number is increased by one at the end. - * The function returns the event number; this event number can be used to configure actions to be - * done when this event is triggered. - * - * @param base SCTimer peripheral base address - * @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t - * @param matchValue The match value that will be programmed to a match register - * @param whichIO The input or output that will be involved in event triggering. This field - * is ignored if the event type is "match only" - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as we have only 1 unified counter; hence ignored. - * @param event Pointer to a variable where the new event number is stored - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of events created or - if we have reached the limit in terms of number of match registers - */ -status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, - sctimer_event_t howToMonitor, - uint32_t matchValue, - uint32_t whichIO, - sctimer_counter_t whichCounter, - uint32_t *event); - -/*! - * @brief Enable an event in the current state. - * - * This function will allow the event passed in to trigger in the current state. The event must - * be created earlier by either calling the function SCTIMER_SetupPwm() or function - * SCTIMER_CreateAndScheduleEvent() . - * - * @param base SCTimer peripheral base address - * @param event Event number to enable in the current state - * - */ -void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event); - -/*! - * @brief Increase the state by 1 - * - * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new - * state. - * - * @param base SCTimer peripheral base address - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of states used - - */ -status_t SCTIMER_IncreaseState(SCT_Type *base); - -/*! - * @brief Provides the current state - * - * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). - * - * @param base SCTimer peripheral base address - * - * @return The current state - */ -uint32_t SCTIMER_GetCurrentState(SCT_Type *base); - -/*! @}*/ - -/*! - * @name Actions to take in response to an event - * @{ - */ - -/*! - * @brief Setup capture of the counter value on trigger of a selected event - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. - * @param captureRegister Pointer to a variable where the capture register number will be returned. User - * can read the captured value from this register when the specified event is triggered. - * @param event Event number that will trigger the capture - * - * @return kStatus_Success on success - * kStatus_Error if we have hit the limit in terms of number of match/capture registers available - */ -status_t SCTIMER_SetupCaptureAction(SCT_Type *base, - sctimer_counter_t whichCounter, - uint32_t *captureRegister, - uint32_t event); - -/*! - * @brief Receive noticification when the event trigger an interrupt. - * - * If the interrupt for the event is enabled by the user, then a callback can be registered - * which will be invoked when the event is triggered - * - * @param base SCTimer peripheral base address - * @param event Event number that will trigger the interrupt - * @param callback Function to invoke when the event is triggered - */ - -void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event); - -/*! - * @brief Transition to the specified state. - * - * This transition will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param nextState The next state SCTimer will transition to - * @param event Event number that will trigger the state transition - */ -static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event) -{ - uint32_t reg = base->EVENT[event].CTRL; - - reg &= ~(SCT_EVENT_CTRL_STATEV_MASK); - /* Load the STATEV value when the event occurs to be the next state */ - reg |= SCT_EVENT_CTRL_STATEV(nextState) | SCT_EVENT_CTRL_STATELD_MASK; - - base->EVENT[event].CTRL = reg; -} - -/*! - * @brief Set the Output. - * - * This output will be set when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to set - * @param event Event number that will trigger the output change - */ -static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - base->OUT[whichIO].SET |= (1U << event); -} - -/*! - * @brief Clear the Output. - * - * This output will be cleared when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to clear - * @param event Event number that will trigger the output change - */ -static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event) -{ - assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - - base->OUT[whichIO].CLR |= (1U << event); -} - -/*! - * @brief Toggle the output level. - * - * This change in the output level is triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param whichIO The output to toggle - * @param event Event number that will trigger the output change - */ -void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event); - -/*! - * @brief Limit the running counter. - * - * The counter is limited when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. - * @param event Event number that will trigger the counter to be limited - */ -static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->LIMIT |= SCT_LIMIT_LIMMSK_L(1U << event); - } - else - { - base->LIMIT |= SCT_LIMIT_LIMMSK_H(1U << event); - } -} - -/*! - * @brief Stop the running counter. - * - * The counter is stopped when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. - * @param event Event number that will trigger the counter to be stopped - */ -static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->STOP |= SCT_STOP_STOPMSK_L(1U << event); - } - else - { - base->STOP |= SCT_STOP_STOPMSK_H(1U << event); - } -} - -/*! - * @brief Re-start the stopped counter. - * - * The counter will re-start when the event number that is passed in by the user is triggered. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. - * @param event Event number that will trigger the counter to re-start - */ -static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->START |= SCT_START_STARTMSK_L(1U << event); - } - else - { - base->START |= SCT_START_STARTMSK_H(1U << event); - } -} - -/*! - * @brief Halt the running counter. - * - * The counter is disabled (halted) when the event number that is passed in by the user is - * triggered. When the counter is halted, all further events are disabled. The HALT condition - * can only be removed by calling the SCTIMER_StartTimer() function. - * - * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. - * @param event Event number that will trigger the counter to be halted - */ -static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) -{ - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->HALT |= SCT_HALT_HALTMSK_L(1U << event); - } - else - { - base->HALT |= SCT_HALT_HALTMSK_H(1U << event); - } -} - -#if !(defined(FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) && FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) -/*! - * @brief Generate a DMA request. - * - * DMA request will be triggered by the event number that is passed in by the user. - * - * @param base SCTimer peripheral base address - * @param dmaNumber The DMA request to generate - * @param event Event number that will trigger the DMA request - */ -static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event) -{ - if (dmaNumber == 0) - { - base->DMA0REQUEST |= (1U << event); - } - else - { - base->DMA1REQUEST |= (1U << event); - } -} -#endif /* FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST */ - -/*! - * @brief SCTimer interrupt handler. - * - * @param base SCTimer peripheral base address. - */ -void SCTIMER_EventHandleIRQ(SCT_Type *base); - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_SCTIMER_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sdif.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sdif.c deleted file mode 100644 index d11f867714..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sdif.c +++ /dev/null @@ -1,1536 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sdif.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sdif" -#endif - -/* Typedef for interrupt handler. */ -typedef void (*sdif_isr_t)(SDIF_Type *base, sdif_handle_t *handle); - -/*! @brief convert the name here, due to RM use SDIO */ -#define SDIF_DriverIRQHandler SDIO_DriverIRQHandler -/*! @brief define the controller support sd/sdio card version 2.0 */ -#define SDIF_SUPPORT_SD_VERSION (0x20) -/*! @brief define the controller support mmc card version 4.4 */ -#define SDIF_SUPPORT_MMC_VERSION (0x44) -/*! @brief define the timeout counter */ -#define SDIF_TIMEOUT_VALUE (~0U) -/*! @brief this value can be any value */ -#define SDIF_POLL_DEMAND_VALUE (0xFFU) -/*! @brief DMA descriptor buffer1 size */ -#define SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(x) ((x)&0x1FFFU) -/*! @brief DMA descriptor buffer2 size */ -#define SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(x) (((x)&0x1FFFU) << 13U) -/*! @brief RX water mark value */ -#define SDIF_RX_WATERMARK (15U) -/*! @brief TX water mark value */ -#define SDIF_TX_WATERMARK (16U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the instance. - * - * @param base SDIF peripheral base address. - * @return Instance number. - */ -static uint32_t SDIF_GetInstance(SDIF_Type *base); - -/* -* @brief config the SDIF interface before transfer between the card and host -* @param SDIF base address -* @param transfer config structure -* @param enDMA DMA enable flag -*/ -static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer, bool enDMA); - -/* -* @brief wait the command done function and check error status -* @param SDIF base address -* @param command config structure -*/ -static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command); - -/* -* @brief transfer data in a blocking way -* @param SDIF base address -* @param data config structure -* @param indicate current transfer mode:DMA or polling -*/ -static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bool isDMA); - -/* -* @brief read the command response -* @param SDIF base address -* @param sdif command pointer -*/ -static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *command); - -/* -* @brief handle transfer command interrupt -* @param SDIF base address -* @param sdif handle -* @param interrupt mask flags -*/ -static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags); - -/* -* @brief handle transfer data interrupt -* @param SDIF base address -* @param sdif handle -* @param interrupt mask flags -*/ -static void SDIF_TransferHandleData(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags); - -/* -* @brief handle DMA transfer -* @param SDIF base address -* @param sdif handle -* @param interrupt mask flag -*/ -static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags); - -/* -* @brief driver IRQ handler -* @param SDIF base address -* @param sdif handle -*/ -static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle); - -/* -* @brief read data port -* @param SDIF base address -* @param sdif data -* @param the number of data been transferred -*/ -static uint32_t SDIF_ReadDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords); - -/* -* @brief write data port -* @param SDIF base address -* @param sdif data -* @param the number of data been transferred -*/ -static uint32_t SDIF_WriteDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords); - -/* -* @brief read data by blocking way -* @param SDIF base address -* @param sdif data -*/ -static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data); - -/* -* @brief write data by blocking way -* @param SDIF base address -* @param sdif data -*/ -static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data); - -/* -* @brief handle sdio interrupt -* This function will call the SDIO interrupt callback -* @param SDIF base address -* @param SDIF handle -*/ -static void SDIF_TransferHandleSDIOInterrupt(SDIF_Type *base, sdif_handle_t *handle); - -/* -* @brief handle card detect -* This function will call the cardInserted callback -* @param SDIF base addres -* @param SDIF handle -*/ -static void SDIF_TransferHandleCardDetect(SDIF_Type *base, sdif_handle_t *handle); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief SDIF internal handle pointer array */ -static sdif_handle_t *s_sdifHandle[FSL_FEATURE_SOC_SDIF_COUNT]; - -/*! @brief SDIF base pointer array */ -static SDIF_Type *const s_sdifBase[] = SDIF_BASE_PTRS; - -/*! @brief SDIF IRQ name array */ -static const IRQn_Type s_sdifIRQ[] = SDIF_IRQS; - -/* SDIF ISR for transactional APIs. */ -static sdif_isr_t s_sdifIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t SDIF_GetInstance(SDIF_Type *base) -{ - uint8_t instance = 0U; - - while ((instance < ARRAY_SIZE(s_sdifBase)) && (s_sdifBase[instance] != base)) - { - instance++; - } - - assert(instance < ARRAY_SIZE(s_sdifBase)); - - return instance; -} - -static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer, bool enDMA) -{ - sdif_command_t *command = transfer->command; - sdif_data_t *data = transfer->data; - - if ((command == NULL) || (data && (data->blockSize > SDIF_BLKSIZ_BLOCK_SIZE_MASK))) - { - return kStatus_SDIF_InvalidArgument; - } - - if (data != NULL) - { - /* config the block size register ,the block size maybe smaller than FIFO - depth, will test on the board */ - base->BLKSIZ = SDIF_BLKSIZ_BLOCK_SIZE(data->blockSize); - /* config the byte count register */ - base->BYTCNT = SDIF_BYTCNT_BYTE_COUNT(data->blockSize * data->blockCount); - - command->flags |= kSDIF_DataExpect; /* need transfer data flag */ - - if (data->txData != NULL) - { - command->flags |= kSDIF_DataWriteToCard; /* data transfer direction */ - } - else - { - /* config the card read threshold,enable the card read threshold */ - if (data->blockSize <= (SDIF_FIFO_COUNT * sizeof(uint32_t))) - { - base->CARDTHRCTL = SDIF_CARDTHRCTL_CARDRDTHREN_MASK | SDIF_CARDTHRCTL_CARDTHRESHOLD(data->blockSize); - } - else - { - base->CARDTHRCTL &= ~SDIF_CARDTHRCTL_CARDRDTHREN_MASK; - } - } - - if (data->streamTransfer) - { - command->flags |= kSDIF_DataStreamTransfer; /* indicate if use stream transfer or block transfer */ - } - - if ((data->enableAutoCommand12) && - (data->blockCount > 1U)) /* indicate if auto stop will send after the data transfer done */ - { - command->flags |= kSDIF_DataTransferAutoStop; - } - - if (enDMA) - { - base->INTMASK &= ~(kSDIF_DataTransferOver | kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest); - } - else - { - base->INTMASK |= (kSDIF_DataTransferOver | kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest); - } - } - /* R2 response length long */ - if (command->responseType == kCARD_ResponseTypeR2) - { - command->flags |= (kSDIF_CmdCheckResponseCRC | kSDIF_CmdResponseLengthLong | kSDIF_CmdResponseExpect); - } - else if ((command->responseType == kCARD_ResponseTypeR3) || (command->responseType == kCARD_ResponseTypeR4)) - { - command->flags |= kSDIF_CmdResponseExpect; /* response R3 do not check Response CRC */ - } - else - { - if (command->responseType != kCARD_ResponseTypeNone) - { - command->flags |= (kSDIF_CmdCheckResponseCRC | kSDIF_CmdResponseExpect); - } - } - - if (command->type == kCARD_CommandTypeAbort) - { - command->flags |= kSDIF_TransferStopAbort; - } - - /* wait pre-transfer complete */ - command->flags |= kSDIF_WaitPreTransferComplete | kSDIF_CmdDataUseHoldReg; - - return kStatus_Success; -} - -static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *command) -{ - /* check if command exist,if not, do not read the response */ - if (NULL != command) - { - /* read response */ - command->response[0U] = base->RESP[0U]; - if (command->responseType == kCARD_ResponseTypeR2) - { - command->response[1U] = base->RESP[1U]; - command->response[2U] = base->RESP[2U]; - command->response[3U] = base->RESP[3U]; - } - - if ((command->responseErrorFlags != 0U) && - ((command->responseType == kCARD_ResponseTypeR1) || (command->responseType == kCARD_ResponseTypeR1b) || - (command->responseType == kCARD_ResponseTypeR6) || (command->responseType == kCARD_ResponseTypeR5))) - { - if (((command->responseErrorFlags) & (command->response[0U])) != 0U) - { - return kStatus_SDIF_ResponseError; - } - } - } - - return kStatus_Success; -} - -static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command) -{ - uint32_t status = 0U; - - do - { - status = SDIF_GetInterruptStatus(base); - } while ((status & kSDIF_CommandDone) != kSDIF_CommandDone); - /* clear interrupt status flag first */ - SDIF_ClearInterruptStatus(base, status & kSDIF_CommandTransferStatus); - if ((status & (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout | kSDIF_HardwareLockError)) != - 0u) - { - return kStatus_SDIF_SendCmdFail; - } - else - { - return SDIF_ReadCommandResponse(base, command); - } -} - -/*! - * brief SDIF release the DMA descriptor to DMA engine - * this function should be called when DMA descriptor unavailable status occurs - * param base SDIF peripheral base address. - * param sdif DMA config pointer - */ -status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig) -{ - assert(NULL != dmaConfig); - assert(NULL != dmaConfig->dmaDesBufferStartAddr); - - sdif_dma_descriptor_t *dmaDesAddr; - uint32_t *tempDMADesBuffer = dmaConfig->dmaDesBufferStartAddr; - uint32_t dmaDesBufferSize = 0U; - - dmaDesAddr = (sdif_dma_descriptor_t *)tempDMADesBuffer; - - /* chain descriptor mode */ - if (dmaConfig->mode == kSDIF_ChainDMAMode) - { - while (((dmaDesAddr->dmaDesAttribute & (1U << kSDIF_DMADescriptorDataBufferEnd)) != - (1U << kSDIF_DMADescriptorDataBufferEnd)) && - (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t))) - { - /* set the OWN bit */ - dmaDesAddr->dmaDesAttribute |= 1U << kSDIF_DMADescriptorOwnByDMA; - dmaDesAddr++; - dmaDesBufferSize += sizeof(sdif_dma_descriptor_t); - } - /* if access dma des address overflow, return fail */ - if (dmaDesBufferSize > dmaConfig->dmaDesBufferLen * sizeof(uint32_t)) - { - return kStatus_Fail; - } - dmaDesAddr->dmaDesAttribute |= 1U << kSDIF_DMADescriptorOwnByDMA; - } - /* dual descriptor mode */ - else - { - while (((dmaDesAddr->dmaDesAttribute & (1U << kSDIF_DMADescriptorEnd)) != (1U << kSDIF_DMADescriptorEnd)) && - (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t))) - { - dmaDesAddr = (sdif_dma_descriptor_t *)tempDMADesBuffer; - dmaDesAddr->dmaDesAttribute |= 1U << kSDIF_DMADescriptorOwnByDMA; - tempDMADesBuffer += dmaConfig->dmaDesSkipLen; - } - /* if access dma des address overflow, return fail */ - if (dmaDesBufferSize > dmaConfig->dmaDesBufferLen * sizeof(uint32_t)) - { - return kStatus_Fail; - } - dmaDesAddr->dmaDesAttribute |= 1U << kSDIF_DMADescriptorOwnByDMA; - } - /* reload DMA descriptor */ - base->PLDMND = SDIF_POLL_DEMAND_VALUE; - - return kStatus_Success; -} - -static uint32_t SDIF_ReadDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords) -{ - uint32_t i; - uint32_t totalWords; - uint32_t wordsCanBeRead; /* The words can be read at this time. */ - uint32_t readWatermark = ((base->FIFOTH & SDIF_FIFOTH_RX_WMARK_MASK) >> SDIF_FIFOTH_RX_WMARK_SHIFT); - - if ((base->CTRL & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) == 0U) - { - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ - if (readWatermark >= totalWords) - { - wordsCanBeRead = totalWords; - } - /* If watermark level is less than totalWords and left words to be sent is equal or bigger than readWatermark, - transfers watermark level words. */ - else if ((readWatermark < totalWords) && ((totalWords - transferredWords) >= readWatermark)) - { - wordsCanBeRead = readWatermark; - } - /* If watermark level is less than totalWords and left words to be sent is less than readWatermark, transfers - left - words. */ - else - { - wordsCanBeRead = (totalWords - transferredWords); - } - - i = 0U; - while (i < wordsCanBeRead) - { - data->rxData[transferredWords++] = base->FIFO[i]; - i++; - } - } - - return transferredWords; -} - -static uint32_t SDIF_WriteDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords) -{ - uint32_t i; - uint32_t totalWords; - uint32_t wordsCanBeWrite; /* The words can be read at this time. */ - uint32_t writeWatermark = ((base->FIFOTH & SDIF_FIFOTH_TX_WMARK_MASK) >> SDIF_FIFOTH_TX_WMARK_SHIFT); - - if ((base->CTRL & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) == 0U) - { - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ - if (writeWatermark >= totalWords) - { - wordsCanBeWrite = totalWords; - } - /* If watermark level is less than totalWords and left words to be sent is equal or bigger than writeWatermark, - transfers watermark level words. */ - else if ((writeWatermark < totalWords) && ((totalWords - transferredWords) >= writeWatermark)) - { - wordsCanBeWrite = writeWatermark; - } - /* If watermark level is less than totalWords and left words to be sent is less than writeWatermark, transfers - left - words. */ - else - { - wordsCanBeWrite = (totalWords - transferredWords); - } - - i = 0U; - while (i < wordsCanBeWrite) - { - base->FIFO[i] = data->txData[transferredWords++]; - i++; - } - } - - return transferredWords; -} - -static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data) -{ - uint32_t totalWords; - uint32_t transferredWords = 0U; - status_t error = kStatus_Success; - uint32_t status; - bool transferOver = false; - - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - while ((transferredWords < totalWords) && (error == kStatus_Success)) - { - /* wait data transfer complete or reach RX watermark */ - do - { - status = SDIF_GetInterruptStatus(base); - if (status & kSDIF_DataTransferError) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - break; - } - } - } while (((status & (kSDIF_DataTransferOver | kSDIF_ReadFIFORequest)) == 0U) && (!transferOver)); - - if ((status & kSDIF_DataTransferOver) == kSDIF_DataTransferOver) - { - transferOver = true; - } - - if (error == kStatus_Success) - { - transferredWords = SDIF_ReadDataPort(base, data, transferredWords); - } - - /* clear interrupt status */ - SDIF_ClearInterruptStatus(base, status); - } - - return error; -} - -static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data) -{ - uint32_t totalWords; - uint32_t transferredWords = 0U; - status_t error = kStatus_Success; - uint32_t status; - - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - while ((transferredWords < totalWords) && (error == kStatus_Success)) - { - /* wait data transfer complete or reach RX watermark */ - do - { - status = SDIF_GetInterruptStatus(base); - if (status & kSDIF_DataTransferError) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - } - } - } while ((status & kSDIF_WriteFIFORequest) == 0U); - - if (error == kStatus_Success) - { - transferredWords = SDIF_WriteDataPort(base, data, transferredWords); - } - - /* clear interrupt status */ - SDIF_ClearInterruptStatus(base, status); - } - - while ((SDIF_GetInterruptStatus(base) & kSDIF_DataTransferOver) != kSDIF_DataTransferOver) - { - } - - if (SDIF_GetInterruptStatus(base) & kSDIF_DataTransferError) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - } - } - SDIF_ClearInterruptStatus(base, (kSDIF_DataTransferOver | kSDIF_DataTransferError)); - - return error; -} - -/*! - * brief reset the different block of the interface. - * param base SDIF peripheral base address. - * param mask indicate which block to reset. - * param timeout value,set to wait the bit self clear - * return reset result. - */ -bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout) -{ - /* reset through CTRL */ - base->CTRL |= mask; - /* DMA software reset */ - if (mask & kSDIF_ResetDMAInterface) - { - /* disable DMA first then do DMA software reset */ - base->BMOD = (base->BMOD & (~SDIF_BMOD_DE_MASK)) | SDIF_BMOD_SWR_MASK; - } - - /* check software DMA reset here for DMA reset also need to check this bit */ - while ((base->CTRL & mask) != 0U) - { - if (!timeout) - { - break; - } - timeout--; - } - - return timeout ? true : false; -} - -static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bool isDMA) -{ - assert(NULL != data); - - uint32_t dmaStatus = 0U; - status_t error = kStatus_Success; - - /* in DMA mode, only need to wait the complete flag and check error */ - if (isDMA) - { - do - { - dmaStatus = SDIF_GetInternalDMAStatus(base); - if ((dmaStatus & kSDIF_DMAFatalBusError) == kSDIF_DMAFatalBusError) - { - SDIF_ClearInternalDMAStatus(base, kSDIF_DMAFatalBusError | kSDIF_AbnormalInterruptSummary); - error = kStatus_SDIF_DMATransferFailWithFBE; /* in this condition,need reset */ - } - /* Card error summary, include EBE,SBE,Data CRC,RTO,DRTO,Response error */ - if ((dmaStatus & kSDIF_DMACardErrorSummary) == kSDIF_DMACardErrorSummary) - { - SDIF_ClearInternalDMAStatus(base, kSDIF_DMACardErrorSummary | kSDIF_AbnormalInterruptSummary); - if (!(data->enableIgnoreError)) - { - error = kStatus_SDIF_DataTransferFail; - } - - /* if error occur, then return */ - break; - } - } while ((dmaStatus & (kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor)) == 0U); - - /* clear the corresponding status bit */ - SDIF_ClearInternalDMAStatus(base, (kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor | - kSDIF_NormalInterruptSummary)); - - SDIF_ClearInterruptStatus(base, SDIF_GetInterruptStatus(base)); - } - else - { - if (data->rxData != NULL) - { - error = SDIF_ReadDataPortBlocking(base, data); - } - else - { - error = SDIF_WriteDataPortBlocking(base, data); - } - } - - return error; -} - -/*! - * brief send command to the card - * param base SDIF peripheral base address. - * param command configuration collection - * param timeout value - * return command excute status - */ -status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout) -{ - assert(NULL != cmd); - - base->CMDARG = cmd->argument; - base->CMD = SDIF_CMD_CMD_INDEX(cmd->index) | SDIF_CMD_START_CMD_MASK | (cmd->flags & (~SDIF_CMD_CMD_INDEX_MASK)); - - /* wait start_cmd bit auto clear within timeout */ - while ((base->CMD & SDIF_CMD_START_CMD_MASK) == SDIF_CMD_START_CMD_MASK) - { - if (!timeout) - { - break; - } - - --timeout; - } - - return timeout ? kStatus_Success : kStatus_Fail; -} - -/*! - * brief SDIF send initialize 80 clocks for SD card after initial - * param base SDIF peripheral base address. - * param timeout value - */ -bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout) -{ - bool enINT = false; - sdif_command_t command = {.index = 0U, .argument = 0U}; - - /* add for conflict with interrupt mode,close the interrupt temporary */ - if ((base->CTRL & SDIF_CTRL_INT_ENABLE_MASK) == SDIF_CTRL_INT_ENABLE_MASK) - { - enINT = true; - base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK; - } - - command.flags = SDIF_CMD_SEND_INITIALIZATION_MASK; - - if (SDIF_SendCommand(base, &command, timeout) == kStatus_Fail) - { - return false; - } - - /* wait command done */ - while ((SDIF_GetInterruptStatus(base) & kSDIF_CommandDone) != kSDIF_CommandDone) - { - } - - /* clear status */ - SDIF_ClearInterruptStatus(base, kSDIF_CommandDone); - - /* add for conflict with interrupt mode */ - if (enINT) - { - base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK; - } - - return true; -} - -/*! - * brief SDIF config the clock delay - * This function is used to config the cclk_in delay to - * sample and driver the data ,should meet the min setup - * time and hold time, and user need to config this parameter - * according to your board setting - * param target freq work mode - * param clock divider which is used to decide if use phase shift for delay - */ -void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider) -{ - uint32_t sdioClkCtrl = SYSCON->SDIOCLKCTRL; - - if (target_HZ >= SDIF_CLOCK_RANGE_NEED_DELAY) - { - if (divider == 1U) - { -#if defined(SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT) && (SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT != 0U) - sdioClkCtrl |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT); -#endif -#if defined(SDIF_HIGHSPEED_DRV_PHASE_SHIFT) && (SDIF_HIGHSPEED_DRV_PHASE_SHIFT != 0U) - sdioClkCtrl |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(SDIF_HIGHSPEED_DRV_PHASE_SHIFT); -#endif - } - else - { -#ifdef SDIF_HIGHSPEED_SAMPLE_DELAY - sdioClkCtrl |= SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_SAMPLE_DELAY); -#endif -#ifdef SDIF_HIGHSPEED_DRV_DELAY - sdioClkCtrl |= SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_DRV_DELAY); -#endif - } - } - - SYSCON->SDIOCLKCTRL = sdioClkCtrl; -} - -/*! - * brief Sets the card bus clock frequency. - * - * param base SDIF peripheral base address. - * param srcClock_Hz SDIF source clock frequency united in Hz. - * param target_HZ card bus clock frequency united in Hz. - * return The nearest frequency of busClock_Hz configured to SD bus. - */ -uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ) -{ - sdif_command_t cmd = {.index = 0U, .argument = 0U}; - uint32_t divider = 0U, targetFreq = target_HZ; - - /* if target freq bigger than the source clk, set the target_HZ to - src clk, this interface can run up to 52MHZ with card */ - if (srcClock_Hz < targetFreq) - { - targetFreq = srcClock_Hz; - } - - /* disable the clock first,need sync to CIU*/ - SDIF_EnableCardClock(base, false); - /* update the clock register and wait the pre-transfer complete */ - cmd.flags = kSDIF_CmdUpdateClockRegisterOnly | kSDIF_WaitPreTransferComplete; - SDIF_SendCommand(base, &cmd, SDIF_TIMEOUT_VALUE); - - /*calculate the divider*/ - if (targetFreq != srcClock_Hz) - { - divider = (srcClock_Hz / targetFreq + 1U) / 2U; - } - /* load the clock divider */ - base->CLKDIV = SDIF_CLKDIV_CLK_DIVIDER0(divider); - /* update the divider to CIU */ - SDIF_SendCommand(base, &cmd, SDIF_TIMEOUT_VALUE); - - /* enable the card clock and sync to CIU */ - SDIF_EnableCardClock(base, true); - SDIF_SendCommand(base, &cmd, SDIF_TIMEOUT_VALUE); - - /* config the clock delay to meet the hold time and setup time */ - SDIF_ConfigClockDelay(target_HZ, divider); - - /* return the actual card clock freq */ - - return (divider != 0U) ? (srcClock_Hz / (divider * 2U)) : srcClock_Hz; -} - -/*! - * brief SDIF abort the read data when SDIF card is in suspend state - * Once assert this bit,data state machine will be reset which is waiting for the - * next blocking data,used in SDIO card suspend sequence,should call after suspend - * cmd send - * param base SDIF peripheral base address. - * param timeout value to wait this bit self clear which indicate the data machine - * reset to idle - */ -bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout) -{ - /* assert this bit to reset the data machine to abort the read data */ - base->CTRL |= SDIF_CTRL_ABORT_READ_DATA_MASK; - /* polling the bit self clear */ - while ((base->CTRL & SDIF_CTRL_ABORT_READ_DATA_MASK) == SDIF_CTRL_ABORT_READ_DATA_MASK) - { - if (!timeout) - { - break; - } - timeout--; - } - - return base->CTRL & SDIF_CTRL_ABORT_READ_DATA_MASK ? false : true; -} - -/*! - * brief SDIF internal DMA config function - * param base SDIF peripheral base address. - * param internal DMA configuration collection - * param data buffer pointer - * param data buffer size - */ -status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize) -{ - assert(NULL != config); - assert(NULL != data); - - uint32_t dmaEntry = 0U, i, dmaBufferSize = 0U, dmaBuffer1Size = 0U; - uint32_t *tempDMADesBuffer = config->dmaDesBufferStartAddr; - const uint32_t *dataBuffer = data; - sdif_dma_descriptor_t *descriptorPoniter = NULL; - uint32_t maxDMABuffer = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE * (config->mode); - - if ((((uint32_t)data % SDIF_INTERNAL_DMA_ADDR_ALIGN) != 0U) || - (((uint32_t)tempDMADesBuffer % SDIF_INTERNAL_DMA_ADDR_ALIGN) != 0U)) - { - return kStatus_SDIF_DMAAddrNotAlign; - } - - /* check the read/write data size,must be a multiple of 4 */ - if (dataSize % sizeof(uint32_t) != 0U) - { - dataSize += sizeof(uint32_t) - (dataSize % sizeof(uint32_t)); - } - - /*config the bus mode*/ - if (config->enableFixBurstLen) - { - base->BMOD |= SDIF_BMOD_FB_MASK; - } - - /* calculate the dma descriptor entry due to DMA buffer size limit */ - /* if data size smaller than one descriptor buffer size */ - if (dataSize > maxDMABuffer) - { - dmaEntry = dataSize / maxDMABuffer + (dataSize % maxDMABuffer ? 1U : 0U); - } - else /* need one dma descriptor */ - { - dmaEntry = 1U; - } - - /* check the DMA descriptor buffer len one more time,it is user's responsibility to make sure the DMA descriptor - table - size is bigger enough to hold the transfer descriptor */ - if (config->dmaDesBufferLen * sizeof(uint32_t) < (dmaEntry * sizeof(sdif_dma_descriptor_t) + config->dmaDesSkipLen)) - { - return kStatus_SDIF_DescriptorBufferLenError; - } - - switch (config->mode) - { - case kSDIF_DualDMAMode: - base->BMOD |= SDIF_BMOD_DSL(config->dmaDesSkipLen); /* config the distance between the DMA descriptor */ - for (i = 0U; i < dmaEntry; i++) - { - if (dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE) - { - dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; - dataSize -= dmaBufferSize; - dmaBuffer1Size = dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE ? - FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE : - dataSize; - dataSize -= dmaBuffer1Size; - } - else - { - dmaBufferSize = dataSize; - dmaBuffer1Size = 0U; - } - - descriptorPoniter = (sdif_dma_descriptor_t *)tempDMADesBuffer; - if (i == 0U) - { - descriptorPoniter->dmaDesAttribute = 1U << kSDIF_DMADescriptorDataBufferStart; - } - descriptorPoniter->dmaDesAttribute |= - (1U << kSDIF_DMADescriptorOwnByDMA) | (1U << kSDIF_DisableCompleteInterrupt); - descriptorPoniter->dmaDataBufferSize = - SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize) | SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(dmaBuffer1Size); - - descriptorPoniter->dmaDataBufferAddr0 = dataBuffer; - descriptorPoniter->dmaDataBufferAddr1 = dataBuffer + dmaBufferSize / sizeof(uint32_t); - dataBuffer += (dmaBufferSize + dmaBuffer1Size) / sizeof(uint32_t); - - /* descriptor skip length */ - tempDMADesBuffer += config->dmaDesSkipLen + sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t); - } - /* enable the completion interrupt when reach the last descriptor */ - descriptorPoniter->dmaDesAttribute &= ~(1U << kSDIF_DisableCompleteInterrupt); - descriptorPoniter->dmaDesAttribute |= - (1U << kSDIF_DMADescriptorDataBufferEnd) | (1U << kSDIF_DMADescriptorEnd); - break; - - case kSDIF_ChainDMAMode: - for (i = 0U; i < dmaEntry; i++) - { - if (dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE) - { - dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; - dataSize -= FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; - } - else - { - dmaBufferSize = dataSize; - } - - descriptorPoniter = (sdif_dma_descriptor_t *)tempDMADesBuffer; - if (i == 0U) - { - descriptorPoniter->dmaDesAttribute = 1U << kSDIF_DMADescriptorDataBufferStart; - } - descriptorPoniter->dmaDesAttribute |= (1U << kSDIF_DMADescriptorOwnByDMA) | - (1U << kSDIF_DMASecondAddrChained) | - (1U << kSDIF_DisableCompleteInterrupt); - descriptorPoniter->dmaDataBufferSize = - SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize); /* use only buffer 1 for data buffer*/ - descriptorPoniter->dmaDataBufferAddr0 = dataBuffer; - dataBuffer += dmaBufferSize / sizeof(uint32_t); - tempDMADesBuffer += - sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t); /* calculate the next descriptor address */ - /* this descriptor buffer2 pointer to the next descriptor address */ - descriptorPoniter->dmaDataBufferAddr1 = tempDMADesBuffer; - } - /* enable the completion interrupt when reach the last descriptor */ - descriptorPoniter->dmaDesAttribute &= ~(1U << kSDIF_DisableCompleteInterrupt); - descriptorPoniter->dmaDesAttribute |= (1U << kSDIF_DMADescriptorDataBufferEnd); - break; - - default: - break; - } - - /* use internal DMA interface */ - base->CTRL |= SDIF_CTRL_USE_INTERNAL_DMAC_MASK; - /* enable the internal SD/MMC DMA */ - base->BMOD |= SDIF_BMOD_DE_MASK; - /* enable DMA status check */ - base->IDINTEN |= kSDIF_DMAAllStatus; - /* load DMA descriptor buffer address */ - base->DBADDR = (uint32_t)config->dmaDesBufferStartAddr; - - return kStatus_Success; -} - -#if defined(FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD) && FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD -/*! - * brief set card data bus width - * param base SDIF peripheral base address. - * param data bus width type - */ -void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type) -{ - switch (type) - { - case kSDIF_Bus1BitWidth: - base->CTYPE &= ~(SDIF_CTYPE_CARD0_WIDTH0_MASK | SDIF_CTYPE_CARD0_WIDTH1_MASK); - break; - case kSDIF_Bus4BitWidth: - base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD0_WIDTH1_MASK)) | SDIF_CTYPE_CARD0_WIDTH0_MASK; - break; - case kSDIF_Bus8BitWidth: - base->CTYPE |= SDIF_CTYPE_CARD0_WIDTH1_MASK; - break; - default: - break; - } -} - -/*! - * brief set card1 data bus width - * param base SDIF peripheral base address. - * param data bus width type - */ -void SDIF_SetCard1BusWidth(SDIF_Type *base, sdif_bus_width_t type) -{ - switch (type) - { - case kSDIF_Bus1BitWidth: - base->CTYPE &= ~(SDIF_CTYPE_CARD1_WIDTH0_MASK | SDIF_CTYPE_CARD1_WIDTH1_MASK); - break; - case kSDIF_Bus4BitWidth: - base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD1_WIDTH1_MASK)) | SDIF_CTYPE_CARD1_WIDTH0_MASK; - break; - case kSDIF_Bus8BitWidth: - base->CTYPE |= SDIF_CTYPE_CARD1_WIDTH1_MASK; - break; - default: - break; - } -} -#else -/*! - * brief set card data bus width - * param base SDIF peripheral base address. - * param data bus width type - */ -void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type) -{ - switch (type) - { - case kSDIF_Bus1BitWidth: - base->CTYPE &= ~(SDIF_CTYPE_CARD_WIDTH0_MASK | SDIF_CTYPE_CARD_WIDTH1_MASK); - break; - case kSDIF_Bus4BitWidth: - base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD_WIDTH1_MASK)) | SDIF_CTYPE_CARD_WIDTH0_MASK; - break; - case kSDIF_Bus8BitWidth: - base->CTYPE |= SDIF_CTYPE_CARD_WIDTH1_MASK; - break; - default: - break; - } -} -#endif - -/*! - * brief SDIF module initialization function. - * - * Configures the SDIF according to the user configuration. - * param base SDIF peripheral base address. - * param config SDIF configuration information. - */ -void SDIF_Init(SDIF_Type *base, sdif_config_t *config) -{ - assert(NULL != config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Sdio); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kSDIO_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - - /*config timeout register */ - base->TMOUT = ((base->TMOUT) & ~(SDIF_TMOUT_RESPONSE_TIMEOUT_MASK | SDIF_TMOUT_DATA_TIMEOUT_MASK)) | - SDIF_TMOUT_RESPONSE_TIMEOUT(config->responseTimeout) | SDIF_TMOUT_DATA_TIMEOUT(config->dataTimeout); - - /* config the card detect debounce clock count */ - base->DEBNCE = SDIF_DEBNCE_DEBOUNCE_COUNT(config->cardDetDebounce_Clock); - - /*config the watermark/burst transfer value */ - base->FIFOTH = - SDIF_FIFOTH_TX_WMARK(SDIF_TX_WATERMARK) | SDIF_FIFOTH_RX_WMARK(SDIF_RX_WATERMARK) | SDIF_FIFOTH_DMA_MTS(1U); - - /* enable the interrupt status */ - SDIF_EnableInterrupt(base, kSDIF_AllInterruptStatus); - - /* clear all interrupt/DMA status */ - SDIF_ClearInterruptStatus(base, kSDIF_AllInterruptStatus); - SDIF_ClearInternalDMAStatus(base, kSDIF_DMAAllStatus); -} - -/*! - * brief SDIF transfer function data/cmd in a blocking way - * param base SDIF peripheral base address. - * param DMA config structure - * 1. NULL - * In this condition, polling transfer mode is selected - * 2. avaliable DMA config - * In this condition, DMA transfer mode is selected - * param sdif transfer configuration collection - */ -status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer) -{ - assert(NULL != transfer); - - bool enDMA = true; - sdif_data_t *data = transfer->data; - status_t error = kStatus_Fail; - - /* if need transfer data in dma mode, config the DMA descriptor first */ - if ((data != NULL) && (dmaConfig != NULL)) - { - if ((error = SDIF_InternalDMAConfig(base, dmaConfig, data->rxData ? data->rxData : data->txData, - data->blockSize * data->blockCount)) == - kStatus_SDIF_DescriptorBufferLenError) - { - return kStatus_SDIF_DescriptorBufferLenError; - } - /* if DMA descriptor address or data buffer address not align with SDIF_INTERNAL_DMA_ADDR_ALIGN, switch to - polling transfer mode, disable the internal DMA */ - if (error == kStatus_SDIF_DMAAddrNotAlign) - { - enDMA = false; - } - } - else - { - enDMA = false; - } - - if (!enDMA) - { - SDIF_EnableInternalDMA(base, false); - /* reset FIFO and clear RAW status for host transfer */ - SDIF_Reset(base, kSDIF_ResetFIFO, SDIF_TIMEOUT_VALUE); - SDIF_ClearInterruptStatus(base, kSDIF_AllInterruptStatus); - } - - /* config the transfer parameter */ - if (SDIF_TransferConfig(base, transfer, enDMA) != kStatus_Success) - { - return kStatus_SDIF_InvalidArgument; - } - - /* send command first */ - if (SDIF_SendCommand(base, transfer->command, SDIF_TIMEOUT_VALUE) != kStatus_Success) - { - return kStatus_SDIF_SyncCmdTimeout; - } - - /* wait the command transfer done and check if error occurs */ - if (SDIF_WaitCommandDone(base, transfer->command) != kStatus_Success) - { - return kStatus_SDIF_SendCmdFail; - } - - /* if use DMA transfer mode ,check the corresponding status bit */ - if (data != NULL) - { - /* handle data transfer */ - if (SDIF_TransferDataBlocking(base, data, enDMA) != kStatus_Success) - { - return kStatus_SDIF_DataTransferFail; - } - } - - return kStatus_Success; -} - -/*! - * brief SDIF transfer function data/cmd in a non-blocking way - * this API should be use in interrupt mode, when use this API user - * must call SDIF_TransferCreateHandle first, all status check through - * interrupt - * param base SDIF peripheral base address. - * param sdif handle - * param DMA config structure - * This parameter can be config as: - * 1. NULL - In this condition, polling transfer mode is selected - 2. avaliable DMA config - In this condition, DMA transfer mode is selected - * param sdif transfer configuration collection - */ -status_t SDIF_TransferNonBlocking(SDIF_Type *base, - sdif_handle_t *handle, - sdif_dma_config_t *dmaConfig, - sdif_transfer_t *transfer) -{ - assert(NULL != transfer); - - sdif_data_t *data = transfer->data; - status_t error = kStatus_Fail; - bool enDMA = true; - - /* save the data and command before transfer */ - handle->data = transfer->data; - handle->command = transfer->command; - handle->transferredWords = 0U; - handle->interruptFlags = 0U; - handle->dmaInterruptFlags = 0U; - - if ((data != NULL) && (dmaConfig != NULL)) - { - /* use internal DMA mode to transfer between the card and host*/ - if ((error = SDIF_InternalDMAConfig(base, dmaConfig, data->rxData ? data->rxData : data->txData, - data->blockSize * data->blockCount)) == - kStatus_SDIF_DescriptorBufferLenError) - { - return kStatus_SDIF_DescriptorBufferLenError; - } - /* if DMA descriptor address or data buffer address not align with SDIF_INTERNAL_DMA_ADDR_ALIGN, switch to - polling transfer mode, disable the internal DMA */ - if (error == kStatus_SDIF_DMAAddrNotAlign) - { - enDMA = false; - } - } - else - { - enDMA = false; - } - - if (!enDMA) - { - SDIF_EnableInternalDMA(base, false); - /* reset FIFO and clear RAW status for host transfer */ - SDIF_Reset(base, kSDIF_ResetFIFO, SDIF_TIMEOUT_VALUE); - SDIF_ClearInterruptStatus(base, kSDIF_AllInterruptStatus); - } - - /* config the transfer parameter */ - if (SDIF_TransferConfig(base, transfer, enDMA) != kStatus_Success) - { - return kStatus_SDIF_InvalidArgument; - } - - /* send command first */ - if (SDIF_SendCommand(base, transfer->command, SDIF_TIMEOUT_VALUE) != kStatus_Success) - { - return kStatus_SDIF_SyncCmdTimeout; - } - - return kStatus_Success; -} - -/*! - * brief Creates the SDIF handle. - * register call back function for interrupt and enable the interrupt - * param base SDIF peripheral base address. - * param handle SDIF handle pointer. - * param callback Structure pointer to contain all callback functions. - * param userData Callback function parameter. - */ -void SDIF_TransferCreateHandle(SDIF_Type *base, - sdif_handle_t *handle, - sdif_transfer_callback_t *callback, - void *userData) -{ - assert(handle); - assert(callback); - - /* reset the handle. */ - memset(handle, 0U, sizeof(*handle)); - - /* Set the callback. */ - handle->callback.SDIOInterrupt = callback->SDIOInterrupt; - handle->callback.DMADesUnavailable = callback->DMADesUnavailable; - handle->callback.CommandReload = callback->CommandReload; - handle->callback.TransferComplete = callback->TransferComplete; - handle->callback.cardInserted = callback->cardInserted; - handle->userData = userData; - - /* Save the handle in global variables to support the double weak mechanism. */ - s_sdifHandle[SDIF_GetInstance(base)] = handle; - - /* save IRQ handler */ - s_sdifIsr = SDIF_TransferHandleIRQ; - - /* enable the global interrupt */ - SDIF_EnableGlobalInterrupt(base, true); - - EnableIRQ(s_sdifIRQ[SDIF_GetInstance(base)]); -} - -/*! - * brief SDIF return the controller capability - * param base SDIF peripheral base address. - * param sdif capability pointer - */ -void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability) -{ - assert(NULL != capability); - - /* Initializes the configure structure to zero. */ - memset(capability, 0, sizeof(*capability)); - - capability->sdVersion = SDIF_SUPPORT_SD_VERSION; - capability->mmcVersion = SDIF_SUPPORT_MMC_VERSION; - capability->maxBlockLength = SDIF_BLKSIZ_BLOCK_SIZE_MASK; - /* set the max block count = max byte count / max block size */ - capability->maxBlockCount = SDIF_BYTCNT_BYTE_COUNT_MASK / SDIF_BLKSIZ_BLOCK_SIZE_MASK; - capability->flags = kSDIF_SupportHighSpeedFlag | kSDIF_SupportDmaFlag | kSDIF_SupportSuspendResumeFlag | - kSDIF_SupportV330Flag | kSDIF_Support4BitFlag | kSDIF_Support8BitFlag; -} - -static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) -{ - assert(handle->command); - - /* cmd buffer full, in this condition user need re-send the command */ - if (interruptFlags & kSDIF_HardwareLockError) - { - if (handle->callback.CommandReload) - { - handle->callback.CommandReload(base, handle->userData); - } - } - /* transfer command done */ - else - { - if ((kSDIF_CommandDone & interruptFlags) != 0U) - { - /* transfer error */ - if (interruptFlags & (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout)) - { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_SendCmdFail, handle->userData); - } - else - { - SDIF_ReadCommandResponse(base, handle->command); - if (((handle->data) == NULL) && (handle->callback.TransferComplete)) - { - handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); - } - } - } - } -} - -static void SDIF_TransferHandleData(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) -{ - assert(handle->data); - - /* data starvation by host time out, software should read/write FIFO*/ - if (interruptFlags & kSDIF_DataStarvationByHostTimeout) - { - if (handle->data->rxData != NULL) - { - handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords); - } - else if (handle->data->txData != NULL) - { - handle->transferredWords = SDIF_WriteDataPort(base, handle->data, handle->transferredWords); - } - else - { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData); - } - } - /* data transfer fail */ - else if (interruptFlags & kSDIF_DataTransferError) - { - if (!handle->data->enableIgnoreError) - { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData); - } - } - /* need fill data to FIFO */ - else if (interruptFlags & kSDIF_WriteFIFORequest) - { - handle->transferredWords = SDIF_WriteDataPort(base, handle->data, handle->transferredWords); - } - /* need read data from FIFO */ - else if (interruptFlags & kSDIF_ReadFIFORequest) - { - handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords); - } - else - { - } - - /* data transfer over */ - if (interruptFlags & kSDIF_DataTransferOver) - { - while ((handle->data->rxData != NULL) && ((base->STATUS & SDIF_STATUS_FIFO_COUNT_MASK) != 0U)) - { - handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords); - } - handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); - } -} - -static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) -{ - if (interruptFlags & kSDIF_DMAFatalBusError) - { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_DMATransferFailWithFBE, handle->userData); - } - else if (interruptFlags & kSDIF_DMADescriptorUnavailable) - { - if (handle->callback.DMADesUnavailable) - { - handle->callback.DMADesUnavailable(base, handle->userData); - } - } - else if ((interruptFlags & (kSDIF_AbnormalInterruptSummary | kSDIF_DMACardErrorSummary)) && - (!handle->data->enableIgnoreError)) - { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData); - } - /* card normal summary */ - else - { - handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); - } -} - -static void SDIF_TransferHandleSDIOInterrupt(SDIF_Type *base, sdif_handle_t *handle) -{ - if (handle->callback.SDIOInterrupt != NULL) - { - handle->callback.SDIOInterrupt(base, handle->userData); - } -} - -static void SDIF_TransferHandleCardDetect(SDIF_Type *base, sdif_handle_t *handle) -{ - if (SDIF_DetectCardInsert(base, false)) - { - if ((handle->callback.cardInserted) != NULL) - { - handle->callback.cardInserted(base, handle->userData); - } - } - else - { - if ((handle->callback.cardRemoved) != NULL) - { - handle->callback.cardRemoved(base, handle->userData); - } - } -} - -static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle) -{ - assert(handle); - - uint32_t interruptFlags, dmaInterruptFlags; - - interruptFlags = SDIF_GetInterruptStatus(base); - dmaInterruptFlags = SDIF_GetInternalDMAStatus(base); - - handle->interruptFlags = interruptFlags; - handle->dmaInterruptFlags = dmaInterruptFlags; - - if ((interruptFlags & kSDIF_CommandTransferStatus) != 0U) - { - SDIF_TransferHandleCommand(base, handle, (interruptFlags & kSDIF_CommandTransferStatus)); - } - if ((interruptFlags & kSDIF_DataTransferStatus) != 0U) - { - SDIF_TransferHandleData(base, handle, (interruptFlags & kSDIF_DataTransferStatus)); - } - if (interruptFlags & kSDIF_SDIOInterrupt) - { - SDIF_TransferHandleSDIOInterrupt(base, handle); - } - if (dmaInterruptFlags & kSDIF_DMAAllStatus) - { - SDIF_TransferHandleDMA(base, handle, dmaInterruptFlags); - } - if (interruptFlags & kSDIF_CardDetect) - { - SDIF_TransferHandleCardDetect(base, handle); - } - - SDIF_ClearInterruptStatus(base, interruptFlags); - SDIF_ClearInternalDMAStatus(base, dmaInterruptFlags); -} - -/*! - * brief SDIF module deinit function. - * user should call this function follow with IP reset - * param base SDIF peripheral base address. - */ -void SDIF_Deinit(SDIF_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_Sdio); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* disable the SDIOCLKCTRL */ - SYSCON->SDIOCLKCTRL &= ~(SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | - SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kSDIO_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -} - -#if defined(SDIF) -void SDIF_DriverIRQHandler(void) -{ - assert(s_sdifHandle[0]); - - s_sdifIsr(SDIF, s_sdifHandle[0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sdif.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sdif.h deleted file mode 100644 index ea86d14bcd..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sdif.h +++ /dev/null @@ -1,995 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SDIF_H_ -#define _FSL_SDIF_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup sdif - * @{ - */ - -/********************************** - * Definitions. - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Driver version 2.0.10. */ -#define FSL_SDIF_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 10U)) -/*@}*/ - -/*! @brief SDIOCLKCTRL setting -* Below clock delay setting should depend on specific platform, so -* it can be redefined when timing mismatch issue occur. -* Such as: response error/CRC error and so on -*/ -/*! @brief clock range value which need to add delay to avoid timing issue */ -#ifndef SDIF_CLOCK_RANGE_NEED_DELAY -#define SDIF_CLOCK_RANGE_NEED_DELAY (50000000U) -#endif - -/* -* Fixed delay configuration -* min hold time:2ns -* min setup time: 6ns -* delay = (x+1)*250ps -*/ -/*! @brief High speed mode clk_sample fixed delay*/ -#ifndef SDIF_HIGHSPEED_SAMPLE_DELAY -#define SDIF_HIGHSPEED_SAMPLE_DELAY (0U) -#endif -/*! @brief High speed mode clk_drv fixed delay */ -#ifndef SDIF_HIGHSPEED_DRV_DELAY -#define SDIF_HIGHSPEED_DRV_DELAY (0x1FU) -#endif - -/* -* Phase shift delay configuration -* 0 degree: no delay -* 90 degree: 0.25/source clk value -* 180 degree: 0.50/source clk value -* 270 degree: 0.75/source clk value -*/ -/*! @brief High speed mode clk_sample phase shift */ -#ifndef SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT -#define SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT (0U) -#endif -/*! @brief High speed mode clk_drv phase shift */ -#ifndef SDIF_HIGHSPEED_DRV_PHASE_SHIFT -#define SDIF_HIGHSPEED_DRV_PHASE_SHIFT (1U) /* 90 degrees clk_drv phase delay */ -#endif - -/*! @brief SDIF internal DMA descriptor address and the data buffer address align */ -#define SDIF_INTERNAL_DMA_ADDR_ALIGN (4U) - -/*! @brief SDIF status */ -enum _sdif_status -{ - kStatus_SDIF_DescriptorBufferLenError = MAKE_STATUS(kStatusGroup_SDIF, 0U), /*!< Set DMA descriptor failed */ - kStatus_SDIF_InvalidArgument = MAKE_STATUS(kStatusGroup_SDIF, 1U), /*!< invalid argument status */ - kStatus_SDIF_SyncCmdTimeout = MAKE_STATUS(kStatusGroup_SDIF, 2U), /*!< sync command to CIU timeout status */ - kStatus_SDIF_SendCmdFail = MAKE_STATUS(kStatusGroup_SDIF, 3U), /*!< send command to card fail */ - kStatus_SDIF_SendCmdErrorBufferFull = - MAKE_STATUS(kStatusGroup_SDIF, 4U), /*!< send command to card fail, due to command buffer full - user need to resend this command */ - kStatus_SDIF_DMATransferFailWithFBE = - MAKE_STATUS(kStatusGroup_SDIF, 5U), /*!< DMA transfer data fail with fatal bus error , - to do with this error :issue a hard reset/controller reset*/ - kStatus_SDIF_DMATransferDescriptorUnavailable = - MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< DMA descriptor unavailable */ - kStatus_SDIF_DataTransferFail = MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< transfer data fail */ - kStatus_SDIF_ResponseError = MAKE_STATUS(kStatusGroup_SDIF, 7U), /*!< response error */ - kStatus_SDIF_DMAAddrNotAlign = MAKE_STATUS(kStatusGroup_SDIF, 8U), /*!< DMA address not align */ -}; - -/*! @brief Host controller capabilities flag mask */ -enum _sdif_capability_flag -{ - kSDIF_SupportHighSpeedFlag = 0x1U, /*!< Support high-speed */ - kSDIF_SupportDmaFlag = 0x2U, /*!< Support DMA */ - kSDIF_SupportSuspendResumeFlag = 0x4U, /*!< Support suspend/resume */ - kSDIF_SupportV330Flag = 0x8U, /*!< Support voltage 3.3V */ - kSDIF_Support4BitFlag = 0x10U, /*!< Support 4 bit mode */ - kSDIF_Support8BitFlag = 0x20U, /*!< Support 8 bit mode */ -}; - -/*! @brief define the reset type */ -enum _sdif_reset_type -{ - kSDIF_ResetController = - SDIF_CTRL_CONTROLLER_RESET_MASK, /*!< reset controller,will reset: BIU/CIU interface - CIU and state machine,ABORT_READ_DATA,SEND_IRQ_RESPONSE - and READ_WAIT bits of control register,START_CMD bit of the - command register*/ - kSDIF_ResetFIFO = SDIF_CTRL_FIFO_RESET_MASK, /*!< reset data FIFO*/ - kSDIF_ResetDMAInterface = SDIF_CTRL_DMA_RESET_MASK, /*!< reset DMA interface */ - - kSDIF_ResetAll = kSDIF_ResetController | kSDIF_ResetFIFO | /*!< reset all*/ - kSDIF_ResetDMAInterface, -}; - -/*! @brief define the card bus width type */ -typedef enum _sdif_bus_width -{ - kSDIF_Bus1BitWidth = 0U, /*!< 1bit bus width, 1bit mode and 4bit mode - share one register bit */ - kSDIF_Bus4BitWidth = 1U, /*!< 4bit mode mask */ - kSDIF_Bus8BitWidth = 2U, /*!< support 8 bit mode */ -} sdif_bus_width_t; - -/*! @brief define the command flags */ -enum _sdif_command_flags -{ - kSDIF_CmdResponseExpect = SDIF_CMD_RESPONSE_EXPECT_MASK, /*!< command request response*/ - kSDIF_CmdResponseLengthLong = SDIF_CMD_RESPONSE_LENGTH_MASK, /*!< command response length long */ - kSDIF_CmdCheckResponseCRC = SDIF_CMD_CHECK_RESPONSE_CRC_MASK, /*!< request check command response CRC*/ - kSDIF_DataExpect = SDIF_CMD_DATA_EXPECTED_MASK, /*!< request data transfer,either read/write*/ - kSDIF_DataWriteToCard = SDIF_CMD_READ_WRITE_MASK, /*!< data transfer direction */ - kSDIF_DataStreamTransfer = SDIF_CMD_TRANSFER_MODE_MASK, /*!< data transfer mode :stream/block transfer command */ - kSDIF_DataTransferAutoStop = SDIF_CMD_SEND_AUTO_STOP_MASK, /*!< data transfer with auto stop at the end of */ - kSDIF_WaitPreTransferComplete = - SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK, /*!< wait pre transfer complete before sending this cmd */ - kSDIF_TransferStopAbort = - SDIF_CMD_STOP_ABORT_CMD_MASK, /*!< when host issue stop or abort cmd to stop data transfer - ,this bit should set so that cmd/data state-machines of CIU can return - to idle correctly*/ - kSDIF_SendInitialization = - SDIF_CMD_SEND_INITIALIZATION_MASK, /*!< send initialization 80 clocks for SD card after power on */ - kSDIF_CmdUpdateClockRegisterOnly = - SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK, /*!< send cmd update the CIU clock register only */ - kSDIF_CmdtoReadCEATADevice = SDIF_CMD_READ_CEATA_DEVICE_MASK, /*!< host is perform read access to CE-ATA device */ - kSDIF_CmdExpectCCS = SDIF_CMD_CCS_EXPECTED_MASK, /*!< command expect command completion signal signal */ - kSDIF_BootModeEnable = SDIF_CMD_ENABLE_BOOT_MASK, /*!< this bit should only be set for mandatory boot mode */ - kSDIF_BootModeExpectAck = SDIF_CMD_EXPECT_BOOT_ACK_MASK, /*!< boot mode expect ack */ - kSDIF_BootModeDisable = SDIF_CMD_DISABLE_BOOT_MASK, /*!< when software set this bit along with START_CMD, CIU - terminates the boot operation*/ - kSDIF_BootModeAlternate = SDIF_CMD_BOOT_MODE_MASK, /*!< select boot mode ,alternate or mandatory*/ - kSDIF_CmdVoltageSwitch = SDIF_CMD_VOLT_SWITCH_MASK, /*!< this bit set for CMD11 only */ - kSDIF_CmdDataUseHoldReg = SDIF_CMD_USE_HOLD_REG_MASK, /*!< cmd and data send to card through the HOLD register*/ -}; - -/*! @brief The command type */ -enum _sdif_command_type -{ - kCARD_CommandTypeNormal = 0U, /*!< Normal command */ - kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */ - kCARD_CommandTypeResume = 2U, /*!< Resume command */ - kCARD_CommandTypeAbort = 3U, /*!< Abort command */ -}; - -/*! - * @brief The command response type. - * - * Define the command response type from card to host controller. - */ -enum _sdif_response_type -{ - kCARD_ResponseTypeNone = 0U, /*!< Response type: none */ - kCARD_ResponseTypeR1 = 1U, /*!< Response type: R1 */ - kCARD_ResponseTypeR1b = 2U, /*!< Response type: R1b */ - kCARD_ResponseTypeR2 = 3U, /*!< Response type: R2 */ - kCARD_ResponseTypeR3 = 4U, /*!< Response type: R3 */ - kCARD_ResponseTypeR4 = 5U, /*!< Response type: R4 */ - kCARD_ResponseTypeR5 = 6U, /*!< Response type: R5 */ - kCARD_ResponseTypeR5b = 7U, /*!< Response type: R5b */ - kCARD_ResponseTypeR6 = 8U, /*!< Response type: R6 */ - kCARD_ResponseTypeR7 = 9U, /*!< Response type: R7 */ -}; - -/*! @brief define the interrupt mask flags */ -enum _sdif_interrupt_mask -{ - kSDIF_CardDetect = SDIF_INTMASK_CDET_MASK, /*!< mask for card detect */ - kSDIF_ResponseError = SDIF_INTMASK_RE_MASK, /*!< command response error */ - kSDIF_CommandDone = SDIF_INTMASK_CDONE_MASK, /*!< command transfer over*/ - kSDIF_DataTransferOver = SDIF_INTMASK_DTO_MASK, /*!< data transfer over flag*/ - kSDIF_WriteFIFORequest = SDIF_INTMASK_TXDR_MASK, /*!< write FIFO request */ - kSDIF_ReadFIFORequest = SDIF_INTMASK_RXDR_MASK, /*!< read FIFO request */ - kSDIF_ResponseCRCError = SDIF_INTMASK_RCRC_MASK, /*!< response CRC error */ - kSDIF_DataCRCError = SDIF_INTMASK_DCRC_MASK, /*!< data CRC error */ - kSDIF_ResponseTimeout = SDIF_INTMASK_RTO_MASK, /*!< response timeout */ - kSDIF_DataReadTimeout = SDIF_INTMASK_DRTO_MASK, /*!< read data timeout */ - kSDIF_DataStarvationByHostTimeout = SDIF_INTMASK_HTO_MASK, /*!< data starvation by host time out */ - kSDIF_FIFOError = SDIF_INTMASK_FRUN_MASK, /*!< indicate the FIFO under run or overrun error */ - kSDIF_HardwareLockError = SDIF_INTMASK_HLE_MASK, /*!< hardware lock write error */ - kSDIF_DataStartBitError = SDIF_INTMASK_SBE_MASK, /*!< start bit error */ - kSDIF_AutoCmdDone = SDIF_INTMASK_ACD_MASK, /*!< indicate the auto command done */ - kSDIF_DataEndBitError = SDIF_INTMASK_EBE_MASK, /*!< end bit error */ - kSDIF_SDIOInterrupt = SDIF_INTMASK_SDIO_INT_MASK_MASK, /*!< interrupt from the SDIO card */ - - kSDIF_CommandTransferStatus = kSDIF_ResponseError | kSDIF_CommandDone | kSDIF_ResponseCRCError | - kSDIF_ResponseTimeout | - kSDIF_HardwareLockError, /*!< command transfer status collection*/ - kSDIF_DataTransferStatus = kSDIF_DataTransferOver | kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest | - kSDIF_DataCRCError | kSDIF_DataReadTimeout | kSDIF_DataStarvationByHostTimeout | - kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError | - kSDIF_AutoCmdDone, /*!< data transfer status collection */ - kSDIF_DataTransferError = - kSDIF_DataCRCError | kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError | kSDIF_DataReadTimeout, - kSDIF_AllInterruptStatus = 0x1FFFFU, /*!< all interrupt mask */ - -}; - -/*! @brief define the internal DMA status flags */ -enum _sdif_dma_status -{ - kSDIF_DMATransFinishOneDescriptor = SDIF_IDSTS_TI_MASK, /*!< DMA transfer finished for one DMA descriptor */ - kSDIF_DMARecvFinishOneDescriptor = SDIF_IDSTS_RI_MASK, /*!< DMA receive finished for one DMA descriptor */ - kSDIF_DMAFatalBusError = SDIF_IDSTS_FBE_MASK, /*!< DMA fatal bus error */ - kSDIF_DMADescriptorUnavailable = SDIF_IDSTS_DU_MASK, /*!< DMA descriptor unavailable */ - kSDIF_DMACardErrorSummary = SDIF_IDSTS_CES_MASK, /*!< card error summary */ - kSDIF_NormalInterruptSummary = SDIF_IDSTS_NIS_MASK, /*!< normal interrupt summary */ - kSDIF_AbnormalInterruptSummary = SDIF_IDSTS_AIS_MASK, /*!< abnormal interrupt summary*/ - - kSDIF_DMAAllStatus = kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor | kSDIF_DMAFatalBusError | - kSDIF_DMADescriptorUnavailable | kSDIF_DMACardErrorSummary | kSDIF_NormalInterruptSummary | - kSDIF_AbnormalInterruptSummary, - -}; - -/*! @brief define the internal DMA descriptor flag */ -enum _sdif_dma_descriptor_flag -{ - kSDIF_DisableCompleteInterrupt = 1, /*!< disable the complete interrupt flag for the ends - in the buffer pointed to by this descriptor*/ - kSDIF_DMADescriptorDataBufferEnd = 2, /*!< indicate this descriptor contain the last data buffer of data */ - kSDIF_DMADescriptorDataBufferStart = 3, /*!< indicate this descriptor contain the first data buffer - of data,if first buffer size is 0,next descriptor contain - the begin of the data*/ - - kSDIF_DMASecondAddrChained = 4, /*!< indicate that the second addr in the descriptor is the - next descriptor addr not the data buffer */ - kSDIF_DMADescriptorEnd = 5, /*!< indicate that the descriptor list reached its final descriptor*/ - kSDIF_DMADescriptorOwnByDMA = 31, /*!< indicate the descriptor is own by SD/MMC DMA */ -}; - -/*! @brief define the internal DMA mode */ -typedef enum _sdif_dma_mode -{ - kSDIF_ChainDMAMode = 0x01U, /* one descriptor with one buffer,but one descriptor point to another */ - kSDIF_DualDMAMode = 0x02U, /* dual mode is one descriptor with two buffer */ -} sdif_dma_mode_t; - -/*! @brief define the internal DMA descriptor */ -typedef struct _sdif_dma_descriptor -{ - uint32_t dmaDesAttribute; /*!< internal DMA attribute control and status */ - uint32_t dmaDataBufferSize; /*!< internal DMA transfer buffer size control */ - const uint32_t *dmaDataBufferAddr0; /*!< internal DMA buffer 0 addr ,the buffer size must be 32bit aligned */ - const uint32_t *dmaDataBufferAddr1; /*!< internal DMA buffer 1 addr ,the buffer size must be 32bit aligned */ - -} sdif_dma_descriptor_t; - -/*! @brief Defines the internal DMA configure structure. */ -typedef struct _sdif_dma_config -{ - bool enableFixBurstLen; /*!< fix burst len enable/disable flag,When set, the AHB will - use only SINGLE, INCR4, INCR8 or INCR16 during start of - normal burst transfers. When reset, the AHB will use SINGLE - and INCR burst transfer operations */ - - sdif_dma_mode_t mode; /*!< define the DMA mode */ - - uint8_t dmaDesSkipLen; /*!< define the descriptor skip length ,the length between two descriptor - this field is special for dual DMA mode */ - - uint32_t *dmaDesBufferStartAddr; /*!< internal DMA descriptor start address*/ - uint32_t dmaDesBufferLen; /*!< internal DMA buffer descriptor buffer len ,user need to pay attention to the - dma descriptor buffer length if it is bigger enough for your transfer */ - -} sdif_dma_config_t; - -/*! - * @brief Card data descriptor - */ -typedef struct _sdif_data -{ - bool streamTransfer; /*!< indicate this is a stream data transfer command */ - bool enableAutoCommand12; /*!< indicate if auto stop will send when data transfer over */ - bool enableIgnoreError; /*!< indicate if enable ignore error when transfer data */ - - size_t blockSize; /*!< Block size, take care when configure this parameter */ - uint32_t blockCount; /*!< Block count */ - uint32_t *rxData; /*!< data buffer to receive */ - const uint32_t *txData; /*!< data buffer to transfer */ -} sdif_data_t; - -/*! - * @brief Card command descriptor - * - * Define card command-related attribute. - */ -typedef struct _sdif_command -{ - uint32_t index; /*!< Command index */ - uint32_t argument; /*!< Command argument */ - uint32_t response[4U]; /*!< Response for this command */ - uint32_t type; /*!< define the command type */ - uint32_t responseType; /*!< Command response type */ - uint32_t flags; /*!< Cmd flags */ - uint32_t responseErrorFlags; /*!< response error flags, need to check the flags when - receive the cmd response */ -} sdif_command_t; - -/*! @brief Transfer state */ -typedef struct _sdif_transfer -{ - sdif_data_t *data; /*!< Data to transfer */ - sdif_command_t *command; /*!< Command to send */ -} sdif_transfer_t; - -/*! @brief Data structure to initialize the sdif */ -typedef struct _sdif_config -{ - uint8_t responseTimeout; /*!< command response timeout value */ - uint32_t cardDetDebounce_Clock; /*!< define the debounce clock count which will used in - card detect logic,typical value is 5-25ms */ - uint32_t endianMode; /*!< define endian mode ,this field is not used in this - module actually, keep for compatible with middleware*/ - uint32_t dataTimeout; /*!< data timeout value */ -} sdif_config_t; - -/*! - * @brief SDIF capability information. - * Defines a structure to get the capability information of SDIF. - */ -typedef struct _sdif_capability -{ - uint32_t sdVersion; /*!< support SD card/sdio version */ - uint32_t mmcVersion; /*!< support emmc card version */ - uint32_t maxBlockLength; /*!< Maximum block length united as byte */ - uint32_t maxBlockCount; /*!< Maximum byte count can be transfered */ - uint32_t flags; /*!< Capability flags to indicate the support information */ -} sdif_capability_t; - -/*! @brief sdif callback functions. */ -typedef struct _sdif_transfer_callback -{ - void (*cardInserted)(SDIF_Type *base, void *userData); /*!< card insert call back */ - void (*cardRemoved)(SDIF_Type *base, void *userData); /*!< card remove call back */ - void (*SDIOInterrupt)(SDIF_Type *base, void *userData); /*!< SDIO card interrupt occurs */ - void (*DMADesUnavailable)(SDIF_Type *base, void *userData); /*!< DMA descriptor unavailable */ - void (*CommandReload)(SDIF_Type *base, void *userData); /*!< command buffer full,need re-load */ - void (*TransferComplete)(SDIF_Type *base, - void *handle, - status_t status, - void *userData); /*!< Transfer complete callback */ -} sdif_transfer_callback_t; - -/*! - * @brief sdif handle - * - * Defines the structure to save the sdif state information and callback function. The detail interrupt status when - * send command or transfer data can be obtained from interruptFlags field by using mask defined in - * sdif_interrupt_flag_t; - * @note All the fields except interruptFlags and transferredWords must be allocated by the user. - */ -typedef struct _sdif_handle -{ - /* Transfer parameter */ - sdif_data_t *volatile data; /*!< Data to transfer */ - sdif_command_t *volatile command; /*!< Command to send */ - - /* Transfer status */ - volatile uint32_t interruptFlags; /*!< Interrupt flags of last transaction */ - volatile uint32_t dmaInterruptFlags; /*!< DMA interrupt flags of last transaction*/ - volatile uint32_t transferredWords; /*!< Words transferred by polling way */ - - /* Callback functions */ - sdif_transfer_callback_t callback; /*!< Callback function */ - void *userData; /*!< Parameter for transfer complete callback */ -} sdif_handle_t; - -/*! @brief sdif transfer function. */ -typedef status_t (*sdif_transfer_function_t)(SDIF_Type *base, sdif_transfer_t *content); - -/*! @brief sdif host descriptor */ -typedef struct _sdif_host -{ - SDIF_Type *base; /*!< sdif peripheral base address */ - uint32_t sourceClock_Hz; /*!< sdif source clock frequency united in Hz */ - sdif_config_t config; /*!< sdif configuration */ - sdif_transfer_function_t transfer; /*!< sdif transfer function */ - sdif_capability_t capability; /*!< sdif capability information */ -} sdif_host_t; - -/************************************************************************************************* - * API - ************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief SDIF module initialization function. - * - * Configures the SDIF according to the user configuration. - * @param base SDIF peripheral base address. - * @param config SDIF configuration information. - */ -void SDIF_Init(SDIF_Type *base, sdif_config_t *config); - -/*! - * @brief SDIF module deinit function. - * user should call this function follow with IP reset - * @param base SDIF peripheral base address. - */ -void SDIF_Deinit(SDIF_Type *base); - -/*! - * @brief SDIF send initialize 80 clocks for SD card after initial - * @param base SDIF peripheral base address. - * @param timeout value - */ -bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout); - -#if defined(FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD) && FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD -/*! - * @brief SDIF module enable/disable card0 clock. - * @param base SDIF peripheral base address. - * @param enable/disable flag - */ -static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK0_ENABLE_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK0_ENABLE_MASK; - } -} - -/*! - * @brief SDIF module enable/disable card1 clock. - * @param base SDIF peripheral base address. - * @param enable/disable flag - */ -static inline void SDIF_EnableCard1Clock(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK1_ENABLE_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK1_ENABLE_MASK; - } -} - -/*! - * @brief SDIF module enable/disable module disable the card clock - * to enter low power mode when card is idle,for SDIF cards, if - * interrupts must be detected, clock should not be stopped - * @param base SDIF peripheral base address. - * @param enable/disable flag - */ -static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK0_LOW_POWER_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK0_LOW_POWER_MASK; - } -} - -/*! - * @brief SDIF module enable/disable module disable the card clock - * to enter low power mode when card is idle,for SDIF cards, if - * interrupts must be detected, clock should not be stopped - * @param base SDIF peripheral base address. - * @param enable/disable flag - */ -static inline void SDIF_EnableCard1LowPowerMode(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK1_LOW_POWER_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK1_LOW_POWER_MASK; - } -} - -/*! - * @brief enable/disable the card0 power. - * once turn power on, software should wait for regulator/switch - * ramp-up time before trying to initialize card. - * @param base SDIF peripheral base address. - * @param enable/disable flag. - */ -static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->PWREN |= SDIF_PWREN_POWER_ENABLE0_MASK; - } - else - { - base->PWREN &= ~SDIF_PWREN_POWER_ENABLE0_MASK; - } -} - -/*! - * @brief enable/disable the card1 power. - * once turn power on, software should wait for regulator/switch - * ramp-up time before trying to initialize card. - * @param base SDIF peripheral base address. - * @param enable/disable flag. - */ -static inline void SDIF_EnableCard1Power(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->PWREN |= SDIF_PWREN_POWER_ENABLE1_MASK; - } - else - { - base->PWREN &= ~SDIF_PWREN_POWER_ENABLE1_MASK; - } -} - -/*! - * @brief set card0 data bus width - * @param base SDIF peripheral base address. - * @param data bus width type - */ -void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type); - -/*! - * @brief set card1 data bus width - * @param base SDIF peripheral base address. - * @param data bus width type - */ -void SDIF_SetCard1BusWidth(SDIF_Type *base, sdif_bus_width_t type); - -/*! - * @brief SDIF module detect card0 insert status function. - * @param base SDIF peripheral base address. - * @param data3 indicate use data3 as card insert detect pin - * @retval 1 card is inserted - * 0 card is removed - */ -static inline uint32_t SDIF_DetectCardInsert(SDIF_Type *base, bool data3) -{ - if (data3) - { - return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1U : 0U; - } - else - { - return (base->CDETECT & SDIF_CDETECT_CARD0_DETECT_MASK) == 0U ? 1U : 0U; - } -} - -/*! - * @brief SDIF module detect card1 insert status function. - * @param base SDIF peripheral base address. - * @param data3 indicate use data3 as card insert detect pin - * @retval 1 card is inserted - * 0 card is removed - */ -static inline uint32_t SDIF_DetectCard1Insert(SDIF_Type *base, bool data3) -{ - if (data3) - { - return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1U : 0U; - } - else - { - return (base->CDETECT & SDIF_CDETECT_CARD1_DETECT_MASK) == 0U ? 1U : 0U; - } -} -#else -/*! - * @brief SDIF module enable/disable card clock. - * @param base SDIF peripheral base address. - * @param enable/disable flag - */ -static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK_ENABLE_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK_ENABLE_MASK; - } -} - -/*! - * @brief SDIF module enable/disable module disable the card clock - * to enter low power mode when card is idle,for SDIF cards, if - * interrupts must be detected, clock should not be stopped - * @param base SDIF peripheral base address. - * @param enable/disable flag - */ -static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CLKENA |= SDIF_CLKENA_CCLK_LOW_POWER_MASK; - } - else - { - base->CLKENA &= ~SDIF_CLKENA_CCLK_LOW_POWER_MASK; - } -} - -/*! - * @brief enable/disable the card power. - * once turn power on, software should wait for regulator/switch - * ramp-up time before trying to initialize card. - * @param base SDIF peripheral base address. - * @param enable/disable flag. - */ -static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->PWREN |= SDIF_PWREN_POWER_ENABLE_MASK; - } - else - { - base->PWREN &= ~SDIF_PWREN_POWER_ENABLE_MASK; - } -} - -/*! - * @brief set card data bus width - * @param base SDIF peripheral base address. - * @param data bus width type - */ -void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type); - -/*! - * @brief SDIF module detect card insert status function. - * @param base SDIF peripheral base address. - * @param data3 indicate use data3 as card insert detect pin - * @retval 1 card is inserted - * 0 card is removed - */ -static inline uint32_t SDIF_DetectCardInsert(SDIF_Type *base, bool data3) -{ - if (data3) - { - return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1U : 0U; - } - else - { - return (base->CDETECT & SDIF_CDETECT_CARD_DETECT_MASK) == 0U ? 1U : 0U; - } -} -#endif - -/*! - * @brief Sets the card bus clock frequency. - * - * @param base SDIF peripheral base address. - * @param srcClock_Hz SDIF source clock frequency united in Hz. - * @param target_HZ card bus clock frequency united in Hz. - * @return The nearest frequency of busClock_Hz configured to SD bus. - */ -uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ); - -/*! - * @brief reset the different block of the interface. - * @param base SDIF peripheral base address. - * @param mask indicate which block to reset. - * @param timeout value,set to wait the bit self clear - * @return reset result. - */ -bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout); - -/*! - * @brief get the card write protect status - * @param base SDIF peripheral base address. - */ -static inline uint32_t SDIF_GetCardWriteProtect(SDIF_Type *base) -{ - return base->WRTPRT & SDIF_WRTPRT_WRITE_PROTECT_MASK; -} - -/*! - * @brief toggle state on hardware reset PIN - * This is used which card has a reset PIN typically. - * @param base SDIF peripheral base address. - */ -static inline void SDIF_AssertHardwareReset(SDIF_Type *base) -{ - base->RST_N &= ~SDIF_RST_N_CARD_RESET_MASK; -} - -/*! - * @brief send command to the card - * @param base SDIF peripheral base address. - * @param command configuration collection - * @param timeout value - * @return command excute status - */ -status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout); - -/*! - * @brief SDIF enable/disable global interrupt - * @param base SDIF peripheral base address. - * @param enable/disable flag - */ -static inline void SDIF_EnableGlobalInterrupt(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK; - } - else - { - base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK; - } -} - -/*! - * @brief SDIF enable interrupt - * @param base SDIF peripheral base address. - * @param interrupt mask - */ -static inline void SDIF_EnableInterrupt(SDIF_Type *base, uint32_t mask) -{ - base->INTMASK |= mask; -} - -/*! - * @brief SDIF disable interrupt - * @param base SDIF peripheral base address. - * @param interrupt mask - */ -static inline void SDIF_DisableInterrupt(SDIF_Type *base, uint32_t mask) -{ - base->INTMASK &= ~mask; -} - -/*! - * @brief SDIF get interrupt status - * @param base SDIF peripheral base address. - */ -static inline uint32_t SDIF_GetInterruptStatus(SDIF_Type *base) -{ - return base->MINTSTS; -} - -/*! - * @brief SDIF clear interrupt status - * @param base SDIF peripheral base address. - * @param status mask to clear - */ -static inline void SDIF_ClearInterruptStatus(SDIF_Type *base, uint32_t mask) -{ - base->RINTSTS &= mask; -} - -/*! - * @brief Creates the SDIF handle. - * register call back function for interrupt and enable the interrupt - * @param base SDIF peripheral base address. - * @param handle SDIF handle pointer. - * @param callback Structure pointer to contain all callback functions. - * @param userData Callback function parameter. - */ -void SDIF_TransferCreateHandle(SDIF_Type *base, - sdif_handle_t *handle, - sdif_transfer_callback_t *callback, - void *userData); - -/*! - * @brief SDIF enable DMA interrupt - * @param base SDIF peripheral base address. - * @param interrupt mask to set - */ -static inline void SDIF_EnableDmaInterrupt(SDIF_Type *base, uint32_t mask) -{ - base->IDINTEN |= mask; -} - -/*! - * @brief SDIF disable DMA interrupt - * @param base SDIF peripheral base address. - * @param interrupt mask to clear - */ -static inline void SDIF_DisableDmaInterrupt(SDIF_Type *base, uint32_t mask) -{ - base->IDINTEN &= ~mask; -} - -/*! - * @brief SDIF get internal DMA status - * @param base SDIF peripheral base address. - * @return the internal DMA status register - */ -static inline uint32_t SDIF_GetInternalDMAStatus(SDIF_Type *base) -{ - return base->IDSTS; -} - -/*! - * @brief SDIF clear internal DMA status - * @param base SDIF peripheral base address. - * @param status mask to clear - */ -static inline void SDIF_ClearInternalDMAStatus(SDIF_Type *base, uint32_t mask) -{ - base->IDSTS &= mask; -} - -/*! - * @brief SDIF internal DMA config function - * @param base SDIF peripheral base address. - * @param internal DMA configuration collection - * @param data buffer pointer - * @param data buffer size - */ -status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize); - -/*! - * @brief SDIF internal DMA enable - * @param base SDIF peripheral base address. - * @param enable internal DMA enable or disable flag. - */ -static inline void SDIF_EnableInternalDMA(SDIF_Type *base, bool enable) -{ - if (enable) - { - /* use internal DMA interface */ - base->CTRL |= SDIF_CTRL_USE_INTERNAL_DMAC_MASK; - /* enable the internal SD/MMC DMA */ - base->BMOD |= SDIF_BMOD_DE_MASK; - } - else - { - /* use internal DMA interface */ - base->CTRL &= ~SDIF_CTRL_USE_INTERNAL_DMAC_MASK; - /* enable the internal SD/MMC DMA */ - base->BMOD &= ~SDIF_BMOD_DE_MASK; - } -} - -/*! - * @brief SDIF send read wait to SDIF card function - * @param base SDIF peripheral base address. - */ -static inline void SDIF_SendReadWait(SDIF_Type *base) -{ - base->CTRL |= SDIF_CTRL_READ_WAIT_MASK; -} - -/*! - * @brief SDIF abort the read data when SDIF card is in suspend state - * Once assert this bit,data state machine will be reset which is waiting for the - * next blocking data,used in SDIO card suspend sequence,should call after suspend - * cmd send - * @param base SDIF peripheral base address. - * @param timeout value to wait this bit self clear which indicate the data machine - * reset to idle - */ -bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout); - -/*! - * @brief SDIF enable/disable CE-ATA card interrupt - * this bit should set together with the card register - * @param base SDIF peripheral base address. - * @param enable/disable flag - */ -static inline void SDIF_EnableCEATAInterrupt(SDIF_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK; - } - else - { - base->CTRL &= ~SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK; - } -} - -/*! - * @brief SDIF transfer function data/cmd in a non-blocking way - * this API should be use in interrupt mode, when use this API user - * must call SDIF_TransferCreateHandle first, all status check through - * interrupt - * @param base SDIF peripheral base address. - * @param sdif handle - * @param DMA config structure - * This parameter can be config as: - * 1. NULL - In this condition, polling transfer mode is selected - 2. avaliable DMA config - In this condition, DMA transfer mode is selected - * @param sdif transfer configuration collection - */ -status_t SDIF_TransferNonBlocking(SDIF_Type *base, - sdif_handle_t *handle, - sdif_dma_config_t *dmaConfig, - sdif_transfer_t *transfer); - -/*! - * @brief SDIF transfer function data/cmd in a blocking way - * @param base SDIF peripheral base address. - * @param DMA config structure - * 1. NULL - * In this condition, polling transfer mode is selected - * 2. avaliable DMA config - * In this condition, DMA transfer mode is selected - * @param sdif transfer configuration collection - */ -status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer); - -/*! - * @brief SDIF release the DMA descriptor to DMA engine - * this function should be called when DMA descriptor unavailable status occurs - * @param base SDIF peripheral base address. - * @param sdif DMA config pointer - */ -status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig); - -/*! - * @brief SDIF return the controller capability - * @param base SDIF peripheral base address. - * @param sdif capability pointer - */ -void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability); - -/*! - * @brief SDIF return the controller status - * @param base SDIF peripheral base address. - */ -static inline uint32_t SDIF_GetControllerStatus(SDIF_Type *base) -{ - return base->STATUS; -} - -/*! - * @brief SDIF send command complete signal disable to CE-ATA card - * @param base SDIF peripheral base address. - * @param send auto stop flag - */ -static inline void SDIF_SendCCSD(SDIF_Type *base, bool withAutoStop) -{ - if (withAutoStop) - { - base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK | SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK; - } - else - { - base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK; - } -} - -/*! - * @brief SDIF config the clock delay - * This function is used to config the cclk_in delay to - * sample and driver the data ,should meet the min setup - * time and hold time, and user need to config this parameter - * according to your board setting - * @param target freq work mode - * @param clock divider which is used to decide if use phase shift for delay - */ -void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider); - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! @} */ - -#endif /* _FSL_sdif_H_*/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_spi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_spi.c deleted file mode 100644 index 4985b50438..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_spi.c +++ /dev/null @@ -1,1035 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_spi.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi" -#endif - -/* Note: FIFOCFG[SIZE] has always value 1 = 8 items depth */ -#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3) - -/* Convert transfer count to transfer bytes. dataWidth is a - * range <0,15>. Range <8,15> represents 2B transfer */ -#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U)) -#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U)) -#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI_CFG_SPOL3_MASK)) - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief internal SPI config array */ -static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0}; - -/*! @brief Array to map SPI instance number to base address. */ -static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS; - -/*! @brief IRQ name array */ -static const IRQn_Type s_spiIRQ[] = SPI_IRQS; - -/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ -volatile uint8_t s_dummyData[FSL_FEATURE_SOC_SPI_COUNT] = {0}; -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the FLEXCOMM */ -/*! brief Returns instance number for SPI peripheral base address. */ -uint32_t SPI_GetInstance(SPI_Type *base) -{ - int i; - - for (i = 0; i < FSL_FEATURE_SOC_SPI_COUNT; i++) - { - if ((uint32_t)base == s_spiBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0; -} - -/*! - * brief Set up the dummy data. - * - * param base SPI peripheral address. - * param dummyData Data to be transferred when tx buffer is NULL. - */ -void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData) -{ - uint32_t instance = SPI_GetInstance(base); - s_dummyData[instance] = dummyData; -} - -/*! - * brief Returns the configurations. - * - * param base SPI peripheral address. - * return return configurations which contain datawidth and SSEL numbers. - * return data type is a pointer of spi_config_t. - */ -void *SPI_GetConfig(SPI_Type *base) -{ - int32_t instance; - instance = SPI_GetInstance(base); - if (instance < 0) - { - return NULL; - } - return &g_configs[instance]; -} - -/*! - * brief Sets the SPI master configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). - * User may use the initialized structure unchanged in SPI_MasterInit(), or modify - * some fields of the structure before calling SPI_MasterInit(). After calling this API, - * the master is ready to transfer. - * Example: - code - spi_master_config_t config; - SPI_MasterGetDefaultConfig(&config); - endcode - * - * param config pointer to master config structure - */ -void SPI_MasterGetDefaultConfig(spi_master_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - - config->enableLoopback = false; - config->enableMaster = true; - config->polarity = kSPI_ClockPolarityActiveHigh; - config->phase = kSPI_ClockPhaseFirstEdge; - config->direction = kSPI_MsbFirst; - config->baudRate_Bps = 500000U; - config->dataWidth = kSPI_Data8Bits; - config->sselNum = kSPI_Ssel0; - config->txWatermark = kSPI_TxFifo0; - config->rxWatermark = kSPI_RxFifo1; - config->sselPol = kSPI_SpolActiveAllLow; - config->delayConfig.preDelay = 0U; - config->delayConfig.postDelay = 0U; - config->delayConfig.frameDelay = 0U; - config->delayConfig.transferDelay = 0U; -} - -/*! - * brief Initializes the SPI with master configuration. - * - * The configuration structure can be filled by user from scratch, or be set with default - * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. - * Example - code - spi_master_config_t config = { - .baudRate_Bps = 400000, - ... - }; - SPI_MasterInit(SPI0, &config); - endcode - * - * param base SPI base pointer - * param config pointer to master configuration structure - * param srcClock_Hz Source clock frequency. - */ -status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) -{ - int32_t result = 0, instance = 0; - uint32_t tmp; - - /* assert params */ - assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to SPI mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - assert(kStatus_Success == result); - if (kStatus_Success != result) - { - return result; - } - - /* set divider */ - result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - /* get instance number */ - instance = SPI_GetInstance(base); - assert(instance >= 0); - - /* configure SPI mode */ - tmp = base->CFG; - tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | - SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); - /* phase */ - tmp |= SPI_CFG_CPHA(config->phase); - /* polarity */ - tmp |= SPI_CFG_CPOL(config->polarity); - /* direction */ - tmp |= SPI_CFG_LSBF(config->direction); - /* master mode */ - tmp |= SPI_CFG_MASTER(1); - /* loopback */ - tmp |= SPI_CFG_LOOP(config->enableLoopback); - /* configure active level for all CS */ - tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); - base->CFG = tmp; - - /* store configuration */ - g_configs[instance].dataWidth = config->dataWidth; - g_configs[instance].sselNum = config->sselNum; - /* enable FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; - /* trigger level - empty txFIFO, one item in rxFIFO */ - tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable generating interrupts for FIFOTRIG levels */ - tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; - /* set FIFOTRIG */ - base->FIFOTRIG = tmp; - - /* Set the delay configuration. */ - SPI_SetTransferDelay(base, &config->delayConfig); - /* Set the dummy data. */ - SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); - - SPI_Enable(base, config->enableMaster); - return kStatus_Success; -} - -/*! - * brief Sets the SPI slave configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). - * Modify some fields of the structure before calling SPI_SlaveInit(). - * Example: - code - spi_slave_config_t config; - SPI_SlaveGetDefaultConfig(&config); - endcode - * - * param config pointer to slave configuration structure - */ -void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - - config->enableSlave = true; - config->polarity = kSPI_ClockPolarityActiveHigh; - config->phase = kSPI_ClockPhaseFirstEdge; - config->direction = kSPI_MsbFirst; - config->dataWidth = kSPI_Data8Bits; - config->txWatermark = kSPI_TxFifo0; - config->rxWatermark = kSPI_RxFifo1; - config->sselPol = kSPI_SpolActiveAllLow; -} - -/*! - * brief Initializes the SPI with slave configuration. - * - * The configuration structure can be filled by user from scratch or be set with - * default values by SPI_SlaveGetDefaultConfig(). - * After calling this API, the slave is ready to transfer. - * Example - code - spi_slave_config_t config = { - .polarity = flexSPIClockPolarity_ActiveHigh; - .phase = flexSPIClockPhase_FirstEdge; - .direction = flexSPIMsbFirst; - ... - }; - SPI_SlaveInit(SPI0, &config); - endcode - * - * param base SPI base pointer - * param config pointer to slave configuration structure - */ -status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) -{ - int32_t result = 0, instance; - uint32_t tmp; - - /* assert params */ - assert(!((NULL == base) || (NULL == config))); - if ((NULL == base) || (NULL == config)) - { - return kStatus_InvalidArgument; - } - /* configure flexcomm to SPI, enable clock gate */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - assert(kStatus_Success == result); - if (kStatus_Success != result) - { - return result; - } - - instance = SPI_GetInstance(base); - - /* configure SPI mode */ - tmp = base->CFG; - tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_ENABLE_MASK | - SPI_SSELPOL_MASK); - /* phase */ - tmp |= SPI_CFG_CPHA(config->phase); - /* polarity */ - tmp |= SPI_CFG_CPOL(config->polarity); - /* direction */ - tmp |= SPI_CFG_LSBF(config->direction); - /* configure active level for all CS */ - tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); - base->CFG = tmp; - - /* store configuration */ - g_configs[instance].dataWidth = config->dataWidth; - /* empty and enable FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; - /* trigger level - empty txFIFO, one item in rxFIFO */ - tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable generating interrupts for FIFOTRIG levels */ - tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; - /* set FIFOTRIG */ - base->FIFOTRIG = tmp; - - SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); - - SPI_Enable(base, config->enableSlave); - return kStatus_Success; -} - -/*! - * brief De-initializes the SPI. - * - * Calling this API resets the SPI module, gates the SPI clock. - * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. - * - * param base SPI base pointer - */ -void SPI_Deinit(SPI_Type *base) -{ - /* Assert arguments */ - assert(NULL != base); - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK | - SPI_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK); - base->CFG &= ~(SPI_CFG_ENABLE_MASK); -} - -/*! - * brief Enables the DMA request from SPI txFIFO. - * - * param base SPI base pointer - * param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableTxDMA(SPI_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK; - } -} - -/*! - * brief Enables the DMA request from SPI rxFIFO. - * - * param base SPI base pointer - * param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableRxDMA(SPI_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK; - } -} - -/*! - * brief Sets the baud rate for SPI transfer. This is only used in master. - * - * param base SPI base pointer - * param baudrate_Bps baud rate needed in Hz. - * param srcClock_Hz SPI source clock frequency in Hz. - */ -status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t tmp; - - /* assert params */ - assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))); - if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* calculate baudrate */ - tmp = (srcClock_Hz / baudrate_Bps) - 1; - if (tmp > 0xFFFF) - { - return kStatus_SPI_BaudrateNotSupport; - } - base->DIV &= ~SPI_DIV_DIVVAL_MASK; - base->DIV |= SPI_DIV_DIVVAL(tmp); - return kStatus_Success; -} - -/*! - * brief Writes a data into the SPI data register. - * - * param base SPI base pointer - * param data needs to be write. - * param configFlags transfer configuration options ref spi_xfer_option_t - */ -void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags) -{ - uint32_t control = 0; - int32_t instance; - - /* check params */ - assert(NULL != base); - /* get and check instance */ - instance = SPI_GetInstance(base); - assert(!(instance < 0)); - if (instance < 0) - { - return; - } - - /* set data width */ - control |= SPI_FIFOWR_LEN(g_configs[instance].dataWidth); - /* set sssel */ - control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum))); - /* mask configFlags */ - control |= (configFlags & SPI_FIFOWR_FLAGS_MASK); - /* control should not affect lower 16 bits */ - assert(!(control & 0xFFFF)); - base->FIFOWR = data | control; -} - -/*! - * brief Initializes the SPI master handle. - * - * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * param base SPI peripheral base address. - * param handle SPI handle pointer. - * param callback Callback function. - * param userData User data. - */ -status_t SPI_MasterTransferCreateHandle(SPI_Type *base, - spi_master_handle_t *handle, - spi_master_callback_t callback, - void *userData) -{ - int32_t instance = 0; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - /* get flexcomm instance by 'base' param */ - instance = SPI_GetInstance(base); - assert(!(instance < 0)); - if (instance < 0) - { - return kStatus_InvalidArgument; - } - - memset(handle, 0, sizeof(*handle)); - /* Initialize the handle */ - if (base->CFG & SPI_CFG_MASTER_MASK) - { - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)SPI_MasterTransferHandleIRQ, handle); - } - else - { - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)SPI_SlaveTransferHandleIRQ, handle); - } - - handle->dataWidth = g_configs[instance].dataWidth; - /* in slave mode, the sselNum is not important */ - handle->sselNum = g_configs[instance].sselNum; - handle->txWatermark = (spi_txfifo_watermark_t)SPI_FIFOTRIG_TXLVL_GET(base); - handle->rxWatermark = (spi_rxfifo_watermark_t)SPI_FIFOTRIG_RXLVL_GET(base); - handle->callback = callback; - handle->userData = userData; - - /* Enable SPI NVIC */ - EnableIRQ(s_spiIRQ[instance]); - - return kStatus_Success; -} - -/*! - * brief Transfers a block of data using a polling method. - * - * param base SPI base pointer - * param xfer pointer to spi_xfer_config_t structure - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - */ -status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) -{ - int32_t instance; - uint32_t tx_ctrl = 0, last_ctrl = 0; - uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth; - uint32_t toReceiveCount = 0; - uint8_t *txData, *rxData; - uint32_t fifoDepth; - - /* check params */ - assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); - if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) - { - return kStatus_InvalidArgument; - } - - fifoDepth = SPI_FIFO_DEPTH(base); - txData = xfer->txData; - rxData = xfer->rxData; - txRemainingBytes = txData ? xfer->dataSize : 0; - rxRemainingBytes = rxData ? xfer->dataSize : 0; - - instance = SPI_GetInstance(base); - assert(instance >= 0); - dataWidth = g_configs[instance].dataWidth; - - /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - assert(!((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))); - if ((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)) - { - return kStatus_InvalidArgument; - } - - /* clear tx/rx errors and empty FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - /* select slave to talk with */ - tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum))); - /* set width of data - range asserted at entry */ - tx_ctrl |= SPI_FIFOWR_LEN(dataWidth); - /* delay for frames */ - tx_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; - /* end of transfer */ - last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; - /* last index of loop */ - while (txRemainingBytes || rxRemainingBytes || toReceiveCount) - { - /* if rxFIFO is not empty */ - if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) - { - tmp32 = base->FIFORD; - /* rxBuffer is not empty */ - if (rxRemainingBytes) - { - *(rxData++) = tmp32; - rxRemainingBytes--; - /* read 16 bits at once */ - if (dataWidth > 8) - { - *(rxData++) = tmp32 >> 8; - rxRemainingBytes--; - } - } - /* decrease number of data expected to receive */ - toReceiveCount -= 1; - } - /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (toReceiveCount < fifoDepth) && - ((txRemainingBytes) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1)))) - { - /* txBuffer is not empty */ - if (txRemainingBytes) - { - tmp32 = *(txData++); - txRemainingBytes--; - /* write 16 bit at once */ - if (dataWidth > 8) - { - tmp32 |= ((uint32_t)(*(txData++))) << 8U; - txRemainingBytes--; - } - if (!txRemainingBytes) - { - tx_ctrl |= last_ctrl; - } - } - else - { - tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance])); - /* last transfer */ - if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1)) - { - tx_ctrl |= last_ctrl; - } - } - /* send data */ - tmp32 = tx_ctrl | tmp32; - base->FIFOWR = tmp32; - toReceiveCount += 1; - } - } - /* wait if TX FIFO of previous transfer is not empty */ - while (!(base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) - { - } - return kStatus_Success; -} - -/*! - * brief Performs a non-blocking SPI interrupt transfer. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state - * param xfer pointer to spi_xfer_config_t structure - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer) -{ - /* check params */ - assert( - !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) - { - return kStatus_InvalidArgument; - } - - /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - assert(!((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))); - if ((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)) - { - return kStatus_InvalidArgument; - } - - /* Check if SPI is busy */ - if (handle->state == kStatus_SPI_Busy) - { - return kStatus_SPI_Busy; - } - - /* Set the handle information */ - handle->txData = xfer->txData; - handle->rxData = xfer->rxData; - /* set count */ - handle->txRemainingBytes = xfer->txData ? xfer->dataSize : 0; - handle->rxRemainingBytes = xfer->rxData ? xfer->dataSize : 0; - handle->totalByteCount = xfer->dataSize; - /* other options */ - handle->toReceiveCount = 0; - handle->configFlags = xfer->configFlags; - /* Set the SPI state to busy */ - handle->state = kStatus_SPI_Busy; - /* clear FIFOs when transfer starts */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */ - base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK; - return kStatus_Success; -} - -/*! - * brief Transfers a block of data using a polling method. - * - * This function will do a half-duplex transfer for SPI master, This is a blocking function, - * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, - * users can set transmit first or receive first. - * - * param base SPI base pointer - * param xfer pointer to spi_half_duplex_transfer_t structure - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer) -{ - assert(xfer); - - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the pcs pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - /* SPI transfer blocking. */ - status = SPI_MasterTransferBlocking(base, &tempXfer); - - return status; -} - -/*! - * brief Performs a non-blocking SPI interrupt transfer. - * - * This function using polling way to do the first half transimission and using interrupts to - * do the second half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state - * param xfer pointer to spi_half_duplex_transfer_t structure - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, - spi_master_handle_t *handle, - spi_half_duplex_transfer_t *xfer) -{ - assert(xfer); - assert(handle); - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the PCS pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - status = SPI_MasterTransferNonBlocking(base, handle, &tempXfer); - - return status; -} - -/*! - * brief Gets the master transfer count. - * - * This function gets the master transfer count. - * - * param base SPI peripheral base address. - * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * param count The number of bytes transferred by using the non-blocking transaction. - * return status of status_t. - */ -status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) -{ - assert(NULL != handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kStatus_SPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - *count = handle->totalByteCount - handle->rxRemainingBytes; - return kStatus_Success; -} - -/*! - * brief SPI master aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * param base SPI peripheral base address. - * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupt requests*/ - base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK); - /* Empty FIFOs */ - base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - - handle->state = kStatus_SPI_Idle; - handle->txRemainingBytes = 0; - handle->rxRemainingBytes = 0; -} - -static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle) -{ - uint32_t tx_ctrl = 0, last_ctrl = 0, tmp32; - bool loopContinue; - uint32_t fifoDepth; - /* Get flexcomm instance by 'base' param */ - uint32_t instance = SPI_GetInstance(base); - - /* check params */ - assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData))); - - fifoDepth = SPI_FIFO_DEPTH(base); - /* select slave to talk with */ - tx_ctrl |= (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(handle->sselNum)); - /* set width of data */ - tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth); - /* delay for frames */ - tx_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; - /* end of transfer */ - last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; - do - { - loopContinue = false; - - /* rxFIFO is not empty */ - if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) - { - tmp32 = base->FIFORD; - /* rxBuffer is not empty */ - if (handle->rxRemainingBytes) - { - /* low byte must go first */ - *(handle->rxData++) = tmp32; - handle->rxRemainingBytes--; - /* read 16 bits at once */ - if (handle->dataWidth > kSPI_Data8Bits) - { - *(handle->rxData++) = tmp32 >> 8; - handle->rxRemainingBytes--; - } - } - /* decrease number of data expected to receive */ - handle->toReceiveCount -= 1; - loopContinue = true; - } - - /* - txFIFO is not full - * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO - * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer - */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (handle->toReceiveCount < fifoDepth) && - ((handle->txRemainingBytes) || - (handle->rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1)))) - { - /* txBuffer is not empty */ - if (handle->txRemainingBytes) - { - /* low byte must go first */ - tmp32 = *(handle->txData++); - handle->txRemainingBytes--; - /* write 16 bit at once */ - if (handle->dataWidth > kSPI_Data8Bits) - { - tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U; - handle->txRemainingBytes--; - } - /* last transfer */ - if (!handle->txRemainingBytes) - { - tx_ctrl |= last_ctrl; - } - } - else - { - tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance])); - /* last transfer */ - if (handle->rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1)) - { - tx_ctrl |= last_ctrl; - } - } - /* send data */ - tmp32 = tx_ctrl | tmp32; - base->FIFOWR = tmp32; - /* increase number of expected data to receive */ - handle->toReceiveCount += 1; - loopContinue = true; - } - } while (loopContinue); -} - -/*! - * brief Interrupts the handler for the SPI. - * - * param base SPI peripheral base address. - * param handle pointer to spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) -{ - assert((NULL != base) && (NULL != handle)); - - /* IRQ behaviour: - * - first interrupt is triggered by empty txFIFO. The transfer function - * then tries empty rxFIFO and fill txFIFO interleaved that results to - * strategy to process as many items as possible. - * - the next IRQs can be: - * rxIRQ from nonempty rxFIFO which requires to empty rxFIFO. - * txIRQ from empty txFIFO which requires to refill txFIFO. - * - last interrupt is triggered by empty txFIFO. The last state is - * known by empty rxBuffer and txBuffer. If there is nothing to receive - * or send - both operations have been finished and interrupts can be - * disabled. - */ - - /* Data to send or read or expected to receive */ - if ((handle->txRemainingBytes) || (handle->rxRemainingBytes) || (handle->toReceiveCount)) - { - /* Transmit or receive data */ - SPI_TransferHandleIRQInternal(base, handle); - /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and - * enable txIRQ to confirm when txFIFO becomes empty */ - if ((!handle->txRemainingBytes) && (!handle->rxRemainingBytes) && (!handle->toReceiveCount)) - { - base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK); - base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK; - } - else - { - uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes); - /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data, - * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */ - if ((!handle->txRemainingBytes) && (rxRemainingCount <= handle->toReceiveCount)) - { - base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK; - } - /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel. - * Cannot clear rxFIFO, txFIFO might be still active */ - if (rxRemainingCount == 0) - { - if ((handle->txRemainingBytes == 0) && (handle->toReceiveCount != 0) && - (handle->toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(handle->toReceiveCount - 1); - } - } - /* Expected to receive less data than rxLevel value, we have to update rxLevel */ - else - { - if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1); - } - } - } - } - else - { - /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */ - base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK; - base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) | - SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark); - /* set idle state and call user callback */ - handle->state = kStatus_SPI_Idle; - if (handle->callback) - { - (handle->callback)(base, handle, handle->state, handle->userData); - } - } -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_spi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_spi.h deleted file mode 100644 index de33f50d6c..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_spi.h +++ /dev/null @@ -1,725 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SPI_H_ -#define _FSL_SPI_H_ - -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/*! - * @addtogroup spi_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SPI driver version 2.0.3. */ -#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -/*! @brief Global variable for dummy data value setting. */ -extern volatile uint8_t s_dummyData[]; - -#ifndef SPI_DUMMYDATA -/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */ -#define SPI_DUMMYDATA (0xFFU) -#endif - -#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFF) -#define SPI_CTRLMASK (0xFFFF0000) - -#define SPI_ASSERTNUM_SSEL(n) ((~(1U << ((n) + 16))) & 0xF0000) -#define SPI_DEASSERTNUM_SSEL(n) (1U << ((n) + 16)) -#define SPI_DEASSERT_ALL (0xF0000) - -#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK)) - -#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT) -#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT) - -/*! @brief SPI transfer option.*/ -typedef enum _spi_xfer_option -{ - kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< A delay may be inserted, defined in the DLY register.*/ - kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< SSEL will be deasserted at the end of a transfer */ -} spi_xfer_option_t; - -/*! @brief SPI data shifter direction options.*/ -typedef enum _spi_shift_direction -{ - kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */ - kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */ -} spi_shift_direction_t; - -/*! @brief SPI clock polarity configuration.*/ -typedef enum _spi_clock_polarity -{ - kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */ - kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */ -} spi_clock_polarity_t; - -/*! @brief SPI clock phase configuration.*/ -typedef enum _spi_clock_phase -{ - kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first - * cycle of a data transfer. */ - kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the - * first cycle of a data transfer. */ -} spi_clock_phase_t; - -/*! @brief txFIFO watermark values */ -typedef enum _spi_txfifo_watermark -{ - kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */ - kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */ - kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */ - kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */ - kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */ - kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */ - kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */ - kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */ -} spi_txfifo_watermark_t; - -/*! @brief rxFIFO watermark values */ -typedef enum _spi_rxfifo_watermark -{ - kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */ - kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */ - kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */ - kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */ - kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */ - kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */ - kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */ - kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */ -} spi_rxfifo_watermark_t; - -/*! @brief Transfer data width */ -typedef enum _spi_data_width -{ - kSPI_Data4Bits = 3, /*!< 4 bits data width */ - kSPI_Data5Bits = 4, /*!< 5 bits data width */ - kSPI_Data6Bits = 5, /*!< 6 bits data width */ - kSPI_Data7Bits = 6, /*!< 7 bits data width */ - kSPI_Data8Bits = 7, /*!< 8 bits data width */ - kSPI_Data9Bits = 8, /*!< 9 bits data width */ - kSPI_Data10Bits = 9, /*!< 10 bits data width */ - kSPI_Data11Bits = 10, /*!< 11 bits data width */ - kSPI_Data12Bits = 11, /*!< 12 bits data width */ - kSPI_Data13Bits = 12, /*!< 13 bits data width */ - kSPI_Data14Bits = 13, /*!< 14 bits data width */ - kSPI_Data15Bits = 14, /*!< 15 bits data width */ - kSPI_Data16Bits = 15, /*!< 16 bits data width */ -} spi_data_width_t; - -/*! @brief Slave select */ -typedef enum _spi_ssel -{ - kSPI_Ssel0 = 0, /*!< Slave select 0 */ - kSPI_Ssel1 = 1, /*!< Slave select 1 */ - kSPI_Ssel2 = 2, /*!< Slave select 2 */ - kSPI_Ssel3 = 3, /*!< Slave select 3 */ -} spi_ssel_t; - -/*! @brief ssel polarity */ -typedef enum _spi_spol -{ - kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1), - kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1), - kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1), - kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1), - kSPI_SpolActiveAllHigh = - (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh), - kSPI_SpolActiveAllLow = 0, -} spi_spol_t; - -/*! - * @brief SPI delay time configure structure. - * Note: - * The DLY register controls several programmable delays related to SPI signalling, - * it stands for how many SPI clock time will be inserted. - * The maxinun value of these delay time is 15. - */ -typedef struct _spi_delay_config -{ - uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */ - uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */ - uint8_t frameDelay; /*!< Delay between frame to frame. */ - uint8_t transferDelay; /*!< Delay between transfer to transfer. */ -} spi_delay_config_t; - -/*! @brief SPI master user configure structure.*/ -typedef struct _spi_master_config -{ - bool enableLoopback; /*!< Enable loopback for test purpose */ - bool enableMaster; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_ssel_t sselNum; /*!< Slave select number */ - spi_spol_t sselPol; /*!< Configure active CS polarity */ - spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ - spi_delay_config_t delayConfig; /*!< Delay configuration. */ -} spi_master_config_t; - -/*! @brief SPI slave user configure structure.*/ -typedef struct _spi_slave_config -{ - bool enableSlave; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_spol_t sselPol; /*!< Configure active CS polarity */ - spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ -} spi_slave_config_t; - -/*! @brief SPI transfer status.*/ -enum _spi_status -{ - kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */ - kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */ - kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */ - kStatus_SPI_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_SPI, 3) /*!< Baudrate is not support in current clock source */ -}; - -/*! @brief SPI interrupt sources.*/ -enum _spi_interrupt_enable -{ - kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */ - kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */ -}; - -/*! @brief SPI status flags.*/ -enum _spi_statusflags -{ - kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, /*!< txFifo is empty */ - kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, /*!< txFifo is not full */ - kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */ - kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, /*!< rxFIFO is full */ -}; - -/*! @brief SPI transfer structure */ -typedef struct _spi_transfer -{ - uint8_t *txData; /*!< Send buffer */ - uint8_t *rxData; /*!< Receive buffer */ - uint32_t configFlags; /*!< Additional option to control transfer, @ref spi_xfer_option_t. */ - size_t dataSize; /*!< Transfer bytes */ -} spi_transfer_t; - -/*! @brief SPI half-duplex(master only) transfer structure */ -typedef struct _spi_half_duplex_transfer -{ - uint8_t *txData; /*!< Send buffer */ - uint8_t *rxData; /*!< Receive buffer */ - size_t txDataSize; /*!< Transfer bytes for transmit */ - size_t rxDataSize; /*!< Transfer bytes */ - uint32_t configFlags; /*!< Transfer configuration flags, @ref spi_xfer_option_t. */ - bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for - deassert. */ - bool isTransmitFirst; /*!< True for transmit first and false for receive first. */ -} spi_half_duplex_transfer_t; - -/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */ -typedef struct _spi_config -{ - spi_data_width_t dataWidth; - spi_ssel_t sselNum; -} spi_config_t; - -/*! @brief Master handle type */ -typedef struct _spi_master_handle spi_master_handle_t; - -/*! @brief Slave handle type */ -typedef spi_master_handle_t spi_slave_handle_t; - -/*! @brief SPI master callback for finished transmit */ -typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI slave callback for finished transmit */ -typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI transfer handle structure */ -struct _spi_master_handle -{ - uint8_t *volatile txData; /*!< Transfer buffer */ - uint8_t *volatile rxData; /*!< Receive buffer */ - volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */ - volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */ - volatile size_t toReceiveCount; /*!< Receive data remaining in bytes */ - size_t totalByteCount; /*!< A number of transfer bytes */ - volatile uint32_t state; /*!< SPI internal state */ - spi_master_callback_t callback; /*!< SPI callback */ - void *userData; /*!< Callback parameter */ - uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */ - uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */ - uint32_t configFlags; /*!< Additional option to control transfer */ - spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ -}; - -#if defined(__cplusplus) -extern "C" { -#endif -/******************************************************************************* - * API - ******************************************************************************/ - -/*! @brief Returns instance number for SPI peripheral base address. */ -uint32_t SPI_GetInstance(SPI_Type *base); - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Sets the SPI master configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). - * User may use the initialized structure unchanged in SPI_MasterInit(), or modify - * some fields of the structure before calling SPI_MasterInit(). After calling this API, - * the master is ready to transfer. - * Example: - @code - spi_master_config_t config; - SPI_MasterGetDefaultConfig(&config); - @endcode - * - * @param config pointer to master config structure - */ -void SPI_MasterGetDefaultConfig(spi_master_config_t *config); - -/*! - * @brief Initializes the SPI with master configuration. - * - * The configuration structure can be filled by user from scratch, or be set with default - * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. - * Example - @code - spi_master_config_t config = { - .baudRate_Bps = 400000, - ... - }; - SPI_MasterInit(SPI0, &config); - @endcode - * - * @param base SPI base pointer - * @param config pointer to master configuration structure - * @param srcClock_Hz Source clock frequency. - */ -status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Sets the SPI slave configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). - * Modify some fields of the structure before calling SPI_SlaveInit(). - * Example: - @code - spi_slave_config_t config; - SPI_SlaveGetDefaultConfig(&config); - @endcode - * - * @param config pointer to slave configuration structure - */ -void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config); - -/*! - * @brief Initializes the SPI with slave configuration. - * - * The configuration structure can be filled by user from scratch or be set with - * default values by SPI_SlaveGetDefaultConfig(). - * After calling this API, the slave is ready to transfer. - * Example - @code - spi_slave_config_t config = { - .polarity = flexSPIClockPolarity_ActiveHigh; - .phase = flexSPIClockPhase_FirstEdge; - .direction = flexSPIMsbFirst; - ... - }; - SPI_SlaveInit(SPI0, &config); - @endcode - * - * @param base SPI base pointer - * @param config pointer to slave configuration structure - */ -status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config); - -/*! - * @brief De-initializes the SPI. - * - * Calling this API resets the SPI module, gates the SPI clock. - * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. - * - * @param base SPI base pointer - */ -void SPI_Deinit(SPI_Type *base); - -/*! - * @brief Enable or disable the SPI Master or Slave - * @param base SPI base pointer - * @param enable or disable ( true = enable, false = disable) - */ -static inline void SPI_Enable(SPI_Type *base, bool enable) -{ - if (enable) - { - base->CFG |= SPI_CFG_ENABLE_MASK; - } - else - { - base->CFG &= ~SPI_CFG_ENABLE_MASK; - } -} - -/*! @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the status flag. - * - * @param base SPI base pointer - * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status. - */ -static inline uint32_t SPI_GetStatusFlags(SPI_Type *base) -{ - assert(NULL != base); - return base->FIFOSTAT; -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the interrupt for the SPI. - * - * @param base SPI base pointer - * @param irqs SPI interrupt source. The parameter can be any combination of the following values: - * @arg kSPI_RxLvlIrq - * @arg kSPI_TxLvlIrq - */ -static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs) -{ - assert(NULL != base); - base->FIFOINTENSET = irqs; -} - -/*! - * @brief Disables the interrupt for the SPI. - * - * @param base SPI base pointer - * @param irqs SPI interrupt source. The parameter can be any combination of the following values: - * @arg kSPI_RxLvlIrq - * @arg kSPI_TxLvlIrq - */ -static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs) -{ - assert(NULL != base); - base->FIFOINTENCLR = irqs; -} - -/*! @} */ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables the DMA request from SPI txFIFO. - * - * @param base SPI base pointer - * @param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableTxDMA(SPI_Type *base, bool enable); - -/*! - * @brief Enables the DMA request from SPI rxFIFO. - * - * @param base SPI base pointer - * @param enable True means enable DMA, false means disable DMA - */ -void SPI_EnableRxDMA(SPI_Type *base, bool enable); - -/*! @} */ - -/*! - * @name Bus Operations - * @{ - */ -/*! - * @brief Returns the configurations. - * - * @param base SPI peripheral address. - * @return return configurations which contain datawidth and SSEL numbers. - * return data type is a pointer of spi_config_t. - */ -void *SPI_GetConfig(SPI_Type *base); - -/*! - * @brief Sets the baud rate for SPI transfer. This is only used in master. - * - * @param base SPI base pointer - * @param baudrate_Bps baud rate needed in Hz. - * @param srcClock_Hz SPI source clock frequency in Hz. - */ -status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Writes a data into the SPI data register. - * - * @param base SPI base pointer - * @param data needs to be write. - * @param configFlags transfer configuration options @ref spi_xfer_option_t - */ -void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags); - -/*! - * @brief Gets a data from the SPI data register. - * - * @param base SPI base pointer - * @return Data in the register. - */ -static inline uint32_t SPI_ReadData(SPI_Type *base) -{ - assert(NULL != base); - return base->FIFORD; -} - -/*! - * @brief Set delay time for transfer. - * the delay uint is SPI clock time, maximum value is 0xF. - * @param base SPI base pointer - * @param config configuration for delay option @ref spi_delay_config_t. - */ -static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config) -{ - assert(NULL != base); - assert(NULL != config); - base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) | - SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay)); -} - -/*! - * @brief Set up the dummy data. - * - * @param base SPI peripheral address. - * @param dummyData Data to be transferred when tx buffer is NULL. - */ -void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData); - -/*! @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the SPI master handle. - * - * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -status_t SPI_MasterTransferCreateHandle(SPI_Type *base, - spi_master_handle_t *handle, - spi_master_callback_t callback, - void *userData); - -/*! - * @brief Transfers a block of data using a polling method. - * - * @param base SPI base pointer - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - */ -status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SPI interrupt transfer. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer); - -/*! - * @brief Transfers a block of data using a polling method. - * - * This function will do a half-duplex transfer for SPI master, This is a blocking function, - * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, - * users can set transmit first or receive first. - * - * @param base SPI base pointer - * @param xfer pointer to spi_half_duplex_transfer_t structure - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SPI interrupt transfer. - * - * This function using polling way to do the first half transimission and using interrupts to - * do the second half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_half_duplex_transfer_t structure - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, - spi_master_handle_t *handle, - spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Gets the master transfer count. - * - * This function gets the master transfer count. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count); - -/*! - * @brief SPI master aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle); - -/*! - * @brief Interrupts the handler for the SPI. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state. - */ -void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle); - -/*! - * @brief Initializes the SPI slave handle. - * - * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually, - * for a specified SPI instance, call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base, - spi_slave_handle_t *handle, - spi_slave_callback_t callback, - void *userData) -{ - return SPI_MasterTransferCreateHandle(base, handle, callback, userData); -} - -/*! - * @brief Performs a non-blocking SPI slave interrupt transfer. - * - * @note The API returns immediately after the transfer initialization is finished. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_master_handle_t structure which stores the transfer state - * @param xfer pointer to spi_xfer_config_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer) -{ - return SPI_MasterTransferNonBlocking(base, handle, xfer); -} - -/*! - * @brief Gets the slave transfer count. - * - * This function gets the slave transfer count. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count) -{ - return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count); -} - -/*! - * @brief SPI slave aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base SPI peripheral base address. - * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state. - */ -static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle) -{ - SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle); -} - -/*! - * @brief Interrupts a handler for the SPI slave. - * - * @param base SPI peripheral base address. - * @param handle pointer to spi_slave_handle_t structure which stores the transfer state - */ -static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle) -{ - SPI_MasterTransferHandleIRQ(base, handle); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_SPI_H_*/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_spi_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_spi_dma.c deleted file mode 100644 index 3e725909c0..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_spi_dma.c +++ /dev/null @@ -1,554 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_spi_dma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_dma" -#endif - -/*configFlags & (uint32_t)kSPI_FrameDelay ? (uint32_t)kSPI_FrameDelay : 0; - *fifowr |= xfer->configFlags & (uint32_t)kSPI_FrameAssert ? (uint32_t)kSPI_FrameAssert : 0; -} - -static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr) -{ - *fifowr |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(config->sselNum))); - /* set width of data - range asserted at entry */ - *fifowr |= SPI_FIFOWR_LEN(config->dataWidth); -} - -static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_config_t *config) -{ - if (config->dataWidth > kSPI_Data8Bits) - { - *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1] << 8U) | (xfer->txData[xfer->dataSize - 2])); - } - else - { - *txLastWord = xfer->txData[xfer->dataSize - 1]; - } - XferToFifoWR(xfer, txLastWord); - SpiConfigToFifoWR(config, txLastWord); -} - -static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) -{ - uint32_t instance = SPI_GetInstance(base); - dummy->word = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]); - dummy->lastWord = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]); - XferToFifoWR(xfer, &dummy->word); - XferToFifoWR(xfer, &dummy->lastWord); - SpiConfigToFifoWR(spi_config_p, &dummy->word); - SpiConfigToFifoWR(spi_config_p, &dummy->lastWord); - /* Clear the end of transfer bit for continue word transfer. */ - dummy->word &= (uint32_t)(~kSPI_FrameAssert); -} - -/*! - * brief Initialize the SPI master DMA handle. - * - * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * param base SPI peripheral base address. - * param handle SPI handle pointer. - * param callback User callback function called at the end of a transfer. - * param userData User data for callback. - * param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle) -{ - int32_t instance = 0; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - instance = SPI_GetInstance(base); - - memset(handle, 0, sizeof(*handle)); - /* Set spi base to handle */ - handle->txHandle = txHandle; - handle->rxHandle = rxHandle; - handle->callback = callback; - handle->userData = userData; - - /* Set SPI state to idle */ - handle->state = kSPI_Idle; - - /* Set handle to global state */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - /* Install callback for Tx dma channel */ - DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]); - DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]); - - return kStatus_Success; -} - -/*! - * brief Perform a non-blocking SPI transfer using DMA. - * - * note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * param base SPI peripheral base address. - * param handle SPI DMA handle pointer. - * param xfer Pointer to dma transfer structure. - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) -{ - int32_t instance; - status_t result = kStatus_Success; - spi_config_t *spi_config_p; - - assert(!((NULL == handle) || (NULL == xfer))); - if ((NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - - /* Byte size is zero. */ - assert(!(xfer->dataSize == 0)); - if (xfer->dataSize == 0) - { - return kStatus_InvalidArgument; - } - /* cannot get instance from base address */ - instance = SPI_GetInstance(base); - assert(!(instance < 0)); - if (instance < 0) - { - return kStatus_InvalidArgument; - } - - /* Check if the device is busy */ - if (handle->state == kSPI_Busy) - { - return kStatus_SPI_Busy; - } - else - { - uint32_t tmp; - dma_transfer_config_t xferConfig = {0}; - spi_config_p = (spi_config_t *)SPI_GetConfig(base); - - handle->state = kStatus_SPI_Busy; - handle->transferSize = xfer->dataSize; - - /* receive */ - SPI_EnableRxDMA(base, true); - if (xfer->rxData) - { - DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), xfer->rxData, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_PeripheralToMemory, NULL); - } - else - { - DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), &s_rxDummy, - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_StaticToStatic, NULL); - } - DMA_SubmitTransfer(handle->rxHandle, &xferConfig); - handle->rxInProgress = true; - DMA_StartTransfer(handle->rxHandle); - - /* transmit */ - SPI_EnableTxDMA(base, true); - - if (xfer->txData) - { - if (xfer->configFlags & kSPI_FrameAssert) - { - PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p); - } - /* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma - * descriptor to send the last data. - */ - if ((xfer->configFlags & kSPI_FrameAssert) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1))) - { - dma_xfercfg_t tmp_xfercfg = {0}; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = sizeof(uint32_t); - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; - tmp_xfercfg.transferCount = 1; - /* Create chained descriptor to transmit last word */ - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance], - ((void *)((uint32_t)&base->FIFOWR)), NULL); - - DMA_PrepareTransfer( - &xferConfig, xfer->txData, ((void *)((uint32_t)&base->FIFOWR)), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)), - kDMA_MemoryToPeripheral, &s_spi_descriptor_table[instance]); - /* Disable interrupts for first descriptor to avoid calling callback twice. */ - xferConfig.xfercfg.intA = false; - xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - else - { - DMA_PrepareTransfer( - &xferConfig, xfer->txData, ((void *)((uint32_t)&base->FIFOWR)), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_MemoryToPeripheral, NULL); - DMA_SubmitTransfer(handle->txHandle, &xferConfig); - } - } - else - { - /* Setup tx dummy data. */ - SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p); - if ((xfer->configFlags & kSPI_FrameAssert) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1))) - { - dma_xfercfg_t tmp_xfercfg = {0}; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = sizeof(uint32_t); - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; - tmp_xfercfg.transferCount = 1; - /* Create chained descriptor to transmit last word */ - DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, - (void *)((uint32_t)&base->FIFOWR), NULL); - /* Use common API to setup first descriptor */ - DMA_PrepareTransfer( - &xferConfig, &s_txDummy[instance].word, ((void *)((uint32_t)&base->FIFOWR)), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)), - kDMA_StaticToStatic, &s_spi_descriptor_table[instance]); - /* Disable interrupts for first descriptor to avoid calling callback twice */ - xferConfig.xfercfg.intA = false; - xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - else - { - DMA_PrepareTransfer( - &xferConfig, &s_txDummy[instance].word, ((void *)((uint32_t)&base->FIFOWR)), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - xfer->dataSize, kDMA_StaticToStatic, NULL); - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); - if (result != kStatus_Success) - { - return result; - } - } - } - - handle->txInProgress = true; - tmp = 0; - XferToFifoWR(xfer, &tmp); - SpiConfigToFifoWR(spi_config_p, &tmp); - - /* Setup the control info. - * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO. - * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR - * will push the data and the current control bits into the FIFO. - */ - if ((xfer->configFlags & kSPI_FrameAssert) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize == 2U) : (xfer->dataSize == 1U))) - { - *(((uint16_t *)((uint32_t) & (base->FIFOWR))) + 1) = (uint16_t)(tmp >> 16U); - } - else - { - /* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */ - tmp &= (uint32_t)(~kSPI_FrameAssert); - *(((uint16_t *)((uint32_t) & (base->FIFOWR))) + 1) = (uint16_t)(tmp >> 16U); - } - - DMA_StartTransfer(handle->txHandle); - } - - return result; -} - -/*! - * brief Transfers a block of data using a DMA method. - * - * This function using polling way to do the first half transimission and using DMA way to - * do the srcond half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * param base SPI base pointer - * param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. - * param transfer A pointer to the spi_half_duplex_transfer_t structure. - * return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer) -{ - assert(xfer); - assert(handle); - spi_transfer_t tempXfer = {0}; - status_t status; - - if (xfer->isTransmitFirst) - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - else - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - /* If the pcs pin keep assert between transmit and receive. */ - if (xfer->isPcsAssertInTransfer) - { - tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); - } - else - { - tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; - } - - status = SPI_MasterTransferBlocking(base, &tempXfer); - if (status != kStatus_Success) - { - return status; - } - - if (xfer->isTransmitFirst) - { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; - tempXfer.dataSize = xfer->rxDataSize; - } - else - { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; - tempXfer.dataSize = xfer->txDataSize; - } - tempXfer.configFlags = xfer->configFlags; - - status = SPI_MasterTransferDMA(base, handle, &tempXfer); - - return status; -} - -static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - - /* change the state */ - spiHandle->rxInProgress = false; - - /* All finished, call the callback */ - if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) - { - spiHandle->state = kSPI_Idle; - if (spiHandle->callback) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } -} - -static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) -{ - spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; - - /* change the state */ - spiHandle->txInProgress = false; - - /* All finished, call the callback */ - if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) - { - spiHandle->state = kSPI_Idle; - if (spiHandle->callback) - { - (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); - } - } -} - -/*! - * brief Abort a SPI transfer using DMA. - * - * param base SPI peripheral base address. - * param handle SPI DMA handle pointer. - */ -void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) -{ - assert(NULL != handle); - - /* Stop tx transfer first */ - DMA_AbortTransfer(handle->txHandle); - /* Then rx transfer */ - DMA_AbortTransfer(handle->rxHandle); - - /* Set the handle state */ - handle->txInProgress = false; - handle->rxInProgress = false; - handle->state = kSPI_Idle; -} - -/*! - * brief Gets the master DMA transfer remaining bytes. - * - * This function gets the master DMA transfer remaining bytes. - * - * param base SPI peripheral base address. - * param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * param count A number of bytes transferred by the non-blocking transaction. - * return status of status_t. - */ -status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t bytes; - - bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel); - - *count = handle->transferSize - bytes; - - return kStatus_Success; -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_spi_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_spi_dma.h deleted file mode 100644 index 801d4f8f5a..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_spi_dma.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SPI_DMA_H_ -#define _FSL_SPI_DMA_H_ - -#include "fsl_dma.h" -#include "fsl_spi.h" - -/*! - * @addtogroup spi_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SPI DMA driver version 2.0.2. */ -#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -typedef struct _spi_dma_handle spi_dma_handle_t; - -/*! @brief SPI DMA callback called at the end of transfer. */ -typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData); - -/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/ -struct _spi_dma_handle -{ - volatile bool txInProgress; /*!< Send transfer finished */ - volatile bool rxInProgress; /*!< Receive transfer finished */ - dma_handle_t *txHandle; /*!< DMA handler for SPI send */ - dma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ - uint8_t bytesPerFrame; /*!< Bytes in a frame for SPI tranfer */ - spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */ - void *userData; /*!< User Data for SPI DMA callback */ - uint32_t state; /*!< Internal state of SPI DMA transfer */ - size_t transferSize; /*!< Bytes need to be transfer */ -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name DMA Transactional - * @{ - */ - -/*! - * @brief Initialize the SPI master DMA handle. - * - * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback User callback function called at the end of a transfer. - * @param userData User data for callback. - * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle); - -/*! - * @brief Perform a non-blocking SPI transfer using DMA. - * - * @note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - * @param xfer Pointer to dma transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer); - -/*! - * @brief Transfers a block of data using a DMA method. - * - * This function using polling way to do the first half transimission and using DMA way to - * do the srcond half transimission, the transfer mechanism is half-duplex. - * When do the second half transimission, code will return right away. When all data is transferred, - * the callback function is called. - * - * @param base SPI base pointer - * @param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. - * @param transfer A pointer to the spi_half_duplex_transfer_t structure. - * @return status of status_t. - */ -status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer); - -/*! - * @brief Initialize the SPI slave DMA handle. - * - * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs. - * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. - * - * @param base SPI peripheral base address. - * @param handle SPI handle pointer. - * @param callback User callback function called at the end of a transfer. - * @param userData User data for callback. - * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. - * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. - */ -static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base, - spi_dma_handle_t *handle, - spi_dma_callback_t callback, - void *userData, - dma_handle_t *txHandle, - dma_handle_t *rxHandle) -{ - return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle); -} - -/*! - * @brief Perform a non-blocking SPI transfer using DMA. - * - * @note This interface returned immediately after transfer initiates, users should call - * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - * @param xfer Pointer to dma transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. - */ -static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) -{ - return SPI_MasterTransferDMA(base, handle, xfer); -} - -/*! - * @brief Abort a SPI transfer using DMA. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - */ -void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle); - -/*! - * @brief Gets the master DMA transfer remaining bytes. - * - * This function gets the master DMA transfer remaining bytes. - * - * @param base SPI peripheral base address. - * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * @param count A number of bytes transferred by the non-blocking transaction. - * @return status of status_t. - */ -status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count); - -/*! - * @brief Abort a SPI transfer using DMA. - * - * @param base SPI peripheral base address. - * @param handle SPI DMA handle pointer. - */ -static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) -{ - SPI_MasterTransferAbortDMA(base, handle); -} - -/*! - * @brief Gets the slave DMA transfer remaining bytes. - * - * This function gets the slave DMA transfer remaining bytes. - * - * @param base SPI peripheral base address. - * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. - * @param count A number of bytes transferred by the non-blocking transaction. - * @return status of status_t. - */ -static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) -{ - return SPI_MasterTransferGetCountDMA(base, handle, count); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_SPI_DMA_H_*/ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sysctl.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sysctl.c deleted file mode 100644 index fb9730b829..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sysctl.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) 2018, NXP Semiconductors, Inc. - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sysctl.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sysctl" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the instance. - * - * @param base SYSCTL peripheral base address. - * @return Instance number. - */ -static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base); - -/*! - * @brief Enable SYSCTL write protect - * - * @param base SYSCTL peripheral base address. - * @param regAddr register address - * @param value value to write. - */ -static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief SYSCTL base address array name */ -static SYSCTL_Type *const s_sysctlBase[] = SYSCTL_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief SYSCTL clock array name */ -static const clock_ip_name_t s_sysctlClock[] = SYSCTL_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value) -{ - base->UPDATELCKOUT &= ~SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; - *regAddr = value; - base->UPDATELCKOUT |= SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; -} - -static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base) -{ - uint8_t instance = 0; - - while ((instance < ARRAY_SIZE(s_sysctlBase)) && (s_sysctlBase[instance] != base)) - { - instance++; - } - - assert(instance < ARRAY_SIZE(s_sysctlBase)); - - return instance; -} - -/*! - * @brief SYSCTL initial - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Init(SYSCTL_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable SYSCTL clock. */ - CLOCK_EnableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); -#endif -} - -/*! - * @brief SYSCTL deinit - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Deinit(SYSCTL_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable SYSCTL clock. */ - CLOCK_DisableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); -#endif -} - -/*! - * @brief SYSCTL share set configure for separate signal - * - * @param base Base address of the SYSCTL peripheral - * @param flexCommIndex index of flexcomm,reference _sysctl_share_src - * @param setIndex share set for sck, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set) -{ - uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; - - tempReg &= ~(SYSCTL_FCCTRLSEL_SCKINSEL_MASK << signal); - tempReg |= (set + 1U) << signal; - - SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); -} - -/*! - * @brief SYSCTL share set configure for flexcomm - * - * @param base Base address of the SYSCTL peripheral. - * @param flexCommIndex index of flexcomm, reference _sysctl_share_src - * @param sckSet share set for sck,reference _sysctl_share_set_index - * @param wsSet share set for ws, reference _sysctl_share_set_index - * @param dataInSet share set for data in, reference _sysctl_share_set_index - * @param dataOutSet share set for data out, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetFlexcommShareSet( - SYSCTL_Type *base, uint32_t flexCommIndex, uint32_t sckSet, uint32_t wsSet, uint32_t dataInSet, uint32_t dataOutSet) -{ - uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; - - tempReg &= ~(SYSCTL_FCCTRLSEL_SCKINSEL_MASK | SYSCTL_FCCTRLSEL_WSINSEL_MASK | SYSCTL_FCCTRLSEL_DATAINSEL_MASK | - SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK); - tempReg |= SYSCTL_FCCTRLSEL_SCKINSEL(sckSet + 1U) | SYSCTL_FCCTRLSEL_WSINSEL(wsSet + 1U) | - SYSCTL_FCCTRLSEL_DATAINSEL(dataInSet + 1U) | SYSCTL_FCCTRLSEL_DATAOUTSEL(dataOutSet + 1U); - - SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); -} - -/*! - * @brief SYSCTL share set source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source for this share set,reference _sysctl_share_src - * @param wsShareSrc ws source for this share set,reference _sysctl_share_src - * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src - * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask - * - */ -void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, - uint32_t setIndex, - uint32_t sckShareSrc, - uint32_t wsShareSrc, - uint32_t dataInShareSrc, - uint32_t dataOutMask) -{ - uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; - - /* WS,SCK,DATA IN */ - tempReg &= - ~(SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK | SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK | - SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK); - tempReg |= SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL(sckShareSrc) | - SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL(wsShareSrc) | - SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL(dataInShareSrc); - - /* data out */ - tempReg &= - ~(SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK | SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK | - SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK | SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK | - SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK); - tempReg |= dataOutMask; - - SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); -} - -/*! - * @brief SYSCTL sck source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source fro this share set,reference _sysctl_share_src - * - */ -void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, - uint32_t setIndex, - sysctl_sharedctrlset_signal_t signal, - uint32_t shareSrc) -{ - uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; - - if (signal == kSYSCTL_SharedCtrlSignalDataOut) - { - tempReg |= 1 << (signal + shareSrc); - } - else - { - tempReg &= ~(SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK << signal); - tempReg |= shareSrc << signal; - } - - SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sysctl.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sysctl.h deleted file mode 100644 index f363cfc80e..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_sysctl.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright (c) 2018, NXP Semiconductors, Inc. - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_SYSCTL_H_ -#define _FSL_SYSCTL_H_ - -#include "fsl_common.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup sysctl - * @{ - */ - -/*! @file */ -/*! @file fsl_sysctl.h */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Group sysctl driver version for SDK */ -#define FSL_SYSCTL_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ -/*@}*/ - -/*! @brief SYSCTL share set*/ -enum _sysctl_share_set_index -{ - kSYSCTL_ShareSet0 = 0, /*!< share set 0 */ - kSYSCTL_ShareSet1 = 1, /*!< share set 1 */ -}; - -/*! @brief SYSCTL flexcomm signal */ -typedef enum _sysctl_fcctrlsel_signal -{ - kSYSCTL_FlexcommSignalSCK = SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT, /*!< SCK signal */ - kSYSCTL_FlexcommSignalWS = SYSCTL_FCCTRLSEL_WSINSEL_SHIFT, /*!< WS signal */ - kSYSCTL_FlexcommSignalDataIn = SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT, /*!< Data in signal */ - kSYSCTL_FlexcommSignalDataOut = SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT, /*!< Data out signal */ -} sysctl_fcctrlsel_signal_t; - -/*! @brief SYSCTL flexcomm index*/ -enum _sysctl_share_src -{ - kSYSCTL_Flexcomm0 = 0, /*!< share set 0 */ - kSYSCTL_Flexcomm1 = 1, /*!< share set 1 */ - kSYSCTL_Flexcomm2 = 2, /*!< share set 2 */ - kSYSCTL_Flexcomm4 = 4, /*!< share set 4 */ - kSYSCTL_Flexcomm5 = 5, /*!< share set 5 */ - kSYSCTL_Flexcomm6 = 6, /*!< share set 6 */ - kSYSCTL_Flexcomm7 = 7, /*!< share set 7 */ -}; - -/*! @brief SYSCTL shared data out mask */ -enum _sysctl_dataout_mask -{ - kSYSCTL_Flexcomm0DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK, /*!< share set 0 */ - kSYSCTL_Flexcomm1DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK, /*!< share set 1 */ - kSYSCTL_Flexcomm2DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK, /*!< share set 2 */ - kSYSCTL_Flexcomm3DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_MASK, /*!< share set 3 */ - kSYSCTL_Flexcomm4DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK, /*!< share set 4 */ - kSYSCTL_Flexcomm5DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK, /*!< share set 5 */ - kSYSCTL_Flexcomm6DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK, /*!< share set 6 */ - kSYSCTL_Flexcomm7DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK, /*!< share set 7 */ -}; - -/*! @brief SYSCTL flexcomm signal */ -typedef enum _sysctl_sharedctrlset_signal -{ - kSYSCTL_SharedCtrlSignalSCK = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT, /*!< SCK signal */ - kSYSCTL_SharedCtrlSignalWS = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT, /*!< WS signal */ - kSYSCTL_SharedCtrlSignalDataIn = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT, /*!< Data in signal */ - kSYSCTL_SharedCtrlSignalDataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT, /*!< Data out signal */ -} sysctl_sharedctrlset_signal_t; -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief SYSCTL initial - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Init(SYSCTL_Type *base); - -/*! - * @brief SYSCTL deinit - * - * @param base Base address of the SYSCTL peripheral. - */ -void SYSCTL_Deinit(SYSCTL_Type *base); - -/* @} */ - -/*! - * @name SYSCTL share signal configure - * @{ - */ - -/*! - * @brief SYSCTL share set configure for flexcomm - * - * @param base Base address of the SYSCTL peripheral. - * @param flexCommIndex index of flexcomm, reference _sysctl_share_src - * @param sckSet share set for sck,reference _sysctl_share_set_index - * @param wsSet share set for ws, reference _sysctl_share_set_index - * @param dataInSet share set for data in, reference _sysctl_share_set_index - * @param dataOutSet share set for data out, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetFlexcommShareSet(SYSCTL_Type *base, - uint32_t flexCommIndex, - uint32_t sckSet, - uint32_t wsSet, - uint32_t dataInSet, - uint32_t dataOutSet); - -/*! - * @brief SYSCTL share set configure for separate signal - * - * @param base Base address of the SYSCTL peripheral - * @param flexCommIndex index of flexcomm,reference _sysctl_share_src - * @param signal FCCTRLSEL signal shift - * @param setIndex share set for sck, reference _sysctl_share_set_index - * - */ -void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set); - -/*! - * @brief SYSCTL share set source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source fro this share set,reference _sysctl_share_src - * @param wsShareSrc ws source fro this share set,reference _sysctl_share_src - * @param dataInShareSrc data in source fro this share set,reference _sysctl_share_src - * @param dataOutShareSrc data out source fro this share set,reference _sysctl_share_src - * - */ -void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, - uint32_t setIndex, - uint32_t sckShareSrc, - uint32_t wsShareSrc, - uint32_t dataInShareSrc, - uint32_t dataOutShareSrc); - -/*! - * @brief SYSCTL sck source configure - * - * @param base Base address of the SYSCTL peripheral - * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source fro this share set,reference _sysctl_share_src - * - */ -void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, - uint32_t setIndex, - sysctl_sharedctrlset_signal_t signal, - uint32_t shareSrc); - -/* @} */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_SYSCTL_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_usart.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_usart.c deleted file mode 100644 index 873876604a..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_usart.c +++ /dev/null @@ -1,918 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_flexcomm.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" -#endif - -enum _usart_transfer_states -{ - kUSART_TxIdle, /* TX idle. */ - kUSART_TxBusy, /* TX busy. */ - kUSART_RxIdle, /* RX idle. */ - kUSART_RxBusy /* RX busy. */ -}; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief IRQ name array */ -static const IRQn_Type s_usartIRQ[] = USART_IRQS; - -/*! @brief Array to map USART instance number to base address. */ -static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the USART */ -/*! brief Returns instance number for USART peripheral base address. */ -uint32_t USART_GetInstance(USART_Type *base) -{ - int i; - - for (i = 0; i < FSL_FEATURE_SOC_USART_COUNT; i++) - { - if ((uint32_t)base == s_usartBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0; -} - -/*! - * brief Get the length of received data in RX ring buffer. - * - * param handle USART handle pointer. - * return Length of received data in RX ring buffer. - */ -size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) -{ - size_t size; - - /* Check arguments */ - assert(NULL != handle); - - if (handle->rxRingBufferTail > handle->rxRingBufferHead) - { - size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); - } - else - { - size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); - } - return size; -} - -static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) -{ - bool full; - - /* Check arguments */ - assert(NULL != handle); - - if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) - { - full = true; - } - else - { - full = false; - } - return full; -} - -/*! - * brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific USART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * param ringBufferSize size of the ring buffer. - */ -void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - assert(NULL != ringBuffer); - - /* Setup the ringbuffer address */ - handle->rxRingBuffer = ringBuffer; - handle->rxRingBufferSize = ringBufferSize; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; - /* ring buffer is ready we can start receiving data */ - base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -} - -/*! - * brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - - if (handle->rxState == kUSART_RxIdle) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; - } - handle->rxRingBuffer = NULL; - handle->rxRingBufferSize = 0U; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; -} - -/*! - * brief Initializes a USART instance with user configuration structure and peripheral clock. - * - * This function configures the USART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the USART_GetDefaultConfig() function. - * Example below shows how to use this API to configure USART. - * code - * usart_config_t usartConfig; - * usartConfig.baudRate_Bps = 115200U; - * usartConfig.parityMode = kUSART_ParityDisabled; - * usartConfig.stopBitCount = kUSART_OneStopBit; - * USART_Init(USART1, &usartConfig, 20000000U); - * endcode - * - * param base USART peripheral base address. - * param config Pointer to user-defined configuration structure. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_InvalidArgument USART base address is not valid - * retval kStatus_Success Status USART initialize succeed - */ -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) -{ - int result; - - /* check arguments */ - assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to USART mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); - if (kStatus_Success != result) - { - return result; - } - - /* setup baudrate */ - result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - - if (config->enableTx) - { - /* empty and enable txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; - } - - /* empty and enable rxFIFO */ - if (config->enableRx) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; - } - /* setup configuration and enable USART */ - base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | - USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | USART_CFG_ENABLE_MASK; - return kStatus_Success; -} - -/*! - * brief Deinitializes a USART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the USART clock. - * - * param base USART peripheral base address. - */ -void USART_Deinit(USART_Type *base) -{ - /* Check arguments */ - assert(NULL != base); - while (!(base->STAT & USART_STAT_TXIDLE_MASK)) - { - } - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | - USART_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); - base->CFG &= ~(USART_CFG_ENABLE_MASK); -} - -/*! - * brief Gets the default configuration structure. - * - * This function initializes the USART configuration structure to a default value. The default - * values are: - * usartConfig->baudRate_Bps = 115200U; - * usartConfig->parityMode = kUSART_ParityDisabled; - * usartConfig->stopBitCount = kUSART_OneStopBit; - * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; - * usartConfig->loopback = false; - * usartConfig->enableTx = false; - * usartConfig->enableRx = false; - * - * param config Pointer to configuration structure. - */ -void USART_GetDefaultConfig(usart_config_t *config) -{ - /* Check arguments */ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - - /* Set always all members ! */ - config->baudRate_Bps = 115200U; - config->parityMode = kUSART_ParityDisabled; - config->stopBitCount = kUSART_OneStopBit; - config->bitCountPerChar = kUSART_8BitsPerChar; - config->loopback = false; - config->enableRx = false; - config->enableTx = false; - config->txWatermark = kUSART_TxFifo0; - config->rxWatermark = kUSART_RxFifo1; -} - -/*! - * brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. This function is used to update - * the USART module baud rate after the USART module is initialized by the USART_Init. - * code - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * endcode - * - * param base USART peripheral base address. - * param baudrate_Bps USART baudrate to be set. - * param srcClock_Hz USART clock source freqency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_Success Set baudrate succeed. - * retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; - uint32_t osrval, brgval, diff, baudrate; - - /* check arguments */ - assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))); - if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* - * Smaller values of OSR can make the sampling position within a data bit less accurate and may - * potentially cause more noise errors or incorrect data. - */ - for (osrval = best_osrval; osrval >= 8; osrval--) - { - brgval = (srcClock_Hz / ((osrval + 1) * baudrate_Bps)) - 1; - if (brgval > 0xFFFF) - { - continue; - } - baudrate = srcClock_Hz / ((osrval + 1) * (brgval + 1)); - diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate; - if (diff < best_diff) - { - best_diff = diff; - best_osrval = osrval; - best_brgval = brgval; - } - } - - /* value over range */ - if (best_brgval > 0xFFFF) - { - return kStatus_USART_BaudrateNotSupport; - } - - base->OSR = best_osrval; - base->BRG = best_brgval; - return kStatus_Success; -} - -/*! - * brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * param base USART peripheral base address. - * param data Start address of the data to write. - * param length Size of the data to write. - */ -void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == data))); - if ((NULL == base) || (NULL == data)) - { - return; - } - /* Check whether txFIFO is enabled */ - if (!(base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) - { - return; - } - for (; length > 0; length--) - { - /* Loop until txFIFO get some space for new data */ - while (!(base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) - { - } - base->FIFOWR = *data; - data++; - } - /* Wait to finish transfer */ - while (!(base->STAT & USART_STAT_TXIDLE_MASK)) - { - } -} - -/*! - * brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * param base USART peripheral base address. - * param data Start address of the buffer to store the received data. - * param length Size of the buffer. - * retval kStatus_USART_FramingError Receiver overrun happened while receiving data. - * retval kStatus_USART_ParityError Noise error happened while receiving data. - * retval kStatus_USART_NoiseError Framing error happened while receiving data. - * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. - * retval kStatus_Success Successfully received all data. - */ -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) -{ - uint32_t status; - - /* check arguments */ - assert(!((NULL == base) || (NULL == data))); - if ((NULL == base) || (NULL == data)) - { - return kStatus_InvalidArgument; - } - - /* Check whether rxFIFO is enabled */ - if (!(base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK)) - { - return kStatus_Fail; - } - for (; length > 0; length--) - { - /* loop until rxFIFO have some data to read */ - while (!(base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) - { - } - /* check receive status */ - status = base->STAT; - if (status & USART_STAT_FRAMERRINT_MASK) - { - base->STAT |= USART_STAT_FRAMERRINT_MASK; - return kStatus_USART_FramingError; - } - if (status & USART_STAT_PARITYERRINT_MASK) - { - base->STAT |= USART_STAT_PARITYERRINT_MASK; - return kStatus_USART_ParityError; - } - if (status & USART_STAT_RXNOISEINT_MASK) - { - base->STAT |= USART_STAT_RXNOISEINT_MASK; - return kStatus_USART_NoiseError; - } - /* check rxFIFO status */ - if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - return kStatus_USART_RxError; - } - - *data = base->FIFORD; - data++; - } - return kStatus_Success; -} - -/*! - * brief Initializes the USART handle. - * - * This function initializes the USART handle which can be used for other USART - * transactional APIs. Usually, for a specified USART instance, - * call this API once to get the initialized handle. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param callback The callback function. - * param userData The parameter of the callback function. - */ -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData) -{ - int32_t instance = 0; - - /* Check 'base' */ - assert(!((NULL == base) || (NULL == handle))); - if ((NULL == base) || (NULL == handle)) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - memset(handle, 0, sizeof(*handle)); - /* Set the TX/RX state. */ - handle->rxState = kUSART_RxIdle; - handle->txState = kUSART_TxIdle; - /* Set the callback and user data. */ - handle->callback = callback; - handle->userData = userData; - handle->rxWatermark = (usart_rxfifo_watermark_t)USART_FIFOTRIG_RXLVL_GET(base); - handle->txWatermark = (usart_txfifo_watermark_t)USART_FIFOTRIG_TXLVL_GET(base); - - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)USART_TransferHandleIRQ, handle); - - /* Enable interrupt in NVIC. */ - EnableIRQ(s_usartIRQ[instance]); - - return kStatus_Success; -} - -/*! - * brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the IRQ handler, the USART driver calls the callback - * function and passes the ref kStatus_USART_TxIdle as status parameter. - * - * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written - * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, - * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART transfer structure. See #usart_transfer_t. - * retval kStatus_Success Successfully start the data transmission. - * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); - if ((0 == xfer->dataSize) || (NULL == xfer->data)) - { - return kStatus_InvalidArgument; - } - - /* Return error if current TX busy. */ - if (kUSART_TxBusy == handle->txState) - { - return kStatus_USART_TxBusy; - } - else - { - handle->txData = xfer->data; - handle->txDataSize = xfer->dataSize; - handle->txDataSizeAll = xfer->dataSize; - handle->txState = kUSART_TxBusy; - /* Enable transmiter interrupt. */ - base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK; - } - return kStatus_Success; -} - -/*! - * brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are still not sent out. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupts */ - USART_DisableInterrupts(base, kUSART_TxLevelInterruptEnable); - /* Empty txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; - - handle->txDataSize = 0; - handle->txState = kUSART_TxIdle; -} - -/*! - * brief Get the number of bytes that have been written to USART TX register. - * - * This function gets the number of bytes that have been written to USART TX - * register by interrupt method. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Send bytes count. - * retval kStatus_NoTransferInProgress No send in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if (kUSART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - handle->txDataSize; - - return kStatus_Success; -} - -/*! - * brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the USART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the USART driver notifies the upper layer - * through a callback function and passes the status parameter ref kStatus_USART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART transfer structure, see #usart_transfer_t. - * param receivedBytes Bytes received from the ring buffer directly. - * retval kStatus_Success Successfully queue the transfer into transmit queue. - * retval kStatus_USART_RxBusy Previous receive request is not finished. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes) -{ - uint32_t i; - /* How many bytes to copy from ring buffer to user memory. */ - size_t bytesToCopy = 0U; - /* How many bytes to receive. */ - size_t bytesToReceive; - /* How many bytes currently have received. */ - size_t bytesCurrentReceived; - uint32_t regPrimask = 0U; - - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); - if ((0 == xfer->dataSize) || (NULL == xfer->data)) - { - return kStatus_InvalidArgument; - } - - /* How to get data: - 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize - to uart handle, enable interrupt to store received data to xfer->data. When - all data received, trigger callback. - 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. - If there are enough data in ring buffer, copy them to xfer->data and return. - If there are not enough data in ring buffer, copy all of them to xfer->data, - save the xfer->data remained empty space to uart handle, receive data - to this empty space and trigger callback when finished. */ - if (kUSART_RxBusy == handle->rxState) - { - return kStatus_USART_RxBusy; - } - else - { - bytesToReceive = xfer->dataSize; - bytesCurrentReceived = 0U; - /* If RX ring buffer is used. */ - if (handle->rxRingBuffer) - { - /* Disable IRQ, protect ring buffer. */ - regPrimask = DisableGlobalIRQ(); - /* How many bytes in RX ring buffer currently. */ - bytesToCopy = USART_TransferGetRxRingBufferLength(handle); - if (bytesToCopy) - { - bytesToCopy = MIN(bytesToReceive, bytesToCopy); - bytesToReceive -= bytesToCopy; - /* Copy data from ring buffer to user memory. */ - for (i = 0U; i < bytesToCopy; i++) - { - xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; - /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - } - /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive) - { - /* No data in ring buffer, save the request to UART handle. */ - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kUSART_RxBusy; - } - /* Enable IRQ if previously enabled. */ - EnableGlobalIRQ(regPrimask); - /* Call user callback since all data are received. */ - if (0 == bytesToReceive) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Ring buffer not used. */ - else - { - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kUSART_RxBusy; - - /* Enable RX interrupt. */ - base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK; - } - /* Return the how many bytes have read. */ - if (receivedBytes) - { - *receivedBytes = bytesCurrentReceived; - } - } - return kStatus_Success; -} - -/*! - * brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (!handle->rxRingBuffer) - { - /* Disable interrupts */ - USART_DisableInterrupts(base, kUSART_RxLevelInterruptEnable); - /* Empty rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - } - - handle->rxDataSize = 0U; - handle->rxState = kUSART_RxIdle; -} - -/*! - * brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Receive bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if (kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - handle->rxDataSize; - - return kStatus_Success; -} - -/*! - * brief USART IRQ handle function. - * - * This function handles the USART transmit and receive IRQ request. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert((NULL != base) && (NULL != handle)); - - bool receiveEnabled = (handle->rxDataSize) || (handle->rxRingBuffer); - bool sendEnabled = handle->txDataSize; - - /* If RX overrun. */ - if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) - { - /* Clear rx error state. */ - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_RxError, handle->userData); - } - } - while ((receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) || - (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))) - { - /* Receive data */ - if (receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) - { - /* Receive to app bufffer if app buffer is present */ - if (handle->rxDataSize) - { - *handle->rxData = base->FIFORD; - handle->rxDataSize--; - handle->rxData++; - receiveEnabled = ((handle->rxDataSize != 0) || (handle->rxRingBuffer)); - if (!handle->rxDataSize) - { - if (!handle->rxRingBuffer) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; - } - handle->rxState = kUSART_RxIdle; - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Otherwise receive to ring buffer if ring buffer is present */ - else - { - if (handle->rxRingBuffer) - { - /* If RX ring buffer is full, trigger callback to notify over run. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); - } - } - /* If ring buffer is still full after callback function, the oldest data is overrided. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - /* Increase handle->rxRingBufferTail to make room for new data. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - /* Read data. */ - handle->rxRingBuffer[handle->rxRingBufferHead] = base->FIFORD; - /* Increase handle->rxRingBufferHead. */ - if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferHead = 0U; - } - else - { - handle->rxRingBufferHead++; - } - } - } - } - /* Send data */ - if (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) - { - base->FIFOWR = *handle->txData; - handle->txDataSize--; - handle->txData++; - sendEnabled = handle->txDataSize != 0; - if (!sendEnabled) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; - handle->txState = kUSART_TxIdle; - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); - } - } - } - } - - /* ring buffer is not used */ - if (NULL == handle->rxRingBuffer) - { - /* restore if rx transfer ends and rxLevel is different from default value */ - if ((handle->rxDataSize == 0) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); - } - /* decrease level if rx transfer is bellow */ - if ((handle->rxDataSize != 0) && (handle->rxDataSize < (USART_FIFOTRIG_RXLVL_GET(base) + 1))) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(handle->rxDataSize - 1)); - } - } -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_usart.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_usart.h deleted file mode 100644 index 802b61831e..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_usart.h +++ /dev/null @@ -1,660 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_USART_H_ -#define _FSL_USART_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup usart_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART driver version 2.0.3. */ -#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) -#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) - -/*! @brief Error codes for the USART driver. */ -enum _usart_status -{ - kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ - kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ - kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ - kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ - kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ - kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ - kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ - kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ - kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ - kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ - kStatus_USART_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ -}; - -/*! @brief USART parity mode. */ -typedef enum _usart_parity_mode -{ - kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ - kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ - kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ -} usart_parity_mode_t; - -/*! @brief USART stop bit count. */ -typedef enum _usart_stop_bit_count -{ - kUSART_OneStopBit = 0U, /*!< One stop bit */ - kUSART_TwoStopBit = 1U, /*!< Two stop bits */ -} usart_stop_bit_count_t; - -/*! @brief USART data size. */ -typedef enum _usart_data_len -{ - kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ - kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ -} usart_data_len_t; - -/*! @brief txFIFO watermark values */ -typedef enum _usart_txfifo_watermark -{ - kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ - kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ - kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ - kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ - kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ - kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ - kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ - kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ -} usart_txfifo_watermark_t; - -/*! @brief rxFIFO watermark values */ -typedef enum _usart_rxfifo_watermark -{ - kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ - kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ - kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ - kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ - kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ - kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ - kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ - kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ -} usart_rxfifo_watermark_t; - -/*! - * @brief USART interrupt configuration structure, default settings all disabled. - */ -enum _usart_interrupt_enable -{ - kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), - kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), - kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), - kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), -}; - -/*! - * @brief USART status flags. - * - * This provides constants for the USART status flags for use in the USART functions. - */ -enum _usart_flags -{ - kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ - kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ - kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ - kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ - kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ - kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ -}; - -/*! @brief USART configuration structure. */ -typedef struct _usart_config -{ - uint32_t baudRate_Bps; /*!< USART baud rate */ - usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ - usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ - usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ - bool loopback; /*!< Enable peripheral loopback */ - bool enableRx; /*!< Enable RX */ - bool enableTx; /*!< Enable TX */ - usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ -} usart_config_t; - -/*! @brief USART transfer structure. */ -typedef struct _usart_transfer -{ - uint8_t *data; /*!< The buffer of data to be transfer.*/ - size_t dataSize; /*!< The byte count to be transfer. */ -} usart_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _usart_handle usart_handle_t; - -/*! @brief USART transfer callback function. */ -typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); - -/*! @brief USART handle structure. */ -struct _usart_handle -{ - uint8_t *volatile txData; /*!< Address of remaining data to send. */ - volatile size_t txDataSize; /*!< Size of the remaining data to send. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ - volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - - uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ - size_t rxRingBufferSize; /*!< Size of the ring buffer. */ - volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ - volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ - - usart_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< USART callback function parameter.*/ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ - - usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! @brief Returns instance number for USART peripheral base address. */ -uint32_t USART_GetInstance(USART_Type *base); - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes a USART instance with user configuration structure and peripheral clock. - * - * This function configures the USART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the USART_GetDefaultConfig() function. - * Example below shows how to use this API to configure USART. - * @code - * usart_config_t usartConfig; - * usartConfig.baudRate_Bps = 115200U; - * usartConfig.parityMode = kUSART_ParityDisabled; - * usartConfig.stopBitCount = kUSART_OneStopBit; - * USART_Init(USART1, &usartConfig, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param config Pointer to user-defined configuration structure. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_InvalidArgument USART base address is not valid - * @retval kStatus_Success Status USART initialize succeed - */ -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes a USART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the USART clock. - * - * @param base USART peripheral base address. - */ -void USART_Deinit(USART_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the USART configuration structure to a default value. The default - * values are: - * usartConfig->baudRate_Bps = 115200U; - * usartConfig->parityMode = kUSART_ParityDisabled; - * usartConfig->stopBitCount = kUSART_OneStopBit; - * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; - * usartConfig->loopback = false; - * usartConfig->enableTx = false; - * usartConfig->enableRx = false; - * - * @param config Pointer to configuration structure. - */ -void USART_GetDefaultConfig(usart_config_t *config); - -/*! - * @brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. This function is used to update - * the USART module baud rate after the USART module is initialized by the USART_Init. - * @code - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param baudrate_Bps USART baudrate to be set. - * @param srcClock_Hz USART clock source freqency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success Set baudrate succeed. - * @retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get USART status flags. - * - * This function get all USART status flags, the flags are returned as the logical - * OR value of the enumerators @ref _usart_flags. To check a specific status, - * compare the return value with enumerators in @ref _usart_flags. - * For example, to check whether the TX is empty: - * @code - * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) - * { - * ... - * } - * @endcode - * - * @param base USART peripheral base address. - * @return USART status flags which are ORed by the enumerators in the _usart_flags. - */ -static inline uint32_t USART_GetStatusFlags(USART_Type *base) -{ - return base->FIFOSTAT; -} - -/*! - * @brief Clear USART status flags. - * - * This function clear supported USART status flags - * Flags that can be cleared or set are: - * kUSART_TxError - * kUSART_RxError - * For example: - * @code - * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) - * @endcode - * - * @param base USART peripheral base address. - * @param mask status flags to be cleared. - */ -static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) -{ - /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ - base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables USART interrupts according to the provided mask. - * - * This function enables the USART interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * For example, to enable TX empty interrupt and RX full interrupt: - * @code - * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) -{ - base->FIFOINTENSET = mask & 0xF; -} - -/*! - * @brief Disables USART interrupts according to a provided mask. - * - * This function disables the USART interrupts according to a provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * This example shows how to disable the TX empty interrupt and RX full interrupt: - * @code - * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) -{ - base->FIFOINTENCLR = mask & 0xF; -} - -/*! - * @brief Returns enabled USART interrupts. - * - * This function returns the enabled USART interrupts. - * - * @param base USART peripheral base address. - */ -static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) -{ - return base->FIFOINTENSET; -} - -/*! -* @brief Enable DMA for Tx -*/ -static inline void USART_EnableTxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); - } -} - -/*! -* @brief Enable DMA for Rx -*/ -static inline void USART_EnableRxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); - } -} - -/*! - * @brief Enable CTS. - * This function will determine whether CTS is used for flow control. - * - * @param base USART peripheral base address. - * @param enable Enable CTS or not, true for enable and false for disable. - */ -static inline void USART_EnableCTS(USART_Type *base, bool enable) -{ - if (enable) - { - base->CFG |= USART_CFG_CTSEN_MASK; - } - else - { - base->CFG &= ~USART_CFG_CTSEN_MASK; - } -} - -/* @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Writes to the FIFOWR register. - * - * This function writes data to the txFIFO directly. The upper layer must ensure - * that txFIFO has space for data to write before calling this function. - * - * @param base USART peripheral base address. - * @param data The byte to write. - */ -static inline void USART_WriteByte(USART_Type *base, uint8_t data) -{ - base->FIFOWR = data; -} - -/*! - * @brief Reads the FIFORD register directly. - * - * This function reads data from the rxFIFO directly. The upper layer must - * ensure that the rxFIFO is not empty before calling this function. - * - * @param base USART peripheral base address. - * @return The byte read from USART data register. - */ -static inline uint8_t USART_ReadByte(USART_Type *base) -{ - return base->FIFORD; -} - -/*! - * @brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * @param base USART peripheral base address. - * @param data Start address of the data to write. - * @param length Size of the data to write. - */ -void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); - -/*! - * @brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * @param base USART peripheral base address. - * @param data Start address of the buffer to store the received data. - * @param length Size of the buffer. - * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. - * @retval kStatus_USART_ParityError Noise error happened while receiving data. - * @retval kStatus_USART_NoiseError Framing error happened while receiving data. - * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. - * @retval kStatus_Success Successfully received all data. - */ -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the USART handle. - * - * This function initializes the USART handle which can be used for other USART - * transactional APIs. Usually, for a specified USART instance, - * call this API once to get the initialized handle. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param callback The callback function. - * @param userData The parameter of the callback function. - */ -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData); - -/*! - * @brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the IRQ handler, the USART driver calls the callback - * function and passes the @ref kStatus_USART_TxIdle as status parameter. - * - * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written - * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, - * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure. See #usart_transfer_t. - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific USART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * @note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * @param ringBufferSize size of the ring buffer. - */ -void USART_TransferStartRingBuffer(USART_Type *base, - usart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize); - -/*! - * @brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the length of received data in RX ring buffer. - * - * @param handle USART handle pointer. - * @return Length of received data in RX ring buffer. - */ -size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); - -/*! - * @brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are still not sent out. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been written to USART TX register. - * - * This function gets the number of bytes that have been written to USART TX - * register by interrupt method. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Send bytes count. - * @retval kStatus_NoTransferInProgress No send in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the USART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the USART driver notifies the upper layer - * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure, see #usart_transfer_t. - * @param receivedBytes Bytes received from the ring buffer directly. - * @retval kStatus_Success Successfully queue the transfer into transmit queue. - * @retval kStatus_USART_RxBusy Previous receive request is not finished. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes); - -/*! - * @brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief USART IRQ handle function. - * - * This function handles the USART transmit and receive IRQ request. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_USART_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_usart_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_usart_dma.c deleted file mode 100644 index 0e39a7a069..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_usart_dma.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_dma.h" -#include "fsl_flexcomm.h" -#include "fsl_usart_dma.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_dma" -#endif - -/*base, false); - - usartPrivateHandle->handle->txState = kUSART_TxIdle; - - if (usartPrivateHandle->handle->callback) - { - usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_TxIdle, - usartPrivateHandle->handle->userData); - } -} - -static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode) -{ - assert(handle); - assert(param); - - usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param; - - /* Disable UART RX DMA. */ - USART_EnableRxDMA(usartPrivateHandle->base, false); - - usartPrivateHandle->handle->rxState = kUSART_RxIdle; - - if (usartPrivateHandle->handle->callback) - { - usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle, - usartPrivateHandle->handle->userData); - } -} - -/*! - * brief Initializes the USART handle which is used in transactional functions. - * param base USART peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param callback Callback function. - * param userData User data. - * param txDmaHandle User-requested DMA handle for TX DMA transfer. - * param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t USART_TransferCreateHandleDMA(USART_Type *base, - usart_dma_handle_t *handle, - usart_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle) -{ - int32_t instance = 0; - - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } - /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - memset(handle, 0, sizeof(*handle)); - /* assign 'base' and 'handle' */ - s_dmaPrivateHandle[instance].base = base; - s_dmaPrivateHandle[instance].handle = handle; - - /* set tx/rx 'idle' state */ - handle->rxState = kUSART_RxIdle; - handle->txState = kUSART_TxIdle; - - handle->callback = callback; - handle->userData = userData; - - handle->rxDmaHandle = rxDmaHandle; - handle->txDmaHandle = txDmaHandle; - - /* Configure TX. */ - if (txDmaHandle) - { - DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); - } - - /* Configure RX. */ - if (rxDmaHandle) - { - DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); - } - - return kStatus_Success; -} - -/*! - * brief Sends data using DMA. - * - * This function sends data using DMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART DMA transfer structure. See #usart_transfer_t. - * retval kStatus_Success if succeed, others failed. - * retval kStatus_USART_TxBusy Previous transfer on going. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) -{ - assert(handle); - assert(handle->txDmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - dma_transfer_config_t xferConfig; - status_t status; - - /* If previous TX not finished. */ - if (kUSART_TxBusy == handle->txState) - { - status = kStatus_USART_TxBusy; - } - else - { - handle->txState = kUSART_TxBusy; - handle->txDataSizeAll = xfer->dataSize; - - /* Enable DMA request from txFIFO */ - USART_EnableTxDMA(base, true); - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, xfer->data, ((void *)((uint32_t)&base->FIFOWR)), sizeof(uint8_t), - xfer->dataSize, kDMA_MemoryToPeripheral, NULL); - - /* Submit transfer. */ - DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); - DMA_StartTransfer(handle->txDmaHandle); - - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * param base USART peripheral base address. - * param handle Pointer to usart_dma_handle_t structure. - * param xfer USART DMA transfer structure. See #usart_transfer_t. - * retval kStatus_Success if succeed, others failed. - * retval kStatus_USART_RxBusy Previous transfer on going. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) -{ - assert(handle); - assert(handle->rxDmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - dma_transfer_config_t xferConfig; - status_t status; - - /* If previous RX not finished. */ - if (kUSART_RxBusy == handle->rxState) - { - status = kStatus_USART_RxBusy; - } - else - { - handle->rxState = kUSART_RxBusy; - handle->rxDataSizeAll = xfer->dataSize; - - /* Enable DMA request from rxFIFO */ - USART_EnableRxDMA(base, true); - - /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), xfer->data, sizeof(uint8_t), - xfer->dataSize, kDMA_PeripheralToMemory, NULL); - - /* Submit transfer. */ - DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); - DMA_StartTransfer(handle->rxDmaHandle); - - status = kStatus_Success; - } - - return status; -} - -/*! - * brief Aborts the sent data using DMA. - * - * This function aborts send data using DMA. - * - * param base USART peripheral base address - * param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->txDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->txDmaHandle); - handle->txState = kUSART_TxIdle; -} - -/*! - * brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * param base USART peripheral base address - * param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) -{ - assert(NULL != handle); - assert(NULL != handle->rxDmaHandle); - - /* Stop transfer. */ - DMA_AbortTransfer(handle->rxDmaHandle); - handle->rxState = kUSART_RxIdle; -} - -/*! - * brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Receive bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(handle->rxDmaHandle); - assert(count); - - if (kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); - - return kStatus_Success; -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_usart_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_usart_dma.h deleted file mode 100644 index a0c1392702..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_usart_dma.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_USART_DMA_H_ -#define _FSL_USART_DMA_H_ - -#include "fsl_common.h" -#include "fsl_dma.h" -#include "fsl_usart.h" - -/*! - * @addtogroup usart_dma_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART dma driver version 2.0.1. */ -#define FSL_USART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/* Forward declaration of the handle typedef. */ -typedef struct _usart_dma_handle usart_dma_handle_t; - -/*! @brief UART transfer callback function. */ -typedef void (*usart_dma_transfer_callback_t)(USART_Type *base, - usart_dma_handle_t *handle, - status_t status, - void *userData); - -/*! -* @brief UART DMA handle -*/ -struct _usart_dma_handle -{ - USART_Type *base; /*!< UART peripheral base address. */ - - usart_dma_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< UART callback function parameter.*/ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - - dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ - dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name DMA transactional - * @{ - */ - -/*! - * @brief Initializes the USART handle which is used in transactional functions. - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param callback Callback function. - * @param userData User data. - * @param txDmaHandle User-requested DMA handle for TX DMA transfer. - * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. - */ -status_t USART_TransferCreateHandleDMA(USART_Type *base, - usart_dma_handle_t *handle, - usart_dma_transfer_callback_t callback, - void *userData, - dma_handle_t *txDmaHandle, - dma_handle_t *rxDmaHandle); - -/*! - * @brief Sends data using DMA. - * - * This function sends data using DMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART DMA transfer structure. See #usart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_USART_TxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Receives data using DMA. - * - * This function receives data using DMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * @param base USART peripheral base address. - * @param handle Pointer to usart_dma_handle_t structure. - * @param xfer USART DMA transfer structure. See #usart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_USART_RxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Aborts the sent data using DMA. - * - * This function aborts send data using DMA. - * - * @param base USART peripheral base address - * @param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle); - -/*! - * @brief Aborts the received data using DMA. - * - * This function aborts the received data using DMA. - * - * @param base USART peripheral base address - * @param handle Pointer to usart_dma_handle_t structure - */ -void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_USART_DMA_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_utick.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_utick.c deleted file mode 100644 index df5a5ac12a..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_utick.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_utick.h" -#include "fsl_power.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.utick" -#endif - -/* Typedef for interrupt handler. */ -typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base UTICK peripheral base address - * - * @return The UTICK instance - */ -static uint32_t UTICK_GetInstance(UTICK_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of UTICK handle. */ -static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT]; -/* Array of UTICK peripheral base address. */ -static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS; -/* Array of UTICK IRQ number. */ -static const IRQn_Type s_utickIRQ[] = UTICK_IRQS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of UTICK clock name. */ -static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) -/*! @brief Pointers to UTICK resets for each instance. */ -static const reset_ip_name_t s_utickResets[] = UTICK_RSTS; -#endif - -/* UTICK ISR for transactional APIs. */ -static utick_isr_t s_utickIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t UTICK_GetInstance(UTICK_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++) - { - if (s_utickBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_utickBases)); - - return instance; -} - -/*! - * brief Starts UTICK. - * - * This function starts a repeat/onetime countdown with an optional callback - * - * param base UTICK peripheral base address. - * param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) - * return none - */ -void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb) -{ - uint32_t instance; - - /* Get instance from peripheral base address. */ - instance = UTICK_GetInstance(base); - - /* Save the handle in global variables to support the double weak mechanism. */ - s_utickHandle[instance] = cb; - EnableDeepSleepIRQ(s_utickIRQ[instance]); - base->CTRL = count | UTICK_CTRL_REPEAT(mode); -} - -/*! -* brief Initializes an UTICK by turning its bus clock on -* -*/ -void UTICK_Init(UTICK_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable utick clock */ - CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]); -#endif - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) - RESET_PeripheralReset(s_utickResets[UTICK_GetInstance(base)]); -#endif - -#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) - /* Power up Watchdog oscillator*/ - POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC); -#endif - - s_utickIsr = UTICK_HandleIRQ; -} - -/*! - * brief Deinitializes a UTICK instance. - * - * This function shuts down Utick bus clock - * - * param base UTICK peripheral base address. - */ -void UTICK_Deinit(UTICK_Type *base) -{ - /* Turn off utick */ - base->CTRL = 0; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable utick clock */ - CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]); -#endif -} - -/*! - * brief Get Status Flags. - * - * This returns the status flag - * - * param base UTICK peripheral base address. - * return status register value - */ -uint32_t UTICK_GetStatusFlags(UTICK_Type *base) -{ - return (base->STAT); -} - -/*! - * brief Clear Status Interrupt Flags. - * - * This clears intr status flag - * - * param base UTICK peripheral base address. - * return none - */ -void UTICK_ClearStatusFlags(UTICK_Type *base) -{ - base->STAT = UTICK_STAT_INTR_MASK; -} - -/*! - * brief UTICK Interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in UTICK_SetTick()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * param base UTICK peripheral base address. - * param cb callback scheduled for this instance of UTICK - * return none - */ -void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) -{ - UTICK_ClearStatusFlags(base); - if (cb) - { - cb(); - } -} - -#if defined(UTICK0) -void UTICK0_DriverIRQHandler(void) -{ - s_utickIsr(UTICK0, s_utickHandle[0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#if defined(UTICK1) -void UTICK1_DriverIRQHandler(void) -{ - s_utickIsr(UTICK1, s_utickHandle[1]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#if defined(UTICK2) -void UTICK2_DriverIRQHandler(void) -{ - s_utickIsr(UTICK2, s_utickHandle[2]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_utick.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_utick.h deleted file mode 100644 index 3c8cf046d1..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_utick.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_UTICK_H_ -#define _FSL_UTICK_H_ - -#include "fsl_common.h" -/*! - * @addtogroup utick - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief UTICK driver version 2.0.2. */ -#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/*! @brief UTICK timer operational mode. */ -typedef enum _utick_mode -{ - kUTICK_Onetime = 0x0U, /*!< Trigger once*/ - kUTICK_Repeat = 0x1U, /*!< Trigger repeatedly */ -} utick_mode_t; - -/*! @brief UTICK callback function. */ -typedef void (*utick_callback_t)(void); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! -* @brief Initializes an UTICK by turning its bus clock on -* -*/ -void UTICK_Init(UTICK_Type *base); - -/*! - * @brief Deinitializes a UTICK instance. - * - * This function shuts down Utick bus clock - * - * @param base UTICK peripheral base address. - */ -void UTICK_Deinit(UTICK_Type *base); -/*! - * @brief Get Status Flags. - * - * This returns the status flag - * - * @param base UTICK peripheral base address. - * @return status register value - */ -uint32_t UTICK_GetStatusFlags(UTICK_Type *base); -/*! - * @brief Clear Status Interrupt Flags. - * - * This clears intr status flag - * - * @param base UTICK peripheral base address. - * @return none - */ -void UTICK_ClearStatusFlags(UTICK_Type *base); - -/*! - * @brief Starts UTICK. - * - * This function starts a repeat/onetime countdown with an optional callback - * - * @param base UTICK peripheral base address. - * @param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * @param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) - * @param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) - * @return none - */ -void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb); -/*! - * @brief UTICK Interrupt Service Handler. - * - * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request - * in UTICK_SetTick()). - * if no user callback is scheduled, the interrupt will simply be cleared. - * - * @param base UTICK peripheral base address. - * @param cb callback scheduled for this instance of UTICK - * @return none - */ -void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_UTICK_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_wwdt.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_wwdt.c deleted file mode 100644 index d341058a5c..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_wwdt.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_wwdt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.wwdt" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Gets the instance from the base address - * - * @param base WWDT peripheral base address - * - * @return The WWDT instance - */ -static uint32_t WWDT_GetInstance(WWDT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to WWDT bases for each instance. */ -static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to WWDT clocks for each instance. */ -static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) -/*! @brief Pointers to WWDT resets for each instance. */ -static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t WWDT_GetInstance(WWDT_Type *base) -{ - uint32_t instance; - uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < wwdtArrayCount; instance++) - { - if (s_wwdtBases[instance] == base) - { - break; - } - } - - assert(instance < wwdtArrayCount); - - return instance; -} - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initializes WWDT configure structure. - * - * This function initializes the WWDT configure structure to default value. The default - * value are: - * code - * config->enableWwdt = true; - * config->enableWatchdogReset = false; - * config->enableWatchdogProtect = false; - * config->enableLockOscillator = false; - * config->windowValue = 0xFFFFFFU; - * config->timeoutValue = 0xFFFFFFU; - * config->warningValue = 0; - * endcode - * - * param config Pointer to WWDT config structure. - * see wwdt_config_t - */ -void WWDT_GetDefaultConfig(wwdt_config_t *config) -{ - assert(config); - - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - - /* Enable the watch dog */ - config->enableWwdt = true; - /* Disable the watchdog timeout reset */ - config->enableWatchdogReset = false; - /* Disable the watchdog protection for updating the timeout value */ - config->enableWatchdogProtect = false; -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - /* Do not lock the watchdog oscillator */ - config->enableLockOscillator = false; -#endif - /* Windowing is not in effect */ - config->windowValue = 0xFFFFFFU; - /* Set the timeout value to the max */ - config->timeoutValue = 0xFFFFFFU; - /* No warning is provided */ - config->warningValue = 0; - /* Set clock frequency. */ - config->clockFreq_Hz = 0U; -} - -/*! - * brief Initializes the WWDT. - * - * This function initializes the WWDT. When called, the WWDT runs according to the configuration. - * - * Example: - * code - * wwdt_config_t config; - * WWDT_GetDefaultConfig(&config); - * config.timeoutValue = 0x7ffU; - * WWDT_Init(wwdt_base,&config); - * endcode - * - * param base WWDT peripheral base address - * param config The configuration of WWDT - */ -void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) -{ - assert(config); - /* The config->clockFreq_Hz must be set in order to config the delay time. */ - assert(config->clockFreq_Hz); - - uint32_t value = 0U; - uint32_t timeDelay = 0U; - - timeDelay = (SystemCoreClock / config->clockFreq_Hz + 1) * 3; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the WWDT clock */ - CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) - /* Reset the module. */ - RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) | - WWDT_MOD_LOCK(config->enableLockOscillator); -#else - value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset); -#endif - /* Set configuration */ - base->TC = WWDT_TC_COUNT(config->timeoutValue); - base->MOD |= value; - base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); - base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue); - WWDT_Refresh(base); - /* This WDPROTECT bit can be set once by software and is only cleared by a reset */ - if ((base->MOD & WWDT_MOD_WDPROTECT_MASK) == 0U) - { - /* Set the WDPROTECT bit after the Feed Sequence (0xAA, 0x55) with 3 WDCLK delay */ - while (timeDelay--) - { - __NOP(); - } - base->MOD |= WWDT_MOD_WDPROTECT(config->enableWatchdogProtect); - } -} - -/*! - * brief Shuts down the WWDT. - * - * This function shuts down the WWDT. - * - * param base WWDT peripheral base address - */ -void WWDT_Deinit(WWDT_Type *base) -{ - WWDT_Disable(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the WWDT clock */ - CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Refreshes the WWDT timer. - * - * This function feeds the WWDT. - * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. - * - * param base WWDT peripheral base address - */ -void WWDT_Refresh(WWDT_Type *base) -{ - uint32_t primaskValue = 0U; - - /* Disable the global interrupt to protect refresh sequence */ - primaskValue = DisableGlobalIRQ(); - base->FEED = WWDT_FIRST_WORD_OF_REFRESH; - base->FEED = WWDT_SECOND_WORD_OF_REFRESH; - EnableGlobalIRQ(primaskValue); -} - -/*! - * brief Clear WWDT flag. - * - * This function clears WWDT status flag. - * - * Example for clearing warning flag: - * code - * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); - * endcode - * param base WWDT peripheral base address - * param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask) -{ - /* Clear the WDINT bit so that we don't accidentally clear it */ - uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK)); - - /* Clear timeout by writing a zero */ - if (mask & kWWDT_TimeoutFlag) - { - reg &= ~WWDT_MOD_WDTOF_MASK; - } - - /* Clear warning interrupt flag by writing a one */ - if (mask & kWWDT_WarningFlag) - { - reg |= WWDT_MOD_WDINT_MASK; - } - - base->MOD = reg; -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_wwdt.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_wwdt.h deleted file mode 100644 index ef71c8143f..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/drivers/fsl_wwdt.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_WWDT_H_ -#define _FSL_WWDT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup wwdt - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines WWDT driver version 2.1.1. */ -#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ - -/*! @name Refresh sequence */ -/*@{*/ -#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */ -#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */ -/*@}*/ - -/*! @brief Describes WWDT configuration structure. */ -typedef struct _wwdt_config -{ - bool enableWwdt; /*!< Enables or disables WWDT */ - bool enableWatchdogReset; /*!< true: Watchdog timeout will cause a chip reset - false: Watchdog timeout will not cause a chip reset */ - bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be - changed after counter is below warning & window values - false: Disable watchdog protect; timeout value can be changed - at any time */ -#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) - bool enableLockOscillator; /*!< true: Disabling or powering down the watchdog oscillator is prevented - Once set, this bit can only be cleared by a reset - false: Do not lock oscillator */ -#endif - uint32_t windowValue; /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */ - uint32_t timeoutValue; /*!< Timeout value */ - uint32_t warningValue; /*!< Watchdog time counter value that will generate a - warning interrupt. Set this to 0 for no warning */ - uint32_t clockFreq_Hz; /*!< Watchdog clock source frequency. */ -} wwdt_config_t; - -/*! - * @brief WWDT status flags. - * - * This structure contains the WWDT status flags for use in the WWDT functions. - */ -enum _wwdt_status_flags_t -{ - kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */ - kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */ -}; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name WWDT Initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes WWDT configure sturcture. - * - * This function initializes the WWDT configure structure to default value. The default - * value are: - * @code - * config->enableWwdt = true; - * config->enableWatchdogReset = false; - * config->enableWatchdogProtect = false; - * config->enableLockOscillator = false; - * config->windowValue = 0xFFFFFFU; - * config->timeoutValue = 0xFFFFFFU; - * config->warningValue = 0; - * @endcode - * - * @param config Pointer to WWDT config structure. - * @see wwdt_config_t - */ -void WWDT_GetDefaultConfig(wwdt_config_t *config); - -/*! - * @brief Initializes the WWDT. - * - * This function initializes the WWDT. When called, the WWDT runs according to the configuration. - * - * Example: - * @code - * wwdt_config_t config; - * WWDT_GetDefaultConfig(&config); - * config.timeoutValue = 0x7ffU; - * WWDT_Init(wwdt_base,&config); - * @endcode - * - * @param base WWDT peripheral base address - * @param config The configuration of WWDT - */ -void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config); - -/*! - * @brief Shuts down the WWDT. - * - * This function shuts down the WWDT. - * - * @param base WWDT peripheral base address - */ -void WWDT_Deinit(WWDT_Type *base); - -/* @} */ - -/*! - * @name WWDT Functional Operation - * @{ - */ - -/*! - * @brief Enables the WWDT module. - * - * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit; - * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run - * permanently. - * - * @param base WWDT peripheral base address - */ -static inline void WWDT_Enable(WWDT_Type *base) -{ - base->MOD |= WWDT_MOD_WDEN_MASK; -} - -/*! - * @brief Disables the WWDT module. - * - * This function write value into WWDT_MOD register to disable the WWDT. - * - * @param base WWDT peripheral base address - */ -static inline void WWDT_Disable(WWDT_Type *base) -{ - base->MOD &= ~WWDT_MOD_WDEN_MASK; -} - -/*! - * @brief Gets all WWDT status flags. - * - * This function gets all status flags. - * - * Example for getting Timeout Flag: - * @code - * uint32_t status; - * status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag; - * @endcode - * @param base WWDT peripheral base address - * @return The status flags. This is the logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base) -{ - return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); -} - -/*! - * @brief Clear WWDT flag. - * - * This function clears WWDT status flag. - * - * Example for clearing warning flag: - * @code - * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); - * @endcode - * @param base WWDT peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::_wwdt_status_flags_t - */ -void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask); - -/*! - * @brief Set the WWDT warning value. - * - * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog - * interrupt. When the watchdog timer counter is no longer greater than the value defined by - * WARNINT, an interrupt will be generated after the subsequent WDCLK. - * - * @param base WWDT peripheral base address - * @param warningValue WWDT warning value. - */ -static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue) -{ - base->WARNINT = WWDT_WARNINT_WARNINT(warningValue); -} - -/*! - * @brief Set the WWDT timeout value. - * - * This function sets the timeout value. Every time a feed sequence occurs the value in the TC - * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be - * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4. - * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change - * the timeout value before the watchdog counter is below the warning and window values - * will cause a watchdog reset and set the WDTOF flag. - * - * @param base WWDT peripheral base address - * @param timeoutCount WWDT timeout value, count of WWDT clock tick. - */ -static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount) -{ - base->TC = WWDT_TC_COUNT(timeoutCount); -} - -/*! - * @brief Sets the WWDT window value. - * - * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed. - * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog - * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer - * value) so windowing is not in effect. - * - * @param base WWDT peripheral base address - * @param windowValue WWDT window value. - */ -static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue) -{ - base->WINDOW = WWDT_WINDOW_WINDOW(windowValue); -} - -/*! - * @brief Refreshes the WWDT timer. - * - * This function feeds the WWDT. - * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. - * - * @param base WWDT peripheral base address - */ -void WWDT_Refresh(WWDT_Type *base); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_WWDT_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/flash_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/flash_api.c deleted file mode 100644 index c4a3049e48..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/flash_api.c +++ /dev/null @@ -1,209 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2017 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "flash_api.h" -#include "mbed_toolchain.h" -#include "mbed_critical.h" - -#if DEVICE_FLASH - -#include "fsl_iap.h" -#include "partition/region_defs.h" -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#include -#endif - -#define LPC55S69_SECURE_FLASH_START (PSA_SECURE_ROM_START - S_ROM_ALIAS_BASE) -#define LPC55S69_SECURE_FLASH_SIZE (PSA_SECURE_ROM_SIZE + FLASH_SST_AREA_SIZE) - -static flash_config_t flash_config; - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/* Check if address range [start_addr, end_addr] is in non-secure flash - * - * @param obj The flash object - * @param start_addr Start address to check - * @param end_addr End address to check. Could be the same as start_addr to just check start_addr - * for e.g. flash_erase_sector. - * @return 0 for success, -1 for error - */ -static int32_t flash_check_nonsecure(flash_t *obj, uint32_t start_addr, uint32_t end_addr) -{ - /* Check if end address wraps around */ - if (end_addr < start_addr) { - return -1; - } - - /* Check if start address is in non-secure flash */ - if ((start_addr < PSA_NON_SECURE_ROM_START) || - (start_addr >= (PSA_NON_SECURE_ROM_START + PSA_NON_SECURE_ROM_SIZE))) { - return -1; - } - - /* Check if end address is in non-secure flash */ - if (end_addr != start_addr) { - if ((end_addr < PSA_NON_SECURE_ROM_START) || - (end_addr >= (PSA_NON_SECURE_ROM_START + PSA_NON_SECURE_ROM_SIZE))) { - return -1; - } - } - - return 0; -} - -MBED_NONSECURE_ENTRY int32_t flash_init(flash_t *obj) -{ - /* Set the clock frequency to prevent from ROM changing the Flash access time */ - flash_config.modeConfig.sysFreqInMHz = SystemCoreClock / 1000000; - - if (FLASH_Init(&flash_config) != kStatus_Success) { - return -1; - } else { - return 0; - } -} - -MBED_NONSECURE_ENTRY int32_t flash_erase_sector(flash_t *obj, uint32_t address) -{ - if (cmse_nonsecure_caller()) { - // Confine non-secure access to non-secure flash - if (flash_check_nonsecure(obj, address, address)) { - return -1; - } - } - - core_util_critical_section_enter(); - - uint32_t status; - - status = FLASH_Erase(&flash_config, address, flash_config.PFlashPageSize, kFLASH_ApiEraseKey); - if (status == kStatus_Success) { - status = FLASH_VerifyErase(&flash_config, address, flash_config.PFlashPageSize); - } - core_util_critical_section_exit(); - - if (status != kStatus_Success) { - return -1; - } else { - return 0; - } -} - -MBED_NONSECURE_ENTRY int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) -{ - if (cmse_nonsecure_caller()) { - // Confine non-secure access to non-secure flash - if (flash_check_nonsecure(obj, address, address + size - 1)) { - return -1; - } - } - - core_util_critical_section_enter(); - - uint32_t n; - uint32_t status; - uint32_t failedAddress, failedData; - - status = FLASH_Program(&flash_config, address, (uint8_t *)data, size); - if (status == kStatus_Success) { - status = FLASH_VerifyProgram(&flash_config, address, size, data, &failedAddress, &failedData); - } - core_util_critical_section_exit(); - - if (status != kStatus_Success) { - return -1; - } else { - return 0; - } -} - -MBED_NONSECURE_ENTRY int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size) -{ - if (cmse_nonsecure_caller()) { - // Confine non-secure access to non-secure flash - if (flash_check_nonsecure(obj, address, address + size - 1)) { - return -1; - } - } - - /* Check if flash is empty */ - if (FLASH_VerifyErase(&flash_config, address, size) == kStatus_FLASH_Success) { - memset(data, 0x0, size); - return 0; - } - - memcpy(data, (const void *)address, size); - return 0; -} -#endif // #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -int32_t flash_free(flash_t *obj) -{ - return 0; -} - -uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) -{ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - if ((address >= LPC55S69_SECURE_FLASH_START) && - (address < (LPC55S69_SECURE_FLASH_START + LPC55S69_SECURE_FLASH_SIZE))) { - return FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES; - } - - return MBED_FLASH_INVALID_SIZE; -#else - if ((address >= PSA_NON_SECURE_ROM_START) && - (address < (PSA_NON_SECURE_ROM_START + PSA_NON_SECURE_ROM_SIZE))) { - return FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES; - } - - return MBED_FLASH_INVALID_SIZE; -#endif -} - -uint32_t flash_get_page_size(const flash_t *obj) -{ - return FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES; -} - -uint32_t flash_get_start_address(const flash_t *obj) -{ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - return LPC55S69_SECURE_FLASH_START; -#else - return PSA_NON_SECURE_ROM_START; -#endif -} - -uint32_t flash_get_size(const flash_t *obj) -{ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - return LPC55S69_SECURE_FLASH_SIZE; -#else - return PSA_NON_SECURE_ROM_SIZE; -#endif -} - -uint8_t flash_get_erase_value(const flash_t *obj) -{ - (void)obj; - - return 0x0; -} - -#endif //DEVICE_FLASH - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/partition/flash_layout.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/partition/flash_layout.h deleted file mode 100644 index e462c6cea8..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/partition/flash_layout.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2018 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __FLASH_LAYOUT_H__ -#define __FLASH_LAYOUT_H__ - -/* Flash layout on LPC55S69 without BL2: - * - * 0x0000_0000 Secure image primary - * 0x0002_8000 SST / ITS - * 0x0003_0000 Non-secure - */ - -/* This header file is included from linker scatter file as well, where only a - * limited C constructs are allowed. Therefore it is not possible to include - * here the platform_retarget.h to access flash related defines. To resolve this - * some of the values are redefined here with different names, these are marked - * with comment. - */ - -/* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */ -#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x8000) /* 32 kB */ -/* Same as FLASH0_SIZE */ -#define FLASH_TOTAL_SIZE (0x00098000) /* 608 kB */ - -/* Flash layout info for BL2 bootloader */ -#define FLASH_BASE_ADDRESS (0x10000000) /* same as FLASH0_BASE_S */ - -/* Offset and size definitions of the flash partitions that are handled by thes - * bootloader. The image swapping is done between IMAGE_0 and IMAGE_1, SCRATCH - * is used as a temporary storage during image swapping. - */ -#define FLASH_AREA_BL2_OFFSET (0x0) -#ifdef BL2 -#define FLASH_AREA_BL2_SIZE (0x10000) /* 64kB */ -#else -#define FLASH_AREA_BL2_SIZE (0x0) -#endif - -/* Secure image */ -#define FLASH_AREA_IMAGE_0_OFFSET (FLASH_AREA_BL2_OFFSET + \ - FLASH_AREA_BL2_SIZE) // 0 -#define FLASH_AREA_IMAGE_0_SIZE (0x00028000 - FLASH_AREA_BL2_SIZE) // 0x00028000 - -#define FLASH_SST_AREA_OFFSET (FLASH_AREA_IMAGE_0_OFFSET + \ - FLASH_AREA_IMAGE_0_SIZE) // 0x00028000 -#define FLASH_SST_AREA_SIZE (0x00008000) /* 32 KB */ - -/* Non-secure image */ -#define FLASH_AREA_IMAGE_1_OFFSET (FLASH_SST_AREA_OFFSET +\ - FLASH_SST_AREA_SIZE) // 0x00030000 -#define FLASH_AREA_IMAGE_1_SIZE (0x00068000) - -#define FLASH_AREA_IMAGE_SCRATCH_OFFSET (FLASH_AREA_IMAGE_1_OFFSET +\ - FLASH_AREA_IMAGE_1_SIZE) -#define FLASH_AREA_IMAGE_SCRATCH_SIZE (0) - -/* Offset and size definition in flash area, used by assemble.py */ -#define SECURE_IMAGE_OFFSET 0x0 -#define SECURE_IMAGE_MAX_SIZE 0x00028000 - -#define NON_SECURE_IMAGE_OFFSET 0x00030000 -#define NON_SECURE_IMAGE_MAX_SIZE 0x00068000 - -/* Flash device name used by BL2 and SST - * Name is defined in flash driver file: Driver_Flash.c - */ -#define FLASH_DEV_NAME Driver_FLASH0 - -/* Secure Storage (SST) Service definitions - * Note: Further documentation of these definitions can be found in the - * TF-M SST Integration Guide. - */ -/* In this target the CMSIS driver requires only the offset from the base - * address instead of the full memory address. - */ -#define SST_FLASH_AREA_ADDR FLASH_SST_AREA_OFFSET -#define SST_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE -/* The sectors must be in consecutive memory location */ -#define SST_NBR_OF_SECTORS (FLASH_SST_AREA_SIZE / SST_SECTOR_SIZE) -/* Specifies the smallest flash programmable unit in bytes */ -#define SST_FLASH_PROGRAM_UNIT (512) -/* The maximum asset size to be stored in the SST area */ -#define SST_MAX_ASSET_SIZE 2048 -/* The maximum number of assets to be stored in the SST area */ -#define SST_NUM_ASSETS 10 - -/* FIXME: Use SRAM2 memory to store RW data */ -#define S_RAM_ALIAS_BASE (0x30000000) -#define NS_RAM_ALIAS_BASE (0x20000000) - -/* Shared data area between bootloader and runtime firmware. - * Shared data area is allocated at the beginning of the RAM, it is overlapping - * with TF-M Secure code's MSP stack - */ -#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE -#define BOOT_TFM_SHARED_DATA_SIZE 0x400 - -#endif /* __FLASH_LAYOUT_H__ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/partition/region_defs.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/partition/region_defs.h deleted file mode 100644 index f2ba531508..0000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/partition/region_defs.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2017-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __REGION_DEFS_H__ -#define __REGION_DEFS_H__ - -#include "flash_layout.h" - -#define TOTAL_ROM_SIZE (0x8000) /* 32KB */ -#define TOTAL_RAM_SIZE (0x00044000) /* 272KB */ - -#define BL2_HEAP_SIZE 0x0001000 -#define BL2_MSP_STACK_SIZE 0x0001000 - -#define S_HEAP_SIZE 0x0004000 -#define S_MSP_STACK_SIZE_INIT 0x0000400 -#define S_MSP_STACK_SIZE 0x0000800 -#define S_PSP_STACK_SIZE 0x0000800 - -#define NS_HEAP_SIZE 0x0001000 -#define NS_MSP_STACK_SIZE 0x0000400 -#define NS_PSP_STACK_SIZE 0x0000C00 - -#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_IMAGE_0_OFFSET) -#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_IMAGE_1_OFFSET) - -/* - * Boot partition structure if MCUBoot is used: - * 0x0_0000 Bootloader header - * 0x0_0400 Image area - * 0x1_FC00 Trailer - */ -#define BL2_HEADER_SIZE (0x0) -#define BL2_TRAILER_SIZE (0x0) - -/* IMAGE_CODE_SIZE is the space available for the software binary image. - * It could be less than the FLASH_AREA_IMAGE_0_SIZE because we reserve space - * for the image header and trailer introduced by the bootloader. - */ -#define IMAGE_CODE_SIZE (FLASH_AREA_IMAGE_0_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) - -#define CMSE_VENEER_REGION_SIZE (0x000001C0) - -/* Use Flash memory to store Code data */ -#define S_ROM_ALIAS_BASE (0x10000000) -#define NS_ROM_ALIAS_BASE (0x00000000) - -#define S_RAM_ALIAS_BASE (0x30000000) -#define NS_RAM_ALIAS_BASE (0x20000000) - -/* Alias definitions for secure and non-secure areas*/ -#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + x) -#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + x) - -#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + x) -#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + x) - -/* Secure regions */ -#define S_IMAGE_PRIMARY_AREA_OFFSET (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) -#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET)) -#define S_CODE_SIZE (IMAGE_CODE_SIZE - CMSE_VENEER_REGION_SIZE) -#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) - -#define S_DATA_START (S_RAM_ALIAS(0x0)) - -//#if defined(TEST_FRAMEWORK_S) || defined(TEST_FRAMEWORK_NS) -/* Increase secure DATA area to run the regression tests */ -//#define S_DATA_SIZE ((TOTAL_RAM_SIZE / 4) * 3) -//#else -#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2) -//#endif - -#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) - -/* CMSE Veneers region */ -#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1) - -/* Non-secure regions */ -#define NS_IMAGE_PRIMARY_AREA_OFFSET (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) -#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET)) -#define NS_CODE_SIZE (FLASH_AREA_IMAGE_1_SIZE) -#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) - -#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE)) -#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) - -#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) - -/* Subregion of RAM in AHB controller is 4 kB */ -#define DATA_SUBREGION_SIZE 0x1000 - -/* NS partition information is used for MPC and SAU configuration */ -#define NS_PARTITION_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET)) - -#define NS_PARTITION_SIZE (NS_CODE_SIZE) - -/* Code SRAM area */ -#define TOTAL_CODE_SRAM_SIZE (TOTAL_ROM_SIZE) -#define S_CODE_SRAM_ALIAS_BASE (0x14000000) -#define NS_CODE_SRAM_ALIAS_BASE (0x04000000) - -#define BL2_CODE_SRAM_EXEC_BASE (S_CODE_SRAM_ALIAS_BASE) -#define S_CODE_SRAM_EXEC_BASE (S_CODE_SRAM_ALIAS_BASE) -#define S_CODE_SRAM_EXEC_LIMIT (S_CODE_SRAM_EXEC_BASE + (TOTAL_CODE_SRAM_SIZE / 2) - 1) -#define NS_CODE_SRAM_EXEC_BASE (NS_CODE_SRAM_ALIAS_BASE + (TOTAL_CODE_SRAM_SIZE / 2)) -#define NS_CODE_SRAM_EXEC_LIMIT (NS_CODE_SRAM_EXEC_BASE + (TOTAL_CODE_SRAM_SIZE / 2) - 1) - -#endif /* __REGION_DEFS_H__ */