Support M251/M261/M453/NANO130/NUC472 PWM duty cycle range as 0 ~ 10000

pull/14379/head
cyliangtw 2021-03-04 19:58:03 +08:00
parent abdcc7b831
commit 045f443bb2
10 changed files with 24 additions and 24 deletions

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@ -138,7 +138,7 @@ uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u
* - PWM1 : PWM Group 1
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%...
* @return Nearest frequency clock in nano second
* @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure PWM frequency may affect
* existing frequency of other channel.
@ -155,7 +155,7 @@ uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u3
* - PWM1 : PWM Group 1
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency = u32Frequency / u32Frequency2
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%...
* @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2
* @return Nearest frequency clock in nano second
* @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure PWM frequency may affect
@ -221,10 +221,10 @@ uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u
if (u32DutyCycle)
{
if (u32DutyCycle >= 100UL)
if (u32DutyCycle >= 10000UL)
PWM_SET_CMR(pwm, u32ChannelNum, u16CNR);
else
PWM_SET_CMR(pwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1UL) / 100UL);
PWM_SET_CMR(pwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1UL) / 10000UL);
(pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1UL));
(pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << ((u32ChannelNum << 1UL) + PWM_WGCTL0_PRDPCTL0_Pos));

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@ -195,10 +195,10 @@ static void pwmout_config(pwmout_t *obj, int start)
// NOTE: Support period < 1s
// NOTE: ARM mbed CI test fails due to first PWM pulse error. Workaround by:
// 1. Inverse duty cycle (100 - duty)
// 1. Inverse duty cycle (10000 - duty)
// 2. Inverse PWM output polarity
// This trick is here to pass ARM mbed CI test. First PWM pulse error still remains.
PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 100 - obj->pulsewidth_us * 100 / obj->period_us, obj->period_us);
PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 10000 - obj->pulsewidth_us * 10000 / obj->period_us, obj->period_us);
pwm_base->POLCTL |= 1 << (PWM_POLCTL_PINV0_Pos + chn);
if (start) {

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@ -117,7 +117,7 @@ uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_
* - EPWM1 : EPWM Group 1
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%...
* @return Nearest frequency clock in nano second
* @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect
* existing frequency of other channel.
@ -136,7 +136,7 @@ uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t
* - EPWM1 : EPWM Group 1
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%...
* @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2
* @return Nearest frequency clock in nano second
* @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect
@ -183,7 +183,7 @@ uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_
u32CNR = u32CNR - 1U;
EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR);
EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL);
EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 10000UL);
(epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~((EPWM_WGCTL0_PRDPCTL0_Msk | EPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1))) | \
(EPWM_OUTPUT_HIGH << (u32ChannelNum << 1UL << EPWM_WGCTL0_ZPCTL0_Pos));

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@ -195,10 +195,10 @@ static void pwmout_config(pwmout_t *obj, int start)
// NOTE: Support period < 1s
// NOTE: ARM mbed CI test fails due to first PWM pulse error. Workaround by:
// 1. Inverse duty cycle (100 - duty)
// 1. Inverse duty cycle (10000 - duty)
// 2. Inverse PWM output polarity
// This trick is here to pass ARM mbed CI test. First PWM pulse error still remains.
EPWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 100 - obj->pulsewidth_us * 100 / obj->period_us, obj->period_us);
EPWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 10000 - obj->pulsewidth_us * 10000 / obj->period_us, obj->period_us);
pwm_base->POLCTL |= 1 << (EPWM_POLCTL_PINV0_Pos + chn);
if (start) {

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@ -97,7 +97,7 @@ uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u
* - PWM1 : PWM Group 1
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%...
* @return Nearest frequency clock in nano second
* @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure PWM frequency may affect
* existing frequency of other channel.
@ -115,7 +115,7 @@ uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
* @param[in] pwm The base address of PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency = u32Frequency / u32Frequency2
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%...
* @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2
* @return Nearest frequency clock in nano second
* @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
@ -178,7 +178,7 @@ uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
PWM_SET_CNR(pwm, u32ChannelNum, --u16CNR);
if(u32DutyCycle)
{
PWM_SET_CMR(pwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1) / 100 - 1);
PWM_SET_CMR(pwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1) / 10000 - 1);
(pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2));
(pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << (u32ChannelNum * 2 + PWM_WGCTL0_PRDPCTL0_Pos));
(pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2));

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@ -195,7 +195,7 @@ static void pwmout_config(pwmout_t *obj)
uint32_t chn = NU_MODSUBINDEX(obj->pwm);
// NOTE: Support period < 1s
//PWM_ConfigOutputChannel(pwm_base, chn, 1000 * 1000 / obj->period_us, obj->pulsewidth_us * 100 / obj->period_us);
PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, obj->pulsewidth_us * 100 / obj->period_us, obj->period_us);
PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, obj->pulsewidth_us * 10000 / obj->period_us, obj->period_us);
}
const PinMap *pwmout_pinmap()

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@ -28,7 +28,7 @@
* @param[in] pwm The base address of PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%...
* @return Nearest frequency clock in nano second
* @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
* existing frequency of other channel.
@ -46,7 +46,7 @@ uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
* @param[in] pwm The base address of PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%...
* @return Nearest frequency clock in nano second
* @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
* existing frequency of other channel.
@ -136,7 +136,7 @@ uint32_t PWM_ConfigOutputChannel2 (PWM_T *pwm,
*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk;
else {
*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk;
*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= ((u32DutyCycle * (u16CNR + 1) / 100 - 1) << PWM_DUTY_CM_Pos);
*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= ((u32DutyCycle * (u16CNR + 1) / 10000 - 1) << PWM_DUTY_CM_Pos);
}
*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CN_Msk;
*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u16CNR;

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@ -198,10 +198,10 @@ static void pwmout_config(pwmout_t *obj)
uint32_t chn = NU_MODSUBINDEX(obj->pwm);
// NOTE: Support period < 1s
// NOTE: ARM mbed CI test fails due to first PWM pulse error. Workaround by:
// 1. Inverse duty cycle (100 - duty)
// 1. Inverse duty cycle (10000 - duty)
// 2. Inverse PWM output polarity
// This trick is here to pass ARM mbed CI test. First PWM pulse error still remains.
PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 100 - (obj->pulsewidth_us * 100 / obj->period_us), obj->period_us);
PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 10000 - (obj->pulsewidth_us * 10000 / obj->period_us), obj->period_us);
}
const PinMap *pwmout_pinmap()

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@ -28,7 +28,7 @@
* @param[in] pwm The base address of PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%...
* @return Nearest frequency clock in nano second
* @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
* existing frequency of other channel.
@ -46,7 +46,7 @@ uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
* @param[in] pwm The base address of PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency = u32Frequency / u32Frequency2
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%...
* @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2
* @return Nearest frequency clock in nano second
* @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
@ -185,7 +185,7 @@ uint32_t PWM_ConfigOutputChannel2 (PWM_T *pwm,
if(u32DutyCycle == 0)
pwm->CMPDAT[u32ChannelNum] = 0;
else
pwm->CMPDAT[u32ChannelNum] = u32DutyCycle * (u16CNR + 1) / 100 - 1;
pwm->CMPDAT[u32ChannelNum] = u32DutyCycle * (u16CNR + 1) / 10000 - 1;
pwm->PERIOD[u32ChannelNum] = u16CNR;
return(i);

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@ -219,7 +219,7 @@ static void pwmout_config(pwmout_t *obj)
uint32_t chn = NU_MODSUBINDEX(obj->pwm);
// NOTE: Support period < 1s
//PWM_ConfigOutputChannel(pwm_base, chn, 1000 * 1000 / obj->period_us, obj->pulsewidth_us * 100 / obj->period_us);
PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, obj->pulsewidth_us * 100 / obj->period_us, obj->period_us);
PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, obj->pulsewidth_us * 10000 / obj->period_us, obj->period_us);
}
const PinMap *pwmout_pinmap()