mirror of https://github.com/ARMmbed/mbed-os.git
Support M480 PWM duty cycle range as 0 ~ 10000
parent
76b2902f48
commit
abdcc7b831
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@ -126,7 +126,7 @@ uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_
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* - EPWM1 : EPWM Group 1
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* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
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* @param[in] u32Frequency Target generator frequency
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* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
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* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 20000 means 20%...
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* @return Nearest frequency clock in nano second
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* @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect
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* existing frequency of other channel.
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@ -145,7 +145,7 @@ uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t
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* - EPWM1 : EPWM Group 1
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* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
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* @param[in] u32Frequency Target generator frequency / u32Frequency2
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* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
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* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%...
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* @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2
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* @return Nearest frequency clock in nano second
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* @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect
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@ -211,7 +211,7 @@ uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_
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u32CNR -= 1U;
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EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR);
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EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1U) / 100U);
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EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1U) / 10000U);
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(epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~(((1UL << EPWM_WGCTL0_PRDPCTL0_Pos) | (1UL << EPWM_WGCTL0_ZPCTL0_Pos)) << (u32ChannelNum << 1U))) | \
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((uint32_t)EPWM_OUTPUT_HIGH << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL0_ZPCTL0_Pos));
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@ -198,10 +198,10 @@ static void pwmout_config(pwmout_t *obj, int start)
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// NOTE: Support period < 1s
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// NOTE: ARM mbed CI test fails due to first PWM pulse error. Workaround by:
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// 1. Inverse duty cycle (100 - duty)
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// 1. Inverse duty cycle (10000 - duty)
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// 2. Inverse PWM output polarity
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// This trick is here to pass ARM mbed CI test. First PWM pulse error still remains.
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EPWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 100 - obj->pulsewidth_us * 100 / obj->period_us, obj->period_us);
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EPWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 10000 - obj->pulsewidth_us * 10000 / obj->period_us, obj->period_us);
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pwm_base->POLCTL |= 1 << (EPWM_POLCTL_PINV0_Pos + chn);
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if (start) {
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