Support M480 PWM duty cycle range as 0 ~ 10000

pull/14379/head
cyliangtw 2021-03-04 17:10:04 +08:00
parent 76b2902f48
commit abdcc7b831
2 changed files with 5 additions and 5 deletions

View File

@ -126,7 +126,7 @@ uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_
* - EPWM1 : EPWM Group 1
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 20000 means 20%...
* @return Nearest frequency clock in nano second
* @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect
* existing frequency of other channel.
@ -145,7 +145,7 @@ uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t
* - EPWM1 : EPWM Group 1
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency / u32Frequency2
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%...
* @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2
* @return Nearest frequency clock in nano second
* @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect
@ -211,7 +211,7 @@ uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_
u32CNR -= 1U;
EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR);
EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1U) / 100U);
EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1U) / 10000U);
(epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~(((1UL << EPWM_WGCTL0_PRDPCTL0_Pos) | (1UL << EPWM_WGCTL0_ZPCTL0_Pos)) << (u32ChannelNum << 1U))) | \
((uint32_t)EPWM_OUTPUT_HIGH << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL0_ZPCTL0_Pos));

View File

@ -198,10 +198,10 @@ static void pwmout_config(pwmout_t *obj, int start)
// NOTE: Support period < 1s
// NOTE: ARM mbed CI test fails due to first PWM pulse error. Workaround by:
// 1. Inverse duty cycle (100 - duty)
// 1. Inverse duty cycle (10000 - duty)
// 2. Inverse PWM output polarity
// This trick is here to pass ARM mbed CI test. First PWM pulse error still remains.
EPWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 100 - obj->pulsewidth_us * 100 / obj->period_us, obj->period_us);
EPWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 10000 - obj->pulsewidth_us * 10000 / obj->period_us, obj->period_us);
pwm_base->POLCTL |= 1 << (EPWM_POLCTL_PINV0_Pos + chn);
if (start) {