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[DISCO_F746NG] Update STM32CubeF7 to V1.0.1

pull/1289/head
bcostm 2015-08-11 12:04:45 +02:00
parent a1bd132fc1
commit 03bd5dbd8f
127 changed files with 832 additions and 639 deletions
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26
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/Release_Notes_stm32f7xx_hal.html
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31
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32_hal_legacy.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
@ -325,6 +325,11 @@
#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
#endif
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
/**
* @}
*/
@ -394,9 +399,16 @@
#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSISTIONS
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSISTIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSISTIONS
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
/* The following 3 definition have also been present in a temporary version of lptim.h */
/* They need to be renamed also to the right name, just in case */
#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
/**
* @}
@ -525,9 +537,17 @@
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
/**
* @}
@ -566,6 +586,7 @@
#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
/**

26
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@ -64,12 +64,15 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup HAL_Private_Constants
* @{
*/
/**
* @brief STM32F7xx HAL Driver version number V1.0.0
* @brief STM32F7xx HAL Driver version number V1.0.1
*/
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __STM32F7xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
@ -77,19 +80,28 @@
|(__STM32F7xx_HAL_VERSION_RC))
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @addtogroup HAL_Private_Variables
* @{
*/
static __IO uint32_t uwTick;
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup HAL_Private_Functions HAL Private Functions
/** @defgroup HAL_Exported_Functions HAL Exported Functions
* @{
*/
/** @defgroup HAL_Group1 Initialization and de-initialization Functions
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
* @brief Initialization and de-initialization functions
*
@verbatim
@ -243,7 +255,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
* @}
*/
/** @defgroup HAL_Group2 HAL Control functions
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
* @brief HAL Control functions
*
@verbatim

54
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
@ -58,7 +58,10 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup HAL_Exported_Macros HAL Exported Macros
* @{
*/
/** @brief Freeze/Unfreeze Peripherals in Debug mode
*/
#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
@ -122,17 +125,30 @@
#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\
SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\
}while(0);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
* @{
*/
/** @addtogroup HAL_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(__IO uint32_t Delay);
@ -152,8 +168,30 @@ void HAL_EnableCompensationCell(void);
void HAL_DisableCompensationCell(void);
void HAL_EnableFMCMemorySwapping(void);
void HAL_DisableFMCMemorySwapping(void);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup HAL_Private_Variables HAL Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup HAL_Private_Constants HAL Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and de-initialization functions

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of ADC HAL extension module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention

5
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.c
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@ -2,10 +2,9 @@
******************************************************************************
* @file stm32f7xx_hal_can.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief CAN HAL module driver.
*
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
* + Initialization and de-initialization functions

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_can.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention

36
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.c
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@ -2,10 +2,9 @@
******************************************************************************
* @file stm32f7xx_hal_cec.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief CEC HAL module driver.
*
* This file provides firmware functions to manage the following
* functionalities of the High Definition Multimedia Interface
* Consumer Electronics Control Peripheral (CEC).
@ -25,24 +24,25 @@
(#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
(##) Enable the CEC interface clock.
(##) CEC pins configuration:
(+) Enable the clock for the CEC GPIOs.
(+) Configure these CEC pins as alternate function pull-up.
(+++) Enable the clock for the CEC GPIOs.
(+++) Configure these CEC pins as alternate function pull-up.
(##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
and HAL_CEC_Receive_IT() APIs):
(+) Configure the CEC interrupt priority.
(+) Enable the NVIC CEC IRQ handle.
(@) The specific CEC interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
and receive process.
(+++) Configure the CEC interrupt priority.
(+++) Enable the NVIC CEC IRQ handle.
(+++) The specific CEC interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
and receive process.
(#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
in case of Bit Rising Error, Error-Bit generation conditions, device logical
address and Listen mode in the hcec Init structure.
(#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
(@) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
[..]
(@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
by calling the customed HAL_CEC_MspInit() API.
@endverbatim
@ -272,7 +272,7 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
*
@verbatim
===============================================================================
##### I/O operation functions #####
##### IO operation functions #####
===============================================================================
This subsection provides a set of functions allowing to manage the CEC data transfers.
@ -368,7 +368,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationA
{
if(Timeout != HAL_MAX_DELAY)
{
if((HAL_GetTick() - tickstart) > Timeout)
if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
{
hcec->State = HAL_CEC_STATE_TIMEOUT;
/* Process Unlocked */
@ -426,7 +426,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationA
{
if(Timeout != HAL_MAX_DELAY)
{
if((HAL_GetTick() - tickstart) > Timeout)
if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
{
hcec->State = HAL_CEC_STATE_ERROR;
__HAL_UNLOCK(hcec);
@ -498,10 +498,10 @@ HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint3
{
if(Timeout != HAL_MAX_DELAY)
{
if((HAL_GetTick() - tickstart) > Timeout)
if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
{
hcec->State = HAL_CEC_STATE_TIMEOUT;
__HAL_UNLOCK(hcec);
__HAL_UNLOCK(hcec);
return HAL_TIMEOUT;
}
}

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cec.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention

24
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cortex.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@ -26,7 +26,7 @@
function according to the following table.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
(#) please refer to programing manual for details in how to configure priority.
(#) please refer to programming manual for details in how to configure priority.
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
@ -297,15 +297,15 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = (MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
(MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
(MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
(MPU_Init->IsShareable << MPU_RASR_S_Pos) |
(MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
(MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
(MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
(MPU_Init->Size << MPU_RASR_SIZE_Pos) |
(MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
else
{

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cortex.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
@ -269,7 +269,7 @@ typedef struct
* @param __VALUE__: 8-bit value to be stored in the ID register
* @retval None
*/
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)))
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)))
/**
* @brief Returns the 8-bit data stored in the Independent Data(ID) register.

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Extended CRC HAL module driver.
*
* This file provides firmware functions to manage the following

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of CRC HAL extension module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief CRYP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:

12
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
@ -68,10 +68,10 @@
typedef struct
{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
This parameter can be a value of @ref CRYP CRYP_Data_Type */
This parameter can be a value of @ref CRYP_Data_Type */
uint32_t KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit key length.
This parameter can be a value of @ref CRYP CRYP_Key_Size */
This parameter can be a value of @ref CRYP_Key_Size */
uint8_t* pKey; /*!< The key used for encryption/decryption */
@ -177,7 +177,7 @@ typedef struct
* @{
*/
/** @defgroup CRYP_Exported_Constants_Group1 CRYP CRYP_Key_Size
/** @defgroup CRYP_Key_Size CRYP Key Size
* @{
*/
#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000)
@ -187,7 +187,7 @@ typedef struct
* @}
*/
/** @defgroup CRYP_Exported_Constants_Group2 CRYP CRYP_Data_Type
/** @defgroup CRYP_Data_Type CRYP Data Type
* @{
*/
#define CRYP_DATATYPE_32B ((uint32_t)0x00000000)

14
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Extended CRYP HAL module driver
* This file provides firmware functions to manage the following
* functionalities of CRYP extension peripheral:
@ -20,7 +20,7 @@
(##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())
(+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
(+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
(+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
(##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA())
(+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
(+++) Configure and enable two DMA streams one for managing data transfer from
@ -59,10 +59,10 @@
authentication messages.
Call those functions after the processing ones (polling, interrupt or DMA).
e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data
then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message
@note: For CCM Encrypt/Decrypt API's, only DataType = 8-bit is supported by this version.
@note: The HAL_CRYPEx_AESGCM_xxxx() implementation is limited to 32bits inputs data length
(Plain/Cyphertext, Header) compared with GCM standards specifications (800-38D).
then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message
-@- For CCM Encrypt/Decrypt API's, only DataType = 8-bit is supported by this version.
-@- The HAL_CRYPEx_AESGCM_xxxx() implementation is limited to 32bits inputs data length
(Plain/Cyphertext, Header) compared with GCM standards specifications (800-38D).
(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
@endverbatim

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of CRYP HAL Extension module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Extended DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief DCMI HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Digital Camera Interface (DCMI) peripheral:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of DCMI HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief DCMI Extension HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DCMI extension peripheral:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of DCMI Extension HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_def.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_def.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma2d.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief DMA2D HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the DMA2D peripheral:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma2d.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of DMA2D HAL module.
******************************************************************************
* @attention

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
@ -15,7 +15,7 @@
==============================================================================
[..]
The DMA Extension HAL driver can be used as follows:
(#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
(+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_eth.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief ETH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Ethernet (ETH) peripheral:

14
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_eth.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of ETH HAL module.
******************************************************************************
* @attention
@ -64,8 +64,6 @@
((SPEED) == ETH_SPEED_100M))
#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
((MODE) == ETH_MODE_HALFDUPLEX))
#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
((MODE) == ETH_MODE_HALFDUPLEX))
#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
((MODE) == ETH_RXINTERRUPT_MODE))
#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
@ -1257,10 +1255,10 @@ typedef struct
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:

12
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
@ -191,7 +191,13 @@ typedef struct
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
/**
* @brief Get the FLASH Latency.
* @retval FLASH Latency
* The value of this parameter depend on device used within the same series
*/
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
/**
* @brief Enable the FLASH prefetch buffer.
* @retval none

34
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extension peripheral:
@ -126,7 +126,7 @@ static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);
static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);
static uint32_t FLASH_OB_GetUser(void);
static uint32_t FLASH_OB_GetWRP(void);
static FlagStatus FLASH_OB_GetRDP(void);
static uint8_t FLASH_OB_GetRDP(void);
static uint32_t FLASH_OB_GetBOR(void);
static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption);
@ -727,18 +727,28 @@ static uint32_t FLASH_OB_GetWRP(void)
/**
* @brief Returns the FLASH Read Protection level.
* @retval FlagStatus FLASH ReadOut Protection Status:
* - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
* - RESET, when OB_RDP_Level_0 is set
* This parameter can be one of the following values:
* @arg OB_RDP_LEVEL_0: No protection
* @arg OB_RDP_LEVEL_1: Read protection of the memory
* @arg OB_RDP_LEVEL_2: Full chip protection
*/
static FlagStatus FLASH_OB_GetRDP(void)
static uint8_t FLASH_OB_GetRDP(void)
{
FlagStatus readstatus = RESET;
if (((uint16_t)(FLASH->OPTCR & 0xFF00)) != (uint16_t)OB_RDP_LEVEL_0)
{
readstatus = SET;
}
uint8_t readstatus = OB_RDP_LEVEL_0;
if (((FLASH->OPTCR & FLASH_OPTCR_RDP) >> 8) == OB_RDP_LEVEL_0)
{
readstatus = OB_RDP_LEVEL_0;
}
else if (((FLASH->OPTCR & FLASH_OPTCR_RDP) >> 8) == OB_RDP_LEVEL_2)
{
readstatus = OB_RDP_LEVEL_2;
}
else
{
readstatus = OB_RDP_LEVEL_1;
}
return readstatus;
}

14
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of FLASH HAL Extension module.
******************************************************************************
* @attention
@ -163,9 +163,9 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
* @{
*/
#define OB_RDP_LEVEL_0 ((uint32_t)0xAA00)
#define OB_RDP_LEVEL_1 ((uint32_t)0x5500)
/*#define OB_RDP_LEVEL_2 ((uint32_t)0xCC)*/ /*!< Warning: When enabling read protection level 2
#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
#define OB_RDP_LEVEL_1 ((uint8_t)0x55)
#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
it s no more possible to go back to level 1 or 0 */
/**
* @}
@ -388,8 +388,8 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
((ADDRESS) == OB_BOOTADDR_SRAM2))
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
((LEVEL) == OB_RDP_LEVEL_1))/*||\
((LEVEL) == OB_RDP_LEVEL_2))*/
((LEVEL) == OB_RDP_LEVEL_1) ||\
((LEVEL) == OB_RDP_LEVEL_2))
#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_gpio.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_gpio.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_gpio_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention

78
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hash.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral:
@ -175,7 +175,7 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
buffersize = hhash->Init.KeySize;
}
/* Configure the number of valid bits in last word of the message */
HASH->STR |= 8 * (buffersize % 4);
MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));
/* Set the HASH DMA transfer complete */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
@ -713,10 +713,14 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
/* Check the parameters */
assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size));
/* Process Locked */
__HAL_LOCK(hhash);
@ -790,15 +794,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
/* Process Locked */
__HAL_LOCK(hhash);
if(hhash->HashITCounter == 0)
{
hhash->HashITCounter = 1;
}
else
{
hhash->HashITCounter = 0;
}
if(hhash->State == HAL_HASH_STATE_READY)
{
/* Change the HASH state */
@ -818,6 +814,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
HASH->CR |= HASH_CR_INIT;
}
/* Reset interrupt counter */
hhash->HashITCounter = 0;
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
@ -850,11 +849,18 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
hhash->State = HAL_HASH_STATE_READY;
/* Call digest computation complete callback */
HAL_HASH_DgstCpltCallback(hhash);
/* Process Unlocked */
__HAL_UNLOCK(hhash);
/* Return function status */
return HAL_OK;
}
}
if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
if(hhash->HashInCount > 64)
if(hhash->HashInCount >= 68)
{
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Write the Input block in the Data IN register */
@ -875,8 +881,11 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
}
else
{
hhash->HashInCount -= 64;
hhash->HashInCount = 0;
hhash->pHashInBuffPtr+= hhash->HashInCount;
}
/* Set Interrupt counter */
hhash->HashITCounter = 1;
}
else
{
@ -900,6 +909,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
{
inputcounter = (inputcounter+4-inputcounter%4);
}
else if ((inputcounter < 4) && (inputcounter != 0))
{
inputcounter = 4;
}
/* Write the Input block in the Data IN register */
for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
@ -911,9 +924,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
__HAL_HASH_START_DIGEST();
/* Reset buffer counter */
hhash->HashInCount = 0;
/* Call Input data transfer complete callback */
HAL_HASH_InCpltCallback(hhash);
}
/* Call Input data transfer complete callback */
HAL_HASH_InCpltCallback(hhash);
}
/* Process Unlocked */
@ -944,14 +957,6 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
/* Process Locked */
__HAL_LOCK(hhash);
if(hhash->HashITCounter == 0)
{
hhash->HashITCounter = 1;
}
else
{
hhash->HashITCounter = 0;
}
if(hhash->State == HAL_HASH_STATE_READY)
{
/* Change the HASH state */
@ -971,6 +976,9 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
HASH->CR |= HASH_CR_INIT;
}
/* Reset interrupt counter */
hhash->HashITCounter = 0;
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
@ -1004,11 +1012,17 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
hhash->State = HAL_HASH_STATE_READY;
/* Call digest computation complete callback */
HAL_HASH_DgstCpltCallback(hhash);
/* Process Unlocked */
__HAL_UNLOCK(hhash);
/* Return function status */
return HAL_OK;
}
}
if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
if(hhash->HashInCount > 64)
if(hhash->HashInCount >= 68)
{
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Write the Input block in the Data IN register */
@ -1029,8 +1043,11 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
}
else
{
hhash->HashInCount -= 64;
hhash->HashInCount = 0;
hhash->pHashInBuffPtr+= hhash->HashInCount;
}
/* Set Interrupt counter */
hhash->HashITCounter = 1;
}
else
{
@ -1054,7 +1071,10 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
{
inputcounter = (inputcounter+4-inputcounter%4);
}
else if ((inputcounter < 4) && (inputcounter != 0))
{
inputcounter = 4;
}
/* Write the Input block in the Data IN register */
for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
{
@ -1065,9 +1085,9 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
__HAL_HASH_START_DIGEST();
/* Reset buffer counter */
hhash->HashInCount = 0;
/* Call Input data transfer complete callback */
HAL_HASH_InCpltCallback(hhash);
}
/* Call Input data transfer complete callback */
HAL_HASH_InCpltCallback(hhash);
}
/* Process Unlocked */

18
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hash.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
@ -68,7 +68,7 @@
typedef struct
{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
This parameter can be a value of @ref HASH DataType */
This parameter can be a value of @ref HASH_Data_Type */
uint32_t KeySize; /*!< The key size is used only in HMAC operation */
@ -173,7 +173,7 @@ typedef struct
* @}
*/
/** @defgroup HASH_Exported_Constants_Group3 HASH DataType
/** @defgroup HASH_Data_Type HASH Data Type
* @{
*/
#define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */
@ -209,8 +209,8 @@ typedef struct
/** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition
* @{
*/
#define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */
#define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */
#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
/**
* @}
*/
@ -240,7 +240,8 @@ typedef struct
* @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_HASH_GET_FLAG(__FLAG__) ((HASH->SR & (__FLAG__)) == (__FLAG__))
#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
((HASH->SR & (__FLAG__)) == (__FLAG__)))
/**
* @brief Enable the multiple DMA mode.
@ -414,6 +415,9 @@ void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
#define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \
((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))
#define IS_HASH_SHA1_BUFFER_SIZE(__SIZE__) ((((__SIZE__)%4) != 0)? 0U: 1U)
/**
* @}

74
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hash_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief HASH HAL Extension module driver.
* This file provides firmware functions to manage the following
* functionalities of HASH peripheral:
@ -264,7 +264,7 @@ static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma)
buffersize = hhash->Init.KeySize;
}
/* Configure the number of valid bits in last word of the message */
HASH->STR |= 8 * (buffersize % 4);
MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));
/* Set the HASH DMA transfer complete */
hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
@ -924,15 +924,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
/* Process Locked */
__HAL_LOCK(hhash);
if(hhash->HashITCounter == 0)
{
hhash->HashITCounter = 1;
}
else
{
hhash->HashITCounter = 0;
}
if(hhash->State == HAL_HASH_STATE_READY)
{
/* Change the HASH state */
@ -951,7 +943,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
the message digest of a new message */
HASH->CR |= HASH_CR_INIT;
}
/* Reset interrupt counter */
hhash->HashITCounter = 0;
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
@ -976,11 +969,16 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
hhash->State = HAL_HASH_STATE_READY;
/* Call digest computation complete callback */
HAL_HASH_DgstCpltCallback(hhash);
/* Process Unlocked */
__HAL_UNLOCK(hhash);
/* Return function status */
return HAL_OK;
}
}
if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
if(hhash->HashInCount > 64)
if(hhash->HashInCount >= 68)
{
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Write the Input block in the Data IN register */
@ -1000,8 +998,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
}
else
{
hhash->HashInCount -= 64;
hhash->HashInCount = 0;
hhash->pHashInBuffPtr+= hhash->HashInCount;
}
/* Set Interrupt counter */
hhash->HashITCounter = 1;
}
else
{
@ -1025,7 +1026,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
{
inputcounter = (inputcounter+4-inputcounter%4);
}
else if ((inputcounter < 4) && (inputcounter != 0))
{
inputcounter = 4;
}
/* Write the Input block in the Data IN register */
for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
{
@ -1036,9 +1040,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
__HAL_HASH_START_DIGEST();
/* Reset buffer counter */
hhash->HashInCount = 0;
/* Call Input data transfer complete callback */
HAL_HASH_InCpltCallback(hhash);
}
/* Call Input data transfer complete callback */
HAL_HASH_InCpltCallback(hhash);
}
/* Process Unlocked */
@ -1068,15 +1072,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
/* Process Locked */
__HAL_LOCK(hhash);
if(hhash->HashITCounter == 0)
{
hhash->HashITCounter = 1;
}
else
{
hhash->HashITCounter = 0;
}
if(hhash->State == HAL_HASH_STATE_READY)
{
/* Change the HASH state */
@ -1096,6 +1092,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
HASH->CR |= HASH_CR_INIT;
}
/* Reset interrupt counter */
hhash->HashITCounter = 0;
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
@ -1120,11 +1119,17 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
hhash->State = HAL_HASH_STATE_READY;
/* Call digest computation complete callback */
HAL_HASH_DgstCpltCallback(hhash);
/* Process Unlocked */
__HAL_UNLOCK(hhash);
/* Return function status */
return HAL_OK;
}
}
if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
if(hhash->HashInCount > 64)
if(hhash->HashInCount >= 68)
{
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Write the Input block in the Data IN register */
@ -1145,8 +1150,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
}
else
{
hhash->HashInCount -= 64;
hhash->HashInCount = 0;
hhash->pHashInBuffPtr+= hhash->HashInCount;
}
/* Set Interrupt counter */
hhash->HashITCounter = 1;
}
else
{
@ -1170,6 +1178,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
{
inputcounter = (inputcounter+4-inputcounter%4);
}
else if ((inputcounter < 4) && (inputcounter != 0))
{
inputcounter = 4;
}
/* Write the Input block in the Data IN register */
for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
@ -1181,9 +1193,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
__HAL_HASH_START_DIGEST();
/* Reset buffer counter */
hhash->HashInCount = 0;
/* Call Input data transfer complete callback */
HAL_HASH_InCpltCallback(hhash);
}
/* Call Input data transfer complete callback */
HAL_HASH_InCpltCallback(hhash);
}
/* Process Unlocked */

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hash_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of HASH HAL Extension module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hcd.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief HCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hcd.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2c.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2c.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2c_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2c_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of I2C HAL Extension module.
******************************************************************************
* @attention

20
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2s.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
@ -522,13 +522,17 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
}
}
/* Wait until Busy flag is reset */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
/* Check if Slave mode is selected */
if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
{
/* Set the error code and execute error callback*/
hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
HAL_I2S_ErrorCallback(hi2s);
return HAL_TIMEOUT;
/* Wait until Busy flag is reset */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
{
/* Set the error code and execute error callback*/
hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
HAL_I2S_ErrorCallback(hi2s);
return HAL_TIMEOUT;
}
}
hi2s->State = HAL_I2S_STATE_READY;

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2s.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention

13
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_irda.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA SIR ENDEC block (IrDA):
@ -858,10 +858,11 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
{
/* The Lock is not implemented on this API to allow the user application
to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
*/
to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
the stream and the corresponding call back is executed. */
/* Disable the UART Tx/Rx DMA requests */
hirda->Instance->CR3 &= ~USART_CR3_DMAT;

8
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_irda.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
@ -77,8 +77,8 @@ typedef struct
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref IRDA_Mode */
uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref IRDA_Transfer_Mode */
uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
to achieve low-power frequency.

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_irda_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of IRDA HAL Extension module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_iwdg.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief IWDG HAL module driver.
*
* This file provides firmware functions to manage the following

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_iwdg.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention

5
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.c
View File

@ -2,10 +2,9 @@
******************************************************************************
* @file stm32f7xx_hal_lptim.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief LPTIM HAL module driver.
*
* This file provides firmware functions to manage the following
* functionalities of the Low Power Timer (LPTIM) peripheral:
* + Initialization and de-initialization functions.

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_lptim.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of LPTIM HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_ltdc.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief LTDC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the LTDC peripheral:

8
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_ltdc.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of LTDC HAL module.
******************************************************************************
* @attention
@ -136,10 +136,10 @@ typedef struct
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t WindowY0; /*!< Configures the Window vertical Start Position.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */
uint32_t PixelFormat; /*!< Specifies the pixel format.
This parameter can be one of value of @ref LTDC_Pixelformat */

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_nand.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_nand.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_nor.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_nor.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pcd.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pcd.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pcd_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pcd_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pwr.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pwr.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pwr_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of PWR extension peripheral:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pwr_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention

87
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c
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@ -2,10 +2,9 @@
******************************************************************************
* @file stm32f7xx_hal_qspi.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief QSPI HAL module driver.
*
* This file provides firmware functions to manage the following
* functionalities of the QuadSPI interface (QSPI).
* + Initialization and de-initialization functions
@ -26,13 +25,13 @@
======================
[..]
(#) As prerequisite, fill in the HAL_QSPI_MspInit() :
(+) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
(+) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
(+) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
(+) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
(+) If interrupt mode is used, enable and configure QuadSPI global
(++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
(++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
(++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
(++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
(++) If interrupt mode is used, enable and configure QuadSPI global
interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
(+) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
(++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
@ -44,31 +43,31 @@
[..]
(#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
functions :
(+) Instruction phase : the mode used and if present the instruction opcode.
(+) Address phase : the mode used and if present the size and the address value.
(+) Alternate-bytes phase : the mode used and if present the size and the alternate
(++) Instruction phase : the mode used and if present the instruction opcode.
(++) Address phase : the mode used and if present the size and the address value.
(++) Alternate-bytes phase : the mode used and if present the size and the alternate
bytes values.
(+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
(+) Data phase : the mode used and if present the number of bytes.
(+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
(++) Data phase : the mode used and if present the number of bytes.
(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
if activated.
(+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
(#) If no data is required for the command, it is sent directly to the memory :
(+) In polling mode, the output of the function is done when the transfer is complete.
(+) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
(++) In polling mode, the output of the function is done when the transfer is complete.
(++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
(#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
HAL_QSPI_Transmit_IT() after the command configuration :
(+) In polling mode, the output of the function is done when the transfer is complete.
(+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
(++) In polling mode, the output of the function is done when the transfer is complete.
(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
(+) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
(++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
(#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
HAL_QSPI_Receive_IT() after the command configuration :
(+) In polling mode, the output of the function is done when the transfer is complete.
(+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
(++) In polling mode, the output of the function is done when the transfer is complete.
(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
(+) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
(++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
*** Auto-polling functional mode ***
@ -76,37 +75,37 @@
[..]
(#) Configure the command sequence and the auto-polling functional mode using the
HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
(+) Instruction phase : the mode used and if present the instruction opcode.
(+) Address phase : the mode used and if present the size and the address value.
(+) Alternate-bytes phase : the mode used and if present the size and the alternate
(++) Instruction phase : the mode used and if present the instruction opcode.
(++) Address phase : the mode used and if present the size and the address value.
(++) Alternate-bytes phase : the mode used and if present the size and the alternate
bytes values.
(+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
(+) Data phase : the mode used.
(+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
(++) Data phase : the mode used.
(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
if activated.
(+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
(+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
(++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
the polling interval and the automatic stop activation.
(#) After the configuration :
(+) In polling mode, the output of the function is done when the status match is reached. The
(++) In polling mode, the output of the function is done when the status match is reached. The
automatic stop is activated to avoid an infinite loop.
(+) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
(++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
*** Memory-mapped functional mode ***
=====================================
[..]
(#) Configure the command sequence and the memory-mapped functional mode using the
HAL_QSPI_MemoryMapped() functions :
(+) Instruction phase : the mode used and if present the instruction opcode.
(+) Address phase : the mode used and the size.
(+) Alternate-bytes phase : the mode used and if present the size and the alternate
(++) Instruction phase : the mode used and if present the instruction opcode.
(++) Address phase : the mode used and the size.
(++) Alternate-bytes phase : the mode used and if present the size and the alternate
bytes values.
(+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
(+) Data phase : the mode used.
(+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
(++) Data phase : the mode used.
(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
if activated.
(+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
(+) The timeout activation and the timeout period.
(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
(++) The timeout activation and the timeout period.
(#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
@ -121,7 +120,7 @@
====================================================
[..]
(#) Workarounds Implemented inside HAL Driver
(+) Extra data written in the FIFO at the end of a read transfer
(++) Extra data written in the FIFO at the end of a read transfer
@endverbatim
******************************************************************************
@ -376,7 +375,7 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
*
@verbatim
===============================================================================
##### I/O operation functions #####
##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to :

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_qspi.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of QSPI HAL module.
******************************************************************************
* @attention

8
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rcc.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@ -48,8 +48,8 @@
after the clock enable bit is set on the hardware register
[..]
Workarounds:
(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
Implemented Workaround:
(+) For AHB & APB peripherals, a dummy read to the peripheral register has been
inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
@endverbatim

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rcc.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention

79
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rcc_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Extension RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
@ -200,27 +200,27 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*------------------------------------ RTC configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait for Backup domain Write protection disable */
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified */
if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
{
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait for Backup domain Write protection disable */
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
@ -230,25 +230,26 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg0;
}
/* If LSE is selected as RTC clock source, wait for LSE reactivation */
if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
/* If LSE is selected as RTC clock source, wait for LSE reactivation */
if (HAL_IS_BIT_SET(tmpreg0, RCC_BDCR_LSERDY))
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
return HAL_TIMEOUT;
}
}
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
/*------------------------------------ TIM configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
{
@ -465,7 +466,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
}
@ -502,7 +503,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
}
@ -517,7 +518,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
}
@ -594,7 +595,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
/* Configure the PLLSAI division factors */
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) × (PLLI2SN/PLLM) */
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
}

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rcc_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rng.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rng.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention

44
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rtc.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
@ -62,7 +62,7 @@
accesses.
[..] To enable access to the RTC Domain and RTC registers, proceed as follows:
(+) Enable the Power Controller (PWR) APB1 interface clock using the
__PWR_CLK_ENABLE() function.
__HAL_RCC_PWR_CLK_ENABLE() function.
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
(+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
(+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
@ -547,16 +547,23 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
/**
* @brief Gets RTC current time.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param sTime: Pointer to Time structure
* @param hrtc: RTC handle
* @param sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned
* with input format (BIN or BCD), also SubSeconds field returning the
* RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
* factor to be used for second fraction ratio computation.
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
* @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
* in the higher-order calendar shadow registers to ensure consistency between the time and date values.
* Reading RTC current time locks the values in calendar shadow registers until Current date is read.
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
* value in second fraction ratio with time unit following generic formula:
* Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
* This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
* @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
* in the higher-order calendar shadow registers to ensure consistency between the time and date values.
* Reading RTC current time locks the values in calendar shadow registers until Current date is read
* to ensure consistency between the time and date values.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
@ -597,8 +604,8 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
* @param sDate: Pointer to date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@ -706,8 +713,11 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
* @param sDate: Pointer to Date structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
* in the higher-order calendar shadow registers to ensure consistency between the time and date values.
* Reading RTC current time locks the values in calendar shadow registers until Current date is read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@ -1237,8 +1247,8 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
* @arg RTC_ALARM_B: AlarmB
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rtc.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention

54
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rtc_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
@ -965,21 +965,25 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
/*Check RTC WUTWF flag is reset only when wake up timer enabled*/
if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
{
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_TIMEOUT;
hrtc->State = HAL_RTC_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_TIMEOUT;
}
return HAL_TIMEOUT;
}
}
}
/* Clear the Wakeup Timer clock source bits in CR register */
@ -1034,21 +1038,25 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
/*Check RTC WUTWF flag is reset only when wake up timer enabled*/
if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
{
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_TIMEOUT;
hrtc->State = HAL_RTC_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_TIMEOUT;
}
return HAL_TIMEOUT;
}
}
}
/* Configure the Wakeup Timer counter */

43
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rtc_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of RTC HAL Extension module.
******************************************************************************
* @attention
@ -186,9 +186,9 @@ typedef struct
/** @defgroup RTCEx_TimeStamp_Pin_Selection RTCEx TimeStamp Pin Selection
* @{
*/
#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)
#define RTC_TIMESTAMPPIN_PI8 ((uint32_t)0x00000002)
#define RTC_TIMESTAMPPIN_PC1 ((uint32_t)0x00000004)
#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)
#define RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00000002)
#define RTC_TIMESTAMPPIN_POS2 ((uint32_t)0x00000004)
/**
* @}
*/
@ -431,7 +431,7 @@ typedef struct
* @arg RTC_FLAG_WUTF
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
* @brief Enable the RTC Tamper1 input detection.
@ -488,7 +488,7 @@ typedef struct
*/
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \
((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \
(((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))
(((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))
/**
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
@ -525,7 +525,7 @@ typedef struct
* @arg RTC_FLAG_TAMP3F: Tamper3 flag
* @retval None
*/
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
* @brief Enable the RTC TimeStamp peripheral.
@ -601,7 +601,7 @@ typedef struct
* @arg RTC_FLAG_TSOVF
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
* @brief Enable the RTC internal TimeStamp peripheral.
@ -819,7 +819,7 @@ typedef struct
* @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
* @retval Line Status.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
* @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
@ -930,7 +930,18 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
* @{
*/
/* Masks Definition */
#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT))
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
* @{
*/
@ -945,11 +956,13 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
#define IS_RTC_BKP(__BKP__) ((__BKP__) < (uint32_t) RTC_BKP_NUMBER)
#define IS_TIMESTAMP_EDGE(__EDGE__) (((__EDGE__) == RTC_TIMESTAMPEDGE_RISING) || \
((__EDGE__) == RTC_TIMESTAMPEDGE_FALLING))
#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & (uint32_t)0xFFFFFFD6) == 0x00) && ((__TAMPER__) != (uint32_t)RESET))
#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)0xFFB6FFFB) == 0x00) && ((__INTERRUPT__) != (uint32_t)RESET))
#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXE))) == 0x00) && ((__TAMPER__) != (uint32_t)RESET))
#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXIE)) == 0x00) && ((__INTERRUPT__) != (uint32_t)RESET))
#define IS_RTC_TIMESTAMP_PIN(__PIN__) (((__PIN__) == RTC_TIMESTAMPPIN_DEFAULT) || \
((__PIN__) == RTC_TIMESTAMPPIN_PI8) || \
((__PIN__) == RTC_TIMESTAMPPIN_PC1))
((__PIN__) == RTC_TIMESTAMPPIN_POS1) || \
((__PIN__) == RTC_TIMESTAMPPIN_POS2))
#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sai.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief SAI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Audio Interface (SAI) peripheral:
@ -413,7 +413,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
((hsai->FrameInit.ActiveFrameLength - 1) << 8));
/* SAI Block_x SLOT Configuration ------------------------------------------*/
/* This register has no meaning in AC’97 and SPDIF audio protocol */
/* This register has no meaning in AC 97 and SPDIF audio protocol */
hsai->Instance->SLOTR&= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \
SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN ));

8
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sai.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of SAI HAL module.
******************************************************************************
* @attention
@ -101,7 +101,7 @@ typedef struct
uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
This parameter can be a value of @ref SAI_Block_NoDivider
@note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length
@note If bit NODIV in the SAI_xCR1 register is cleared, the frame length
should be aligned to a number equal to a power of 2, from 8 to 256.
If bit NODIV in the SAI_xCR1 register is set, the frame length can
take any of the values without constraint since the input clock of
@ -152,7 +152,7 @@ typedef struct
uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
This parameter must be a number between Min_Data = 8 and Max_Data = 256.
@note: If master clock MCLK_x pin is declared as an output, the frame length
@note If master clock MCLK_x pin is declared as an output, the frame length
should be aligned to a number equal to power of 2 in order to keep
in an audio frame, an integer number of MCLK pulses by bit Clock. */

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sai_ex.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief SAI Extension HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of SAI extension peripheral:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sai_ex.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of SAI Extension HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sd.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief SD card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sd.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of SD HAL module.
******************************************************************************
* @attention
@ -603,7 +603,7 @@ typedef enum
/**
* @brief Clear the SD's interrupt pending bits.
* @param __HANDLE__ : SD Handle
* @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sdram.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief SDRAM HAL module driver.
* This file provides a generic firmware to drive SDRAM memories mounted
* as external device.

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sdram.h
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief Header file of SDRAM HAL module.
******************************************************************************
* @attention

27
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_smartcard.c
* @author MCD Application Team
* @version V1.0.0
* @date 12-May-2015
* @version V1.0.1
* @date 25-June-2015
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
@ -29,9 +29,9 @@
and HAL_SMARTCARD_Receive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
(+++) Enable the NVIC USART IRQ handle.
(@) The specific USART interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
(+++) The specific USART interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
(##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
and HAL_SMARTCARD_Receive_DMA() APIs):
(+++) Declare a DMA handle structure for the Tx/Rx stream.
@ -49,8 +49,9 @@
in the hsc AdvancedInit structure.
(#) Initialize the SMARTCARD associated USART registers by calling
the HAL_SMARTCARD_Init() API.
the HAL_SMARTCARD_Init() API.
[..]
(@) HAL_SMARTCARD_Init() API also configure also the low level Hardware GPIO, CLOCK, CORTEX...etc) by
calling the customized HAL_SMARTCARD_MspInit() API.
@ -150,11 +151,13 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc);
(++) Parity: parity should be enabled,
Frame Length is fixed to 8 bits plus parity:
the USART frame format is given in the following table:
+---------------------------------------------------------------+
| M1M0 bits | PCE bit | USART frame |
|-----------------------|---------------------------------------|
| 01 | 1 | | SB | 8 bit data | PB | STB | |
+---------------------------------------------------------------+
(+++) +---------------------------------------------------------------+
(+++) | M1M0 bits | PCE bit | USART frame |
(+++) |-----------------------|---------------------------------------|
(+++) | 01 | 1 | | SB | 8 bit data | PB | STB | |
(+++) +---------------------------------------------------------------+
(++) Receiver/transmitter modes
(++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
(++) Prescaler value

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