diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/Release_Notes_stm32f7xx_hal.html b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/Release_Notes_stm32f7xx_hal.html
index 7ff6fa3a4b..0c78c59e5a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/Release_Notes_stm32f7xx_hal.html
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/Release_Notes_stm32f7xx_hal.html
@@ -676,6 +676,32 @@ Notes for STM32F7xx HAL Drivers
Update History
+V1.0.1 / 25-June-2015
+Main
+Changes - General updates
+to fix known defects and enhancements implementation
- HAL CRC update
- update __HAL_CRC_SET_IDR() macro implementation to use WRITE_REG() instead of MODIFY_REG()
- HAL CEC update
- update timeout management in HAL_CEC_Transmit() and HAL_CEC_Receive() functions
- HAL Cortex update
- update HAL_MPU_ConfigRegion() function to be misra compliant
- HAL ETH update
- Remove
+duplicated IS_ETH_DUPLEX_MODE() and IS_ETH_RX_MODE() macros
- Remove
+illegal space ETH_MAC_READCONTROLLER_FLUSHING macro
- Update
+ETH_MAC_READCONTROLLER_XXX defined values (XXX can be IDLE, READING_DATA and
+READING_STATUS)
- HAL FLASH update
- update FLASH_OB_GetRDP() function to return uint8_t instead of FlagStatus
- update OB_RDP_LEVELx definition
- add __HAL_FLASH_GET_LATENCY() macro
- HAL HASH update
- update
+HASH_DMAXferCplt() and HASHEx_DMAXferCplt() functions to properly
+configure the number of valid bits in last word of the message
- update HAL_HASH_SHA1_Accumulate() function to check on the length of the input buffer
- update
+HAL_HASH_MODE_Start_IT() functions (Mode stands for MD5, SHA1, SHA224 and SHA256 ) to :
- Fix processing
+fail for small input buffers
+
- to unlock
+the process and call return HAL_OK at the end of HASH processing to avoid
+incorrect repeating software
+
- properly to manage
+the HashITCounter efficiency
+
- Update to call the
+HAL_HASH_InCpltCallback() at the end of the complete buffer instead
+of
+every each 512 bits
- update HASH_IT_DINI and HASH_IT_DCI definition
- update __HAL_HASH_GET_FLAG() macro definition
- HAL I2S update
- update HAL_I2S_Transmit() function to ensure the waiting on Busy flag in case of slave mode selection
- HAL RTC update
- update HAL_RTCEx_SetWakeUpTimer() and HAL_RTCEx_SetWakeUpTimer_IT() functions to properly check on WUTWF flag
- rename RTC_TIMESTAMPPIN_PI8 define to RTC_TIMESTAMPPIN_POS1
- rename RTC_TIMESTAMPPIN_PC1 define to RTC_TIMESTAMPPIN_POS2
- update __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG() macro definition
- update __HAL_RTC_TAMPER_GET_IT() macro definition
- update __HAL_RTC_TAMPER_CLEAR_FLAG() macro definition
- update __HAL_RTC_TIMESTAMP_CLEAR_FLAG() macro definition
- update __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() macro definition
- add RTC_TAMPCR_TAMPXE and RTC_TAMPCR_TAMPXIE defines
- HAL SMARTCARD update
- add SMARTCARD_FLAG_IDLE, SMARTCARD_IT_IDLE and SMARTCARD_CLEAR_IDLEF defines
- HAL UART update
- update HAL_UART_DMAResume() function to clear overrun flag before resuming the Rx transfer
- update UART_FLAG_SBKF definition
- HAL USART update
- update HAL_USART_DMAResume() function to clear overrun flag before resuming the Rx transfer
- LL FMC update
- update NAND timing maximum values
- LL USB update
+
- USB_FlushTxFifo API:
+update to flush all Tx FIFO
+
- Update to use local
+variable in USB Host channel re-activation
+
V1.0.0 / 12-May-2015
Main
Changes - First official release for STM32F756xx/746xx/745xx
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32_hal_legacy.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32_hal_legacy.h
index 3bbff8fe49..c256044db0 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32_hal_legacy.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32_hal_legacy.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
@@ -325,6 +325,11 @@
#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
#endif
+
+#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
+
/**
* @}
*/
@@ -394,9 +399,16 @@
#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSISTIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSISTIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSISTIONS
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
/**
* @}
@@ -525,9 +537,17 @@
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
/**
* @}
@@ -566,6 +586,7 @@
#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
/**
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c
index 2f5bac5437..f610ac0dc8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@@ -64,12 +64,15 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @addtogroup HAL_Private_Constants
+ * @{
+ */
/**
- * @brief STM32F7xx HAL Driver version number V1.0.0
+ * @brief STM32F7xx HAL Driver version number V1.0.1
*/
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
-#define __STM32F7xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F7xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
@@ -77,19 +80,28 @@
|(__STM32F7xx_HAL_VERSION_RC))
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Private_Variables
+ * @{
+ */
static __IO uint32_t uwTick;
+/**
+ * @}
+ */
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup HAL_Private_Functions HAL Private Functions
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
* @{
*/
-/** @defgroup HAL_Group1 Initialization and de-initialization Functions
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
* @brief Initialization and de-initialization functions
*
@verbatim
@@ -243,7 +255,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
* @}
*/
-/** @defgroup HAL_Group2 HAL Control functions
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
* @brief HAL Control functions
*
@verbatim
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h
index ad974a2a10..eeb5448572 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
@@ -58,7 +58,10 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
-
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+ * @{
+ */
+
/** @brief Freeze/Unfreeze Peripherals in Debug mode
*/
#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
@@ -122,17 +125,30 @@
#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\
SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\
}while(0);
-
-
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
-
+/** @addtogroup HAL_Exported_Functions
+ * @{
+ */
+/** @addtogroup HAL_Exported_Functions_Group1
+ * @{
+ */
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
-
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group2
+ * @{
+ */
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(__IO uint32_t Delay);
@@ -152,8 +168,30 @@ void HAL_EnableCompensationCell(void);
void HAL_DisableCompensationCell(void);
void HAL_EnableFMCMemorySwapping(void);
void HAL_DisableFMCMemorySwapping(void);
+/**
+ * @}
+ */
-
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Variables HAL Private Variables
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Constants HAL Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.c
index 63eb07b6d7..f1a75f9056 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and de-initialization functions
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h
index 67d765feba..236178b07c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of ADC HAL extension module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.c
index ec0155c82c..b985e0ed12 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.h
index 0664b1d578..82cb5e3b02 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.c
index 9e4cab15d4..22e8c93f88 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.c
@@ -2,10 +2,9 @@
******************************************************************************
* @file stm32f7xx_hal_can.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief CAN HAL module driver.
- *
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
* + Initialization and de-initialization functions
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.h
index cdf5d25617..598cb9c84c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_can.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.c
index 539eba8670..7d896a6706 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.c
@@ -2,10 +2,9 @@
******************************************************************************
* @file stm32f7xx_hal_cec.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief CEC HAL module driver.
- *
* This file provides firmware functions to manage the following
* functionalities of the High Definition Multimedia Interface
* Consumer Electronics Control Peripheral (CEC).
@@ -25,24 +24,25 @@
(#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
(##) Enable the CEC interface clock.
(##) CEC pins configuration:
- (+) Enable the clock for the CEC GPIOs.
- (+) Configure these CEC pins as alternate function pull-up.
+ (+++) Enable the clock for the CEC GPIOs.
+ (+++) Configure these CEC pins as alternate function pull-up.
(##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
and HAL_CEC_Receive_IT() APIs):
- (+) Configure the CEC interrupt priority.
- (+) Enable the NVIC CEC IRQ handle.
- (@) The specific CEC interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
- and receive process.
+ (+++) Configure the CEC interrupt priority.
+ (+++) Enable the NVIC CEC IRQ handle.
+ (+++) The specific CEC interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
+ and receive process.
(#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
in case of Bit Rising Error, Error-Bit generation conditions, device logical
address and Listen mode in the hcec Init structure.
(#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
-
- (@) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+
+ [..]
+ (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
by calling the customed HAL_CEC_MspInit() API.
@endverbatim
@@ -272,7 +272,7 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
*
@verbatim
===============================================================================
- ##### I/O operation functions #####
+ ##### IO operation functions #####
===============================================================================
This subsection provides a set of functions allowing to manage the CEC data transfers.
@@ -368,7 +368,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationA
{
if(Timeout != HAL_MAX_DELAY)
{
- if((HAL_GetTick() - tickstart) > Timeout)
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
{
hcec->State = HAL_CEC_STATE_TIMEOUT;
/* Process Unlocked */
@@ -426,7 +426,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationA
{
if(Timeout != HAL_MAX_DELAY)
{
- if((HAL_GetTick() - tickstart) > Timeout)
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
{
hcec->State = HAL_CEC_STATE_ERROR;
__HAL_UNLOCK(hcec);
@@ -498,10 +498,10 @@ HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint3
{
if(Timeout != HAL_MAX_DELAY)
{
- if((HAL_GetTick() - tickstart) > Timeout)
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
{
hcec->State = HAL_CEC_STATE_TIMEOUT;
- __HAL_UNLOCK(hcec);
+ __HAL_UNLOCK(hcec);
return HAL_TIMEOUT;
}
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.h
index be1699c0dd..acd1ceb50e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cec.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c
index ddc1195c88..9a17168689 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cortex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@@ -26,7 +26,7 @@
function according to the following table.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
- (#) please refer to programing manual for details in how to configure priority.
+ (#) please refer to programming manual for details in how to configure priority.
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
@@ -297,15 +297,15 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
MPU->RBAR = MPU_Init->BaseAddress;
- MPU->RASR = (MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
- (MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
- (MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
- (MPU_Init->IsShareable << MPU_RASR_S_Pos) |
- (MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
- (MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
- (MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
- (MPU_Init->Size << MPU_RASR_SIZE_Pos) |
- (MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
else
{
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h
index 27a570d485..c83d3dc4e4 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cortex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.c
index a2c5b7faff..d15792f1f2 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.h
index b2b088e034..e007eaaa26 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
@@ -269,7 +269,7 @@ typedef struct
* @param __VALUE__: 8-bit value to be stored in the ID register
* @retval None
*/
-#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)))
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)))
/**
* @brief Returns the 8-bit data stored in the Independent Data(ID) register.
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.c
index 94ae7fcbbb..321bff351c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Extended CRC HAL module driver.
*
* This file provides firmware functions to manage the following
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.h
index e856dd14cb..707648e10b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of CRC HAL extension module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.c
index b537978079..f64e8f66c6 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief CRYP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.h
index 01b56e1819..d997ec45a9 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
@@ -68,10 +68,10 @@
typedef struct
{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
- This parameter can be a value of @ref CRYP CRYP_Data_Type */
+ This parameter can be a value of @ref CRYP_Data_Type */
uint32_t KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit key length.
- This parameter can be a value of @ref CRYP CRYP_Key_Size */
+ This parameter can be a value of @ref CRYP_Key_Size */
uint8_t* pKey; /*!< The key used for encryption/decryption */
@@ -177,7 +177,7 @@ typedef struct
* @{
*/
-/** @defgroup CRYP_Exported_Constants_Group1 CRYP CRYP_Key_Size
+/** @defgroup CRYP_Key_Size CRYP Key Size
* @{
*/
#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000)
@@ -187,7 +187,7 @@ typedef struct
* @}
*/
-/** @defgroup CRYP_Exported_Constants_Group2 CRYP CRYP_Data_Type
+/** @defgroup CRYP_Data_Type CRYP Data Type
* @{
*/
#define CRYP_DATATYPE_32B ((uint32_t)0x00000000)
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c
index 4fe4800734..fa0f50c8b8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Extended CRYP HAL module driver
* This file provides firmware functions to manage the following
* functionalities of CRYP extension peripheral:
@@ -20,7 +20,7 @@
(##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())
(+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
- (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
+ (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
(##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA())
(+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
(+++) Configure and enable two DMA streams one for managing data transfer from
@@ -59,10 +59,10 @@
authentication messages.
Call those functions after the processing ones (polling, interrupt or DMA).
e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data
- then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message
- @note: For CCM Encrypt/Decrypt API's, only DataType = 8-bit is supported by this version.
- @note: The HAL_CRYPEx_AESGCM_xxxx() implementation is limited to 32bits inputs data length
- (Plain/Cyphertext, Header) compared with GCM standards specifications (800-38D).
+ then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message
+ -@- For CCM Encrypt/Decrypt API's, only DataType = 8-bit is supported by this version.
+ -@- The HAL_CRYPEx_AESGCM_xxxx() implementation is limited to 32bits inputs data length
+ (Plain/Cyphertext, Header) compared with GCM standards specifications (800-38D).
(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
@endverbatim
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h
index b40020de4c..ed6d45f539 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of CRYP HAL Extension module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.c
index add5834d0c..5f92022879 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.h
index 3ceb271c7c..9556ef1eda 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.c
index cc12b553ed..3586c8a175 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Extended DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.h
index 40460af1e6..ff4b6fa62a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.c
index 159647492c..2bd407e6b2 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief DCMI HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Digital Camera Interface (DCMI) peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.h
index 43f3fdceb2..cc2eb820f7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of DCMI HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c
index 3147f27073..7be8a52141 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief DCMI Extension HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DCMI extension peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h
index bf3f25759c..16d49c5863 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of DCMI Extension HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_def.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_def.h
index 2b6366ef1d..a9b7fcea43 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_def.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_def.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_def.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c
index 069de43256..a0a7cb78a0 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h
index 525d1f1e47..6b45bb77c0 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c
index 79c2fa7ebb..904e76173b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma2d.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief DMA2D HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the DMA2D peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.h
index 5cadcb3ee5..08f9528fe4 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma2d.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of DMA2D HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.c
index 2336da2e64..e5d77521ab 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
@@ -15,7 +15,7 @@
==============================================================================
[..]
The DMA Extension HAL driver can be used as follows:
- (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
+ (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.h
index f214f320ab..0fc88a196e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c
index f9fedd124e..684fd39dad 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_eth.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief ETH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Ethernet (ETH) peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h
index bb0521faf8..051dcb0dfe 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_eth.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of ETH HAL module.
******************************************************************************
* @attention
@@ -64,8 +64,6 @@
((SPEED) == ETH_SPEED_100M))
#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
((MODE) == ETH_MODE_HALFDUPLEX))
-#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
- ((MODE) == ETH_MODE_HALFDUPLEX))
#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
((MODE) == ETH_RXINTERRUPT_MODE))
#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
@@ -1257,10 +1255,10 @@ typedef struct
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
-#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.c
index 68a8957b4e..129f174d1a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.h
index c2d2f14054..d93fc5b15b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
@@ -191,7 +191,13 @@ typedef struct
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
-
+/**
+ * @brief Get the FLASH Latency.
+ * @retval FLASH Latency
+ * The value of this parameter depend on device used within the same series
+ */
+#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
/**
* @brief Enable the FLASH prefetch buffer.
* @retval none
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.c
index ae0a8ad939..0d91b41d13 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extension peripheral:
@@ -126,7 +126,7 @@ static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);
static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);
static uint32_t FLASH_OB_GetUser(void);
static uint32_t FLASH_OB_GetWRP(void);
-static FlagStatus FLASH_OB_GetRDP(void);
+static uint8_t FLASH_OB_GetRDP(void);
static uint32_t FLASH_OB_GetBOR(void);
static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption);
@@ -727,18 +727,28 @@ static uint32_t FLASH_OB_GetWRP(void)
/**
* @brief Returns the FLASH Read Protection level.
* @retval FlagStatus FLASH ReadOut Protection Status:
- * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
- * - RESET, when OB_RDP_Level_0 is set
+ * This parameter can be one of the following values:
+ * @arg OB_RDP_LEVEL_0: No protection
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory
+ * @arg OB_RDP_LEVEL_2: Full chip protection
*/
-static FlagStatus FLASH_OB_GetRDP(void)
+static uint8_t FLASH_OB_GetRDP(void)
{
- FlagStatus readstatus = RESET;
-
- if (((uint16_t)(FLASH->OPTCR & 0xFF00)) != (uint16_t)OB_RDP_LEVEL_0)
- {
- readstatus = SET;
- }
+ uint8_t readstatus = OB_RDP_LEVEL_0;
+ if (((FLASH->OPTCR & FLASH_OPTCR_RDP) >> 8) == OB_RDP_LEVEL_0)
+ {
+ readstatus = OB_RDP_LEVEL_0;
+ }
+ else if (((FLASH->OPTCR & FLASH_OPTCR_RDP) >> 8) == OB_RDP_LEVEL_2)
+ {
+ readstatus = OB_RDP_LEVEL_2;
+ }
+ else
+ {
+ readstatus = OB_RDP_LEVEL_1;
+ }
+
return readstatus;
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.h
index 1d3aa4216c..fa55ca57e7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of FLASH HAL Extension module.
******************************************************************************
* @attention
@@ -163,9 +163,9 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
* @{
*/
-#define OB_RDP_LEVEL_0 ((uint32_t)0xAA00)
-#define OB_RDP_LEVEL_1 ((uint32_t)0x5500)
-/*#define OB_RDP_LEVEL_2 ((uint32_t)0xCC)*/ /*!< Warning: When enabling read protection level 2
+#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
+#define OB_RDP_LEVEL_1 ((uint8_t)0x55)
+#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
it s no more possible to go back to level 1 or 0 */
/**
* @}
@@ -388,8 +388,8 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
((ADDRESS) == OB_BOOTADDR_SRAM2))
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
- ((LEVEL) == OB_RDP_LEVEL_1))/*||\
- ((LEVEL) == OB_RDP_LEVEL_2))*/
+ ((LEVEL) == OB_RDP_LEVEL_1) ||\
+ ((LEVEL) == OB_RDP_LEVEL_2))
#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.c
index 64a8b569a6..ffc7e08932 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_gpio.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.h
index 6573e52ccd..5ae5430556 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_gpio.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h
index 110df8e3e1..f4a25b224b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_gpio_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.c
index b9bdde9234..b75e961911 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hash.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral:
@@ -175,7 +175,7 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
buffersize = hhash->Init.KeySize;
}
/* Configure the number of valid bits in last word of the message */
- HASH->STR |= 8 * (buffersize % 4);
+ MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));
/* Set the HASH DMA transfer complete */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
@@ -713,10 +713,14 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
+ /* Check the parameters */
+ assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size));
+
/* Process Locked */
__HAL_LOCK(hhash);
@@ -790,15 +794,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
/* Process Locked */
__HAL_LOCK(hhash);
-
- if(hhash->HashITCounter == 0)
- {
- hhash->HashITCounter = 1;
- }
- else
- {
- hhash->HashITCounter = 0;
- }
+
if(hhash->State == HAL_HASH_STATE_READY)
{
/* Change the HASH state */
@@ -818,6 +814,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
HASH->CR |= HASH_CR_INIT;
}
+ /* Reset interrupt counter */
+ hhash->HashITCounter = 0;
+
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
@@ -850,11 +849,18 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
hhash->State = HAL_HASH_STATE_READY;
/* Call digest computation complete callback */
HAL_HASH_DgstCpltCallback(hhash);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
}
}
+
if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
- if(hhash->HashInCount > 64)
+ if(hhash->HashInCount >= 68)
{
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Write the Input block in the Data IN register */
@@ -875,8 +881,11 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
}
else
{
- hhash->HashInCount -= 64;
+ hhash->HashInCount = 0;
+ hhash->pHashInBuffPtr+= hhash->HashInCount;
}
+ /* Set Interrupt counter */
+ hhash->HashITCounter = 1;
}
else
{
@@ -900,6 +909,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
{
inputcounter = (inputcounter+4-inputcounter%4);
}
+ else if ((inputcounter < 4) && (inputcounter != 0))
+ {
+ inputcounter = 4;
+ }
/* Write the Input block in the Data IN register */
for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
@@ -911,9 +924,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
__HAL_HASH_START_DIGEST();
/* Reset buffer counter */
hhash->HashInCount = 0;
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
}
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
}
/* Process Unlocked */
@@ -944,14 +957,6 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
/* Process Locked */
__HAL_LOCK(hhash);
- if(hhash->HashITCounter == 0)
- {
- hhash->HashITCounter = 1;
- }
- else
- {
- hhash->HashITCounter = 0;
- }
if(hhash->State == HAL_HASH_STATE_READY)
{
/* Change the HASH state */
@@ -971,6 +976,9 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
HASH->CR |= HASH_CR_INIT;
}
+ /* Reset interrupt counter */
+ hhash->HashITCounter = 0;
+
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
@@ -1004,11 +1012,17 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
hhash->State = HAL_HASH_STATE_READY;
/* Call digest computation complete callback */
HAL_HASH_DgstCpltCallback(hhash);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
}
}
if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
- if(hhash->HashInCount > 64)
+ if(hhash->HashInCount >= 68)
{
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Write the Input block in the Data IN register */
@@ -1029,8 +1043,11 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
}
else
{
- hhash->HashInCount -= 64;
+ hhash->HashInCount = 0;
+ hhash->pHashInBuffPtr+= hhash->HashInCount;
}
+ /* Set Interrupt counter */
+ hhash->HashITCounter = 1;
}
else
{
@@ -1054,7 +1071,10 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
{
inputcounter = (inputcounter+4-inputcounter%4);
}
-
+ else if ((inputcounter < 4) && (inputcounter != 0))
+ {
+ inputcounter = 4;
+ }
/* Write the Input block in the Data IN register */
for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
{
@@ -1065,9 +1085,9 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
__HAL_HASH_START_DIGEST();
/* Reset buffer counter */
hhash->HashInCount = 0;
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
}
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
}
/* Process Unlocked */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.h
index efdf74da41..1b7be41300 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hash.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
@@ -68,7 +68,7 @@
typedef struct
{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
- This parameter can be a value of @ref HASH DataType */
+ This parameter can be a value of @ref HASH_Data_Type */
uint32_t KeySize; /*!< The key size is used only in HMAC operation */
@@ -173,7 +173,7 @@ typedef struct
* @}
*/
-/** @defgroup HASH_Exported_Constants_Group3 HASH DataType
+/** @defgroup HASH_Data_Type HASH Data Type
* @{
*/
#define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */
@@ -209,8 +209,8 @@ typedef struct
/** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition
* @{
*/
-#define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */
-#define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */
+#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
+#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
/**
* @}
*/
@@ -240,7 +240,8 @@ typedef struct
* @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_HASH_GET_FLAG(__FLAG__) ((HASH->SR & (__FLAG__)) == (__FLAG__))
+#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
+ ((HASH->SR & (__FLAG__)) == (__FLAG__)))
/**
* @brief Enable the multiple DMA mode.
@@ -414,6 +415,9 @@ void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
#define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \
((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))
+
+#define IS_HASH_SHA1_BUFFER_SIZE(__SIZE__) ((((__SIZE__)%4) != 0)? 0U: 1U)
+
/**
* @}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c
index e5e670b661..12f82fb31a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hash_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief HASH HAL Extension module driver.
* This file provides firmware functions to manage the following
* functionalities of HASH peripheral:
@@ -264,7 +264,7 @@ static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma)
buffersize = hhash->Init.KeySize;
}
/* Configure the number of valid bits in last word of the message */
- HASH->STR |= 8 * (buffersize % 4);
+ MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));
/* Set the HASH DMA transfer complete */
hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
@@ -924,15 +924,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
/* Process Locked */
__HAL_LOCK(hhash);
-
- if(hhash->HashITCounter == 0)
- {
- hhash->HashITCounter = 1;
- }
- else
- {
- hhash->HashITCounter = 0;
- }
+
if(hhash->State == HAL_HASH_STATE_READY)
{
/* Change the HASH state */
@@ -951,7 +943,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
the message digest of a new message */
HASH->CR |= HASH_CR_INIT;
}
-
+ /* Reset interrupt counter */
+ hhash->HashITCounter = 0;
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
@@ -976,11 +969,16 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
hhash->State = HAL_HASH_STATE_READY;
/* Call digest computation complete callback */
HAL_HASH_DgstCpltCallback(hhash);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
}
}
if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
- if(hhash->HashInCount > 64)
+ if(hhash->HashInCount >= 68)
{
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Write the Input block in the Data IN register */
@@ -1000,8 +998,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
}
else
{
- hhash->HashInCount -= 64;
+ hhash->HashInCount = 0;
+ hhash->pHashInBuffPtr+= hhash->HashInCount;
}
+ /* Set Interrupt counter */
+ hhash->HashITCounter = 1;
}
else
{
@@ -1025,7 +1026,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
{
inputcounter = (inputcounter+4-inputcounter%4);
}
-
+ else if ((inputcounter < 4) && (inputcounter != 0))
+ {
+ inputcounter = 4;
+ }
/* Write the Input block in the Data IN register */
for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
{
@@ -1036,9 +1040,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
__HAL_HASH_START_DIGEST();
/* Reset buffer counter */
hhash->HashInCount = 0;
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
}
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
}
/* Process Unlocked */
@@ -1068,15 +1072,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
/* Process Locked */
__HAL_LOCK(hhash);
-
- if(hhash->HashITCounter == 0)
- {
- hhash->HashITCounter = 1;
- }
- else
- {
- hhash->HashITCounter = 0;
- }
+
if(hhash->State == HAL_HASH_STATE_READY)
{
/* Change the HASH state */
@@ -1096,6 +1092,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
HASH->CR |= HASH_CR_INIT;
}
+ /* Reset interrupt counter */
+ hhash->HashITCounter = 0;
+
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
@@ -1120,11 +1119,17 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
hhash->State = HAL_HASH_STATE_READY;
/* Call digest computation complete callback */
HAL_HASH_DgstCpltCallback(hhash);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
}
}
if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
- if(hhash->HashInCount > 64)
+ if(hhash->HashInCount >= 68)
{
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Write the Input block in the Data IN register */
@@ -1145,8 +1150,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
}
else
{
- hhash->HashInCount -= 64;
+ hhash->HashInCount = 0;
+ hhash->pHashInBuffPtr+= hhash->HashInCount;
}
+ /* Set Interrupt counter */
+ hhash->HashITCounter = 1;
}
else
{
@@ -1170,6 +1178,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
{
inputcounter = (inputcounter+4-inputcounter%4);
}
+ else if ((inputcounter < 4) && (inputcounter != 0))
+ {
+ inputcounter = 4;
+ }
/* Write the Input block in the Data IN register */
for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
@@ -1181,9 +1193,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
__HAL_HASH_START_DIGEST();
/* Reset buffer counter */
hhash->HashInCount = 0;
+ /* Call Input data transfer complete callback */
+ HAL_HASH_InCpltCallback(hhash);
}
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
}
/* Process Unlocked */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.h
index 9ad3d04c92..e6ad9895cd 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hash_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of HASH HAL Extension module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.c
index 0aba52047a..99e408367d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hcd.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief HCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.h
index 665a543db1..855b6f6112 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hcd.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.c
index db670c0cae..40142f8159 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2c.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.h
index a7cf0b91eb..3fdfaa61c7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2c.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c
index 318df74e15..0fcfb5f5f6 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2c_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h
index 4101ce6d72..e856ce2eb6 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2c_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of I2C HAL Extension module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c
index 4aaa53e923..f89f23a4e6 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2s.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
@@ -522,13 +522,17 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
}
}
- /* Wait until Busy flag is reset */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ /* Check if Slave mode is selected */
+ if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
{
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
+ /* Wait until Busy flag is reset */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
}
hi2s->State = HAL_I2S_STATE_READY;
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.h
index 31bcf2f168..f3d34bc0f7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2s.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.c
index 9097af1936..32716ba6bf 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_irda.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA SIR ENDEC block (IrDA):
@@ -858,10 +858,11 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
{
/* The Lock is not implemented on this API to allow the user application
- to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
- when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
- and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
- */
+ to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
+ HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ the stream and the corresponding call back is executed. */
/* Disable the UART Tx/Rx DMA requests */
hirda->Instance->CR3 &= ~USART_CR3_DMAT;
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.h
index bc67db06b2..69c1c8896a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_irda.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
@@ -77,8 +77,8 @@ typedef struct
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
- uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref IRDA_Mode */
+ uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref IRDA_Transfer_Mode */
uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
to achieve low-power frequency.
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda_ex.h
index 09dd006b6b..cba21cd82d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_irda_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of IRDA HAL Extension module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.c
index 4ef7c00167..ca63f0f9d9 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_iwdg.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief IWDG HAL module driver.
*
* This file provides firmware functions to manage the following
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.h
index 41eec1ee66..4b579cce35 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_iwdg.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.c
index e064f8706b..9c05928648 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.c
@@ -2,10 +2,9 @@
******************************************************************************
* @file stm32f7xx_hal_lptim.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief LPTIM HAL module driver.
- *
* This file provides firmware functions to manage the following
* functionalities of the Low Power Timer (LPTIM) peripheral:
* + Initialization and de-initialization functions.
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.h
index 8e626d28a3..783e2c012f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_lptim.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of LPTIM HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.c
index 30e222de90..e05240bbc5 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_ltdc.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief LTDC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the LTDC peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.h
index be989ccbcb..4cacf080eb 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_ltdc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of LTDC HAL module.
******************************************************************************
* @attention
@@ -136,10 +136,10 @@ typedef struct
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t WindowY0; /*!< Configures the Window vertical Start Position.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */
uint32_t PixelFormat; /*!< Specifies the pixel format.
This parameter can be one of value of @ref LTDC_Pixelformat */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c
index 58ed4bacb3..fa42247714 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_nand.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.h
index cd50b9538e..3aff116f07 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_nand.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.c
index df0a503057..f7d0d9adbb 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_nor.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.h
index f86f704d21..b07c75fcd4 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_nor.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.c
index d6f02b01d4..ca106b7220 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pcd.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.h
index 3f2ed02b21..8335584225 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pcd.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c
index 6ed6b3dea7..0dc553c216 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pcd_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h
index 85b8c82dcc..d6d43c06d9 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pcd_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.c
index 277ab468fe..bd881ac8f4 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pwr.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.h
index 5c266670c1..63ef22cbba 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pwr.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c
index 55c099c1b9..a3182693b7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pwr_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of PWR extension peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h
index a8359cfacb..fa77f76a1e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pwr_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c
index 3ae154a7fd..00ef8a41af 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c
@@ -2,10 +2,9 @@
******************************************************************************
* @file stm32f7xx_hal_qspi.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief QSPI HAL module driver.
- *
* This file provides firmware functions to manage the following
* functionalities of the QuadSPI interface (QSPI).
* + Initialization and de-initialization functions
@@ -26,13 +25,13 @@
======================
[..]
(#) As prerequisite, fill in the HAL_QSPI_MspInit() :
- (+) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
- (+) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
- (+) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
- (+) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
- (+) If interrupt mode is used, enable and configure QuadSPI global
+ (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
+ (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
+ (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+ (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
+ (++) If interrupt mode is used, enable and configure QuadSPI global
interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
- (+) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
+ (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
@@ -44,31 +43,31 @@
[..]
(#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
functions :
- (+) Instruction phase : the mode used and if present the instruction opcode.
- (+) Address phase : the mode used and if present the size and the address value.
- (+) Alternate-bytes phase : the mode used and if present the size and the alternate
+ (++) Instruction phase : the mode used and if present the instruction opcode.
+ (++) Address phase : the mode used and if present the size and the address value.
+ (++) Alternate-bytes phase : the mode used and if present the size and the alternate
bytes values.
- (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
- (+) Data phase : the mode used and if present the number of bytes.
- (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+ (++) Data phase : the mode used and if present the number of bytes.
+ (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
if activated.
- (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+ (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
(#) If no data is required for the command, it is sent directly to the memory :
- (+) In polling mode, the output of the function is done when the transfer is complete.
- (+) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
+ (++) In polling mode, the output of the function is done when the transfer is complete.
+ (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
(#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
HAL_QSPI_Transmit_IT() after the command configuration :
- (+) In polling mode, the output of the function is done when the transfer is complete.
- (+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
+ (++) In polling mode, the output of the function is done when the transfer is complete.
+ (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
- (+) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
+ (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
(#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
HAL_QSPI_Receive_IT() after the command configuration :
- (+) In polling mode, the output of the function is done when the transfer is complete.
- (+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
+ (++) In polling mode, the output of the function is done when the transfer is complete.
+ (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
- (+) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
+ (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
*** Auto-polling functional mode ***
@@ -76,37 +75,37 @@
[..]
(#) Configure the command sequence and the auto-polling functional mode using the
HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
- (+) Instruction phase : the mode used and if present the instruction opcode.
- (+) Address phase : the mode used and if present the size and the address value.
- (+) Alternate-bytes phase : the mode used and if present the size and the alternate
+ (++) Instruction phase : the mode used and if present the instruction opcode.
+ (++) Address phase : the mode used and if present the size and the address value.
+ (++) Alternate-bytes phase : the mode used and if present the size and the alternate
bytes values.
- (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
- (+) Data phase : the mode used.
- (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+ (++) Data phase : the mode used.
+ (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
if activated.
- (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
- (+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
+ (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+ (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
the polling interval and the automatic stop activation.
(#) After the configuration :
- (+) In polling mode, the output of the function is done when the status match is reached. The
+ (++) In polling mode, the output of the function is done when the status match is reached. The
automatic stop is activated to avoid an infinite loop.
- (+) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
+ (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
*** Memory-mapped functional mode ***
=====================================
[..]
(#) Configure the command sequence and the memory-mapped functional mode using the
HAL_QSPI_MemoryMapped() functions :
- (+) Instruction phase : the mode used and if present the instruction opcode.
- (+) Address phase : the mode used and the size.
- (+) Alternate-bytes phase : the mode used and if present the size and the alternate
+ (++) Instruction phase : the mode used and if present the instruction opcode.
+ (++) Address phase : the mode used and the size.
+ (++) Alternate-bytes phase : the mode used and if present the size and the alternate
bytes values.
- (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
- (+) Data phase : the mode used.
- (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+ (++) Data phase : the mode used.
+ (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
if activated.
- (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
- (+) The timeout activation and the timeout period.
+ (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+ (++) The timeout activation and the timeout period.
(#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
@@ -121,7 +120,7 @@
====================================================
[..]
(#) Workarounds Implemented inside HAL Driver
- (+) Extra data written in the FIFO at the end of a read transfer
+ (++) Extra data written in the FIFO at the end of a read transfer
@endverbatim
******************************************************************************
@@ -376,7 +375,7 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
*
@verbatim
===============================================================================
- ##### I/O operation functions #####
+ ##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to :
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.h
index 81ed67ab8d..d8835f9866 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_qspi.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of QSPI HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.c
index 69af1b8340..3ec90947c7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -48,8 +48,8 @@
after the clock enable bit is set on the hardware register
[..]
- Workarounds:
- (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+ Implemented Workaround:
+ (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
@endverbatim
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h
index 888928d02c..2ae5f2cffe 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rcc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c
index c660343a51..fd6fc1c90e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rcc_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Extension RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
@@ -200,27 +200,27 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*------------------------------------ RTC configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
-
- /* Enable write access to Backup domain */
- PWR->CR1 |= PWR_CR1_DBP;
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait for Backup domain Write protection disable */
- while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- {
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
/* Reset the Backup domain only if the RTC Clock source selection is modified */
if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
{
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ PWR->CR1 |= PWR_CR1_DBP;
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait for Backup domain Write protection disable */
+ while((PWR->CR1 & PWR_CR1_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
@@ -230,25 +230,26 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg0;
- }
-
- /* If LSE is selected as RTC clock source, wait for LSE reactivation */
- if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+
+ /* If LSE is selected as RTC clock source, wait for LSE reactivation */
+ if (HAL_IS_BIT_SET(tmpreg0, RCC_BDCR_LSERDY))
{
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
- return HAL_TIMEOUT;
- }
- }
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
+
/*------------------------------------ TIM configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
{
@@ -465,7 +466,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
/* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
}
@@ -502,7 +503,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
/* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
}
@@ -517,7 +518,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
}
@@ -594,7 +595,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
/* Configure the PLLSAI division factors */
- /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) × (PLLI2SN/PLLM) */
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h
index 42ef7ce0e5..03d389174b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.c
index 2df71feca8..8848718c5f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rng.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.h
index 4f4d68592c..0f0a48bb69 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rng.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.c
index 90eb121225..a52dd008fb 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rtc.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
@@ -62,7 +62,7 @@
accesses.
[..] To enable access to the RTC Domain and RTC registers, proceed as follows:
(+) Enable the Power Controller (PWR) APB1 interface clock using the
- __PWR_CLK_ENABLE() function.
+ __HAL_RCC_PWR_CLK_ENABLE() function.
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
(+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
(+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
@@ -547,16 +547,23 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
/**
* @brief Gets RTC current time.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param sTime: Pointer to Time structure
+ * @param hrtc: RTC handle
+ * @param sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned
+ * with input format (BIN or BCD), also SubSeconds field returning the
+ * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
+ * factor to be used for second fraction ratio computation.
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
- * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
- * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
- * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
+ * value in second fraction ratio with time unit following generic formula:
+ * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+ * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read
+ * to ensure consistency between the time and date values.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
@@ -597,8 +604,8 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
* @param sDate: Pointer to date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@@ -706,8 +713,11 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
* @param sDate: Pointer to Date structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@@ -1237,8 +1247,8 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
* @arg RTC_ALARM_B: AlarmB
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.h
index 31cf93cede..52dabe13e8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rtc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c
index f6c9b38089..2ff39477d7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rtc_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
@@ -965,21 +965,25 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
/* Get tick */
tickstart = HAL_GetTick();
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
{
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
{
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
+ }
+ }
}
/* Clear the Wakeup Timer clock source bits in CR register */
@@ -1034,21 +1038,25 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
/* Get tick */
tickstart = HAL_GetTick();
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
{
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
{
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
+ }
+ }
}
/* Configure the Wakeup Timer counter */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.h
index 364267980c..e80c37beb1 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rtc_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of RTC HAL Extension module.
******************************************************************************
* @attention
@@ -186,9 +186,9 @@ typedef struct
/** @defgroup RTCEx_TimeStamp_Pin_Selection RTCEx TimeStamp Pin Selection
* @{
*/
-#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)
-#define RTC_TIMESTAMPPIN_PI8 ((uint32_t)0x00000002)
-#define RTC_TIMESTAMPPIN_PC1 ((uint32_t)0x00000004)
+#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)
+#define RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00000002)
+#define RTC_TIMESTAMPPIN_POS2 ((uint32_t)0x00000004)
/**
* @}
*/
@@ -431,7 +431,7 @@ typedef struct
* @arg RTC_FLAG_WUTF
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
* @brief Enable the RTC Tamper1 input detection.
@@ -488,7 +488,7 @@ typedef struct
*/
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \
((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \
- (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))
+ (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))
/**
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
@@ -525,7 +525,7 @@ typedef struct
* @arg RTC_FLAG_TAMP3F: Tamper3 flag
* @retval None
*/
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
* @brief Enable the RTC TimeStamp peripheral.
@@ -601,7 +601,7 @@ typedef struct
* @arg RTC_FLAG_TSOVF
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
* @brief Enable the RTC internal TimeStamp peripheral.
@@ -819,7 +819,7 @@ typedef struct
* @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
* @retval Line Status.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
* @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
@@ -930,7 +930,18 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
* @}
*/
-/* Private macros ------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
+ * @{
+ */
+/* Masks Definition */
+#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
+#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT))
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
* @{
*/
@@ -945,11 +956,13 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
#define IS_RTC_BKP(__BKP__) ((__BKP__) < (uint32_t) RTC_BKP_NUMBER)
#define IS_TIMESTAMP_EDGE(__EDGE__) (((__EDGE__) == RTC_TIMESTAMPEDGE_RISING) || \
((__EDGE__) == RTC_TIMESTAMPEDGE_FALLING))
-#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & (uint32_t)0xFFFFFFD6) == 0x00) && ((__TAMPER__) != (uint32_t)RESET))
-#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)0xFFB6FFFB) == 0x00) && ((__INTERRUPT__) != (uint32_t)RESET))
+#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXE))) == 0x00) && ((__TAMPER__) != (uint32_t)RESET))
+
+#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXIE)) == 0x00) && ((__INTERRUPT__) != (uint32_t)RESET))
+
#define IS_RTC_TIMESTAMP_PIN(__PIN__) (((__PIN__) == RTC_TIMESTAMPPIN_DEFAULT) || \
- ((__PIN__) == RTC_TIMESTAMPPIN_PI8) || \
- ((__PIN__) == RTC_TIMESTAMPPIN_PC1))
+ ((__PIN__) == RTC_TIMESTAMPPIN_POS1) || \
+ ((__PIN__) == RTC_TIMESTAMPPIN_POS2))
#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.c
index 80c31189e1..cab0a701b9 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sai.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief SAI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Audio Interface (SAI) peripheral:
@@ -413,7 +413,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
((hsai->FrameInit.ActiveFrameLength - 1) << 8));
/* SAI Block_x SLOT Configuration ------------------------------------------*/
- /* This register has no meaning in AC’97 and SPDIF audio protocol */
+ /* This register has no meaning in AC 97 and SPDIF audio protocol */
hsai->Instance->SLOTR&= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \
SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN ));
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.h
index 1e5184e34c..ddb8508832 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sai.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of SAI HAL module.
******************************************************************************
* @attention
@@ -101,7 +101,7 @@ typedef struct
uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
This parameter can be a value of @ref SAI_Block_NoDivider
- @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length
+ @note If bit NODIV in the SAI_xCR1 register is cleared, the frame length
should be aligned to a number equal to a power of 2, from 8 to 256.
If bit NODIV in the SAI_xCR1 register is set, the frame length can
take any of the values without constraint since the input clock of
@@ -152,7 +152,7 @@ typedef struct
uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
This parameter must be a number between Min_Data = 8 and Max_Data = 256.
- @note: If master clock MCLK_x pin is declared as an output, the frame length
+ @note If master clock MCLK_x pin is declared as an output, the frame length
should be aligned to a number equal to power of 2 in order to keep
in an audio frame, an integer number of MCLK pulses by bit Clock. */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.c
index 492027284d..942ebc0cb3 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sai_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief SAI Extension HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of SAI extension peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.h
index 2328de58e1..a3d506bfdb 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sai_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of SAI Extension HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.c
index 49e1788a4e..8ae5553ad7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sd.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief SD card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.h
index 9dd473c603..77b0d024e7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sd.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of SD HAL module.
******************************************************************************
* @attention
@@ -603,7 +603,7 @@ typedef enum
/**
* @brief Clear the SD's interrupt pending bits.
- * @param __HANDLE__ : SD Handle
+ * @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c
index c564fb9e5d..8aba81f8af 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sdram.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief SDRAM HAL module driver.
* This file provides a generic firmware to drive SDRAM memories mounted
* as external device.
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.h
index 349b98b94a..8978716c58 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sdram.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of SDRAM HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.c
index 0a7bc978c0..9d42679a28 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_smartcard.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
@@ -29,9 +29,9 @@
and HAL_SMARTCARD_Receive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
(+++) Enable the NVIC USART IRQ handle.
- (@) The specific USART interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+ (+++) The specific USART interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
(##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
and HAL_SMARTCARD_Receive_DMA() APIs):
(+++) Declare a DMA handle structure for the Tx/Rx stream.
@@ -49,8 +49,9 @@
in the hsc AdvancedInit structure.
(#) Initialize the SMARTCARD associated USART registers by calling
- the HAL_SMARTCARD_Init() API.
-
+ the HAL_SMARTCARD_Init() API.
+
+ [..]
(@) HAL_SMARTCARD_Init() API also configure also the low level Hardware GPIO, CLOCK, CORTEX...etc) by
calling the customized HAL_SMARTCARD_MspInit() API.
@@ -150,11 +151,13 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc);
(++) Parity: parity should be enabled,
Frame Length is fixed to 8 bits plus parity:
the USART frame format is given in the following table:
- +---------------------------------------------------------------+
- | M1M0 bits | PCE bit | USART frame |
- |-----------------------|---------------------------------------|
- | 01 | 1 | | SB | 8 bit data | PB | STB | |
- +---------------------------------------------------------------+
+
+ (+++) +---------------------------------------------------------------+
+ (+++) | M1M0 bits | PCE bit | USART frame |
+ (+++) |-----------------------|---------------------------------------|
+ (+++) | 01 | 1 | | SB | 8 bit data | PB | STB | |
+ (+++) +---------------------------------------------------------------+
+
(++) Receiver/transmitter modes
(++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
(++) Prescaler value
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.h
index 8c32186d43..bbe2895e7a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_smartcard.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
@@ -103,7 +103,7 @@ typedef struct
uint32_t NACKState; /*!< Specifies whether the SmartCard NACK transmission is enabled
in case of parity error.
- This parameter can be a value of @ref SmartCard_NACK_State */
+ This parameter can be a value of @ref SMARTCARD_NACK_State */
uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled.
This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
@@ -311,7 +311,7 @@ typedef struct
*/
-/** @defgroup SmartCard_NACK_State SMARTCARD NACK State
+/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State
* @{
*/
#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
@@ -329,7 +329,7 @@ typedef struct
* @}
*/
-/** @defgroup SmartCard_DMA_Requests SMARTCARD DMA requests
+/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
* @{
*/
@@ -431,6 +431,7 @@ typedef struct
#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080)
#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040)
#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020)
+#define SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010)
#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008)
#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004)
#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002)
@@ -454,7 +455,7 @@ typedef struct
#define SMARTCARD_IT_TXE ((uint16_t)0x0727)
#define SMARTCARD_IT_TC ((uint16_t)0x0626)
#define SMARTCARD_IT_RXNE ((uint16_t)0x0525)
-
+#define SMARTCARD_IT_IDLE ((uint16_t)0x0424)
#define SMARTCARD_IT_ERR ((uint16_t)0x0060)
#define SMARTCARD_IT_ORE ((uint16_t)0x0300)
#define SMARTCARD_IT_NE ((uint16_t)0x0200)
@@ -474,6 +475,7 @@ typedef struct
#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< Idle line detected clear Flag */
#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.c
index fd17f6b64b..137d022353 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_smartcard_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief SMARTCARD HAL module driver.
*
* This file provides extended firmware functions to manage the following
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.h
index bee9883729..e0555b1ea9 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_smartcard_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.c
index 096d9304af..c14a10a84a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_spdifrx.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the SPDIFRX audio interface:
* + Initialization and Configuration
@@ -28,7 +28,7 @@
(+++) Enable the NVIC SPDIFRX IRQ handle.
(##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's).
(+++) Declare a DMA handle structure for the reception of the Data Flow channel.
- (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
+ (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.
(+++) Configure the DMA Channel.
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.h
index 57567c5280..612afa4f20 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_spdifrx.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of SPDIFRX HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c
index c0c2c0720e..79e80e8d66 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c
@@ -2,10 +2,9 @@
******************************************************************************
* @file stm32f7xx_hal_spi.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief SPI HAL module driver.
- *
* This file provides firmware functions to manage the following
* functionalities of the Serial Peripheral Interface (SPI) peripheral:
* + Initialization and de-initialization functions
@@ -2141,6 +2140,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
hspi->RxISR = SPI_2linesRxISR_8BITCRC;
return;
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.h
index 7658a8f79f..fdfb1202a6 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_spi.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.c
index 1f72712bc8..22466a150a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sram.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief SRAM HAL module driver.
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.h
index f7c4a74901..578efb21d7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sram.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c
index e9d082f018..2176bf097e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_tim.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.h
index ff7a09df24..54b04bd298 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_tim.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.c
index 12993ecbfc..754b3b1dfa 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_tim_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer extension peripheral:
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.h
index 7053d15db9..f043937de6 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_tim_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of TIM HAL Extension module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.c
index 31bc983a5b..a321b7d86d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.c
@@ -2,10 +2,9 @@
******************************************************************************
* @file stm32f7xx_hal_uart.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief UART HAL module driver.
- *
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
* + Initialization and de-initialization functions
@@ -551,7 +550,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
*
@verbatim
===============================================================================
- ##### I/O operation functions #####
+ ##### IO operation functions #####
===============================================================================
This subsection provides a set of functions allowing to manage the UART asynchronous
and Half duplex data transfers.
@@ -1053,13 +1052,20 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
}
else if(huart->State == HAL_UART_STATE_BUSY_RX)
{
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
+
/* Enable the UART DMA Rx request */
huart->Instance->CR3 |= USART_CR3_DMAR;
}
else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
{
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
+
/* Enable the UART DMA Rx request before the DMA Tx request */
huart->Instance->CR3 |= USART_CR3_DMAR;
+
/* Enable the UART DMA Tx request */
huart->Instance->CR3 |= USART_CR3_DMAT;
}
@@ -1071,8 +1077,7 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
__HAL_UART_ENABLE(huart);
}
- /* TEACK and/or REACK to check before moving huart->State to Ready */
- return (UART_CheckIdleState(huart));
+ return HAL_OK;
}
/**
@@ -1082,8 +1087,12 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
*/
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
{
- /* Process Locked */
- __HAL_LOCK(huart);
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
+ HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ the stream and the corresponding call back is executed. */
/* Disable the UART Tx/Rx DMA requests */
huart->Instance->CR3 &= ~USART_CR3_DMAT;
@@ -1100,14 +1109,8 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
HAL_DMA_Abort(huart->hdmarx);
}
- /* Disable UART peripheral */
- __HAL_UART_DISABLE(huart);
-
huart->State = HAL_UART_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.h
index 64873456ee..076aed8fc3 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_uart.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
@@ -532,7 +532,7 @@ typedef struct
* @{
*/
#define UART_FLAG_TEACK ((uint32_t)0x00200000)
-#define UART_FLAG_SBKF ((uint32_t)0x00040000
+#define UART_FLAG_SBKF ((uint32_t)0x00040000)
#define UART_FLAG_CMF ((uint32_t)0x00020000)
#define UART_FLAG_BUSY ((uint32_t)0x00010000)
#define UART_FLAG_ABRF ((uint32_t)0x00008000)
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart_ex.h
index 79d35ea63d..bff4b06894 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_uart_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of UART HAL Extension module.
******************************************************************************
* @attention
@@ -99,7 +99,7 @@
/** @brief Reports the UART clock source.
* @param __HANDLE__: specifies the UART Handle
- * @param __CLOCKSOURCE__ : output variable
+ * @param __CLOCKSOURCE__: output variable
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.c
index caeeca724a..2bfa1160d5 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.c
@@ -2,10 +2,9 @@
******************************************************************************
* @file stm32f7xx_hal_usart.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief USART HAL module driver.
- *
* This file provides firmware functions to manage the following
* functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
* Peripheral (USART).
@@ -24,30 +23,30 @@
(#) Initialize the USART low level resources by implement the HAL_USART_MspInit ()API:
(##) Enable the USARTx interface clock.
(##) USART pins configuration:
- (+) Enable the clock for the USART GPIOs.
- (+) Configure these USART pins as alternate function pull-up.
+ (+++) Enable the clock for the USART GPIOs.
+ (+++) Configure these USART pins as alternate function pull-up.
(##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
- (+) Configure the USARTx interrupt priority.
- (+) Enable the NVIC USART IRQ handle.
- (@) The specific USART interrupts (Transmission complete interrupt,
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (+++) The specific USART interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
(##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
- (+) Declare a DMA handle structure for the Tx/Rx stream.
- (+) Enable the DMAx interface clock.
- (+) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+) Configure the DMA Tx/Rx Stream.
- (+) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
- (+) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
+ (+++) Declare a DMA handle structure for the Tx/Rx stream.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx Stream.
+ (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
(#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
flow control and Mode(Receiver/Transmitter) in the husart Init structure.
(#) Initialize the USART registers by calling the HAL_USART_Init() API:
- (+) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_USART_MspInit(&husart) API.
+ (++) These API's configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_USART_MspInit(&husart) API.
@endverbatim
******************************************************************************
@@ -159,13 +158,14 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
8-bit or 9-bit), the possible USART frame formats are as listed in the
following table:
- +---------------------------------------------------------------+
- | M1M0 bits | PCE bit | USART frame |
- |-----------------------|---------------------------------------|
- | 10 | 0 | | SB | 7-bit data | STB | |
- |-----------|-----------|---------------------------------------|
- | 10 | 1 | | SB | 6-bit data | PB | STB | |
- +---------------------------------------------------------------+
+ (+++) +---------------------------------------------------------------+
+ (+++) | M1M0 bits | PCE bit | USART frame |
+ (+++) |-----------------------|---------------------------------------|
+ (+++) | 10 | 0 | | SB | 7-bit data | STB | |
+ (+++) |-----------|-----------|---------------------------------------|
+ (+++) | 10 | 1 | | SB | 6-bit data | PB | STB | |
+ (+++) +---------------------------------------------------------------+
+
(++) USART polarity
(++) USART phase
(++) USART LastBit
@@ -304,10 +304,10 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
clock (SCLK is always an output).
(#) There are two mode of transfer:
- (+) Blocking mode: The communication is performed in polling mode.
+ (++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
- (+) No-Blocking mode: The communication is performed using Interrupts
+ (++) No-Blocking mode: The communication is performed using Interrupts
or DMA, These API's return the HAL status.
The end of the data processing will be indicated through the
dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
@@ -317,31 +317,31 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
(#) Blocking mode API's are :
- (+) HAL_USART_Transmit()in simplex mode
- (+) HAL_USART_Receive() in full duplex receive only
- (+) HAL_USART_TransmitReceive() in full duplex mode
+ (++) HAL_USART_Transmit()in simplex mode
+ (++) HAL_USART_Receive() in full duplex receive only
+ (++) HAL_USART_TransmitReceive() in full duplex mode
(#) Non-Blocking mode API's with Interrupt are :
- (+) HAL_USART_Transmit_IT()in simplex mode
- (+) HAL_USART_Receive_IT() in full duplex receive only
- (+) HAL_USART_TransmitReceive_IT()in full duplex mode
- (+) HAL_USART_IRQHandler()
+ (++) HAL_USART_Transmit_IT()in simplex mode
+ (++) HAL_USART_Receive_IT() in full duplex receive only
+ (++) HAL_USART_TransmitReceive_IT()in full duplex mode
+ (++) HAL_USART_IRQHandler()
(#) No-Blocking mode functions with DMA are :
- (+) HAL_USART_Transmit_DMA()in simplex mode
- (+) HAL_USART_Receive_DMA() in full duplex receive only
- (+) HAL_USART_TransmitReceive_DMA() in full duplex mode
- (+) HAL_USART_DMAPause()
- (+) HAL_USART_DMAResume()
- (+) HAL_USART_DMAStop()
+ (++) HAL_USART_Transmit_DMA()in simplex mode
+ (++) HAL_USART_Receive_DMA() in full duplex receive only
+ (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
+ (++) HAL_USART_DMAPause()
+ (++) HAL_USART_DMAResume()
+ (++) HAL_USART_DMAStop()
(#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
- (+) HAL_USART_TxCpltCallback()
- (+) HAL_USART_RxCpltCallback()
- (+) HAL_USART_TxHalfCpltCallback()
- (+) HAL_USART_RxHalfCpltCallback()
- (+) HAL_USART_ErrorCallback()
- (+) HAL_USART_TxRxCpltCallback()
+ (++) HAL_USART_TxCpltCallback()
+ (++) HAL_USART_RxCpltCallback()
+ (++) HAL_USART_TxHalfCpltCallback()
+ (++) HAL_USART_RxHalfCpltCallback()
+ (++) HAL_USART_ErrorCallback()
+ (++) HAL_USART_TxRxCpltCallback()
@endverbatim
* @{
@@ -1000,24 +1000,24 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
}
else if(husart->State == HAL_USART_STATE_BUSY_RX)
{
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
+
/* Enable the USART DMA Rx request */
husart->Instance->CR3 |= USART_CR3_DMAR;
}
else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
{
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
+
/* Enable the USART DMA Rx request before the DMA Tx request */
husart->Instance->CR3 |= USART_CR3_DMAR;
+
/* Enable the USART DMA Tx request */
husart->Instance->CR3 |= USART_CR3_DMAT;
}
- /* If the USART peripheral is still not enabled, enable it */
- if((husart->Instance->CR1 & USART_CR1_UE) == 0)
- {
- /* Enable USART peripheral */
- __HAL_USART_ENABLE(husart);
- }
-
/* Process Unlocked */
__HAL_UNLOCK(husart);
@@ -1031,8 +1031,12 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
*/
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
{
- /* Process Locked */
- __HAL_LOCK(husart);
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
+ HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ the stream and the corresponding call back is executed. */
/* Disable the USART Tx/Rx DMA requests */
husart->Instance->CR3 &= ~USART_CR3_DMAT;
@@ -1049,14 +1053,8 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
HAL_DMA_Abort(husart->hdmarx);
}
- /* Disable USART peripheral */
- __HAL_USART_DISABLE(husart);
-
husart->State = HAL_USART_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
return HAL_OK;
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.h
index d2481fb0bb..03be547c20 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_usart.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart_ex.h
index 4f586d833a..ad6aa19c8e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart_ex.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_usart_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of USART HAL Extension module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.c
index c33e624e24..724653ed52 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_wwdg.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
@@ -31,8 +31,8 @@
(+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
(+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
(+) WWDG Counter refresh is allowed between the following limits :
- (++) min time (mS) = 1000 * (Counter – Window) / WWDG clock
- (++) max time (mS) = 1000 * (Counter – 0x40) / WWDG clock
+ (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
+ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Min-max timeout value at 50 MHz(PCLK1): 81.9 us / 41.9 ms
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.h
index 04c8f9e6b2..a889bf8664 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_wwdg.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.c
index 5ff27d4f89..38adbcae50 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_ll_fmc.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief FMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h
index 190c4fafbf..019ec0643b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_ll_fmc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of FMC HAL module.
******************************************************************************
* @attention
@@ -145,7 +145,7 @@
/** @defgroup FMC_Setup_Time FMC Setup Time
* @{
*/
-#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
+#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254)
/**
* @}
*/
@@ -153,7 +153,7 @@
/** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time
* @{
*/
-#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
+#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254)
/**
* @}
*/
@@ -161,7 +161,7 @@
/** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time
* @{
*/
-#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
+#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254)
/**
* @}
*/
@@ -169,7 +169,7 @@
/** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time
* @{
*/
-#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
+#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254)
/**
* @}
*/
@@ -552,26 +552,26 @@ typedef struct
the command assertion for NAND-Flash read or write access
to common/Attribute or I/O memory space (depending on
the memory space timing to be configured).
- This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+ This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the
memory space timing to be configured).
- This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+ This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command de-assertion
for NAND-Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing
to be configured).
- This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+ This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
data bus is kept in HiZ after the start of a NAND-Flash
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
- This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+ This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
}FMC_NAND_PCC_TimingTypeDef;
/**
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.c
index e4f44aa3dd..565a24271c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_ll_sdmmc.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief SDMMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.h
index a7fb2a13ee..454ceffe4b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_ll_sdmmc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of SDMMC HAL module.
******************************************************************************
* @attention
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.c
index a70d72e7d7..2e9d772332 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_ll_usb.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief USB Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -335,7 +335,7 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
{
uint32_t count = 0;
- USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 5 ));
+ USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6));
do
{
@@ -1430,7 +1430,8 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
uint16_t len_words = 0;
uint16_t num_packets = 0;
uint16_t max_hc_pkt_count = 256;
-
+ uint32_t tmpreg = 0;
+
if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
{
if((dma == 0) && (hc->do_ping == 1))
@@ -1483,8 +1484,10 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);
/* Set host channel enable */
- USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
- USBx_HC(hc->ch_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
if (dma == 0) /* Slave mode */
{
@@ -1611,13 +1614,16 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
{
uint8_t num_packets = 1;
+ uint32_t tmpreg = 0;
USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
USB_OTG_HCTSIZ_DOPING;
/* Set host channel enable */
- USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
- USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
return HAL_OK;
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.h
index 134218cc38..7b0b0acc68 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.h
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_ll_usb.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 12-May-2015
+ * @version V1.0.1
+ * @date 25-June-2015
* @brief Header file of USB Core HAL module.
******************************************************************************
* @attention
|