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Update GeneratedSource of 064B0S2 with repo-starging 15347 revision

pull/13122/head
Roman Okhrimenko 2020-06-18 21:45:17 +03:00
parent dcc3559a82
commit 00cbc2d54e
16 changed files with 494 additions and 323 deletions
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8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
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@ -4,13 +4,11 @@
* Description: * Description:
* Wrapper function to initialize all generated code. * Wrapper function to initialize all generated code.
* This file was automatically generated and should not be modified. * This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747 * cfg-backend-cli: 1.2.0.1483
* psoc6pdl 1.6.0.4266 * Device Support Library (libs/psoc6pdl): 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* *
******************************************************************************** ********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation * Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
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@ -4,13 +4,11 @@
* Description: * Description:
* Simple wrapper header containing all generated files. * Simple wrapper header containing all generated files.
* This file was automatically generated and should not be modified. * This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747 * cfg-backend-cli: 1.2.0.1483
* psoc6pdl 1.6.0.4266 * Device Support Library (libs/psoc6pdl): 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* *
******************************************************************************** ********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation * Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
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@ -4,13 +4,11 @@
* Description: * Description:
* Sentinel file for determining if generated source is up to date. * Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified. * This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747 * cfg-backend-cli: 1.2.0.1483
* psoc6pdl 1.6.0.4266 * Device Support Library (libs/psoc6pdl): 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* *
******************************************************************************** ********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation * Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
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@ -4,13 +4,11 @@
* Description: * Description:
* Clock configuration * Clock configuration
* This file was automatically generated and should not be modified. * This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747 * cfg-backend-cli: 1.2.0.1483
* psoc6pdl 1.6.0.4266 * Device Support Library (libs/psoc6pdl): 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* *
******************************************************************************** ********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation * Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
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@ -4,13 +4,11 @@
* Description: * Description:
* Clock configuration * Clock configuration
* This file was automatically generated and should not be modified. * This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747 * cfg-backend-cli: 1.2.0.1483
* psoc6pdl 1.6.0.4266 * Device Support Library (libs/psoc6pdl): 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* *
******************************************************************************** ********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation * Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
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@ -5,13 +5,11 @@
* Contains warnings and errors that occurred while generating code for the * Contains warnings and errors that occurred while generating code for the
* design. * design.
* This file was automatically generated and should not be modified. * This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747 * cfg-backend-cli: 1.2.0.1483
* psoc6pdl 1.6.0.4266 * Device Support Library (libs/psoc6pdl): 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* *
******************************************************************************** ********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation * Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
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@ -4,13 +4,11 @@
* Description: * Description:
* Peripheral Hardware Block configuration * Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified. * This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747 * cfg-backend-cli: 1.2.0.1483
* psoc6pdl 1.6.0.4266 * Device Support Library (libs/psoc6pdl): 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* *
******************************************************************************** ********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation * Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");

10
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
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@ -4,13 +4,11 @@
* Description: * Description:
* Peripheral Hardware Block configuration * Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified. * This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747 * cfg-backend-cli: 1.2.0.1483
* psoc6pdl 1.6.0.4266 * Device Support Library (libs/psoc6pdl): 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* *
******************************************************************************** ********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation * Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");
@ -40,7 +38,7 @@ extern "C" {
#define CYBSP_CSD_ENABLED 1U #define CYBSP_CSD_ENABLED 1U
#define CY_CAPSENSE_CORE 4u #define CY_CAPSENSE_CORE 4u
#define CY_CAPSENSE_CPU_CLK 100000000u #define CY_CAPSENSE_CPU_CLK 100000000u
#define CY_CAPSENSE_PERI_CLK 50000000u #define CY_CAPSENSE_PERI_CLK 100000000u
#define CY_CAPSENSE_VDDA_MV 3300u #define CY_CAPSENSE_VDDA_MV 3300u
#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT #define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
#define CY_CAPSENSE_PERI_DIV_INDEX 0u #define CY_CAPSENSE_PERI_DIV_INDEX 0u

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
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@ -4,13 +4,11 @@
* Description: * Description:
* Pin configuration * Pin configuration
* This file was automatically generated and should not be modified. * This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747 * cfg-backend-cli: 1.2.0.1483
* psoc6pdl 1.6.0.4266 * Device Support Library (libs/psoc6pdl): 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* *
******************************************************************************** ********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation * Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
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@ -4,13 +4,11 @@
* Description: * Description:
* Pin configuration * Pin configuration
* This file was automatically generated and should not be modified. * This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747 * cfg-backend-cli: 1.2.0.1483
* psoc6pdl 1.6.0.4266 * Device Support Library (libs/psoc6pdl): 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* *
******************************************************************************** ********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation * Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
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@ -4,13 +4,11 @@
* Description: * Description:
* Establishes all necessary connections between hardware elements. * Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified. * This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747 * cfg-backend-cli: 1.2.0.1483
* psoc6pdl 1.6.0.4266 * Device Support Library (libs/psoc6pdl): 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* *
******************************************************************************** ********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation * Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");

14
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
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@ -4,13 +4,11 @@
* Description: * Description:
* Establishes all necessary connections between hardware elements. * Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified. * This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747 * cfg-backend-cli: 1.2.0.1483
* psoc6pdl 1.6.0.4266 * Device Support Library (libs/psoc6pdl): 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* *
******************************************************************************** ********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation * Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");
@ -38,7 +36,7 @@ void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing() #define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN #define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT #define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
@ -47,11 +45,11 @@ void init_cycfg_routing(void);
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
#if defined(__cplusplus) #if defined(__cplusplus)
} }

162
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
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@ -4,13 +4,11 @@
* Description: * Description:
* System configuration * System configuration
* This file was automatically generated and should not be modified. * This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747 * cfg-backend-cli: 1.2.0.1483
* psoc6pdl 1.6.0.4266 * Device Support Library (libs/psoc6pdl): 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* *
******************************************************************************** ********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation * Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");
@ -34,7 +32,7 @@
#define CY_CFG_SYSCLK_FLL_ERROR 4 #define CY_CFG_SYSCLK_FLL_ERROR 4
#define CY_CFG_SYSCLK_WCO_ERROR 5 #define CY_CFG_SYSCLK_WCO_ERROR 5
#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 #define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_WCO #define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_CLKLF
#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 #define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
#define CY_CFG_SYSCLK_CLKFAST_DIVIDER 0 #define CY_CFG_SYSCLK_CLKFAST_DIVIDER 0
#define CY_CFG_SYSCLK_FLL_ENABLED 1 #define CY_CFG_SYSCLK_FLL_ENABLED 1
@ -45,14 +43,26 @@
#define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 10U #define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 10U
#define CY_CFG_SYSCLK_FLL_IGAIN 9U #define CY_CFG_SYSCLK_FLL_IGAIN 9U
#define CY_CFG_SYSCLK_FLL_PGAIN 5U #define CY_CFG_SYSCLK_FLL_PGAIN 5U
#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 8U #define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 8
#define CY_CFG_SYSCLK_FLL_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT #define CY_CFG_SYSCLK_FLL_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT
#define CY_CFG_SYSCLK_FLL_CCO_FREQ 355U #define CY_CFG_SYSCLK_FLL_CCO_FREQ 355
#define CY_CFG_SYSCLK_FLL_OUT_FREQ 100000000 #define CY_CFG_SYSCLK_FLL_OUT_FREQ 100000000
#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 #define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE #define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL #define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 #define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF2_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_2
#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF3_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF4_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_ILO_ENABLED 1 #define CY_CFG_SYSCLK_ILO_ENABLED 1
#define CY_CFG_SYSCLK_ILO_HIBERNATE true #define CY_CFG_SYSCLK_ILO_HIBERNATE true
#define CY_CFG_SYSCLK_IMO_ENABLED 1 #define CY_CFG_SYSCLK_IMO_ENABLED 1
@ -60,12 +70,32 @@
#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO #define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL #define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL
#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 0UL
#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM 0UL
#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 #define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
#define CY_CFG_SYSCLK_CLKPERI_DIVIDER 1 #define CY_CFG_SYSCLK_CLKPERI_DIVIDER 0
#define CY_CFG_SYSCLK_PLL0_ENABLED 1
#define CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV 36
#define CY_CFG_SYSCLK_PLL0_REFERENCE_DIV 1
#define CY_CFG_SYSCLK_PLL0_OUTPUT_DIV 2
#define CY_CFG_SYSCLK_PLL0_LF_MODE false
#define CY_CFG_SYSCLK_PLL0_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
#define CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ 144000000
#define CY_CFG_SYSCLK_PLL1_ENABLED 1
#define CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV 30
#define CY_CFG_SYSCLK_PLL1_REFERENCE_DIV 1
#define CY_CFG_SYSCLK_PLL1_OUTPUT_DIV 5
#define CY_CFG_SYSCLK_PLL1_LF_MODE false
#define CY_CFG_SYSCLK_PLL1_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
#define CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ 48000000
#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 #define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
#define CY_CFG_SYSCLK_CLKSLOW_DIVIDER 0 #define CY_CFG_SYSCLK_CLKSLOW_DIVIDER 0
#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1 #define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
#define CY_CFG_SYSCLK_CLKTIMER_SOURCE CY_SYSCLK_CLKTIMER_IN_HF0_NODIV #define CY_CFG_SYSCLK_CLKTIMER_SOURCE CY_SYSCLK_CLKTIMER_IN_IMO
#define CY_CFG_SYSCLK_CLKTIMER_DIVIDER 0U #define CY_CFG_SYSCLK_CLKTIMER_DIVIDER 0U
#define CY_CFG_SYSCLK_WCO_ENABLED 1 #define CY_CFG_SYSCLK_WCO_ENABLED 1
#define CY_CFG_SYSCLK_WCO_IN_PRT GPIO_PRT0 #define CY_CFG_SYSCLK_WCO_IN_PRT GPIO_PRT0
@ -107,6 +137,42 @@
.channel_num = 0U, .channel_num = 0U,
}; };
#endif //defined (CY_USING_HAL) #endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 1U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 2U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
{
.feedbackDiv = 36,
.referenceDiv = 1,
.outputDiv = 2,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
};
#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig =
{
.feedbackDiv = 30,
.referenceDiv = 1,
.outputDiv = 5,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
};
#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
__WEAK void cycfg_ClockStartupError(uint32_t error) __WEAK void cycfg_ClockStartupError(uint32_t error)
{ {
@ -588,7 +654,7 @@ __WEAK void cycfg_ClockStartupError(uint32_t error)
#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
__STATIC_INLINE void Cy_SysClk_ClkBakInit() __STATIC_INLINE void Cy_SysClk_ClkBakInit()
{ {
Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
} }
#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
@ -617,6 +683,30 @@ __WEAK void cycfg_ClockStartupError(uint32_t error)
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
} }
#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
}
#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
}
#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
}
#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
__STATIC_INLINE void Cy_SysClk_IloInit() __STATIC_INLINE void Cy_SysClk_IloInit()
{ {
@ -638,10 +728,48 @@ __WEAK void cycfg_ClockStartupError(uint32_t error)
Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
} }
#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
__STATIC_INLINE void Cy_SysClk_ClkPath1Init()
{
Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
}
#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
__STATIC_INLINE void Cy_SysClk_ClkPath2Init()
{
Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
}
#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
__STATIC_INLINE void Cy_SysClk_ClkPeriInit() __STATIC_INLINE void Cy_SysClk_ClkPeriInit()
{ {
Cy_SysClk_ClkPeriSetDivider(1U); Cy_SysClk_ClkPeriSetDivider(0U);
}
#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
__STATIC_INLINE void Cy_SysClk_Pll0Init()
{
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
}
#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
__STATIC_INLINE void Cy_SysClk_Pll1Init()
{
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
} }
#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
@ -654,7 +782,7 @@ __WEAK void cycfg_ClockStartupError(uint32_t error)
__STATIC_INLINE void Cy_SysClk_ClkTimerInit() __STATIC_INLINE void Cy_SysClk_ClkTimerInit()
{ {
Cy_SysClk_ClkTimerDisable(); Cy_SysClk_ClkTimerDisable();
Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_HF0_NODIV); Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
Cy_SysClk_ClkTimerSetDivider(0U); Cy_SysClk_ClkTimerSetDivider(0U);
Cy_SysClk_ClkTimerEnable(); Cy_SysClk_ClkTimerEnable();
} }
@ -1042,4 +1170,12 @@ void init_cycfg_system(void)
#if defined (CY_USING_HAL) #if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
#endif //defined (CY_USING_HAL) #endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
#endif //defined (CY_USING_HAL)
} }

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
View File

@ -4,13 +4,11 @@
* Description: * Description:
* System configuration * System configuration
* This file was automatically generated and should not be modified. * This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747 * cfg-backend-cli: 1.2.0.1483
* psoc6pdl 1.6.0.4266 * Device Support Library (libs/psoc6pdl): 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* *
******************************************************************************** ********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation * Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");
@ -51,13 +49,26 @@ extern "C" {
#define srss_0_clock_0_hfclk_0_ENABLED 1U #define srss_0_clock_0_hfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF0 0UL #define CY_CFG_SYSCLK_CLKHF0 0UL
#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL #define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
#define srss_0_clock_0_hfclk_2_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF2 2UL
#define CY_CFG_SYSCLK_CLKHF2_CLKPATH_NUM 0UL
#define srss_0_clock_0_hfclk_3_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF3 3UL
#define CY_CFG_SYSCLK_CLKHF3_CLKPATH_NUM 0UL
#define srss_0_clock_0_hfclk_4_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF4 4UL
#define CY_CFG_SYSCLK_CLKHF4_CLKPATH_NUM 0UL
#define srss_0_clock_0_ilo_0_ENABLED 1U #define srss_0_clock_0_ilo_0_ENABLED 1U
#define srss_0_clock_0_imo_0_ENABLED 1U #define srss_0_clock_0_imo_0_ENABLED 1U
#define srss_0_clock_0_lfclk_0_ENABLED 1U #define srss_0_clock_0_lfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 #define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO #define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO
#define srss_0_clock_0_pathmux_0_ENABLED 1U #define srss_0_clock_0_pathmux_0_ENABLED 1U
#define srss_0_clock_0_pathmux_1_ENABLED 1U
#define srss_0_clock_0_pathmux_2_ENABLED 1U
#define srss_0_clock_0_periclk_0_ENABLED 1U #define srss_0_clock_0_periclk_0_ENABLED 1U
#define srss_0_clock_0_pll_0_ENABLED 1U
#define srss_0_clock_0_pll_1_ENABLED 1U
#define srss_0_clock_0_slowclk_0_ENABLED 1U #define srss_0_clock_0_slowclk_0_ENABLED 1U
#define srss_0_clock_0_timerclk_0_ENABLED 1U #define srss_0_clock_0_timerclk_0_ENABLED 1U
#define srss_0_clock_0_wco_0_ENABLED 1U #define srss_0_clock_0_wco_0_ENABLED 1U
@ -81,6 +92,12 @@ extern "C" {
#if defined (CY_USING_HAL) #if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj; extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
#endif //defined (CY_USING_HAL) #endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_system(void); void init_cycfg_system(void);

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
View File

@ -1,4 +1,4 @@
[Device=CY8C624ABZI-D44] [Device=CYB0644ABZI-S2D44]
[Blocks] [Blocks]
# WIFI # WIFI

66
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<Design version="12" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v3"> <Design version="12" xmlns="http://cypress.com/xsd/cydesignfile_v3">
<ToolInfo version="2.2.0.1747"/> <ToolInfo version="1.0.0"/>
<Devices> <Devices>
<Device mpn="CYB0644ABZI-S2D44"> <Device mpn="CYB0644ABZI-S2D44">
<BlockConfig> <BlockConfig>
@ -270,7 +270,7 @@
</Block> </Block>
<Block location="srss[0].clock[0].bakclk[0]"> <Block location="srss[0].clock[0].bakclk[0]">
<Personality template="mxs40bakclk" version="1.0"> <Personality template="mxs40bakclk" version="1.0">
<Param id="sourceClock" value="wco"/> <Param id="sourceClock" value="lfclk"/>
</Personality> </Personality>
</Block> </Block>
<Block location="srss[0].clock[0].fastclk[0]"> <Block location="srss[0].clock[0].fastclk[0]">
@ -279,12 +279,9 @@
</Personality> </Personality>
</Block> </Block>
<Block location="srss[0].clock[0].fll[0]"> <Block location="srss[0].clock[0].fll[0]">
<Personality template="mxs40fll" version="2.0"> <Personality template="mxs40fll" version="1.0">
<Param id="configuration" value="auto"/> <Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value=""/> <Param id="desiredFrequency" value="100.000"/>
<Param id="multiplier" value=""/>
<Param id="reference" value=""/>
<Param id="tolerance" value=""/>
</Personality> </Personality>
</Block> </Block>
<Block location="srss[0].clock[0].hfclk[0]"> <Block location="srss[0].clock[0].hfclk[0]">
@ -293,6 +290,24 @@
<Param id="divider" value="1"/> <Param id="divider" value="1"/>
</Personality> </Personality>
</Block> </Block>
<Block location="srss[0].clock[0].hfclk[2]">
<Personality template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="2"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[3]">
<Personality template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[4]">
<Personality template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].ilo[0]"> <Block location="srss[0].clock[0].ilo[0]">
<Personality template="mxs40ilo" version="1.0"> <Personality template="mxs40ilo" version="1.0">
<Param id="hibernate" value="true"/> <Param id="hibernate" value="true"/>
@ -313,9 +328,35 @@
<Param id="sourceClock" value="imo"/> <Param id="sourceClock" value="imo"/>
</Personality> </Personality>
</Block> </Block>
<Block location="srss[0].clock[0].pathmux[1]">
<Personality template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pathmux[2]">
<Personality template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].periclk[0]"> <Block location="srss[0].clock[0].periclk[0]">
<Personality template="mxs40periclk" version="1.0"> <Personality template="mxs40periclk" version="1.0">
<Param id="divider" value="2"/> <Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pll[0]">
<Personality template="mxs40pll" version="1.0">
<Param id="lowFrequencyMode" value="false"/>
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="144.000"/>
<Param id="optimization" value="MinPower"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pll[1]">
<Personality template="mxs40pll" version="1.0">
<Param id="lowFrequencyMode" value="false"/>
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="48.000"/>
<Param id="optimization" value="MinPower"/>
</Personality> </Personality>
</Block> </Block>
<Block location="srss[0].clock[0].slowclk[0]"> <Block location="srss[0].clock[0].slowclk[0]">
@ -325,7 +366,7 @@
</Block> </Block>
<Block location="srss[0].clock[0].timerclk[0]"> <Block location="srss[0].clock[0].timerclk[0]">
<Personality template="mxs40timerclk" version="1.0"> <Personality template="mxs40timerclk" version="1.0">
<Param id="sourceClock" value="hfclk"/> <Param id="sourceClock" value="imo"/>
<Param id="timerDivider" value="1"/> <Param id="timerDivider" value="1"/>
</Personality> </Personality>
</Block> </Block>
@ -342,8 +383,8 @@
<Block location="srss[0].power[0]"> <Block location="srss[0].power[0]">
<Personality template="mxs40power" version="1.3"> <Personality template="mxs40power" version="1.3">
<Param id="pwrMode" value="LDO_1_1"/> <Param id="pwrMode" value="LDO_1_1"/>
<Param id="actPwrMode" value=""/> <Param id="actPwrMode" value="LP"/>
<Param id="coreRegulator" value=""/> <Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
<Param id="pmicEnable" value="false"/> <Param id="pmicEnable" value="false"/>
<Param id="backupSrc" value="VDDD"/> <Param id="backupSrc" value="VDDD"/>
<Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/> <Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
@ -427,5 +468,6 @@
<Netlist/> <Netlist/>
</Device> </Device>
</Devices> </Devices>
<Libraries/>
<ConfiguratorData/> <ConfiguratorData/>
</Design> </Design>