mirror of https://github.com/milvus-io/milvus.git
fix Milvus docker image report illegal instruction (#2598)
Signed-off-by: yudong.cai <yudong.cai@zilliz.com>pull/2615/head
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290ff2e439
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6ac3d2bd08
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@ -8,6 +8,7 @@ Please mark all change in change log and use the issue from GitHub
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- \#2585 IVF_PQ on GPU with using metric_type IP
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- \#2578 Result count doesn't match target vectors count
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- \#2557 fix random crash of INSERT_DUPLICATE_ID case
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- \#2598 fix Milvus docker image report illegal instruction
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## Feature
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@ -3,6 +3,7 @@
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#include <array>
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#include <bitset>
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#include <cpuid.h>
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#include <cstring>
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#include <iostream>
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#include <string>
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@ -10,58 +11,6 @@
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namespace faiss {
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#if defined(__i386__) && defined(__PIC__)
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/* %ebx may be the PIC register. */
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#if __GNUC__ >= 3
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#define __cpuid(level, a, b, c, d) \
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__asm__( \
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"xchg{l}\t{%%}ebx, %1\n\t" \
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"cpuid\n\t" \
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"xchg{l}\t{%%}ebx, %1\n\t" \
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: "=a"(a), "=r"(b), "=c"(c), "=d"(d) \
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: "0"(level))
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#define __cpuid_count(level, count, a, b, c, d) \
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__asm__( \
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"xchg{l}\t{%%}ebx, %1\n\t" \
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"cpuid\n\t" \
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"xchg{l}\t{%%}ebx, %1\n\t" \
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: "=a"(a), "=r"(b), "=c"(c), "=d"(d) \
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: "0"(level), "2"(count))
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#else /* __GNUC__ >= 3 */
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/* Host GCCs older than 3.0 weren't supporting Intel asm syntax
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nor alternatives in i386 code. */
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#define __cpuid(level, a, b, c, d) \
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__asm__( \
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"xchgl\t%%ebx, %1\n\t" \
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"cpuid\n\t" \
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"xchgl\t%%ebx, %1\n\t" \
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: "=a"(a), "=r"(b), "=c"(c), "=d"(d) \
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: "0"(level))
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#define __cpuid_count(level, count, a, b, c, d) \
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__asm__( \
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"xchgl\t%%ebx, %1\n\t" \
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"cpuid\n\t" \
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"xchgl\t%%ebx, %1\n\t" \
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: "=a"(a), "=r"(b), "=c"(c), "=d"(d) \
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: "0"(level), "2"(count))
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#endif /* __GNUC__ >= 3 */
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#else /* defined(__i386__) && defined(__PIC__) */
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#define __cpuid(level, a, b, c, d) __asm__("cpuid\n\t" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "0"(level))
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#define __cpuid_count(level, count, a, b, c, d) \
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__asm__("cpuid\n\t" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "0"(level), "2"(count))
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#endif /* defined(__i386__) && defined(__PIC__) */
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class InstructionSet {
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public:
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static InstructionSet&
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