596 lines
18 KiB
Go
596 lines
18 KiB
Go
// +build amd64
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// Copyright 2015 Intel Corporation.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// Package cpuid provides access to the information available
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// through the CPUID instruction.
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// All information is gathered during package initialization phase
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// so package's public interface doesn't call CPUID instruction.
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package cpuid
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func cpuid_low(arg1, arg2 uint32) (eax, ebx, ecx, edx uint32) // implemented in cpuidlow_amd64.s
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func xgetbv_low(arg1 uint32) (eax, edx uint32) // implemented in cpuidlow_amd64.s
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func init() {
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detectFeatures()
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}
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func detectFeatures() {
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leaf0()
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leaf1()
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leaf2()
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leaf3()
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leaf4()
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leaf5()
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leaf6()
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leaf7()
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leaf0x80000000()
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leaf0x80000001()
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leaf0x80000004()
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leaf0x80000005()
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leaf0x80000006()
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if HasFeature(OSXSAVE) {
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eax, _ := xgetbv_low(0)
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if (eax & 0x6) == 0x6 {
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EnabledAVX = true
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}
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if (eax & 0xE0) == 0xE0 {
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EnabledAVX512 = true
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}
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}
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}
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var leaf02Names = [...]string{
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"NULL",
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"DATA_CACHE",
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"INSTRUCTION_CACHE",
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"UNIFIED_CACHE",
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"TLB",
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"DTLB",
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"STLB",
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"PREFETCH",
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}
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func leaf0() {
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eax, ebx, ecx, edx := cpuid_low(0, 0)
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maxInputValue = eax
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VendorIdentificatorString = string(int32sToBytes(ebx, edx, ecx))
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brandId = brandStrings[VendorIdentificatorString]
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}
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func leaf1() {
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if maxInputValue < 1 {
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return
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}
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eax, ebx, ecx, edx := cpuid_low(1, 0)
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// Parse EAX
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SteppingId = (eax & 0xF)
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modelId := (eax >> 4) & 0xF
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familyId := (eax >> 8) & 0xF
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ProcessorType = (eax >> 12) & 0x3
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ExtendedModelId := (eax >> 16) & 0xF
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extendedFamilyId := (eax >> 20) & 0xFF
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DisplayFamily = familyId
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DisplayModel = modelId
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if familyId == 0xF {
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DisplayFamily = extendedFamilyId + familyId
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}
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if familyId == 0x6 || familyId == 0xF {
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DisplayModel = ExtendedModelId<<4 + modelId
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}
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// Parse EBX
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brandIndex = ebx & 0xFF
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CacheLineSize = ((ebx >> 8) & 0xFF) << 3
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MaxLogocalCPUId = (ebx >> 16) & 0xFF
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InitialAPICId = (ebx >> 24)
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// Parse ECX & EDX not needed. Ask through HasFeature function
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featureFlags = (uint64(edx) << 32) | uint64(ecx)
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}
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func leaf2() {
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if brandId != INTEL {
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return
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}
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if maxInputValue < 2 {
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return
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}
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bytes := int32sToBytes(cpuid_low(2, 0))
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for i := 0; i < len(bytes); i++ {
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if (i%4 == 0) && (bytes[i+3]&(1<<7) != 0) {
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i += 4
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continue
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}
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if bytes[i] == 0xFF { // it means that we should use leaf 4 for cache info
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CacheDescriptors = CacheDescriptors[0:0]
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break
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}
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CacheDescriptors = append(CacheDescriptors, leaf02Descriptors[int16(bytes[i])])
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}
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}
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func leaf3() {
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if brandId != INTEL {
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return
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}
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if maxInputValue < 3 {
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return
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}
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// TODO SerialNumber for < Pentium 4
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}
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func leaf4() {
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if brandId != INTEL {
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return
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}
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if maxInputValue < 4 {
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return
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}
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cacheId := 0
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for {
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eax, ebx, ecx, _ := cpuid_low(4, uint32(cacheId))
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cacheId++
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cacheType := eax & 0xF
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if cacheType == NULL {
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break
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}
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cacheLevel := (eax >> 5) & 0x7
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// selfInitializingCacheLevel := eax & (1<<8)
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// fullyAssociativeCache := eax & (1<<9)
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// maxNumLogicalCoresSharing := (eax >> 14) & 0x3FF
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// maxNumPhisCores := (eax >> 26) & 0x3F
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systemCoherencyLineSize := (ebx & 0xFFF) + 1
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physicalLinePartions := (ebx>>12)&0x3FF + 1
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waysOfAssiociativity := (ebx>>22)&0x3FF + 1
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numberOfSets := ecx + 1
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// writeBackInvalidate := edx & 1
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// cacheInclusiveness := edx & (1<<1)
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// complexCacheIndexing := edx & (1<<2)
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cacheSize := (waysOfAssiociativity * physicalLinePartions *
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systemCoherencyLineSize * numberOfSets) >> 10
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CacheDescriptors = append(CacheDescriptors,
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CacheDescriptor{int(cacheLevel),
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int(cacheType),
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"",
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int(cacheSize),
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int(waysOfAssiociativity),
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int(systemCoherencyLineSize),
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int(numberOfSets),
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int(physicalLinePartions),
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})
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}
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}
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func leaf5() {
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if maxInputValue < 5 {
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return
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}
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eax, ebx, ecx, _ := cpuid_low(4, 0) // TODO process EDX with C0-C7 C-states
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MonLineSizeMax = eax & (0xFFFF)
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MonLineSizeMax = ebx & (0xFFFF)
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MonitorEMX = (ecx & (1 << 0)) != 0
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MonitorIBE = (ecx & (1 << 1)) != 0
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}
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func leaf6() {
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// Thermal and Power Management Features for Intel
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if maxInputValue < 6 {
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return
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}
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eax, ebx, ecx, _ := cpuid_low(6, 0)
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thermalAndPowerFeatureFlags = (eax & 0xFFFF) | (ecx << 16)
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ThermalSensorInterruptThresholds = ebx & 7
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}
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func leaf7() {
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_, ebx, ecx, _ := cpuid_low(7, 0)
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extendedFeatureFlags = (uint64(ecx) << 32) | uint64(ebx)
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}
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func leaf0x80000000() {
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maxExtendedInputValue, _, _, _ = cpuid_low(0x80000000, 0)
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}
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func leaf0x80000001() {
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if maxExtendedInputValue < 0x80000001 {
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return
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}
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_, _, ecx, edx := cpuid_low(0x80000001, 0)
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//extendedProcessorSignatureAndFeatureBits := eax
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extraFeatureFlags = (uint64(edx) << 32) | uint64(ecx)
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}
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// leaf0x80000004 looks at the Processor Brand String in leaves 0x80000002 through 0x80000004
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func leaf0x80000004() {
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if maxExtendedInputValue < 0x80000004 {
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return
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}
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ProcessorBrandString += string(int32sToBytes(cpuid_low(0x80000002, 0)))
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ProcessorBrandString += string(int32sToBytes(cpuid_low(0x80000003, 0)))
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ProcessorBrandString += string(int32sToBytes(cpuid_low(0x80000004, 0)))
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}
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func leaf0x80000005() {
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// AMD L1 Cache and TLB Information
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if maxExtendedInputValue < 0x80000005 {
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return
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}
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if brandId != AMD {
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return
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}
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eax, ebx, ecx, edx := cpuid_low(0x80000005, 0)
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L1DTlb2and4MAssoc := (eax >> 24) & 0xFF
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L1DTlb2and4MSize := (eax >> 16) & 0xFF
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CacheDescriptors = append(CacheDescriptors,
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CacheDescriptor{1,
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DTLB,
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"DTLB 2M/4M",
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2 * 1024,
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int(L1DTlb2and4MAssoc),
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-1,
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int(L1DTlb2and4MSize),
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0,
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})
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L1ITlb2and4MAssoc := (eax >> 8) & 0xFF
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L1ITlb2and4MSize := (eax) & 0xFF
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CacheDescriptors = append(CacheDescriptors,
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CacheDescriptor{1,
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TLB,
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"ITLB 2M/4M",
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2 * 1024,
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int(L1ITlb2and4MAssoc),
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-1,
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int(L1ITlb2and4MSize),
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0,
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})
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L1DTlb4KAssoc := (ebx >> 24) & 0xFF
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L1DTlb4KSize := (ebx >> 16) & 0xFF
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CacheDescriptors = append(CacheDescriptors,
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CacheDescriptor{1,
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DTLB,
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"DTLB 4K",
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4,
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int(L1DTlb4KAssoc),
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-1,
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int(L1DTlb4KSize),
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0,
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})
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L1ITlb4KAssoc := (ebx >> 8) & 0xFF
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L1ITlb4KSize := (ebx) & 0xFF
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CacheDescriptors = append(CacheDescriptors,
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CacheDescriptor{1,
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TLB,
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"ITLB 4K",
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4,
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int(L1ITlb4KAssoc),
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-1,
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int(L1ITlb4KSize),
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0,
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})
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L1DcSize := (ecx >> 24) & 0xFF
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L1DcAssoc := (ecx >> 16) & 0xFF
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L1DcLinesPerTag := (ecx >> 8) & 0xFF
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L1DcLineSize := (ecx >> 0) & 0xFF
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CacheDescriptors = append(CacheDescriptors,
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CacheDescriptor{1,
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DATA_CACHE,
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"L1 Data cache",
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int(L1DcSize),
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int(L1DcAssoc),
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int(L1DcLineSize),
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-1,
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int(L1DcLinesPerTag),
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})
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L1IcSize := (edx >> 24) & 0xFF
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L1IcAssoc := (edx >> 16) & 0xFF
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L1IcLinesPerTag := (edx >> 8) & 0xFF
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L1IcLineSize := (edx >> 0) & 0xFF
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CacheDescriptors = append(CacheDescriptors,
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CacheDescriptor{1,
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INSTRUCTION_CACHE,
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"L1 Instruction cache",
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int(L1IcSize),
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int(L1IcAssoc),
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int(L1IcLineSize),
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-1,
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int(L1IcLinesPerTag),
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})
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}
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func leaf0x80000006() {
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if maxExtendedInputValue < 0x80000006 {
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return
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}
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var associativityEncodings = map[uint]uint{
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0x00: 0,
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0x01: 1,
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0x02: 2,
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0x04: 4,
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0x06: 8,
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0x08: 16,
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0x0A: 32,
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0x0B: 48,
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0x0C: 64,
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0x0D: 96,
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0x0E: 128,
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0x0F: 0xFF, // - Fully associative
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}
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eax, ebx, ecx, edx := cpuid_low(0x80000006, 0)
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if brandId == INTEL {
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CacheLineSize := (ecx >> 0) & 0xFF
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L2Associativity := uint((ecx >> 12) & 0xF)
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CacheSize := (ecx >> 16) & 0xFFFF
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CacheDescriptors = append(CacheDescriptors,
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CacheDescriptor{2,
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0,
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"Cache info from leaf 0x80000006 for Intel",
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int(CacheSize),
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int(associativityEncodings[L2Associativity]),
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int(CacheLineSize),
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-1,
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0,
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})
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}
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if brandId == AMD {
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L2DTlb2and4MAssoc := uint((eax >> 28) & 0xF)
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L2DTlb2and4MSize := (eax >> 16) & 0xFFF
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CacheDescriptors = append(CacheDescriptors,
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CacheDescriptor{2,
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DTLB,
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"DTLB 2M/4M",
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2 * 1024,
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int(associativityEncodings[L2DTlb2and4MAssoc]),
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-1,
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int(L2DTlb2and4MSize),
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0,
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})
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L2ITlb2and4MAssoc := uint((eax >> 12) & 0xF)
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L2ITlb2and4MSize := (eax) & 0xFFF
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CacheDescriptors = append(CacheDescriptors,
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CacheDescriptor{2,
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TLB,
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"ITLB 2M/4M",
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2 * 1024,
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int(associativityEncodings[L2ITlb2and4MAssoc]),
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-1,
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int(L2ITlb2and4MSize),
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0,
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})
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L2DTlb4KAssoc := uint((ebx >> 28) & 0xF)
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L2DTlb4KSize := (ebx >> 16) & 0xFFF
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CacheDescriptors = append(CacheDescriptors,
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CacheDescriptor{2,
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DTLB,
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"DTLB 4K",
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4,
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int(associativityEncodings[L2DTlb4KAssoc]),
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-1,
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int(L2DTlb4KSize),
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0,
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})
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L2ITlb4KAssoc := uint((ebx >> 12) & 0xF)
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L2ITlb4KSize := (ebx) & 0xFFF
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CacheDescriptors = append(CacheDescriptors,
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CacheDescriptor{2,
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TLB,
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"ITLB 4K",
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4,
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int(associativityEncodings[L2ITlb4KAssoc]),
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-1,
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int(L2ITlb4KSize),
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0,
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})
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L2Size := (ecx >> 16) & 0xFFFF
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L2Assoc := uint((ecx >> 12) & 0xF)
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L2LinesPerTag := (ecx >> 8) & 0xF
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L2LineSize := (ecx >> 0) & 0xFF
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CacheDescriptors = append(CacheDescriptors,
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CacheDescriptor{2,
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DATA_CACHE,
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"L2 Data cache",
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int(L2Size),
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int(associativityEncodings[L2Assoc]),
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int(L2LineSize),
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-1,
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int(L2LinesPerTag),
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})
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L3Size := ((edx >> 18) & 0xF) * 512
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L3Assoc := uint((edx >> 12) & 0xF)
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L3LinesPerTag := (edx >> 8) & 0xF
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L3LineSize := (edx >> 0) & 0xFF
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CacheDescriptors = append(CacheDescriptors,
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CacheDescriptor{3,
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DATA_CACHE,
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"L3 Data cache",
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int(L3Size),
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int(associativityEncodings[L3Assoc]),
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int(L3LineSize),
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-1,
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int(L3LinesPerTag),
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})
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}
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}
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// TODO split fused descritops with bits in high key's byte like for 0x49
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var leaf02Descriptors = map[int16]CacheDescriptor{
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0x01: {-1, TLB, "Instruction TLB", 4, 4, -1, 32, 0},
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0x02: {-1, TLB, "Instruction TLB", 4 * 1024, 0xFF, -1, 2, 0},
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0x03: {-1, TLB, "Data TLB", 4, 4, -1, 64, 0},
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0x04: {-1, TLB, "Data TLB", 4 * 1024, 4, -1, 8, 0},
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0x05: {-1, TLB, "Data TLB1", 4 * 1024, 4, -1, 32, 0},
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0x06: {1, INSTRUCTION_CACHE, "1st-level instruction cache", 8, 4, 32, -1, 0},
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0x08: {1, INSTRUCTION_CACHE, "1st-level instruction cache", 16, 4, 32, -1, 0},
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0x09: {1, INSTRUCTION_CACHE, "1st-level instruction cache", 32, 4, 64, -1, 0},
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0x0A: {1, DATA_CACHE, "1st-level data cache", 8, 2, 32, -1, 0},
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0x0B: {-1, TLB, "Instruction TLB", 4 * 1024, 4, -1, 4, 0},
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0x0C: {1, DATA_CACHE, "1st-level data cache", 16, 4, 32, -1, 0},
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0x0D: {1, DATA_CACHE, "1st-level data cache", 16, 4, 64, -1, 0},
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0x0E: {1, DATA_CACHE, "1st-level data cache", 24, 6, 64, -1, 0},
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0x1D: {2, DATA_CACHE, "2nd-level cache", 128, 2, 64, -1, 0},
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0x21: {2, DATA_CACHE, "2nd-level cache", 256, 8, 64, -1, 0},
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0x22: {3, DATA_CACHE, "3nd-level cache", 512, 4, 64, -1, 2},
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0x23: {3, DATA_CACHE, "3nd-level cache", 1 * 1024, 8, 64, -1, 2},
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0x24: {2, DATA_CACHE, "2nd-level cache", 1 * 1024, 16, 64, -1, 0},
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0x25: {3, DATA_CACHE, "3nd-level cache", 2 * 1024, 8, 64, -1, 2},
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0x29: {3, DATA_CACHE, "2nd-level cache", 4 * 1024, 8, 64, -1, 2},
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0x2C: {1, DATA_CACHE, "1st-level cache", 32, 8, 64, -1, 0},
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0x30: {1, INSTRUCTION_CACHE, "1st-level instruction cache", 32, 8, 64, -1, 0},
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0x40: {-1, DATA_CACHE, "No 2nd-level cache or, if processor contains a " +
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"valid 2nd-level cache, no 3rd-level cache", -1, -1, -1, -1, 0},
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0x41: {2, DATA_CACHE, "2nd-level cache", 128, 4, 32, -1, 0},
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0x42: {2, DATA_CACHE, "2nd-level cache", 256, 4, 32, -1, 0},
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0x43: {2, DATA_CACHE, "2nd-level cache", 512, 4, 32, -1, 0},
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0x44: {2, DATA_CACHE, "2nd-level cache", 1 * 1024, 4, 32, -1, 0},
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0x45: {2, DATA_CACHE, "2nd-level cache", 2 * 1024, 4, 32, -1, 0},
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0x46: {3, DATA_CACHE, "3nd-level cache", 4 * 1024, 4, 64, -1, 0},
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0x47: {3, DATA_CACHE, "3nd-level cache", 8 * 1024, 8, 64, -1, 0},
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0x48: {2, DATA_CACHE, "2nd-level cache", 3 * 1024, 12, 64, -1, 0},
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0x49: {2, DATA_CACHE, "2nd-level cache", 4 * 1024, 16, 64, -1, 0},
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// (Intel Xeon processor MP, Family 0FH, Model 06H)
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(0x49 | (1 << 8)): {3, DATA_CACHE, "3nd-level cache", 4 * 1024, 16, 64, -1, 0},
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0x4A: {3, DATA_CACHE, "3nd-level cache", 6 * 1024, 12, 64, -1, 0},
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0x4B: {3, DATA_CACHE, "3nd-level cache", 8 * 1024, 16, 64, -1, 0},
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0x4C: {3, DATA_CACHE, "3nd-level cache", 12 * 1024, 12, 64, -1, 0},
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0x4D: {3, DATA_CACHE, "3nd-level cache", 16 * 1024, 16, 64, -1, 0},
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0x4E: {2, DATA_CACHE, "3nd-level cache", 6 * 1024, 24, 64, -1, 0},
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0x4F: {-1, TLB, "Instruction TLB", 4, -1, -1, 32, 0},
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0x50: {-1, TLB, "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages", 4, -1, -1, 64, 0},
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0x51: {-1, TLB, "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages", 4, -1, -1, 128, 0},
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0x52: {-1, TLB, "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages", 4, -1, -1, 256, 0},
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0x55: {-1, TLB, "Instruction TLB: 2-MByte or 4-MByte pages", 2 * 1024, 0xFF, -1, 7, 0},
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0x56: {-1, TLB, "Data TLB0", 4 * 1024, 4, -1, 16, 0},
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0x57: {-1, TLB, "Data TLB0", 4, 4, -1, 16, 0},
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0x59: {-1, TLB, "Data TLB0", 4, 0xFF, -1, 16, 0},
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0x5A: {-1, TLB, "Data TLB0 2-MByte or 4 MByte pages", 2 * 1024, 4, -1, 32, 0},
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0x5B: {-1, TLB, "Data TLB 4 KByte and 4 MByte pages", 4, -1, -1, 64, 0},
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0x5C: {-1, TLB, "Data TLB 4 KByte and 4 MByte pages", 4, -1, -1, 128, 0},
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0x5D: {-1, TLB, "Data TLB 4 KByte and 4 MByte pages", 4, -1, -1, 256, 0},
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0x60: {1, DATA_CACHE, "1st-level data cache", 16, 8, 64, -1, 0},
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0x61: {-1, TLB, "Instruction TLB", 4, 0xFF, -1, 48, 0},
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0x63: {-1, TLB, "Data TLB", 1 * 1024 * 1024, 4, -1, 4, 0},
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0x66: {1, DATA_CACHE, "1st-level data cache", 8, 4, 64, -1, 0},
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0x67: {1, DATA_CACHE, "1st-level data cache", 16, 4, 64, -1, 0},
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0x68: {1, DATA_CACHE, "1st-level data cache", 32, 4, 64, -1, 0},
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0x70: {1, INSTRUCTION_CACHE, "Trace cache (size in K of uop)", 12, 8, -1, -1, 0},
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0x71: {1, INSTRUCTION_CACHE, "Trace cache (size in K of uop)", 16, 8, -1, -1, 0},
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0x72: {1, INSTRUCTION_CACHE, "Trace cache (size in K of uop)", 32, 8, -1, -1, 0},
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0x76: {-1, TLB, "Instruction TLB: 2M/4M pages", 2 * 1024, 0xFF, -1, 8, 0},
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0x78: {2, DATA_CACHE, "2nd-level cache", 1 * 1024, 4, 64, -1, 0},
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0x79: {2, DATA_CACHE, "2nd-level cache", 128, 8, 64, -1, 2},
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0x7A: {2, DATA_CACHE, "2nd-level cache", 256, 8, 64, -1, 2},
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0x7B: {2, DATA_CACHE, "2nd-level cache", 512, 8, 64, -1, 2},
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0x7C: {2, DATA_CACHE, "2nd-level cache", 1 * 1024, 8, 64, -1, 2},
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0x7D: {2, DATA_CACHE, "2nd-level cache", 2 * 1024, 8, 64, -1, 0},
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0x7F: {2, DATA_CACHE, "2nd-level cache", 512, 2, 64, -1, 0},
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0x80: {2, DATA_CACHE, "2nd-level cache", 512, 8, 64, -1, 0},
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0x82: {2, DATA_CACHE, "2nd-level cache", 256, 8, 32, -1, 0},
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0x83: {2, DATA_CACHE, "2nd-level cache", 512, 8, 32, -1, 0},
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0x84: {2, DATA_CACHE, "2nd-level cache", 1 * 1024, 8, 32, -1, 0},
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0x85: {2, DATA_CACHE, "2nd-level cache", 2 * 1024, 8, 32, -1, 0},
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0x86: {2, DATA_CACHE, "2nd-level cache", 512, 4, 32, -1, 0},
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0x87: {2, DATA_CACHE, "2nd-level cache", 1 * 1024, 8, 64, -1, 0},
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0xA0: {-1, DTLB, "DTLB", 4, 0xFF, -1, 32, 0},
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0xB0: {-1, TLB, "Instruction TLB", 4, 4, -1, 128, 0},
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0xB1: {-1, TLB, "Instruction TLB 2M pages 4 way 8 entries or" +
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"4M pages 4-way, 4 entries", 2 * 1024, 4, -1, 8, 0},
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0xB2: {-1, TLB, "Instruction TLB", 4, 4, -1, 64, 0},
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0xB3: {-1, TLB, "Data TLB", 4, 4, -1, 128, 0},
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0xB4: {-1, TLB, "Data TLB1", 4, 4, -1, 256, 0},
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0xB5: {-1, TLB, "Instruction TLB", 4, 8, -1, 64, 0},
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0xB6: {-1, TLB, "Instruction TLB", 4, 8, -1, 128, 0},
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0xBA: {-1, TLB, "Data TLB1", 4, 4, -1, 64, 0},
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0xC0: {-1, TLB, "Data TLB: 4 KByte and 4 MByte pages", 4, 4, -1, 8, 0},
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0xC1: {-1, STLB, "Shared 2nd-Level TLB: 4Kbyte and 2Mbyte pages", 4, 8, -1, 1024, 0},
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0xC2: {-1, DTLB, "DTLB 4KByte/2 MByte pages", 4, 4, -1, 16, 0},
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0xC3: {-1, STLB, "Shared 2nd-Level TLB: " +
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"4 KByte /2 MByte pages, 6-way associative, 1536 entries." +
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"Also 1GBbyte pages, 4-way,16 entries.", 4, 6, -1, 1536, 0},
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0xCA: {-1, STLB, "Shared 2nd-Level TLB", 4, 4, -1, 512, 0},
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0xD0: {3, DATA_CACHE, "3nd-level cache", 512, 4, 64, -1, 0},
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0xD1: {3, DATA_CACHE, "3nd-level cache", 1 * 1024, 4, 64, -1, 0},
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0xD2: {3, DATA_CACHE, "3nd-level cache", 2 * 1024, 4, 64, -1, 0},
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0xD6: {3, DATA_CACHE, "3nd-level cache", 1 * 1024, 8, 64, -1, 0},
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0xD7: {3, DATA_CACHE, "3nd-level cache", 2 * 1024, 8, 64, -1, 0},
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0xD8: {3, DATA_CACHE, "3nd-level cache", 4 * 1024, 8, 64, -1, 0},
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0xDC: {3, DATA_CACHE, "3nd-level cache", 1 * 1536, 12, 64, -1, 0},
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0xDD: {3, DATA_CACHE, "3nd-level cache", 3 * 1024, 12, 64, -1, 0},
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0xDE: {3, DATA_CACHE, "3nd-level cache", 6 * 1024, 12, 64, -1, 0},
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0xE2: {3, DATA_CACHE, "3nd-level cache", 2 * 1024, 16, 64, -1, 0},
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0xE3: {3, DATA_CACHE, "3nd-level cache", 4 * 1024, 16, 64, -1, 0},
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0xE4: {3, DATA_CACHE, "3nd-level cache", 8 * 1024, 16, 64, -1, 0},
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0xEA: {3, DATA_CACHE, "3nd-level cache", 12 * 1024, 24, 64, -1, 0},
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0xEB: {3, DATA_CACHE, "3nd-level cache", 18 * 1024, 24, 64, -1, 0},
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0xEC: {3, DATA_CACHE, "3nd-level cache", 24 * 1024, 24, 64, -1, 0},
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0xF0: {-1, PREFETCH, "", 64, -1, -1, -1, 0},
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0xF1: {-1, PREFETCH, "", 128, -1, -1, -1, 0},
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0xFF: {-1, NULL, "CPUID leaf 2 does not report cache descriptor " +
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"information, use CPUID leaf 4 to query cache parameters",
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-1, -1, -1, -1, 0},
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}
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func int32sToBytes(args ...uint32) []byte {
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var result []byte
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for _, arg := range args {
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result = append(result,
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byte((arg)&0xFF),
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byte((arg>>8)&0xFF),
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byte((arg>>16)&0xFF),
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byte((arg>>24)&0xFF))
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}
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return result
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}
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