mirror of https://github.com/ARMmbed/mbed-os.git
237 lines
8.2 KiB
C
237 lines
8.2 KiB
C
/*******************************************************************************
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* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*
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* $Date: 2016-06-21 16:19:28 -0500 (Tue, 21 Jun 2016) $
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* $Revision: 23450 $
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*
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******************************************************************************/
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#include <stdio.h>
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#include <stddef.h>
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#include "mxc_config.h"
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#include "mxc_assert.h"
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#include "pmu.h"
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#if (MXC_PMU_REV == 0)
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/* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 -- workaround */
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#include "clkman_regs.h"
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/* Channel 5 infinite loop program */
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static const uint32_t pmu_0[] = {
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PMU_JUMP(0, 0, (uint32_t)pmu_0)
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};
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#endif
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static void (*callbacks[MXC_CFG_PMU_CHANNELS])(int);
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/******************************************************************************/
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void PMU_Handler(void)
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{
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int channel;
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uint32_t cfg1, cfg2;
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mxc_pmu_regs_t *MXC_PMUn;
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for (channel = 0; channel < MXC_CFG_PMU_CHANNELS; channel++) {
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MXC_PMUn = &MXC_PMU0[channel];
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if (MXC_PMUn->cfg & MXC_F_PMU_CFG_INTERRUPT) {
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cfg1 = MXC_PMUn->cfg;
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/* Since any set flags will be cleared by the write-back below, mask them off */
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cfg2 = cfg1 & ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT);
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/* Clear the interrupt flag */
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MXC_PMUn->cfg = cfg2 | MXC_F_PMU_CFG_INTERRUPT;
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if (callbacks[channel]) {
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callbacks[channel](cfg1);
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}
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}
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}
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}
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/******************************************************************************/
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int PMU_Start(unsigned int channel, const void *program_address, pmu_callback callback)
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{
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if(channel >= MXC_CFG_PMU_CHANNELS)
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return E_BAD_PARAM;
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mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
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uint32_t cfg = MXC_PMUn->cfg;
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/* is this channel already running? */
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if (cfg & MXC_F_PMU_CFG_ENABLE) {
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return E_BUSY;
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}
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#if (MXC_PMU_REV == 0)
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/* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 */
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if (channel == 5) {
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/* Channel 5 is used for the work-around */
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return E_BUSY;
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}
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/* Select always-ON clock for PMU */
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MXC_CLKMAN->clk_gate_ctrl0 |= MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER;
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/* Start channel 5 with infinite-loop program */
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MXC_PMU5->cfg &= ~MXC_F_PMU_CFG_ENABLE; /* Clear enable and wipe W1C flags */
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MXC_PMU5->dscadr = (uint32_t)pmu_0;
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MXC_PMU5->cfg = MXC_F_PMU_CFG_ENABLE | (0x1c << MXC_F_PMU_CFG_BURST_SIZE_POS);
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#endif
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/* Set callback */
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callbacks[channel] = callback;
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/* Set start op-code */
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MXC_PMUn->dscadr = (uint32_t)program_address;
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/* Configure the channel */
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cfg = (cfg & ~(MXC_F_PMU_CFG_MANUAL | MXC_F_PMU_CFG_BURST_SIZE)) | (0x1c << MXC_F_PMU_CFG_BURST_SIZE_POS);
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/* Enable if necessary */
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if (callback) {
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cfg |= MXC_F_PMU_CFG_INT_EN;
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} else {
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cfg &= ~MXC_F_PMU_CFG_INT_EN;
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}
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/* Start the channel */
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cfg |= MXC_F_PMU_CFG_ENABLE;
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/*If any W1C flags are set, this write will clear them */
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MXC_PMUn->cfg = cfg;
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return E_NO_ERROR;
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}
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/******************************************************************************/
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void PMU_Stop(unsigned int channel)
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{
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mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
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uint32_t cfg = MXC_PMUn->cfg;
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/* Since any set flags will be cleared by the write-back below, mask them off */
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cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT);
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/* Clear the enable bit to stop the channel */
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cfg &= ~MXC_F_PMU_CFG_ENABLE;
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MXC_PMUn->cfg = cfg;
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/* Remove callback */
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callbacks[channel] = NULL;
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#if (MXC_PMU_REV == 0)
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/* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 */
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/* Check channels 0-4 for any running channels. If none found, stop channel 5 */
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if ((MXC_PMU0->cfg & MXC_F_PMU_CFG_ENABLE) == 0 &&
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(MXC_PMU1->cfg & MXC_F_PMU_CFG_ENABLE) == 0 &&
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(MXC_PMU2->cfg & MXC_F_PMU_CFG_ENABLE) == 0 &&
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(MXC_PMU3->cfg & MXC_F_PMU_CFG_ENABLE) == 0 &&
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(MXC_PMU4->cfg & MXC_F_PMU_CFG_ENABLE) == 0) {
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MXC_PMU5->cfg &= ~MXC_F_PMU_CFG_ENABLE;
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}
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#endif
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}
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/******************************************************************************/
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int PMU_SetCounter(unsigned int channel, unsigned int counter, uint16_t value)
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{
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if((channel >= MXC_CFG_PMU_CHANNELS) || counter > 1)
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return E_BAD_PARAM;
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mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
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if (counter == 0) {
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MXC_PMUn->loop = (MXC_PMUn->loop & ~MXC_F_PMU_LOOP_COUNTER_0) | (value << MXC_F_PMU_LOOP_COUNTER_0_POS);
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} else {
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MXC_PMUn->loop = (MXC_PMUn->loop & ~MXC_F_PMU_LOOP_COUNTER_1) | (value << MXC_F_PMU_LOOP_COUNTER_1_POS);
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}
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return E_NO_ERROR;
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}
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/******************************************************************************/
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int PMU_SetTimeout(unsigned int channel, pmu_ps_sel_t timeoutClkScale, pmu_to_sel_t timeoutTicks)
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{
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if(channel >= MXC_CFG_PMU_CHANNELS)
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return E_BAD_PARAM;
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mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
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uint32_t cfg = MXC_PMUn->cfg;
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/* Since any set flags will be cleared by the write-back below, mask them off */
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cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT);
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/* Adjust timeout settings */
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cfg &= ~(MXC_F_PMU_CFG_TO_SEL | MXC_F_PMU_CFG_PS_SEL);
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cfg |= ((timeoutClkScale << MXC_F_PMU_CFG_PS_SEL_POS) & MXC_F_PMU_CFG_PS_SEL) |
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((timeoutTicks << MXC_F_PMU_CFG_TO_SEL_POS) & MXC_F_PMU_CFG_TO_SEL);
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MXC_PMUn->cfg = cfg;
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return E_NO_ERROR;
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}
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/******************************************************************************/
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uint32_t PMU_GetFlags(unsigned int channel)
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{
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mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
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uint32_t cfg = MXC_PMUn->cfg;
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/* Mask off configuration bits leaving only flag bits */
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cfg &= ~(MXC_F_PMU_CFG_ENABLE | MXC_F_PMU_CFG_MANUAL | MXC_F_PMU_CFG_TO_SEL | MXC_F_PMU_CFG_PS_SEL |
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MXC_F_PMU_CFG_INT_EN | MXC_F_PMU_CFG_BURST_SIZE);
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return cfg;
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}
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/******************************************************************************/
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void PMU_ClearFlags(unsigned int channel, unsigned int mask)
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{
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mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
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uint32_t cfg = MXC_PMUn->cfg;
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/* Since any set flags will be cleared by the write-back below, mask them off */
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cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT);
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/* Now, apply the caller-supplied bits to clear */
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cfg |= mask;
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MXC_PMUn->cfg = cfg;
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}
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/******************************************************************************/
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uint32_t PMU_IsActive(unsigned int channel)
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{
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mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
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return (MXC_PMUn->cfg & MXC_F_PMU_CFG_ENABLE);
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}
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