mirror of https://github.com/ARMmbed/mbed-os.git
1034 lines
31 KiB
C
1034 lines
31 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2015-2016 Nuvoton
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "i2c_api.h"
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#if DEVICE_I2C
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#include "cmsis.h"
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#include "pinmap.h"
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#include "PeripheralPins.h"
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#include "nu_modutil.h"
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#include "nu_miscutil.h"
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#include "nu_bitutil.h"
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#include "mbed_critical.h"
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#define NU_I2C_DEBUG 0
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#if NU_I2C_DEBUG
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struct i2c_s MY_I2C;
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struct i2c_s MY_I2C_2;
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char MY_I2C_STATUS[64];
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int MY_I2C_STATUS_POS = 0;
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uint32_t MY_I2C_TIMEOUT;
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uint32_t MY_I2C_ELAPSED;
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uint32_t MY_I2C_T1;
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uint32_t MY_I2C_T2;
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#endif
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struct nu_i2c_var {
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i2c_t * obj;
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void (*vec)(void);
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};
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static void i2c0_vec(void);
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static void i2c1_vec(void);
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static void i2c2_vec(void);
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static void i2c3_vec(void);
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static void i2c4_vec(void);
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static void i2c_irq(i2c_t *obj);
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static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl);
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static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked);
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static struct nu_i2c_var i2c0_var = {
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.obj = NULL,
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.vec = i2c0_vec,
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};
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static struct nu_i2c_var i2c1_var = {
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.obj = NULL,
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.vec = i2c1_vec,
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};
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static struct nu_i2c_var i2c2_var = {
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.obj = NULL,
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.vec = i2c2_vec,
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};
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static struct nu_i2c_var i2c3_var = {
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.obj = NULL,
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.vec = i2c3_vec,
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};
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static struct nu_i2c_var i2c4_var = {
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.obj = NULL,
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.vec = i2c4_vec,
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};
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static uint32_t i2c_modinit_mask = 0;
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static const struct nu_modinit_s i2c_modinit_tab[] = {
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{I2C_0, I2C0_MODULE, 0, 0, I2C0_RST, I2C0_IRQn, &i2c0_var},
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{I2C_1, I2C1_MODULE, 0, 0, I2C1_RST, I2C1_IRQn, &i2c1_var},
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{I2C_2, I2C2_MODULE, 0, 0, I2C2_RST, I2C2_IRQn, &i2c2_var},
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{I2C_3, I2C3_MODULE, 0, 0, I2C3_RST, I2C3_IRQn, &i2c3_var},
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{I2C_4, I2C4_MODULE, 0, 0, I2C4_RST, I2C4_IRQn, &i2c4_var},
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{NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
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};
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static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata);
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static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync);
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#define NU_I2C_TIMEOUT_STAT_INT 500000
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#define NU_I2C_TIMEOUT_STOP 500000
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static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout);
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static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout);
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//static int i2c_is_stat_int(i2c_t *obj);
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//static int i2c_is_stop_det(i2c_t *obj);
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static int i2c_is_trsn_done(i2c_t *obj);
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static int i2c_is_tran_started(i2c_t *obj);
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static int i2c_addr2data(int address, int read);
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#if DEVICE_I2CSLAVE
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// Convert mbed address to BSP address.
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static int i2c_addr2bspaddr(int address);
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#endif // #if DEVICE_I2CSLAVE
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static void i2c_enable_int(i2c_t *obj);
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static void i2c_disable_int(i2c_t *obj);
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static int i2c_set_int(i2c_t *obj, int inten);
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#if DEVICE_I2C_ASYNCH
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static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
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static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable);
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static void i2c_rollback_vector_interrupt(i2c_t *obj);
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#endif
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#define TRANCTRL_STARTED (1)
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#define TRANCTRL_NAKLASTDATA (1 << 1)
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#define TRANCTRL_LASTDATANAKED (1 << 2)
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uint32_t us_ticker_read(void);
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void i2c_init(i2c_t *obj, PinName sda, PinName scl)
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{
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uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
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uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
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obj->i2c.i2c = (I2CName) pinmap_merge(i2c_sda, i2c_scl);
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MBED_ASSERT((int)obj->i2c.i2c != NC);
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const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
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MBED_ASSERT(modinit != NULL);
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MBED_ASSERT(modinit->modname == obj->i2c.i2c);
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// Reset this module
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SYS_ResetModule(modinit->rsetidx);
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// Enable IP clock
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CLK_EnableModuleClock(modinit->clkidx);
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pinmap_pinout(sda, PinMap_I2C_SDA);
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pinmap_pinout(scl, PinMap_I2C_SCL);
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#if DEVICE_I2C_ASYNCH
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obj->i2c.dma_usage = DMA_USAGE_NEVER;
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obj->i2c.event = 0;
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obj->i2c.stop = 0;
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obj->i2c.address = 0;
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#endif
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// NOTE: Setting I2C bus clock to 100 KHz is required. See I2C::I2C in common/I2C.cpp.
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I2C_Open((I2C_T *) NU_MODBASE(obj->i2c.i2c), 100000);
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// NOTE: INTEN bit and FSM control bits (STA, STO, SI, AA) are packed in one register CTL. We cannot control interrupt through
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// INTEN bit without impacting FSM control bits. Use NVIC_EnableIRQ/NVIC_DisableIRQ instead for interrupt control.
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I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
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i2c_base->CTL |= (I2C_CTL_INTEN_Msk | I2C_CTL_I2CEN_Msk);
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// Enable sync-moce vector interrupt.
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struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
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var->obj = obj;
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obj->i2c.tran_ctrl = 0;
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obj->i2c.stop = 0;
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i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);
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// Mark this module to be inited.
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int i = modinit - i2c_modinit_tab;
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i2c_modinit_mask |= 1 << i;
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}
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int i2c_start(i2c_t *obj)
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{
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return i2c_do_trsn(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk, 1);
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}
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int i2c_stop(i2c_t *obj)
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{
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return i2c_do_trsn(obj, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk, 1);
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}
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void i2c_frequency(i2c_t *obj, int hz)
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{
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I2C_SetBusClockFreq((I2C_T *) NU_MODBASE(obj->i2c.i2c), hz);
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}
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int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
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{
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if (i2c_start(obj)) {
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i2c_stop(obj);
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return I2C_ERROR_BUS_BUSY;
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}
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if (i2c_byte_write(obj, i2c_addr2data(address, 1)) != 1) {
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i2c_stop(obj);
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return I2C_ERROR_NO_SLAVE;
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}
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// Read in bytes
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length = i2c_do_tran(obj, data, length, 1, 1);
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// If not repeated start, send stop.
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if (stop) {
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i2c_stop(obj);
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}
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return length;
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}
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int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
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{
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if (i2c_start(obj)) {
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i2c_stop(obj);
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return I2C_ERROR_BUS_BUSY;
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}
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if (i2c_byte_write(obj, i2c_addr2data(address, 0)) != 1) {
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i2c_stop(obj);
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return I2C_ERROR_NO_SLAVE;
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}
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// Write out bytes
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length = i2c_do_tran(obj, (char *) data, length, 0, 1);
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if (stop) {
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i2c_stop(obj);
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}
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return length;
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}
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void i2c_reset(i2c_t *obj)
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{
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i2c_stop(obj);
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}
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int i2c_byte_read(i2c_t *obj, int last)
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{
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char data = 0;
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i2c_do_tran(obj, &data, 1, 1, last);
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return data;
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}
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int i2c_byte_write(i2c_t *obj, int data)
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{
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char data_[1];
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data_[0] = data & 0xFF;
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if (i2c_do_tran(obj, data_, 1, 0, 0) == 1 &&
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! (obj->i2c.tran_ctrl & TRANCTRL_LASTDATANAKED)) {
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return 1;
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}
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else {
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return 0;
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}
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}
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#if DEVICE_I2CSLAVE
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// See I2CSlave.h
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#define NoData 0 // the slave has not been addressed
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#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
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#define WriteGeneral 2 // the master is writing to all slave
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#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
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void i2c_slave_mode(i2c_t *obj, int enable_slave)
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{
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I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
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i2c_disable_int(obj);
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obj->i2c.slaveaddr_state = NoData;
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// Switch to not addressed mode
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I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
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i2c_enable_int(obj);
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}
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int i2c_slave_receive(i2c_t *obj)
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{
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int slaveaddr_state;
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i2c_disable_int(obj);
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slaveaddr_state = obj->i2c.slaveaddr_state;
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i2c_enable_int(obj);
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return slaveaddr_state;
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}
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int i2c_slave_read(i2c_t *obj, char *data, int length)
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{
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return i2c_do_tran(obj, data, length, 1, 1);
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}
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int i2c_slave_write(i2c_t *obj, const char *data, int length)
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{
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return i2c_do_tran(obj, (char *) data, length, 0, 1);
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}
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void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
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{
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I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
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i2c_disable_int(obj);
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I2C_SetSlaveAddr(i2c_base, 0, i2c_addr2bspaddr(address), I2C_GCMODE_ENABLE);
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i2c_enable_int(obj);
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}
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static int i2c_addr2bspaddr(int address)
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{
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return (address >> 1);
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}
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#endif // #if DEVICE_I2CSLAVE
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static void i2c_enable_int(i2c_t *obj)
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{
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const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
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core_util_critical_section_enter();
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// Enable I2C interrupt
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NVIC_EnableIRQ(modinit->irq_n);
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obj->i2c.inten = 1;
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core_util_critical_section_exit();
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}
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static void i2c_disable_int(i2c_t *obj)
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{
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const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
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core_util_critical_section_enter();
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// Disable I2C interrupt
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NVIC_DisableIRQ(modinit->irq_n);
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obj->i2c.inten = 0;
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core_util_critical_section_exit();
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}
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static int i2c_set_int(i2c_t *obj, int inten)
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{
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int inten_back;
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core_util_critical_section_enter();
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inten_back = obj->i2c.inten;
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core_util_critical_section_exit();
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if (inten) {
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i2c_enable_int(obj);
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}
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else {
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i2c_disable_int(obj);
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}
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return inten_back;
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}
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static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata)
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{
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if (! buf || ! length) {
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return 0;
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}
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int tran_len = 0;
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i2c_disable_int(obj);
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obj->i2c.tran_ctrl = naklastdata ? (TRANCTRL_STARTED | TRANCTRL_NAKLASTDATA) : TRANCTRL_STARTED;
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obj->i2c.tran_beg = buf;
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obj->i2c.tran_pos = buf;
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obj->i2c.tran_end = buf + length;
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i2c_enable_int(obj);
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if (i2c_poll_tran_heatbeat_timeout(obj, NU_I2C_TIMEOUT_STAT_INT)) {
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#if NU_I2C_DEBUG
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MY_I2C_2 = obj->i2c;
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while (1);
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#endif
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}
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else {
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i2c_disable_int(obj);
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tran_len = obj->i2c.tran_pos - obj->i2c.tran_beg;
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obj->i2c.tran_beg = NULL;
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obj->i2c.tran_pos = NULL;
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obj->i2c.tran_end = NULL;
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i2c_enable_int(obj);
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}
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return tran_len;
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}
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static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync)
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{
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I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
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int err = 0;
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i2c_disable_int(obj);
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if (i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
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err = I2C_ERROR_BUS_BUSY;
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#if NU_I2C_DEBUG
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MY_I2C_2 = obj->i2c;
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while (1);
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#endif
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}
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else {
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#if 1
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// NOTE: Avoid duplicate Start/Stop. Otherwise, we may meet strange error.
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uint32_t status = I2C_GET_STATUS(i2c_base);
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switch (status) {
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case 0x08: // Start
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case 0x10: // Master Repeat Start
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if (i2c_ctl & I2C_CTL_STA_Msk) {
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return 0;
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}
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else {
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break;
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}
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case 0xF8: // Bus Released
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if (i2c_ctl & (I2C_CTL_STA_Msk | I2C_CTL_STO_Msk) == I2C_CTL_STO_Msk) {
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return 0;
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}
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else {
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break;
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}
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}
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#endif
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I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
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if (sync && i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
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err = I2C_ERROR_BUS_BUSY;
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#if NU_I2C_DEBUG
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MY_I2C_2 = obj->i2c;
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while (1);
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#endif
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}
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}
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i2c_enable_int(obj);
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return err;
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}
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static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout)
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{
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uint32_t t1, t2, elapsed = 0;
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int status_assert = 0;
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t1 = us_ticker_read();
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while (1) {
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status_assert = is_status(obj);
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if (status_assert) {
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break;
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}
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t2 = us_ticker_read();
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elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
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if (elapsed >= timeout) {
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#if NU_I2C_DEBUG
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MY_I2C_T1 = t1;
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MY_I2C_T2 = t2;
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MY_I2C_ELAPSED = elapsed;
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MY_I2C_TIMEOUT = timeout;
|
|
MY_I2C_2 = obj->i2c;
|
|
while (1);
|
|
#endif
|
|
break;
|
|
}
|
|
}
|
|
|
|
return (elapsed >= timeout);
|
|
}
|
|
|
|
static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout)
|
|
{
|
|
uint32_t t1, t2, elapsed = 0;
|
|
int tran_started;
|
|
char *tran_pos = NULL;
|
|
char *tran_pos2 = NULL;
|
|
|
|
i2c_disable_int(obj);
|
|
tran_pos = obj->i2c.tran_pos;
|
|
i2c_enable_int(obj);
|
|
t1 = us_ticker_read();
|
|
while (1) {
|
|
i2c_disable_int(obj);
|
|
tran_started = i2c_is_tran_started(obj);
|
|
i2c_enable_int(obj);
|
|
if (! tran_started) { // Transfer completed or stopped
|
|
break;
|
|
}
|
|
|
|
i2c_disable_int(obj);
|
|
tran_pos2 = obj->i2c.tran_pos;
|
|
i2c_enable_int(obj);
|
|
t2 = us_ticker_read();
|
|
if (tran_pos2 != tran_pos) { // Transfer on-going
|
|
t1 = t2;
|
|
tran_pos = tran_pos2;
|
|
continue;
|
|
}
|
|
|
|
elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
|
|
if (elapsed >= timeout) { // Transfer idle
|
|
#if NU_I2C_DEBUG
|
|
MY_I2C = obj->i2c;
|
|
MY_I2C_T1 = t1;
|
|
MY_I2C_T2 = t2;
|
|
MY_I2C_ELAPSED = elapsed;
|
|
MY_I2C_TIMEOUT = timeout;
|
|
MY_I2C_2 = obj->i2c;
|
|
while (1);
|
|
#endif
|
|
break;
|
|
}
|
|
}
|
|
|
|
return (elapsed >= timeout);
|
|
}
|
|
|
|
#if 0
|
|
static int i2c_is_stat_int(i2c_t *obj)
|
|
{
|
|
I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
|
|
|
|
return !! (i2c_base->CTL & I2C_CTL_SI_Msk);
|
|
}
|
|
|
|
|
|
static int i2c_is_stop_det(i2c_t *obj)
|
|
{
|
|
I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
|
|
|
|
return ! (i2c_base->CTL & I2C_CTL_STO_Msk);
|
|
}
|
|
#endif
|
|
|
|
static int i2c_is_trsn_done(i2c_t *obj)
|
|
{
|
|
I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
|
|
int i2c_int;
|
|
uint32_t status;
|
|
int inten_back;
|
|
|
|
inten_back = i2c_set_int(obj, 0);
|
|
i2c_int = !! (i2c_base->CTL & I2C_CTL_SI_Msk);
|
|
status = I2C_GET_STATUS(i2c_base);
|
|
i2c_set_int(obj, inten_back);
|
|
|
|
return (i2c_int || status == 0xF8);
|
|
}
|
|
|
|
static int i2c_is_tran_started(i2c_t *obj)
|
|
{
|
|
int started;
|
|
int inten_back;
|
|
|
|
inten_back = i2c_set_int(obj, 0);
|
|
started = !! (obj->i2c.tran_ctrl & TRANCTRL_STARTED);
|
|
i2c_set_int(obj, inten_back);
|
|
|
|
return started;
|
|
}
|
|
|
|
static int i2c_addr2data(int address, int read)
|
|
{
|
|
return read ? (address | 1) : (address & 0xFE);
|
|
}
|
|
|
|
static void i2c0_vec(void)
|
|
{
|
|
i2c_irq(i2c0_var.obj);
|
|
}
|
|
static void i2c1_vec(void)
|
|
{
|
|
i2c_irq(i2c1_var.obj);
|
|
}
|
|
static void i2c2_vec(void)
|
|
{
|
|
i2c_irq(i2c2_var.obj);
|
|
}
|
|
static void i2c3_vec(void)
|
|
{
|
|
i2c_irq(i2c3_var.obj);
|
|
}
|
|
static void i2c4_vec(void)
|
|
{
|
|
i2c_irq(i2c4_var.obj);
|
|
}
|
|
|
|
static void i2c_irq(i2c_t *obj)
|
|
{
|
|
I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
|
|
uint32_t status;
|
|
|
|
if (I2C_GET_TIMEOUT_FLAG(i2c_base)) {
|
|
I2C_ClearTimeoutFlag(i2c_base);
|
|
return;
|
|
}
|
|
|
|
status = I2C_GET_STATUS(i2c_base);
|
|
#if NU_I2C_DEBUG
|
|
if (MY_I2C_STATUS_POS < (sizeof (MY_I2C_STATUS) / sizeof (MY_I2C_STATUS[0]))) {
|
|
MY_I2C_STATUS[MY_I2C_STATUS_POS ++] = status;
|
|
}
|
|
else {
|
|
memset(MY_I2C_STATUS, 0x00, sizeof (MY_I2C_STATUS));
|
|
MY_I2C_STATUS_POS = 0;
|
|
}
|
|
#endif
|
|
|
|
switch (status) {
|
|
// Master Transmit
|
|
case 0x28: // Master Transmit Data ACK
|
|
case 0x18: // Master Transmit Address ACK
|
|
case 0x08: // Start
|
|
case 0x10: // Master Repeat Start
|
|
if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
|
|
if (obj->i2c.tran_pos < obj->i2c.tran_end) {
|
|
I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
|
|
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
|
|
}
|
|
else {
|
|
i2c_fsm_tranfini(obj, 0);
|
|
}
|
|
}
|
|
else {
|
|
i2c_disable_int(obj);
|
|
}
|
|
break;
|
|
|
|
case 0x30: // Master Transmit Data NACK
|
|
i2c_fsm_tranfini(obj, 1);
|
|
break;
|
|
|
|
case 0x20: // Master Transmit Address NACK
|
|
i2c_fsm_tranfini(obj, 1);
|
|
break;
|
|
|
|
case 0x38: // Master Arbitration Lost
|
|
i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
|
|
break;
|
|
|
|
case 0x48: // Master Receive Address NACK
|
|
i2c_fsm_tranfini(obj, 1);
|
|
break;
|
|
|
|
case 0x40: // Master Receive Address ACK
|
|
case 0x50: // Master Receive Data ACK
|
|
case 0x58: // Master Receive Data NACK
|
|
if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
|
|
if (obj->i2c.tran_pos < obj->i2c.tran_end) {
|
|
if (status == 0x50 || status == 0x58) {
|
|
*obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
|
|
}
|
|
|
|
if (status == 0x58) {
|
|
#if NU_I2C_DEBUG
|
|
if (obj->i2c.tran_pos != obj->i2c.tran_end) {
|
|
MY_I2C = obj->i2c;
|
|
while (1);
|
|
}
|
|
#endif
|
|
i2c_fsm_tranfini(obj, 1);
|
|
}
|
|
else {
|
|
uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
|
|
if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
|
|
obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
|
|
// Last data
|
|
i2c_ctl &= ~I2C_CTL_AA_Msk;
|
|
}
|
|
I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
|
|
}
|
|
}
|
|
else {
|
|
obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
|
|
i2c_disable_int(obj);
|
|
break;
|
|
}
|
|
}
|
|
else {
|
|
i2c_disable_int(obj);
|
|
}
|
|
break;
|
|
|
|
//case 0x00: // Bus error
|
|
|
|
// Slave Transmit
|
|
case 0xB8: // Slave Transmit Data ACK
|
|
case 0xA8: // Slave Transmit Address ACK
|
|
case 0xB0: // Slave Transmit Arbitration Lost
|
|
if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
|
|
if (obj->i2c.tran_pos < obj->i2c.tran_end) {
|
|
uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
|
|
|
|
I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
|
|
if (obj->i2c.tran_pos == obj->i2c.tran_end &&
|
|
obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
|
|
// Last data
|
|
i2c_ctl &= ~I2C_CTL_AA_Msk;
|
|
}
|
|
I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
|
|
}
|
|
else {
|
|
obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
|
|
i2c_disable_int(obj);
|
|
break;
|
|
}
|
|
}
|
|
else {
|
|
i2c_disable_int(obj);
|
|
}
|
|
obj->i2c.slaveaddr_state = ReadAddressed;
|
|
break;
|
|
//case 0xA0: // Slave Transmit Repeat Start or Stop
|
|
case 0xC0: // Slave Transmit Data NACK
|
|
case 0xC8: // Slave Transmit Last Data ACK
|
|
obj->i2c.slaveaddr_state = NoData;
|
|
i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
|
|
break;
|
|
|
|
// Slave Receive
|
|
case 0x80: // Slave Receive Data ACK
|
|
case 0x88: // Slave Receive Data NACK
|
|
case 0x60: // Slave Receive Address ACK
|
|
case 0x68: // Slave Receive Arbitration Lost
|
|
obj->i2c.slaveaddr_state = WriteAddressed;
|
|
if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
|
|
if (obj->i2c.tran_pos < obj->i2c.tran_end) {
|
|
if (status == 0x80 || status == 0x88) {
|
|
*obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
|
|
}
|
|
|
|
if (status == 0x88) {
|
|
#if NU_I2C_DEBUG
|
|
if (obj->i2c.tran_pos != obj->i2c.tran_end) {
|
|
MY_I2C = obj->i2c;
|
|
while (1);
|
|
}
|
|
#endif
|
|
obj->i2c.slaveaddr_state = NoData;
|
|
i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
|
|
}
|
|
else {
|
|
uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
|
|
if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
|
|
obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
|
|
// Last data
|
|
i2c_ctl &= ~I2C_CTL_AA_Msk;
|
|
}
|
|
I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
|
|
}
|
|
}
|
|
else {
|
|
obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
|
|
i2c_disable_int(obj);
|
|
break;
|
|
}
|
|
}
|
|
else {
|
|
i2c_disable_int(obj);
|
|
}
|
|
break;
|
|
//case 0xA0: // Slave Receive Repeat Start or Stop
|
|
|
|
// GC mode
|
|
//case 0xA0: // GC mode Repeat Start or Stop
|
|
case 0x90: // GC mode Data ACK
|
|
case 0x98: // GC mode Data NACK
|
|
case 0x70: // GC mode Address ACK
|
|
case 0x78: // GC mode Arbitration Lost
|
|
obj->i2c.slaveaddr_state = WriteAddressed;
|
|
if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
|
|
if (obj->i2c.tran_pos < obj->i2c.tran_end) {
|
|
if (status == 0x90 || status == 0x98) {
|
|
*obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
|
|
}
|
|
|
|
if (status == 0x98) {
|
|
#if NU_I2C_DEBUG
|
|
if (obj->i2c.tran_pos != obj->i2c.tran_end) {
|
|
MY_I2C = obj->i2c;
|
|
while (1);
|
|
}
|
|
#endif
|
|
obj->i2c.slaveaddr_state = NoData;
|
|
i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
|
|
}
|
|
else {
|
|
uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
|
|
if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
|
|
obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
|
|
// Last data
|
|
i2c_ctl &= ~I2C_CTL_AA_Msk;
|
|
}
|
|
I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
|
|
}
|
|
}
|
|
else {
|
|
obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
|
|
i2c_disable_int(obj);
|
|
break;
|
|
}
|
|
}
|
|
else {
|
|
i2c_disable_int(obj);
|
|
}
|
|
break;
|
|
|
|
case 0xF8: // Bus Released
|
|
break;
|
|
|
|
default:
|
|
i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
|
|
}
|
|
}
|
|
|
|
static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl)
|
|
{
|
|
I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
|
|
|
|
obj->i2c.stop = 0;
|
|
|
|
obj->i2c.tran_ctrl = 0;
|
|
|
|
I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
|
|
obj->i2c.slaveaddr_state = NoData;
|
|
}
|
|
|
|
static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked)
|
|
{
|
|
if (lastdatanaked) {
|
|
obj->i2c.tran_ctrl |= TRANCTRL_LASTDATANAKED;
|
|
}
|
|
|
|
obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
|
|
i2c_disable_int(obj);
|
|
}
|
|
|
|
#if DEVICE_I2C_ASYNCH
|
|
|
|
void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
|
|
{
|
|
// NOTE: NUC472 I2C only supports 7-bit slave address. The mbed I2C address passed in is shifted left by 1 bit (7-bit addr << 1).
|
|
MBED_ASSERT((address & 0xFFFFFF00) == 0);
|
|
|
|
// NOTE: First transmit and then receive.
|
|
|
|
(void) hint;
|
|
obj->i2c.dma_usage = DMA_USAGE_NEVER;
|
|
obj->i2c.stop = stop;
|
|
obj->i2c.address = address;
|
|
obj->i2c.event = event;
|
|
i2c_buffer_set(obj, tx, tx_length, rx, rx_length);
|
|
|
|
//I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
|
|
|
|
i2c_enable_vector_interrupt(obj, handler, 1);
|
|
i2c_start(obj);
|
|
}
|
|
|
|
uint32_t i2c_irq_handler_asynch(i2c_t *obj)
|
|
{
|
|
int event = 0;
|
|
|
|
I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
|
|
uint32_t status = I2C_GET_STATUS(i2c_base);
|
|
switch (status) {
|
|
case 0x08: // Start
|
|
case 0x10: {// Master Repeat Start
|
|
if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
|
|
I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 0)));
|
|
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
|
|
}
|
|
else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
|
|
I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 1)));
|
|
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
|
|
}
|
|
else {
|
|
event = I2C_EVENT_TRANSFER_COMPLETE;
|
|
if (obj->i2c.stop) {
|
|
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
|
|
case 0x18: // Master Transmit Address ACK
|
|
case 0x28: // Master Transmit Data ACK
|
|
if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
|
|
uint8_t *tx = (uint8_t *)obj->tx_buff.buffer;
|
|
I2C_SET_DATA(i2c_base, tx[obj->tx_buff.pos ++]);
|
|
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
|
|
}
|
|
else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
|
|
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
|
|
}
|
|
else {
|
|
event = I2C_EVENT_TRANSFER_COMPLETE;
|
|
if (obj->i2c.stop) {
|
|
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 0x20: // Master Transmit Address NACK
|
|
event = I2C_EVENT_ERROR_NO_SLAVE;
|
|
if (obj->i2c.stop) {
|
|
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
|
|
}
|
|
break;
|
|
|
|
case 0x30: // Master Transmit Data NACK
|
|
if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
|
|
event = I2C_EVENT_TRANSFER_EARLY_NACK;
|
|
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
|
|
}
|
|
else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
|
|
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
|
|
}
|
|
else {
|
|
event = I2C_EVENT_TRANSFER_COMPLETE;
|
|
if (obj->i2c.stop) {
|
|
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 0x38: // Master Arbitration Lost
|
|
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk); // Enter not addressed SLV mode
|
|
event = I2C_EVENT_ERROR;
|
|
break;
|
|
|
|
case 0x50: // Master Receive Data ACK
|
|
if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
|
|
uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
|
|
rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
|
|
}
|
|
case 0x40: // Master Receive Address ACK
|
|
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | ((obj->rx_buff.pos != obj->rx_buff.length - 1) ? I2C_CTL_AA_Msk : 0));
|
|
break;
|
|
|
|
case 0x48: // Master Receive Address NACK
|
|
event = I2C_EVENT_ERROR_NO_SLAVE;
|
|
if (obj->i2c.stop) {
|
|
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
|
|
}
|
|
break;
|
|
|
|
case 0x58: // Master Receive Data NACK
|
|
if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
|
|
uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
|
|
rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
|
|
}
|
|
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
|
|
break;
|
|
|
|
case 0x00: // Bus error
|
|
event = I2C_EVENT_ERROR;
|
|
i2c_reset(obj);
|
|
break;
|
|
|
|
default:
|
|
event = I2C_EVENT_ERROR;
|
|
if (obj->i2c.stop) {
|
|
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
|
|
}
|
|
}
|
|
|
|
if (event) {
|
|
i2c_rollback_vector_interrupt(obj);
|
|
}
|
|
|
|
return (event & obj->i2c.event);
|
|
}
|
|
|
|
uint8_t i2c_active(i2c_t *obj)
|
|
{
|
|
const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
|
|
MBED_ASSERT(modinit != NULL);
|
|
MBED_ASSERT(modinit->modname == obj->i2c.i2c);
|
|
|
|
// Vector will be changed for async transfer. Use it to judge if async transfer is on-going.
|
|
uint32_t vec = NVIC_GetVector(modinit->irq_n);
|
|
struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
|
|
return (vec && vec != (uint32_t) var->vec);
|
|
}
|
|
|
|
void i2c_abort_asynch(i2c_t *obj)
|
|
{
|
|
i2c_rollback_vector_interrupt(obj);
|
|
i2c_stop(obj);
|
|
}
|
|
|
|
static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
|
|
{
|
|
obj->tx_buff.buffer = (void *) tx;
|
|
obj->tx_buff.length = tx_length;
|
|
obj->tx_buff.pos = 0;
|
|
obj->rx_buff.buffer = rx;
|
|
obj->rx_buff.length = rx_length;
|
|
obj->rx_buff.pos = 0;
|
|
}
|
|
|
|
static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable)
|
|
{
|
|
const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
|
|
MBED_ASSERT(modinit != NULL);
|
|
MBED_ASSERT(modinit->modname == obj->i2c.i2c);
|
|
|
|
if (enable) {
|
|
NVIC_SetVector(modinit->irq_n, handler);
|
|
i2c_enable_int(obj);
|
|
}
|
|
else {
|
|
i2c_disable_int(obj);
|
|
}
|
|
}
|
|
|
|
static void i2c_rollback_vector_interrupt(i2c_t *obj)
|
|
{
|
|
const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
|
|
MBED_ASSERT(modinit != NULL);
|
|
MBED_ASSERT(modinit->modname == obj->i2c.i2c);
|
|
|
|
struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
|
|
i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif
|