mirror of https://github.com/ARMmbed/mbed-os.git
520 lines
12 KiB
C++
520 lines
12 KiB
C++
/*
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* Copyright (c) 2018-2019, Arm Limited and affiliates.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if defined(DEVICE_USBDEVICE) && (DEVICE_USBDEVICE) && \
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(defined(TARGET_MAX32620) || defined(TARGET_MAX32625) || defined(TARGET_MAX32630))
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#include "mbed.h"
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#include "USBPhyHw.h"
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#include "usb_phy_api.h"
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#include "USBEndpoints_Maxim.h"
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#include "usb_regs.h"
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#include "clkman_regs.h"
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#if defined(TARGET_MAX32625) || defined(TARGET_MAX32630)
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#include "pwrman_regs.h"
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#endif
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#define CONNECT_INTS (MXC_F_USB_DEV_INTEN_BRST | MXC_F_USB_DEV_INTEN_SETUP | MXC_F_USB_DEV_INTEN_EP_IN | MXC_F_USB_DEV_INTEN_EP_OUT | MXC_F_USB_DEV_INTEN_DMA_ERR)
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typedef struct {
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volatile uint32_t buf0_desc;
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volatile uint32_t buf0_address;
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volatile uint32_t buf1_desc;
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volatile uint32_t buf1_address;
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} ep_buffer_t;
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typedef struct {
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ep_buffer_t out_buffer;
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ep_buffer_t in_buffer;
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} ep0_buffer_t;
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typedef struct {
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ep0_buffer_t ep0;
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ep_buffer_t ep[MXC_USB_NUM_EP - 1];
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} ep_buffer_descriptor_t;
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// control packet state
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static enum {
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CTRL_NONE = 0,
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CTRL_SETUP,
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CTRL_OUT,
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CTRL_IN,
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} control_state;
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// Static storage for endpoint buffer descriptor table. Must be 512 byte aligned for DMA.
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MBED_ALIGN(512)
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ep_buffer_descriptor_t ep_buffer_descriptor;
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// static storage for temporary data buffers. Must be 32 byte aligned.
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MBED_ALIGN(4)
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static uint8_t aligned_buffer[NUMBER_OF_LOGICAL_ENDPOINTS][MXC_USB_MAX_PACKET];
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static uint8_t* read_buf_addr[NUMBER_OF_LOGICAL_ENDPOINTS];
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static USBPhyHw *instance;
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static ep_buffer_t *get_desc(uint8_t endpoint)
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{
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uint8_t epnum = EP_NUM(endpoint);
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ep_buffer_t *desc;
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if (epnum == 0) {
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if (IN_EP(endpoint)) {
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desc = &ep_buffer_descriptor.ep0.in_buffer;
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} else {
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desc = &ep_buffer_descriptor.ep0.out_buffer;
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}
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} else {
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desc = &ep_buffer_descriptor.ep[epnum - 1];
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}
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return desc;
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}
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USBPhy *get_usb_phy()
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{
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static USBPhyHw usbphy;
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return &usbphy;
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}
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USBPhyHw::USBPhyHw(): events(NULL)
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{
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}
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USBPhyHw::~USBPhyHw()
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{
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}
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void USBPhyHw::init(USBPhyEvents *events)
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{
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this->events = events;
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// Disable IRQ
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NVIC_DisableIRQ(USB_IRQn);
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// Enable the USB clock
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#if defined(TARGET_MAX32620)
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MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE;
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#elif defined(TARGET_MAX32625) || defined(TARGET_MAX32630)
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MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED;
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MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE;
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#endif
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// reset the device
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MXC_USB->cn = 0;
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MXC_USB->cn = MXC_F_USB_CN_USB_EN;
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MXC_USB->dev_inten = 0;
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MXC_USB->dev_cn = 0;
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MXC_USB->dev_cn = MXC_F_USB_DEV_CN_URST;
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MXC_USB->dev_cn = 0;
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// clear driver state
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control_state = CTRL_NONE;
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// set the descriptor location
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MXC_USB->ep_base = (uint32_t)&ep_buffer_descriptor;
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// enable VBUS interrupts
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MXC_USB->dev_inten = MXC_F_USB_DEV_INTEN_NO_VBUS | MXC_F_USB_DEV_INTEN_VBUS;
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// Attach IRQ handler and Enable IRQ
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instance = this;
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NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr);
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NVIC_EnableIRQ(USB_IRQn);
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}
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void USBPhyHw::deinit()
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{
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// Disconnect and disable interrupt
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MXC_USB->dev_cn = MXC_F_USB_DEV_CN_URST;
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MXC_USB->dev_cn = 0;
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MXC_USB->cn = 0;
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disconnect();
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NVIC_DisableIRQ(USB_IRQn);
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}
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bool USBPhyHw::powered()
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{
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return true;
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}
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void USBPhyHw::connect()
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{
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// enable interrupts
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MXC_USB->dev_inten |= CONNECT_INTS;
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// allow interrupts on ep0
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MXC_USB->ep[0] |= MXC_F_USB_EP_INT_EN;
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// pullup enable
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MXC_USB->dev_cn |= (MXC_F_USB_DEV_CN_CONNECT | MXC_F_USB_DEV_CN_FIFO_MODE);
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}
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void USBPhyHw::disconnect()
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{
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// disable interrupts
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MXC_USB->dev_inten &= ~CONNECT_INTS;
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// disable pullup
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MXC_USB->dev_cn &= ~MXC_F_USB_DEV_CN_CONNECT;
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}
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void USBPhyHw::configure()
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{
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// Do nothing
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}
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void USBPhyHw::unconfigure()
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{
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// reset endpoints
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for (int i = 0; i < MXC_USB_NUM_EP; i++) {
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// Disable endpoint and clear the data toggle
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MXC_USB->ep[i] &= ~MXC_F_USB_EP_DIR;
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MXC_USB->ep[i] |= MXC_F_USB_EP_DT;
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}
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}
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void USBPhyHw::sof_enable()
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{
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// Do nothing
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}
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void USBPhyHw::sof_disable()
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{
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// Do nothing
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}
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void USBPhyHw::set_address(uint8_t address)
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{
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// Do nothing
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}
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void USBPhyHw::remote_wakeup()
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{
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// Do nothing
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}
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const usb_ep_table_t *USBPhyHw::endpoint_table()
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{
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static const usb_ep_table_t endpoint_table = {
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4096 - 32 * 4, // 32 words for endpoint buffers
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// +3 based added to interrupt and isochronous to ensure enough
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// space for 4 byte alignment
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{
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{USB_EP_ATTR_ALLOW_CTRL | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0},
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{USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_DIR_OUT, 0, 0},
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{USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_DIR_IN, 0, 0},
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{USB_EP_ATTR_ALLOW_INT | USB_EP_ATTR_DIR_OUT, 0, 0},
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{USB_EP_ATTR_ALLOW_INT | USB_EP_ATTR_DIR_IN, 0, 0},
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{USB_EP_ATTR_ALLOW_INT | USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0},
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{USB_EP_ATTR_ALLOW_INT | USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0},
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{USB_EP_ATTR_ALLOW_INT | USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0},
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}
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};
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return &endpoint_table;
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}
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uint32_t USBPhyHw::ep0_set_max_packet(uint32_t max_packet)
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{
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return MAX_PACKET_SIZE_EP0;
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}
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void USBPhyHw::ep0_setup_read_result(uint8_t *buffer, uint32_t size)
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{
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uint32_t *ptr32 = (uint32_t*)buffer;
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// read setup packet
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ptr32[0] = (uint32_t)MXC_USB->setup0;
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ptr32[1] = (uint32_t)MXC_USB->setup1;
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}
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void USBPhyHw::ep0_read(uint8_t *data, uint32_t size)
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{
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// Setup data buffer to receive next endpoint 0 OUT packet
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if (control_state == CTRL_IN) {
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// This is the status stage. ACK.
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MXC_USB->ep[0] |= MXC_F_USB_EP_ST_ACK;
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control_state = CTRL_NONE;
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return;
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}
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control_state = CTRL_OUT;
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endpoint_read(EP0OUT, data, size);
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}
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uint32_t USBPhyHw::ep0_read_result()
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{
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// Return the size of the last OUT packet received on endpoint 0
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return endpoint_read_result(EP0OUT);
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}
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void USBPhyHw::ep0_write(uint8_t *buffer, uint32_t size)
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{
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// Start transferring buffer on endpoint 0 IN
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if ((size == 0) && (control_state != CTRL_IN)) {
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// This is a status stage ACK. Handle in hardware.
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MXC_USB->ep[0] |= MXC_F_USB_EP_ST_ACK;
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control_state = CTRL_NONE;
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return;
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}
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control_state = CTRL_IN;
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endpoint_write(EP0IN, buffer, size);
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}
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void USBPhyHw::ep0_stall()
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{
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endpoint_stall(EP0OUT);
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}
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bool USBPhyHw::endpoint_add(usb_ep_t endpoint, uint32_t max_packet, usb_ep_type_t type)
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{
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uint8_t epnum = EP_NUM(endpoint);
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uint32_t ep_ctrl = 0;
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if (epnum >= NUMBER_OF_PHYSICAL_ENDPOINTS) {
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return false;
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}
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if (IN_EP(endpoint)) {
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ep_ctrl = MXC_S_USB_EP_DIR_IN;
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} else {
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ep_ctrl = MXC_S_USB_EP_DIR_OUT;
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}
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ep_ctrl |= (MXC_F_USB_EP_DT | MXC_F_USB_EP_INT_EN);
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MXC_USB->ep[epnum] = ep_ctrl;
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return true;
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}
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void USBPhyHw::endpoint_remove(usb_ep_t endpoint)
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{
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uint8_t epnum = EP_NUM(endpoint);
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// Disable and remove this endpoint
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MXC_USB->ep[epnum] &= ~MXC_F_USB_EP_DIR;
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MXC_USB->ep[epnum] |= MXC_F_USB_EP_DT;
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}
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void USBPhyHw::endpoint_stall(usb_ep_t endpoint)
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{
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// Stall this endpoint until it is explicitly cleared
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uint8_t epnum = EP_NUM(endpoint);
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if (epnum == 0) {
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MXC_USB->ep[epnum] |= MXC_F_USB_EP_ST_STALL;
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}
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MXC_USB->ep[epnum] |= MXC_F_USB_EP_STALL;
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}
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void USBPhyHw::endpoint_unstall(usb_ep_t endpoint)
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{
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// Unstall this endpoint
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MXC_USB->ep[EP_NUM(endpoint)] &= ~MXC_F_USB_EP_STALL;
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}
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bool USBPhyHw::endpoint_read(usb_ep_t endpoint, uint8_t *data, uint32_t size)
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{
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// Setup data buffer to receive next endpoint OUT packet and return true if successful
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uint8_t epnum = EP_NUM(endpoint);
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if ((epnum >= NUMBER_OF_PHYSICAL_ENDPOINTS) ||
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IN_EP(endpoint) ||
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(size > MAX_PACKET_SIZE_EP0)) {
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return false;
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}
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uint32_t mask = (1 << epnum);
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if (MXC_USB->out_owner & mask) {
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return false;
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}
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read_buf_addr[epnum] = data;
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ep_buffer_t *desc = get_desc(endpoint);
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desc->buf0_desc = size;
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desc->buf0_address = (uint32_t)aligned_buffer[epnum];
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MXC_USB->out_owner = mask;
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return true;
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}
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uint32_t USBPhyHw::endpoint_read_result(usb_ep_t endpoint)
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{
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uint32_t size = 0;
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uint8_t epnum = EP_NUM(endpoint);
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if ((epnum >= NUMBER_OF_PHYSICAL_ENDPOINTS) || IN_EP(endpoint)) {
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return 0;
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}
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uint32_t mask = (1 << epnum);
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if (MXC_USB->out_owner & mask) {
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return 0;
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}
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// get the packet length and contents
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ep_buffer_t *desc = get_desc(endpoint);
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size = desc->buf0_desc;
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memcpy(read_buf_addr[epnum], aligned_buffer[epnum], size);
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return size;
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}
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bool USBPhyHw::endpoint_write(usb_ep_t endpoint, uint8_t *data, uint32_t size)
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{
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// Start transferring buffer on endpoint IN
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uint8_t epnum = EP_NUM(endpoint);
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if ((epnum >= NUMBER_OF_PHYSICAL_ENDPOINTS) ||
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OUT_EP(endpoint) ||
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(size > MAX_PACKET_SIZE_EP0)) {
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return false;
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}
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uint32_t mask = (1 << epnum);
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if (MXC_USB->in_owner & mask) {
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return false;
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}
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memcpy(aligned_buffer[epnum], data, size);
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ep_buffer_t *desc = get_desc(endpoint);
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desc->buf0_desc = size;
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desc->buf0_address = (uint32_t)aligned_buffer[epnum];
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// start the DMA
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MXC_USB->in_owner = mask;
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return true;
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}
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void USBPhyHw::endpoint_abort(usb_ep_t endpoint)
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{
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// Stop the current transfer on this endpoint and don't call the IN or OUT callback
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ep_buffer_t *desc = get_desc(endpoint);
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desc->buf0_desc = 0;
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desc->buf0_address = 0;
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}
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void USBPhyHw::process()
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{
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// get and clear irqs
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uint32_t irq_flags = MXC_USB->dev_intfl;
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MXC_USB->dev_intfl = irq_flags;
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// process only enabled interrupts
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irq_flags &= MXC_USB->dev_inten;
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// suspend
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if (irq_flags & MXC_F_USB_DEV_INTFL_SUSP) {
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events->suspend(true);
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}
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// bus reset
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if (irq_flags & MXC_F_USB_DEV_INTFL_BRST) {
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// reset endpoints
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for (int i = 0; i < NUMBER_OF_LOGICAL_ENDPOINTS; i++) {
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// Disable endpoint and clear the data toggle
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MXC_USB->ep[i] &= ~MXC_F_USB_EP_DIR;
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MXC_USB->ep[i] |= MXC_F_USB_EP_DT;
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}
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events->reset();
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// clear driver state
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control_state = CTRL_NONE;
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}
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// power applied
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if (irq_flags & MXC_F_USB_DEV_INTFL_VBUS) {
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events->power(true);
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}
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// power lost
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if (irq_flags & MXC_F_USB_DEV_INTFL_NO_VBUS) {
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events->power(false);
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}
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// Setup packet
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if (irq_flags & MXC_F_USB_DEV_INTFL_SETUP) {
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events->ep0_setup();
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}
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// IN packets
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if (irq_flags & MXC_F_USB_DEV_INTFL_EP_IN) {
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// get and clear IN irqs
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uint32_t in_irqs = MXC_USB->in_int;
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MXC_USB->in_int = in_irqs;
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if (in_irqs & 1) {
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events->ep0_in();
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}
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for (uint8_t epnum = 1; epnum < NUMBER_OF_LOGICAL_ENDPOINTS; epnum++) {
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uint32_t irq_mask = (1 << epnum);
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if (in_irqs & irq_mask) {
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uint8_t endpoint = epnum | DIR_IN;
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events->in(endpoint);
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}
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}
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}
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// OUT packets
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if (irq_flags & MXC_F_USB_DEV_INTFL_EP_OUT) {
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// get and clear OUT irqs
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uint32_t out_irqs = MXC_USB->out_int;
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MXC_USB->out_int = out_irqs;
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if (out_irqs & 1) {
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events->ep0_out();
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}
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for (uint8_t epnum = 1; epnum < NUMBER_OF_LOGICAL_ENDPOINTS; epnum++) {
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uint32_t irq_mask = (1 << epnum);
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if (out_irqs & irq_mask) {
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uint8_t endpoint = epnum | DIR_OUT;
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events->out(endpoint);
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}
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}
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}
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// Re-enable interrupt
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NVIC_ClearPendingIRQ(USB_IRQn);
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NVIC_EnableIRQ(USB_IRQn);
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}
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void USBPhyHw::_usbisr(void)
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{
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NVIC_DisableIRQ(USB_IRQn);
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// Handle interrupts
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instance->events->start_process();
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}
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#endif
|