mirror of https://github.com/ARMmbed/mbed-os.git
575 lines
17 KiB
C
575 lines
17 KiB
C
/*
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* Copyright (c) 2013 Nordic Semiconductor ASA
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
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* integrated circuit in a product or a software update for such product, must reproduce
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* the above copyright notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
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* used to endorse or promote products derived from this software without specific prior
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* written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* Nordic Semiconductor ASA integrated circuit.
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*
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* 5. Any software provided in binary or object form under this license must not be reverse
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* engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include "spi_api.h"
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#if DEVICE_SPI
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#include "cmsis.h"
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#include "pinmap.h"
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#include "mbed_assert.h"
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#include "mbed_error.h"
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#include "nrf_drv_spi.h"
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#include "nrf_drv_spis.h"
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#include "app_util_platform.h"
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#include "sdk_config.h"
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#if DEVICE_SPI_ASYNCH
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#define SPI_IDX(obj) ((obj)->spi.spi_idx)
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#else
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#define SPI_IDX(obj) ((obj)->spi_idx)
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#endif
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#define SPI_INFO(obj) (&m_spi_info[SPI_IDX(obj)])
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#define MASTER_INST(obj) (&m_instances[SPI_IDX(obj)].master)
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#define SLAVE_INST(obj) (&m_instances[SPI_IDX(obj)].slave)
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typedef struct {
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bool initialized;
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bool master;
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uint8_t sck_pin;
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uint8_t mosi_pin;
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uint8_t miso_pin;
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uint8_t ss_pin;
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uint8_t spi_mode;
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nrf_drv_spi_frequency_t frequency;
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volatile union {
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bool busy; // master
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bool readable; // slave
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} flag;
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volatile uint8_t tx_buf;
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volatile uint8_t rx_buf;
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#if DEVICE_SPI_ASYNCH
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uint32_t handler;
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uint32_t event;
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#endif
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} spi_info_t;
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static spi_info_t m_spi_info[SPI_COUNT];
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typedef struct {
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nrf_drv_spi_t master;
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nrf_drv_spis_t slave;
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} sdk_driver_instances_t;
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void SPI0_TWI0_IRQHandler(void);
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void SPI1_TWI1_IRQHandler(void);
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void SPIM2_SPIS2_SPI2_IRQHandler(void);
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static const peripheral_handler_desc_t spi_handler_desc[SPI_COUNT] = {
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#if SPI0_ENABLED
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{
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SPI0_IRQ,
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(uint32_t) SPI0_TWI0_IRQHandler
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},
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#endif
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#if SPI1_ENABLED
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{
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SPI1_IRQ,
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(uint32_t) SPI1_TWI1_IRQHandler
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},
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#endif
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#if SPI2_ENABLED
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{
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SPI2_IRQ,
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(uint32_t) SPIM2_SPIS2_SPI2_IRQHandler
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},
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#endif
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};
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static sdk_driver_instances_t m_instances[SPI_COUNT] = {
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#if SPI0_ENABLED
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{
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NRF_DRV_SPI_INSTANCE(0),
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NRF_DRV_SPIS_INSTANCE(0)
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},
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#endif
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#if SPI1_ENABLED
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{
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NRF_DRV_SPI_INSTANCE(1),
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NRF_DRV_SPIS_INSTANCE(1)
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},
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#endif
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#if SPI2_ENABLED
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{
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NRF_DRV_SPI_INSTANCE(2),
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NRF_DRV_SPIS_INSTANCE(2)
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},
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#endif
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};
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static void master_event_handler(uint8_t spi_idx,
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nrf_drv_spi_evt_t const *p_event)
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{
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spi_info_t *p_spi_info = &m_spi_info[spi_idx];
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if (p_event->type == NRF_DRV_SPI_EVENT_DONE) {
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p_spi_info->flag.busy = false;
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#if DEVICE_SPI_ASYNCH
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if (p_spi_info->handler) {
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void (*handler)(void) = (void (*)(void))p_spi_info->handler;
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p_spi_info->handler = 0;
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handler();
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}
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#endif
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}
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}
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#define MASTER_EVENT_HANDLER(idx) \
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static void master_event_handler_##idx(nrf_drv_spi_evt_t const *p_event) { \
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master_event_handler(SPI##idx##_INSTANCE_INDEX, p_event); \
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}
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#if SPI0_ENABLED
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MASTER_EVENT_HANDLER(0)
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#endif
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#if SPI1_ENABLED
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MASTER_EVENT_HANDLER(1)
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#endif
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#if SPI2_ENABLED
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MASTER_EVENT_HANDLER(2)
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#endif
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static nrf_drv_spi_handler_t const m_master_event_handlers[SPI_COUNT] = {
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#if SPI0_ENABLED
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master_event_handler_0,
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#endif
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#if SPI1_ENABLED
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master_event_handler_1,
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#endif
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#if SPI2_ENABLED
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master_event_handler_2,
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#endif
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};
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static void slave_event_handler(uint8_t spi_idx,
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nrf_drv_spis_event_t event)
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{
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spi_info_t *p_spi_info = &m_spi_info[spi_idx];
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if (event.evt_type == NRF_DRV_SPIS_XFER_DONE) {
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// Signal that there is some data received that could be read.
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p_spi_info->flag.readable = true;
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// And prepare for the next transfer.
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// Previous data set in 'spi_slave_write' (if any) has been transmitted,
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// now use the default one, until some new is set by 'spi_slave_write'.
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p_spi_info->tx_buf = SPIS_DEFAULT_ORC;
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nrf_drv_spis_buffers_set(&m_instances[spi_idx].slave,
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(uint8_t const *)&p_spi_info->tx_buf, 1,
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(uint8_t *)&p_spi_info->rx_buf, 1);
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}
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}
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#define SLAVE_EVENT_HANDLER(idx) \
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static void slave_event_handler_##idx(nrf_drv_spis_event_t event) { \
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slave_event_handler(SPIS##idx##_INSTANCE_INDEX, event); \
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}
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#if SPIS0_ENABLED
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SLAVE_EVENT_HANDLER(0)
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#endif
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#if SPIS1_ENABLED
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SLAVE_EVENT_HANDLER(1)
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#endif
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#if SPIS2_ENABLED
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SLAVE_EVENT_HANDLER(2)
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#endif
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static nrf_drv_spis_event_handler_t const m_slave_event_handlers[SPIS_COUNT] = {
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#if SPIS0_ENABLED
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slave_event_handler_0,
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#endif
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#if SPIS1_ENABLED
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slave_event_handler_1,
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#endif
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#if SPIS2_ENABLED
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slave_event_handler_2,
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#endif
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};
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static void prepare_master_config(nrf_drv_spi_config_t *p_config,
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spi_info_t const *p_spi_info)
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{
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p_config->sck_pin = p_spi_info->sck_pin;
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p_config->mosi_pin = p_spi_info->mosi_pin;
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p_config->miso_pin = p_spi_info->miso_pin;
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p_config->ss_pin = p_spi_info->ss_pin;
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p_config->frequency = p_spi_info->frequency;
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p_config->mode = (nrf_drv_spi_mode_t)p_spi_info->spi_mode;
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p_config->irq_priority = SPI_DEFAULT_CONFIG_IRQ_PRIORITY;
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p_config->orc = 0xFF;
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p_config->bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST;
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}
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static void prepare_slave_config(nrf_drv_spis_config_t *p_config,
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spi_info_t const *p_spi_info)
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{
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p_config->sck_pin = p_spi_info->sck_pin;
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p_config->mosi_pin = p_spi_info->mosi_pin;
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p_config->miso_pin = p_spi_info->miso_pin;
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p_config->csn_pin = p_spi_info->ss_pin;
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p_config->mode = (nrf_drv_spis_mode_t)p_spi_info->spi_mode;
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p_config->irq_priority = SPIS_DEFAULT_CONFIG_IRQ_PRIORITY;
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p_config->orc = SPIS_DEFAULT_ORC;
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p_config->def = SPIS_DEFAULT_DEF;
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p_config->bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST;
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p_config->csn_pullup = NRF_DRV_SPIS_DEFAULT_CSN_PULLUP;
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p_config->miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE;
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}
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void spi_init(spi_t *obj,
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PinName mosi, PinName miso, PinName sclk, PinName ssel)
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{
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int i;
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// This block is only a workaround that allows to create SPI object several
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// times, what would be otherwise impossible in the current implementation
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// of mbed driver that does not call spi_free() from SPI destructor.
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// Once this mbed's imperfection is corrected, this block should be removed.
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for (i = 0; i < SPI_COUNT; ++i) {
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spi_info_t *p_spi_info = &m_spi_info[i];
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if (p_spi_info->initialized &&
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p_spi_info->mosi_pin == (uint8_t)mosi &&
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p_spi_info->miso_pin == (uint8_t)miso &&
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p_spi_info->sck_pin == (uint8_t)sclk &&
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p_spi_info->ss_pin == (uint8_t)ssel) {
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// Reuse the already allocated SPI instance (instead of allocating
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// a new one), if it appears to be initialized with exactly the same
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// pin assignments.
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SPI_IDX(obj) = i;
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return;
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}
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}
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for (i = SPI_COUNT - 1; i >= 0; i--) {
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spi_info_t *p_spi_info = &m_spi_info[i];
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if (!p_spi_info->initialized) {
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p_spi_info->sck_pin = (uint8_t)sclk;
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p_spi_info->mosi_pin = (mosi != NC) ?
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(uint8_t)mosi : NRF_DRV_SPI_PIN_NOT_USED;
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p_spi_info->miso_pin = (miso != NC) ?
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(uint8_t)miso : NRF_DRV_SPI_PIN_NOT_USED;
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p_spi_info->ss_pin = (ssel != NC) ?
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(uint8_t)ssel : NRF_DRV_SPI_PIN_NOT_USED;
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p_spi_info->spi_mode = (uint8_t)NRF_DRV_SPI_MODE_0;
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p_spi_info->frequency = NRF_DRV_SPI_FREQ_1M;
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// By default each SPI instance is initialized to work as a master.
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// Should the slave mode be used, the instance will be reconfigured
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// appropriately in 'spi_format'.
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nrf_drv_spi_config_t config;
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prepare_master_config(&config, p_spi_info);
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nrf_drv_spi_t const *p_spi = &m_instances[i].master;
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ret_code_t ret_code = nrf_drv_spi_init(p_spi,
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&config, m_master_event_handlers[i]);
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if (ret_code == NRF_SUCCESS) {
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p_spi_info->initialized = true;
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p_spi_info->master = true;
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p_spi_info->flag.busy = false;
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#if DEVICE_SPI_ASYNCH
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p_spi_info->handler = 0;
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#endif
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SPI_IDX(obj) = i;
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NVIC_SetVector(spi_handler_desc[i].IRQn, spi_handler_desc[i].vector);
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return;
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}
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}
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}
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// No available peripheral
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error("No available SPI peripheral\r\n");
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}
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void spi_free(spi_t *obj)
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{
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spi_info_t *p_spi_info = SPI_INFO(obj);
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if (p_spi_info->master) {
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nrf_drv_spi_uninit(MASTER_INST(obj));
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}
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else {
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nrf_drv_spis_uninit(SLAVE_INST(obj));
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}
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p_spi_info->initialized = false;
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}
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int spi_busy(spi_t *obj)
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{
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return (int)(SPI_INFO(obj)->flag.busy);
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}
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void spi_format(spi_t *obj, int bits, int mode, int slave)
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{
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if (bits != 8) {
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error("Only 8-bits SPI is supported\r\n");
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}
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if (mode > 3) {
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error("SPI format error\r\n");
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}
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spi_info_t *p_spi_info = SPI_INFO(obj);
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if (slave)
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{
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nrf_drv_spis_mode_t spi_modes[4] = {
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NRF_DRV_SPIS_MODE_0,
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NRF_DRV_SPIS_MODE_1,
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NRF_DRV_SPIS_MODE_2,
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NRF_DRV_SPIS_MODE_3,
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};
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nrf_drv_spis_mode_t new_mode = spi_modes[mode];
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// If the peripheral is currently working as a master, the SDK driver
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// it uses needs to be switched from SPI to SPIS.
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if (p_spi_info->master) {
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nrf_drv_spi_uninit(MASTER_INST(obj));
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}
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// I the SPI mode has to be changed, the SDK's SPIS driver needs to be
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// re-initialized (there is no other way to change its configuration).
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else if (p_spi_info->spi_mode != (uint8_t)new_mode) {
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nrf_drv_spis_uninit(SLAVE_INST(obj));
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}
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else {
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return;
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}
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p_spi_info->spi_mode = (uint8_t)new_mode;
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p_spi_info->master = false;
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p_spi_info->flag.readable = false;
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// Initialize SDK's SPIS driver with the new configuration.
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nrf_drv_spis_config_t config;
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prepare_slave_config(&config, p_spi_info);
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(void)nrf_drv_spis_init(SLAVE_INST(obj), &config,
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m_slave_event_handlers[SPI_IDX(obj)]);
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// Prepare the slave for transfer.
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p_spi_info->tx_buf = SPIS_DEFAULT_ORC;
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nrf_drv_spis_buffers_set(SLAVE_INST(obj),
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(uint8_t const *)&p_spi_info->tx_buf, 1,
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(uint8_t *)&p_spi_info->rx_buf, 1);
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}
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else // master
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{
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nrf_drv_spi_mode_t spi_modes[4] = {
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NRF_DRV_SPI_MODE_0,
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NRF_DRV_SPI_MODE_1,
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NRF_DRV_SPI_MODE_2,
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NRF_DRV_SPI_MODE_3,
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};
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nrf_drv_spi_mode_t new_mode = spi_modes[mode];
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// If the peripheral is currently working as a slave, the SDK driver
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// it uses needs to be switched from SPIS to SPI.
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if (!p_spi_info->master) {
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nrf_drv_spis_uninit(SLAVE_INST(obj));
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}
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// I the SPI mode has to be changed, the SDK's SPI driver needs to be
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// re-initialized (there is no other way to change its configuration).
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else if (p_spi_info->spi_mode != (uint8_t)new_mode) {
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nrf_drv_spi_uninit(MASTER_INST(obj));
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}
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else {
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return;
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}
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p_spi_info->spi_mode = (uint8_t)new_mode;
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p_spi_info->master = true;
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p_spi_info->flag.busy = false;
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// Initialize SDK's SPI driver with the new configuration.
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nrf_drv_spi_config_t config;
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prepare_master_config(&config, p_spi_info);
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(void)nrf_drv_spi_init(MASTER_INST(obj), &config,
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m_master_event_handlers[SPI_IDX(obj)]);
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}
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}
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static nrf_drv_spi_frequency_t freq_translate(int hz)
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{
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nrf_drv_spi_frequency_t frequency;
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if (hz<250000) { //125Kbps
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frequency = NRF_DRV_SPI_FREQ_125K;
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} else if (hz<500000) { //250Kbps
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frequency = NRF_DRV_SPI_FREQ_250K;
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} else if (hz<1000000) { //500Kbps
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frequency = NRF_DRV_SPI_FREQ_500K;
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} else if (hz<2000000) { //1Mbps
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frequency = NRF_DRV_SPI_FREQ_1M;
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} else if (hz<4000000) { //2Mbps
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frequency = NRF_DRV_SPI_FREQ_2M;
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} else if (hz<8000000) { //4Mbps
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frequency = NRF_DRV_SPI_FREQ_4M;
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} else { //8Mbps
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frequency = NRF_DRV_SPI_FREQ_8M;
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}
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return frequency;
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}
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void spi_frequency(spi_t *obj, int hz)
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{
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spi_info_t *p_spi_info = SPI_INFO(obj);
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nrf_drv_spi_frequency_t new_frequency = freq_translate(hz);
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if (p_spi_info->master)
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{
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if (p_spi_info->frequency != new_frequency) {
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p_spi_info->frequency = new_frequency;
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nrf_drv_spi_config_t config;
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prepare_master_config(&config, p_spi_info);
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nrf_drv_spi_t const *p_spi = MASTER_INST(obj);
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nrf_drv_spi_uninit(p_spi);
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(void)nrf_drv_spi_init(p_spi, &config,
|
|
m_master_event_handlers[SPI_IDX(obj)]);
|
|
}
|
|
}
|
|
// There is no need to set anything in slaves when it comes to frequency,
|
|
// since slaves just synchronize with the clock provided by a master.
|
|
}
|
|
|
|
int spi_master_write(spi_t *obj, int value)
|
|
{
|
|
spi_info_t *p_spi_info = SPI_INFO(obj);
|
|
|
|
#if DEVICE_SPI_ASYNCH
|
|
while (p_spi_info->flag.busy) {
|
|
}
|
|
#endif
|
|
|
|
p_spi_info->tx_buf = value;
|
|
p_spi_info->flag.busy = true;
|
|
(void)nrf_drv_spi_transfer(MASTER_INST(obj),
|
|
(uint8_t const *)&p_spi_info->tx_buf, 1,
|
|
(uint8_t *)&p_spi_info->rx_buf, 1);
|
|
while (p_spi_info->flag.busy) {
|
|
}
|
|
|
|
return p_spi_info->rx_buf;
|
|
}
|
|
|
|
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
|
|
char *rx_buffer, int rx_length, char write_fill) {
|
|
int total = (tx_length > rx_length) ? tx_length : rx_length;
|
|
|
|
for (int i = 0; i < total; i++) {
|
|
char out = (i < tx_length) ? tx_buffer[i] : write_fill;
|
|
char in = spi_master_write(obj, out);
|
|
if (i < rx_length) {
|
|
rx_buffer[i] = in;
|
|
}
|
|
}
|
|
|
|
return total;
|
|
}
|
|
|
|
int spi_slave_receive(spi_t *obj)
|
|
{
|
|
spi_info_t *p_spi_info = SPI_INFO(obj);
|
|
MBED_ASSERT(!p_spi_info->master);
|
|
return p_spi_info->flag.readable;
|
|
;
|
|
}
|
|
|
|
int spi_slave_read(spi_t *obj)
|
|
{
|
|
spi_info_t *p_spi_info = SPI_INFO(obj);
|
|
MBED_ASSERT(!p_spi_info->master);
|
|
while (!p_spi_info->flag.readable) {
|
|
}
|
|
p_spi_info->flag.readable = false;
|
|
return p_spi_info->rx_buf;
|
|
}
|
|
|
|
void spi_slave_write(spi_t *obj, int value)
|
|
{
|
|
spi_info_t *p_spi_info = SPI_INFO(obj);
|
|
MBED_ASSERT(!p_spi_info->master);
|
|
|
|
p_spi_info->tx_buf = (uint8_t)value;
|
|
}
|
|
|
|
#if DEVICE_SPI_ASYNCH
|
|
|
|
void spi_master_transfer(spi_t *obj,
|
|
const void *tx, size_t tx_length,
|
|
void *rx, size_t rx_length, uint8_t bit_width,
|
|
uint32_t handler, uint32_t event, DMAUsage hint)
|
|
{
|
|
spi_info_t *p_spi_info = SPI_INFO(obj);
|
|
MBED_ASSERT(p_spi_info->master);
|
|
(void)hint;
|
|
(void)bit_width;
|
|
|
|
p_spi_info->handler = handler;
|
|
p_spi_info->event = event;
|
|
|
|
p_spi_info->flag.busy = true;
|
|
(void)nrf_drv_spi_transfer(MASTER_INST(obj),
|
|
(uint8_t const *)tx, tx_length,
|
|
(uint8_t *)rx, rx_length);
|
|
}
|
|
|
|
uint32_t spi_irq_handler_asynch(spi_t *obj)
|
|
{
|
|
spi_info_t *p_spi_info = SPI_INFO(obj);
|
|
MBED_ASSERT(p_spi_info->master);
|
|
return p_spi_info->event & SPI_EVENT_COMPLETE;
|
|
}
|
|
|
|
uint8_t spi_active(spi_t *obj)
|
|
{
|
|
spi_info_t *p_spi_info = SPI_INFO(obj);
|
|
MBED_ASSERT(p_spi_info->master);
|
|
return p_spi_info->flag.busy;
|
|
}
|
|
|
|
void spi_abort_asynch(spi_t *obj)
|
|
{
|
|
MBED_ASSERT(SPI_INFO(obj)->master);
|
|
nrf_drv_spi_abort(MASTER_INST(obj));
|
|
}
|
|
|
|
#endif // DEVICE_SPI_ASYNCH
|
|
|
|
#endif // DEVICE_SPI
|