mirror of https://github.com/ARMmbed/mbed-os.git
368 lines
28 KiB
C
368 lines
28 KiB
C
/*******************************************************************************
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* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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******************************************************************************/
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#ifndef _MXC_PWRMAN_REGS_H_
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#define _MXC_PWRMAN_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include "mxc_device.h"
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/*
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If types are not defined elsewhere (CMSIS) define them here
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*/
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#ifndef __IO
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#define __IO volatile
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#endif
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#ifndef __I
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#define __I volatile const
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#endif
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#ifndef __O
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#define __O volatile
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#endif
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/**
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* @brief Defines PAD Modes for Wake Up Detection.
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*/
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typedef enum {
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/** WUD Mode for Selected PAD = Clear/Activate */
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MXC_E_PWRMAN_PAD_MODE_CLEAR_SET,
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/** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */
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MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO,
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/** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */
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MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO,
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/** WUD Mode for Selected PAD = No pad state change */
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MXC_E_PWRMAN_PAD_MODE_NONE
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} mxc_pwrman_pad_mode_t;
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/*
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Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
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access to each register in module.
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*/
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/* Offset Register Description
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============= ============================================================================ */
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typedef struct {
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__IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */
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__IO uint32_t intfl; /* 0x0004 Interrupt Flags */
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__IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */
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__IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */
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__IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */
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__IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */
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__IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */
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__IO uint32_t wud_seen0; /* 0x001C Wake-up Detect Status for P0/P1/P2/P3 */
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__IO uint32_t wud_seen1; /* 0x0020 Wake-up Detect Status for P4/P5/P6/P7 */
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__I uint32_t rsv024[3]; /* 0x0024-0x002C */
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__IO uint32_t pt_regmap_ctrl; /* 0x0030 PT Register Mapping Control */
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__I uint32_t rsv034; /* 0x0034 */
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__IO uint32_t die_type; /* 0x0038 Die Type ID Register */
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__IO uint32_t base_part_num; /* 0x003C Base Part Number */
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__IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */
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__IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */
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__IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */
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} mxc_pwrman_regs_t;
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/*
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Register offsets for module PWRMAN.
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*/
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#define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL)
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#define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL)
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#define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL)
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#define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL)
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#define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL)
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#define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL)
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#define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL)
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#define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x0000001CUL)
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#define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000020UL)
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#define MXC_R_PWRMAN_OFFS_PT_REGMAP_CTRL ((uint32_t)0x00000030UL)
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#define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL)
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#define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL)
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#define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL)
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#define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL)
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#define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL)
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/*
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Field positions and masks for module PWRMAN.
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*/
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#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2
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#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS))
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#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3
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#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS))
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#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4
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#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS))
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#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5
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#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS))
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#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8
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#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS))
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#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9
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#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS))
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#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16
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#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS))
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#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 17
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#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS))
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#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 18
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#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS))
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#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 19
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#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS))
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#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 20
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#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS))
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#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21
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#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS))
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#define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22
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#define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS))
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#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31
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#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS))
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#define MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS 0
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#define MXC_F_PWRMAN_INTFL_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS))
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#define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 1
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#define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS))
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#define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2
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#define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS))
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#define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 3
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#define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS))
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#define MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS 4
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#define MXC_F_PWRMAN_INTFL_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS))
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#define MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS 5
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#define MXC_F_PWRMAN_INTFL_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS))
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#define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS 6
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#define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS))
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#define MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS 0
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#define MXC_F_PWRMAN_INTEN_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS))
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#define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 1
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#define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS))
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#define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2
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#define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS))
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#define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 3
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#define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS))
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#define MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS 4
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#define MXC_F_PWRMAN_INTEN_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS))
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#define MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS 5
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#define MXC_F_PWRMAN_INTEN_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS))
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#define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS 6
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#define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS))
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#define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS 0
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#define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS))
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#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 1
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#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS))
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#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2
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#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS))
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#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 3
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#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS))
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#define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS 4
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#define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS))
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#define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS 5
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#define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS))
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#define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS 6
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#define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS))
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#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0
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#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS))
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#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8
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#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS))
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#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12
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#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS))
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#define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS 16
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#define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS))
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31
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#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS))
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#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0
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#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS))
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#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1
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#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS))
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#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2
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#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS))
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#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3
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#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS))
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#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4
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#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS))
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#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5
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#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS))
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#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6
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#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS))
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#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7
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#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS))
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#define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS 0
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#define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS))
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#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0
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#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS))
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#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0
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#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS))
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#define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4
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#define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS))
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#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0
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#define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS))
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#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31
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#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 0
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS 1
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS 2
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 3
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 4
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 5
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 7
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 8
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 9
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 10
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 11
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS 12
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS 13
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 14
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 15
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 16
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS 17
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 19
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 20
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS 23
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS 24
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS 25
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS 27
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 28
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS))
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS 29
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#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS))
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#ifdef __cplusplus
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}
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#endif
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#endif /* _MXC_PWRMAN_REGS_H_ */
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