Jaeden Amero 778d6822bf RTX5: uVisor: Switch threads very carefully ... uVisor doesn't set the PSP of the target thread. The RTOS sets the PSP of the target thread from the target thread's TCB. However, when interrupts of higher priority than PendSV happen between the call to uVisor to switch boxes, and the RTOS setting PSP, the uVisor vIRQ interrupt handler will attempt to use an invalid PSP (the PSP from before the box and thread switch). This leads to a crash. Make box and thread switching atomic by disabling interrupts immediately before the box switching until immediately after the new PSP is set.		2017-06-04 14:41:59 +01:00
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TARGET_CORTEX_M	RTX5: uVisor: Switch threads very carefully	2017-06-04 14:41:59 +01:00
mbed_rtx_conf.h	Bump number of ARMC mutexes to fix PAL test failure	2017-05-30 18:55:56 +01:00
mbed_rtx_handlers.c	Add more verbose RTOS error messages	2017-05-30 18:55:56 +01:00