mirror of https://github.com/ARMmbed/mbed-os.git
205 lines
6.4 KiB
C
205 lines
6.4 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <stddef.h>
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#include "us_ticker_api.h"
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#include "PeripheralNames.h"
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#include "clk_freqs.h"
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static void pit_init(void);
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static void lptmr_init(void);
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static int us_ticker_inited = 0;
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void us_ticker_init(void) {
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if (us_ticker_inited) return;
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us_ticker_inited = 1;
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pit_init();
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lptmr_init();
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}
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/******************************************************************************
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* Timer for us timing.
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******************************************************************************/
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static void pit_init(void) {
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SIM->SCGC6 |= SIM_SCGC6_PIT_MASK; // Clock PIT
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PIT->MCR = 0; // Enable PIT
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// Channel 1
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PIT->CHANNEL[1].LDVAL = 0xFFFFFFFF;
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PIT->CHANNEL[1].TCTRL = PIT_TCTRL_CHN_MASK; // Chain to timer 0, disable Interrupts
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PIT->CHANNEL[1].TCTRL |= PIT_TCTRL_TEN_MASK; // Start timer 1
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// Use channel 0 as a prescaler for channel 1
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PIT->CHANNEL[0].LDVAL = (bus_frequency() + 500000) / 1000000 - 1;
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PIT->CHANNEL[0].TCTRL = PIT_TCTRL_TEN_MASK; // Start timer 0, disable interrupts
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}
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uint32_t us_ticker_read() {
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if (!us_ticker_inited)
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us_ticker_init();
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// The PIT is a countdown timer
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return ~(PIT->CHANNEL[1].CVAL);
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}
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/******************************************************************************
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* Timer Event
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*
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* It schedules interrupts at given (32bit)us interval of time.
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* It is implemented used the 16bit Low Power Timer that remains powered in all
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* power modes.
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******************************************************************************/
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static void lptmr_isr(void);
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static void lptmr_init(void) {
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uint32_t extosc;
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/* Clock the timer */
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SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK;
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/* Reset */
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LPTMR0->CSR = 0;
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#if defined(TARGET_KL43Z)
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/* Set interrupt handler */
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NVIC_SetVector(LPTMR0_IRQn, (uint32_t)lptmr_isr);
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NVIC_EnableIRQ(LPTMR0_IRQn);
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MCG->C1 |= MCG_C1_IRCLKEN_MASK;
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extosc = mcgirc_frequency();
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#else
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/* Set interrupt handler */
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NVIC_SetVector(LPTimer_IRQn, (uint32_t)lptmr_isr);
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NVIC_EnableIRQ(LPTimer_IRQn);
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/* Clock at (1)MHz -> (1)tick/us */
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/* Check if the external oscillator can be divided to 1MHz */
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extosc = extosc_frequency();
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#endif
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if (extosc != 0) { //If external oscillator found
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if (extosc % 1000000u == 0) { //If it is a multiple if 1MHz
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extosc /= 1000000;
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if (extosc == 1) { //1MHz, set timerprescaler in bypass mode
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LPTMR0->PSR = LPTMR_PSR_PCS(3) | LPTMR_PSR_PBYP_MASK;
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return;
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} else { //See if we can divide it to 1MHz
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uint32_t divider = 0;
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extosc >>= 1;
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while (1) {
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if (extosc == 1) {
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LPTMR0->PSR = LPTMR_PSR_PCS(3) | LPTMR_PSR_PRESCALE(divider);
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return;
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}
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if (extosc % 2 != 0) //If we can't divide by two anymore
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break;
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divider++;
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extosc >>= 1;
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}
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}
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}
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}
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#if defined(TARGET_KL43Z)
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//No suitable actual IRC oscillator clock -> Set it to (8MHz / divider)
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MCG->SC &= ~MCG_SC_FCRDIV_MASK;
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MCG->MC &= ~MCG->MC & MCG_MC_LIRC_DIV2_MASK;
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LPTMR0->PSR = LPTMR_PSR_PCS(0) | LPTMR_PSR_PRESCALE(2);
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#else
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//No suitable external oscillator clock -> Use fast internal oscillator (4MHz / divider)
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MCG->C1 |= MCG_C1_IRCLKEN_MASK;
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MCG->C2 |= MCG_C2_IRCS_MASK;
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LPTMR0->PSR = LPTMR_PSR_PCS(0);
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switch (MCG->SC & MCG_SC_FCRDIV_MASK) {
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case MCG_SC_FCRDIV(0): //4MHz
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LPTMR0->PSR |= LPTMR_PSR_PRESCALE(1);
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break;
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case MCG_SC_FCRDIV(1): //2MHz
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LPTMR0->PSR |= LPTMR_PSR_PRESCALE(0);
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break;
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default: //1MHz or anything else, in which case we put it on 1MHz
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MCG->SC &= ~MCG_SC_FCRDIV_MASK;
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MCG->SC |= MCG_SC_FCRDIV(2);
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LPTMR0->PSR |= LPTMR_PSR_PBYP_MASK;
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}
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#endif
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}
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void us_ticker_disable_interrupt(void) {
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LPTMR0->CSR &= ~LPTMR_CSR_TIE_MASK;
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}
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void us_ticker_clear_interrupt(void) {
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// we already clear interrupt in lptmr_isr
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}
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static uint32_t us_ticker_int_counter = 0;
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static uint16_t us_ticker_int_remainder = 0;
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static void lptmr_set(unsigned short count) {
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/* Reset */
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LPTMR0->CSR = 0;
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/* Set the compare register */
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LPTMR0->CMR = count;
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/* Enable interrupt */
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LPTMR0->CSR |= LPTMR_CSR_TIE_MASK;
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/* Start the timer */
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LPTMR0->CSR |= LPTMR_CSR_TEN_MASK;
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}
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static void lptmr_isr(void) {
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// write 1 to TCF to clear the LPT timer compare flag
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LPTMR0->CSR |= LPTMR_CSR_TCF_MASK;
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if (us_ticker_int_counter > 0) {
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lptmr_set(0xFFFF);
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us_ticker_int_counter--;
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} else {
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if (us_ticker_int_remainder > 0) {
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lptmr_set(us_ticker_int_remainder);
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us_ticker_int_remainder = 0;
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} else {
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// This function is going to disable the interrupts if there are
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// no other events in the queue
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us_ticker_irq_handler();
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}
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}
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}
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void us_ticker_set_interrupt(timestamp_t timestamp) {
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int delta = (int)((uint32_t)timestamp - us_ticker_read());
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if (delta <= 0) {
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// This event was in the past:
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us_ticker_irq_handler();
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return;
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}
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us_ticker_int_counter = (uint32_t)(delta >> 16);
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us_ticker_int_remainder = (uint16_t)(0xFFFF & delta);
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if (us_ticker_int_counter > 0) {
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lptmr_set(0xFFFF);
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us_ticker_int_counter--;
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} else {
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lptmr_set(us_ticker_int_remainder);
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us_ticker_int_remainder = 0;
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}
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}
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