mirror of https://github.com/ARMmbed/mbed-os.git
293 lines
11 KiB
C
293 lines
11 KiB
C
/* mbed Microcontroller Library
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*******************************************************************************
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* Copyright (c) 2018, STMicroelectronics
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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*/
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#if DEVICE_SLEEP
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#include "sleep_api.h"
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#include "us_ticker_api.h"
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#include "us_ticker_data.h"
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#include "mbed_critical.h"
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#include "mbed_error.h"
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extern void save_timer_ctx(void);
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extern void restore_timer_ctx(void);
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extern void SetSysClock(void);
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/* Wait loop - assuming tick is 1 us */
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static void wait_loop(uint32_t timeout)
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{
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uint32_t t1, t2, elapsed = 0;
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t1 = us_ticker_read();
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do {
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t2 = us_ticker_read();
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elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t)t2 + 0xFFFFFFFF - t1 + 1);
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} while (elapsed < timeout);
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return;
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}
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static void ForcePeriphOutofDeepSleep(void)
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{
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uint32_t pFLatency = 0;
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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/* Get the Clocks configuration according to the internal RCC registers */
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HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &pFLatency);
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#ifdef RCC_CLOCKTYPE_PCLK2
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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#else /* RCC_CLOCKTYPE_PCLK2 */
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1);
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#endif /* RCC_CLOCKTYPE_PCLK2 */
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#if defined (RCC_SYSCLKSOURCE_MSI) /* STM32Lx */
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
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#else /* defined RCC_SYSCLKSOURCE_MSI */
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
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#endif /* defined RCC_SYSCLKSOURCE_MSI */
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, pFLatency) != HAL_OK) {
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error("ForcePeriphOutofDeepSleep clock issue\r\n");
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}
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}
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static void ForceOscOutofDeepSleep(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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/* Enable Power Control clock */
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__HAL_RCC_PWR_CLK_ENABLE();
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/* Get the Oscillators configuration according to the internal RCC registers */
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HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
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#if defined (RCC_SYSCLKSOURCE_MSI) /* STM32Lx */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
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RCC_OscInitStruct.MSIState = RCC_MSI_ON;
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RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
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#if defined RCC_MSIRANGE_11
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RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; // Highest freq, 48MHz range
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#else
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RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; // 4MHz range
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#endif
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
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#else /* defined RCC_SYSCLKSOURCE_MSI */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = 16;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
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#endif /* defined RCC_SYSCLKSOURCE_MSI */
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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error("ForceOscOutofDeepSleep clock issue\r\n");
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}
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}
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void hal_sleep(void)
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{
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// Disable IRQs
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core_util_critical_section_enter();
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// Request to enter SLEEP mode
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#if defined(PWR_CR1_LPR)
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// State Transitions (see 5.3 Low-power modes, Fig. 13):
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// * (opt): Low Power Run (LPR) Mode -> Run Mode
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// * Run Mode -> Sleep
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// --- Wait for Interrupt --
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// * Sleep -> Run Mode
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// * (opt): Run Mode -> Low Power Run Mode
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// [5.4.1 Power control register 1 (PWR_CR1)]
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// LPR: When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR).
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uint32_t lowPowerMode = LL_PWR_IsEnabledLowPowerRunMode();
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if (lowPowerMode) {
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HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
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} else {
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HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
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}
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#elif defined(PWR_CR_LPDS) || defined(PWR_CR1_LPDS)
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uint32_t lowPowerMode = LL_PWR_GetRegulModeDS();
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if (lowPowerMode) {
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HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
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} else {
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HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
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}
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#else
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HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
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#endif
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// Enable IRQs
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core_util_critical_section_exit();
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}
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extern int serial_is_tx_ongoing(void);
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extern int mbed_sdk_inited;
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/* Most of STM32 targets can have the same generic deep sleep
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* function, but a few targets might need very specific sleep
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* mode management, so this function is defined as WEAK.
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* Check for alternative hal_deepsleep specific implementation
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* in targets folders in case of doubt */
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__WEAK void hal_deepsleep(void)
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{
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/* WORKAROUND:
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* MBED serial driver does not handle deepsleep lock
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* to prevent entering deepsleep until HW serial FIFO is empty.
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* This is tracked in mbed issue 4408.
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* For now, we're checking all Serial HW FIFO. If any transfer is ongoing
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* we're not entering deep sleep and returning immediately. */
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if (serial_is_tx_ongoing()) {
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return;
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}
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// Disable IRQs
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core_util_critical_section_enter();
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save_timer_ctx();
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// Request to enter STOP mode with regulator in low power mode
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//PWR_CR1_LPMS_STOP2 -> STM32L4 ; PWR_LOWPOWERMODE_STOP2 -> STM32WL
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#if defined (PWR_CR1_LPMS_STOP2) || defined(PWR_LOWPOWERMODE_STOP2)
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int pwrClockEnabled = __HAL_RCC_PWR_IS_CLK_ENABLED();
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int lowPowerModeEnabled = PWR->CR1 & PWR_CR1_LPR;
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if (!pwrClockEnabled) {
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__HAL_RCC_PWR_CLK_ENABLE();
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}
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if (lowPowerModeEnabled) {
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HAL_PWREx_DisableLowPowerRunMode();
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}
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#if defined(PWR_CR1_RRSTP)
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HAL_PWREx_EnableSRAM3ContentRetention();
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#endif
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HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI);
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if (lowPowerModeEnabled) {
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HAL_PWREx_EnableLowPowerRunMode();
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}
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if (!pwrClockEnabled) {
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__HAL_RCC_PWR_CLK_DISABLE();
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}
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#elif defined(DUAL_CORE) && (TARGET_STM32H7)
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int lowPowerModeEnabled = LL_PWR_GetRegulModeDS();
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#if defined(CORE_CM7)
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HAL_PWREx_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI, PWR_D3_DOMAIN);
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HAL_PWREx_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI, PWR_D1_DOMAIN);
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#elif defined(CORE_CM4)
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HAL_PWREx_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI, PWR_D3_DOMAIN);
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HAL_PWREx_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI, PWR_D2_DOMAIN);
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#else
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#error "Wrong Core selection"
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#endif /* CORE_CM7 */
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if (lowPowerModeEnabled) {
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LL_PWR_SetRegulModeDS(lowPowerModeEnabled);
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}
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#else /* PWR_CR1_LPMS_STOP2 */
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HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
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#endif /* PWR_CR1_LPMS_STOP2 */
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/* Prevent HAL_GetTick() from using ticker_read_us() to read the
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* us_ticker timestamp until the us_ticker context is restored. */
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mbed_sdk_inited = 0;
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/* After wake-up from STOP reconfigure the PLL */
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#if defined(DUAL_CORE) && (TARGET_STM32H7)
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/* CFG_HW_STOP_MODE_SEMID is used to protect read access to STOP flag, and this avoid both core to configure clocks if both exit from stop at the same time */
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while (LL_HSEM_1StepLock(HSEM, CFG_HW_STOP_MODE_SEMID)) {
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}
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/* Clocks need to be reconfigured only if system has been in stop mode */
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if (LL_PWR_CPU_IsActiveFlag_STOP() && LL_PWR_CPU2_IsActiveFlag_STOP()) {
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/* We've seen unstable PLL CLK configuration when DEEP SLEEP exits just few µs after being entered
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* So we need to force clock init out of Deep Sleep.
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* This init has been split into 2 separate functions so that the involved structures are not allocated on the stack in parallel.
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* This will reduce the maximum stack usage in case on non-optimized / debug compilers settings
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*/
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while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
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}
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ForceOscOutofDeepSleep();
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ForcePeriphOutofDeepSleep();
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SetSysClock();
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LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
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}
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#if defined(CORE_CM7)
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LL_PWR_ClearFlag_CPU();
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#elif defined(CORE_CM4)
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LL_PWR_ClearFlag_CPU2();
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#else
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#error "Core not supported"
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#endif
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LL_HSEM_ReleaseLock(HSEM, CFG_HW_STOP_MODE_SEMID, HSEM_CR_COREID_CURRENT);
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#else
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/* We've seen unstable PLL CLK configuration when DEEP SLEEP exits just few µs after being entered
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* So we need to force clock init out of Deep Sleep.
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* This init has been split into 2 separate functions so that the involved structures are not allocated on the stack in parallel.
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* This will reduce the maximum stack usage in case on non-optimized / debug compilers settings
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*/
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ForceOscOutofDeepSleep();
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ForcePeriphOutofDeepSleep();
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SetSysClock();
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#endif
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/* Wait for clock to be stabilized.
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* TO DO: a better way of doing this, would be to rely on
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* HW Flag. At least this ensures proper operation out of
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* deep sleep */
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wait_loop(500);
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restore_timer_ctx();
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/* us_ticker context restored, allow HAL_GetTick() to read the us_ticker
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* timestamp via ticker_read_us() again. */
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mbed_sdk_inited = 1;
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// Enable IRQs
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core_util_critical_section_exit();
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}
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#endif
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