mirror of https://github.com/ARMmbed/mbed-os.git
233 lines
7.5 KiB
C
233 lines
7.5 KiB
C
/****************************************************************************
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*
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* Copyright 2020 Samsung Electronics All Rights Reserved.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing,
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* software distributed under the License is distributed on an
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* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied. See the License for the specific
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* language governing permissions and limitations under the License.
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*
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****************************************************************************/
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#include <stdbool.h>
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#include "s1sbp6a.h"
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#include "s1sbp6a_type.h"
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#include "s1sbp6a_pmu.h"
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void PMU_SetSysconControl(pmu_syscon_ctrl_t field, bool enable)
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{
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modifyreg32(&BP_SYSCON->PMU_SYSCON_CTRL, 0x01 << field, enable << field);
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}
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bool PMU_GetSysconControl(pmu_syscon_ctrl_t field)
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{
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return !!((getreg32(&BP_SYSCON->PMU_SYSCON_CTRL) >> field) & 0x01);
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}
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void PMU_SetDelayControl(pmu_delay_ctrl_t field, uint32_t val)
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{
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uint32_t reg = (uint32_t)(&BP_SYSCON->PMU_SYSCON_DLY_CTRL);
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uint32_t mask = 0x0F;
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if (field > PMU_DLEAY_MCU_RESET_POWN_PD) {
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reg = (uint32_t)(&BP_SYSCON->PMU_MCU_DLY_CTRL);
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mask = 0xFF;
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}
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modifyreg32(reg, mask << field, (val & mask) << field);
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}
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uint32_t PMU_GetDelayControl(pmu_delay_ctrl_t field)
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{
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uint32_t reg = (uint32_t)(&BP_SYSCON->PMU_SYSCON_DLY_CTRL);
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uint32_t mask = 0x0F;
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if (field > PMU_DLEAY_MCU_RESET_POWN_PD) {
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reg = (uint32_t)(&BP_SYSCON->PMU_MCU_DLY_CTRL);
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mask = 0xFF;
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}
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return ((getreg32(reg) >> field) & mask);
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}
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void PMU_SetSysconDelayEnable(bool val)
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{
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putreg32(&BP_SYSCON->PMU_SYSCON_DLY_EN, (uint32_t)val);
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}
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bool PMU_GetSysconDelayEnable(void)
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{
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return !!(getreg32(&BP_SYSCON->PMU_SYSCON_DLY_EN));
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}
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void PMU_SetSysconFastBoot(bool val)
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{
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putreg32(&BP_SYSCON->PMU_SYSCON_FAST_BOOT, (uint32_t)val);
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}
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bool PMU_GetSysconFastBoot(void)
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{
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return !!(getreg32(&BP_SYSCON->PMU_SYSCON_FAST_BOOT));
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}
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void PMU_SetPowerControl(pmu_power_ctrl_t field, bool enable)
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{
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modifyreg32(&BP_SYSCON->PMU_SYSCON_PD_CTRL, 0x01 << field, enable << field);
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}
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bool PMU_GetPowerControl(pmu_power_ctrl_t field)
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{
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return !!((getreg32(&BP_SYSCON->PMU_SYSCON_PD_CTRL) >> field) & 0x01);
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}
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bool PMU_GetPowerStatus(pmu_power_ctrl_t field)
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{
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return !!((getreg32(&BP_SYSCON->PMU_SYSCON_PD_CTRL) >> field) & 0x01);
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}
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void PMU_SetRetentionControl(pmu_retention_ctrl_t field, bool enable)
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{
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modifyreg32(&BP_SYSCON->PMU_SYSCON_RET_CTRL, 0x1 << field, enable << field);
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}
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bool PMU_GetRetentionControl(pmu_retention_ctrl_t field, bool *pEnable)
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{
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return !!((getreg32(&BP_SYSCON->PMU_SYSCON_RET_CTRL) >> field) & 0x01);
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}
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void bp6a_power_mode(pmu_LPM_t mode)
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{
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switch (mode) {
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case PMU_LPM0:
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putreg32(&BP_SYSCTRL->PMUCTRL, 0x1);
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PMU_SetRetentionControl(PMU_RETENTION_SYSTEM_POWER, true);
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PMU_SetSysconControl(PMU_RTC_MODE_READY, true);
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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__DSB();
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__WFI();
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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break;
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case PMU_LPM1:
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putreg32(&BP_SYSCTRL->PMUCTRL, 0x1);
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PMU_SetRetentionControl(PMU_RETENTION_SYSTEM_POWER, true);
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modifyreg32(&BP_SYSCON->PMU_SYSCON_CTRL,
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PMU_SYSCON_CTRL_RTCMODEREADY_MASK |
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PMU_SYSCON_CTRL_STANBYTEADY_MASK |
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PMU_SYSCON_CTRL_CORE_RETENTION_MASK |
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PMU_SYSCON_CTRL_SYSTEM_RETENTION_MASK |
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PMU_SYSCON_CTRL_HOSCEN_CTRL_MASK |
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PMU_SYSCON_CTRL_LOSCEN_CTRL_MASK |
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PMU_SYSCON_CTRL_PLLEN_CTRL_MASK |
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PMU_SYSCON_CTRL_HOSCEN_SEQ_MASK |
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PMU_SYSCON_CTRL_LOSCEN_SEQ_MASK |
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PMU_SYSCON_CTRL_PLLEN_SEQ_MASK |
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PMU_SYSCON_CTRL_MANUAL_OSC_MASK,
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PMU_SYSCON_CTRL_RTCMODEREADY(0) |
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PMU_SYSCON_CTRL_STANBYTEADY(0) |
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PMU_SYSCON_CTRL_CORE_RETENTION(1) |
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PMU_SYSCON_CTRL_SYSTEM_RETENTION(1) |
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PMU_SYSCON_CTRL_HOSCEN_CTRL(1) |
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PMU_SYSCON_CTRL_LOSCEN_CTRL(1) |
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PMU_SYSCON_CTRL_PLLEN_CTRL(1) |
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PMU_SYSCON_CTRL_HOSCEN_SEQ(1) |
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PMU_SYSCON_CTRL_LOSCEN_SEQ(1) |
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PMU_SYSCON_CTRL_PLLEN_SEQ(0) |
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PMU_SYSCON_CTRL_MANUAL_OSC(1));
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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PMU_SetSysconControl(PMU_STANDBY_MODE_READY, true);
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__DSB();
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__WFI();
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PMU_SetSysconControl(PMU_STANDBY_MODE_READY, false);
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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PMU_SetRetentionControl(PMU_RETENTION_SYSTEM_POWER, false);
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break;
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case PMU_LPM2:
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putreg32(&BP_SYSCTRL->PMUCTRL, 0x1);
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PMU_SetRetentionControl(PMU_RETENTION_SYSTEM_POWER, true);
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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__DSB();
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__WFI();
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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PMU_SetRetentionControl(PMU_RETENTION_SYSTEM_POWER, false);
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break;
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case PMU_LPM3:
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putreg32(&BP_SYSCTRL->PMUCTRL, 0x1);
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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__DSB();
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__WFI();
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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break;
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case PMU_LPM4:
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putreg32(&BP_SYSCTRL->PMUCTRL, 0x1);
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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__DSB();
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__WFI();
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break;
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}
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}
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void bp6a_pum_init(void)
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{
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modifyreg32(&(BP_SYSCON->PMU_SYSCON_CTRL),
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PMU_SYSCON_CTRL_RTCMODEREADY_MASK |
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PMU_SYSCON_CTRL_STANBYTEADY_MASK |
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PMU_SYSCON_CTRL_HOSCEN_CTRL_MASK |
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PMU_SYSCON_CTRL_LOSCEN_CTRL_MASK |
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PMU_SYSCON_CTRL_PLLEN_CTRL_MASK |
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PMU_SYSCON_CTRL_HOSCEN_SEQ_MASK |
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PMU_SYSCON_CTRL_LOSCEN_SEQ_MASK |
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PMU_SYSCON_CTRL_PLLEN_SEQ_MASK |
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PMU_SYSCON_CTRL_MANUAL_OSC_MASK,
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PMU_SYSCON_CTRL_RTCMODEREADY(1) |
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PMU_SYSCON_CTRL_STANBYTEADY(0) |
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PMU_SYSCON_CTRL_HOSCEN_CTRL(1) |
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PMU_SYSCON_CTRL_LOSCEN_CTRL(1) |
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PMU_SYSCON_CTRL_PLLEN_CTRL(0) |
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PMU_SYSCON_CTRL_HOSCEN_SEQ(1) |
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PMU_SYSCON_CTRL_LOSCEN_SEQ(1) |
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PMU_SYSCON_CTRL_PLLEN_SEQ(0) |
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PMU_SYSCON_CTRL_MANUAL_OSC(1));
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modifyreg32(&(BP_SYSCON->PMU_SYSCON_PD_CTRL),
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PMU_SYSCON_PD_DSP_TMEM_MASK |
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PMU_SYSCON_PD_DSP_DMEM_MASK |
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PMU_SYSCON_PD_DECIM_MASK |
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PMU_SYSCON_PD_DSP_MASK,
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PMU_SYSCON_PD_DSP_TMEM(1) |
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PMU_SYSCON_PD_DSP_DMEM(0x0F) |
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PMU_SYSCON_PD_DSP(1) |
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PMU_SYSCON_PD_DECIM(1));
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modifyreg32(&(BP_SYSCON->PMU_SYSCON_PD_CTRL),
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PMU_SYSCON_CHG_PWR_STATE_MASK,
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PMU_SYSCON_CHG_PWR_STATE(1));
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modifyreg32(&(BP_SYSCON->PMU_SYSCON_DLY_EN),
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PMU_SYSCON_MCU_DLY_CTRL_PWR_GATING_MASK,
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PMU_SYSCON_MCU_DLY_CTRL_PWR_GATING(0));
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}
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