mirror of https://github.com/ARMmbed/mbed-os.git
88 lines
4.1 KiB
C
88 lines
4.1 KiB
C
/****************************************************************************
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*
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* Copyright 2020 Samsung Electronics All Rights Reserved.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing,
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* software distributed under the License is distributed on an
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* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied. See the License for the specific
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* language governing permissions and limitations under the License.
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*
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****************************************************************************/
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#ifndef __S1SBP6A_FLASH_H
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#define __S1SBP6A_FLASH_H
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#define FLASH_PAGE_SIZE 2048
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#define UFC_FRWCON0_OFFSET 0x0000
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#define UFC_FSHSTAT_OFFSET 0x0004
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#define UFC_PROTCON_OFFSET 0x0010
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#define UFC_PROTMON_OFFSET 0x0014
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#define UFC_DCYCRDCON_OFFSET 0x0020
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#define UFC_LDTCON_OFFSET 0x0030
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#define UFC_FSHCON0_OFFSET 0x0034
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#define UFC_FECCCON_OFFSET 0x0038
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#define UFC_FECCFADR_OFFSET 0x003C
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#define UFC_DCT0_OFFSET 0x0040
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#define UFC_DCT1_OFFSET 0x0044
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#define UFC_LDT0_OFFSET 0x0050
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#define UFC_LDT1_OFFSET 0x0054
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#define UFC_LDT2_OFFSET 0x0058
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#define UFC_LDT3_OFFSET 0x005C
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#define UFC_MODE_OFFSET 0x0060
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#define UFC_CPA0_OFFSET 0x0064
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#define UFC_RED0_OFFSET 0x0090
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#define UFC_RED0_MBIT_OFFSET 0x0094
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#define UFC_RED1_OFFSET 0x0098
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#define UFC_RED1_MBIT_OFFSET 0x009C
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#define PAGE_ERASE (0)
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#define SECTOR_ERASE (1)
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#define MAT_ERASE (2)
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#define UFC_FRWCON_PROG_EN_SHIFT (0)
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#define UFC_FRWCON_ERASE_MODE_SHIFT (2)
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#define UFC_FRWCON_ECC_DATA_SHIFT (3)
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#define UFC_FRWCON_ERASE_WRITE_SEL_SHIFT (8)
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#define UFC_FRWCON_ECC_FAIL_SHIFT (15)
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#define UFC_FRWCON_WRMD_SHIFT (0)
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#define UFC_FRWCON_HVEN_SHIFT (2)
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#define UFC_FRWCON_ERSMD_SHIFT (3)
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#define UFC_FRWCON_BURSTPRM_SHIFT (8)
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#define UFC_FRWCON_HVERSFAIL_SHIFT (10)
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#define UFC_FRWCON_RED_ADDR_EN_SHIFT (11)
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#define UFC_FRWCON_ECC_FAIL_SHIFT (15)
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#define UFC_FRWCON_WRMD_MASK (0x03<<UFC_FRWCON_WRMD_SHIFT)
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#define UFC_FRWCON_HVEN_MASK (0x01<<UFC_FRWCON_HVEN_SHIFT)
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#define UFC_FRWCON_ERSMD_MASK (0x03<<UFC_FRWCON_ERSMD_SHIFT)
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#define UFC_FRWCON_BURSTPRM_MASK (0x01<<UFC_FRWCON_BURSTPRM_SHIFT)
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#define UFC_FRWCON_HVERSFAIL_MASK (0x01<<UFC_FRWCON_HVERSFAIL_SHIFT)
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#define UFC_FRWCON_RED_ADDR_EN_MASK (0x01<<UFC_FRWCON_RED_ADDR_EN_SHIFT)
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#define UFC_FRWCON_ECC_FAIL_MASK (0x01<<UFC_FRWCON_ECC_FAIL_SHIFT)
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#define UFC_FRWCON_WRMD(c) ((c)<<UFC_FRWCON_WRMD_SHIFT)
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#define UFC_FRWCON_HVEN(c) ((c)<<UFC_FRWCON_HVEN_SHIFT)
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#define UFC_FRWCON_ERSMD(c) ((c)<<UFC_FRWCON_ERSMD_SHIFT)
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#define UFC_FRWCON_BURSTPRM(c) ((c)<<UFC_FRWCON_BURSTPRM_SHIFT)
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#define UFC_FRWCON_HVERSFAIL(c) ((c)<<UFC_FRWCON_HVERSFAIL_SHIFT)
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#define UFC_FRWCON_RED_ADDR_EN(c) ((c)<<UFC_FRWCON_RED_ADDR_EN_SHIFT)
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#define UFC_FRWCON_ECC_FAILT(c) ((c)<<UFC_FRWCON_ECC_FAIL_SHIFT)
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#define PAGE_ERASE_MODE (0)
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#define SECTOR_ERASE_MODE (1)
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#define MAT_ERASE_MODE (2)
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#define NO_OP_MODE (0)
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#define ERASE_MODE (1)
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#define WRITE_MODE (2)
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#endif /* __S1SBP6A_FLASH_H */
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