mirror of https://github.com/ARMmbed/mbed-os.git
108 lines
2.9 KiB
C
108 lines
2.9 KiB
C
/* mbed Microcontroller Library
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* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "us_ticker_api.h"
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#include "TMPM4G9.h"
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#include "txz_t32a.h"
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#define CLR_TIMER_INT_FLAG (uint8_t)0x41
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static uint8_t us_ticker_inited = 0; // Is ticker initialized yet?
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const ticker_info_t* us_ticker_get_info()
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{
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static const ticker_info_t info = {
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2500000,
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32
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};
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return &info;
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}
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// Initialize us_ticker
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void us_ticker_init(void)
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{
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if (us_ticker_inited) {
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us_ticker_disable_interrupt();
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return;
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}
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us_ticker_inited = 1;
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// Enable clock for T32A0
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TSB_CG_FSYSMENA_IPMENA06 = TXZ_ENABLE;
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// T32A ch0 TimerC Reg Match/Over Flow/Under Flow
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TSB_IB->IMC006 = TXZ_ENABLE;
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// Configure Timer T32A0
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TSB_T32A0->MOD = T32A_MODE_32;
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TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
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TSB_T32A0->CRC = T32A_PRSCLx_32;
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TSB_T32A0->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ);
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TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
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NVIC_SetVector(INTT32A00_A_CT_IRQn, (uint32_t)us_ticker_irq_handler);
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NVIC_EnableIRQ(INTT32A00_A_CT_IRQn);
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}
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uint32_t us_ticker_read(void)
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{
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uint32_t ret_val = 0;
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if (!us_ticker_inited) {
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us_ticker_init();
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}
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ret_val = (TSB_T32A0->TMRC);
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return ret_val;
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}
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void us_ticker_set_interrupt(timestamp_t timestamp)
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{
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NVIC_DisableIRQ(INTT32A00_A_CT_IRQn);
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TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
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TSB_T32A0->RGC1 = timestamp ;
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NVIC_EnableIRQ(INTT32A00_A_CT_IRQn);
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TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
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}
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void us_ticker_fire_interrupt(void)
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{
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NVIC_SetPendingIRQ(INTT32A00_A_CT_IRQn);
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NVIC_EnableIRQ(INTT32A00_A_CT_IRQn);
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}
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void us_ticker_disable_interrupt(void)
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{
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// Disable interrupts in NVIC
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TSB_IB->IMC006 = CLR_TIMER_INT_FLAG;
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NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn);
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NVIC_DisableIRQ(INTT32A00_A_CT_IRQn);
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}
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void us_ticker_clear_interrupt(void)
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{
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TSB_IB->IMC006 = CLR_TIMER_INT_FLAG;
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NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn);
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}
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void us_ticker_free(void)
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{
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TSB_T32A0->RUNC = T32A_RUN_DISABLE;
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TSB_IB->IMC006 = CLR_TIMER_INT_FLAG;
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NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn);
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NVIC_DisableIRQ(INTT32A00_A_CT_IRQn);
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TSB_CG_FSYSMENA_IPMENA06 = TXZ_DISABLE;
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}
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