mirror of https://github.com/ARMmbed/mbed-os.git
82 lines
3.7 KiB
Plaintext
82 lines
3.7 KiB
Plaintext
mbed port to NXP LPC43xx
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Updated: 07/11/14
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The NXP LPC43xx microcontrollers includes multiple Cortex-M cores in a single
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microcontroller package. This port allows mbed developers to take advantage
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of the LPC43xx in their application using APIs that they are familiar with.
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Some of the key features of the LPC43xx include:
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* Dual core ARM Cortex-M4/M0 both capable of up to 204 MHz
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* Up to 264 KB SRAM, 1 MB internal flash
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* Two High-speed USB 2.0 interfaces
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* Ethernet MAC
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* LCD interface
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* Quad-SPI Flash Interface (SPIFI)
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* State Configurable Timer (SCT)
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* Serial GPIO (SGPIO)
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* Up to 164 GPIO
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The NXP LPC18xx is a single core Cortex-M3 implementation that is compatible
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with the LPC43XX for cost-sensitive applications not requiring multiple cores.
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mbed port to the LPC43XX - Micromint USA <support@micromint.com>
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Compatibility
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-------------
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* This port has been tested with the following boards:
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Board MCU RAM/Flash
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Micromint Bambino 200 LPC4330 264K SRAM/4 MB SPIFI flash
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Micromint Bambino 200E LPC4330 264K SRAM/8 MB SPIFI flash
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Micromint Bambino 210 LPC4330 264K SRAM/4 MB SPIFI flash
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Micromint Bambino 210E LPC4330 264K SRAM/8 MB SPIFI flash
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* CMSIS-DAP debugging is implemented with the Micromint Bambino 210/210E.
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To debug other LPC4330 targets, use a JTAG. The NXP DFU tool can be used
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for flash programming.
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* This port should support NXP LPC43XX and LPC18XX variants with a single
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codebase. The core declaration specifies the binaries to be built:
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mbed define CMSIS define MCU Target
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__CORTEX_M4 CORE_M4 LPC43xx Cortex-M4
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__CORTEX_M0 CORE_M0 LPC43xx Cortex-M0
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__CORTEX_M3 CORE_M3 LPC18xx Cortex-M3
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These MCUs all share the peripheral IP, common driver code is feasible.
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Yet each variant can have different memory segments, peripherals, etc.
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Plus, each board design can integrate different external peripherals
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or interfaces. A future release of the mbed SDK and its build tools will
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support specifying the target board when building binaries. At this time
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building binaries for different targets requires an external project or
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Makefile.
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* No testing has been done with LPC18xx hardware.
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Notes
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-----
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* On the LPC43xx the hardware pin name and the GPIO pin name are not the same,
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requiring different offsets for the SCU and GPIO registers. To simplify logic
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the pin identifier encodes the offsets. Macros are used for decoding.
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For example, P6_11 corresponds to GPIO3[7] and is encoded/decoded as follows:
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P6_11 = MBED_PIN(0x06, 11, 3, 7) = 0x032C0067
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MBED_SCU_REG(P6_11) = 0x4008632C MBED_GPIO_PORT(P6_11) = 3
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MBED_GPIO_REG(P6_11) = 0x400F4000 MBED_GPIO_PIN(P6_11) = 7
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* Pin names use multiple aliases to support Arduino naming conventions as well
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as others. For example, to use pin p21 on the Bambino 210 from mbed applications
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the following aliases are equivalent: p21, D0, UART0_TX, COM1_TX, P6_4.
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See the board pinout graphic and the PinNames.h for available aliases.
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* The LPC43xx implements GPIO pin and group interrupts. Any pin in the 8 32-bit
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GPIO ports can interrupt (LPC4350 supports up to 164). On group interrupts a
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pin can only interrupt on the rising or falling edge, not both as required
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by the mbed InterruptIn class. Also, group interrupts can't be cleared
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individually. This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
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A future implementation may provide group interrupt support.
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* The LPC3xx PWM driver uses the State Configurable Timer (SCT). The default
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build (PWM_MODE=0) uses the unified 32-bit times. Applications that use PWM
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and require other SCT uses can use the dual 16-bit mode by changing PWM_MODE
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when building the library.
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