mirror of https://github.com/ARMmbed/mbed-os.git
115 lines
6.8 KiB
C
115 lines
6.8 KiB
C
/**************************************************************************//**
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* @file pl310.h
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* @brief Implementation of pl310 functions
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* @version
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* @date 11 June 2013
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*
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* @note
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*
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******************************************************************************/
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/* Copyright (c) 2011 - 2013 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#ifndef __PL310
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#define __PL310
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typedef struct
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{
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__I uint32_t CACHE_ID; /*!< Offset: 0x0000 Cache ID Register */
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__I uint32_t CACHE_TYPE; /*!< Offset: 0x0004 Cache Type Register */
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uint32_t RESERVED0[0x3e];
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__IO uint32_t CONTROL; /*!< Offset: 0x0100 Control Register */
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__IO uint32_t AUX_CNT; /*!< Offset: 0x0104 Auxiliary Control */
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uint32_t RESERVED1[0x3e];
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__IO uint32_t EVENT_CONTROL; /*!< Offset: 0x0200 Event Counter Control */
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__IO uint32_t EVENT_COUNTER1_CONF; /*!< Offset: 0x0204 Event Counter 1 Configuration */
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__IO uint32_t EVENT_COUNTER0_CONF; /*!< Offset: 0x0208 Event Counter 1 Configuration */
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uint32_t RESERVED2[0x2];
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__IO uint32_t INTERRUPT_MASK; /*!< Offset: 0x0214 Interrupt Mask */
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__I uint32_t MASKED_INT_STATUS; /*!< Offset: 0x0218 Masked Interrupt Status */
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__I uint32_t RAW_INT_STATUS; /*!< Offset: 0x021c Raw Interrupt Status */
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__O uint32_t INTERRUPT_CLEAR; /*!< Offset: 0x0220 Interrupt Clear */
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uint32_t RESERVED3[0x143];
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__IO uint32_t CACHE_SYNC; /*!< Offset: 0x0730 Cache Sync */
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uint32_t RESERVED4[0xf];
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__IO uint32_t INV_LINE_PA; /*!< Offset: 0x0770 Invalidate Line By PA */
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uint32_t RESERVED6[2];
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__IO uint32_t INV_WAY; /*!< Offset: 0x077c Invalidate by Way */
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uint32_t RESERVED5[0xc];
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__IO uint32_t CLEAN_LINE_PA; /*!< Offset: 0x07b0 Clean Line by PA */
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uint32_t RESERVED7[1];
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__IO uint32_t CLEAN_LINE_INDEX_WAY; /*!< Offset: 0x07b8 Clean Line by Index/Way */
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__IO uint32_t CLEAN_WAY; /*!< Offset: 0x07bc Clean by Way */
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uint32_t RESERVED8[0xc];
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__IO uint32_t CLEAN_INV_LINE_PA; /*!< Offset: 0x07f0 Clean and Invalidate Line by PA */
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uint32_t RESERVED9[1];
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__IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< Offset: 0x07f8 Clean and Invalidate Line by Index/Way */
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__IO uint32_t CLEAN_INV_WAY; /*!< Offset: 0x07fc Clean and Invalidate by Way */
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uint32_t RESERVED10[0x40];
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__IO uint32_t DATA_LOCK_0_WAY; /*!< Offset: 0x0900 Data Lockdown 0 by Way */
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__IO uint32_t INST_LOCK_0_WAY; /*!< Offset: 0x0904 Instruction Lockdown 0 by Way */
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__IO uint32_t DATA_LOCK_1_WAY; /*!< Offset: 0x0908 Data Lockdown 1 by Way */
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__IO uint32_t INST_LOCK_1_WAY; /*!< Offset: 0x090c Instruction Lockdown 1 by Way */
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__IO uint32_t DATA_LOCK_2_WAY; /*!< Offset: 0x0910 Data Lockdown 2 by Way */
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__IO uint32_t INST_LOCK_2_WAY; /*!< Offset: 0x0914 Instruction Lockdown 2 by Way */
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__IO uint32_t DATA_LOCK_3_WAY; /*!< Offset: 0x0918 Data Lockdown 3 by Way */
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__IO uint32_t INST_LOCK_3_WAY; /*!< Offset: 0x091c Instruction Lockdown 3 by Way */
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__IO uint32_t DATA_LOCK_4_WAY; /*!< Offset: 0x0920 Data Lockdown 4 by Way */
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__IO uint32_t INST_LOCK_4_WAY; /*!< Offset: 0x0924 Instruction Lockdown 4 by Way */
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__IO uint32_t DATA_LOCK_5_WAY; /*!< Offset: 0x0928 Data Lockdown 5 by Way */
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__IO uint32_t INST_LOCK_5_WAY; /*!< Offset: 0x092c Instruction Lockdown 5 by Way */
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__IO uint32_t DATA_LOCK_6_WAY; /*!< Offset: 0x0930 Data Lockdown 5 by Way */
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__IO uint32_t INST_LOCK_6_WAY; /*!< Offset: 0x0934 Instruction Lockdown 5 by Way */
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__IO uint32_t DATA_LOCK_7_WAY; /*!< Offset: 0x0938 Data Lockdown 6 by Way */
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__IO uint32_t INST_LOCK_7_WAY; /*!< Offset: 0x093c Instruction Lockdown 6 by Way */
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uint32_t RESERVED11[0x4];
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__IO uint32_t LOCK_LINE_EN; /*!< Offset: 0x0950 Lockdown by Line Enable */
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__IO uint32_t UNLOCK_ALL_BY_WAY; /*!< Offset: 0x0954 Unlock All Lines by Way */
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uint32_t RESERVED12[0xaa];
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__IO uint32_t ADDRESS_FILTER_START; /*!< Offset: 0x0c00 Address Filtering Start */
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__IO uint32_t ADDRESS_FILTER_END; /*!< Offset: 0x0c04 Address Filtering End */
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uint32_t RESERVED13[0xce];
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__IO uint32_t DEBUG_CONTROL; /*!< Offset: 0x0f40 Debug Control Register */
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} PL310_TypeDef;
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#define PL310 ((PL310_TypeDef *)Renesas_RZ_A1_PL310_BASE) /*!< PL310 Declaration */
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extern int PL310_GetID (void);
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extern int PL310_GetType (void);
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extern void PL310_InvAllByWay (void);
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extern void PL310_CleanInvAllByWay(void);
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extern void PL310_Enable(void);
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extern void PL310_Disable(void);
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extern void PL310_InvPa (void *);
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extern void PL310_CleanPa (void *);
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extern void PL310_CleanInvPa (void *);
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#endif
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