mirror of https://github.com/ARMmbed/mbed-os.git
129 lines
3.5 KiB
C
129 lines
3.5 KiB
C
/**************************************************************************//**
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* @file pl310.c
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* @brief Implementation of PL310 PrimeCell Level 2 Cache Controller functions
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* @version
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* @date 3 December 2014
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*
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* @note
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*
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******************************************************************************/
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/* Copyright (c) 2011 - 2013 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#include "MBRZA1H.h"
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//Cache Sync operation
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void PL310_Sync(void)
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{
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PL310->CACHE_SYNC = 0x0;
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}
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//return Cache controller cache ID
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int PL310_GetID (void)
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{
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return PL310->CACHE_ID;
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}
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//return Cache controller cache Type
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int PL310_GetType (void)
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{
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return PL310->CACHE_TYPE;
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}
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//Invalidate all cache by way
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void PL310_InvAllByWay (void)
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{
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unsigned int assoc;
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if (PL310->AUX_CNT & (1<<16))
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assoc = 16;
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else
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assoc = 8;
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PL310->INV_WAY = (1 << assoc) - 1;
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while(PL310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
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PL310_Sync();
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}
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//Clean and Invalidate all cache by way
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void PL310_CleanInvAllByWay (void)
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{
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unsigned int assoc;
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if (PL310->AUX_CNT & (1<<16))
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assoc = 16;
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else
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assoc = 8;
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PL310->CLEAN_INV_WAY = (1 << assoc) - 1;
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while(PL310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
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PL310_Sync();
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}
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//Enable Cache
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void PL310_Enable(void)
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{
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PL310->CONTROL = 0;
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PL310->INTERRUPT_CLEAR = 0x000001FFuL;
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PL310->DEBUG_CONTROL = 0;
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PL310->DATA_LOCK_0_WAY = 0;
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PL310->CACHE_SYNC = 0;
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PL310->CONTROL = 0x01;
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PL310_Sync();
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}
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//Disable Cache
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void PL310_Disable(void)
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{
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PL310->CONTROL = 0x00;
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PL310_Sync();
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}
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//Invalidate cache by physical address
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void PL310_InvPa (void *pa)
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{
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PL310->INV_LINE_PA = (unsigned int)pa;
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PL310_Sync();
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}
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//Clean cache by physical address
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void PL310_CleanPa (void *pa)
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{
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PL310->CLEAN_LINE_PA = (unsigned int)pa;
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PL310_Sync();
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}
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//Clean and invalidate cache by physical address
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void PL310_CleanInvPa (void *pa)
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{
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PL310->CLEAN_INV_LINE_PA = (unsigned int)pa;
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PL310_Sync();
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}
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