mirror of https://github.com/ARMmbed/mbed-os.git
152 lines
6.6 KiB
C
152 lines
6.6 KiB
C
/**
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******************************************************************************
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* @file clock_map.h
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* @brief CLOCK hw module register map
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* @internal
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* @author ON Semiconductor
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* $Rev: 2848 $
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* $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $
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******************************************************************************
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* Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
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* All rights reserved. This software and/or documentation is licensed by ON Semiconductor
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* under limited terms and conditions. The terms and conditions pertaining to the software
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* and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
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* (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
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* if applicable the software license agreement. Do not use this software and/or
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* documentation unless you have carefully read and you agree to the limited terms and
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* conditions. By using this software and/or documentation, you agree to the limited
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* terms and conditions.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
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* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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* @endinternal
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*
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* @ingroup clock
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*
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* @details
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*/
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#ifndef CLOCK_MAP_H_
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#define CLOCK_MAP_H_
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/*************************************************************************************************
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* *
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* Header files *
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* *
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*************************************************************************************************/
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#include "architecture.h"
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/**************************************************************************************************
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* *
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* Type definitions *
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* *
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**************************************************************************************************/
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/** Clock control HW structure overlay */
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typedef struct {
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union {
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struct {
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__IO uint32_t OSC_SEL:1;
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__IO uint32_t PAD0:1;
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__IO uint32_t CAL32K:1;
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__IO uint32_t CAL32M:1;
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__IO uint32_t RTCEN:1;
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} BITS;
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__IO uint32_t WORD;
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} CCR; /**< 0x4001B000 Clock control register */
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union {
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struct {
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__I uint32_t XTAL32M:1;
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__I uint32_t XTAL32K:1;
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__I uint32_t CAL32K:1;
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__I uint32_t DONE32K:1;
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__I uint32_t CAL32MFAIL:1;
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__I uint32_t CAL32MDONE:1;
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} BITS;
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__I uint32_t WORD;
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} CSR; /**< 0x4001B004 Clock status register */
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union {
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struct {
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__IO uint32_t IE32K:1;
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__IO uint32_t IE32M:1;
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} BITS;
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__IO uint32_t WORD;
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} IER; /**< 0x4001B008 Interrup enable register */
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__IO uint32_t ICR; /**< 0x4001B00C Interrupt clear register */
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union {
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struct {
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__IO uint32_t TIMER0:1;
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__IO uint32_t TIMER1:1;
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__IO uint32_t TIMER2:1;
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__IO uint32_t PAD0:2;
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__IO uint32_t UART1:1;
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__IO uint32_t SPI:1;
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__IO uint32_t I2C:1;
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__IO uint32_t UART2:1;
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__IO uint32_t PAD1:1;
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__IO uint32_t WDOG:1;
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__IO uint32_t PWM:1;
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__IO uint32_t GPIO:1;
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__IO uint32_t PAD2:2;
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__IO uint32_t RTC:1;
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__IO uint32_t XBAR:1;
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__IO uint32_t RAND:1;
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__IO uint32_t PAD3:2;
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__IO uint32_t MACHW:1;
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__IO uint32_t ADC:1;
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__IO uint32_t AES:1;
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__IO uint32_t FLASH:1;
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__IO uint32_t PAD4:1;
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__IO uint32_t RFANA:1;
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__IO uint32_t IO:1;
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__IO uint32_t PAD5:1;
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__IO uint32_t PAD:1;
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__IO uint32_t PMU:1;
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__IO uint32_t PAD6:1;
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__IO uint32_t TEST:1;
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} BITS;
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__IO uint32_t WORD;
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} PDIS; /**< 0x4001B010 Periphery disable */
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__IO uint32_t FDIV; /**< 0x4001B014 FCLK divider */
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__IO uint32_t TDIV; /**< 0x4001B01C Traceclk divider */
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__IO uint32_t WDIV; /**< 0x4001B020 Watchdog clock divider */
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__IO uint32_t TRIM_32M_INT; /**< 0x4001B024 32Mhz internal trim */
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__IO uint32_t TRIM_32K_INT; /**< 0x4001B02C 32kHz internal trim */
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union {
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struct {
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__IO uint32_t TRIM_VALUE :6; /* External 32MHz Trim Value */
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__IO uint32_t BOOST :2; /* Boost done signal tap control */
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__IO uint32_t READY :2; /* Ready signal tap control */
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__IO uint32_t GAIN_MODE :2; /* Gain Mode */
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__IO uint32_t PAD :20; /* Unused bits */
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} BITS;
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__IO uint32_t WORD;
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} TRIM_32M_EXT; /**< 0x4001B030 32Mhz external trim */
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union {
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struct {
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__IO uint32_t TRIM_VALUE :6; /* External 32MHz Trim Value */
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__IO uint32_t BOOST :2; /* Boost done signal tap control */
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__IO uint32_t READY :2; /* Ready signal tap control */
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__IO uint32_t GAIN_MODE :2; /* Gain Mode */
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__IO uint32_t PAD :20; /* Unused bits */
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} BITS;
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__IO uint32_t WORD;
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} TRIM_32K_EXT;
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union {
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struct {
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__IO uint32_t OV32M;
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__IO uint32_t EN32M;
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__IO uint32_t OV32K;
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__IO uint32_t EN32K;
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} BITS;
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__IO uint32_t WORD;
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} CER; /**< 0x4001B038 clock enable register*/
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} ClockReg_t, *ClockReg_pt;
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#endif /* CLOCK_MAP_H_ */
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