mirror of https://github.com/ARMmbed/mbed-os.git
599 lines
18 KiB
C
599 lines
18 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <stdlib.h>
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#include <string.h>
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#include "i2c_api.h"
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#include "cmsis.h"
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#include "pinmap.h"
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#define LPC824_I2C0_FMPLUS 1
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#if DEVICE_I2C
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static const SWM_Map SWM_I2C_SDA[] = {
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//PINASSIGN Register ID, Pinselect bitfield position
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{ 9, 8},
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{ 9, 24},
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{10, 8},
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};
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static const SWM_Map SWM_I2C_SCL[] = {
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//PINASSIGN Register ID, Pinselect bitfield position
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{ 9, 16},
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{10, 0},
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{10, 16},
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};
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static int i2c_used = 0;
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static uint8_t repeated_start = 0;
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#define I2C_DAT(x) (x->i2c->MSTDAT)
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#define I2C_STAT(x) ((x->i2c->STAT >> 1) & (0x07))
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static inline void i2c_power_enable(int ch)
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{
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switch(ch) {
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case 0:
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// I2C0, Same as for LPC812
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LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 5);
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LPC_SYSCON->PRESETCTRL &= ~(1 << 6);
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LPC_SYSCON->PRESETCTRL |= (1 << 6);
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break;
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case 1:
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case 2:
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case 3:
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// I2C1,I2C2 or I2C3. Not available for LPC812
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LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (20 + ch));
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LPC_SYSCON->PRESETCTRL &= ~(1 << (13 + ch));
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LPC_SYSCON->PRESETCTRL |= (1 << (13 + ch));
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break;
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default:
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break;
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}
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}
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static inline void i2c_interface_enable(i2c_t *obj) {
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obj->i2c->CFG |= (1 << 0); // Enable Master mode
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// obj->i2c->CFG &= ~(1 << 1); // Disable Slave mode
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}
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static int get_available_i2c(void) {
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int i;
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for (i=0; i<3; i++) {
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if ((i2c_used & (1 << i)) == 0)
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return i+1;
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}
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return -1;
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}
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void i2c_init(i2c_t *obj, PinName sda, PinName scl)
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{
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const SWM_Map *swm;
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uint32_t regVal;
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int i2c_ch = 0;
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//LPC824
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//I2C0 can support FM+ but only on P0_11 and P0_10
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if (sda == I2C_SDA && scl == I2C_SCL) {
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//Select I2C mode for P0_11 and P0_10
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LPC_SWM->PINENABLE0 &= ~(0x3 << 11);
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#if(LPC824_I2C0_FMPLUS == 1)
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// Enable FM+ mode on P0_11, P0_10
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LPC_IOCON->PIO0_10 &= ~(0x3 << 8);
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LPC_IOCON->PIO0_10 |= (0x2 << 8); //FM+ mode
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LPC_IOCON->PIO0_11 &= ~(0x3 << 8);
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LPC_IOCON->PIO0_11 |= (0x2 << 8); //FM+ mode
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#endif
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}
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else {
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//Select any other pin for I2C1, I2C2 or I2C3
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i2c_ch = get_available_i2c();
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if (i2c_ch == -1)
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return;
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i2c_used |= (1 << (i2c_ch - 1));
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swm = &SWM_I2C_SDA[i2c_ch - 1];
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regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
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LPC_SWM->PINASSIGN[swm->n] = regVal | ((sda >> PIN_SHIFT) << swm->offset);
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swm = &SWM_I2C_SCL[i2c_ch - 1];
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regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
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LPC_SWM->PINASSIGN[swm->n] = regVal | ((scl >> PIN_SHIFT) << swm->offset);
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}
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switch(i2c_ch) {
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case 0:
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obj->i2c = (LPC_I2C0_Type *)LPC_I2C0;
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break;
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case 1:
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obj->i2c = (LPC_I2C0_Type *)LPC_I2C1;
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break;
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case 2:
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obj->i2c = (LPC_I2C0_Type *)LPC_I2C2;
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break;
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case 3:
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obj->i2c = (LPC_I2C0_Type *)LPC_I2C3;
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break;
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default:
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break;
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}
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// enable power
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i2c_power_enable(i2c_ch);
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// set default frequency at 100k
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i2c_frequency(obj, 100000);
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i2c_interface_enable(obj);
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}
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static inline int i2c_status(i2c_t *obj) {
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return I2C_STAT(obj);
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}
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// Wait until the Master Serial Interrupt (SI) is set
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// Timeout when it takes too long.
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static int i2c_wait_SI(i2c_t *obj) {
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int timeout = 0;
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while (!(obj->i2c->STAT & (1 << 0))) {
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timeout++;
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if (timeout > 100000) return -1;
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}
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return 0;
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}
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//Attention. Spec says: First store Address in DAT before setting STA !
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//Undefined state when using single byte I2C operations and too much delay
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//between i2c_start and do_i2c_write(Address).
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//Also note that lpc812/824 will immediately continue reading a byte when Address b0 == 1
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inline int i2c_start(i2c_t *obj) {
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int status = 0;
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if (repeated_start) {
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obj->i2c->MSTCTL = (1 << 1) | (1 << 0); // STA bit and Continue bit to complete previous RD or WR
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repeated_start = 0;
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} else {
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obj->i2c->MSTCTL = (1 << 1); // STA bit
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}
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return status;
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}
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//Generate Stop condition and wait until bus is Idle
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//Will also send NAK for previous RD
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inline int i2c_stop(i2c_t *obj) {
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int timeout = 0;
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// STP bit and Continue bit. Sends NAK to complete previous RD
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obj->i2c->MSTCTL = (1 << 2) | (1 << 0);
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//Spin until Ready (b0 == 1)and Status is Idle (b3..b1 == 000)
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while ((obj->i2c->STAT & ((7 << 1) | (1 << 0))) != ((0 << 1) | (1 << 0))) {
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timeout ++;
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if (timeout > 100000) return 1;
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}
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// repeated_start = 0; // bus free
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return 0;
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}
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//Spec says: first check Idle and status is Ok
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static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
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// write the data
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I2C_DAT(obj) = value;
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if (!addr)
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obj->i2c->MSTCTL = (1 << 0); //Set continue for data. Should not be set for addr since that uses STA
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// wait and return status
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i2c_wait_SI(obj);
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return i2c_status(obj);
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}
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//Attention, correct Order: wait for data ready, read data, read status, continue, return
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//Dont read DAT or STAT when not ready, so dont read after setting continue.
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//Results may be invalid when next read is underway.
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static inline int i2c_do_read(i2c_t *obj, int last) {
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// wait for it to arrive
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i2c_wait_SI(obj);
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if (!last)
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obj->i2c->MSTCTL = (1 << 0); //ACK and Continue
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// return the data
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return (I2C_DAT(obj) & 0xFF);
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}
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void i2c_frequency(i2c_t *obj, int hz) {
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// No peripheral clock divider on the M0
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uint32_t PCLK = SystemCoreClock;
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uint32_t clkdiv = PCLK / (hz * 4) - 1;
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obj->i2c->CLKDIV = clkdiv;
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obj->i2c->MSTTIME = 0;
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}
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// The I2C does a read or a write as a whole operation
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// There are two types of error conditions it can encounter
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// 1) it can not obtain the bus
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// 2) it gets error responses at part of the transmission
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//
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// We tackle them as follows:
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// 1) we retry until we get the bus. we could have a "timeout" if we can not get it
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// which basically turns it in to a 2)
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// 2) on error, we use the standard error mechanisms to report/debug
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//
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// Therefore an I2C transaction should always complete. If it doesn't it is usually
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// because something is setup wrong (e.g. wiring), and we don't need to programatically
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// check for that
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int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
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int count, status;
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//Store the address+RD and then generate STA
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I2C_DAT(obj) = address | 0x01;
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i2c_start(obj);
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// Wait for completion of STA and Sending of SlaveAddress+RD and first Read byte
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i2c_wait_SI(obj);
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status = i2c_status(obj);
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if (status == 0x03) { // NAK on SlaveAddress
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i2c_stop(obj);
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return I2C_ERROR_NO_SLAVE;
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}
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// Read in all except last byte
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for (count = 0; count < (length-1); count++) {
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// Wait for it to arrive, note that first byte read after address+RD is already waiting
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i2c_wait_SI(obj);
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status = i2c_status(obj);
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if (status != 0x01) { // RX RDY
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i2c_stop(obj);
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return count;
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}
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data[count] = I2C_DAT(obj) & 0xFF; // Store read byte
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obj->i2c->MSTCTL = (1 << 0); // Send ACK and Continue to read
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}
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// Read final byte
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// Wait for it to arrive
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i2c_wait_SI(obj);
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status = i2c_status(obj);
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if (status != 0x01) { // RX RDY
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i2c_stop(obj);
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return count;
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}
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data[count] = I2C_DAT(obj) & 0xFF; // Store final read byte
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// If not repeated start, send stop.
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if (stop) {
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i2c_stop(obj); // Also sends NAK for last read byte
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} else {
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repeated_start = 1;
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}
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return length;
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}
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int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
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int i, status;
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//Store the address+/WR and then generate STA
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I2C_DAT(obj) = address & 0xFE;
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i2c_start(obj);
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// Wait for completion of STA and Sending of SlaveAddress+/WR
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i2c_wait_SI(obj);
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status = i2c_status(obj);
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if (status == 0x03) { // NAK SlaveAddress
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i2c_stop(obj);
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return I2C_ERROR_NO_SLAVE;
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}
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//Write all bytes
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for (i=0; i<length; i++) {
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status = i2c_do_write(obj, data[i], 0);
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if (status != 0x02) { // TX RDY. Handles a Slave NAK on datawrite
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i2c_stop(obj);
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return i;
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}
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}
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// If not repeated start, send stop.
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if (stop) {
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i2c_stop(obj);
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} else {
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repeated_start = 1;
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}
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return length;
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}
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void i2c_reset(i2c_t *obj) {
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i2c_stop(obj);
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}
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int i2c_byte_read(i2c_t *obj, int last) {
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return (i2c_do_read(obj, last) & 0xFF);
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// return (i2c_do_read(obj, last, 0) & 0xFF);
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}
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int i2c_byte_write(i2c_t *obj, int data) {
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int ack;
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int status = i2c_do_write(obj, (data & 0xFF), 0);
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switch(status) {
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case 2: // TX RDY. Handles a Slave NAK on datawrite
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ack = 1;
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break;
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default:
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ack = 0;
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break;
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}
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return ack;
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}
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#if DEVICE_I2CSLAVE
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#define I2C_SLVDAT(x) (x->i2c->SLVDAT)
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#define I2C_SLVSTAT(x) ((x->i2c->STAT >> 9) & (0x03))
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#define I2C_SLVSI(x) ((x->i2c->STAT >> 8) & (0x01))
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//#define I2C_SLVCNT(x) (x->i2c->SLVCTL = (1 << 0))
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//#define I2C_SLVNAK(x) (x->i2c->SLVCTL = (1 << 1))
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#if(0)
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// Wait until the Slave Serial Interrupt (SI) is set
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// Timeout when it takes too long.
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static int i2c_wait_slave_SI(i2c_t *obj) {
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int timeout = 0;
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while (!(obj->i2c->STAT & (1 << 8))) {
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timeout++;
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if (timeout > 100000) return -1;
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}
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return 0;
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}
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#endif
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void i2c_slave_mode(i2c_t *obj, int enable_slave) {
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if (enable_slave) {
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// obj->i2c->CFG &= ~(1 << 0); //Disable Master mode
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obj->i2c->CFG |= (1 << 1); //Enable Slave mode
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}
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else {
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// obj->i2c->CFG |= (1 << 0); //Enable Master mode
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obj->i2c->CFG &= ~(1 << 1); //Disable Slave mode
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}
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}
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// Wait for next I2C event and find out what is going on
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//
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int i2c_slave_receive(i2c_t *obj) {
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int addr;
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// Check if there is any data pending
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if (! I2C_SLVSI(obj)) {
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return 0; //NoData
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};
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// Check State
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switch(I2C_SLVSTAT(obj)) {
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case 0x0: // Slave address plus R/W received
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// At least one of the four slave addresses has been matched by hardware.
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// You can figure out which address by checking Slave address match Index in STAT register.
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// Get the received address
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addr = I2C_SLVDAT(obj) & 0xFF;
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// Send ACK on address and Continue
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obj->i2c->SLVCTL = (1 << 0);
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if (addr == 0x00) {
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return 2; //WriteGeneral
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}
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//check the RW bit
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if ((addr & 0x01) == 0x01) {
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return 1; //ReadAddressed
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}
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else {
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return 3; //WriteAddressed
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}
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//break;
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case 0x1: // Slave receive. Received data is available (Slave Receiver mode).
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// Oops, should never get here...
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obj->i2c->SLVCTL = (1 << 1); // Send NACK on received data, try to recover...
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return 0; //NoData
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case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode).
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// Oops, should never get here...
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I2C_SLVDAT(obj) = 0xFF; // Send dummy data for transmission
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obj->i2c->SLVCTL = (1 << 0); // Continue and try to recover...
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return 0; //NoData
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case 0x3: // Reserved.
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default: // Oops, should never get here...
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obj->i2c->SLVCTL = (1 << 0); // Continue and try to recover...
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return 0; //NoData
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//break;
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} //switch status
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}
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// The dedicated I2C Slave byte read and byte write functions need to be called
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// from 'common' mbed I2CSlave API for devices that have separate Master and
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// Slave engines such as the lpc812 and lpc1549.
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//Called when Slave is addressed for Write, Slave will receive Data in polling mode
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//Parameter last=1 means received byte will be NACKed.
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int i2c_slave_byte_read(i2c_t *obj, int last) {
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int data;
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// Wait for data
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while (!I2C_SLVSI(obj)); // Wait forever
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//if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout
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// Dont bother to check State, were not returning it anyhow..
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//if (I2C_SLVSTAT(obj)) == 0x01) {
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// Slave receive. Received data is available (Slave Receiver mode).
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//};
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data = I2C_SLVDAT(obj) & 0xFF; // Get and store the received data
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if (last) {
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obj->i2c->SLVCTL = (1 << 1); // Send NACK on received data and Continue
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}
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else {
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obj->i2c->SLVCTL = (1 << 0); // Send ACK on data and Continue to read
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}
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return data;
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}
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//Called when Slave is addressed for Read, Slave will send Data in polling mode
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//
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int i2c_slave_byte_write(i2c_t *obj, int data) {
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// Wait until Ready
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while (!I2C_SLVSI(obj)); // Wait forever
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// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout
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// Check State
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switch(I2C_SLVSTAT(obj)) {
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case 0x0: // Slave address plus R/W received
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// At least one of the four slave addresses has been matched by hardware.
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// You can figure out which address by checking Slave address match Index in STAT register.
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// I2C Restart occurred
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return -1;
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//break;
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case 0x1: // Slave receive. Received data is available (Slave Receiver mode).
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// Should not get here...
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return -2;
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//break;
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case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode).
|
|
I2C_SLVDAT(obj) = data & 0xFF; // Store the data for transmission
|
|
obj->i2c->SLVCTL = (1 << 0); // Continue to send
|
|
|
|
return 1;
|
|
//break;
|
|
case 0x3: // Reserved.
|
|
default:
|
|
// Should not get here...
|
|
return -3;
|
|
//break;
|
|
} // switch status
|
|
}
|
|
|
|
|
|
//Called when Slave is addressed for Write, Slave will receive Data in polling mode
|
|
//Parameter length (>=1) is the maximum allowable number of bytes. All bytes will be ACKed.
|
|
int i2c_slave_read(i2c_t *obj, char *data, int length) {
|
|
int count=0;
|
|
|
|
// Read and ACK all expected bytes
|
|
while (count < length) {
|
|
// Wait for data
|
|
while (!I2C_SLVSI(obj)); // Wait forever
|
|
// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout
|
|
|
|
// Check State
|
|
switch(I2C_SLVSTAT(obj)) {
|
|
case 0x0: // Slave address plus R/W received
|
|
// At least one of the four slave addresses has been matched by hardware.
|
|
// You can figure out which address by checking Slave address match Index in STAT register.
|
|
// I2C Restart occurred
|
|
return -1;
|
|
//break;
|
|
|
|
case 0x1: // Slave receive. Received data is available (Slave Receiver mode).
|
|
data[count] = I2C_SLVDAT(obj) & 0xFF; // Get and store the received data
|
|
obj->i2c->SLVCTL = (1 << 0); // Send ACK on data and Continue to read
|
|
break;
|
|
|
|
case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode).
|
|
case 0x3: // Reserved.
|
|
default: // Should never get here...
|
|
return -2;
|
|
//break;
|
|
} // switch status
|
|
|
|
count++;
|
|
} // for all bytes
|
|
|
|
return count; // Received the expected number of bytes
|
|
}
|
|
|
|
|
|
//Called when Slave is addressed for Read, Slave will send Data in polling mode
|
|
//Parameter length (>=1) is the maximum number of bytes. Exit when Slave byte is NACKed.
|
|
int i2c_slave_write(i2c_t *obj, const char *data, int length) {
|
|
int count;
|
|
|
|
// Send and all bytes or Exit on NAK
|
|
for (count=0; count < length; count++) {
|
|
// Wait until Ready for data
|
|
while (!I2C_SLVSI(obj)); // Wait forever
|
|
// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout
|
|
|
|
// Check State
|
|
switch(I2C_SLVSTAT(obj)) {
|
|
case 0x0: // Slave address plus R/W received
|
|
// At least one of the four slave addresses has been matched by hardware.
|
|
// You can figure out which address by checking Slave address match Index in STAT register.
|
|
// I2C Restart occurred
|
|
return -1;
|
|
//break;
|
|
case 0x1: // Slave receive. Received data is available (Slave Receiver mode).
|
|
// Should not get here...
|
|
return -2;
|
|
//break;
|
|
case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode).
|
|
I2C_SLVDAT(obj) = data[count] & 0xFF; // Store the data for transmission
|
|
obj->i2c->SLVCTL = (1 << 0); // Continue to send
|
|
break;
|
|
case 0x3: // Reserved.
|
|
default:
|
|
// Should not get here...
|
|
return -3;
|
|
//break;
|
|
} // switch status
|
|
} // for all bytes
|
|
|
|
return length; // Transmitted the max number of bytes
|
|
}
|
|
|
|
|
|
// Set the four slave addresses.
|
|
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
|
|
obj->i2c->SLVADR0 = (address & 0xFE); // Store address in address 0 register
|
|
obj->i2c->SLVADR1 = (0x00 & 0xFE); // Store general call write address in address 1 register
|
|
obj->i2c->SLVADR2 = (0x01); // Disable address 2 register
|
|
obj->i2c->SLVADR3 = (0x01); // Disable address 3 register
|
|
obj->i2c->SLVQUAL0 = (mask & 0xFE); // Qualifier mask for address 0 register. Any maskbit that is 1 will always be a match
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif
|