mirror of https://github.com/ARMmbed/mbed-os.git
326 lines
8.4 KiB
C
326 lines
8.4 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2006-2018 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if DEVICE_SPI
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#include "mbed_assert.h"
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#include <math.h>
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#include "spi_api.h"
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#include "rda_ccfg_api.h"
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#include "cmsis.h"
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#include "pinmap.h"
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/*------------- Wlan Monitor (WLANMON) ---------------------------------------*/
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typedef struct
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{
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__IO uint32_t PHYSEL_3_0; /* 0x00 : PHY select register 0 - 3 */
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} RDA_WLANMON_TypeDef;
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/*
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* Macros
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*/
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#define RDA_MON ((RDA_WLANMON_TypeDef *)RDA_MON_BASE)
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#define ENABLE_RDA_SPI_MODE 0
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#define SPI_CLKGATE_REG (RDA_SCU->CLKGATE2)
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#define SPI_MODESEL_REG (RDA_GPIO->CTRL)
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#define SPI_PINSEL_REG0 (RDA_GPIO->MEMCFG)
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#define SPI_PINSEL_REG1 (RDA_MON->PHYSEL_3_0)
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#define SPI_PINSEL_REG2 (RDA_EXIF->MISCCFG)
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/*
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* Global Variables
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*/
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static const PinMap PinMap_SPI_SCLK[] = {
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{PB_4, SPI_0, 4},
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{PD_0, SPI_0, 1},
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{NC , NC , 0}
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};
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static const PinMap PinMap_SPI_MOSI[] = {
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{PB_6, SPI_0, 3},
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{PC_0, SPI_0, 6},
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{PD_2, SPI_0, 1},
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{PB_3, SPI_0, 2},
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{NC , NC , 0}
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};
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static const PinMap PinMap_SPI_MISO[] = {
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{PB_7, SPI_0, 3},
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{PC_1, SPI_0, 6},
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{PD_3, SPI_0, 1},
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{PB_8, SPI_0, 3},
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{NC , NC , 0}
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};
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static const PinMap PinMap_SPI_SSEL[] = {
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{PD_1, SPI_0, 1},
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{PB_5, SPI_0, 4},
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{PA_0, SPI_0, 3},
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{PA_1, SPI_0, 3},
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{NC , NC , 0}
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};
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/*
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* Inline Functions
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*/
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static inline int spi_pin_cs_num(PinName ssel);
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static inline void spi_write(spi_t *obj, int value);
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static inline int spi_read(spi_t *obj);
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/*
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* Functions
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*/
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void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
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{
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uint32_t reg_val;
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/* Determine the SPI to use */
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SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
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SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
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SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
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SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
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SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
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SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
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obj->spi = (RDA_SPI_TypeDef*)pinmap_merge(spi_data, spi_cntl);
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MBED_ASSERT((int)obj->spi != NC);
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/* Enable power and clocking */
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SPI_CLKGATE_REG |= (0x01UL << 18);
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/* Select 4-wire SPI mode */
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SPI_MODESEL_REG &= ~(0x01UL << 14);
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/* Set Config Reg */
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reg_val = obj->spi->CFG;
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#if ENABLE_RDA_SPI_MODE
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/* RDA SPI mode */
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reg_val |= (0x01UL << 2);
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#else /* ENABLE_RDA_SPI_MODE */
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/* Normal SPI mode */
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reg_val &= ~(0x01UL << 2);
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/* Set read flag */
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reg_val |= (0x01UL << 3);
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#endif /* ENABLE_RDA_SPI_MODE */
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/* Set core cfg for mosi, miso */
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if (PB_6 == mosi) {
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rda_ccfg_gp(6U, 0x01U);
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}
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if (PB_7 == miso) {
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rda_ccfg_gp(7U, 0x01U);
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}
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/* Config gpio/wlan_mon regs */
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if (PB_3 == mosi) {
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SPI_MODESEL_REG &= ~(0x0FUL);
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SPI_PINSEL_REG1 &= ~(0x3FUL << 24);
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SPI_PINSEL_REG2 &= ~(0x0FUL << 12);
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SPI_MODESEL_REG |= (0x0BUL);
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SPI_PINSEL_REG1 |= (0x02UL << 24);
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SPI_PINSEL_REG2 |= (0x01UL << 12);
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}
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if (PB_8 == miso) {
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SPI_PINSEL_REG0 &= ~(0x01UL << 11);
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}
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/* Pin out the SPI pins */
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pinmap_pinout(mosi, PinMap_SPI_MOSI);
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pinmap_pinout(miso, PinMap_SPI_MISO);
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pinmap_pinout(sclk, PinMap_SPI_SCLK);
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if (ssel != NC) {
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int cs_num = spi_pin_cs_num(ssel);
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reg_val &= ~(0x03UL << 23);
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reg_val |= (((uint32_t)cs_num & 0x03UL) << 23);
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pinmap_pinout(ssel, PinMap_SPI_SSEL);
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}
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obj->spi->CFG = reg_val;
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}
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void spi_free(spi_t *obj)
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{
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/* Disable SPI clock gating */
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SPI_CLKGATE_REG &= ~(0x01UL << 18);
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}
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void spi_format(spi_t *obj, int bits, int mode, int slave)
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{
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uint32_t polarity = (mode & 0x2) ? (0x01UL) : (0x00UL);
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uint32_t reg_val;
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#if ENABLE_RDA_SPI_MODE
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MBED_ASSERT(((bits >= 4) && (bits <= 64)) && (mode >= 0 && mode <= 3));
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#else /* ENABLE_RDA_SPI_MODE */
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MBED_ASSERT(((bits >= 4) && (bits <= 32)) && (mode >= 0 && mode <= 3));
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#endif /* ENABLE_RDA_SPI_MODE */
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/* Set number of frame bits and clock phase */
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reg_val = obj->spi->CFG & ~(0x7FUL << 16) & ~(0x01UL << 1);
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obj->spi->CFG = reg_val | ((uint32_t)bits << 16) | (polarity << 1);
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#if ENABLE_RDA_SPI_MODE
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/* Set bit offset value */
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obj->bit_ofst[0] = 0;
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obj->bit_ofst[1] = 0;
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if (2 > (bits >> 5)) {
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obj->bit_ofst[bits >> 5] = (uint8_t)(32 - (bits & 0x1F));
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}
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#else /* ENABLE_RDA_SPI_MODE */
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obj->bit_ofst[0] = (uint8_t)(32 - bits);
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#endif /* ENABLE_RDA_SPI_MODE */
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}
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void spi_frequency(spi_t *obj, int hz)
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{
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uint32_t clk_rate = ((AHBBusClock / (uint32_t)hz) >> 2) - 1U;
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uint32_t reg_val;
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/* Check for valid frequency */
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MBED_ASSERT(clk_rate <= 0x3FUL);
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/* Set clk rate field */
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reg_val = obj->spi->CFG & ~(0x3FUL << 4);
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obj->spi->CFG = reg_val | ((clk_rate & 0x3FUL) << 4);
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}
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int spi_master_write(spi_t *obj, int value)
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{
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spi_write(obj, value);
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return spi_read(obj);
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}
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int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill)
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{
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int total = (tx_length > rx_length) ? tx_length : rx_length;
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for (int i = 0; i < total; i++) {
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char out = (i < tx_length) ? tx_buffer[i] : write_fill;
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char in = spi_master_write(obj, out);
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if (i < rx_length) {
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rx_buffer[i] = in;
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}
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}
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return total;
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}
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int spi_busy(spi_t *obj)
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{
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return (obj->spi->CFG & (0x01UL << 31)) ? (1) : (0);
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}
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static inline int spi_pin_cs_num(PinName ssel)
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{
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int idx = 0;
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while (PinMap_SPI_SSEL[idx].pin != NC) {
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if (PinMap_SPI_SSEL[idx].pin == ssel)
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return idx;
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idx++;
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}
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return (int)NC;
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}
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static inline void spi_write(spi_t *obj, int value)
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{
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#if ENABLE_RDA_SPI_MODE
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/* Write data register */
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if (obj->bit_ofst[0] != 0) {
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obj->spi->D1CMD = (uint32_t)value << obj->bit_ofst[0];
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} else {
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obj->spi->D1CMD = (uint32_t)value;
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obj->spi->D0CMD = (uint32_t)value << obj->bit_ofst[1];
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}
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/* Set write bit & start bit */
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obj->spi->CFG = (obj->spi->CFG & ~(0x01UL << 3)) | 0x01UL;
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#else /* ENABLE_RDA_SPI_MODE */
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/* Write data reg */
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if (obj->bit_ofst[0] != 0) {
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obj->spi->D1CMD = ((uint32_t)value << obj->bit_ofst[0]) | (0xFFFFFFFFUL >> (32 - obj->bit_ofst[0]));
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} else {
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obj->spi->D1CMD = (uint32_t)value;
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obj->spi->D0CMD = 0xFFFFFFFFUL;
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}
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/* Set start bit */
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obj->spi->CFG |= 0x01UL;
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#endif /* ENABLE_RDA_SPI_MODE */
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__DSB();
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while (spi_busy(obj));
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}
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static inline int spi_read(spi_t *obj)
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{
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uint32_t ret_val;
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#if ENABLE_RDA_SPI_MODE
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/* Set read bit & start bit */
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obj->spi->CFG |= ((0x01UL << 3) | 0x01UL);
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__DSB();
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while (spi_busy(obj));
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/* Read data register */
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if (obj->bit_ofst[0] != 0) {
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ret_val = obj->spi->D0CMD & ((0x01UL << (32UL - obj->bit_ofst[0])) - 1UL);
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} else {
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ret_val = obj->spi->D0CMD;
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ret_val = obj->spi->D1CMD & ((0x01UL << (32UL - obj->bit_ofst[1])) - 1UL);
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}
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#else /* ENABLE_RDA_SPI_MODE */
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/* Read data register */
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ret_val = obj->spi->D0CMD & ((0x01UL << (32UL - obj->bit_ofst[0])) - 1UL);
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#endif /* ENABLE_RDA_SPI_MODE */
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return (int)ret_val;
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}
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const PinMap *spi_master_mosi_pinmap()
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{
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return PinMap_SPI_MOSI;
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}
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const PinMap *spi_master_miso_pinmap()
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{
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return PinMap_SPI_MISO;
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}
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const PinMap *spi_master_clk_pinmap()
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{
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return PinMap_SPI_SCLK;
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}
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const PinMap *spi_master_cs_pinmap()
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{
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return PinMap_SPI_SSEL;
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}
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const PinMap *spi_slave_mosi_pinmap()
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{
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return PinMap_SPI_MOSI;
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}
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const PinMap *spi_slave_miso_pinmap()
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{
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return PinMap_SPI_MISO;
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}
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const PinMap *spi_slave_clk_pinmap()
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{
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return PinMap_SPI_SCLK;
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}
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const PinMap *spi_slave_cs_pinmap()
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{
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return PinMap_SPI_SSEL;
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}
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#endif
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