mirror of https://github.com/ARMmbed/mbed-os.git
424 lines
12 KiB
C
424 lines
12 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2006-2018 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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// math.h required for floating point operations for baud rate calculation
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#include "mbed_assert.h"
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#include <math.h>
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#include <string.h>
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#include <stdlib.h>
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#include "serial_api.h"
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#include "cmsis.h"
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#include "pinmap.h"
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#include "gpio_api.h"
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/******************************************************************************
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* INITIALIZATION
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******************************************************************************/
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#define UART_NUM 2
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#define UART_CLKGATE_REG (RDA_SCU->CLKGATE0)
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#define UART1_CLKEN_MASK (0x01UL << 21)
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#define RXFIFO_EMPTY_MASK (0x01UL << 0)
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#define TXFIFO_FULL_MASK (0x01UL << 19)
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#define AFCE_MASK (0x01UL << 5)
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static const PinMap PinMap_UART_TX[] = {
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{PA_1, UART_0, 0},
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{PB_2, UART_1, 5},
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{PD_3, UART_1, 2},
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{NC , NC , 0}
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};
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static const PinMap PinMap_UART_RX[] = {
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{PA_0, UART_0, 0},
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{PB_1, UART_1, 5},
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{PD_2, UART_1, 2},
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{NC , NC , 0}
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};
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static const PinMap PinMap_UART_RTS[] = {
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{PD_1, UART_1, 2},
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{NC, NC, 0}
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};
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static const PinMap PinMap_UART_CTS[] = {
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{PD_0, UART_1, 2},
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{NC, NC, 0}
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};
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static uart_irq_handler irq_handler[UART_NUM];
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int stdio_uart_inited = 0;
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serial_t stdio_uart;
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struct serial_global_data_s {
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uint32_t serial_irq_id;
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gpio_t sw_rts, sw_cts;
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uint8_t count, rx_irq_set_flow, rx_irq_set_api;
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};
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static struct serial_global_data_s uart_data[UART_NUM];
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void serial_init(serial_t *obj, PinName tx, PinName rx)
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{
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int is_stdio_uart = 0;
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// determine the UART to use
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UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
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UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
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UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
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MBED_ASSERT((int)uart != NC);
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switch (uart) {
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case UART_0:
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obj->index = 0;
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break;
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case UART_1:
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obj->index = 1;
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/* Enable clock-gating */
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UART_CLKGATE_REG |= UART1_CLKEN_MASK;
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break;
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}
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obj->uart = (RDA_UART_TypeDef *)uart;
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// enable fifos and default rx trigger level
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obj->uart->FCR = 0 << 0 //FIFO Enable - 0 = Disables, 1 = Enabled
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| 0 << 1 // Rx Fifo Reset
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| 0 << 2 // Tx Fifo Reset
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| 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
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// disable irqs
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obj->uart->IER = 0 << 0 // Rx Data available irq enable
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| 0 << 1 // Tx Fifo empty irq enable
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| 0 << 2; // Rx Line Status irq enable
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obj->uart->MCR = 1 << 8; //select clock
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obj->uart->FRR = 0x2001; //tx_trigger = 0x10, rx_trigger = 0x01
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serial_format(obj, 8, ParityNone, 1);
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// pinout the chosen uart
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pinmap_pinout(tx, PinMap_UART_TX);
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pinmap_pinout(rx, PinMap_UART_RX);
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// set rx/tx pins in PullUp mode
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if (tx != NC) {
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pin_mode(tx, PullUp);
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}
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if (rx != NC) {
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pin_mode(rx, PullUp);
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}
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if ((rx != NC) && (tx != NC)) {
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obj->uart->FCR |= 1 << 0; //enable fifo
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}
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uart_data[obj->index].sw_rts.pin = NC;
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uart_data[obj->index].sw_cts.pin = NC;
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serial_set_flow_control(obj, FlowControlNone, NC, NC);
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is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
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if (is_stdio_uart) {
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stdio_uart_inited = 1;
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memcpy(&stdio_uart, obj, sizeof(serial_t));
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}
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serial_clear(obj);
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}
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void serial_free(serial_t *obj)
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{
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uart_data[obj->index].serial_irq_id = 0;
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}
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// serial_baud
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// set the baud rate, taking in to account the current SystemFrequency
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void serial_baud(serial_t *obj, int baudrate)
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{
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MBED_ASSERT((int)obj->uart <= UART_1);
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uint32_t baud_divisor;
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uint32_t baud_mod;
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baud_divisor = (AHBBusClock / baudrate) >> 4;
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baud_mod = (AHBBusClock / baudrate) & 0x0F;
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obj->uart->LCR |= (1 << 7); //enable load devisor register
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obj->uart->DLL = (baud_divisor >> 0) & 0xFF;
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obj->uart->DLH = (baud_divisor >> 8) & 0xFF;
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obj->uart->DL2 = (baud_mod>>1) + ((baud_mod - (baud_mod>>1))<<4);
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obj->uart->LCR &= ~(1 << 7);// after loading, disable load devisor register
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}
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void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
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{
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MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
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MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits
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MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
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(parity == ParityForced1) || (parity == ParityForced0));
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stop_bits -= 1;
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data_bits -= 5;
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int parity_enable, parity_select;
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switch (parity) {
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case ParityNone:
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parity_enable = 0;
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parity_select = 0;
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break;
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case ParityOdd:
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parity_enable = 1;
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parity_select = 0;
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break;
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case ParityEven:
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parity_enable = 1;
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parity_select = 1;
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break;
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case ParityForced1:
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parity_enable = 1;
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parity_select = 2;
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break;
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case ParityForced0:
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parity_enable = 1;
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parity_select = 3;
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break;
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default:
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parity_enable = 0;
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parity_select = 0;
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break;
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}
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obj->uart->LCR = (obj->uart->LCR) &
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((~0x3FUL) |
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(data_bits << 0) |
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(stop_bits << 2) |
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(parity_enable << 3) |
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(parity_select << 4));
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}
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/******************************************************************************
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* INTERRUPTS HANDLING
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******************************************************************************/
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static inline void uart_irq(uint32_t iir, uint32_t index, RDA_UART_TypeDef *puart)
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{
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SerialIrq irq_type;
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switch (iir) {
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case 0x02UL: irq_type = TxIrq; break;
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case 0x04UL: irq_type = RxIrq; break;
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case 0x00UL: iir = puart->MSR;
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default: return;
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}
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if ((RxIrq == irq_type) && ((NC != uart_data[index].sw_rts.pin) && ((puart->MCR & AFCE_MASK) == 0x00UL))) {
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gpio_write(&uart_data[index].sw_rts, 1);
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// Disable interrupt if it wasn't enabled by other part of the application
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if (!uart_data[index].rx_irq_set_api)
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puart->IER &= ~(1 << RxIrq);
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}
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if (uart_data[index].serial_irq_id != 0)
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if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
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(irq_handler[index])(uart_data[index].serial_irq_id, irq_type);
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}
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void uart0_irq(void)
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{
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uart_irq((RDA_UART0->IIR & 0x0FUL), 0, (RDA_UART_TypeDef*)RDA_UART0);
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}
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void uart1_irq(void)
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{
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uart_irq((RDA_UART1->IIR & 0x0FUL), 1, (RDA_UART_TypeDef*)RDA_UART1);
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}
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void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
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{
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irq_handler[obj->index] = handler;
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uart_data[obj->index].serial_irq_id = id;
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}
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static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable)
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{
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IRQn_Type irq_n = (IRQn_Type)0;
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uint32_t vector = 0;
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switch ((int)obj->uart) {
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case UART_0:
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irq_n=UART0_IRQn;
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vector = (uint32_t)&uart0_irq;
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break;
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case UART_1:
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irq_n=UART1_IRQn;
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vector = (uint32_t)&uart1_irq;
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break;
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default:
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break;
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}
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if (enable) {
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obj->uart->IER |= 1 << irq;
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NVIC_SetVector(irq_n, vector);
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NVIC_SetPriority(irq_n, 0x1FUL);
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NVIC_EnableIRQ(irq_n);
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}
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else if ((TxIrq == irq) ||
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(uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable
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int all_disabled = 0;
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SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
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obj->uart->IER &= ~(1 << irq);
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all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
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if (all_disabled)
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NVIC_DisableIRQ(irq_n);
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}
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}
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void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
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{
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if (RxIrq == irq)
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uart_data[obj->index].rx_irq_set_api = enable;
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serial_irq_set_internal(obj, irq, enable);
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}
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static void serial_flow_irq_set(serial_t *obj, uint32_t enable)
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{
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uart_data[obj->index].rx_irq_set_flow = enable;
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serial_irq_set_internal(obj, RxIrq, enable);
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}
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/******************************************************************************
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* READ/WRITE
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******************************************************************************/
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int serial_getc(serial_t *obj)
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{
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int data = 0;
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while (!serial_readable(obj));
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data = (int)(obj->uart->RBR & 0x00FFUL);
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if (((obj->uart->MCR & AFCE_MASK) == 0x00UL) && (NC != uart_data[obj->index].sw_rts.pin)) { //enable flow control rx
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gpio_write(&uart_data[obj->index].sw_rts, 0);
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obj->uart->IER |= 1 << RxIrq;
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}
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return data;
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}
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void serial_putc(serial_t *obj, int c)
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{
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while (serial_writable(obj));
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obj->uart->THR = c;
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}
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int serial_readable(serial_t *obj)
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{
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return (obj->uart->LSR & RXFIFO_EMPTY_MASK);
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}
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int serial_writable(serial_t *obj)
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{
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int isWritable = 1;
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if (obj->index == 0) {
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return (obj->uart->FSR & TXFIFO_FULL_MASK); // uart0 not have flow control
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} else {
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if (((obj->uart->MCR & AFCE_MASK) == 0x00UL) && (NC != uart_data[obj->index].sw_cts.pin)) //If flow control: writable if CTS low + UART done
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isWritable = (gpio_read(&uart_data[obj->index].sw_cts) == 0) && (obj->uart->FSR & TXFIFO_FULL_MASK);
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else
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isWritable = (obj->uart->FSR & TXFIFO_FULL_MASK);
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return isWritable;
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}
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}
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void serial_clear(serial_t *obj)
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{
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obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
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| 1 << 1 // rx FIFO reset
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| 1 << 2; // tx FIFO reset
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}
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void serial_pinout_tx(PinName tx)
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{
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pinmap_pinout(tx, PinMap_UART_TX);
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}
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void serial_break_set(serial_t *obj)
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{
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obj->uart->LCR |= (1 << 6);
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}
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void serial_break_clear(serial_t *obj)
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{
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obj->uart->LCR &= ~(1 << 6);
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}
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void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
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{
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// Only UART1 has hardware flow control on RDA5991H
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MBED_ASSERT((rxflow != UART0_RX) && (txflow != UART0_TX));
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RDA_UART_TypeDef *uart1 = (uint32_t)obj->uart == (uint32_t)RDA_UART1 ? RDA_UART1 : NULL;
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int index = obj->index;
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// First, disable flow control completely
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uart_data[index].sw_rts.pin = uart_data[index].sw_cts.pin = NC;
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serial_flow_irq_set(obj, 0);
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if (FlowControlNone == type) {
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RDA_GPIO->IFCTRL &= ~(0x01UL << 2); //disable flow control
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return;
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}
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// Check type(s) of flow control to use
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UARTName uart_rts = (UARTName)pinmap_find_peripheral(rxflow, PinMap_UART_RTS);
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UARTName uart_cts = (UARTName)pinmap_find_peripheral(txflow, PinMap_UART_CTS);
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if ((UART_1 == uart_cts) && (NULL != uart1)) {
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pinmap_pinout(txflow, PinMap_UART_CTS);
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gpio_init_in(&uart_data[index].sw_cts, txflow);
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}
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if ((UART_1 == uart_rts) && (NULL != uart1)) {
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pinmap_pinout(rxflow, PinMap_UART_RTS);
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gpio_init_out(&uart_data[index].sw_rts, rxflow);
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serial_flow_irq_set(obj, 1);
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}
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uart1->MCR = uart1->MCR | AFCE_MASK; //enable auto flow control, in this case we don't have to read and write sw_cts & sw_rts
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uart1->FRR = (0x3EUL << 0) | (0x3EUL << 9); //rts/cts fifo trigger
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RDA_GPIO->IFCTRL |= 0x01UL << 2; //enable flow control
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}
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const PinMap *serial_tx_pinmap()
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{
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return PinMap_UART_TX;
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}
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const PinMap *serial_rx_pinmap()
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{
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return PinMap_UART_RX;
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}
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const PinMap *serial_cts_pinmap()
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{
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return PinMap_UART_CTS;
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}
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const PinMap *serial_rts_pinmap()
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{
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return PinMap_UART_RTS;
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}
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