mirror of https://github.com/ARMmbed/mbed-os.git
94 lines
4.8 KiB
C
94 lines
4.8 KiB
C
/**
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******************************************************************************
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* @file spi_ipc7207_map.h
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* @brief SPI IPC 7207 HW register map
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* @internal
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* @author ON Semiconductor
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* $Rev: 2110 $
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* $Date: 2013-07-16 20:13:03 +0530 (Tue, 16 Jul 2013) $
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******************************************************************************
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* Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
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* All rights reserved. This software and/or documentation is licensed by ON Semiconductor
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* under limited terms and conditions. The terms and conditions pertaining to the software
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* and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
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* (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
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* if applicable the software license agreement. Do not use this software and/or
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* documentation unless you have carefully read and you agree to the limited terms and
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* conditions. By using this software and/or documentation, you agree to the limited
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* terms and conditions.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
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* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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* @endinternal
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*
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* @ingroup spi_ipc7207
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*
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* @details
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* <p>
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* SPI HW register map description
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* </p>
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*
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* <h1> Reference document(s) </h1>
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* <p>
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* <a href="../pdf/IPC7207_SPI_APB_DS_v1P2.pdf" target="_blank">
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* IPC7207 APB SPI Design Specification v1.2 </a>
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* </p>
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*/
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#ifndef SPI_IPC7207_MAP_H_
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#define SPI_IPC7207_MAP_H_
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#include "architecture.h"
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/** SPI HW Structure Overlay */
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typedef struct {
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__O uint32_t TX_DATA;
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__I uint32_t RX_DATA;
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__IO uint32_t FDIV;
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union {
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struct {
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__IO uint32_t ENABLE :1; /**< SPI port enable: 0 = disable , 1 = enable */
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__IO uint32_t SAMPLING_EDGE :1; /**< SDI sampling edge: 0 = opposite to SDO edge / 1 = same as SDO edge */
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__IO uint32_t ENDIAN :1; /**< Bits endianness: 0 = LSB first (little-endian) / 1 = MSB first (big-endian) */
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__IO uint32_t CPHA :1; /**< Clock phase: 0 = SDO set before first SCLK edge / 1 = SDO set after first SCLK edge */
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__IO uint32_t CPOL :1; /**< Clock polarity: 0 = active high / 1 = active low */
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__IO uint32_t MODE :1; /**< Device mode: 0 = slave mode / 1 = master mode */
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__IO uint32_t WORD_WIDTH :2; /**< Word width: 0 = 8b / 1 = 16b / 2 = 32b / 3 = reserved */
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} BITS;
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__IO uint32_t WORD;
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} CONTROL;
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union {
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struct {
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__I uint32_t XFER_IP :1; /**< Transfer in progress: 0 = No transfer in progress / 1 = transfer in progress */
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__I uint32_t XFER_ERROR :1;/**< Transfer error: 0 = no error / 1 = SPI Overflow or Underflow */
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__I uint32_t TX_EMPTY :1; /**< Transmit FIFO/buffer empty flag: 0 = not empty / 1 = empty */
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__I uint32_t TX_HALF :1; /**< Transmit FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */
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__I uint32_t TX_FULL :1; /**< Transmit FIFO/buffer full flag: 0 = not full / 1 = full */
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__I uint32_t RX_EMPTY :1; /**< Receive FIFO/buffer empty flag: 0 = not empty / 1 = empty */
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__I uint32_t RX_HALF :1; /**< Receive FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */
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__I uint32_t RX_FULL :1; /**< Receive FIFO/buffer full flag: 0 = not full / 1 = full */
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} BITS;
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__I uint32_t WORD;
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} STATUS;
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union {
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struct {
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__IO uint32_t SS_ENABLE :4; /**< Slave Select (x4): 0 = disable / 1 = enable */
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__IO uint32_t SS_BURST :1; /**< Slave Select burst mode (maintain SS active if TXFIFO not empty) */
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} BITS;
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__IO uint32_t WORD;
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} SLAVE_SELECT;
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__IO uint32_t SLAVE_SELECT_POLARITY; /**< Slave Select polarity for up to 4 slaves:0 = active low / 1 = active high */
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__IO uint32_t IRQ_ENABLE; /**< IRQ (x8) enable: 0 = disable / 1 = enable */
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__I uint32_t IRQ_STATUS; /**< IRQ (x8) status: 0 = no IRQ occurred / 1 = IRQ occurred */
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__O uint32_t IRQ_CLEAR; /**< IRQ (x8) clearing: write 1 to clear IRQ */
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__IO uint32_t TX_WATERMARK; /**< Transmit FIFO Watermark: Defines level of RX Half Full Flag */
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__IO uint32_t RX_WATERMARK; /**< Receive FIFO Watermark: Defines level of TX Half Full Flag */
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__I uint32_t TX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of TX FIFO. */
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__I uint32_t RX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of RX FIFO. */
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} SpiIpc7207Reg_t, *SpiIpc7207Reg_pt;
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#endif /* SPI_IPC7207_MAP_H_ */
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