mirror of https://github.com/ARMmbed/mbed-os.git
88 lines
4.6 KiB
C
88 lines
4.6 KiB
C
/**
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******************************************************************************
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* @file rtc_map.h
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* @brief Real Time Clock HW register map
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* @internal
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* @author ON Semiconductor.
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* $Rev: 3008 $
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* $Date: 2014-10-16 18:42:48 +0530 (Thu, 16 Oct 2014) $
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******************************************************************************
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* Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
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* All rights reserved. This software and/or documentation is licensed by ON Semiconductor
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* under limited terms and conditions. The terms and conditions pertaining to the software
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* and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
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* (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
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* if applicable the software license agreement. Do not use this software and/or
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* documentation unless you have carefully read and you agree to the limited terms and
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* conditions. By using this software and/or documentation, you agree to the limited
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* terms and conditions.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
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* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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* @endinternal
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*
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* @ingroup rtc
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*
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* @details
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* <p>
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* Teal Time Clock HW register map description
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* </p>
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*
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* <h1> Reference document(s) </h1>
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* <p>
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* <a HOURef="../pdf/IPC7206_RTC_APB_DS_v1P0.pdf" target="_blank">
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* IPC7206 APB RTC Design Specification v1.0 </a>
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* </p>
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*/
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#ifndef RTC_MAP_H_
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#define RTC_MAP_H_
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#include "architecture.h"
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/** Real Time Clock Control HW Structure Overlay */
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typedef struct {
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__IO uint32_t SUB_SECOND_COUNTER; /**<SUB SECOND Counter */ /* 0x4000F000 */
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__IO uint32_t SECOND_COUNTER; /**<SECOND Counter */ /* 0x4000F004 */
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__IO uint32_t SUB_SECOND_ALARM; /**< SUB SECOND alarm */ /* 0x4000F008 */
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__IO uint32_t SECOND_ALARM; /**< SECOND alarm */ /* 0x4000F00c */
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union {
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struct {
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__IO uint32_t SUB_SEC_COUNTER_EN :1; /**<Sub-second counter enable. (1=count is enabled, 0=retain count value) */
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__IO uint32_t SEC_COUNTER_EN :1; /**<Second counter enable. (1=count is enabled, 0=retain count value) */
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__IO uint32_t SUB_SECOND_INT_EN :1; /**<Sub-second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
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__IO uint32_t SECOND_INT_EN :1; /**<Second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
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} BITS;
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__IO uint32_t WORD;
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} CONTROL; /* 0x4000F010 */
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union {
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struct {
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/**<Any write to the status register will clear the error bit. */
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__IO uint32_t SUB_SECOND_INT:1; /**<Sub-second interrupt status. (1=interrupt active, 0=no interrupt)*/
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__IO uint32_t SECOND_INT :1; /**<Second interrupt status. (1=interrupt active, 0=no interrupt)*/
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__IO uint32_t WRITE_ERROR :1; /**<Reads error bit which is set when a write occurs before a previous write to the same register has completed. */
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__IO uint32_t BSY_ANY_WRT :1; /**<Busy with any write.*/
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__IO uint32_t BSY_SUB_SEC_CNTR_REG_WRT :1; /**<Busy with a sub-second counter register write.*/
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__IO uint32_t BSY_SEC_CNTR_REG_WRT :1; /**<Busy with a second counter register write.*/
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__IO uint32_t BSY_SUB_SEC_ALRM_REG_WRT :1; /**<Busy with a sub-second alarm register write.*/
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__IO uint32_t BSY_SEC_ALRM_REG_WRT:1; /**<Busy with a second alarm register write.*/
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__IO uint32_t BSY_CTRL_REG_WRT :1; /**<Busy with a control register write.*/
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__IO uint32_t BSY_SUB_SEC_INT_CLR_WRT :1; /**<Busy with a sub-second interrupt clear write.*/
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__IO uint32_t BSY_SEC_INT_CLR_WRT :1; /**<Busy with a second interrupt clear write.*/
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} BITS;
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__IO uint32_t WORD;
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} STATUS; /* 0x4000F014 */
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union {
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struct {
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__O uint32_t SUB_SECOND :1; /**<Write 1 to this register to clear the sub-second interrupt.*/
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__O uint32_t SECOND :1; /**<Write 1 to this register to clear the second interrupt.*/
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} BITS;
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__O uint32_t WORD;
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} INT_CLEAR; /* 0x4000F018 */
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} RtcReg_t, *RtcReg_pt;
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#endif /* RTC_MAP_H_ */
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