mirror of https://github.com/ARMmbed/mbed-os.git
308 lines
11 KiB
C
308 lines
11 KiB
C
/**
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*******************************************************************************
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* @file rtc.c
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* @brief Implementation of a Rtc driver
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* @internal
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* @author ON Semiconductor
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* $Rev: 3525 $
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* $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $
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******************************************************************************
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* Copyright 2016 Semiconductor Components Industries LLC (d/b/a <20>ON Semiconductor<6F>).
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* All rights reserved. This software and/or documentation is licensed by ON Semiconductor
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* under limited terms and conditions. The terms and conditions pertaining to the software
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* and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
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* (<28>ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software<72>) and
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* if applicable the software license agreement. Do not use this software and/or
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* documentation unless you have carefully read and you agree to the limited terms and
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* conditions. By using this software and/or documentation, you agree to the limited
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* terms and conditions.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
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* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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* @endinternal
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*
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* @ingroup rtc
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*
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* @details
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* A real-time clock (RTC) is a computer clock ,that keeps track of the current time. The heart of the RTC is a series of
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* freely running counters one for each time unit, The series of counters is linked as follows: a roll over event of
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* the seconds counter produces a minutes enable pulse; a roll over event of the minutes counter produces an hours
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* enable pulse, etc.Note that all Counter registers are in an undefined state on power-up.
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* Use the Reset bit in the Control Register to reset the counters to their default values.
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* DIVISOR is the register containing the value to divide the clock frequency to produce 1Hz strobe ; 1Hz strobe is used
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* internally to time the incrementing of the Seconds Counter.
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* There is a set of register to set the values in the counter for each time unit.from where time is start to increment.
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* There is another set of register to set the ALARM ...Each of the Alarm Registers can be programmed with a value that
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* is used to compare to a Counter Register in order to produce an alarm (an interrupt) when the values match.
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* There is a programmable bit in each Alarm Register that determines if the alarm occurs upon a value match, or
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* if the alarm occurs upon a Counter increment condition.
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*
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*/
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#if DEVICE_RTC
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#include "rtc.h"
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#include "mbed_assert.h"
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#include "lp_ticker_api.h"
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static volatile uint64_t last_time_read;
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/**
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* Convert sub seconds ticks to micro seconds.
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* The clock running at 32kHz, a tick is 1/32768 of a second.
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*/
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static inline uint32_t ticks_to_us(uint16_t ticks) {
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return (((uint64_t)ticks * RTC_SEC_TO_US) / RTC_CLOCK_HZ);
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}
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/**
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* Convert us into sub seconds ticks.
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* @note result might be troncated to be in the range [0 - RTC_SUB_SEC_MASK].
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*/
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static inline uint16_t us_to_ticks(uint32_t us) {
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return (((uint64_t) us * RTC_CLOCK_HZ) / RTC_SEC_TO_US) & RTC_SUB_SEC_MASK;
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}
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#define RTC_TICK_THRESHOLD 5
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/* See rtc.h for details */
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void fRtcInit(void)
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{
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CLOCK_ENABLE(CLOCK_RTC); /* enable rtc peripheral */
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CLOCKREG->CCR.BITS.RTCEN = True; /* Enable RTC clock 32K */
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/* Reset RTC control register */
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RTCREG->CONTROL.WORD = 0;
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/* Initialize all counters */
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RTCREG->SECOND_COUNTER = 0;
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RTCREG->SUB_SECOND_COUNTER = 0;
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RTCREG->SECOND_ALARM = 0;
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RTCREG->SUB_SECOND_ALARM = 0;
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last_time_read = 0;
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/* Reset RTC Status register */
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RTCREG->STATUS.WORD = 0;
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/* Clear interrupt status */
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RTCREG->INT_CLEAR.WORD = (
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(1 << RTC_INT_CLR_SUB_SEC_BIT_POS) |
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(1 << RTC_INT_CLR_SEC_BIT_POS)
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);
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/* Wait previous write to complete */
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while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
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/* Start sec & sub_sec counter */
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RTCREG->CONTROL.WORD |= (
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(True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
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(True << RTC_CONTROL_SEC_CNT_START_BIT_POS)
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);
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/* enable interruption associated with the rtc at NVIC level */
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NVIC_SetVector(Rtc_IRQn,(uint32_t) fRtcHandler); /* TODO define lp_ticker_isr */
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NVIC_ClearPendingIRQ(Rtc_IRQn);
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NVIC_EnableIRQ(Rtc_IRQn);
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/* Wait for RTC to finish writing register */
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while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
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}
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/* See rtc.h for details */
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void fRtcFree(void)
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{
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/* Disable interrupts and counter */
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RTCREG->CONTROL.WORD = 0;
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/* disable interruption associated with the rtc */
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NVIC_DisableIRQ(Rtc_IRQn);
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/* Wait for RTC to finish writing register */
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while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
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}
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/* See rtc.h for details */
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void fRtcSetInterrupt(uint32_t timestamp)
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{
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uint64_t current_time = fRtcRead();
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uint64_t full_timestamp = (current_time & ~UINT32_MAX) | timestamp;
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if ( (uint32_t)current_time > timestamp) {
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full_timestamp += ((uint64_t) UINT32_MAX) + 1;
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}
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uint32_t target_seconds = full_timestamp / RTC_SEC_TO_US;
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uint16_t target_ticks = us_to_ticks(full_timestamp);
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/*
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* If the interrupt is in more than one second from now then use the
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* second alarm, otherwise use the subsecond alarm.
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* In case of the second alarm is used, there is no need to preserve the
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* remaining subsecond because the irq handler should manage spurious
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* interrupts (like when the timestamp is in the past). In such case, irq
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* handler will schedule a new interrupt with the remaining us.
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*/
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NVIC_DisableIRQ(Rtc_IRQn);
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if (target_seconds != RTCREG->SECOND_COUNTER) {
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RTCREG->SECOND_ALARM = target_seconds;
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uint32_t rtc_control = RTCREG->CONTROL.WORD;
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rtc_control |= (1 << RTC_CONTROL_SEC_CNT_INT_BIT_POS); // enable seconds interrupt
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rtc_control &= ~(1 << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS); // disable sub sec interrupt
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RTCREG->CONTROL.WORD = rtc_control;
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} else {
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uint16_t current_ticks = RTCREG->SUB_SECOND_COUNTER;
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if (current_ticks == target_ticks ||
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((target_ticks > current_ticks) && ((target_ticks - current_ticks) < RTC_TICK_THRESHOLD)) ||
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((target_ticks < current_ticks) && ((RTC_SUB_SEC_MASK - (current_ticks - target_ticks)) < RTC_TICK_THRESHOLD))) {
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// target ticks too close; schedule the interrupt immediately
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NVIC_SetPendingIRQ(Rtc_IRQn);
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} else {
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RTCREG->SUB_SECOND_ALARM = target_ticks;
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uint32_t rtc_control = RTCREG->CONTROL.WORD;
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rtc_control &= ~(1 << RTC_CONTROL_SEC_CNT_INT_BIT_POS); // disable seconds interrupt
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rtc_control |= (1 << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS); // enable sub sec interrupt
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RTCREG->CONTROL.WORD = rtc_control;
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}
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}
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NVIC_EnableIRQ(Rtc_IRQn);
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/* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
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while(RTCREG->STATUS.WORD &
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(
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(True << RTC_STATUS_SUB_SEC_ALARM_WRT_BIT_POS) |
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(True << RTC_STATUS_SEC_ALARM_WRT_BIT_POS) |
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(True << RTC_STATUS_CONTROL_WRT_BIT_POS)
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)
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);
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}
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/* See rtc.h for details */
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void fRtcDisableInterrupt(void)
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{
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NVIC_DisableIRQ(Rtc_IRQn);
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}
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/* See rtc.h for details */
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void fRtcEnableInterrupt(void)
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{
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NVIC_EnableIRQ(Rtc_IRQn);
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}
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/* See rtc.h for details */
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void fRtcClearInterrupt(void)
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{
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/* Disable subsec/sec interrupt */
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/* Clear sec & sub_sec interrupts */
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RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
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(True << RTC_INT_CLR_SEC_BIT_POS));
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while((RTCREG->STATUS.WORD & ((True << RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS) |
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(True << RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS)))); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
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}
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/* See rtc.h for details */
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uint64_t fRtcRead(void)
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{
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/* Hardware Bug fix: The rollover of the sub-second counter initiates the increment of the second counter.
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* That means there is one cycle where the sub-second has rolled back to zero and the second counter has not incremented
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* and a read during that cycle will be incorrect. That will occur for one RTC cycle and that is about 31us of exposure.
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* If you read a zero in the sub-second counter then increment the second counter by 1.
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* Alternatively, subtract 1 from the Sub-seconds counter to align the Second and Sub-Second rollover.
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*/
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uint32_t seconds = RTCREG->SECOND_COUNTER;
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uint16_t ticks = (RTCREG->SUB_SECOND_COUNTER - 1) & SUB_SEC_MASK;
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/*
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* If seconds has changed while reading ticks, read them both again.
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*/
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while (seconds != RTCREG->SECOND_COUNTER) {
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seconds = RTCREG->SECOND_COUNTER;
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ticks = (RTCREG->SUB_SECOND_COUNTER - 1) & SUB_SEC_MASK;
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}
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uint64_t current_time = ((uint64_t) seconds * RTC_SEC_TO_US) + ticks_to_us(ticks);
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/*check that the time did not go backwards */
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MBED_ASSERT(current_time >= last_time_read);
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last_time_read = current_time;
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return current_time;
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}
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/* See rtc.h for details */
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void fRtcWrite(uint64_t RtcTimeus)
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{
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uint32_t Second = False;
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uint16_t SubSecond = False;
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/* Stop RTC */
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RTCREG->CONTROL.WORD &= ~((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
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(True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
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if(RtcTimeus > RTC_SEC_TO_US) {
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/* TimeStamp is big enough to set second counter */
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Second = ((RtcTimeus / RTC_SEC_TO_US) & RTC_SEC_MASK);
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}
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RTCREG->SECOND_COUNTER = Second;
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RtcTimeus = RtcTimeus - (Second * RTC_SEC_TO_US);
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if(RtcTimeus > False) {
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/* Convert TimeStamp to sub_seconds */
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SubSecond = (uint16_t)((float)(RtcTimeus * RTC_CLOCK_HZ / RTC_SEC_TO_US)) & RTC_SUB_SEC_MASK;
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}
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/* Set SUB_SEC_ALARM */
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RTCREG->SUB_SECOND_COUNTER = SubSecond;
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while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
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/* Start RTC */
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RTCREG->CONTROL.WORD |= ((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
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(True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
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while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
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}
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/* See rtc.h for details */
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void fRtcHandler(void)
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{
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/* Disable RTC interrupt */
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NVIC_DisableIRQ(Rtc_IRQn);
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/* Clear sec & sub_sec interrupts */
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RTCREG->INT_CLEAR.WORD = (
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(True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
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(True << RTC_INT_CLR_SEC_BIT_POS)
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);
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/* Disable sub seconds and seconds interrupts */
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RTCREG->CONTROL.WORD &= ~(
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(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
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(True << RTC_CONTROL_SEC_CNT_INT_BIT_POS)
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);
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NVIC_EnableIRQ(Rtc_IRQn);
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/* Wait for RTC to finish writing registers */
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while(RTCREG->STATUS.WORD &
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(
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(True << RTC_STATUS_CONTROL_WRT_BIT_POS) |
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(True << RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS) |
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(True << RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS)
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)
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);
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lp_ticker_irq_handler();
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}
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boolean fIsRtcEnabled(void)
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{
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if(RTCREG->CONTROL.BITS.SUB_SEC_COUNTER_EN | RTCREG->CONTROL.BITS.SEC_COUNTER_EN) {
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return True;
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} else {
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return False;
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}
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}
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#endif
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