mirror of https://github.com/ARMmbed/mbed-os.git
120 lines
3.3 KiB
C
120 lines
3.3 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if DEVICE_RTC
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#include "rtc_api.h"
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#include "PeripheralPins.h"
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#include "clk_freqs.h"
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static void init(void) {
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// enable RTC clock
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SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
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// select RTC clock source
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SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
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// Enable external crystal source if clock source is 32KHz
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if (extosc_frequency()==32768) {
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SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(OSC32KCLK);
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}
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else{
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// If main clock is NOT 32KHz crystal, use external 32KHz clock source defined in PeripheralPins.c
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SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(PinMap_RTC[0].peripheral);
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pinmap_pinout(PinMap_RTC[0].pin, PinMap_RTC); //Map RTC clk input (if not NC)
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}
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}
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void rtc_init(void) {
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init();
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// Configure the TSR. default value: 1
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RTC->TSR = 1;
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// Configure Time Compensation Register to calibrate RTC accuracy
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// dissable LRL lock
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RTC->LR &= ~RTC_LR_LRL_MASK;
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// RTC->TCR: RTC_TCR_CIR_MASK,RTC_TCR_CIR(x)=0,RTC_TCR_TCR(x)=0 Default no correction
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RTC->TCR = RTC_TCR_CIR(0) | RTC_TCR_TCR(0);
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/*
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RTC_TCR_CIR(x) sets the compensation interval in seconds from 1 to 256.
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0x05 will apply the compensation once every 4 seconds.
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RTC_TCR_TCR(x) sets the Register Overflow
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0x80 Time Prescaler Register overflows every 32896 clock cycles. (+128)
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... ... RTC runs slower
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0xFF Time Prescaler Register overflows every 32769 clock cycles.
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0x00 Time Prescaler Register overflows every 32768 clock cycles, Default.
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0x01 Time Prescaler Register overflows every 32767 clock cycles.
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... ... RTC runs faster
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0x7F Time Prescaler Register overflows every 32641 clock cycles. (-128)
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*/
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// enable TCL lock
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RTC->LR |= RTC_LR_TCL_MASK;
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// enable LRL lock
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RTC->LR |= RTC_LR_LRL_MASK;
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// enable counter
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RTC->SR |= RTC_SR_TCE_MASK;
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}
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void rtc_free(void) {
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// [TODO]
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}
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/*
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* Little check routine to see if the RTC has been enabled
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* 0 = Disabled, 1 = Enabled
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*/
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int rtc_isenabled(void) {
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// even if the RTC module is enabled,
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// as we use RTC_CLKIN and an external clock,
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// we need to reconfigure the pins. That is why we
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// call init() if the rtc is enabled
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// if RTC not enabled return 0
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SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
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SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
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if ((RTC->SR & RTC_SR_TCE_MASK) == 0)
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return 0;
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init();
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return 1;
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}
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time_t rtc_read(void) {
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return RTC->TSR;
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}
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void rtc_write(time_t t) {
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// disable counter
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RTC->SR &= ~RTC_SR_TCE_MASK;
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// we do not write 0 into TSR
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// to avoid invalid time
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if (t == 0)
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t = 1;
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// write seconds
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RTC->TSR = t;
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// re-enable counter
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RTC->SR |= RTC_SR_TCE_MASK;
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}
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#endif
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