mirror of https://github.com/ARMmbed/mbed-os.git
320 lines
10 KiB
C
320 lines
10 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2017, STMicroelectronics
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cmsis.h"
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#include "objects.h"
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#include "platform/mbed_error.h"
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int mbed_sdk_inited = 0;
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extern void SetSysClock(void);
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#if defined(RCC_LSE_HIGHDRIVE_MODE) || defined(RCC_LSEDRIVE_HIGH)
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# define LSE_CONFIG_AVAILABLE
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#endif
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// set defaults for LSE drive load level
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#if defined(LSE_CONFIG_AVAILABLE)
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# if defined(MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL)
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# define LSE_DRIVE_LOAD_LEVEL MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL
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# else
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# if defined(RCC_LSE_HIGHDRIVE_MODE) // STM32F4
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# define LSE_DRIVE_LOAD_LEVEL RCC_LSE_LOWPOWER_MODE
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# else
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# define LSE_DRIVE_LOAD_LEVEL RCC_LSEDRIVE_LOW
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# endif
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# endif
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/**
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* @brief configure the LSE crystal driver load
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* This settings ist target hardware dependend and
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* depends on the crystal that is used for LSE clock.
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* For low power requirements, crystals with low load capacitors can be used and
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* driver setting is RCC_LSEDRIVE_LOW.
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* For higher stablity, crystals with higher load capacitys can be used and
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* driver setting is RCC_LSEDRIVE_HIGH.
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*
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* A detailed description about this setting can be found here:
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* https://www.st.com/resource/en/application_note/cd00221665-oscillator-design-guide-for-stm8afals-stm32-mcus-and-mpus-stmicroelectronics.pdf
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*
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* LSE maybe used later, but crystal load drive setting is necessary before
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* enabling LSE.
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*
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* @param None
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* @retval None
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*/
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static void LSEDriveConfig(void) {
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HAL_PWR_EnableBkUpAccess();
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#if defined(__HAL_RCC_LSEDRIVE_CONFIG)
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__HAL_RCC_LSEDRIVE_CONFIG(LSE_DRIVE_LOAD_LEVEL);
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#else
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HAL_RCCEx_SelectLSEMode(LSE_DRIVE_LOAD_LEVEL);
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#endif
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}
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#endif // LSE_CONFIG_AVAILABLE
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/**
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* @brief Setup the target board-specific configuration
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* of the microcontroller
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*
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* @note If used, this function should be implemented
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* elsewhere. This declaration is weak so it may be overridden
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* by user code.
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*
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* @param None
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* @retval None
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*/
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MBED_WEAK void TargetBSP_Init(void) {
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/** Do nothing */
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}
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void GPIO_Full_Init(void) {
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GPIO_InitTypeDef GPIO_InitStruct;
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GPIO_InitStruct.Pin = GPIO_PIN_All;
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GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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#if !TARGET_STM32F1
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Alternate = 0;
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#endif
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#if defined(GPIOA)
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__HAL_RCC_GPIOA_CLK_ENABLE();
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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__HAL_RCC_GPIOA_CLK_DISABLE();
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#endif
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#if defined(GPIOB)
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__HAL_RCC_GPIOB_CLK_ENABLE();
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HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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__HAL_RCC_GPIOB_CLK_DISABLE();
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#endif
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#if defined(GPIOC)
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__HAL_RCC_GPIOC_CLK_ENABLE();
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HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
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__HAL_RCC_GPIOC_CLK_DISABLE();
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#endif
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#if defined(GPIOD)
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__HAL_RCC_GPIOD_CLK_ENABLE();
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HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
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__HAL_RCC_GPIOD_CLK_DISABLE();
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#endif
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#if defined(GPIOE)
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__HAL_RCC_GPIOE_CLK_ENABLE();
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HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
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__HAL_RCC_GPIOE_CLK_DISABLE();
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#endif
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#if defined(GPIOF)
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__HAL_RCC_GPIOF_CLK_ENABLE();
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HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
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__HAL_RCC_GPIOF_CLK_DISABLE();
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#endif
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#if defined(GPIOG)
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__HAL_RCC_GPIOG_CLK_ENABLE();
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HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
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__HAL_RCC_GPIOG_CLK_DISABLE();
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#endif
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#if defined(GPIOH)
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__HAL_RCC_GPIOH_CLK_ENABLE();
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HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
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__HAL_RCC_GPIOH_CLK_DISABLE();
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#endif
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#if defined(GPIOI)
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__HAL_RCC_GPIOI_CLK_ENABLE();
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HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
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__HAL_RCC_GPIOI_CLK_DISABLE();
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#endif
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#if defined(GPIOJ)
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__HAL_RCC_GPIOJ_CLK_ENABLE();
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HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct);
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__HAL_RCC_GPIOJ_CLK_DISABLE();
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#endif
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#if defined(GPIOK)
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__HAL_RCC_GPIOK_CLK_ENABLE();
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HAL_GPIO_Init(GPIOK, &GPIO_InitStruct);
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__HAL_RCC_GPIOK_CLK_DISABLE();
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#endif
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}
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// This function is called after RAM initialization and before main.
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void mbed_sdk_init()
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{
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#if defined(__ICACHE_PRESENT) /* STM32F7 */
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// The mbed_sdk_init can be called either during cold boot or during
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// application boot after bootloader has been executed.
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// In case the bootloader has already enabled the cache,
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// is is needed to not enable it again.
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if ((SCB->CCR & (uint32_t)SCB_CCR_IC_Msk) == 0) { // If ICache is disabled
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SCB_EnableICache();
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}
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if ((SCB->CCR & (uint32_t)SCB_CCR_DC_Msk) == 0) { // If DCache is disabled
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SCB_EnableDCache();
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}
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#endif /* __ICACHE_PRESENT */
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#if defined(DUAL_CORE)
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/* HW semaphore Clock enable*/
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__HAL_RCC_HSEM_CLK_ENABLE();
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#if defined(CORE_CM4)
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__HAL_RCC_FLASH_C2_ALLOCATE();
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/* Check wether CM4 boot in parallel with CM7. If CM4 was gated but CM7 trigger the CM4 boot. No need to wait for synchronization.
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otherwise wait for CM7, which is in charge of sytem clock configuration */
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if (!LL_RCC_IsCM4BootForced()) {
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/* CM4 boots at the same time than CM7. It is necessary to synchronize with CM7, by mean of HSEM, that CM7 finishes its initialization. */
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/* Activate HSEM notification for Cortex-M4*/
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LL_HSEM_EnableIT_C2IER(HSEM, CFG_HW_STOP_MODE_MASK_SEMID);
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/*
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* Domain D2 goes to STOP mode (Cortex-M4 in deep-sleep) waiting for
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* Cortex-M7 to perform system initialization (system clock config,
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* external memory configuration.. )
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*/
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/* Select the domain Power Down DeepSleep */
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LL_PWR_SetRegulModeDS(LL_PWR_REGU_DSMODE_MAIN);
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/* Keep DSTOP mode when D2 domain enters Deepsleep */
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LL_PWR_CPU_SetD2PowerMode(LL_PWR_CPU_MODE_D2STOP);
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LL_PWR_CPU2_SetD2PowerMode(LL_PWR_CPU2_MODE_D2STOP);
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/* Set SLEEPDEEP bit of Cortex System Control Register */
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LL_LPM_EnableDeepSleep();
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/* Ensure that all instructions done before entering STOP mode */
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__DSB();
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__ISB();
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/* Request Wait For Event */
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__WFE();
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/* Reset SLEEPDEEP bit of Cortex System Control Register,
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* the following LL API Clear SLEEPDEEP bit of Cortex
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* System Control Register
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*/
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LL_LPM_EnableSleep();
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/* Clear HSEM flag */
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LL_HSEM_DisableIT_C2IER(HSEM, CFG_HW_STOP_MODE_MASK_SEMID);
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LL_HSEM_ClearFlag_C2ICR(HSEM, CFG_HW_STOP_MODE_MASK_SEMID);
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}
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// Update the SystemCoreClock variable.
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SystemCoreClockUpdate();
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HAL_Init();
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#else
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/* CORE_M7 */
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// Update the SystemCoreClock variable.
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SystemCoreClockUpdate();
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HAL_Init();
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/* Configure the System clock source, PLL Multiplier and Divider factors,
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AHB/APBx prescalers and Flash settings */
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#if defined(LSE_CONFIG_AVAILABLE)
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// LSE oscillator drive capability set before LSE is started
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if (!LL_RCC_LSE_IsReady()) {
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LSEDriveConfig();
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}
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#endif
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#if defined(MBED_CONF_TARGET_SYSTEM_POWER_SUPPLY)
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#if IS_PWR_SUPPLY(MBED_CONF_TARGET_SYSTEM_POWER_SUPPLY)
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HAL_PWREx_ConfigSupply(MBED_CONF_TARGET_SYSTEM_POWER_SUPPLY);
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#else
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#error system_power_supply not configured
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#endif
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#endif
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SetSysClock();
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SystemCoreClockUpdate();
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/* Check wether CM4 boot in parallel with CM7. If CM4 was gated but CM7 trigger the CM4 boot. No need to wait for synchronization.
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otherwise CM7 should wakeup CM4 when system clocks initialization is done. */
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if (READ_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4)) {
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LL_HSEM_1StepLock(HSEM, CFG_HW_STOP_MODE_SEMID);
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/*Release HSEM in order to notify the CPU2(CM4)*/
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LL_HSEM_ReleaseLock(HSEM, CFG_HW_STOP_MODE_SEMID, 0);
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} else {
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LL_RCC_ForceCM4Boot();
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}
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/* wait until CPU2 wakes up from stop mode */
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while (LL_RCC_D2CK_IsReady() == 0);
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#endif /* CORE_M4 */
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#else /* Single core */
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// Update the SystemCoreClock variable.
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SystemCoreClockUpdate();
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HAL_Init();
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#if defined(LSE_CONFIG_AVAILABLE)
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// LSE oscillator drive capability set before LSE is started
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if (!LL_RCC_LSE_IsReady()) {
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LSEDriveConfig();
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}
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#endif
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#if defined(MBED_CONF_TARGET_SYSTEM_POWER_SUPPLY)
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#if IS_PWR_SUPPLY(MBED_CONF_TARGET_SYSTEM_POWER_SUPPLY)
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HAL_PWREx_ConfigSupply(MBED_CONF_TARGET_SYSTEM_POWER_SUPPLY);
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#else
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#error system_power_supply not configured
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#endif
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#endif
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SetSysClock();
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SystemCoreClockUpdate();
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#endif /* DUAL_CORE */
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/* Start LSI clock for RTC */
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#if DEVICE_RTC
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#if !MBED_CONF_TARGET_LSE_AVAILABLE
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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if (__HAL_RCC_GET_RTC_SOURCE() != RCC_RTCCLKSOURCE_NO_CLK) {
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#if TARGET_STM32WB
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1;
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#else
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
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#endif
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
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RCC_OscInitStruct.LSIState = RCC_LSI_ON;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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error("Init : cannot initialize LSI\n");
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}
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}
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#endif /* ! MBED_CONF_TARGET_LSE_AVAILABLE */
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#endif /* DEVICE_RTC */
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/* Reset all GPIO */
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GPIO_Full_Init();
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/* BSP initialization hook (external RAM, etc) */
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TargetBSP_Init();
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mbed_sdk_inited = 1;
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}
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