mirror of https://github.com/ARMmbed/mbed-os.git
170 lines
7.8 KiB
C
170 lines
7.8 KiB
C
/***************************************************************************//**
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* \file cyip_lpcomp.h
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*
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* \brief
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* LPCOMP IP definitions
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*
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* \note
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* Generator version: 1.2.0.117
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* Database revision: rev#1034984
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*
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********************************************************************************
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* \copyright
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* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*******************************************************************************/
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#ifndef _CYIP_LPCOMP_H_
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#define _CYIP_LPCOMP_H_
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#include "cyip_headers.h"
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/*******************************************************************************
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* LPCOMP
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*******************************************************************************/
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#define LPCOMP_SECTION_SIZE 0x00010000UL
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/**
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* \brief Low Power Comparators (LPCOMP)
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*/
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typedef struct {
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__IOM uint32_t CONFIG; /*!< 0x00000000 LPCOMP Configuration Register */
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__IM uint32_t STATUS; /*!< 0x00000004 LPCOMP Status Register */
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__IM uint32_t RESERVED[2];
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__IOM uint32_t INTR; /*!< 0x00000010 LPCOMP Interrupt request register */
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__IOM uint32_t INTR_SET; /*!< 0x00000014 LPCOMP Interrupt set register */
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__IOM uint32_t INTR_MASK; /*!< 0x00000018 LPCOMP Interrupt request mask */
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__IM uint32_t INTR_MASKED; /*!< 0x0000001C LPCOMP Interrupt request masked */
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__IM uint32_t RESERVED1[8];
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__IOM uint32_t CMP0_CTRL; /*!< 0x00000040 Comparator 0 control Register */
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__IM uint32_t RESERVED2[3];
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__IOM uint32_t CMP0_SW; /*!< 0x00000050 Comparator 0 switch control */
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__IOM uint32_t CMP0_SW_CLEAR; /*!< 0x00000054 Comparator 0 switch control clear */
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__IM uint32_t RESERVED3[10];
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__IOM uint32_t CMP1_CTRL; /*!< 0x00000080 Comparator 1 control Register */
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__IM uint32_t RESERVED4[3];
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__IOM uint32_t CMP1_SW; /*!< 0x00000090 Comparator 1 switch control */
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__IOM uint32_t CMP1_SW_CLEAR; /*!< 0x00000094 Comparator 1 switch control clear */
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} LPCOMP_Type; /*!< Size = 152 (0x98) */
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/* LPCOMP.CONFIG */
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#define LPCOMP_CONFIG_LPREF_EN_Pos 30UL
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#define LPCOMP_CONFIG_LPREF_EN_Msk 0x40000000UL
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#define LPCOMP_CONFIG_ENABLED_Pos 31UL
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#define LPCOMP_CONFIG_ENABLED_Msk 0x80000000UL
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/* LPCOMP.STATUS */
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#define LPCOMP_STATUS_OUT0_Pos 0UL
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#define LPCOMP_STATUS_OUT0_Msk 0x1UL
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#define LPCOMP_STATUS_OUT1_Pos 16UL
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#define LPCOMP_STATUS_OUT1_Msk 0x10000UL
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/* LPCOMP.INTR */
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#define LPCOMP_INTR_COMP0_Pos 0UL
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#define LPCOMP_INTR_COMP0_Msk 0x1UL
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#define LPCOMP_INTR_COMP1_Pos 1UL
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#define LPCOMP_INTR_COMP1_Msk 0x2UL
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/* LPCOMP.INTR_SET */
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#define LPCOMP_INTR_SET_COMP0_Pos 0UL
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#define LPCOMP_INTR_SET_COMP0_Msk 0x1UL
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#define LPCOMP_INTR_SET_COMP1_Pos 1UL
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#define LPCOMP_INTR_SET_COMP1_Msk 0x2UL
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/* LPCOMP.INTR_MASK */
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#define LPCOMP_INTR_MASK_COMP0_MASK_Pos 0UL
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#define LPCOMP_INTR_MASK_COMP0_MASK_Msk 0x1UL
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#define LPCOMP_INTR_MASK_COMP1_MASK_Pos 1UL
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#define LPCOMP_INTR_MASK_COMP1_MASK_Msk 0x2UL
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/* LPCOMP.INTR_MASKED */
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#define LPCOMP_INTR_MASKED_COMP0_MASKED_Pos 0UL
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#define LPCOMP_INTR_MASKED_COMP0_MASKED_Msk 0x1UL
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#define LPCOMP_INTR_MASKED_COMP1_MASKED_Pos 1UL
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#define LPCOMP_INTR_MASKED_COMP1_MASKED_Msk 0x2UL
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/* LPCOMP.CMP0_CTRL */
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#define LPCOMP_CMP0_CTRL_MODE0_Pos 0UL
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#define LPCOMP_CMP0_CTRL_MODE0_Msk 0x3UL
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#define LPCOMP_CMP0_CTRL_HYST0_Pos 5UL
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#define LPCOMP_CMP0_CTRL_HYST0_Msk 0x20UL
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#define LPCOMP_CMP0_CTRL_INTTYPE0_Pos 6UL
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#define LPCOMP_CMP0_CTRL_INTTYPE0_Msk 0xC0UL
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#define LPCOMP_CMP0_CTRL_DSI_BYPASS0_Pos 10UL
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#define LPCOMP_CMP0_CTRL_DSI_BYPASS0_Msk 0x400UL
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#define LPCOMP_CMP0_CTRL_DSI_LEVEL0_Pos 11UL
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#define LPCOMP_CMP0_CTRL_DSI_LEVEL0_Msk 0x800UL
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/* LPCOMP.CMP0_SW */
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#define LPCOMP_CMP0_SW_CMP0_IP0_Pos 0UL
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#define LPCOMP_CMP0_SW_CMP0_IP0_Msk 0x1UL
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#define LPCOMP_CMP0_SW_CMP0_AP0_Pos 1UL
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#define LPCOMP_CMP0_SW_CMP0_AP0_Msk 0x2UL
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#define LPCOMP_CMP0_SW_CMP0_BP0_Pos 2UL
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#define LPCOMP_CMP0_SW_CMP0_BP0_Msk 0x4UL
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#define LPCOMP_CMP0_SW_CMP0_IN0_Pos 4UL
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#define LPCOMP_CMP0_SW_CMP0_IN0_Msk 0x10UL
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#define LPCOMP_CMP0_SW_CMP0_AN0_Pos 5UL
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#define LPCOMP_CMP0_SW_CMP0_AN0_Msk 0x20UL
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#define LPCOMP_CMP0_SW_CMP0_BN0_Pos 6UL
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#define LPCOMP_CMP0_SW_CMP0_BN0_Msk 0x40UL
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#define LPCOMP_CMP0_SW_CMP0_VN0_Pos 7UL
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#define LPCOMP_CMP0_SW_CMP0_VN0_Msk 0x80UL
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/* LPCOMP.CMP0_SW_CLEAR */
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#define LPCOMP_CMP0_SW_CLEAR_CMP0_IP0_Pos 0UL
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#define LPCOMP_CMP0_SW_CLEAR_CMP0_IP0_Msk 0x1UL
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#define LPCOMP_CMP0_SW_CLEAR_CMP0_AP0_Pos 1UL
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#define LPCOMP_CMP0_SW_CLEAR_CMP0_AP0_Msk 0x2UL
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#define LPCOMP_CMP0_SW_CLEAR_CMP0_BP0_Pos 2UL
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#define LPCOMP_CMP0_SW_CLEAR_CMP0_BP0_Msk 0x4UL
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#define LPCOMP_CMP0_SW_CLEAR_CMP0_IN0_Pos 4UL
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#define LPCOMP_CMP0_SW_CLEAR_CMP0_IN0_Msk 0x10UL
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#define LPCOMP_CMP0_SW_CLEAR_CMP0_AN0_Pos 5UL
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#define LPCOMP_CMP0_SW_CLEAR_CMP0_AN0_Msk 0x20UL
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#define LPCOMP_CMP0_SW_CLEAR_CMP0_BN0_Pos 6UL
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#define LPCOMP_CMP0_SW_CLEAR_CMP0_BN0_Msk 0x40UL
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#define LPCOMP_CMP0_SW_CLEAR_CMP0_VN0_Pos 7UL
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#define LPCOMP_CMP0_SW_CLEAR_CMP0_VN0_Msk 0x80UL
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/* LPCOMP.CMP1_CTRL */
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#define LPCOMP_CMP1_CTRL_MODE1_Pos 0UL
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#define LPCOMP_CMP1_CTRL_MODE1_Msk 0x3UL
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#define LPCOMP_CMP1_CTRL_HYST1_Pos 5UL
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#define LPCOMP_CMP1_CTRL_HYST1_Msk 0x20UL
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#define LPCOMP_CMP1_CTRL_INTTYPE1_Pos 6UL
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#define LPCOMP_CMP1_CTRL_INTTYPE1_Msk 0xC0UL
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#define LPCOMP_CMP1_CTRL_DSI_BYPASS1_Pos 10UL
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#define LPCOMP_CMP1_CTRL_DSI_BYPASS1_Msk 0x400UL
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#define LPCOMP_CMP1_CTRL_DSI_LEVEL1_Pos 11UL
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#define LPCOMP_CMP1_CTRL_DSI_LEVEL1_Msk 0x800UL
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/* LPCOMP.CMP1_SW */
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#define LPCOMP_CMP1_SW_CMP1_IP1_Pos 0UL
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#define LPCOMP_CMP1_SW_CMP1_IP1_Msk 0x1UL
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#define LPCOMP_CMP1_SW_CMP1_AP1_Pos 1UL
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#define LPCOMP_CMP1_SW_CMP1_AP1_Msk 0x2UL
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#define LPCOMP_CMP1_SW_CMP1_BP1_Pos 2UL
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#define LPCOMP_CMP1_SW_CMP1_BP1_Msk 0x4UL
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#define LPCOMP_CMP1_SW_CMP1_IN1_Pos 4UL
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#define LPCOMP_CMP1_SW_CMP1_IN1_Msk 0x10UL
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#define LPCOMP_CMP1_SW_CMP1_AN1_Pos 5UL
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#define LPCOMP_CMP1_SW_CMP1_AN1_Msk 0x20UL
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#define LPCOMP_CMP1_SW_CMP1_BN1_Pos 6UL
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#define LPCOMP_CMP1_SW_CMP1_BN1_Msk 0x40UL
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#define LPCOMP_CMP1_SW_CMP1_VN1_Pos 7UL
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#define LPCOMP_CMP1_SW_CMP1_VN1_Msk 0x80UL
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/* LPCOMP.CMP1_SW_CLEAR */
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#define LPCOMP_CMP1_SW_CLEAR_CMP1_IP1_Pos 0UL
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#define LPCOMP_CMP1_SW_CLEAR_CMP1_IP1_Msk 0x1UL
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#define LPCOMP_CMP1_SW_CLEAR_CMP1_AP1_Pos 1UL
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#define LPCOMP_CMP1_SW_CLEAR_CMP1_AP1_Msk 0x2UL
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#define LPCOMP_CMP1_SW_CLEAR_CMP1_BP1_Pos 2UL
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#define LPCOMP_CMP1_SW_CLEAR_CMP1_BP1_Msk 0x4UL
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#define LPCOMP_CMP1_SW_CLEAR_CMP1_IN1_Pos 4UL
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#define LPCOMP_CMP1_SW_CLEAR_CMP1_IN1_Msk 0x10UL
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#define LPCOMP_CMP1_SW_CLEAR_CMP1_AN1_Pos 5UL
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#define LPCOMP_CMP1_SW_CLEAR_CMP1_AN1_Msk 0x20UL
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#define LPCOMP_CMP1_SW_CLEAR_CMP1_BN1_Pos 6UL
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#define LPCOMP_CMP1_SW_CLEAR_CMP1_BN1_Msk 0x40UL
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#define LPCOMP_CMP1_SW_CLEAR_CMP1_VN1_Pos 7UL
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#define LPCOMP_CMP1_SW_CLEAR_CMP1_VN1_Msk 0x80UL
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#endif /* _CYIP_LPCOMP_H_ */
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/* [] END OF FILE */
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