mirror of https://github.com/ARMmbed/mbed-os.git
165 lines
6.3 KiB
C
165 lines
6.3 KiB
C
/* mbed Microcontroller Library
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* Copyright (C) 2008-2015 ARM Limited. All rights reserved.
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*
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* ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
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*/
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#include <stdint.h>
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#include "LPC24xx.h"
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#define CLOCK_SETUP 1
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#define SCS_Val ((1<<4) | (1 << 5))
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#define CLKSRCSEL_Val 0x00000001
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#define PLL0_SETUP 1
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#define PLL0CFG_Val 0x0000000B
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#define CCLKCFG_Val 0x00000003
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#define USBCLKCFG_Val 0x00000005
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#define PCLKSEL0_Val 0x00000000
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#define PCLKSEL1_Val 0x00000000
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#define PCONP_Val (1 << PCEMC)
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#define CLKOUTCFG_Val 0x00000000
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#define MAMCR_Val 0x00000002
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#define MAMTIM_Val 0x00000004
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/*----------------------------------------------------------------------------
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DEFINES
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*----------------------------------------------------------------------------*/
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#define XTAL (12000000UL) /* Oscillator frequency */
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#define OSC_CLK ( XTAL) /* Main oscillator frequency */
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#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
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#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
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/* F_cco0 = (2 * M * F_in) / N */
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#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
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#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
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#define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
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#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
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/* Determine core clock frequency according to settings */
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#if (PLL0_SETUP)
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#if ((CLKSRCSEL_Val & 0x03) == 1)
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#define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
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#elif ((CLKSRCSEL_Val & 0x03) == 2)
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#define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
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#else
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#define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
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#endif
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#endif
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/*----------------------------------------------------------------------------
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Clock Variable definitions
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*----------------------------------------------------------------------------*/
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uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
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/*----------------------------------------------------------------------------
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Clock functions
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*----------------------------------------------------------------------------*/
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void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
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{
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/* Determine clock frequency according to clock register values */
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if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
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switch (LPC_SC->CLKSRCSEL & 0x03) {
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case 0: /* Int. RC oscillator => PLL0 */
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case 3: /* Reserved, default to Int. RC */
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SystemCoreClock = (IRC_OSC *
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(((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
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(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
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((LPC_SC->CCLKCFG & 0xFF)+ 1));
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break;
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case 1: /* Main oscillator => PLL0 */
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SystemCoreClock = (OSC_CLK *
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(((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
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(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
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((LPC_SC->CCLKCFG & 0xFF)+ 1));
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break;
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case 2: /* RTC oscillator => PLL0 */
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SystemCoreClock = (RTC_CLK *
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(((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
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(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
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((LPC_SC->CCLKCFG & 0xFF)+ 1));
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break;
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}
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} else {
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switch (LPC_SC->CLKSRCSEL & 0x03) {
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case 0: /* Int. RC oscillator => PLL0 */
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case 3: /* Reserved, default to Int. RC */
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SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
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break;
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case 1: /* Main oscillator => PLL0 */
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SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
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break;
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case 2: /* RTC oscillator => PLL0 */
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SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
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break;
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}
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}
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}
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void vectorRemap()
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{
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#define ARM_VECTOR_REBASE (0x40000000)
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extern unsigned long __privileged_code_start__; /* Startup code address from linker */
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int i;
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/* Copy ARM vector table into internal RAM */
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for (i = 0; i <= 56; i+=2)
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{
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*(unsigned short *)(ARM_VECTOR_REBASE + i) = *(unsigned short *)((unsigned long)(&__privileged_code_start__) + i);
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}
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// *(unsigned long *)(ARM_VECTOR_REBASE) = (unsigned long)armUnexpReset;
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/* Remap the interrupt vectors to RAM */
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LPC_SC->MEMMAP = 2;
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}
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System and update the SystemFrequency variable.
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*/
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void SystemInit (void)
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{
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LPC_WDT->WDMOD = 0; /* Disable internal watchdog */
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#if (CLOCK_SETUP) /* Clock Setup */
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LPC_SC->SCS = SCS_Val;
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if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
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while ((LPC_SC->SCS & (1 << 6)) == 0); /* Wait for Oscillator to be ready */
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}
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LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
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#if (PLL0_SETUP)
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LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
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LPC_SC->PLL0CFG = PLL0CFG_Val;
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LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
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LPC_SC->PLL0FEED = 0xAA;
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LPC_SC->PLL0FEED = 0x55;
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while (!(LPC_SC->PLL0STAT & (1 << 26))); /* Wait for PLOCK0 */
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LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
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LPC_SC->PLL0FEED = 0xAA;
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LPC_SC->PLL0FEED = 0x55;
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#endif
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LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
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#endif
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LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
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LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
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LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
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// Setup MAM
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LPC_SC->MAMTIM = MAMTIM_Val;
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LPC_SC->MAMCR = MAMCR_Val;
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vectorRemap();
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}
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