mirror of https://github.com/ARMmbed/mbed-os.git
312 lines
13 KiB
C
312 lines
13 KiB
C
/**
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*******************************************************************************
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* @file system_TMPM3Hx.c
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for the
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* TOSHIBA 'TMPM3Hx' Device Series
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* @version V1.0.7.0
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* $Date:: 2017-11-06 #$
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*
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* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT.
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*
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* (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
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*******************************************************************************
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*/
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#include "TMPM3H6.h"
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/*-------- <<< Start of configuration section >>> ----------------------------*/
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/* Semi-Independent Watchdog Timer (SIWDT) Configuration */
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#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */
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#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */
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#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */
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/* Clock Generator (CG) Configuration */
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#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */
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#define SYSCR_Val (0x00000000UL)
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#define STBYCR_Val (0x00000000UL)
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#define CG_6M_MUL_6_664_FPLL (0x001C7535UL<<8U) /* fPLL = 6MHz * 6.664 */
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#define CG_8M_MUL_5_FPLL (0x00247028UL<<8U) /* fPLL = 8MHz * 5 */
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#define CG_10M_MUL_4_FPLL (0x002E7020UL<<8U) /* fPLL = 10MHz * 4 */
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#define CG_12M_MUL_3_328_FPLL (0x0036FA1AUL<<8U) /* fPLL = 12MHz * 3.328 */
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#define CG_PLL0SEL_PLL0ON_SET ((uint32_t)0x00000001)
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#define CG_PLL0SEL_PLL0ON_CLEAR ((uint32_t)0xFFFFFFFE)
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#define CG_PLL0SEL_PLL0SEL_SET ((uint32_t)0x00000002)
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#define CG_PLL0SEL_PLL0SEL_CLEAR ((uint32_t)0xFFFFFFFD)
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#define CG_OSCCR_IHOSC1EN_CLEAR ((uint32_t)0xFFFFFFFE)
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#define CG_OSCCR_EOSCEN_SET ((uint32_t)0x00000002)
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#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100)
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#define CG_WUPHCR_WUON_START_SET ((uint32_t)0x00000001)
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#if (CLOCK_SETUP)
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#define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000100)
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#define PLL0SEL_Ready CG_12M_MUL_3_328_FPLL
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#else
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#define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000000)
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#define PLL0SEL_Ready CG_10M_MUL_4_FPLL
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#endif
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#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL)
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#define PLL0SEL_MASK (0xFFFFFF00UL)
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/*-------- <<< End of configuration section >>> ------------------------------*/
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/*-------- DEFINES -----------------------------------------------------------*/
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/* Define clocks */
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#define EOSC_6M (6000000UL)
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#define EOSC_8M (8000000UL)
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#define EOSC_10M (10000000UL)
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#define EOSC_12M (12000000UL)
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#define IOSC_10M (10000000UL)
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#define EXTALH EOSC_12M /* External high-speed oscillator freq */
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#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */
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#define EOSC_6M_PLLON (39980000UL) /* 6.00MHz * 53.3125 / 8 */
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#define EOSC_8M_PLLON (40000000UL) /* 8.00MHz * 40.0000 / 8 */
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#define EOSC_10M_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */
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#define EOSC_12M_PLLON (39940000UL) /* 12.00MHz * 26.6250 / 8 */
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#define IOSC_10M_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */
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/* Configure Warm-up time */
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#define HZ_1M (1000000UL)
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#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */
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#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */
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#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */
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#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR<WUPT11:0> = warm-up time(us) * EXTALH / 16 */
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#if (CLOCK_SETUP)
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#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
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#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
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#else
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#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U))
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#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U))
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#endif
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/* Determine core clock frequency according to settings */
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/* System clock is high-speed clock*/
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#if (CLOCK_SETUP)
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#define CORE_TALH (EXTALH)
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#else
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#define CORE_TALH (IXTALH)
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#endif
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#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */
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#if (CORE_TALH == EOSC_6M) /* If input is 6MHz */
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#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_6_664_FPLL))
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#define __CORE_CLK EOSC_6M_PLLON /* output clock is 39.98MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 6MHz */
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#elif (CORE_TALH == EOSC_8M) /* If input is 8MHz */
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#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_5_FPLL))
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#define __CORE_CLK EOSC_8M_PLLON /* output clock is 40MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 8MHz */
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#elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */
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#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL)
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#define __CORE_CLK EOSC_10M_PLLON /* output clock is 40MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 10MHz */
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#elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */
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#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL)
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#define __CORE_CLK EOSC_12M_PLLON /* output clock is 39.94MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 12MHz */
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#elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */
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#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL)
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#define __CORE_CLK IOSC_10M_PLLON /* output clock is 40MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 10MHz */
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#else /* input clock not known */
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#define __CORE_CLK (0U)
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#error "Core Oscillator Frequency invalid!"
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#endif /* End switch input clock */
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#else
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#define __CORE_CLK (CORE_TALH)
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#endif
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#if ((SYSCR_Val & 7U) == 0U) /* Gear -> fc */
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#define __CORE_SYS (__CORE_CLK)
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#elif ((SYSCR_Val & 7U) == 1U) /* Gear -> fc/2 */
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#define __CORE_SYS (__CORE_CLK / 2U)
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#elif ((SYSCR_Val & 7U) == 2U) /* Gear -> fc/4 */
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#define __CORE_SYS (__CORE_CLK / 4U )
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#elif ((SYSCR_Val & 7U) == 3U) /* Gear -> fc/8 */
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#define __CORE_SYS (__CORE_CLK / 8U)
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#elif ((SYSCR_Val & 7U) == 4U) /* Gear -> fc/16 */
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#define __CORE_SYS (__CORE_CLK / 16U)
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#else /* Gear -> reserved */
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#define __CORE_SYS (0U)
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#endif
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/* Clock Variable definitions */
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uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Update SystemCoreClock according register values.
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*/
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void SystemCoreClockUpdate(void)
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{ /* Get Core Clock Frequency */
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uint32_t CoreClock = 0U;
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uint32_t CoreClockInput = 0U;
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uint32_t regval = 0U;
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uint32_t oscsel = 0U;
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uint32_t pll0sel = 0U;
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uint32_t pll0on = 0U;
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/* Determine clock frequency according to clock register values */
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/* System clock is high-speed clock */
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regval = TSB_CG->OSCCR;
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oscsel = regval & CG_OSCCR_OSCSEL_SET;
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if (oscsel) { /* If system clock is External high-speed oscillator freq */
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CoreClock = EXTALH;
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} else { /* If system clock is Internal high-speed oscillator freq */
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CoreClock = IXTALH;
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}
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regval = TSB_CG->PLL0SEL;
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pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET;
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pll0on = regval & CG_PLL0SEL_PLL0ON_SET;
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if (pll0sel && pll0on) { /* If PLL enabled */
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if (CoreClock == EOSC_6M) { /* If input is 6MHz */
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if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_6_664_FPLL) {
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CoreClockInput = EOSC_6M_PLLON; /* output clock is 39.98MHz */
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} else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else if (CoreClock == EOSC_8M) { /* If input is 8MHz */
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if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_5_FPLL) {
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CoreClockInput = EOSC_8M_PLLON; /* output clock is 40MHz */
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} else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else if (CoreClock == EOSC_10M) { /* If input is 10MHz */
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if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) {
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CoreClockInput = EOSC_10M_PLLON; /* output clock is 40MHz */
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} else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else if (CoreClock == EOSC_12M) { /* If input is 12MHz */
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if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL) {
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CoreClockInput = EOSC_12M_PLLON; /* output clock is 39.94MHz */
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} else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else if (CoreClock == IOSC_10M) { /* If input is 10MHz */
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if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) {
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CoreClockInput = IOSC_10M_PLLON; /* output clock is 40MHz */
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} else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else {
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CoreClockInput = 0U;
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}
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} else { /* If PLL not used */
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CoreClockInput = CoreClock;
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}
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switch (TSB_CG->SYSCR & 7U) {
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case 0U: /* Gear -> fc */
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SystemCoreClock = CoreClockInput;
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break;
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case 1U: /* Gear -> fc/2 */
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SystemCoreClock = CoreClockInput / 2U;
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break;
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case 2U: /* Gear -> fc/4 */
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SystemCoreClock = CoreClockInput / 4U;
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break;
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case 3U: /* Gear -> fc/8 */
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if (CoreClockInput >= EOSC_8M) {
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SystemCoreClock = CoreClockInput / 8U;
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} else {
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SystemCoreClock = 0U;
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}
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break;
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case 4U: /* Gear -> fc/16 */
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if (CoreClockInput > EOSC_12M) {
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SystemCoreClock = CoreClockInput / 16U;
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} else {
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SystemCoreClock = 0U;
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}
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break;
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case 5U:
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case 6U:
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case 7U:
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SystemCoreClock = 0U;
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break;
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default:
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SystemCoreClock = 0U;
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break;
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}
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}
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System.
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*/
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void SystemInit(void)
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{
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#if (SIWD_SETUP) /* Watchdog Setup */
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/* SIWD Disable */
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TSB_SIWD0->EN = SIWDEN_Val;
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TSB_SIWD0->CR = SIWDCR_Val;
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#else
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/* SIWD Enable (Setting after a Reset) */
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#endif
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#if (CLOCK_SETUP) /* Clock(external) Setup */
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TSB_CG->SYSCR = SYSCR_Val;
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TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET);
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TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET;
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TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
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while (TSB_CG_WUPHCR_WUEF) {
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;
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} /* Warm-up */
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TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
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while (!TSB_CG_OSCCR_OSCF) {
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;
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} /* Confirm CGOSCCR<OSCF>="1" */
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TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ;
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#else
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/* Internal HOSC Enable (Setting after a Reset) */
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#endif
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TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET);
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TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */
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TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR;
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TSB_CG->PLL0SEL = PLL0SEL_Ready;
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TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
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while (TSB_CG_WUPHCR_WUEF) {
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;
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} /* Warm-up */
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TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET);
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TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */
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TSB_CG->STBYCR = STBYCR_Val;
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TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
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while (TSB_CG_WUPHCR_WUEF) {
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;
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} /* Lockup */
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TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET;
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while (!TSB_CG_PLL0SEL_PLL0ST) {
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;
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} /*Confirm CGPLL0SEL<PLL0ST> = "1" */
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}
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