mirror of https://github.com/ARMmbed/mbed-os.git
107 lines
3.2 KiB
C
107 lines
3.2 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2015 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _FCACHE_DRV_H
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#define _FCACHE_DRV_H
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#ifdef __cplusplus
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extern "C" {
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#else
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#include <stdio.h>
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#endif
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/* Flash Cache Address Map */
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#define SYS_FCACHE_BASE 0x40003000
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/* Configuration and Control Register */
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#define SYS_FCACHE_CCR (SYS_FCACHE_BASE)
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/* Status Register */
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#define SYS_FCACHE_SR (SYS_FCACHE_BASE + 0x4)
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/* Interrupt Req Status Register */
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#define SYS_FCACHE_IRQSTAT (SYS_FCACHE_BASE + 0x8)
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/* Cache Statistic Hit Register */
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#define SYS_FCACHE_CSHR (SYS_FCACHE_BASE + 0x14)
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/* Cache Statistic Miss Register */
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#define SYS_FCACHE_CSMR (SYS_FCACHE_BASE + 0x18)
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/* SYS_FCACHE_CCR (RW): Configuration and Control Register */
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#define FCACHE_EN 1 /* FCache Enable */
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#define FCACHE_INV_REQ (1 << 1) /* Manual Invalidate Request */
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#define FCACHE_POW_REQ (1 << 2) /* Manual SRAM Power Request */
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#define FCACHE_SET_MAN_POW (1 << 3) /* Power Control Setting */
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#define FCACHE_SET_MAN_INV (1 << 4) /* Invalidate Control Setting */
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#define FCACHE_SET_PREFETCH (1 << 5) /* Cache Prefetch Setting */
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#define FCACHE_STATISTIC_EN (1 << 6) /* Enable Statistics Logic */
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/* SYS_FCACHE_SR (RO): Status Register */
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#define FCACHE_CS 0x3 /* Cache Status Mask */
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#define FCACHE_CS_DISABLED 0x0
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#define FCACHE_CS_ENABLING 0x1
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#define FCACHE_CS_ENABLED 0x2
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#define FCACHE_CS_DISABLING 0x3
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#define FCACHE_INV_STAT 0x4 /* Invalidating Status */
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#define FCACHE_POW_STAT 0x10 /* SRAM Power Ack */
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/* SYS_FCACHE_IRQSTAT (RW): Interrupt Req Status Register */
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#define FCACHE_POW_ERR 1 /* SRAM Power Error */
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#define FCACHE_MAN_INV_ERR (1 << 1) /* Manual Invalidation error status */
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/* Macros */
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#define FCache_Readl(reg) *(volatile unsigned int *)reg
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#define FCache_Writel(reg, val) *(volatile unsigned int *)reg = val;
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/* Functions */
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/*
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* FCache_DriverInitialize: flash cache driver initialize funtion
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*/
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void FCache_DriverInitialize(void);
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/*
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* FCache_Enable: Enables the flash cache mode
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* mode: supported modes:
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* 0 - auto-power auto-invalidate
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* 1 - manual-power, manual-invalidate
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*/
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void FCache_Enable(int mode);
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/*
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* FCache_Disable: Disables the flash cache mode previously enabled
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*/
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void FCache_Disable(void);
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/*
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* FCache_Invalidate: to be invalidated the cache needs to be disabled.
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* return -1: flash cannot be disabled
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* -2: flash cannot be enabled
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*/
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int FCache_Invalidate(void);
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/*
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* FCache_GetStats: provides cache stats
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*/
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unsigned int * FCache_GetStats(void);
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/*
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* FCache_isEnabled: returns 1 if FCache is enabled
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*/
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unsigned int FCache_isEnabled(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _FCACHE_DRV_H */
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