mirror of https://github.com/ARMmbed/mbed-os.git
95 lines
5.2 KiB
C
95 lines
5.2 KiB
C
/**
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******************************************************************************
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* @file dma_map.h
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* @brief DMA hw module register map
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* @internal
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* @author ON Semiconductor
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* $Rev: 3415 $
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* $Date: 2015-06-05 13:29:52 +0530 (Fri, 05 Jun 2015) $
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******************************************************************************
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* Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
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* All rights reserved. This software and/or documentation is licensed by ON Semiconductor
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* under limited terms and conditions. The terms and conditions pertaining to the software
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* and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
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* (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
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* if applicable the software license agreement. Do not use this software and/or
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* documentation unless you have carefully read and you agree to the limited terms and
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* conditions. By using this software and/or documentation, you agree to the limited
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* terms and conditions.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
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* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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* @endinternal
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*
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* @ingroup dma
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*
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* @details
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*/
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#ifndef DMA_MAP_H_
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#define DMA_MAP_H_
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/*************************************************************************************************
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* *
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* Header files *
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* *
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*************************************************************************************************/
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#include "architecture.h"
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/**************************************************************************************************
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* *
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* Type definitions *
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* *
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**************************************************************************************************/
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/** DMA control HW registers structure overlay */
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typedef struct {
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union {
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struct {
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__IO uint32_t ENABLE:1; /**< DMA enable: 1 to enable; 0 to disable */
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__IO uint32_t MODE :2; /**< DMA mode: 00 – Memory to memory; 01 – Memory to peripheral; 10 – Peripheral to memory; 11 – Peripheral to peripheral */
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} BITS;
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__IO uint32_t WORD;
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} CONTROL; /**< Control register */
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__IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
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__IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
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__IO uint32_t SIZE; /**< Lenght of the entire transfer */
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union {
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struct {
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__I uint32_t COMPLETED:1; /**< Done: 0 – Not complete, 1 – Complete */
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__I uint32_t SOURCE_ERROR:1; /**< Source Error: 0 – No Error, 1 – Error */
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__I uint32_t DESTINATION_ERROR:1; /**< Destination Error: 0 – No Error, 1 – Source Error */
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} BITS;
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__I uint32_t WORD;
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} STATUS; /**< Status register */
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union {
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struct {
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__IO uint32_t COMPLETED:1; /**< A write of ‘1’ enables the interrupt generated by a DMA transfer complete */
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__IO uint32_t SOURCE_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the source side of the DMA transfer */
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__IO uint32_t DESTINATION_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the destination side of the DMA transfer */
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} BITS;
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__IO uint32_t WORD;
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} INT_ENABLE; /**< Interrupt enable */
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union {
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struct {
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__IO uint32_t COMPLETED:1; /**< A write clears the interrupt generated by a DMA transfer complete */
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__IO uint32_t SOURCE_ERROR:1; /**< A write clears the interrupt generated by an error on the source side of the DMA transfer */
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__IO uint32_t DESTINATION_ERROR:1; /**< A write clears the interrupt generated by an error on the destination side of the DMA transfer */
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} BITS;
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__IO uint32_t WORD;
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} INT_CLEAR; /**< Interrupt clear */
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union {
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struct {
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__I uint32_t COMPLETED:1; /**< Transfer complete interrupt */
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__I uint32_t SOURCE_ERROR:1; /**< Source error interrupt */
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__I uint32_t DESTINATION_ERROR:1; /**< Destination error interrupt */
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} BITS;
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__I uint32_t WORD;
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} INT_STATUS; /**< Interrupt status */
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} DmaReg_t, *DmaReg_pt;
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#endif /* DMA_MAP_H_ */
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