mirror of https://github.com/ARMmbed/mbed-os.git
142 lines
4.4 KiB
C
142 lines
4.4 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <stddef.h>
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#include "cmsis.h"
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#include "gpio_irq_api.h"
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#include "mbed_error.h"
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#define CHANNEL_NUM 8
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#define LPC_GPIO_X LPC_GPIO_PIN_INT
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#define PININT_IRQ 0
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static uint32_t channel_ids[CHANNEL_NUM] = {0};
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static gpio_irq_handler irq_handler;
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static inline void handle_interrupt_in(uint32_t channel) {
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uint32_t ch_bit = (1 << channel);
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// Return immediately if:
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// * The interrupt was already served
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// * There is no user handler
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// * It is a level interrupt, not an edge interrupt
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if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
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(channel_ids[channel] == 0 ) ||
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(LPC_GPIO_X->ISEL & ch_bit ) ) return;
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if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
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irq_handler(channel_ids[channel], IRQ_RISE);
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LPC_GPIO_X->RISE = ch_bit;
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}
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if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
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irq_handler(channel_ids[channel], IRQ_FALL);
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}
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LPC_GPIO_X->IST = ch_bit;
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}
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void gpio_irq0(void) {handle_interrupt_in(0);}
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void gpio_irq1(void) {handle_interrupt_in(1);}
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void gpio_irq2(void) {handle_interrupt_in(2);}
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void gpio_irq3(void) {handle_interrupt_in(3);}
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void gpio_irq4(void) {handle_interrupt_in(4);}
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void gpio_irq5(void) {handle_interrupt_in(5);}
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void gpio_irq6(void) {handle_interrupt_in(6);}
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void gpio_irq7(void) {handle_interrupt_in(7);}
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int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
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if (pin == NC) return -1;
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irq_handler = handler;
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int found_free_channel = 0;
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int i = 0;
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for (i=0; i<CHANNEL_NUM; i++) {
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if (channel_ids[i] == 0) {
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channel_ids[i] = id;
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obj->ch = i;
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found_free_channel = 1;
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break;
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}
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}
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if (!found_free_channel) return -1;
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/* Enable AHB clock to the GPIO domain. */
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LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
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/* Enable AHB clock to the FlexInt, GroupedInt domain. */
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LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24));
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/* To select a pin for any of the eight pin interrupts, write the pin number
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* as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
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* @see: mbed_capi/PinNames.h
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*/
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LPC_SYSCON->PINTSEL[obj->ch] = (pin >> 5) ? (pin - 8) : (pin);
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// Interrupt Wake-Up Enable
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LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
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void (*channels_irq)(void) = NULL;
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switch (obj->ch) {
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case 0: channels_irq = &gpio_irq0; break;
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case 1: channels_irq = &gpio_irq1; break;
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case 2: channels_irq = &gpio_irq2; break;
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case 3: channels_irq = &gpio_irq3; break;
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case 4: channels_irq = &gpio_irq4; break;
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case 5: channels_irq = &gpio_irq5; break;
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case 6: channels_irq = &gpio_irq6; break;
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case 7: channels_irq = &gpio_irq7; break;
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}
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NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
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NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
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return 0;
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}
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void gpio_irq_free(gpio_irq_t *obj) {
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channel_ids[obj->ch] = 0;
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LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
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}
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void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
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unsigned int ch_bit = (1 << obj->ch);
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// Clear interrupt
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if (!(LPC_GPIO_X->ISEL & ch_bit))
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LPC_GPIO_X->IST = ch_bit;
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// Edge trigger
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LPC_GPIO_X->ISEL &= ~ch_bit;
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if (event == IRQ_RISE) {
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if (enable) {
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LPC_GPIO_X->IENR |= ch_bit;
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} else {
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LPC_GPIO_X->IENR &= ~ch_bit;
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}
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} else {
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if (enable) {
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LPC_GPIO_X->IENF |= ch_bit;
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} else {
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LPC_GPIO_X->IENF &= ~ch_bit;
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}
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}
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}
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void gpio_irq_enable(gpio_irq_t *obj) {
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NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
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}
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void gpio_irq_disable(gpio_irq_t *obj) {
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NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
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}
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