mirror of https://github.com/ARMmbed/mbed-os.git
173 lines
5.6 KiB
C
173 lines
5.6 KiB
C
/*
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* Copyright (c) 2014-2015 ARM Limited. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef AT86RFREG_H_
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#define AT86RFREG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*AT86RF212 PHY Modes*/
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#define BPSK_20 0x00
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#define BPSK_40 0x04
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#define BPSK_40_ALT 0x14
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#define OQPSK_SIN_RC_100 0x08
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#define OQPSK_SIN_RC_200 0x09
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#define OQPSK_RC_100 0x18
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#define OQPSK_RC_200 0x19
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#define OQPSK_SIN_250 0x0c
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#define OQPSK_SIN_500 0x0d
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#define OQPSK_SIN_500_ALT 0x0f
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#define OQPSK_RC_250 0x1c
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#define OQPSK_RC_500 0x1d
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#define OQPSK_RC_500_ALT 0x1f
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#define OQPSK_SIN_RC_400_SCR_ON 0x2A
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#define OQPSK_SIN_RC_400_SCR_OFF 0x0A
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#define OQPSK_RC_400_SCR_ON 0x3A
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#define OQPSK_RC_400_SCR_OFF 0x1A
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#define OQPSK_SIN_1000_SCR_ON 0x2E
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#define OQPSK_SIN_1000_SCR_OFF 0x0E
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#define OQPSK_RC_1000_SCR_ON 0x3E
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#define OQPSK_RC_1000_SCR_OFF 0x1E
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/*Supported transceivers*/
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#define PART_AT86RF231 0x03
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#define PART_AT86RF212 0x07
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#define PART_AT86RF233 0x0B
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#define VERSION_AT86RF212 0x01
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#define VERSION_AT86RF212B 0x03
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/*RF Configuration Registers*/
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#define TRX_STATUS 0x01
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#define TRX_STATE 0x02
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#define TRX_CTRL_0 0x03
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#define TRX_CTRL_1 0x04
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#define PHY_TX_PWR 0x05
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#define PHY_RSSI 0x06
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#define PHY_ED_LEVEL 0x07
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#define PHY_CC_CCA 0x08
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#define RX_CTRL 0x0A
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#define SFD_VALUE 0x0B
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#define TRX_CTRL_2 0x0C
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#define ANT_DIV 0x0D
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#define IRQ_MASK 0x0E
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#define IRQ_STATUS 0x0F
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#define VREG_CTRL 0x10
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#define BATMON 0x11
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#define XOSC_CTRL 0x12
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#define CC_CTRL_0 0x13
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#define CC_CTRL_1 0x14
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#define RX_SYN 0x15
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#define TRX_RPC 0x16
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#define RF_CTRL_0 0x16
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#define XAH_CTRL_1 0x17
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#define FTN_CTRL 0x18
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#define PLL_CF 0x1A
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#define PLL_DCU 0x1B
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#define PART_NUM 0x1C
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#define VERSION_NUM 0x1D
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#define MAN_ID_0 0x1E
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#define MAN_ID_1 0x1F
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#define SHORT_ADDR_0 0x20
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#define SHORT_ADDR_1 0x21
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#define PAN_ID_0 0x22
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#define PAN_ID_1 0x23
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#define IEEE_ADDR_0 0x24
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#define IEEE_ADDR_1 0x25
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#define IEEE_ADDR_2 0x26
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#define IEEE_ADDR_3 0x27
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#define IEEE_ADDR_4 0x28
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#define IEEE_ADDR_5 0x29
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#define IEEE_ADDR_6 0x2A
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#define IEEE_ADDR_7 0x2B
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#define XAH_CTRL_0 0x2C
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#define CSMA_SEED_0 0x2D
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#define CSMA_SEED_1 0x2E
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#define CSMA_BE 0x2F
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/* CSMA_SEED_1*/
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#define AACK_FVN_MODE1 7
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#define AACK_FVN_MODE0 6
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#define AACK_SET_PD 5
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#define AACK_DIS_ACK 4
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#define AACK_I_AM_COORD 3
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#define CSMA_SEED_12 2
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#define CSMA_SEED_11 1
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#define CSMA_SEED_10 0
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/*TRX_STATUS bits*/
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#define CCA_STATUS 0x40
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#define CCA_DONE 0x80
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/*PHY_CC_CCA bits*/
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#define CCA_REQUEST 0x80
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#define CCA_MODE_3A 0x00
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#define CCA_MODE_1 0x20
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#define CCA_MODE_2 0x40
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#define CCA_MODE_3B 0x60
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#define CCA_MODE_MASK 0x60
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#define CCA_CHANNEL_MASK 0x1F
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/*IRQ_MASK bits*/
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#define RX_START 0x04
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#define TRX_END 0x08
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#define CCA_ED_DONE 0x10
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#define AMI 0x20
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#define TRX_UR 0x40
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/*ANT_DIV bits*/
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#define ANT_DIV_EN 0x08
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#define ANT_EXT_SW_EN 0x04
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#define ANT_CTRL_DEFAULT 0x03
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/*TRX_CTRL_1 bits*/
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#define PA_EXT_EN 0x80
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#define TX_AUTO_CRC_ON 0x20
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#define SPI_CMD_MODE_TRX_STATUS 0x04
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#define SPI_CMD_MODE_PHY_RSSI 0x08
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#define SPI_CMD_MODE_IRQ_STATUS 0x0C
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/*TRX_CTRL_2 bits*/
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#define RX_SAFE_MODE 0x80
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/*FTN_CTRL bits*/
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#define FTN_START 0x80
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/*PHY_RSSI bits*/
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#define CRC_VALID 0x80
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/*RX_SYN bits*/
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#define RX_PDT_DIS 0x80
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/*TRX_RPC bits */
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#define RX_RPC_CTRL 0xC0
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#define RX_RPC_EN 0x20
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#define PDT_RPC_EN 0x10
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#define PLL_RPC_EN 0x08
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#define XAH_TX_RPC_EN 0x04
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#define IPAN_RPC_EN 0x02
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#define TRX_RPC_RSVD_1 0x01
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/*XAH_CTRL_1 bits*/
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#define AACK_PROM_MODE 0x02
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#ifdef __cplusplus
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}
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#endif
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#endif /* AT86RFREG_H_ */
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