mirror of https://github.com/ARMmbed/mbed-os.git
176 lines
6.8 KiB
C
176 lines
6.8 KiB
C
/****************************************************************************
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*
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* Copyright 2020 Samsung Electronics All Rights Reserved.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing,
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* software distributed under the License is distributed on an
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* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied. See the License for the specific
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* language governing permissions and limitations under the License.
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*
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****************************************************************************/
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/*
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* I2C interface Support
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* =====================
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*/
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#ifndef MBED_I2C_DEF_H
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#define MBED_I2C_DEF_H
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#include <stdint.h> /* standard types definitions */
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typedef struct beetle_i2c {
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__IO uint32_t CONTROL; /* RW Control register */
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__I uint32_t STATUS; /* RO Status register */
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__IO uint32_t ADDRESS; /* RW I2C address register */
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__IO uint32_t DATA; /* RW I2C data register */
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__IO uint32_t IRQ_STATUS; /* RO Interrupt status register ( read only but write to clear bits) */
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__IO uint32_t TRANSFER_SIZE; /* RW Transfer size register */
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__IO uint32_t SLAVE_MONITOR; /* RW Slave monitor pause register */
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__IO uint32_t TIMEOUT; /* RW Time out register */
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__I uint32_t IRQ_MASK; /* RO Interrupt mask register */
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__O uint32_t IRQ_ENABLE; /* WO Interrupt enable register */
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__O uint32_t IRQ_DISABLE; /* WO Interrupt disable register */
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} I2C_TypeDef;
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// revise me
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#define I2C0_BASE (0x83017000) /* Shield Header I2C Base Address */
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#define I2C1_BASE (0x4000E000ul) /* Onboard I2C Base Address */
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#define SHIELD_I2C ((I2C_TypeDef *) I2C0_BASE )
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#define BOARD_I2C ((I2C_TypeDef *) I2C1_BASE )
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/* Control Register Masks */
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#define I2C_CTRL_RW 0x0001 /* Transfer direction */
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#define I2C_CTRL_MS 0x0002 /* Mode (master / slave) */
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#define I2C_CTRL_NEA 0x0004 /* Addressing mode */
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#define I2C_CTRL_ACKEN 0x0008 /* ACK enable */
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#define I2C_CTRL_HOLD 0x0010 /* Clock hold enable */
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#define I2C_SLVMON 0x0020 /* Slave monitor mode */
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#define I2C_CTRL_CLR_FIFO 0x0040 /* Force clear of FIFO */
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#define I2C_CTRL_DIVISOR_B 0x3F00 /* Stage B clock divider */
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#define I2C_CTRL_DIVISOR_A 0xA000 /* Stage A clock divider */
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#define I2C_CTRL_DIVISORS 0xFF00 /* Combined A and B fields */
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#define I2C_CTRL_DIVISOR_OFFSET 8 /* Offset of the clock divisor in
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* the CONTROL register
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*/
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#define I2C_CTRL_DIVISOR_A_BIT_MASK 0x03
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/*
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* First part of the clock
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* divisor in the CONTROL register
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*/
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#define I2C_CTRL_DIVISOR_B_BIT_MASK 0x3F
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/*
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* Second part of the clock
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* divisor in the CONTROL register
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*/
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/* Status Register Masks */
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#define I2C_STATUS_RXRW 0x0008 /* Mode of transmission from master */
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#define I2C_STATUS_RXDV 0x0020 /* Valid data waiting to be read */
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#define I2C_STATUS_TXDV 0x0040 /* Still a data byte to be sent */
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#define I2C_STATUS_RXOVF 0x0080 /* Receiver overflow */
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#define I2C_STATUS_BA 0x0100 /* Bus active */
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/* Address Register Masks */
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#define I2C_ADDRESS_7BIT 0x007F
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/* Interrupt Status / Enable / Disable Register Masks */
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#define I2C_IRQ_COMP 0x0001 /* Transfer complete */
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#define I2C_IRQ_DATA 0x0002 /* More data */
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#define I2C_IRQ_NACK 0x0004 /* Transfer not acknowledged */
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#define I2C_IRQ_TO 0x0008 /* Transfer timed out */
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#define I2C_IRQ_SLV_RDY 0x0010 /* Monitored slave ready */
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#define I2C_IRQ_RX_OVF 0x0020 /* Receive overflow */
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#define I2C_IRQ_TX_OVF 0x0040 /* Transmit overflow */
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#define I2C_IRQ_RX_UNF 0x0080 /* Receive underflow */
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#define I2C_IRQ_ARB_LOST 0x0200 /* Arbitration lost */
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/* Transfer Size Register Masks */
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#define I2C_TRANSFER_SIZE 0xFF
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/* Error codes */
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#define E_SUCCESS 0x0
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#define E_INCOMPLETE_DATA 0x1
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#define CTL 0x0000
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#define FIFO_CTL 0x0004
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#define TRAILING_CTL 0x0008
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#define INT_EN 0x0020
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#define INT_STAT 0x0024
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#define FIFO_STAT 0x0030
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#define TXDATA 0x0034
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#define RXDATA 0x0038
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#define I2C_CONF 0x0040
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#define I2C_AUTO_CONF 0x0044
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#define I2C_TIMEOUT 0x0048
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#define I2C_MANUAL_CMD 0x004C
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#define I2C_TRANS_STATUS 0x0050
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#define I2C_TIMING_HS1 0x0054
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#define I2C_TIMING_HS2 0x0058
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#define I2C_TIMING_HS3 0x005C
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#define I2C_TIMING_FS1 0x0060
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#define I2C_TIMING_FS2 0x0064
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#define I2C_TIMING_FS3 0x0068
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#define I2C_TIMING_SLA 0x006C
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#define I2C_ADDR 0x0070
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#define I2C_START (1 << 0)
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#define I2C_RESTART (1 << 1)
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#define I2C_STOP (1 << 2)
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#define I2C_SEND_DATA (1 << 3)
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#define I2C_READ_DATA (1 << 4)
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#define I2C_RX_ACK (1 << 5)
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#define I2C_TX_MASK (0xFF << 24)
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#define I2C_RX_MASK (0xFF << 16)
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#define I2C_SPEED_400KHZ 400000
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#define HSI2C_INT_SLAVE_ADDR_MATCH (1 << 15)
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#define HSI2C_INT_XFER_DONE_MANUAL (1 << 13)
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#define HSI2C_INT_XFER_DONE_NOACK_MANUAL (1 << 12)
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#define HSI2C_INT_NO_DEV_AUTO (1 << 10)
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#define HSI2C_INT_NO_DEV_ACK_AUTO (1 << 9)
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#define HSI2C_INT_TRANS_ABORT_AUTO (1 << 8)
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#define HSI2C_INT_TRANSFER_DONE_AUTO (1 << 7)
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#define HSI2C_INT_RX_OVERRUN (1 << 5)
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#define HSI2C_INT_TX_UNDERRUN (1 << 2)
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#define HSI2C_INT_RX_ALMOST_FULL (1 << 1)
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#define HSI2C_INT_TX_ALMOST_EMPTY (1 << 0)
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#define HSI2C_INT_ALL 0xFFFF
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#define I2C_M_READ 0x0001 /**< Read data, from slave to master */
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#define I2C_M_TEN 0x0002 /**< Ten bit address */
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#define I2C_M_NORESTART 0x0080 /**< Message should not begin with
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* (re-)start of transfer */
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#define I2C_SLAVE 0x0703 /**< Use this slave address */
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#define I2C_SLAVE_FORCE 0x0706 /**< Use this slave address, even if it
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* is already in use by a driver! */
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#define I2C_TENBIT 0x0704 /**< 0 for 7 bit addrs, != 0 for 10 bit */
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#define I2C_RDWR 0x0707 /**< Combined R/W transfer (one STOP only) */
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#define I2C_FREQUENCY 0X801
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#define I2C_M_IGNORE_NAK 0x1000 /**< if I2C_FUNC_PROTOCOL_MANGLING */
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#define I2C_M_NOSTART 0x4000 /**< if I2C_FUNC_NOSTART */
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#define I2C_MASTER 0
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#define I2C_SLAVE_MODE 1
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#define I2C_POLLING 0
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#define I2C_INTERRUPT 1
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#endif
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