mirror of https://github.com/ARMmbed/mbed-os.git
128 lines
4.3 KiB
C++
128 lines
4.3 KiB
C++
/*
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* Copyright (c) 2019, Arm Limited and affiliates.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef SPI_TESTER_H
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#define SPI_TESTER_H
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#include "MbedTester.h"
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class SPITester: public MbedTester {
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public:
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enum SpiMode {
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Mode0 = 0,
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Mode1 = 1,
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Mode2 = 2,
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Mode3 = 3
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};
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enum SpiBitOrder {
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MSBFirst = 0,
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LSBFirst = 1
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};
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enum SpiDuplex {
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FullDuplex = 0,
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HalfDuplex = 1
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};
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SPITester(const PinList *form_factor, const PinList *exclude_pins)
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: MbedTester(form_factor, exclude_pins)
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{
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}
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protected:
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/*
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* Read the number of transfers which have occurred
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*
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* return The number of SPI transfers that have completed since
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* spi was reset.
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*/
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uint16_t get_transfer_count(uint32_t addr_transfers, uint32_t size_transfers);
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/*
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* Read a checksum of data send to the tester
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*
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* param addr_checksum Address of the FPGA checksum reg.
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* param size_checksum Size of the FPGA checksum reg.
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*
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* return The sum of all bytes sent to the tester since reset.
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*/
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uint32_t get_receive_checksum(uint32_t addr_checksum, uint32_t size_checksum);
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/*
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* Set the clock mode of the spi_slave module.
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*
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* param mode Spi clock mode
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* param addr_spi_ctrl Address of the FPGA spi control reg.
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* param size_spi_ctrl Size of the FPGA FPGA spi control reg.
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* param offset_clk_mode Clock mode offset.
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* param size_clk_mode Clock mode size.
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*/
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void set_mode(SpiMode mode, uint32_t addr_spi_ctrl, uint32_t size_spi_ctrl, uint32_t offset_clk_mode, uint32_t size_clk_mode);
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/*
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* Set bit order durring transmission of the spi_slave module.
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*
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* param bit_order Spi clock mode
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* param addr_spi_ctrl Address of the FPGA spi control reg.
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* param size_spi_ctrl Size of the FPGA FPGA spi control reg.
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* param offset_bit_order Bit order offset.
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* param size_bit_order Bit order size.
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*/
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void set_bit_order(SpiBitOrder bit_order, uint32_t addr_spi_ctrl, uint32_t size_spi_ctrl, uint32_t offset_bit_order, uint32_t size_bit_order);
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/*
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* Set symbol size used durring transmission of the spi_slave module.
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*
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* param sym_size Spi symbol size
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* param addr_spi_ctrl Address of the FPGA spi control reg.
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* param size_spi_ctrl Size of the FPGA FPGA spi control reg.
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* param offset_sym_size Symbol size offset.
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* param size_sym_size Symbol size size.
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*/
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void set_sym_size(uint32_t sym_size, uint32_t addr_spi_ctrl, uint32_t size_spi_ctrl, uint32_t offset_sym_size, uint32_t size_sym_size);
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/*
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* Set full-duplex/half-duplex transmission mode of the spi_slave module.
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*
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* param duplex Duplex mode used for the transmission
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* param addr_spi_ctrl Address of the FPGA spi control reg.
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* param size_spi_ctrl Size of the FPGA FPGA spi control reg.
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* param offset_duplex Duplex mode offset.
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* param size_duplex Duplex mode size.
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*/
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void set_duplex_mode(SpiDuplex duplex, uint32_t addr_spi_ctrl, uint32_t size_spi_ctrl, uint32_t offset_duplex, uint32_t size_duplex);
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/*
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* Set tx/rx symbol count.
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*
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* tx_cnt TX symbol count
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* rx_cnt RX symbol count
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* param addr_hd_rx_cnt Address of the FPGA half duplex RX count reg.
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* param size_hd_rx_cnt Size of the FPGA half duplex RX count reg.
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* param addr_hd_tx_cnt Address of the FPGA half duplex TX count reg.
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* param size_hd_tx_cnt Size of the FPGA half duplex TX count reg.
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*
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* note Required only in Half-Duplex mode.
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*/
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void set_hd_tx_rx_cnt(uint16_t tx_cnt, uint16_t rx_cnt, uint32_t addr_hd_rx_cnt, uint32_t size_hd_rx_cnt, uint32_t addr_hd_tx_cnt, uint32_t size_hd_tx_cnt);
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};
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#endif
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