Jaeden Amero 75ad20b65f RTX5: uVisor: Switch threads very carefully ... uVisor doesn't set the PSP of the target thread. The RTOS sets the PSP of the target thread from the target thread's TCB. However, when interrupts of higher priority than PendSV happen between the call to uVisor to switch boxes, and the RTOS setting PSP, the uVisor vIRQ interrupt handler will attempt to use an invalid PSP (the PSP from before the box and thread switch). This leads to a crash. Make box and thread switching atomic by disabling interrupts immediately before the box switching until immediately after the new PSP is set.		2017-11-01 09:25:43 +00:00
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rtx4	CMSIS/RTX: Patch RTX4 to preserve osThreadDef compatibility	2017-11-01 09:25:42 +00:00
rtx5	RTX5: uVisor: Switch threads very carefully	2017-11-01 09:25:43 +00:00
mbed_boot.c	Update mbed OS to handle ARMC6 requirements	2017-09-11 13:20:32 -05:00
mbed_rtos1_types.h	Move Cortex specific RTX behind TARGET_CORTEX	2017-08-31 19:55:54 -05:00
mbed_rtos_storage.h	Remove use of internal RTX types	2017-09-04 11:26:38 -05:00
mbed_rtx_conf.h	Add error if OS tickrate is changed	2017-10-05 16:31:14 -05:00
mbed_rtx_handlers.c	Added thread terminate hook	2017-09-14 16:21:48 -05:00
mbed_rtx_idle.cpp	mbed_rtx_idle: uVisor: Don't attempt to sleep	2017-09-14 17:20:23 +01:00