mirror of https://github.com/ARMmbed/mbed-os.git
294 lines
10 KiB
C
294 lines
10 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2017, ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#if DEVICE_QSPI
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#include "qspi_api.h"
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#include "mbed_error.h"
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#include "cmsis.h"
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#include "pinmap.h"
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#include "PeripheralPins.h"
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/* Max amount of flash size is 4Gbytes */
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/* hence 2^(31+1), then FLASH_SIZE_DEFAULT = 1<<31 */
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#define QSPI_FLASH_SIZE_DEFAULT 0x80000000
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void qspi_prepare_command(const qspi_command_t *command, QSPI_CommandTypeDef *st_command)
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{
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// TODO: shift these around to get more dynamic mapping
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switch (command->instruction.bus_width) {
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case QSPI_CFG_BUS_SINGLE:
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st_command->InstructionMode = QSPI_INSTRUCTION_1_LINE;
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break;
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case QSPI_CFG_BUS_DUAL:
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st_command->InstructionMode = QSPI_INSTRUCTION_2_LINES;
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break;
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case QSPI_CFG_BUS_QUAD:
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st_command->InstructionMode = QSPI_INSTRUCTION_4_LINES;
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break;
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default:
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st_command->InstructionMode = QSPI_INSTRUCTION_NONE;
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break;
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}
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st_command->Instruction = command->instruction.value;
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st_command->DummyCycles = command->dummy_count,
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// these are target specific settings, use default values
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st_command->SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
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st_command->DdrMode = QSPI_DDR_MODE_DISABLE;
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st_command->DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
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switch (command->address.bus_width) {
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case QSPI_CFG_BUS_SINGLE:
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st_command->AddressMode = QSPI_ADDRESS_1_LINE;
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break;
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case QSPI_CFG_BUS_DUAL:
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st_command->AddressMode = QSPI_ADDRESS_2_LINES;
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break;
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case QSPI_CFG_BUS_QUAD:
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st_command->AddressMode = QSPI_ADDRESS_4_LINES;
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break;
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default:
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st_command->AddressMode = QSPI_ADDRESS_NONE;
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break;
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}
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if (command->address.disabled == true) {
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st_command->AddressMode = QSPI_ADDRESS_NONE;
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st_command->AddressSize = 0;
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} else {
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st_command->Address = command->address.value;
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/* command->address.size needs to be shifted by QUADSPI_CCR_ADSIZE_Pos */
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st_command->AddressSize = (command->address.size << QUADSPI_CCR_ADSIZE_Pos) & QUADSPI_CCR_ADSIZE_Msk;
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}
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switch (command->alt.bus_width) {
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case QSPI_CFG_BUS_SINGLE:
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st_command->AlternateByteMode = QSPI_ALTERNATE_BYTES_1_LINE;
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break;
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case QSPI_CFG_BUS_DUAL:
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st_command->AlternateByteMode = QSPI_ALTERNATE_BYTES_2_LINES;
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break;
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case QSPI_CFG_BUS_QUAD:
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st_command->AlternateByteMode = QSPI_ALTERNATE_BYTES_4_LINES;
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break;
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default:
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st_command->AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
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break;
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}
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if (command->alt.disabled == true) {
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st_command->AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
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st_command->AlternateBytesSize = 0;
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} else {
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st_command->AlternateBytes = command->alt.value;
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/* command->AlternateBytesSize needs to be shifted by QUADSPI_CCR_ABSIZE_Pos */
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st_command->AlternateBytesSize = (command->alt.size << QUADSPI_CCR_ABSIZE_Pos) & QUADSPI_CCR_ABSIZE_Msk;
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st_command->AlternateBytesSize = command->alt.size;
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}
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switch (command->data.bus_width) {
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case QSPI_CFG_BUS_SINGLE:
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st_command->DataMode = QSPI_DATA_1_LINE;
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break;
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case QSPI_CFG_BUS_DUAL:
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st_command->DataMode = QSPI_DATA_2_LINES;
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break;
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case QSPI_CFG_BUS_QUAD:
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st_command->DataMode = QSPI_DATA_4_LINES;
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break;
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default:
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st_command->DataMode = QSPI_DATA_NONE;
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break;
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}
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st_command->NbData = 0;
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}
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qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, uint32_t hz, uint8_t mode)
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{
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// Enable interface clock for QSPI
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__HAL_RCC_QSPI_CLK_ENABLE();
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// Reset QSPI
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__HAL_RCC_QSPI_FORCE_RESET();
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__HAL_RCC_QSPI_RELEASE_RESET();
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// Set default QSPI handle values
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obj->handle.Init.ClockPrescaler = 1;
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obj->handle.Init.FifoThreshold = 1;
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obj->handle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
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obj->handle.Init.FlashSize = POSITION_VAL(QSPI_FLASH_SIZE_DEFAULT) - 1;
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obj->handle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE;
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obj->handle.Init.ClockMode = QSPI_CLOCK_MODE_0;
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#ifdef QSPI_DUALFLASH_ENABLE
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obj->handle.Init.FlashID = QSPI_FLASH_ID_1;
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obj->handle.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
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#endif
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obj->handle.Init.ClockMode = mode == 0 ? QSPI_CLOCK_MODE_0 : QSPI_CLOCK_MODE_3;
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QSPIName qspiio0name = (QSPIName)pinmap_peripheral(io0, PinMap_QSPI_DATA);
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QSPIName qspiio1name = (QSPIName)pinmap_peripheral(io1, PinMap_QSPI_DATA);
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QSPIName qspiio2name = (QSPIName)pinmap_peripheral(io2, PinMap_QSPI_DATA);
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QSPIName qspiio3name = (QSPIName)pinmap_peripheral(io3, PinMap_QSPI_DATA);
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QSPIName qspiclkname = (QSPIName)pinmap_peripheral(sclk, PinMap_QSPI_SCLK);
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QSPIName qspisselname = (QSPIName)pinmap_peripheral(ssel, PinMap_QSPI_SSEL);
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QSPIName qspi_data_first = (QSPIName)pinmap_merge(qspiio0name, qspiio1name);
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QSPIName qspi_data_second = (QSPIName)pinmap_merge(qspiio2name, qspiio3name);
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QSPIName qspi_data_third = (QSPIName)pinmap_merge(qspiclkname, qspisselname);
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if (qspi_data_first != qspi_data_second || qspi_data_second != qspi_data_third ||
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qspi_data_first != qspi_data_third) {
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return QSPI_STATUS_INVALID_PARAMETER;
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}
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// tested all combinations, take first
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obj->handle.Instance = (QUADSPI_TypeDef *)qspi_data_first;
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// TODO pinmap here for pins (enable clock)
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pinmap_pinout(io0, PinMap_QSPI_DATA);
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pinmap_pinout(io1, PinMap_QSPI_DATA);
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pinmap_pinout(io2, PinMap_QSPI_DATA);
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pinmap_pinout(io3, PinMap_QSPI_DATA);
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pinmap_pinout(sclk, PinMap_QSPI_SCLK);
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pinmap_pinout(ssel, PinMap_QSPI_SSEL);
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if (HAL_QSPI_Init(&obj->handle) != HAL_OK) {
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return QSPI_STATUS_ERROR;
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}
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qspi_frequency(obj, hz);
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return QSPI_STATUS_OK;
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}
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qspi_status_t qspi_free(qspi_t *obj)
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{
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// TODO
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//return QSPI_STATUS_ERROR;
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return QSPI_STATUS_OK;
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}
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qspi_status_t qspi_frequency(qspi_t *obj, int hz)
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{
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qspi_status_t status = QSPI_STATUS_OK;
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// HCLK drives QSPI
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int div = HAL_RCC_GetHCLKFreq() / hz;
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if (div > 256 || div < 1) {
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status = QSPI_STATUS_INVALID_PARAMETER;
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return status;
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}
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obj->handle.Init.ClockPrescaler = div - 1;
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if (HAL_QSPI_Init(&obj->handle) != HAL_OK) {
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status = QSPI_STATUS_ERROR;
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}
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return status;
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}
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qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void *data, size_t *length)
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{
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QSPI_CommandTypeDef st_command;
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qspi_prepare_command(command, &st_command);
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st_command.NbData = *length;
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qspi_status_t status = QSPI_STATUS_OK;
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if (HAL_QSPI_Command(&obj->handle, &st_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
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status = QSPI_STATUS_ERROR;
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return status;
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}
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if (HAL_QSPI_Transmit(&obj->handle, (uint8_t *)data, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
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status = QSPI_STATUS_ERROR;
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}
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return status;
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}
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qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, size_t *length)
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{
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QSPI_CommandTypeDef st_command;
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qspi_prepare_command(command, &st_command);
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st_command.NbData = *length;
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qspi_status_t status = QSPI_STATUS_OK;
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if (HAL_QSPI_Command(&obj->handle, &st_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
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status = QSPI_STATUS_ERROR;
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return status;
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}
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if (HAL_QSPI_Receive(&obj->handle, data, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
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status = QSPI_STATUS_ERROR;
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}
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return status;
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}
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qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size)
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{
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qspi_status_t status = QSPI_STATUS_OK;
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if ((tx_data == NULL || tx_size == 0) && (rx_data == NULL || rx_size == 0)) {
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// only command, no rx or tx
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QSPI_CommandTypeDef st_command;
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qspi_prepare_command(command, &st_command);
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st_command.NbData = 1;
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st_command.DataMode = QSPI_DATA_NONE; /* Instruction only */
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if (HAL_QSPI_Command(&obj->handle, &st_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
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status = QSPI_STATUS_ERROR;
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return status;
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}
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} else {
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// often just read a register, check if we need to transmit anything prior reading
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if (tx_data != NULL && tx_size) {
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size_t tx_length = tx_size;
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status = qspi_write(obj, command, tx_data, &tx_length);
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if (status != QSPI_STATUS_OK) {
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return status;
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}
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}
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if (rx_data != NULL && rx_size) {
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size_t rx_length = rx_size;
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status = qspi_read(obj, command, rx_data, &rx_length);
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}
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}
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return status;
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}
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#endif
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/** @}*/
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