Przemyslaw Stekiel 87902a8e76 Add SCLK and SIN stats to SPIMasterTester. ... It has been found that there is a problem with the new K66F SPI driver when clock polarity is high. After setting clock polarity to high SCLK line is still low. When transmission starts and CS is asserted (in case of manual CS handling) SCLK signal is invalid (low). After first transfer SCLK idle state becomes high. SPI implementation on FPGA test shield is resistant on this bug and transmission is successful. The problem has been found on two boards communication test where transmission fails. The idea is to add support to the FPGA test shield to catch such errors and verify this in the test.		2019-05-27 09:48:33 +02:00
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COMPONENT_FPGA_CI_TEST_SHIELD	Add SCLK and SIN stats to SPIMasterTester.	2019-05-27 09:48:33 +02:00