mirror of https://github.com/ARMmbed/mbed-os.git
158 lines
7.0 KiB
C
158 lines
7.0 KiB
C
/***************************************************************************//**
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* @file sl_eth_hw.c
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*******************************************************************************
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* @section License
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* <b>(C) Copyright 2017 Silicon Labs, http://www.silabs.com</b>
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*******************************************************************************
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************/
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#include "sl_eth_hw.h"
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#include "device.h"
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#include "em_cmu.h"
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#include "em_gpio.h"
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#include "hal/gpio_api.h"
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#if defined(ETH_PRESENT)
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void sl_eth_hw_init(void)
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{
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/* Turn on clocks to ETH */
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CMU_ClockEnable(cmuClock_HFPER, true);
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CMU_ClockEnable(cmuClock_ETH, true);
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CMU_ClockEnable(cmuClock_GPIO, true);
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/* Drive RMII from the MCU-side 50MHz clock */
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GPIO_PinModeSet(AF_CMU_CLK2_PORT(MBED_CONF_SL_ETH_REFCLK_LOCATION),
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AF_CMU_CLK2_PIN(MBED_CONF_SL_ETH_REFCLK_LOCATION),
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gpioModePushPull, 0);
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CMU->CTRL |= CMU_CTRL_CLKOUTSEL2_HFXO;
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CMU->ROUTELOC0 = (CMU->ROUTELOC0 & ~_CMU_ROUTELOC0_CLKOUT2LOC_MASK) | (MBED_CONF_SL_ETH_REFCLK_LOCATION << _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT);
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CMU->ROUTEPEN |= CMU_ROUTEPEN_CLKOUT2PEN;
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ETH->CTRL = ETH_CTRL_GBLCLKEN | ETH_CTRL_MIISEL_RMII;
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/* Set pins to ETH for RMII config */
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GPIO_PinModeSet(AF_ETH_RMIICRSDV_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
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AF_ETH_RMIICRSDV_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
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gpioModeInput, 0); /* CRS_DV */
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GPIO_PinModeSet(AF_ETH_RMIITXD0_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
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AF_ETH_RMIITXD0_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
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gpioModePushPull, 0); /* TXD0 */
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GPIO_PinModeSet(AF_ETH_RMIITXD1_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
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AF_ETH_RMIITXD1_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
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gpioModePushPull, 0); /* TXD1 */
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GPIO_PinModeSet(AF_ETH_RMIITXEN_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
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AF_ETH_RMIITXEN_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
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gpioModePushPull, 0); /* TX_EN */
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GPIO_PinModeSet(AF_ETH_RMIIRXD0_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
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AF_ETH_RMIIRXD0_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
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gpioModeInput, 0); /* RXD0 */
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GPIO_PinModeSet(AF_ETH_RMIIRXD1_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
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AF_ETH_RMIIRXD1_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
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gpioModeInput, 0); /* RXD1 */
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GPIO_PinModeSet(AF_ETH_RMIIRXER_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
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AF_ETH_RMIIRXER_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
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gpioModeInput, 0); /* RX_ER */
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/* Setup route locations and enable pins */
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ETH->ROUTELOC1 = (MBED_CONF_SL_ETH_RMII_LOCATION << _ETH_ROUTELOC1_RMIILOC_SHIFT)
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| (MBED_CONF_SL_ETH_MDIO_LOCATION << _ETH_ROUTELOC1_MDIOLOC_SHIFT);
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ETH->ROUTEPEN = ETH_ROUTEPEN_RMIIPEN | ETH_ROUTEPEN_MDIOPEN;
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ETH->ROUTEPEN = ETH_ROUTEPEN_RMIIPEN | ETH_ROUTEPEN_MDIOPEN;
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/* Setup the MDIO pins */
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GPIO_PinModeSet(AF_ETH_MDIO_PORT(MBED_CONF_SL_ETH_MDIO_LOCATION),
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AF_ETH_MDIO_PIN(MBED_CONF_SL_ETH_MDIO_LOCATION),
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gpioModePushPull, 0); /* MDIO */
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GPIO_PinModeSet(AF_ETH_MDC_PORT(MBED_CONF_SL_ETH_MDIO_LOCATION),
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AF_ETH_MDC_PIN(MBED_CONF_SL_ETH_MDIO_LOCATION),
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gpioModePushPull, 0); /* MDC */
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/* Enable the PHY on the STK */
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#if defined(MBED_CONF_SL_ETH_PHY_POWER_PIN)
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gpio_t pwr_pin;
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gpio_init_out_ex(&pwr_pin, MBED_CONF_SL_ETH_PHY_POWER_PIN, 1);
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#endif
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#if defined(MBED_CONF_SL_ETH_PHY_ENABLE_PIN)
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gpio_t en_pin;
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gpio_init_out_ex(&en_pin, MBED_CONF_SL_ETH_PHY_ENABLE_PIN, 1);
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#endif
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}
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void sl_eth_hw_deinit(void)
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{
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/* Turn off PHY */
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#if defined(MBED_CONF_SL_ETH_PHY_POWER_PIN)
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gpio_t pwr_pin;
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gpio_init(&pwr_pin, MBED_CONF_SL_ETH_PHY_ENABLE_PIN);
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gpio_write(&pwr_pin, 0);
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gpio_mode(&pwr_pin, Disabled);
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#endif
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#if defined(MBED_CONF_SL_ETH_PHY_ENABLE_PIN)
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gpio_t en_pin;
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gpio_init(&en_pin, MBED_CONF_SL_ETH_PHY_POWER_PIN);
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gpio_write(&en_pin, 0);
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gpio_mode(&en_pin, Disabled);
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#endif
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/* Turn off MAC */
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ETH->ROUTEPEN = 0;
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ETH->CTRL = _ETH_CTRL_RESETVALUE;
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/* Turn off clock */
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CMU->CTRL &= ~CMU_CTRL_CLKOUTSEL2_HFXO;
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CMU->ROUTEPEN &= ~CMU_ROUTEPEN_CLKOUT2PEN;
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CMU_ClockEnable(cmuClock_ETH, false);
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/* Set used pins back to disabled */
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GPIO_PinModeSet(AF_ETH_MDIO_PORT(MBED_CONF_SL_ETH_MDIO_LOCATION),
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AF_ETH_MDIO_PIN(MBED_CONF_SL_ETH_MDIO_LOCATION),
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gpioModeDisabled, 0); /* MDIO */
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GPIO_PinModeSet(AF_ETH_MDC_PORT(MBED_CONF_SL_ETH_MDIO_LOCATION),
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AF_ETH_MDC_PIN(MBED_CONF_SL_ETH_MDIO_LOCATION),
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gpioModeDisabled, 0); /* MDC */
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GPIO_PinModeSet(AF_ETH_RMIICRSDV_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
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AF_ETH_RMIICRSDV_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
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gpioModeDisabled, 0); /* CRS_DV */
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GPIO_PinModeSet(AF_ETH_RMIITXD0_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
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AF_ETH_RMIITXD0_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
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gpioModeDisabled, 0); /* TXD0 */
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GPIO_PinModeSet(AF_ETH_RMIITXD1_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
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AF_ETH_RMIITXD1_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
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gpioModeDisabled, 0); /* TXD1 */
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GPIO_PinModeSet(AF_ETH_RMIITXEN_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
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AF_ETH_RMIITXEN_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
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gpioModeDisabled, 0); /* TX_EN */
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GPIO_PinModeSet(AF_ETH_RMIIRXD0_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
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AF_ETH_RMIIRXD0_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
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gpioModeDisabled, 0); /* RXD0 */
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GPIO_PinModeSet(AF_ETH_RMIIRXD1_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
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AF_ETH_RMIIRXD1_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
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gpioModeDisabled, 0); /* RXD1 */
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GPIO_PinModeSet(AF_ETH_RMIIRXER_PORT(MBED_CONF_SL_ETH_RMII_LOCATION),
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AF_ETH_RMIIRXER_PIN(MBED_CONF_SL_ETH_RMII_LOCATION),
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gpioModeDisabled, 0); /* RX_ER */
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GPIO_PinModeSet(AF_CMU_CLK2_PORT(MBED_CONF_SL_ETH_REFCLK_LOCATION),
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AF_CMU_CLK2_PIN(MBED_CONF_SL_ETH_REFCLK_LOCATION),
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gpioModeDisabled, 0); /* REF_CLK */
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}
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#endif //ETH_PRESENT
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