mirror of https://github.com/ARMmbed/mbed-os.git
283 lines
8.7 KiB
C
283 lines
8.7 KiB
C
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/** \addtogroup hal */
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/** @{*/
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/* mbed Microcontroller Library
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* Copyright (c) 2017 ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_QSPI_API_H
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#define MBED_QSPI_API_H
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#include "device.h"
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#include "pinmap.h"
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#include <stdbool.h>
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#if DEVICE_QSPI
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* \defgroup hal_qspi QSPI HAL
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* @{
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*/
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/** QSPI HAL object
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*/
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typedef struct qspi_s qspi_t;
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typedef struct {
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int peripheral;
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PinName data0_pin;
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int data0_function;
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PinName data1_pin;
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int data1_function;
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PinName data2_pin;
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int data2_function;
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PinName data3_pin;
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int data3_function;
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PinName sclk_pin;
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int sclk_function;
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PinName ssel_pin;
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int ssel_function;
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} qspi_pinmap_t;
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/** QSPI Bus width
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*
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* Some parts of commands provide variable bus width
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*/
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typedef enum qspi_bus_width {
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QSPI_CFG_BUS_SINGLE,
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QSPI_CFG_BUS_DUAL,
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QSPI_CFG_BUS_QUAD,
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} qspi_bus_width_t;
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/** Address size in bits
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*/
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typedef enum qspi_address_size {
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QSPI_CFG_ADDR_SIZE_8,
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QSPI_CFG_ADDR_SIZE_16,
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QSPI_CFG_ADDR_SIZE_24,
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QSPI_CFG_ADDR_SIZE_32,
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} qspi_address_size_t;
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/** Alternative size in bits
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*/
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typedef uint8_t qspi_alt_size_t;
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// The following defines are provided for backwards compatibilty. New code should explicitly
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// specify the required number of alt bits.
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#define QSPI_CFG_ALT_SIZE_8 8u
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#define QSPI_CFG_ALT_SIZE_16 16u
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#define QSPI_CFG_ALT_SIZE_24 24u
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#define QSPI_CFG_ALT_SIZE_32 32u
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/** QSPI command
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*
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* Defines a frame format. It consists of instruction, address, alternative, dummy count and data
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*/
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typedef struct qspi_command {
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struct {
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qspi_bus_width_t bus_width; /**< Bus width for the instruction >*/
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uint8_t value; /**< Instruction value >*/
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bool disabled; /**< Instruction phase skipped if disabled is set to true >*/
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} instruction;
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struct {
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qspi_bus_width_t bus_width; /**< Bus width for the address >*/
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qspi_address_size_t size; /**< Address size >*/
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uint32_t value; /**< Address value >*/
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bool disabled; /**< Address phase skipped if disabled is set to true >*/
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} address;
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struct {
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qspi_bus_width_t bus_width; /**< Bus width for alternative >*/
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qspi_alt_size_t size; /**< Alternative size >*/
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uint32_t value; /**< Alternative value >*/
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bool disabled; /**< Alternative phase skipped if disabled is set to true >*/
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} alt;
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uint8_t dummy_count; /**< Dummy cycles count >*/
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struct {
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qspi_bus_width_t bus_width; /**< Bus width for data >*/
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} data;
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} qspi_command_t;
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/** QSPI return status
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*/
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typedef enum qspi_status {
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QSPI_STATUS_ERROR = -1, /**< Generic error >*/
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QSPI_STATUS_INVALID_PARAMETER = -2, /**< The parameter is invalid >*/
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QSPI_STATUS_OK = 0, /**< Function executed sucessfully >*/
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} qspi_status_t;
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/** Initialize QSPI peripheral.
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*
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* It should initialize QSPI pins (io0-io3, sclk and ssel), set frequency, clock polarity and phase mode. The clock for the peripheral should be enabled
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*
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* @param obj QSPI object
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* @param io0 Data pin 0
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* @param io1 Data pin 1
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* @param io2 Data pin 2
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* @param io3 Data pin 3
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* @param sclk The clock pin
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* @param ssel The chip select pin
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* @param hz The bus frequency
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* @param mode Clock polarity and phase mode (0 - 3)
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* @return QSPI_STATUS_OK if initialisation successfully executed
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QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
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QSPI_STATUS_ERROR otherwise
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*/
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qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, uint32_t hz, uint8_t mode);
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/** Initialize QSPI peripheral.
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*
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* It should initialize QSPI pins (io0-io3, sclk and ssel), set frequency, clock polarity and phase mode. The clock for the peripheral should be enabled
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*
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* @param obj QSPI object
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* @param pinmap pointer to structure which holds static pinmap
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* @param hz The bus frequency
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* @param mode Clock polarity and phase mode (0 - 3)
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* @return QSPI_STATUS_OK if initialisation successfully executed
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QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
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QSPI_STATUS_ERROR otherwise
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*/
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qspi_status_t qspi_init_direct(qspi_t *obj, const qspi_pinmap_t *pinmap, uint32_t hz, uint8_t mode);
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/** Deinitilize QSPI peripheral
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*
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* It should release pins that are associated with the QSPI object, and disable clocks for QSPI peripheral module that was associated with the object
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*
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* @param obj QSPI object
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* @return QSPI_STATUS_OK if deinitialisation successfully executed
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QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
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QSPI_STATUS_ERROR otherwise
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*/
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qspi_status_t qspi_free(qspi_t *obj);
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/** Set the QSPI baud rate
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*
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* Actual frequency may differ from the desired frequency due to available dividers and the bus clock
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* Configures the QSPI peripheral's baud rate
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* @param obj The SPI object to configure
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* @param hz The baud rate in Hz
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* @return QSPI_STATUS_OK if frequency was set
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QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
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QSPI_STATUS_ERROR otherwise
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*/
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qspi_status_t qspi_frequency(qspi_t *obj, int hz);
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/** Send a command and block of data
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*
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* @param obj QSPI object
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* @param command QSPI command
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* @param data TX buffer
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* @param[in,out] length in - TX buffer length in bytes, out - number of bytes written
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* @return QSPI_STATUS_OK if the data has been succesfully sent
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QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
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QSPI_STATUS_ERROR otherwise
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*/
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qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void *data, size_t *length);
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/** Send a command (and optionally data) and get the response. Can be used to send/receive device specific commands
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*
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* @param obj QSPI object
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* @param command QSPI command
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* @param tx_data TX buffer
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* @param tx_size TX buffer length in bytes
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* @param rx_data RX buffer
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* @param rx_size RX buffer length in bytes
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* @return QSPI_STATUS_OK if the data has been succesfully sent
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QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
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QSPI_STATUS_ERROR otherwise
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*/
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qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size);
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/** Receive a command and block of data
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*
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* @param obj QSPI object
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* @param command QSPI command
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* @param data RX buffer
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* @param[in,out] length in - RX buffer length in bytes, out - number of bytes read
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* @return QSPI_STATUS_OK if data has been succesfully received
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QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
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QSPI_STATUS_ERROR otherwise
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*/
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qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, size_t *length);
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/** Get the pins that support QSPI SCLK
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*
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* Return a PinMap array of pins that support QSPI SCLK in
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* master mode. The array is terminated with {NC, NC, 0}.
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*
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* @return PinMap array
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*/
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const PinMap *qspi_master_sclk_pinmap(void);
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/** Get the pins that support QSPI SSEL
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*
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* Return a PinMap array of pins that support QSPI SSEL in
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* master mode. The array is terminated with {NC, NC, 0}.
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*
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* @return PinMap array
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*/
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const PinMap *qspi_master_ssel_pinmap(void);
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/** Get the pins that support QSPI DATA0
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*
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* Return a PinMap array of pins that support QSPI DATA0 in
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* master mode. The array is terminated with {NC, NC, 0}.
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*
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* @return PinMap array
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*/
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const PinMap *qspi_master_data0_pinmap(void);
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/** Get the pins that support QSPI DATA1
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*
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* Return a PinMap array of pins that support QSPI DATA1 in
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* master mode. The array is terminated with {NC, NC, 0}.
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*
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* @return PinMap array
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*/
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const PinMap *qspi_master_data1_pinmap(void);
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/** Get the pins that support QSPI DATA2
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*
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* Return a PinMap array of pins that support QSPI DATA2 in
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* master mode. The array is terminated with {NC, NC, 0}.
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*
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* @return PinMap array
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*/
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const PinMap *qspi_master_data2_pinmap(void);
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/** Get the pins that support QSPI DATA3
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*
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* Return a PinMap array of pins that support QSPI DATA3 in
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* master mode. The array is terminated with {NC, NC, 0}.
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*
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* @return PinMap array
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*/
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const PinMap *qspi_master_data3_pinmap(void);
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/**@}*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif
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/** @}*/
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